mbed-src - mbed w/ spi bug fig

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mbed w/ spi bug fig

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@20:4263a77256ae, 2013-09-10 (annotated)

Committer:: bogdanm
Date:: Tue Sep 10 15:14:19 2013 +0300
Revision:: 20:4263a77256ae

Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

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User	Revision	Line number	New contents of line
bogdanm	20:4263a77256ae	1	/*
bogdanm	20:4263a77256ae	2	* @brief LPC43xx/LPC18xx MCU header
bogdanm	20:4263a77256ae	3	*
bogdanm	20:4263a77256ae	4	* Copyright(C) NXP Semiconductors, 2012
bogdanm	20:4263a77256ae	5	* All rights reserved.
bogdanm	20:4263a77256ae	6	*
bogdanm	20:4263a77256ae	7	* Software that is described herein is for illustrative purposes only
bogdanm	20:4263a77256ae	8	* which provides customers with programming information regarding the
bogdanm	20:4263a77256ae	9	* LPC products. This software is supplied "AS IS" without any warranties of
bogdanm	20:4263a77256ae	10	* any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm	20:4263a77256ae	11	* all warranties, express or implied, including all implied warranties of
bogdanm	20:4263a77256ae	12	* merchantability, fitness for a particular purpose and non-infringement of
bogdanm	20:4263a77256ae	13	* intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm	20:4263a77256ae	14	* or liability for the use of the software, conveys no license or rights under any
bogdanm	20:4263a77256ae	15	* patent, copyright, mask work right, or any other intellectual property rights in
bogdanm	20:4263a77256ae	16	* or to any products. NXP Semiconductors reserves the right to make changes
bogdanm	20:4263a77256ae	17	* in the software without notification. NXP Semiconductors also makes no
bogdanm	20:4263a77256ae	18	* representation or warranty that such application will be suitable for the
bogdanm	20:4263a77256ae	19	* specified use without further testing or modification.
bogdanm	20:4263a77256ae	20	*
bogdanm	20:4263a77256ae	21	* Permission to use, copy, modify, and distribute this software and its
bogdanm	20:4263a77256ae	22	* documentation is hereby granted, under NXP Semiconductors' and its
bogdanm	20:4263a77256ae	23	* licensor's relevant copyrights in the software, without fee, provided that it
bogdanm	20:4263a77256ae	24	* is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm	20:4263a77256ae	25	* copyright, permission, and disclaimer notice must appear in all copies of
bogdanm	20:4263a77256ae	26	* this code.
bogdanm	20:4263a77256ae	27	*
bogdanm	20:4263a77256ae	28	* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
bogdanm	20:4263a77256ae	29	* 05/15/13 Micromint USA <support@micromint.com>
bogdanm	20:4263a77256ae	30	*/
bogdanm	20:4263a77256ae	31
bogdanm	20:4263a77256ae	32	#ifndef __LPC43XX_H
bogdanm	20:4263a77256ae	33	#define __LPC43XX_H
bogdanm	20:4263a77256ae	34
bogdanm	20:4263a77256ae	35	#ifdef __cplusplus
bogdanm	20:4263a77256ae	36	extern "C" {
bogdanm	20:4263a77256ae	37	#endif
bogdanm	20:4263a77256ae	38
bogdanm	20:4263a77256ae	39	/** @defgroup LPC43XX_H: LPC43xx include file
bogdanm	20:4263a77256ae	40	* @ingroup LPC43XX_Headers
bogdanm	20:4263a77256ae	41	* @{
bogdanm	20:4263a77256ae	42	*/
bogdanm	20:4263a77256ae	43
bogdanm	20:4263a77256ae	44	/* Treat __CORE_Mx as CORE_Mx for mbed builds */
bogdanm	20:4263a77256ae	45	#if defined(__CORTEX_M0) && !defined(CORE_M0)
bogdanm	20:4263a77256ae	46	#define CORE_M0
bogdanm	20:4263a77256ae	47	#endif
bogdanm	20:4263a77256ae	48	#if defined(__CORTEX_M3) && !defined(CORE_M3)
bogdanm	20:4263a77256ae	49	#define CORE_M3
bogdanm	20:4263a77256ae	50	#endif
bogdanm	20:4263a77256ae	51	/* Default to M4 core if no core explicitly declared */
bogdanm	20:4263a77256ae	52	#if !defined(CORE_M0) && !defined(CORE_M3)
bogdanm	20:4263a77256ae	53	#define CORE_M4
bogdanm	20:4263a77256ae	54	#endif
bogdanm	20:4263a77256ae	55
bogdanm	20:4263a77256ae	56	/* Start of section using anonymous unions */
bogdanm	20:4263a77256ae	57	#if defined(__ARMCC_VERSION)
bogdanm	20:4263a77256ae	58	// Kill warning "#pragma push with no matching #pragma pop"
bogdanm	20:4263a77256ae	59	#pragma diag_suppress 2525
bogdanm	20:4263a77256ae	60	#pragma push
bogdanm	20:4263a77256ae	61	#pragma anon_unions
bogdanm	20:4263a77256ae	62	#elif defined(__CWCC__)
bogdanm	20:4263a77256ae	63	#pragma push
bogdanm	20:4263a77256ae	64	#pragma cpp_extensions on
bogdanm	20:4263a77256ae	65	#elif defined(__IAR_SYSTEMS_ICC__)
bogdanm	20:4263a77256ae	66	//#pragma push // FIXME not usable for IAR
bogdanm	20:4263a77256ae	67	#pragma language=extended
bogdanm	20:4263a77256ae	68	#else /* defined(__GNUC__) and others */
bogdanm	20:4263a77256ae	69	/* Assume anonymous unions are enabled by default */
bogdanm	20:4263a77256ae	70	#endif
bogdanm	20:4263a77256ae	71
bogdanm	20:4263a77256ae	72	#if defined(CORE_M4)
bogdanm	20:4263a77256ae	73	/**
bogdanm	20:4263a77256ae	74	* @brief LPC43xx Cortex CMSIS definitions
bogdanm	20:4263a77256ae	75	*/
bogdanm	20:4263a77256ae	76
bogdanm	20:4263a77256ae	77	#define __CM4_REV 0x0000 /!< Cortex-M4 Core Revision /
bogdanm	20:4263a77256ae	78	#define __MPU_PRESENT 1 /!< MPU present or not /
bogdanm	20:4263a77256ae	79	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
bogdanm	20:4263a77256ae	80	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	20:4263a77256ae	81	#define __FPU_PRESENT 1 /!< FPU present or not /
bogdanm	20:4263a77256ae	82	#define CHIP_LPC43XX /!< LPCOPEN /
bogdanm	20:4263a77256ae	83
bogdanm	20:4263a77256ae	84	/**
bogdanm	20:4263a77256ae	85	* @brief LPC43xx peripheral interrupt numbers
bogdanm	20:4263a77256ae	86	*/
bogdanm	20:4263a77256ae	87
bogdanm	20:4263a77256ae	88	typedef enum {
bogdanm	20:4263a77256ae	89	/* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */
bogdanm	20:4263a77256ae	90	Reset_IRQn = -15,/!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	20:4263a77256ae	91	NonMaskableInt_IRQn = -14,/!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	20:4263a77256ae	92	HardFault_IRQn = -13,/!< 3 Hard Fault, all classes of Fault /
bogdanm	20:4263a77256ae	93	MemoryManagement_IRQn = -12,/!< 4 Memory Management, MPU mismatch, including Access Violation and No Match /
bogdanm	20:4263a77256ae	94	BusFault_IRQn = -11,/!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault /
bogdanm	20:4263a77256ae	95	UsageFault_IRQn = -10,/!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
bogdanm	20:4263a77256ae	96	SVCall_IRQn = -5,/!< 11 System Service Call via SVC instruction /
bogdanm	20:4263a77256ae	97	DebugMonitor_IRQn = -4,/!< 12 Debug Monitor /
bogdanm	20:4263a77256ae	98	PendSV_IRQn = -2,/!< 14 Pendable request for system service /
bogdanm	20:4263a77256ae	99	SysTick_IRQn = -1,/!< 15 System Tick Timer /
bogdanm	20:4263a77256ae	100
bogdanm	20:4263a77256ae	101	/* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
bogdanm	20:4263a77256ae	102	DAC_IRQn = 0,/!< 0 DAC /
bogdanm	20:4263a77256ae	103	M0CORE_IRQn = 1,/!< 1 M0a /
bogdanm	20:4263a77256ae	104	DMA_IRQn = 2,/!< 2 DMA /
bogdanm	20:4263a77256ae	105	RESERVED1_IRQn = 3,/!< 3 EZH/EDM /
bogdanm	20:4263a77256ae	106	RESERVED2_IRQn = 4,
bogdanm	20:4263a77256ae	107	ETHERNET_IRQn = 5,/!< 5 ETHERNET /
bogdanm	20:4263a77256ae	108	SDIO_IRQn = 6,/!< 6 SDIO /
bogdanm	20:4263a77256ae	109	LCD_IRQn = 7,/!< 7 LCD /
bogdanm	20:4263a77256ae	110	USB0_IRQn = 8,/!< 8 USB0 /
bogdanm	20:4263a77256ae	111	USB1_IRQn = 9,/!< 9 USB1 /
bogdanm	20:4263a77256ae	112	SCT_IRQn = 10,/!< 10 SCT /
bogdanm	20:4263a77256ae	113	RITIMER_IRQn = 11,/!< 11 RITIMER /
bogdanm	20:4263a77256ae	114	TIMER0_IRQn = 12,/!< 12 TIMER0 /
bogdanm	20:4263a77256ae	115	TIMER1_IRQn = 13,/!< 13 TIMER1 /
bogdanm	20:4263a77256ae	116	TIMER2_IRQn = 14,/!< 14 TIMER2 /
bogdanm	20:4263a77256ae	117	TIMER3_IRQn = 15,/!< 15 TIMER3 /
bogdanm	20:4263a77256ae	118	MCPWM_IRQn = 16,/!< 16 MCPWM /
bogdanm	20:4263a77256ae	119	ADC0_IRQn = 17,/!< 17 ADC0 /
bogdanm	20:4263a77256ae	120	I2C0_IRQn = 18,/!< 18 I2C0 /
bogdanm	20:4263a77256ae	121	I2C1_IRQn = 19,/!< 19 I2C1 /
bogdanm	20:4263a77256ae	122	SPI_INT_IRQn = 20,/!< 20 SPI_INT /
bogdanm	20:4263a77256ae	123	ADC1_IRQn = 21,/!< 21 ADC1 /
bogdanm	20:4263a77256ae	124	SSP0_IRQn = 22,/!< 22 SSP0 /
bogdanm	20:4263a77256ae	125	SSP1_IRQn = 23,/!< 23 SSP1 /
bogdanm	20:4263a77256ae	126	USART0_IRQn = 24,/!< 24 USART0 /
bogdanm	20:4263a77256ae	127	UART1_IRQn = 25,/!< 25 UART1 /
bogdanm	20:4263a77256ae	128	USART2_IRQn = 26,/!< 26 USART2 /
bogdanm	20:4263a77256ae	129	USART3_IRQn = 27,/!< 27 USART3 /
bogdanm	20:4263a77256ae	130	I2S0_IRQn = 28,/!< 28 I2S0 /
bogdanm	20:4263a77256ae	131	I2S1_IRQn = 29,/!< 29 I2S1 /
bogdanm	20:4263a77256ae	132	RESERVED4_IRQn = 30,
bogdanm	20:4263a77256ae	133	SGPIO_INT_IRQn = 31,/!< 31 SGPIO_IINT /
bogdanm	20:4263a77256ae	134	PIN_INT0_IRQn = 32,/!< 32 PIN_INT0 /
bogdanm	20:4263a77256ae	135	PIN_INT1_IRQn = 33,/!< 33 PIN_INT1 /
bogdanm	20:4263a77256ae	136	PIN_INT2_IRQn = 34,/!< 34 PIN_INT2 /
bogdanm	20:4263a77256ae	137	PIN_INT3_IRQn = 35,/!< 35 PIN_INT3 /
bogdanm	20:4263a77256ae	138	PIN_INT4_IRQn = 36,/!< 36 PIN_INT4 /
bogdanm	20:4263a77256ae	139	PIN_INT5_IRQn = 37,/!< 37 PIN_INT5 /
bogdanm	20:4263a77256ae	140	PIN_INT6_IRQn = 38,/!< 38 PIN_INT6 /
bogdanm	20:4263a77256ae	141	PIN_INT7_IRQn = 39,/!< 39 PIN_INT7 /
bogdanm	20:4263a77256ae	142	GINT0_IRQn = 40,/!< 40 GINT0 /
bogdanm	20:4263a77256ae	143	GINT1_IRQn = 41,/!< 41 GINT1 /
bogdanm	20:4263a77256ae	144	EVENTROUTER_IRQn = 42,/!< 42 EVENTROUTER /
bogdanm	20:4263a77256ae	145	C_CAN1_IRQn = 43,/!< 43 C_CAN1 /
bogdanm	20:4263a77256ae	146	RESERVED6_IRQn = 44,
bogdanm	20:4263a77256ae	147	RESERVED7_IRQn = 45,/!< 45 VADC /
bogdanm	20:4263a77256ae	148	ATIMER_IRQn = 46,/!< 46 ATIMER /
bogdanm	20:4263a77256ae	149	RTC_IRQn = 47,/!< 47 RTC /
bogdanm	20:4263a77256ae	150	RESERVED8_IRQn = 48,
bogdanm	20:4263a77256ae	151	WWDT_IRQn = 49,/!< 49 WWDT /
bogdanm	20:4263a77256ae	152	RESERVED9_IRQn = 50,
bogdanm	20:4263a77256ae	153	C_CAN0_IRQn = 51,/!< 51 C_CAN0 /
bogdanm	20:4263a77256ae	154	QEI_IRQn = 52,/!< 52 QEI /
bogdanm	20:4263a77256ae	155	} IRQn_Type;
bogdanm	20:4263a77256ae	156
bogdanm	20:4263a77256ae	157	#include "core_cm4.h" /!< Cortex-M4 processor and core peripherals /
bogdanm	20:4263a77256ae	158
bogdanm	20:4263a77256ae	159	#elif defined(CORE_M3)
bogdanm	20:4263a77256ae	160	/**
bogdanm	20:4263a77256ae	161	* @brief LPC18xx Cortex CMSIS definitions
bogdanm	20:4263a77256ae	162	*/
bogdanm	20:4263a77256ae	163	#define __MPU_PRESENT 1 /!< MPU present or not /
bogdanm	20:4263a77256ae	164	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
bogdanm	20:4263a77256ae	165	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	20:4263a77256ae	166	#define __FPU_PRESENT 0 /!< FPU present or not /
bogdanm	20:4263a77256ae	167	#define CHIP_LPC18XX /!< LPCOPEN /
bogdanm	20:4263a77256ae	168
bogdanm	20:4263a77256ae	169	/**
bogdanm	20:4263a77256ae	170	* @brief LPC18xx peripheral interrupt numbers
bogdanm	20:4263a77256ae	171	*/
bogdanm	20:4263a77256ae	172
bogdanm	20:4263a77256ae	173	typedef enum {
bogdanm	20:4263a77256ae	174	/* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
bogdanm	20:4263a77256ae	175	Reset_IRQn = -15,/!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	20:4263a77256ae	176	NonMaskableInt_IRQn = -14,/!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	20:4263a77256ae	177	HardFault_IRQn = -13,/!< 3 Hard Fault, all classes of Fault /
bogdanm	20:4263a77256ae	178	MemoryManagement_IRQn = -12,/!< 4 Memory Management, MPU mismatch, including Access Violation and No Match /
bogdanm	20:4263a77256ae	179	BusFault_IRQn = -11,/!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault /
bogdanm	20:4263a77256ae	180	UsageFault_IRQn = -10,/!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
bogdanm	20:4263a77256ae	181	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
bogdanm	20:4263a77256ae	182	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
bogdanm	20:4263a77256ae	183	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
bogdanm	20:4263a77256ae	184	SysTick_IRQn = -1, /!< 15 System Tick Timer /
bogdanm	20:4263a77256ae	185
bogdanm	20:4263a77256ae	186	/* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
bogdanm	20:4263a77256ae	187	DAC_IRQn = 0,/!< 0 DAC /
bogdanm	20:4263a77256ae	188	RESERVED0_IRQn = 1,
bogdanm	20:4263a77256ae	189	DMA_IRQn = 2,/!< 2 DMA /
bogdanm	20:4263a77256ae	190	RESERVED1_IRQn = 3,/!< 3 EZH/EDM /
bogdanm	20:4263a77256ae	191	RESERVED2_IRQn = 4,
bogdanm	20:4263a77256ae	192	ETHERNET_IRQn = 5,/!< 5 ETHERNET /
bogdanm	20:4263a77256ae	193	SDIO_IRQn = 6,/!< 6 SDIO /
bogdanm	20:4263a77256ae	194	LCD_IRQn = 7,/!< 7 LCD /
bogdanm	20:4263a77256ae	195	USB0_IRQn = 8,/!< 8 USB0 /
bogdanm	20:4263a77256ae	196	USB1_IRQn = 9,/!< 9 USB1 /
bogdanm	20:4263a77256ae	197	SCT_IRQn = 10,/!< 10 SCT /
bogdanm	20:4263a77256ae	198	RITIMER_IRQn = 11,/!< 11 RITIMER /
bogdanm	20:4263a77256ae	199	TIMER0_IRQn = 12,/!< 12 TIMER0 /
bogdanm	20:4263a77256ae	200	TIMER1_IRQn = 13,/!< 13 TIMER1 /
bogdanm	20:4263a77256ae	201	TIMER2_IRQn = 14,/!< 14 TIMER2 /
bogdanm	20:4263a77256ae	202	TIMER3_IRQn = 15,/!< 15 TIMER3 /
bogdanm	20:4263a77256ae	203	MCPWM_IRQn = 16,/!< 16 MCPWM /
bogdanm	20:4263a77256ae	204	ADC0_IRQn = 17,/!< 17 ADC0 /
bogdanm	20:4263a77256ae	205	I2C0_IRQn = 18,/!< 18 I2C0 /
bogdanm	20:4263a77256ae	206	I2C1_IRQn = 19,/!< 19 I2C1 /
bogdanm	20:4263a77256ae	207	RESERVED3_IRQn = 20,
bogdanm	20:4263a77256ae	208	ADC1_IRQn = 21,/!< 21 ADC1 /
bogdanm	20:4263a77256ae	209	SSP0_IRQn = 22,/!< 22 SSP0 /
bogdanm	20:4263a77256ae	210	SSP1_IRQn = 23,/!< 23 SSP1 /
bogdanm	20:4263a77256ae	211	USART0_IRQn = 24,/!< 24 USART0 /
bogdanm	20:4263a77256ae	212	UART1_IRQn = 25,/!< 25 UART1 /
bogdanm	20:4263a77256ae	213	USART2_IRQn = 26,/!< 26 USART2 /
bogdanm	20:4263a77256ae	214	USART3_IRQn = 27,/!< 27 USART3 /
bogdanm	20:4263a77256ae	215	I2S0_IRQn = 28,/!< 28 I2S0 /
bogdanm	20:4263a77256ae	216	I2S1_IRQn = 29,/!< 29 I2S1 /
bogdanm	20:4263a77256ae	217	RESERVED4_IRQn = 30,
bogdanm	20:4263a77256ae	218	RESERVED5_IRQn = 31,
bogdanm	20:4263a77256ae	219	PIN_INT0_IRQn = 32,/!< 32 PIN_INT0 /
bogdanm	20:4263a77256ae	220	PIN_INT1_IRQn = 33,/!< 33 PIN_INT1 /
bogdanm	20:4263a77256ae	221	PIN_INT2_IRQn = 34,/!< 34 PIN_INT2 /
bogdanm	20:4263a77256ae	222	PIN_INT3_IRQn = 35,/!< 35 PIN_INT3 /
bogdanm	20:4263a77256ae	223	PIN_INT4_IRQn = 36,/!< 36 PIN_INT4 /
bogdanm	20:4263a77256ae	224	PIN_INT5_IRQn = 37,/!< 37 PIN_INT5 /
bogdanm	20:4263a77256ae	225	PIN_INT6_IRQn = 38,/!< 38 PIN_INT6 /
bogdanm	20:4263a77256ae	226	PIN_INT7_IRQn = 39,/!< 39 PIN_INT7 /
bogdanm	20:4263a77256ae	227	GINT0_IRQn = 40,/!< 40 GINT0 /
bogdanm	20:4263a77256ae	228	GINT1_IRQn = 41,/!< 41 GINT1 /
bogdanm	20:4263a77256ae	229	EVENTROUTER_IRQn = 42,/!< 42 EVENTROUTER /
bogdanm	20:4263a77256ae	230	C_CAN1_IRQn = 43,/!< 43 C_CAN1 /
bogdanm	20:4263a77256ae	231	RESERVED6_IRQn = 44,
bogdanm	20:4263a77256ae	232	RESERVED7_IRQn = 45,/!< 45 VADC /
bogdanm	20:4263a77256ae	233	ATIMER_IRQn = 46,/!< 46 ATIMER /
bogdanm	20:4263a77256ae	234	RTC_IRQn = 47,/!< 47 RTC /
bogdanm	20:4263a77256ae	235	RESERVED8_IRQn = 48,
bogdanm	20:4263a77256ae	236	WWDT_IRQn = 49,/!< 49 WWDT /
bogdanm	20:4263a77256ae	237	RESERVED9_IRQn = 50,
bogdanm	20:4263a77256ae	238	C_CAN0_IRQn = 51,/!< 51 C_CAN0 /
bogdanm	20:4263a77256ae	239	QEI_IRQn = 52,/!< 52 QEI /
bogdanm	20:4263a77256ae	240	} IRQn_Type;
bogdanm	20:4263a77256ae	241
bogdanm	20:4263a77256ae	242	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
bogdanm	20:4263a77256ae	243
bogdanm	20:4263a77256ae	244	#elif defined(CORE_M0)
bogdanm	20:4263a77256ae	245	/**
bogdanm	20:4263a77256ae	246	* @brief LPC43xx (M0 Core) Cortex CMSIS definitions
bogdanm	20:4263a77256ae	247	*/
bogdanm	20:4263a77256ae	248
bogdanm	20:4263a77256ae	249	#define __MPU_PRESENT 0 /!< MPU present or not /
bogdanm	20:4263a77256ae	250	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
bogdanm	20:4263a77256ae	251	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	20:4263a77256ae	252	#define __FPU_PRESENT 0 /!< FPU present or not /
bogdanm	20:4263a77256ae	253	#define CHIP_LPC43XX /!< LPCOPEN /
bogdanm	20:4263a77256ae	254
bogdanm	20:4263a77256ae	255	/**
bogdanm	20:4263a77256ae	256	* @brief LPC43xx (M0 Core) peripheral interrupt numbers
bogdanm	20:4263a77256ae	257	*/
bogdanm	20:4263a77256ae	258
bogdanm	20:4263a77256ae	259	typedef enum {
bogdanm	20:4263a77256ae	260	/* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */
bogdanm	20:4263a77256ae	261	Reset_IRQn = -15,/!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	20:4263a77256ae	262	NonMaskableInt_IRQn = -14,/!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	20:4263a77256ae	263	HardFault_IRQn = -13,/!< 3 Hard Fault, all classes of Fault /
bogdanm	20:4263a77256ae	264	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
bogdanm	20:4263a77256ae	265	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
bogdanm	20:4263a77256ae	266	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
bogdanm	20:4263a77256ae	267	SysTick_IRQn = -1, /!< 15 System Tick Timer /
bogdanm	20:4263a77256ae	268
bogdanm	20:4263a77256ae	269	/* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
bogdanm	20:4263a77256ae	270	DAC_IRQn = 0,/!< 0 DAC /
bogdanm	20:4263a77256ae	271	M0_M4CORE_IRQn = 1,/!< 1 M0a /
bogdanm	20:4263a77256ae	272	DMA_IRQn = 2,/!< 2 DMA r /
bogdanm	20:4263a77256ae	273	RESERVED1_IRQn = 3,/!< 3 EZH/EDM /
bogdanm	20:4263a77256ae	274	FLASHEEPROM_IRQn = 4,/!< 4 ORed Flash EEPROM Bank A, B, EEPROM /
bogdanm	20:4263a77256ae	275	ETHERNET_IRQn = 5,/!< 5 ETHERNET /
bogdanm	20:4263a77256ae	276	SDIO_IRQn = 6,/!< 6 SDIO /
bogdanm	20:4263a77256ae	277	LCD_IRQn = 7,/!< 7 LCD /
bogdanm	20:4263a77256ae	278	USB0_IRQn = 8,/!< 8 USB0 /
bogdanm	20:4263a77256ae	279	USB1_IRQn = 9,/!< 9 USB1 /
bogdanm	20:4263a77256ae	280	SCT_IRQn = 10,/!< 10 SCT /
bogdanm	20:4263a77256ae	281	RITIMER_IRQn = 11,/!< 11 ORed RITIMER, WDT /
bogdanm	20:4263a77256ae	282	TIMER0_IRQn = 12,/!< 12 TIMER0 /
bogdanm	20:4263a77256ae	283	GINT1_IRQn = 13,/!< 13 GINT1 /
bogdanm	20:4263a77256ae	284	PIN_INT4_IRQn = 14,/!< 14 GPIO 4 /
bogdanm	20:4263a77256ae	285	TIMER3_IRQn = 15,/!< 15 TIMER3 /
bogdanm	20:4263a77256ae	286	MCPWM_IRQn = 16,/!< 16 MCPWM /
bogdanm	20:4263a77256ae	287	ADC0_IRQn = 17,/!< 17 ADC0 /
bogdanm	20:4263a77256ae	288	I2C0_IRQn = 18,/!< 18 ORed I2C0, I2C1 /
bogdanm	20:4263a77256ae	289	SGPIO_INT_IRQn = 19,/!< 19 SGPIO /
bogdanm	20:4263a77256ae	290	SPI_INT_IRQn = 20,/!< 20 SPI_INT /
bogdanm	20:4263a77256ae	291	ADC1_IRQn = 21,/!< 21 ADC1 /
bogdanm	20:4263a77256ae	292	SSP0_IRQn = 22,/!< 22 ORed SSP0, SSP1 /
bogdanm	20:4263a77256ae	293	EVENTROUTER_IRQn = 23,/!< 23 EVENTROUTER /
bogdanm	20:4263a77256ae	294	USART0_IRQn = 24,/!< 24 USART0 /
bogdanm	20:4263a77256ae	295	UART1_IRQn = 25,/!< 25 UART1 /
bogdanm	20:4263a77256ae	296	USART2_IRQn = 26,/!< 26 USART2 /
bogdanm	20:4263a77256ae	297	USART3_IRQn = 27,/!< 27 USART3 /
bogdanm	20:4263a77256ae	298	I2S0_IRQn = 28,/!< 28 ORed I2S0, I2S1 /
bogdanm	20:4263a77256ae	299	C_CAN0_IRQn = 29,/!< 29 C_CAN0 /
bogdanm	20:4263a77256ae	300	I2S1_IRQn = 29,/!< 29 I2S1 /
bogdanm	20:4263a77256ae	301	RESERVED2_IRQn = 30,
bogdanm	20:4263a77256ae	302	RESERVED3_IRQn = 31,
bogdanm	20:4263a77256ae	303	} IRQn_Type;
bogdanm	20:4263a77256ae	304
bogdanm	20:4263a77256ae	305	#include "core_cm0.h" /!< Cortex-M4 processor and core peripherals /
bogdanm	20:4263a77256ae	306	#else
bogdanm	20:4263a77256ae	307	#error Please #define CORE_M0, CORE_M3 or CORE_M4
bogdanm	20:4263a77256ae	308	#endif
bogdanm	20:4263a77256ae	309
bogdanm	20:4263a77256ae	310	#include "system_LPC43xx.h"
bogdanm	20:4263a77256ae	311
bogdanm	20:4263a77256ae	312	/**
bogdanm	20:4263a77256ae	313	* @brief State Configurable Timer register block structure
bogdanm	20:4263a77256ae	314	*/
bogdanm	20:4263a77256ae	315	#define LPC_SCT_BASE 0x40000000
bogdanm	20:4263a77256ae	316	#define CONFIG_SCT_nEV (16) /!< Number of events /
bogdanm	20:4263a77256ae	317	#define CONFIG_SCT_nRG (16) /!< Number of match/compare registers /
bogdanm	20:4263a77256ae	318	#define CONFIG_SCT_nOU (16) /!< Number of outputs /
bogdanm	20:4263a77256ae	319
bogdanm	20:4263a77256ae	320	typedef struct {
bogdanm	20:4263a77256ae	321	__IO uint32_t CONFIG; /!< Configuration Register /
bogdanm	20:4263a77256ae	322	union {
bogdanm	20:4263a77256ae	323	__IO uint32_t CTRL_U; /!< Control Register /
bogdanm	20:4263a77256ae	324	struct {
bogdanm	20:4263a77256ae	325	__IO uint16_t CTRL_L; /!< Low control register /
bogdanm	20:4263a77256ae	326	__IO uint16_t CTRL_H; /!< High control register /
bogdanm	20:4263a77256ae	327	};
bogdanm	20:4263a77256ae	328
bogdanm	20:4263a77256ae	329	};
bogdanm	20:4263a77256ae	330
bogdanm	20:4263a77256ae	331	__IO uint16_t LIMIT_L; /!< limit register for counter L /
bogdanm	20:4263a77256ae	332	__IO uint16_t LIMIT_H; /!< limit register for counter H /
bogdanm	20:4263a77256ae	333	__IO uint16_t HALT_L; /!< halt register for counter L /
bogdanm	20:4263a77256ae	334	__IO uint16_t HALT_H; /!< halt register for counter H /
bogdanm	20:4263a77256ae	335	__IO uint16_t STOP_L; /!< stop register for counter L /
bogdanm	20:4263a77256ae	336	__IO uint16_t STOP_H; /!< stop register for counter H /
bogdanm	20:4263a77256ae	337	__IO uint16_t START_L; /!< start register for counter L /
bogdanm	20:4263a77256ae	338	__IO uint16_t START_H; /!< start register for counter H /
bogdanm	20:4263a77256ae	339	uint32_t RESERVED1[10]; /!< 0x03C reserved /
bogdanm	20:4263a77256ae	340	union {
bogdanm	20:4263a77256ae	341	__IO uint32_t COUNT_U; /!< counter register /
bogdanm	20:4263a77256ae	342	struct {
bogdanm	20:4263a77256ae	343	__IO uint16_t COUNT_L; /!< counter register for counter L /
bogdanm	20:4263a77256ae	344	__IO uint16_t COUNT_H; /!< counter register for counter H /
bogdanm	20:4263a77256ae	345	};
bogdanm	20:4263a77256ae	346
bogdanm	20:4263a77256ae	347	};
bogdanm	20:4263a77256ae	348
bogdanm	20:4263a77256ae	349	__IO uint16_t STATE_L; /!< state register for counter L /
bogdanm	20:4263a77256ae	350	__IO uint16_t STATE_H; /!< state register for counter H /
bogdanm	20:4263a77256ae	351	__I uint32_t INPUT; /!< input register /
bogdanm	20:4263a77256ae	352	__IO uint16_t REGMODE_L; /!< match - capture registers mode register L /
bogdanm	20:4263a77256ae	353	__IO uint16_t REGMODE_H; /!< match - capture registers mode register H /
bogdanm	20:4263a77256ae	354	__IO uint32_t OUTPUT; /!< output register /
bogdanm	20:4263a77256ae	355	__IO uint32_t OUTPUTDIRCTRL; /!< output counter direction Control Register /
bogdanm	20:4263a77256ae	356	__IO uint32_t RES; /!< conflict resolution register /
bogdanm	20:4263a77256ae	357	__IO uint32_t DMA0REQUEST; /!< DMA0 Request Register /
bogdanm	20:4263a77256ae	358	__IO uint32_t DMA1REQUEST; /!< DMA1 Request Register /
bogdanm	20:4263a77256ae	359	uint32_t RESERVED2[35];
bogdanm	20:4263a77256ae	360	__IO uint32_t EVEN; /!< event enable register /
bogdanm	20:4263a77256ae	361	__IO uint32_t EVFLAG; /!< event flag register /
bogdanm	20:4263a77256ae	362	__IO uint32_t CONEN; /!< conflict enable register /
bogdanm	20:4263a77256ae	363	__IO uint32_t CONFLAG; /!< conflict flag register /
bogdanm	20:4263a77256ae	364	union {
bogdanm	20:4263a77256ae	365	__IO union { /!< ... Match / Capture value /
bogdanm	20:4263a77256ae	366	uint32_t U; /!< SCTMATCH[i].U Unified 32-bit register /
bogdanm	20:4263a77256ae	367	struct {
bogdanm	20:4263a77256ae	368	uint16_t L; /!< SCTMATCH[i].L Access to L value /
bogdanm	20:4263a77256ae	369	uint16_t H; /!< SCTMATCH[i].H Access to H value /
bogdanm	20:4263a77256ae	370	};
bogdanm	20:4263a77256ae	371
bogdanm	20:4263a77256ae	372	} MATCH[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	373
bogdanm	20:4263a77256ae	374	__I union {
bogdanm	20:4263a77256ae	375	uint32_t U; /!< SCTCAP[i].U Unified 32-bit register /
bogdanm	20:4263a77256ae	376	struct {
bogdanm	20:4263a77256ae	377	uint16_t L; /!< SCTCAP[i].L Access to L value /
bogdanm	20:4263a77256ae	378	uint16_t H; /!< SCTCAP[i].H Access to H value /
bogdanm	20:4263a77256ae	379	};
bogdanm	20:4263a77256ae	380
bogdanm	20:4263a77256ae	381	} CAP[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	382
bogdanm	20:4263a77256ae	383	};
bogdanm	20:4263a77256ae	384
bogdanm	20:4263a77256ae	385	uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /!< ...-0x17C reserved /
bogdanm	20:4263a77256ae	386	union {
bogdanm	20:4263a77256ae	387	__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /!< 0x180-... Match Value L counter /
bogdanm	20:4263a77256ae	388	__I uint16_t CAP_L[CONFIG_SCT_nRG]; /!< 0x180-... Capture Value L counter /
bogdanm	20:4263a77256ae	389	};
bogdanm	20:4263a77256ae	390
bogdanm	20:4263a77256ae	391	uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /!< ...-0x1BE reserved /
bogdanm	20:4263a77256ae	392	union {
bogdanm	20:4263a77256ae	393	__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /!< 0x1C0-... Match Value H counter /
bogdanm	20:4263a77256ae	394	__I uint16_t CAP_H[CONFIG_SCT_nRG]; /!< 0x1C0-... Capture Value H counter /
bogdanm	20:4263a77256ae	395	};
bogdanm	20:4263a77256ae	396
bogdanm	20:4263a77256ae	397	uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /!< ...-0x1FE reserved /
bogdanm	20:4263a77256ae	398	union {
bogdanm	20:4263a77256ae	399	__IO union { /!< 0x200-... Match Reload / Capture Control value /
bogdanm	20:4263a77256ae	400	uint32_t U; /!< SCTMATCHREL[i].U Unified 32-bit register /
bogdanm	20:4263a77256ae	401	struct {
bogdanm	20:4263a77256ae	402	uint16_t L; /!< SCTMATCHREL[i].L Access to L value /
bogdanm	20:4263a77256ae	403	uint16_t H; /!< SCTMATCHREL[i].H Access to H value /
bogdanm	20:4263a77256ae	404	};
bogdanm	20:4263a77256ae	405
bogdanm	20:4263a77256ae	406	} MATCHREL[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	407
bogdanm	20:4263a77256ae	408	__IO union {
bogdanm	20:4263a77256ae	409	uint32_t U; /!< SCTCAPCTRL[i].U Unified 32-bit register /
bogdanm	20:4263a77256ae	410	struct {
bogdanm	20:4263a77256ae	411	uint16_t L; /!< SCTCAPCTRL[i].L Access to L value /
bogdanm	20:4263a77256ae	412	uint16_t H; /!< SCTCAPCTRL[i].H Access to H value /
bogdanm	20:4263a77256ae	413	};
bogdanm	20:4263a77256ae	414
bogdanm	20:4263a77256ae	415	} CAPCTRL[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	416
bogdanm	20:4263a77256ae	417	};
bogdanm	20:4263a77256ae	418
bogdanm	20:4263a77256ae	419	uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /!< ...-0x27C reserved /
bogdanm	20:4263a77256ae	420	union {
bogdanm	20:4263a77256ae	421	__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /!< 0x280-... Match Reload value L counter /
bogdanm	20:4263a77256ae	422	__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /!< 0x280-... Capture Control value L counter /
bogdanm	20:4263a77256ae	423	};
bogdanm	20:4263a77256ae	424
bogdanm	20:4263a77256ae	425	uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /!< ...-0x2BE reserved /
bogdanm	20:4263a77256ae	426	union {
bogdanm	20:4263a77256ae	427	__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /!< 0x2C0-... Match Reload value H counter /
bogdanm	20:4263a77256ae	428	__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /!< 0x2C0-... Capture Control value H counter /
bogdanm	20:4263a77256ae	429	};
bogdanm	20:4263a77256ae	430
bogdanm	20:4263a77256ae	431	uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /!< ...-0x2FE reserved /
bogdanm	20:4263a77256ae	432	__IO struct { /!< 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL/
bogdanm	20:4263a77256ae	433	uint32_t STATE; /!< Event State Register /
bogdanm	20:4263a77256ae	434	uint32_t CTRL; /!< Event Control Register /
bogdanm	20:4263a77256ae	435	} EVENT[CONFIG_SCT_nEV];
bogdanm	20:4263a77256ae	436
bogdanm	20:4263a77256ae	437	uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /!< ...-0x4FC reserved /
bogdanm	20:4263a77256ae	438	__IO struct { /!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR /
bogdanm	20:4263a77256ae	439	uint32_t SET; /!< Output n Set Register /
bogdanm	20:4263a77256ae	440	uint32_t CLR; /!< Output n Clear Register /
bogdanm	20:4263a77256ae	441	} OUT[CONFIG_SCT_nOU];
bogdanm	20:4263a77256ae	442
bogdanm	20:4263a77256ae	443	uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /!< ...-0x7F8 reserved /
bogdanm	20:4263a77256ae	444	__I uint32_t MODULECONTENT; /!< 0x7FC Module Content /
bogdanm	20:4263a77256ae	445	} LPC_SCT_T;
bogdanm	20:4263a77256ae	446
bogdanm	20:4263a77256ae	447	/**
bogdanm	20:4263a77256ae	448	* @brief GPDMA Channel register block structure
bogdanm	20:4263a77256ae	449	*/
bogdanm	20:4263a77256ae	450	#define LPC_GPDMA_BASE 0x40002000
bogdanm	20:4263a77256ae	451
bogdanm	20:4263a77256ae	452	typedef struct {
bogdanm	20:4263a77256ae	453	__IO uint32_t SRCADDR; /!< DMA Channel Source Address Register /
bogdanm	20:4263a77256ae	454	__IO uint32_t DESTADDR; /!< DMA Channel Destination Address Register /
bogdanm	20:4263a77256ae	455	__IO uint32_t LLI; /!< DMA Channel Linked List Item Register /
bogdanm	20:4263a77256ae	456	__IO uint32_t CONTROL; /!< DMA Channel Control Register /
bogdanm	20:4263a77256ae	457	__IO uint32_t CONFIG; /!< DMA Channel Configuration Register /
bogdanm	20:4263a77256ae	458	__I uint32_t RESERVED1[3];
bogdanm	20:4263a77256ae	459	} LPC_GPDMA_CH_T;
bogdanm	20:4263a77256ae	460
bogdanm	20:4263a77256ae	461	#define GPDMA_CHANNELS 8
bogdanm	20:4263a77256ae	462
bogdanm	20:4263a77256ae	463	/**
bogdanm	20:4263a77256ae	464	* @brief GPDMA register block
bogdanm	20:4263a77256ae	465	*/
bogdanm	20:4263a77256ae	466	typedef struct { /!< GPDMA Structure /
bogdanm	20:4263a77256ae	467	__I uint32_t INTSTAT; /!< DMA Interrupt Status Register /
bogdanm	20:4263a77256ae	468	__I uint32_t INTTCSTAT; /!< DMA Interrupt Terminal Count Request Status Register /
bogdanm	20:4263a77256ae	469	__O uint32_t INTTCCLEAR; /!< DMA Interrupt Terminal Count Request Clear Register /
bogdanm	20:4263a77256ae	470	__I uint32_t INTERRSTAT; /!< DMA Interrupt Error Status Register /
bogdanm	20:4263a77256ae	471	__O uint32_t INTERRCLR; /!< DMA Interrupt Error Clear Register /
bogdanm	20:4263a77256ae	472	__I uint32_t RAWINTTCSTAT; /!< DMA Raw Interrupt Terminal Count Status Register /
bogdanm	20:4263a77256ae	473	__I uint32_t RAWINTERRSTAT; /!< DMA Raw Error Interrupt Status Register /
bogdanm	20:4263a77256ae	474	__I uint32_t ENBLDCHNS; /!< DMA Enabled Channel Register /
bogdanm	20:4263a77256ae	475	__IO uint32_t SOFTBREQ; /!< DMA Software Burst Request Register /
bogdanm	20:4263a77256ae	476	__IO uint32_t SOFTSREQ; /!< DMA Software Single Request Register /
bogdanm	20:4263a77256ae	477	__IO uint32_t SOFTLBREQ; /!< DMA Software Last Burst Request Register /
bogdanm	20:4263a77256ae	478	__IO uint32_t SOFTLSREQ; /!< DMA Software Last Single Request Register /
bogdanm	20:4263a77256ae	479	__IO uint32_t CONFIG; /!< DMA Configuration Register /
bogdanm	20:4263a77256ae	480	__IO uint32_t SYNC; /!< DMA Synchronization Register /
bogdanm	20:4263a77256ae	481	__I uint32_t RESERVED0[50];
bogdanm	20:4263a77256ae	482	LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
bogdanm	20:4263a77256ae	483	} LPC_GPDMA_T;
bogdanm	20:4263a77256ae	484
bogdanm	20:4263a77256ae	485	/**
bogdanm	20:4263a77256ae	486	* @brief SD/MMC & SDIO register block structure
bogdanm	20:4263a77256ae	487	*/
bogdanm	20:4263a77256ae	488	#define LPC_SDMMC_BASE 0x40004000
bogdanm	20:4263a77256ae	489
bogdanm	20:4263a77256ae	490	typedef struct { /!< SDMMC Structure /
bogdanm	20:4263a77256ae	491	__IO uint32_t CTRL; /!< Control Register /
bogdanm	20:4263a77256ae	492	__IO uint32_t PWREN; /!< Power Enable Register /
bogdanm	20:4263a77256ae	493	__IO uint32_t CLKDIV; /!< Clock Divider Register /
bogdanm	20:4263a77256ae	494	__IO uint32_t CLKSRC; /!< SD Clock Source Register /
bogdanm	20:4263a77256ae	495	__IO uint32_t CLKENA; /!< Clock Enable Register /
bogdanm	20:4263a77256ae	496	__IO uint32_t TMOUT; /!< Timeout Register /
bogdanm	20:4263a77256ae	497	__IO uint32_t CTYPE; /!< Card Type Register /
bogdanm	20:4263a77256ae	498	__IO uint32_t BLKSIZ; /!< Block Size Register /
bogdanm	20:4263a77256ae	499	__IO uint32_t BYTCNT; /!< Byte Count Register /
bogdanm	20:4263a77256ae	500	__IO uint32_t INTMASK; /!< Interrupt Mask Register /
bogdanm	20:4263a77256ae	501	__IO uint32_t CMDARG; /!< Command Argument Register /
bogdanm	20:4263a77256ae	502	__IO uint32_t CMD; /!< Command Register /
bogdanm	20:4263a77256ae	503	__I uint32_t RESP0; /!< Response Register 0 /
bogdanm	20:4263a77256ae	504	__I uint32_t RESP1; /!< Response Register 1 /
bogdanm	20:4263a77256ae	505	__I uint32_t RESP2; /!< Response Register 2 /
bogdanm	20:4263a77256ae	506	__I uint32_t RESP3; /!< Response Register 3 /
bogdanm	20:4263a77256ae	507	__I uint32_t MINTSTS; /!< Masked Interrupt Status Register /
bogdanm	20:4263a77256ae	508	__IO uint32_t RINTSTS; /!< Raw Interrupt Status Register /
bogdanm	20:4263a77256ae	509	__I uint32_t STATUS; /!< Status Register /
bogdanm	20:4263a77256ae	510	__IO uint32_t FIFOTH; /!< FIFO Threshold Watermark Register /
bogdanm	20:4263a77256ae	511	__I uint32_t CDETECT; /!< Card Detect Register /
bogdanm	20:4263a77256ae	512	__I uint32_t WRTPRT; /!< Write Protect Register /
bogdanm	20:4263a77256ae	513	__IO uint32_t GPIO; /!< General Purpose Input/Output Register /
bogdanm	20:4263a77256ae	514	__I uint32_t TCBCNT; /!< Transferred CIU Card Byte Count Register /
bogdanm	20:4263a77256ae	515	__I uint32_t TBBCNT; /!< Transferred Host to BIU-FIFO Byte Count Register /
bogdanm	20:4263a77256ae	516	__IO uint32_t DEBNCE; /!< Debounce Count Register /
bogdanm	20:4263a77256ae	517	__IO uint32_t USRID; /!< User ID Register /
bogdanm	20:4263a77256ae	518	__I uint32_t VERID; /!< Version ID Register /
bogdanm	20:4263a77256ae	519	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	520	__IO uint32_t UHS_REG; /!< UHS-1 Register /
bogdanm	20:4263a77256ae	521	__IO uint32_t RST_N; /!< Hardware Reset /
bogdanm	20:4263a77256ae	522	__I uint32_t RESERVED1;
bogdanm	20:4263a77256ae	523	__IO uint32_t BMOD; /!< Bus Mode Register /
bogdanm	20:4263a77256ae	524	__O uint32_t PLDMND; /!< Poll Demand Register /
bogdanm	20:4263a77256ae	525	__IO uint32_t DBADDR; /!< Descriptor List Base Address Register /
bogdanm	20:4263a77256ae	526	__IO uint32_t IDSTS; /!< Internal DMAC Status Register /
bogdanm	20:4263a77256ae	527	__IO uint32_t IDINTEN; /!< Internal DMAC Interrupt Enable Register /
bogdanm	20:4263a77256ae	528	__I uint32_t DSCADDR; /!< Current Host Descriptor Address Register /
bogdanm	20:4263a77256ae	529	__I uint32_t BUFADDR; /!< Current Buffer Descriptor Address Register /
bogdanm	20:4263a77256ae	530	} LPC_SDMMC_T;
bogdanm	20:4263a77256ae	531
bogdanm	20:4263a77256ae	532	/**
bogdanm	20:4263a77256ae	533	* @brief External Memory Controller (EMC) register block structure
bogdanm	20:4263a77256ae	534	*/
bogdanm	20:4263a77256ae	535	#define LPC_EMC_BASE 0x40005000
bogdanm	20:4263a77256ae	536
bogdanm	20:4263a77256ae	537	typedef struct { /!< EMC Structure /
bogdanm	20:4263a77256ae	538	__IO uint32_t CONTROL; /!< Controls operation of the memory controller. /
bogdanm	20:4263a77256ae	539	__I uint32_t STATUS; /!< Provides EMC status information. /
bogdanm	20:4263a77256ae	540	__IO uint32_t CONFIG; /!< Configures operation of the memory controller. /
bogdanm	20:4263a77256ae	541	__I uint32_t RESERVED0[5];
bogdanm	20:4263a77256ae	542	__IO uint32_t DYNAMICCONTROL; /!< Controls dynamic memory operation. /
bogdanm	20:4263a77256ae	543	__IO uint32_t DYNAMICREFRESH; /!< Configures dynamic memory refresh operation. /
bogdanm	20:4263a77256ae	544	__IO uint32_t DYNAMICREADCONFIG; /!< Configures the dynamic memory read strategy. /
bogdanm	20:4263a77256ae	545	__I uint32_t RESERVED1;
bogdanm	20:4263a77256ae	546	__IO uint32_t DYNAMICRP; /!< Selects the precharge command period. /
bogdanm	20:4263a77256ae	547	__IO uint32_t DYNAMICRAS; /!< Selects the active to precharge command period. /
bogdanm	20:4263a77256ae	548	__IO uint32_t DYNAMICSREX; /!< Selects the self-refresh exit time. /
bogdanm	20:4263a77256ae	549	__IO uint32_t DYNAMICAPR; /!< Selects the last-data-out to active command time. /
bogdanm	20:4263a77256ae	550	__IO uint32_t DYNAMICDAL; /!< Selects the data-in to active command time. /
bogdanm	20:4263a77256ae	551	__IO uint32_t DYNAMICWR; /!< Selects the write recovery time. /
bogdanm	20:4263a77256ae	552	__IO uint32_t DYNAMICRC; /!< Selects the active to active command period. /
bogdanm	20:4263a77256ae	553	__IO uint32_t DYNAMICRFC; /!< Selects the auto-refresh period. /
bogdanm	20:4263a77256ae	554	__IO uint32_t DYNAMICXSR; /!< Selects the exit self-refresh to active command time. /
bogdanm	20:4263a77256ae	555	__IO uint32_t DYNAMICRRD; /!< Selects the active bank A to active bank B latency. /
bogdanm	20:4263a77256ae	556	__IO uint32_t DYNAMICMRD; /!< Selects the load mode register to active command time. /
bogdanm	20:4263a77256ae	557	__I uint32_t RESERVED2[9];
bogdanm	20:4263a77256ae	558	__IO uint32_t STATICEXTENDEDWAIT; /!< Selects time for long static memory read and write transfers. /
bogdanm	20:4263a77256ae	559	__I uint32_t RESERVED3[31];
bogdanm	20:4263a77256ae	560	__IO uint32_t DYNAMICCONFIG0; /!< Selects the configuration information for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	561	__IO uint32_t DYNAMICRASCAS0; /!< Selects the RAS and CAS latencies for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	562	__I uint32_t RESERVED4[6];
bogdanm	20:4263a77256ae	563	__IO uint32_t DYNAMICCONFIG1; /!< Selects the configuration information for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	564	__IO uint32_t DYNAMICRASCAS1; /!< Selects the RAS and CAS latencies for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	565	__I uint32_t RESERVED5[6];
bogdanm	20:4263a77256ae	566	__IO uint32_t DYNAMICCONFIG2; /!< Selects the configuration information for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	567	__IO uint32_t DYNAMICRASCAS2; /!< Selects the RAS and CAS latencies for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	568	__I uint32_t RESERVED6[6];
bogdanm	20:4263a77256ae	569	__IO uint32_t DYNAMICCONFIG3; /!< Selects the configuration information for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	570	__IO uint32_t DYNAMICRASCAS3; /!< Selects the RAS and CAS latencies for dynamic memory chip select n. /
bogdanm	20:4263a77256ae	571	__I uint32_t RESERVED7[38];
bogdanm	20:4263a77256ae	572	__IO uint32_t STATICCONFIG0; /!< Selects the memory configuration for static chip select n. /
bogdanm	20:4263a77256ae	573	__IO uint32_t STATICWAITWEN0; /!< Selects the delay from chip select n to write enable. /
bogdanm	20:4263a77256ae	574	__IO uint32_t STATICWAITOEN0; /!< Selects the delay from chip select n or address change, whichever is later, to output enable. /
bogdanm	20:4263a77256ae	575	__IO uint32_t STATICWAITRD0; /!< Selects the delay from chip select n to a read access. /
bogdanm	20:4263a77256ae	576	__IO uint32_t STATICWAITPAG0; /!< Selects the delay for asynchronous page mode sequential accesses for chip select n. /
bogdanm	20:4263a77256ae	577	__IO uint32_t STATICWAITWR0; /!< Selects the delay from chip select n to a write access. /
bogdanm	20:4263a77256ae	578	__IO uint32_t STATICWAITTURN0; /!< Selects bus turnaround cycles /
bogdanm	20:4263a77256ae	579	__I uint32_t RESERVED8;
bogdanm	20:4263a77256ae	580	__IO uint32_t STATICCONFIG1; /!< Selects the memory configuration for static chip select n. /
bogdanm	20:4263a77256ae	581	__IO uint32_t STATICWAITWEN1; /!< Selects the delay from chip select n to write enable. /
bogdanm	20:4263a77256ae	582	__IO uint32_t STATICWAITOEN1; /!< Selects the delay from chip select n or address change, whichever is later, to output enable. /
bogdanm	20:4263a77256ae	583	__IO uint32_t STATICWAITRD1; /!< Selects the delay from chip select n to a read access. /
bogdanm	20:4263a77256ae	584	__IO uint32_t STATICWAITPAG1; /!< Selects the delay for asynchronous page mode sequential accesses for chip select n. /
bogdanm	20:4263a77256ae	585	__IO uint32_t STATICWAITWR1; /!< Selects the delay from chip select n to a write access. /
bogdanm	20:4263a77256ae	586	__IO uint32_t STATICWAITTURN1; /!< Selects bus turnaround cycles /
bogdanm	20:4263a77256ae	587	__I uint32_t RESERVED9;
bogdanm	20:4263a77256ae	588	__IO uint32_t STATICCONFIG2; /!< Selects the memory configuration for static chip select n. /
bogdanm	20:4263a77256ae	589	__IO uint32_t STATICWAITWEN2; /!< Selects the delay from chip select n to write enable. /
bogdanm	20:4263a77256ae	590	__IO uint32_t STATICWAITOEN2; /!< Selects the delay from chip select n or address change, whichever is later, to output enable. /
bogdanm	20:4263a77256ae	591	__IO uint32_t STATICWAITRD2; /!< Selects the delay from chip select n to a read access. /
bogdanm	20:4263a77256ae	592	__IO uint32_t STATICWAITPAG2; /!< Selects the delay for asynchronous page mode sequential accesses for chip select n. /
bogdanm	20:4263a77256ae	593	__IO uint32_t STATICWAITWR2; /!< Selects the delay from chip select n to a write access. /
bogdanm	20:4263a77256ae	594	__IO uint32_t STATICWAITTURN2; /!< Selects bus turnaround cycles /
bogdanm	20:4263a77256ae	595	__I uint32_t RESERVED10;
bogdanm	20:4263a77256ae	596	__IO uint32_t STATICCONFIG3; /!< Selects the memory configuration for static chip select n. /
bogdanm	20:4263a77256ae	597	__IO uint32_t STATICWAITWEN3; /!< Selects the delay from chip select n to write enable. /
bogdanm	20:4263a77256ae	598	__IO uint32_t STATICWAITOEN3; /!< Selects the delay from chip select n or address change, whichever is later, to output enable. /
bogdanm	20:4263a77256ae	599	__IO uint32_t STATICWAITRD3; /!< Selects the delay from chip select n to a read access. /
bogdanm	20:4263a77256ae	600	__IO uint32_t STATICWAITPAG3; /!< Selects the delay for asynchronous page mode sequential accesses for chip select n. /
bogdanm	20:4263a77256ae	601	__IO uint32_t STATICWAITWR3; /!< Selects the delay from chip select n to a write access. /
bogdanm	20:4263a77256ae	602	__IO uint32_t STATICWAITTURN3; /!< Selects bus turnaround cycles /
bogdanm	20:4263a77256ae	603	} LPC_EMC_T;
bogdanm	20:4263a77256ae	604
bogdanm	20:4263a77256ae	605	/**
bogdanm	20:4263a77256ae	606	* @brief USB High-Speed register block structure
bogdanm	20:4263a77256ae	607	*/
bogdanm	20:4263a77256ae	608	#define LPC_USB0_BASE 0x40006000
bogdanm	20:4263a77256ae	609	#define LPC_USB1_BASE 0x40007000
bogdanm	20:4263a77256ae	610
bogdanm	20:4263a77256ae	611	typedef struct { /!< USB Structure /
bogdanm	20:4263a77256ae	612	__I uint32_t RESERVED0[64];
bogdanm	20:4263a77256ae	613	__I uint32_t CAPLENGTH; /!< Capability register length /
bogdanm	20:4263a77256ae	614	__I uint32_t HCSPARAMS; /!< Host controller structural parameters /
bogdanm	20:4263a77256ae	615	__I uint32_t HCCPARAMS; /!< Host controller capability parameters /
bogdanm	20:4263a77256ae	616	__I uint32_t RESERVED1[5];
bogdanm	20:4263a77256ae	617	__I uint32_t DCIVERSION; /!< Device interface version number /
bogdanm	20:4263a77256ae	618	__I uint32_t RESERVED2[7];
bogdanm	20:4263a77256ae	619	union {
bogdanm	20:4263a77256ae	620	__IO uint32_t USBCMD_H; /!< USB command (host mode) /
bogdanm	20:4263a77256ae	621	__IO uint32_t USBCMD_D; /!< USB command (device mode) /
bogdanm	20:4263a77256ae	622	};
bogdanm	20:4263a77256ae	623
bogdanm	20:4263a77256ae	624	union {
bogdanm	20:4263a77256ae	625	__IO uint32_t USBSTS_H; /!< USB status (host mode) /
bogdanm	20:4263a77256ae	626	__IO uint32_t USBSTS_D; /!< USB status (device mode) /
bogdanm	20:4263a77256ae	627	};
bogdanm	20:4263a77256ae	628
bogdanm	20:4263a77256ae	629	union {
bogdanm	20:4263a77256ae	630	__IO uint32_t USBINTR_H; /!< USB interrupt enable (host mode) /
bogdanm	20:4263a77256ae	631	__IO uint32_t USBINTR_D; /!< USB interrupt enable (device mode) /
bogdanm	20:4263a77256ae	632	};
bogdanm	20:4263a77256ae	633
bogdanm	20:4263a77256ae	634	union {
bogdanm	20:4263a77256ae	635	__IO uint32_t FRINDEX_H; /!< USB frame index (host mode) /
bogdanm	20:4263a77256ae	636	__I uint32_t FRINDEX_D; /!< USB frame index (device mode) /
bogdanm	20:4263a77256ae	637	};
bogdanm	20:4263a77256ae	638
bogdanm	20:4263a77256ae	639	__I uint32_t RESERVED3;
bogdanm	20:4263a77256ae	640	union {
bogdanm	20:4263a77256ae	641	__IO uint32_t PERIODICLISTBASE; /!< Frame list base address /
bogdanm	20:4263a77256ae	642	__IO uint32_t DEVICEADDR; /!< USB device address /
bogdanm	20:4263a77256ae	643	};
bogdanm	20:4263a77256ae	644
bogdanm	20:4263a77256ae	645	union {
bogdanm	20:4263a77256ae	646	__IO uint32_t ASYNCLISTADDR; /!< Address of endpoint list in memory (host mode) /
bogdanm	20:4263a77256ae	647	__IO uint32_t ENDPOINTLISTADDR; /!< Address of endpoint list in memory (device mode) /
bogdanm	20:4263a77256ae	648	};
bogdanm	20:4263a77256ae	649
bogdanm	20:4263a77256ae	650	__IO uint32_t TTCTRL; /!< Asynchronous buffer status for embedded TT (host mode) /
bogdanm	20:4263a77256ae	651	__IO uint32_t BURSTSIZE; /!< Programmable burst size /
bogdanm	20:4263a77256ae	652	__IO uint32_t TXFILLTUNING; /!< Host transmit pre-buffer packet tuning (host mode) /
bogdanm	20:4263a77256ae	653	__I uint32_t RESERVED4[2];
bogdanm	20:4263a77256ae	654	__IO uint32_t ULPIVIEWPORT; /!< ULPI viewport /
bogdanm	20:4263a77256ae	655	__IO uint32_t BINTERVAL; /!< Length of virtual frame /
bogdanm	20:4263a77256ae	656	__IO uint32_t ENDPTNAK; /!< Endpoint NAK (device mode) /
bogdanm	20:4263a77256ae	657	__IO uint32_t ENDPTNAKEN; /!< Endpoint NAK Enable (device mode) /
bogdanm	20:4263a77256ae	658	__I uint32_t RESERVED5;
bogdanm	20:4263a77256ae	659	union {
bogdanm	20:4263a77256ae	660	__IO uint32_t PORTSC1_H; /!< Port 1 status/control (host mode) /
bogdanm	20:4263a77256ae	661	__IO uint32_t PORTSC1_D; /!< Port 1 status/control (device mode) /
bogdanm	20:4263a77256ae	662	};
bogdanm	20:4263a77256ae	663
bogdanm	20:4263a77256ae	664	__I uint32_t RESERVED6[7];
bogdanm	20:4263a77256ae	665	__IO uint32_t OTGSC; /!< OTG status and control /
bogdanm	20:4263a77256ae	666	union {
bogdanm	20:4263a77256ae	667	__IO uint32_t USBMODE_H; /!< USB mode (host mode) /
bogdanm	20:4263a77256ae	668	__IO uint32_t USBMODE_D; /!< USB mode (device mode) /
bogdanm	20:4263a77256ae	669	};
bogdanm	20:4263a77256ae	670
bogdanm	20:4263a77256ae	671	__IO uint32_t ENDPTSETUPSTAT; /!< Endpoint setup status /
bogdanm	20:4263a77256ae	672	__IO uint32_t ENDPTPRIME; /!< Endpoint initialization /
bogdanm	20:4263a77256ae	673	__IO uint32_t ENDPTFLUSH; /!< Endpoint de-initialization /
bogdanm	20:4263a77256ae	674	__I uint32_t ENDPTSTAT; /!< Endpoint status /
bogdanm	20:4263a77256ae	675	__IO uint32_t ENDPTCOMPLETE; /!< Endpoint complete /
bogdanm	20:4263a77256ae	676	__IO uint32_t ENDPTCTRL[6]; /!< Endpoint control 0 /
bogdanm	20:4263a77256ae	677	} LPC_USBHS_T;
bogdanm	20:4263a77256ae	678
bogdanm	20:4263a77256ae	679	/**
bogdanm	20:4263a77256ae	680	* @brief LCD Controller register block structure
bogdanm	20:4263a77256ae	681	*/
bogdanm	20:4263a77256ae	682	#define LPC_LCD_BASE 0x40008000
bogdanm	20:4263a77256ae	683
bogdanm	20:4263a77256ae	684	typedef struct { /!< LCD Structure /
bogdanm	20:4263a77256ae	685	__IO uint32_t TIMH; /!< Horizontal Timing Control register /
bogdanm	20:4263a77256ae	686	__IO uint32_t TIMV; /!< Vertical Timing Control register /
bogdanm	20:4263a77256ae	687	__IO uint32_t POL; /!< Clock and Signal Polarity Control register /
bogdanm	20:4263a77256ae	688	__IO uint32_t LE; /!< Line End Control register /
bogdanm	20:4263a77256ae	689	__IO uint32_t UPBASE; /!< Upper Panel Frame Base Address register /
bogdanm	20:4263a77256ae	690	__IO uint32_t LPBASE; /!< Lower Panel Frame Base Address register /
bogdanm	20:4263a77256ae	691	__IO uint32_t CTRL; /!< LCD Control register /
bogdanm	20:4263a77256ae	692	__IO uint32_t INTMSK; /!< Interrupt Mask register /
bogdanm	20:4263a77256ae	693	__I uint32_t INTRAW; /!< Raw Interrupt Status register /
bogdanm	20:4263a77256ae	694	__I uint32_t INTSTAT; /!< Masked Interrupt Status register /
bogdanm	20:4263a77256ae	695	__O uint32_t INTCLR; /!< Interrupt Clear register /
bogdanm	20:4263a77256ae	696	__I uint32_t UPCURR; /!< Upper Panel Current Address Value register /
bogdanm	20:4263a77256ae	697	__I uint32_t LPCURR; /!< Lower Panel Current Address Value register /
bogdanm	20:4263a77256ae	698	__I uint32_t RESERVED0[115];
bogdanm	20:4263a77256ae	699	__IO uint16_t PAL[256]; /!< 256x16-bit Color Palette registers /
bogdanm	20:4263a77256ae	700	__I uint32_t RESERVED1[256];
bogdanm	20:4263a77256ae	701	__IO uint32_t CRSR_IMG[256];/!< Cursor Image registers /
bogdanm	20:4263a77256ae	702	__IO uint32_t CRSR_CTRL; /!< Cursor Control register /
bogdanm	20:4263a77256ae	703	__IO uint32_t CRSR_CFG; /!< Cursor Configuration register /
bogdanm	20:4263a77256ae	704	__IO uint32_t CRSR_PAL0; /!< Cursor Palette register 0 /
bogdanm	20:4263a77256ae	705	__IO uint32_t CRSR_PAL1; /!< Cursor Palette register 1 /
bogdanm	20:4263a77256ae	706	__IO uint32_t CRSR_XY; /!< Cursor XY Position register /
bogdanm	20:4263a77256ae	707	__IO uint32_t CRSR_CLIP; /!< Cursor Clip Position register /
bogdanm	20:4263a77256ae	708	__I uint32_t RESERVED2[2];
bogdanm	20:4263a77256ae	709	__IO uint32_t CRSR_INTMSK; /!< Cursor Interrupt Mask register /
bogdanm	20:4263a77256ae	710	__O uint32_t CRSR_INTCLR; /!< Cursor Interrupt Clear register /
bogdanm	20:4263a77256ae	711	__I uint32_t CRSR_INTRAW; /!< Cursor Raw Interrupt Status register /
bogdanm	20:4263a77256ae	712	__I uint32_t CRSR_INTSTAT;/!< Cursor Masked Interrupt Status register /
bogdanm	20:4263a77256ae	713	} LPC_LCD_T;
bogdanm	20:4263a77256ae	714
bogdanm	20:4263a77256ae	715	/**
bogdanm	20:4263a77256ae	716	* @brief EEPROM register block structure
bogdanm	20:4263a77256ae	717	*/
bogdanm	20:4263a77256ae	718	#define LPC_EEPROM_BASE 0x4000E000
bogdanm	20:4263a77256ae	719
bogdanm	20:4263a77256ae	720	typedef struct { /* EEPROM Structure */
bogdanm	20:4263a77256ae	721	__IO uint32_t CMD; /!< EEPROM command register /
bogdanm	20:4263a77256ae	722	uint32_t RESERVED0;
bogdanm	20:4263a77256ae	723	__IO uint32_t RWSTATE; /!< EEPROM read wait state register /
bogdanm	20:4263a77256ae	724	__IO uint32_t AUTOPROG; /!< EEPROM auto programming register /
bogdanm	20:4263a77256ae	725	__IO uint32_t WSTATE; /!< EEPROM wait state register /
bogdanm	20:4263a77256ae	726	__IO uint32_t CLKDIV; /!< EEPROM clock divider register /
bogdanm	20:4263a77256ae	727	__IO uint32_t PWRDWN; /!< EEPROM power-down register /
bogdanm	20:4263a77256ae	728	uint32_t RESERVED2[1007];
bogdanm	20:4263a77256ae	729	__O uint32_t INTENCLR; /!< EEPROM interrupt enable clear /
bogdanm	20:4263a77256ae	730	__O uint32_t INTENSET; /!< EEPROM interrupt enable set /
bogdanm	20:4263a77256ae	731	__I uint32_t INTSTAT; /!< EEPROM interrupt status /
bogdanm	20:4263a77256ae	732	__I uint32_t INTEN; /!< EEPROM interrupt enable /
bogdanm	20:4263a77256ae	733	__O uint32_t INTSTATCLR; /!< EEPROM interrupt status clear /
bogdanm	20:4263a77256ae	734	__O uint32_t INTSTATSET; /!< EEPROM interrupt status set /
bogdanm	20:4263a77256ae	735	} LPC_EEPROM_T;
bogdanm	20:4263a77256ae	736
bogdanm	20:4263a77256ae	737	/**
bogdanm	20:4263a77256ae	738	* @brief 10/100 MII & RMII Ethernet with timestamping register block structure
bogdanm	20:4263a77256ae	739	*/
bogdanm	20:4263a77256ae	740	#define LPC_ETHERNET_BASE 0x40010000
bogdanm	20:4263a77256ae	741
bogdanm	20:4263a77256ae	742	typedef struct { /!< ETHERNET Structure /
bogdanm	20:4263a77256ae	743	__IO uint32_t MAC_CONFIG; /!< MAC configuration register /
bogdanm	20:4263a77256ae	744	__IO uint32_t MAC_FRAME_FILTER; /!< MAC frame filter /
bogdanm	20:4263a77256ae	745	__IO uint32_t MAC_HASHTABLE_HIGH; /!< Hash table high register /
bogdanm	20:4263a77256ae	746	__IO uint32_t MAC_HASHTABLE_LOW; /!< Hash table low register /
bogdanm	20:4263a77256ae	747	__IO uint32_t MAC_MII_ADDR; /!< MII address register /
bogdanm	20:4263a77256ae	748	__IO uint32_t MAC_MII_DATA; /!< MII data register /
bogdanm	20:4263a77256ae	749	__IO uint32_t MAC_FLOW_CTRL; /!< Flow control register /
bogdanm	20:4263a77256ae	750	__IO uint32_t MAC_VLAN_TAG; /!< VLAN tag register /
bogdanm	20:4263a77256ae	751	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	752	__I uint32_t MAC_DEBUG; /!< Debug register /
bogdanm	20:4263a77256ae	753	__IO uint32_t MAC_RWAKE_FRFLT; /!< Remote wake-up frame filter /
bogdanm	20:4263a77256ae	754	__IO uint32_t MAC_PMT_CTRL_STAT; /!< PMT control and status /
bogdanm	20:4263a77256ae	755	__I uint32_t RESERVED1[2];
bogdanm	20:4263a77256ae	756	__I uint32_t MAC_INTR; /!< Interrupt status register /
bogdanm	20:4263a77256ae	757	__IO uint32_t MAC_INTR_MASK; /!< Interrupt mask register /
bogdanm	20:4263a77256ae	758	__IO uint32_t MAC_ADDR0_HIGH; /!< MAC address 0 high register /
bogdanm	20:4263a77256ae	759	__IO uint32_t MAC_ADDR0_LOW; /!< MAC address 0 low register /
bogdanm	20:4263a77256ae	760	__I uint32_t RESERVED2[430];
bogdanm	20:4263a77256ae	761	__IO uint32_t MAC_TIMESTP_CTRL; /!< Time stamp control register /
bogdanm	20:4263a77256ae	762	__IO uint32_t SUBSECOND_INCR; /!< Sub-second increment register /
bogdanm	20:4263a77256ae	763	__I uint32_t SECONDS; /!< System time seconds register /
bogdanm	20:4263a77256ae	764	__I uint32_t NANOSECONDS; /!< System time nanoseconds register /
bogdanm	20:4263a77256ae	765	__IO uint32_t SECONDSUPDATE; /!< System time seconds update register /
bogdanm	20:4263a77256ae	766	__IO uint32_t NANOSECONDSUPDATE; /!< System time nanoseconds update register /
bogdanm	20:4263a77256ae	767	__IO uint32_t ADDEND; /!< Time stamp addend register /
bogdanm	20:4263a77256ae	768	__IO uint32_t TARGETSECONDS; /!< Target time seconds register /
bogdanm	20:4263a77256ae	769	__IO uint32_t TARGETNANOSECONDS; /!< Target time nanoseconds register /
bogdanm	20:4263a77256ae	770	__IO uint32_t HIGHWORD; /!< System time higher word seconds register /
bogdanm	20:4263a77256ae	771	__I uint32_t TIMESTAMPSTAT; /!< Time stamp status register /
bogdanm	20:4263a77256ae	772	__IO uint32_t PPSCTRL; /!< PPS control register /
bogdanm	20:4263a77256ae	773	__I uint32_t AUXNANOSECONDS; /!< Auxiliary time stamp nanoseconds register /
bogdanm	20:4263a77256ae	774	__I uint32_t AUXSECONDS; /!< Auxiliary time stamp seconds register /
bogdanm	20:4263a77256ae	775	__I uint32_t RESERVED3[562];
bogdanm	20:4263a77256ae	776	__IO uint32_t DMA_BUS_MODE; /!< Bus Mode Register /
bogdanm	20:4263a77256ae	777	__IO uint32_t DMA_TRANS_POLL_DEMAND; /!< Transmit poll demand register /
bogdanm	20:4263a77256ae	778	__IO uint32_t DMA_REC_POLL_DEMAND; /!< Receive poll demand register /
bogdanm	20:4263a77256ae	779	__IO uint32_t DMA_REC_DES_ADDR; /!< Receive descriptor list address register /
bogdanm	20:4263a77256ae	780	__IO uint32_t DMA_TRANS_DES_ADDR; /!< Transmit descriptor list address register /
bogdanm	20:4263a77256ae	781	__IO uint32_t DMA_STAT; /!< Status register /
bogdanm	20:4263a77256ae	782	__IO uint32_t DMA_OP_MODE; /!< Operation mode register /
bogdanm	20:4263a77256ae	783	__IO uint32_t DMA_INT_EN; /!< Interrupt enable register /
bogdanm	20:4263a77256ae	784	__I uint32_t DMA_MFRM_BUFOF; /!< Missed frame and buffer overflow register /
bogdanm	20:4263a77256ae	785	__IO uint32_t DMA_REC_INT_WDT; /!< Receive interrupt watchdog timer register /
bogdanm	20:4263a77256ae	786	__I uint32_t RESERVED4[8];
bogdanm	20:4263a77256ae	787	__I uint32_t DMA_CURHOST_TRANS_DES; /!< Current host transmit descriptor register /
bogdanm	20:4263a77256ae	788	__I uint32_t DMA_CURHOST_REC_DES; /!< Current host receive descriptor register /
bogdanm	20:4263a77256ae	789	__I uint32_t DMA_CURHOST_TRANS_BUF; /!< Current host transmit buffer address register /
bogdanm	20:4263a77256ae	790	__I uint32_t DMA_CURHOST_REC_BUF; /!< Current host receive buffer address register /
bogdanm	20:4263a77256ae	791	} LPC_ENET_T;
bogdanm	20:4263a77256ae	792
bogdanm	20:4263a77256ae	793	/**
bogdanm	20:4263a77256ae	794	* @brief Alarm Timer register block structure
bogdanm	20:4263a77256ae	795	*/
bogdanm	20:4263a77256ae	796	#define LPC_ATIMER_BASE 0x40040000
bogdanm	20:4263a77256ae	797
bogdanm	20:4263a77256ae	798	typedef struct { /!< ATIMER Structure /
bogdanm	20:4263a77256ae	799	__IO uint32_t DOWNCOUNTER; /!< Downcounter register /
bogdanm	20:4263a77256ae	800	__IO uint32_t PRESET; /!< Preset value register /
bogdanm	20:4263a77256ae	801	__I uint32_t RESERVED0[1012];
bogdanm	20:4263a77256ae	802	__O uint32_t CLR_EN; /!< Interrupt clear enable register /
bogdanm	20:4263a77256ae	803	__O uint32_t SET_EN; /!< Interrupt set enable register /
bogdanm	20:4263a77256ae	804	__I uint32_t STATUS; /!< Status register /
bogdanm	20:4263a77256ae	805	__I uint32_t ENABLE; /!< Enable register /
bogdanm	20:4263a77256ae	806	__O uint32_t CLR_STAT; /!< Clear register /
bogdanm	20:4263a77256ae	807	__O uint32_t SET_STAT; /!< Set register /
bogdanm	20:4263a77256ae	808	} LPC_ATIMER_T;
bogdanm	20:4263a77256ae	809
bogdanm	20:4263a77256ae	810	/**
bogdanm	20:4263a77256ae	811	* @brief Register File register block structure
bogdanm	20:4263a77256ae	812	*/
bogdanm	20:4263a77256ae	813	#define LPC_REGFILE_BASE 0x40041000
bogdanm	20:4263a77256ae	814
bogdanm	20:4263a77256ae	815	typedef struct {
bogdanm	20:4263a77256ae	816	__IO uint32_t REGFILE[64]; /!< General purpose storage register /
bogdanm	20:4263a77256ae	817	} LPC_REGFILE_T;
bogdanm	20:4263a77256ae	818
bogdanm	20:4263a77256ae	819	/**
bogdanm	20:4263a77256ae	820	* @brief Power Management Controller register block structure
bogdanm	20:4263a77256ae	821	*/
bogdanm	20:4263a77256ae	822	#define LPC_PMC_BASE 0x40042000
bogdanm	20:4263a77256ae	823
bogdanm	20:4263a77256ae	824	typedef struct { /!< PMC Structure /
bogdanm	20:4263a77256ae	825	__IO uint32_t PD0_SLEEP0_HW_ENA; /!< Hardware sleep event enable register /
bogdanm	20:4263a77256ae	826	__I uint32_t RESERVED0[6];
bogdanm	20:4263a77256ae	827	__IO uint32_t PD0_SLEEP0_MODE; /!< Sleep power mode register /
bogdanm	20:4263a77256ae	828	} LPC_PMC_T;
bogdanm	20:4263a77256ae	829
bogdanm	20:4263a77256ae	830	/**
bogdanm	20:4263a77256ae	831	* @brief CREG Register Block
bogdanm	20:4263a77256ae	832	*/
bogdanm	20:4263a77256ae	833	#define LPC_CREG_BASE 0x40043000
bogdanm	20:4263a77256ae	834
bogdanm	20:4263a77256ae	835	typedef struct { /!< CREG Structure /
bogdanm	20:4263a77256ae	836	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	837	__IO uint32_t CREG0; /!< Chip configuration register 32 kHz oscillator output and BOD control register. /
bogdanm	20:4263a77256ae	838	__I uint32_t RESERVED1[62];
bogdanm	20:4263a77256ae	839	__IO uint32_t MXMEMMAP; /!< ARM Cortex-M3/M4 memory mapping /
bogdanm	20:4263a77256ae	840	#if defined(CHIP_LPC18XX)
bogdanm	20:4263a77256ae	841	__I uint32_t RESERVED2[5];
bogdanm	20:4263a77256ae	842	#else
bogdanm	20:4263a77256ae	843	__I uint32_t RESERVED2;
bogdanm	20:4263a77256ae	844	__I uint32_t CREG1; /!< Configuration Register 1 /
bogdanm	20:4263a77256ae	845	__I uint32_t CREG2; /!< Configuration Register 2 /
bogdanm	20:4263a77256ae	846	__I uint32_t CREG3; /!< Configuration Register 3 /
bogdanm	20:4263a77256ae	847	__I uint32_t CREG4; /!< Configuration Register 4 /
bogdanm	20:4263a77256ae	848	#endif
bogdanm	20:4263a77256ae	849	__IO uint32_t CREG5; /!< Chip configuration register 5. Controls JTAG access. /
bogdanm	20:4263a77256ae	850	__IO uint32_t DMAMUX; /!< DMA muxing control /
bogdanm	20:4263a77256ae	851	__IO uint32_t FLASHCFGA; /!< Flash accelerator configuration register for flash bank A /
bogdanm	20:4263a77256ae	852	__IO uint32_t FLASHCFGB; /!< Flash accelerator configuration register for flash bank B /
bogdanm	20:4263a77256ae	853	__IO uint32_t ETBCFG; /!< ETB RAM configuration /
bogdanm	20:4263a77256ae	854	__IO uint32_t CREG6; /!< Chip configuration register 6. /
bogdanm	20:4263a77256ae	855	#if defined(CHIP_LPC18XX)
bogdanm	20:4263a77256ae	856	__I uint32_t RESERVED4[52];
bogdanm	20:4263a77256ae	857	#else
bogdanm	20:4263a77256ae	858	__IO uint32_t M4TXEVENT; /!< M4 IPC event register /
bogdanm	20:4263a77256ae	859	__I uint32_t RESERVED4[51];
bogdanm	20:4263a77256ae	860	#endif
bogdanm	20:4263a77256ae	861	__I uint32_t CHIPID; /!< Part ID /
bogdanm	20:4263a77256ae	862	#if defined(CHIP_LPC18XX)
bogdanm	20:4263a77256ae	863	__I uint32_t RESERVED5[191];
bogdanm	20:4263a77256ae	864	#else
bogdanm	20:4263a77256ae	865	__I uint32_t RESERVED5[127];
bogdanm	20:4263a77256ae	866	__IO uint32_t M0TXEVENT; /!< M0 IPC Event register /
bogdanm	20:4263a77256ae	867	__IO uint32_t M0APPMEMMAP; /!< ARM Cortex M0 memory mapping /
bogdanm	20:4263a77256ae	868	__I uint32_t RESERVED6[62];
bogdanm	20:4263a77256ae	869	#endif
bogdanm	20:4263a77256ae	870	__IO uint32_t USB0FLADJ; /!< USB0 frame length adjust register /
bogdanm	20:4263a77256ae	871	__I uint32_t RESERVED7[63];
bogdanm	20:4263a77256ae	872	__IO uint32_t USB1FLADJ; /!< USB1 frame length adjust register /
bogdanm	20:4263a77256ae	873	} LPC_CREG_T;
bogdanm	20:4263a77256ae	874
bogdanm	20:4263a77256ae	875	/**
bogdanm	20:4263a77256ae	876	* @brief Event Router register structure
bogdanm	20:4263a77256ae	877	*/
bogdanm	20:4263a77256ae	878	#define LPC_EVRT_BASE 0x40044000
bogdanm	20:4263a77256ae	879
bogdanm	20:4263a77256ae	880	typedef struct { /!< EVENTROUTER Structure /
bogdanm	20:4263a77256ae	881	__IO uint32_t HILO; /!< Level configuration register /
bogdanm	20:4263a77256ae	882	__IO uint32_t EDGE; /!< Edge configuration /
bogdanm	20:4263a77256ae	883	__I uint32_t RESERVED0[1012];
bogdanm	20:4263a77256ae	884	__O uint32_t CLR_EN; /!< Event clear enable register /
bogdanm	20:4263a77256ae	885	__O uint32_t SET_EN; /!< Event set enable register /
bogdanm	20:4263a77256ae	886	__I uint32_t STATUS; /!< Status register /
bogdanm	20:4263a77256ae	887	__I uint32_t ENABLE; /!< Enable register /
bogdanm	20:4263a77256ae	888	__O uint32_t CLR_STAT; /!< Clear register /
bogdanm	20:4263a77256ae	889	__O uint32_t SET_STAT; /!< Set register /
bogdanm	20:4263a77256ae	890	} LPC_EVRT_T;
bogdanm	20:4263a77256ae	891
bogdanm	20:4263a77256ae	892	/**
bogdanm	20:4263a77256ae	893	* @brief Real Time Clock register block structure
bogdanm	20:4263a77256ae	894	*/
bogdanm	20:4263a77256ae	895	#define LPC_RTC_BASE 0x40046000
bogdanm	20:4263a77256ae	896	#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
bogdanm	20:4263a77256ae	897
bogdanm	20:4263a77256ae	898	typedef enum IP_RTC_TIMEINDEX {
bogdanm	20:4263a77256ae	899	RTC_TIMETYPE_SECOND, /!< Second /
bogdanm	20:4263a77256ae	900	RTC_TIMETYPE_MINUTE, /!< Month /
bogdanm	20:4263a77256ae	901	RTC_TIMETYPE_HOUR, /!< Hour /
bogdanm	20:4263a77256ae	902	RTC_TIMETYPE_DAYOFMONTH, /!< Day of month /
bogdanm	20:4263a77256ae	903	RTC_TIMETYPE_DAYOFWEEK, /!< Day of week /
bogdanm	20:4263a77256ae	904	RTC_TIMETYPE_DAYOFYEAR, /!< Day of year /
bogdanm	20:4263a77256ae	905	RTC_TIMETYPE_MONTH, /!< Month /
bogdanm	20:4263a77256ae	906	RTC_TIMETYPE_YEAR, /!< Year /
bogdanm	20:4263a77256ae	907	RTC_TIMETYPE_LAST
bogdanm	20:4263a77256ae	908	} IP_RTC_TIMEINDEX_T;
bogdanm	20:4263a77256ae	909
bogdanm	20:4263a77256ae	910	#if RTC_EV_SUPPORT
bogdanm	20:4263a77256ae	911	typedef enum LPC_RTC_EV_CHANNEL {
bogdanm	20:4263a77256ae	912	RTC_EV_CHANNEL_1 = 0,
bogdanm	20:4263a77256ae	913	RTC_EV_CHANNEL_2,
bogdanm	20:4263a77256ae	914	RTC_EV_CHANNEL_3,
bogdanm	20:4263a77256ae	915	RTC_EV_CHANNEL_NUM,
bogdanm	20:4263a77256ae	916	} LPC_RTC_EV_CHANNEL_T;
bogdanm	20:4263a77256ae	917	#endif /RTC_EV_SUPPORT/
bogdanm	20:4263a77256ae	918
bogdanm	20:4263a77256ae	919	typedef struct { /!< RTC Structure /
bogdanm	20:4263a77256ae	920	__IO uint32_t ILR; /!< Interrupt Location Register /
bogdanm	20:4263a77256ae	921	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	922	__IO uint32_t CCR; /!< Clock Control Register /
bogdanm	20:4263a77256ae	923	__IO uint32_t CIIR; /!< Counter Increment Interrupt Register /
bogdanm	20:4263a77256ae	924	__IO uint32_t AMR; /!< Alarm Mask Register /
bogdanm	20:4263a77256ae	925	__I uint32_t CTIME[3]; /!< Consolidated Time Register 0,1,2 /
bogdanm	20:4263a77256ae	926	__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /!< Timer field registers /
bogdanm	20:4263a77256ae	927	__IO uint32_t CALIBRATION; /!< Calibration Value Register /
bogdanm	20:4263a77256ae	928	__I uint32_t RESERVED1[7];
bogdanm	20:4263a77256ae	929	__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /!< Alarm field registers /
bogdanm	20:4263a77256ae	930	#if RTC_EV_SUPPORT
bogdanm	20:4263a77256ae	931	__IO uint32_t ERSTATUS; /!< Event Monitor/Recorder Status register/
bogdanm	20:4263a77256ae	932	__IO uint32_t ERCONTROL; /!< Event Monitor/Recorder Control register/
bogdanm	20:4263a77256ae	933	__I uint32_t ERCOUNTERS; /!< Event Monitor/Recorder Counters register/
bogdanm	20:4263a77256ae	934	__I uint32_t RESERVED2;
bogdanm	20:4263a77256ae	935	__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /!<Event Monitor/Recorder First Stamp registers/
bogdanm	20:4263a77256ae	936	__I uint32_t RESERVED3;
bogdanm	20:4263a77256ae	937	__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /!<Event Monitor/Recorder Last Stamp registers/
bogdanm	20:4263a77256ae	938	#endif /RTC_EV_SUPPORT/
bogdanm	20:4263a77256ae	939	} LPC_RTC_T;
bogdanm	20:4263a77256ae	940
bogdanm	20:4263a77256ae	941	/**
bogdanm	20:4263a77256ae	942	* @brief LPC18XX/43XX CGU register block structure
bogdanm	20:4263a77256ae	943	*/
bogdanm	20:4263a77256ae	944	#define LPC_CGU_BASE 0x40050000
bogdanm	20:4263a77256ae	945	#define LPC_CCU1_BASE 0x40051000
bogdanm	20:4263a77256ae	946	#define LPC_CCU2_BASE 0x40052000
bogdanm	20:4263a77256ae	947	/**
bogdanm	20:4263a77256ae	948	* These are possible input clocks for the CGU and can come
bogdanm	20:4263a77256ae	949	* from both external (crystal) and internal (PLL) sources. These
bogdanm	20:4263a77256ae	950	* clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T).
bogdanm	20:4263a77256ae	951	*/
bogdanm	20:4263a77256ae	952	typedef enum CGU_CLKIN {
bogdanm	20:4263a77256ae	953	CLKIN_32K, /!< External 32KHz input /
bogdanm	20:4263a77256ae	954	CLKIN_IRC, /!< Internal IRC (12MHz) input /
bogdanm	20:4263a77256ae	955	CLKIN_ENET_RX, /!< External ENET_RX pin input /
bogdanm	20:4263a77256ae	956	CLKIN_ENET_TX, /!< External ENET_TX pin input /
bogdanm	20:4263a77256ae	957	CLKIN_CLKIN, /!< External GPCLKIN pin input /
bogdanm	20:4263a77256ae	958	CLKIN_RESERVED1,
bogdanm	20:4263a77256ae	959	CLKIN_CRYSTAL, /!< External (main) crystal pin input /
bogdanm	20:4263a77256ae	960	CLKIN_USBPLL, /!< Internal USB PLL input /
bogdanm	20:4263a77256ae	961	CLKIN_AUDIOPLL, /!< Internal Audio PLL input /
bogdanm	20:4263a77256ae	962	CLKIN_MAINPLL, /!< Internal Main PLL input /
bogdanm	20:4263a77256ae	963	CLKIN_RESERVED2,
bogdanm	20:4263a77256ae	964	CLKIN_RESERVED3,
bogdanm	20:4263a77256ae	965	CLKIN_IDIVA, /!< Internal divider A input /
bogdanm	20:4263a77256ae	966	CLKIN_IDIVB, /!< Internal divider B input /
bogdanm	20:4263a77256ae	967	CLKIN_IDIVC, /!< Internal divider C input /
bogdanm	20:4263a77256ae	968	CLKIN_IDIVD, /!< Internal divider D input /
bogdanm	20:4263a77256ae	969	CLKIN_IDIVE, /!< Internal divider E input /
bogdanm	20:4263a77256ae	970	CLKINPUT_PD /!< External 32KHz input /
bogdanm	20:4263a77256ae	971	} CGU_CLKIN_T;
bogdanm	20:4263a77256ae	972
bogdanm	20:4263a77256ae	973	#define CLKIN_PLL0USB CLKIN_USBPLL
bogdanm	20:4263a77256ae	974	#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
bogdanm	20:4263a77256ae	975	#define CLKIN_PLL1 CLKIN_MAINPLL
bogdanm	20:4263a77256ae	976
bogdanm	20:4263a77256ae	977	/**
bogdanm	20:4263a77256ae	978	* CGU base clocks are clocks that are associated with a single input clock
bogdanm	20:4263a77256ae	979	* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
bogdanm	20:4263a77256ae	980	* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
bogdanm	20:4263a77256ae	981	* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
bogdanm	20:4263a77256ae	982	* CLK_PERIPH_SGPIO periphral clocks.
bogdanm	20:4263a77256ae	983	*/
bogdanm	20:4263a77256ae	984	typedef enum CGU_BASE_CLK {
bogdanm	20:4263a77256ae	985	CLK_BASE_SAFE, /!< Base clock for WDT oscillator, IRC input only /
bogdanm	20:4263a77256ae	986	CLK_BASE_USB0, /!< Base USB clock for USB0, USB PLL input only /
bogdanm	20:4263a77256ae	987	#if defined(CHIP_LPC43XX)
bogdanm	20:4263a77256ae	988	CLK_BASE_PERIPH, /!< Base clock for SGPIO /
bogdanm	20:4263a77256ae	989	#else
bogdanm	20:4263a77256ae	990	CLK_BASE_RESERVED1,
bogdanm	20:4263a77256ae	991	#endif
bogdanm	20:4263a77256ae	992	CLK_BASE_USB1, /!< Base USB clock for USB1 /
bogdanm	20:4263a77256ae	993	CLK_BASE_MX, /!< Base clock for CPU core /
bogdanm	20:4263a77256ae	994	CLK_BASE_SPIFI, /!< Base clock for SPIFI /
bogdanm	20:4263a77256ae	995	#if defined(CHIP_LPC43XX)
bogdanm	20:4263a77256ae	996	CLK_BASE_SPI, /!< Base clock for SPI /
bogdanm	20:4263a77256ae	997	#else
bogdanm	20:4263a77256ae	998	CLK_BASE_RESERVED2,
bogdanm	20:4263a77256ae	999	#endif
bogdanm	20:4263a77256ae	1000	CLK_BASE_PHY_RX, /!< Base clock for PHY RX /
bogdanm	20:4263a77256ae	1001	CLK_BASE_PHY_TX, /!< Base clock for PHY TX /
bogdanm	20:4263a77256ae	1002	CLK_BASE_APB1, /!< Base clock for APB1 group /
bogdanm	20:4263a77256ae	1003	CLK_BASE_APB3, /!< Base clock for APB3 group /
bogdanm	20:4263a77256ae	1004	CLK_BASE_LCD, /!< Base clock for LCD pixel clock /
bogdanm	20:4263a77256ae	1005	#if defined(CHIP_LPC43XX)
bogdanm	20:4263a77256ae	1006	CLK_BASE_VADC, /!< Base clock for VADC /
bogdanm	20:4263a77256ae	1007	#else
bogdanm	20:4263a77256ae	1008	CLK_BASE_RESERVED3,
bogdanm	20:4263a77256ae	1009	#endif
bogdanm	20:4263a77256ae	1010	CLK_BASE_SDIO, /!< Base clock for SDIO /
bogdanm	20:4263a77256ae	1011	CLK_BASE_SSP0, /!< Base clock for SSP0 /
bogdanm	20:4263a77256ae	1012	CLK_BASE_SSP1, /!< Base clock for SSP1 /
bogdanm	20:4263a77256ae	1013	CLK_BASE_UART0, /!< Base clock for UART0 /
bogdanm	20:4263a77256ae	1014	CLK_BASE_UART1, /!< Base clock for UART1 /
bogdanm	20:4263a77256ae	1015	CLK_BASE_UART2, /!< Base clock for UART2 /
bogdanm	20:4263a77256ae	1016	CLK_BASE_UART3, /!< Base clock for UART3 /
bogdanm	20:4263a77256ae	1017	CLK_BASE_OUT, /!< Base clock for CLKOUT pin /
bogdanm	20:4263a77256ae	1018	CLK_BASE_RESERVED4,
bogdanm	20:4263a77256ae	1019	CLK_BASE_RESERVED5,
bogdanm	20:4263a77256ae	1020	CLK_BASE_RESERVED6,
bogdanm	20:4263a77256ae	1021	CLK_BASE_RESERVED7,
bogdanm	20:4263a77256ae	1022	CLK_BASE_APLL, /!< Base clock for audio PLL /
bogdanm	20:4263a77256ae	1023	CLK_BASE_CGU_OUT0, /!< Base clock for CGUOUT0 pin /
bogdanm	20:4263a77256ae	1024	CLK_BASE_CGU_OUT1, /!< Base clock for CGUOUT1 pin /
bogdanm	20:4263a77256ae	1025	CLK_BASE_LAST,
bogdanm	20:4263a77256ae	1026	CLK_BASE_NONE = CLK_BASE_LAST
bogdanm	20:4263a77256ae	1027	} CGU_BASE_CLK_T;
bogdanm	20:4263a77256ae	1028
bogdanm	20:4263a77256ae	1029	/**
bogdanm	20:4263a77256ae	1030	* CGU dividers provide an extra clock state where a specific clock can be
bogdanm	20:4263a77256ae	1031	* divided before being routed to a peripheral group. A divider accepts an
bogdanm	20:4263a77256ae	1032	* input clock and then divides it. To use the divided clock for a base clock
bogdanm	20:4263a77256ae	1033	* group, use the divider as the input clock for the base clock (for example,
bogdanm	20:4263a77256ae	1034	* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
bogdanm	20:4263a77256ae	1035	*/
bogdanm	20:4263a77256ae	1036	typedef enum CGU_IDIV {
bogdanm	20:4263a77256ae	1037	CLK_IDIV_A, /!< CGU clock divider A /
bogdanm	20:4263a77256ae	1038	CLK_IDIV_B, /!< CGU clock divider B /
bogdanm	20:4263a77256ae	1039	CLK_IDIV_C, /!< CGU clock divider A /
bogdanm	20:4263a77256ae	1040	CLK_IDIV_D, /!< CGU clock divider D /
bogdanm	20:4263a77256ae	1041	CLK_IDIV_E, /!< CGU clock divider E /
bogdanm	20:4263a77256ae	1042	CLK_IDIV_LAST
bogdanm	20:4263a77256ae	1043	} CGU_IDIV_T;
bogdanm	20:4263a77256ae	1044
bogdanm	20:4263a77256ae	1045	/**
bogdanm	20:4263a77256ae	1046	* Peripheral clocks are individual clocks routed to peripherals. Although
bogdanm	20:4263a77256ae	1047	* multiple peripherals may share a same base clock, each peripheral's clock
bogdanm	20:4263a77256ae	1048	* can be enabled or disabled individually. Some peripheral clocks also have
bogdanm	20:4263a77256ae	1049	* additional dividers associated with them.
bogdanm	20:4263a77256ae	1050	*/
bogdanm	20:4263a77256ae	1051	typedef enum CCU_CLK {
bogdanm	20:4263a77256ae	1052	/* CCU1 clocks */
bogdanm	20:4263a77256ae	1053	CLK_APB3_BUS, /!< APB3 bus clock from base clock CLK_BASE_APB3 /
bogdanm	20:4263a77256ae	1054	CLK_APB3_I2C1, /!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 /
bogdanm	20:4263a77256ae	1055	CLK_APB3_DAC, /!< DAC peripheral clock from base clock CLK_BASE_APB3 /
bogdanm	20:4263a77256ae	1056	CLK_APB3_ADC0, /!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 /
bogdanm	20:4263a77256ae	1057	CLK_APB3_ADC1, /!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 /
bogdanm	20:4263a77256ae	1058	CLK_APB3_CAN0, /!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 /
bogdanm	20:4263a77256ae	1059	CLK_APB1_BUS = 32, /!< APB1 bus clock clock from base clock CLK_BASE_APB1 /
bogdanm	20:4263a77256ae	1060	CLK_APB1_MOTOCON, /!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 /
bogdanm	20:4263a77256ae	1061	CLK_APB1_I2C0, /!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 /
bogdanm	20:4263a77256ae	1062	CLK_APB1_I2S, /!< I2S register/perigheral clock from base clock CLK_BASE_APB1 /
bogdanm	20:4263a77256ae	1063	CLK_APB1_CAN1, /!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 /
bogdanm	20:4263a77256ae	1064	CLK_SPIFI = 64, /!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI /
bogdanm	20:4263a77256ae	1065	CLK_MX_BUS = 96, /!< M3/M4 BUS core clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1066	CLK_MX_SPIFI, /!< SPIFI register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1067	CLK_MX_GPIO, /!< GPIO register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1068	CLK_MX_LCD, /!< LCD register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1069	CLK_MX_ETHERNET, /!< ETHERNET register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1070	CLK_MX_USB0, /!< USB0 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1071	CLK_MX_EMC, /!< EMC clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1072	CLK_MX_SDIO, /!< SDIO register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1073	CLK_MX_DMA, /!< DMA register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1074	CLK_MX_MXCORE, /!< M3/M4 CPU core clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1075	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
bogdanm	20:4263a77256ae	1076	CLK_MX_SCT, /!< SCT register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1077	CLK_MX_USB1, /!< USB1 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1078	CLK_MX_EMC_DIV, /!< ENC divider clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1079	CLK_MX_FLASHA, /!< FLASHA bank clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1080	CLK_MX_FLASHB, /!< FLASHB bank clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1081	#if defined(CHIP_LPC43XX)
bogdanm	20:4263a77256ae	1082	CLK_M4_M0APP, /!< M0 app CPU core clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1083	CLK_MX_VADC, /!< VADC clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1084	#else
bogdanm	20:4263a77256ae	1085	CLK_RESERVED1,
bogdanm	20:4263a77256ae	1086	CLK_RESERVED2,
bogdanm	20:4263a77256ae	1087	#endif
bogdanm	20:4263a77256ae	1088	CLK_MX_EEPROM, /!< EEPROM clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1089	CLK_MX_WWDT = 128, /!< WWDT register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1090	CLK_MX_UART0, /!< UART0 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1091	CLK_MX_UART1, /!< UART1 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1092	CLK_MX_SSP0, /!< SSP0 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1093	CLK_MX_TIMER0, /!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1094	CLK_MX_TIMER1, /!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1095	CLK_MX_SCU, /!< SCU register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1096	CLK_MX_CREG, /!< CREG clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1097	CLK_MX_RITIMER = 160, /!< RITIMER register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1098	CLK_MX_UART2, /!< UART3 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1099	CLK_MX_UART3, /!< UART4 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1100	CLK_MX_TIMER2, /!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1101	CLK_MX_TIMER3, /!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1102	CLK_MX_SSP1, /!< SSP1 register clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1103	CLK_MX_QEI, /!< QEI register/perigheral clock from base clock CLK_BASE_MX /
bogdanm	20:4263a77256ae	1104	#if defined(CHIP_LPC43XX)
bogdanm	20:4263a77256ae	1105	CLK_PERIPH_BUS = 192, /!< Peripheral bus clock from base clock CLK_BASE_PERIPH /
bogdanm	20:4263a77256ae	1106	CLK_RESERVED3,
bogdanm	20:4263a77256ae	1107	CLK_PERIPH_CORE, /!< Peripheral core clock from base clock CLK_BASE_PERIPH /
bogdanm	20:4263a77256ae	1108	CLK_PERIPH_SGPIO, /!< SGPIO clock from base clock CLK_BASE_PERIPH /
bogdanm	20:4263a77256ae	1109	#else
bogdanm	20:4263a77256ae	1110	CLK_RESERVED3 = 192,
bogdanm	20:4263a77256ae	1111	CLK_RESERVED3A,
bogdanm	20:4263a77256ae	1112	CLK_RESERVED4,
bogdanm	20:4263a77256ae	1113	CLK_RESERVED5,
bogdanm	20:4263a77256ae	1114	#endif
bogdanm	20:4263a77256ae	1115	CLK_USB0 = 224, /!< USB0 clock from base clock CLK_BASE_USB0 /
bogdanm	20:4263a77256ae	1116	CLK_USB1 = 256, /!< USB1 clock from base clock CLK_BASE_USB1 /
bogdanm	20:4263a77256ae	1117	#if defined(CHIP_LPC43XX)
bogdanm	20:4263a77256ae	1118	CLK_SPI = 288, /!< SPI clock from base clock CLK_BASE_SPI /
bogdanm	20:4263a77256ae	1119	CLK_VADC, /!< VADC clock from base clock CLK_BASE_VADC /
bogdanm	20:4263a77256ae	1120	#else
bogdanm	20:4263a77256ae	1121	CLK_RESERVED7 = 320,
bogdanm	20:4263a77256ae	1122	CLK_RESERVED8,
bogdanm	20:4263a77256ae	1123	#endif
bogdanm	20:4263a77256ae	1124	CLK_CCU1_LAST,
bogdanm	20:4263a77256ae	1125
bogdanm	20:4263a77256ae	1126	/* CCU2 clocks */
bogdanm	20:4263a77256ae	1127	CLK_CCU2_START,
bogdanm	20:4263a77256ae	1128	CLK_APLL = CLK_CCU2_START, /!< Audio PLL clock from base clock CLK_BASE_APLL /
bogdanm	20:4263a77256ae	1129	RESERVED_ALIGNB = CLK_CCU2_START + 31,
bogdanm	20:4263a77256ae	1130	CLK_APB2_UART3, /!< UART3 clock from base clock CLK_BASE_UART3 /
bogdanm	20:4263a77256ae	1131	RESERVED_ALIGNC = CLK_CCU2_START + 63,
bogdanm	20:4263a77256ae	1132	CLK_APB2_UART2, /!< UART2 clock from base clock CLK_BASE_UART2 /
bogdanm	20:4263a77256ae	1133	RESERVED_ALIGND = CLK_CCU2_START + 95,
bogdanm	20:4263a77256ae	1134	CLK_APB0_UART1, /!< UART1 clock from base clock CLK_BASE_UART1 /
bogdanm	20:4263a77256ae	1135	RESERVED_ALIGNE = CLK_CCU2_START + 127,
bogdanm	20:4263a77256ae	1136	CLK_APB0_UART0, /!< UART0 clock from base clock CLK_BASE_UART0 /
bogdanm	20:4263a77256ae	1137	RESERVED_ALIGNF = CLK_CCU2_START + 159,
bogdanm	20:4263a77256ae	1138	CLK_APB2_SSP1, /!< SSP1 clock from base clock CLK_BASE_SSP1 /
bogdanm	20:4263a77256ae	1139	RESERVED_ALIGNG = CLK_CCU2_START + 191,
bogdanm	20:4263a77256ae	1140	CLK_APB0_SSP0, /!< SSP0 clock from base clock CLK_BASE_SSP0 /
bogdanm	20:4263a77256ae	1141	RESERVED_ALIGNH = CLK_CCU2_START + 223,
bogdanm	20:4263a77256ae	1142	CLK_APB2_SDIO, /!< SDIO clock from base clock CLK_BASE_SDIO /
bogdanm	20:4263a77256ae	1143	CLK_CCU2_LAST
bogdanm	20:4263a77256ae	1144	} CCU_CLK_T;
bogdanm	20:4263a77256ae	1145
bogdanm	20:4263a77256ae	1146	/**
bogdanm	20:4263a77256ae	1147	* Audio or USB PLL selection
bogdanm	20:4263a77256ae	1148	*/
bogdanm	20:4263a77256ae	1149	typedef enum CHIP_CGU_USB_AUDIO_PLL {
bogdanm	20:4263a77256ae	1150	CGU_USB_PLL,
bogdanm	20:4263a77256ae	1151	CGU_AUDIO_PLL
bogdanm	20:4263a77256ae	1152	} CHIP_CGU_USB_AUDIO_PLL_T;
bogdanm	20:4263a77256ae	1153
bogdanm	20:4263a77256ae	1154	/**
bogdanm	20:4263a77256ae	1155	* PLL register block
bogdanm	20:4263a77256ae	1156	*/
bogdanm	20:4263a77256ae	1157	typedef struct {
bogdanm	20:4263a77256ae	1158	__I uint32_t PLL_STAT; /!< PLL status register /
bogdanm	20:4263a77256ae	1159	__IO uint32_t PLL_CTRL; /!< PLL control register /
bogdanm	20:4263a77256ae	1160	__IO uint32_t PLL_MDIV; /!< PLL M-divider register /
bogdanm	20:4263a77256ae	1161	__IO uint32_t PLL_NP_DIV; /!< PLL N/P-divider register /
bogdanm	20:4263a77256ae	1162	} CGU_PLL_REG_T;
bogdanm	20:4263a77256ae	1163
bogdanm	20:4263a77256ae	1164	typedef struct { /!< (@ 0x40050000) CGU Structure /
bogdanm	20:4263a77256ae	1165	__I uint32_t RESERVED0[5];
bogdanm	20:4263a77256ae	1166	__IO uint32_t FREQ_MON; /!< (@ 0x40050014) Frequency monitor register /
bogdanm	20:4263a77256ae	1167	__IO uint32_t XTAL_OSC_CTRL; /!< (@ 0x40050018) Crystal oscillator control register /
bogdanm	20:4263a77256ae	1168	CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /!< (@ 0x4005001C) USB and audio PLL blocks /
bogdanm	20:4263a77256ae	1169	__IO uint32_t PLL0AUDIO_FRAC; /!< (@ 0x4005003C) PLL0 (audio) /
bogdanm	20:4263a77256ae	1170	__I uint32_t PLL1_STAT; /!< (@ 0x40050040) PLL1 status register /
bogdanm	20:4263a77256ae	1171	__IO uint32_t PLL1_CTRL; /!< (@ 0x40050044) PLL1 control register /
bogdanm	20:4263a77256ae	1172	__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/!< (@ 0x40050048) Integer divider A-E control registers /
bogdanm	20:4263a77256ae	1173	__IO uint32_t BASE_CLK[CLK_BASE_LAST]; /!< (@ 0x4005005C) Start of base clock registers /
bogdanm	20:4263a77256ae	1174	} LPC_CGU_T;
bogdanm	20:4263a77256ae	1175
bogdanm	20:4263a77256ae	1176	/**
bogdanm	20:4263a77256ae	1177	* @brief CCU clock config/status register pair
bogdanm	20:4263a77256ae	1178	*/
bogdanm	20:4263a77256ae	1179	typedef struct {
bogdanm	20:4263a77256ae	1180	__IO uint32_t CFG; /!< CCU clock configuration register /
bogdanm	20:4263a77256ae	1181	__I uint32_t STAT; /!< CCU clock status register /
bogdanm	20:4263a77256ae	1182	} CCU_CFGSTAT_T;
bogdanm	20:4263a77256ae	1183
bogdanm	20:4263a77256ae	1184	/**
bogdanm	20:4263a77256ae	1185	* @brief CCU1 register block structure
bogdanm	20:4263a77256ae	1186	*/
bogdanm	20:4263a77256ae	1187	typedef struct { /!< (@ 0x40051000) CCU1 Structure /
bogdanm	20:4263a77256ae	1188	__IO uint32_t PM; /!< (@ 0x40051000) CCU1 power mode register /
bogdanm	20:4263a77256ae	1189	__I uint32_t BASE_STAT; /!< (@ 0x40051004) CCU1 base clocks status register /
bogdanm	20:4263a77256ae	1190	__I uint32_t RESERVED0[62];
bogdanm	20:4263a77256ae	1191	CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /!< (@ 0x40051100) Start of CCU1 clock registers /
bogdanm	20:4263a77256ae	1192	} LPC_CCU1_T;
bogdanm	20:4263a77256ae	1193
bogdanm	20:4263a77256ae	1194	/**
bogdanm	20:4263a77256ae	1195	* @brief CCU2 register block structure
bogdanm	20:4263a77256ae	1196	*/
bogdanm	20:4263a77256ae	1197	typedef struct { /!< (@ 0x40052000) CCU2 Structure /
bogdanm	20:4263a77256ae	1198	__IO uint32_t PM; /!< (@ 0x40052000) Power mode register /
bogdanm	20:4263a77256ae	1199	__I uint32_t BASE_STAT; /!< (@ 0x40052004) CCU base clocks status register /
bogdanm	20:4263a77256ae	1200	__I uint32_t RESERVED0[62];
bogdanm	20:4263a77256ae	1201	CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /!< (@ 0x40052100) Start of CCU2 clock registers /
bogdanm	20:4263a77256ae	1202	} LPC_CCU2_T;
bogdanm	20:4263a77256ae	1203
bogdanm	20:4263a77256ae	1204	/**
bogdanm	20:4263a77256ae	1205	* @brief RGU register structure
bogdanm	20:4263a77256ae	1206	*/
bogdanm	20:4263a77256ae	1207	#define LPC_RGU_BASE 0x40053000
bogdanm	20:4263a77256ae	1208
bogdanm	20:4263a77256ae	1209	typedef enum CHIP_RGU_RST {
bogdanm	20:4263a77256ae	1210	RGU_CORE_RST,
bogdanm	20:4263a77256ae	1211	RGU_PERIPH_RST,
bogdanm	20:4263a77256ae	1212	RGU_MASTER_RST,
bogdanm	20:4263a77256ae	1213	RGU_WWDT_RST = 4,
bogdanm	20:4263a77256ae	1214	RGU_CREG_RST,
bogdanm	20:4263a77256ae	1215	RGU_BUS_RST = 8,
bogdanm	20:4263a77256ae	1216	RGU_SCU_RST,
bogdanm	20:4263a77256ae	1217	RGU_M3_RST = 13,
bogdanm	20:4263a77256ae	1218	RGU_LCD_RST = 16,
bogdanm	20:4263a77256ae	1219	RGU_USB0_RST,
bogdanm	20:4263a77256ae	1220	RGU_USB1_RST,
bogdanm	20:4263a77256ae	1221	RGU_DMA_RST,
bogdanm	20:4263a77256ae	1222	RGU_SDIO_RST,
bogdanm	20:4263a77256ae	1223	RGU_EMC_RST,
bogdanm	20:4263a77256ae	1224	RGU_ETHERNET_RST,
bogdanm	20:4263a77256ae	1225	RGU_FLASHA_RST = 25,
bogdanm	20:4263a77256ae	1226	RGU_EEPROM_RST = 27,
bogdanm	20:4263a77256ae	1227	RGU_GPIO_RST,
bogdanm	20:4263a77256ae	1228	RGU_FLASHB_RST,
bogdanm	20:4263a77256ae	1229	RGU_TIMER0_RST = 32,
bogdanm	20:4263a77256ae	1230	RGU_TIMER1_RST,
bogdanm	20:4263a77256ae	1231	RGU_TIMER2_RST,
bogdanm	20:4263a77256ae	1232	RGU_TIMER3_RST,
bogdanm	20:4263a77256ae	1233	RGU_RITIMER_RST,
bogdanm	20:4263a77256ae	1234	RGU_SCT_RST,
bogdanm	20:4263a77256ae	1235	RGU_MOTOCONPWM_RST,
bogdanm	20:4263a77256ae	1236	RGU_QEI_RST,
bogdanm	20:4263a77256ae	1237	RGU_ADC0_RST,
bogdanm	20:4263a77256ae	1238	RGU_ADC1_RST,
bogdanm	20:4263a77256ae	1239	RGU_DAC_RST,
bogdanm	20:4263a77256ae	1240	RGU_UART0_RST = 44,
bogdanm	20:4263a77256ae	1241	RGU_UART1_RST,
bogdanm	20:4263a77256ae	1242	RGU_UART2_RST,
bogdanm	20:4263a77256ae	1243	RGU_UART3_RST,
bogdanm	20:4263a77256ae	1244	RGU_I2C0_RST,
bogdanm	20:4263a77256ae	1245	RGU_I2C1_RST,
bogdanm	20:4263a77256ae	1246	RGU_SSP0_RST,
bogdanm	20:4263a77256ae	1247	RGU_SSP1_RST,
bogdanm	20:4263a77256ae	1248	RGU_I2S_RST,
bogdanm	20:4263a77256ae	1249	RGU_SPIFI_RST,
bogdanm	20:4263a77256ae	1250	RGU_CAN1_RST,
bogdanm	20:4263a77256ae	1251	RGU_CAN0_RST,
bogdanm	20:4263a77256ae	1252	#ifdef CHIP_LPC43XX
bogdanm	20:4263a77256ae	1253	RGU_M0APP_RST,
bogdanm	20:4263a77256ae	1254	RGU_SGPIO_RST,
bogdanm	20:4263a77256ae	1255	RGU_SPI_RST,
bogdanm	20:4263a77256ae	1256	#endif
bogdanm	20:4263a77256ae	1257	RGU_LAST_RST = 63,
bogdanm	20:4263a77256ae	1258	} CHIP_RGU_RST_T;
bogdanm	20:4263a77256ae	1259
bogdanm	20:4263a77256ae	1260	typedef struct { /!< RGU Structure /
bogdanm	20:4263a77256ae	1261	__I uint32_t RESERVED0[64];
bogdanm	20:4263a77256ae	1262	__O uint32_t RESET_CTRL0; /!< Reset control register 0 /
bogdanm	20:4263a77256ae	1263	__O uint32_t RESET_CTRL1; /!< Reset control register 1 /
bogdanm	20:4263a77256ae	1264	__I uint32_t RESERVED1[2];
bogdanm	20:4263a77256ae	1265	__IO uint32_t RESET_STATUS0; /!< Reset status register 0 /
bogdanm	20:4263a77256ae	1266	__IO uint32_t RESET_STATUS1; /!< Reset status register 1 /
bogdanm	20:4263a77256ae	1267	__IO uint32_t RESET_STATUS2; /!< Reset status register 2 /
bogdanm	20:4263a77256ae	1268	__IO uint32_t RESET_STATUS3; /!< Reset status register 3 /
bogdanm	20:4263a77256ae	1269	__I uint32_t RESERVED2[12];
bogdanm	20:4263a77256ae	1270	__I uint32_t RESET_ACTIVE_STATUS0; /!< Reset active status register 0 /
bogdanm	20:4263a77256ae	1271	__I uint32_t RESET_ACTIVE_STATUS1; /!< Reset active status register 1 /
bogdanm	20:4263a77256ae	1272	__I uint32_t RESERVED3[170];
bogdanm	20:4263a77256ae	1273	__IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/!< Reset external status registers /
bogdanm	20:4263a77256ae	1274	} LPC_RGU_T;
bogdanm	20:4263a77256ae	1275
bogdanm	20:4263a77256ae	1276	/**
bogdanm	20:4263a77256ae	1277	* @brief Windowed Watchdog register block structure
bogdanm	20:4263a77256ae	1278	*/
bogdanm	20:4263a77256ae	1279	#define LPC_WWDT_BASE 0x40080000
bogdanm	20:4263a77256ae	1280
bogdanm	20:4263a77256ae	1281	typedef struct { /!< WWDT Structure /
bogdanm	20:4263a77256ae	1282	__IO uint32_t MOD; /!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. /
bogdanm	20:4263a77256ae	1283	__IO uint32_t TC; /!< Watchdog timer constant register. This register determines the time-out value. /
bogdanm	20:4263a77256ae	1284	__O uint32_t FEED; /!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. /
bogdanm	20:4263a77256ae	1285	__I uint32_t TV; /!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. /
bogdanm	20:4263a77256ae	1286	#ifdef WATCHDOG_CLKSEL_SUPPORT
bogdanm	20:4263a77256ae	1287	__IO uint32_t CLKSEL; /!< Watchdog clock select register. /
bogdanm	20:4263a77256ae	1288	#else
bogdanm	20:4263a77256ae	1289	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	1290	#endif
bogdanm	20:4263a77256ae	1291	#ifdef WATCHDOG_WINDOW_SUPPORT
bogdanm	20:4263a77256ae	1292	__IO uint32_t WARNINT; /!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. /
bogdanm	20:4263a77256ae	1293	__IO uint32_t WINDOW; /!< Watchdog timer window register. This register contains the Watchdog window value. /
bogdanm	20:4263a77256ae	1294	#endif
bogdanm	20:4263a77256ae	1295	} LPC_WWDT_T;
bogdanm	20:4263a77256ae	1296
bogdanm	20:4263a77256ae	1297	/**
bogdanm	20:4263a77256ae	1298	* @brief USART register block structure
bogdanm	20:4263a77256ae	1299	*/
bogdanm	20:4263a77256ae	1300	#define LPC_USART0_BASE 0x40081000
bogdanm	20:4263a77256ae	1301	#define LPC_UART1_BASE 0x40082000
bogdanm	20:4263a77256ae	1302	#define LPC_USART2_BASE 0x400C1000
bogdanm	20:4263a77256ae	1303	#define LPC_USART3_BASE 0x400C2000
bogdanm	20:4263a77256ae	1304
bogdanm	20:4263a77256ae	1305	typedef struct { /!< USARTn Structure /
bogdanm	20:4263a77256ae	1306
bogdanm	20:4263a77256ae	1307	union {
bogdanm	20:4263a77256ae	1308	__IO uint32_t DLL; /!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). /
bogdanm	20:4263a77256ae	1309	__O uint32_t THR; /!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). /
bogdanm	20:4263a77256ae	1310	__I uint32_t RBR; /!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). /
bogdanm	20:4263a77256ae	1311	};
bogdanm	20:4263a77256ae	1312
bogdanm	20:4263a77256ae	1313	union {
bogdanm	20:4263a77256ae	1314	__IO uint32_t IER; /!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). /
bogdanm	20:4263a77256ae	1315	__IO uint32_t DLM; /!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). /
bogdanm	20:4263a77256ae	1316	};
bogdanm	20:4263a77256ae	1317
bogdanm	20:4263a77256ae	1318	union {
bogdanm	20:4263a77256ae	1319	__O uint32_t FCR; /!< FIFO Control Register. Controls UART FIFO usage and modes. /
bogdanm	20:4263a77256ae	1320	__I uint32_t IIR; /!< Interrupt ID Register. Identifies which interrupt(s) are pending. /
bogdanm	20:4263a77256ae	1321	};
bogdanm	20:4263a77256ae	1322
bogdanm	20:4263a77256ae	1323	__IO uint32_t LCR; /!< Line Control Register. Contains controls for frame formatting and break generation. /
bogdanm	20:4263a77256ae	1324	__IO uint32_t MCR; /!< Modem Control Register. Only present on USART ports with full modem support. /
bogdanm	20:4263a77256ae	1325	__I uint32_t LSR; /!< Line Status Register. Contains flags for transmit and receive status, including line errors. /
bogdanm	20:4263a77256ae	1326	__I uint32_t MSR; /!< Modem Status Register. Only present on USART ports with full modem support. /
bogdanm	20:4263a77256ae	1327	__IO uint32_t SCR; /!< Scratch Pad Register. Eight-bit temporary storage for software. /
bogdanm	20:4263a77256ae	1328	__IO uint32_t ACR; /!< Auto-baud Control Register. Contains controls for the auto-baud feature. /
bogdanm	20:4263a77256ae	1329	__IO uint32_t ICR; /!< IrDA control register (not all UARTS) /
bogdanm	20:4263a77256ae	1330	__IO uint32_t FDR; /!< Fractional Divider Register. Generates a clock input for the baud rate divider. /
bogdanm	20:4263a77256ae	1331	__IO uint32_t OSR; /!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. /
bogdanm	20:4263a77256ae	1332	__IO uint32_t TER1; /!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. /
bogdanm	20:4263a77256ae	1333	uint32_t RESERVED0[3];
bogdanm	20:4263a77256ae	1334	__IO uint32_t HDEN; /!< Half-duplex enable Register- only on some UARTs /
bogdanm	20:4263a77256ae	1335	__I uint32_t RESERVED1[1];
bogdanm	20:4263a77256ae	1336	__IO uint32_t SCICTRL; /!< Smart card interface control register- only on some UARTs /
bogdanm	20:4263a77256ae	1337	__IO uint32_t RS485CTRL; /!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. /
bogdanm	20:4263a77256ae	1338	__IO uint32_t RS485ADRMATCH; /!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. /
bogdanm	20:4263a77256ae	1339	__IO uint32_t RS485DLY; /!< RS-485/EIA-485 direction control delay. /
bogdanm	20:4263a77256ae	1340	union {
bogdanm	20:4263a77256ae	1341	__IO uint32_t SYNCCTRL; /!< Synchronous mode control register. Only on USARTs. /
bogdanm	20:4263a77256ae	1342	__I uint32_t FIFOLVL; /!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. /
bogdanm	20:4263a77256ae	1343	};
bogdanm	20:4263a77256ae	1344
bogdanm	20:4263a77256ae	1345	__IO uint32_t TER2; /!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. /
bogdanm	20:4263a77256ae	1346	} LPC_USART_T;
bogdanm	20:4263a77256ae	1347
bogdanm	20:4263a77256ae	1348	/**
bogdanm	20:4263a77256ae	1349	* @brief SSP register block structure
bogdanm	20:4263a77256ae	1350	*/
bogdanm	20:4263a77256ae	1351	#define LPC_SSP0_BASE 0x40083000
bogdanm	20:4263a77256ae	1352	#define LPC_SSP1_BASE 0x400C5000
bogdanm	20:4263a77256ae	1353
bogdanm	20:4263a77256ae	1354	typedef struct { /!< SSPn Structure /
bogdanm	20:4263a77256ae	1355	__IO uint32_t CR0; /!< Control Register 0. Selects the serial clock rate, bus type, and data size. /
bogdanm	20:4263a77256ae	1356	__IO uint32_t CR1; /!< Control Register 1. Selects master/slave and other modes. /
bogdanm	20:4263a77256ae	1357	__IO uint32_t DR; /!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. /
bogdanm	20:4263a77256ae	1358	__I uint32_t SR; /!< Status Register /
bogdanm	20:4263a77256ae	1359	__IO uint32_t CPSR; /!< Clock Prescale Register /
bogdanm	20:4263a77256ae	1360	__IO uint32_t IMSC; /!< Interrupt Mask Set and Clear Register /
bogdanm	20:4263a77256ae	1361	__I uint32_t RIS; /!< Raw Interrupt Status Register /
bogdanm	20:4263a77256ae	1362	__I uint32_t MIS; /!< Masked Interrupt Status Register /
bogdanm	20:4263a77256ae	1363	__O uint32_t ICR; /!< SSPICR Interrupt Clear Register /
bogdanm	20:4263a77256ae	1364	__IO uint32_t DMACR; /!< SSPn DMA control register /
bogdanm	20:4263a77256ae	1365	} LPC_SSP_T;
bogdanm	20:4263a77256ae	1366
bogdanm	20:4263a77256ae	1367	/**
bogdanm	20:4263a77256ae	1368	* @brief 32-bit Standard timer register block structure
bogdanm	20:4263a77256ae	1369	*/
bogdanm	20:4263a77256ae	1370	typedef struct { /!< TIMERn Structure /
bogdanm	20:4263a77256ae	1371	__IO uint32_t IR; /!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. /
bogdanm	20:4263a77256ae	1372	__IO uint32_t TCR; /!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. /
bogdanm	20:4263a77256ae	1373	__IO uint32_t TC; /!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. /
bogdanm	20:4263a77256ae	1374	__IO uint32_t PR; /!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. /
bogdanm	20:4263a77256ae	1375	__IO uint32_t PC; /!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. /
bogdanm	20:4263a77256ae	1376	__IO uint32_t MCR; /!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. /
bogdanm	20:4263a77256ae	1377	__IO uint32_t MR[4]; /!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. /
bogdanm	20:4263a77256ae	1378	__IO uint32_t CCR; /!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. /
bogdanm	20:4263a77256ae	1379	__IO uint32_t CR[4]; /!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. /
bogdanm	20:4263a77256ae	1380	__IO uint32_t EMR; /!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). /
bogdanm	20:4263a77256ae	1381	__I uint32_t RESERVED0[12];
bogdanm	20:4263a77256ae	1382	__IO uint32_t CTCR; /!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. /
bogdanm	20:4263a77256ae	1383	} LPC_TIMER_T;
bogdanm	20:4263a77256ae	1384
bogdanm	20:4263a77256ae	1385	#define LPC_TIMER0_BASE 0x40084000
bogdanm	20:4263a77256ae	1386	#define LPC_TIMER1_BASE 0x40085000
bogdanm	20:4263a77256ae	1387	#define LPC_TIMER2_BASE 0x400C3000
bogdanm	20:4263a77256ae	1388	#define LPC_TIMER3_BASE 0x400C4000
bogdanm	20:4263a77256ae	1389
bogdanm	20:4263a77256ae	1390	/**
bogdanm	20:4263a77256ae	1391	* @brief System Control Unit register block
bogdanm	20:4263a77256ae	1392	*/
bogdanm	20:4263a77256ae	1393	#define LPC_SCU_BASE 0x40086000
bogdanm	20:4263a77256ae	1394
bogdanm	20:4263a77256ae	1395	typedef struct {
bogdanm	20:4263a77256ae	1396	__IO uint32_t SFSP[16][32];
bogdanm	20:4263a77256ae	1397	__I uint32_t RESERVED0[256];
bogdanm	20:4263a77256ae	1398	__IO uint32_t SFSCLK[4]; /!< Pin configuration register for pins CLK0-3 /
bogdanm	20:4263a77256ae	1399	__I uint32_t RESERVED16[28];
bogdanm	20:4263a77256ae	1400	__IO uint32_t SFSUSB; /!< Pin configuration register for USB /
bogdanm	20:4263a77256ae	1401	__IO uint32_t SFSI2C0; /!< Pin configuration register for I2C0-bus pins /
bogdanm	20:4263a77256ae	1402	__IO uint32_t ENAIO[3]; /!< Analog function select registers /
bogdanm	20:4263a77256ae	1403	__I uint32_t RESERVED17[27];
bogdanm	20:4263a77256ae	1404	__IO uint32_t EMCDELAYCLK; /!< EMC clock delay register /
bogdanm	20:4263a77256ae	1405	__I uint32_t RESERVED18[63];
bogdanm	20:4263a77256ae	1406	__IO uint32_t PINTSEL0; /!< Pin interrupt select register for pin interrupts 0 to 3. /
bogdanm	20:4263a77256ae	1407	__IO uint32_t PINTSEL1; /!< Pin interrupt select register for pin interrupts 4 to 7. /
bogdanm	20:4263a77256ae	1408	} LPC_SCU_T;
bogdanm	20:4263a77256ae	1409
bogdanm	20:4263a77256ae	1410	/**
bogdanm	20:4263a77256ae	1411	* SCU function and mode selection definitions
bogdanm	20:4263a77256ae	1412	* See the User Manual for specific modes and functions supoprted by the
bogdanm	20:4263a77256ae	1413	* various LPC18xx/43xx devices. Functionality can vary per device.
bogdanm	20:4263a77256ae	1414	*/
bogdanm	20:4263a77256ae	1415	#define SCU_MODE_MODE_INACT (0x0 << 3) /!< Disable pull-down and pull-up resistor at resistor at pad /
bogdanm	20:4263a77256ae	1416	#define SCU_MODE_MODE_PULLDOWN (0x1 << 3) /!< Enable pull-down resistor at pad /
bogdanm	20:4263a77256ae	1417	#define SCU_MODE_MODE_PULLUP_DIS (0x2 << 3) /!< Disable pull-up resistor at pad /
bogdanm	20:4263a77256ae	1418	#define SCU_MODE_MODE_REPEATER (0x3 << 3) /!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) /
bogdanm	20:4263a77256ae	1419	#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /!< Enable high-speed slew /
bogdanm	20:4263a77256ae	1420	#define SCU_MODE_INBUFF_EN (0x1 << 6) /!< Enable Input buffer /
bogdanm	20:4263a77256ae	1421	#define SCU_MODE_ZIF_DIS (0x1 << 7) /!< Disable input glitch filter /
bogdanm	20:4263a77256ae	1422	#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /!< Normal drive: 4mA drive strength /
bogdanm	20:4263a77256ae	1423	#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /!< Medium drive: 8mA drive strength /
bogdanm	20:4263a77256ae	1424	#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /!< High drive: 14mA drive strength /
bogdanm	20:4263a77256ae	1425	#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /!< Ultra high- drive: 20mA drive strength /
bogdanm	20:4263a77256ae	1426
bogdanm	20:4263a77256ae	1427	/* Common SCU configurations */
bogdanm	20:4263a77256ae	1428	#define SCU_PINIO_FAST (SCU_MODE_MODE_PULLUP_DIS \| SCU_MODE_HIGHSPEEDSLEW_EN \| SCU_MODE_INBUFF_EN \| SCU_MODE_ZIF_DIS)
bogdanm	20:4263a77256ae	1429	#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
bogdanm	20:4263a77256ae	1430	#define SCU_PINIO_PULLDOWN (SCU_MODE_MODE_PULLDOWN \| SCU_MODE_MODE_PULLUP_DIS \| SCU_MODE_INBUFF_EN)
bogdanm	20:4263a77256ae	1431	#define SCU_PINIO_PULLNONE (SCU_MODE_MODE_PULLUP_DIS \| SCU_MODE_INBUFF_EN)
bogdanm	20:4263a77256ae	1432
bogdanm	20:4263a77256ae	1433	/* Calculate SCU offset and register address from group and pin number */
bogdanm	20:4263a77256ae	1434	#define SCU_OFF(group, num) ((0x80 * group) + (0x04 * num))
bogdanm	20:4263a77256ae	1435	#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
bogdanm	20:4263a77256ae	1436
bogdanm	20:4263a77256ae	1437	/**
bogdanm	20:4263a77256ae	1438	* @brief GPIO pin interrupt register block structure
bogdanm	20:4263a77256ae	1439	*/
bogdanm	20:4263a77256ae	1440	#define LPC_GPIO_PIN_INT_BASE 0x40087000
bogdanm	20:4263a77256ae	1441
bogdanm	20:4263a77256ae	1442	typedef struct { /!< GPIO_PIN_INT Structure /
bogdanm	20:4263a77256ae	1443	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
bogdanm	20:4263a77256ae	1444	__IO uint32_t IENR; /!< Pin Interrupt Enable (Rising) register /
bogdanm	20:4263a77256ae	1445	__O uint32_t SIENR; /!< Set Pin Interrupt Enable (Rising) register /
bogdanm	20:4263a77256ae	1446	__O uint32_t CIENR; /!< Clear Pin Interrupt Enable (Rising) register /
bogdanm	20:4263a77256ae	1447	__IO uint32_t IENF; /!< Pin Interrupt Enable Falling Edge / Active Level register /
bogdanm	20:4263a77256ae	1448	__O uint32_t SIENF; /!< Set Pin Interrupt Enable Falling Edge / Active Level register /
bogdanm	20:4263a77256ae	1449	__O uint32_t CIENF; /!< Clear Pin Interrupt Enable Falling Edge / Active Level address /
bogdanm	20:4263a77256ae	1450	__IO uint32_t RISE; /!< Pin Interrupt Rising Edge register /
bogdanm	20:4263a77256ae	1451	__IO uint32_t FALL; /!< Pin Interrupt Falling Edge register /
bogdanm	20:4263a77256ae	1452	__IO uint32_t IST; /!< Pin Interrupt Status register /
bogdanm	20:4263a77256ae	1453	} LPC_GPIOPININT_T;
bogdanm	20:4263a77256ae	1454
bogdanm	20:4263a77256ae	1455	typedef enum LPC_GPIOPININT_MODE {
bogdanm	20:4263a77256ae	1456	GPIOPININT_RISING_EDGE = 0x01,
bogdanm	20:4263a77256ae	1457	GPIOPININT_FALLING_EDGE = 0x02,
bogdanm	20:4263a77256ae	1458	GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
bogdanm	20:4263a77256ae	1459	GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
bogdanm	20:4263a77256ae	1460	} LPC_GPIOPININT_MODE_T;
bogdanm	20:4263a77256ae	1461
bogdanm	20:4263a77256ae	1462	/**
bogdanm	20:4263a77256ae	1463	* @brief GPIO grouped interrupt register block structure
bogdanm	20:4263a77256ae	1464	*/
bogdanm	20:4263a77256ae	1465	#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
bogdanm	20:4263a77256ae	1466	#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
bogdanm	20:4263a77256ae	1467
bogdanm	20:4263a77256ae	1468	typedef struct { /!< GPIO_GROUP_INTn Structure /
bogdanm	20:4263a77256ae	1469	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
bogdanm	20:4263a77256ae	1470	__I uint32_t RESERVED0[7];
bogdanm	20:4263a77256ae	1471	__IO uint32_t PORT_POL[8]; /!< GPIO grouped interrupt port polarity register /
bogdanm	20:4263a77256ae	1472	__IO uint32_t PORT_ENA[8]; /!< GPIO grouped interrupt port m enable register /
bogdanm	20:4263a77256ae	1473	} LPC_GPIOGROUPINT_T;
bogdanm	20:4263a77256ae	1474
bogdanm	20:4263a77256ae	1475	/**
bogdanm	20:4263a77256ae	1476	* @brief Motor Control PWM register block structure
bogdanm	20:4263a77256ae	1477	*/
bogdanm	20:4263a77256ae	1478	#define LPC_MCPWM_BASE 0x400A0000
bogdanm	20:4263a77256ae	1479
bogdanm	20:4263a77256ae	1480	typedef struct { /!< MCPWM Structure /
bogdanm	20:4263a77256ae	1481	__I uint32_t CON; /!< PWM Control read address /
bogdanm	20:4263a77256ae	1482	__O uint32_t CON_SET; /!< PWM Control set address /
bogdanm	20:4263a77256ae	1483	__O uint32_t CON_CLR; /!< PWM Control clear address /
bogdanm	20:4263a77256ae	1484	__I uint32_t CAPCON; /!< Capture Control read address /
bogdanm	20:4263a77256ae	1485	__O uint32_t CAPCON_SET; /!< Capture Control set address /
bogdanm	20:4263a77256ae	1486	__O uint32_t CAPCON_CLR; /!< Event Control clear address /
bogdanm	20:4263a77256ae	1487	__IO uint32_t TC[3]; /!< Timer Counter register /
bogdanm	20:4263a77256ae	1488	__IO uint32_t LIM[3]; /!< Limit register /
bogdanm	20:4263a77256ae	1489	__IO uint32_t MAT[3]; /!< Match register /
bogdanm	20:4263a77256ae	1490	__IO uint32_t DT; /!< Dead time register /
bogdanm	20:4263a77256ae	1491	__IO uint32_t CCP; /!< Communication Pattern register /
bogdanm	20:4263a77256ae	1492	__I uint32_t CAP[3]; /!< Capture register /
bogdanm	20:4263a77256ae	1493	__I uint32_t INTEN; /!< Interrupt Enable read address /
bogdanm	20:4263a77256ae	1494	__O uint32_t INTEN_SET; /!< Interrupt Enable set address /
bogdanm	20:4263a77256ae	1495	__O uint32_t INTEN_CLR; /!< Interrupt Enable clear address /
bogdanm	20:4263a77256ae	1496	__I uint32_t CNTCON; /!< Count Control read address /
bogdanm	20:4263a77256ae	1497	__O uint32_t CNTCON_SET; /!< Count Control set address /
bogdanm	20:4263a77256ae	1498	__O uint32_t CNTCON_CLR; /!< Count Control clear address /
bogdanm	20:4263a77256ae	1499	__I uint32_t INTF; /!< Interrupt flags read address /
bogdanm	20:4263a77256ae	1500	__O uint32_t INTF_SET; /!< Interrupt flags set address /
bogdanm	20:4263a77256ae	1501	__O uint32_t INTF_CLR; /!< Interrupt flags clear address /
bogdanm	20:4263a77256ae	1502	__O uint32_t CAP_CLR; /!< Capture clear address /
bogdanm	20:4263a77256ae	1503	} LPC_MCPWM_T;
bogdanm	20:4263a77256ae	1504
bogdanm	20:4263a77256ae	1505	/**
bogdanm	20:4263a77256ae	1506	* @brief I2C register block structure
bogdanm	20:4263a77256ae	1507	*/
bogdanm	20:4263a77256ae	1508	#define LPC_I2C0_BASE 0x400A1000
bogdanm	20:4263a77256ae	1509	#define LPC_I2C1_BASE 0x400E0000
bogdanm	20:4263a77256ae	1510
bogdanm	20:4263a77256ae	1511	typedef struct { /* I2C0 Structure */
bogdanm	20:4263a77256ae	1512	__IO uint32_t CONSET; /!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. /
bogdanm	20:4263a77256ae	1513	__I uint32_t STAT; /!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. /
bogdanm	20:4263a77256ae	1514	__IO uint32_t DAT; /!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. /
bogdanm	20:4263a77256ae	1515	__IO uint32_t ADR0; /!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. /
bogdanm	20:4263a77256ae	1516	__IO uint32_t SCLH; /!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. /
bogdanm	20:4263a77256ae	1517	__IO uint32_t SCLL; /!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. /
bogdanm	20:4263a77256ae	1518	__O uint32_t CONCLR; /!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. /
bogdanm	20:4263a77256ae	1519	__IO uint32_t MMCTRL; /!< Monitor mode control register. /
bogdanm	20:4263a77256ae	1520	__IO uint32_t ADR1; /!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. /
bogdanm	20:4263a77256ae	1521	__IO uint32_t ADR2; /!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. /
bogdanm	20:4263a77256ae	1522	__IO uint32_t ADR3; /!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. /
bogdanm	20:4263a77256ae	1523	__I uint32_t DATA_BUFFER; /!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. /
bogdanm	20:4263a77256ae	1524	__IO uint32_t MASK[4]; /!< I2C Slave address mask register /
bogdanm	20:4263a77256ae	1525	} LPC_I2C_T;
bogdanm	20:4263a77256ae	1526
bogdanm	20:4263a77256ae	1527	/**
bogdanm	20:4263a77256ae	1528	* @brief I2S register block structure
bogdanm	20:4263a77256ae	1529	*/
bogdanm	20:4263a77256ae	1530	#define LPC_I2S0_BASE 0x400A2000
bogdanm	20:4263a77256ae	1531	#define LPC_I2S1_BASE 0x400A3000
bogdanm	20:4263a77256ae	1532
bogdanm	20:4263a77256ae	1533	typedef struct { /!< I2S Structure /
bogdanm	20:4263a77256ae	1534	__IO uint32_t DAO; /!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel /
bogdanm	20:4263a77256ae	1535	__IO uint32_t DAI; /!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel /
bogdanm	20:4263a77256ae	1536	__O uint32_t TXFIFO; /!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO /
bogdanm	20:4263a77256ae	1537	__I uint32_t RXFIFO; /!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO /
bogdanm	20:4263a77256ae	1538	__I uint32_t STATE; /!< I2S Status Feedback Register. Contains status information about the I2S interface /
bogdanm	20:4263a77256ae	1539	__IO uint32_t DMA1; /!< I2S DMA Configuration Register 1. Contains control information for DMA request 1 /
bogdanm	20:4263a77256ae	1540	__IO uint32_t DMA2; /!< I2S DMA Configuration Register 2. Contains control information for DMA request 2 /
bogdanm	20:4263a77256ae	1541	__IO uint32_t IRQ; /!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated /
bogdanm	20:4263a77256ae	1542	__IO uint32_t TXRATE; /!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK /
bogdanm	20:4263a77256ae	1543	__IO uint32_t RXRATE; /!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK /
bogdanm	20:4263a77256ae	1544	__IO uint32_t TXBITRATE; /!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock /
bogdanm	20:4263a77256ae	1545	__IO uint32_t RXBITRATE; /!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock /
bogdanm	20:4263a77256ae	1546	__IO uint32_t TXMODE; /!< I2S Transmit mode control /
bogdanm	20:4263a77256ae	1547	__IO uint32_t RXMODE; /!< I2S Receive mode control /
bogdanm	20:4263a77256ae	1548	} LPC_I2S_T;
bogdanm	20:4263a77256ae	1549
bogdanm	20:4263a77256ae	1550	/**
bogdanm	20:4263a77256ae	1551	* @brief CCAN Controller Area Network register block structure
bogdanm	20:4263a77256ae	1552	*/
bogdanm	20:4263a77256ae	1553	#define LPC_C_CAN1_BASE 0x400A4000
bogdanm	20:4263a77256ae	1554	#define LPC_C_CAN0_BASE 0x400E2000
bogdanm	20:4263a77256ae	1555
bogdanm	20:4263a77256ae	1556	typedef struct { /!< C_CAN message interface Structure /
bogdanm	20:4263a77256ae	1557	__IO uint32_t IF_CMDREQ; /!< Message interface command request /
bogdanm	20:4263a77256ae	1558	union {
bogdanm	20:4263a77256ae	1559	__IO uint32_t IF_CMDMSK_R; /!< Message interface command mask (read direction) /
bogdanm	20:4263a77256ae	1560	__IO uint32_t IF_CMDMSK_W; /!< Message interface command mask (write direction) /
bogdanm	20:4263a77256ae	1561	};
bogdanm	20:4263a77256ae	1562
bogdanm	20:4263a77256ae	1563	__IO uint32_t IF_MSK1; /!< Message interface mask 1 /
bogdanm	20:4263a77256ae	1564	__IO uint32_t IF_MSK2; /!< Message interface mask 2 /
bogdanm	20:4263a77256ae	1565	__IO uint32_t IF_ARB1; /!< Message interface arbitration 1 /
bogdanm	20:4263a77256ae	1566	__IO uint32_t IF_ARB2; /!< Message interface arbitration 2 /
bogdanm	20:4263a77256ae	1567	__IO uint32_t IF_MCTRL; /!< Message interface message control /
bogdanm	20:4263a77256ae	1568	__IO uint32_t IF_DA1; /!< Message interface data A1 /
bogdanm	20:4263a77256ae	1569	__IO uint32_t IF_DA2; /!< Message interface data A2 /
bogdanm	20:4263a77256ae	1570	__IO uint32_t IF_DB1; /!< Message interface data B1 /
bogdanm	20:4263a77256ae	1571	__IO uint32_t IF_DB2; /!< Message interface data B2 /
bogdanm	20:4263a77256ae	1572	__I uint32_t RESERVED[13];
bogdanm	20:4263a77256ae	1573	} LPC_CCAN_IF_T;
bogdanm	20:4263a77256ae	1574
bogdanm	20:4263a77256ae	1575	typedef struct { /!< C_CAN Structure /
bogdanm	20:4263a77256ae	1576	__IO uint32_t CNTL; /!< CAN control /
bogdanm	20:4263a77256ae	1577	__IO uint32_t STAT; /!< Status register /
bogdanm	20:4263a77256ae	1578	__I uint32_t EC; /!< Error counter /
bogdanm	20:4263a77256ae	1579	__IO uint32_t BT; /!< Bit timing register /
bogdanm	20:4263a77256ae	1580	__I uint32_t INT; /!< Interrupt register /
bogdanm	20:4263a77256ae	1581	__IO uint32_t TEST; /!< Test register /
bogdanm	20:4263a77256ae	1582	__IO uint32_t BRPE; /!< Baud rate prescaler extension register /
bogdanm	20:4263a77256ae	1583	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	1584	LPC_CCAN_IF_T IF[2];
bogdanm	20:4263a77256ae	1585	__I uint32_t RESERVED2[8];
bogdanm	20:4263a77256ae	1586	__I uint32_t TXREQ1; /!< Transmission request 1 /
bogdanm	20:4263a77256ae	1587	__I uint32_t TXREQ2; /!< Transmission request 2 /
bogdanm	20:4263a77256ae	1588	__I uint32_t RESERVED3[6];
bogdanm	20:4263a77256ae	1589	__I uint32_t ND1; /!< New data 1 /
bogdanm	20:4263a77256ae	1590	__I uint32_t ND2; /!< New data 2 /
bogdanm	20:4263a77256ae	1591	__I uint32_t RESERVED4[6];
bogdanm	20:4263a77256ae	1592	__I uint32_t IR1; /!< Interrupt pending 1 /
bogdanm	20:4263a77256ae	1593	__I uint32_t IR2; /!< Interrupt pending 2 /
bogdanm	20:4263a77256ae	1594	__I uint32_t RESERVED5[6];
bogdanm	20:4263a77256ae	1595	__I uint32_t MSGV1; /!< Message valid 1 /
bogdanm	20:4263a77256ae	1596	__I uint32_t MSGV2; /!< Message valid 2 /
bogdanm	20:4263a77256ae	1597	__I uint32_t RESERVED6[6];
bogdanm	20:4263a77256ae	1598	__IO uint32_t CLKDIV; /!< CAN clock divider register /
bogdanm	20:4263a77256ae	1599	} LPC_CCAN_T;
bogdanm	20:4263a77256ae	1600
bogdanm	20:4263a77256ae	1601	/**
bogdanm	20:4263a77256ae	1602	* @brief Repetitive Interrupt Timer register block structure
bogdanm	20:4263a77256ae	1603	*/
bogdanm	20:4263a77256ae	1604	#define LPC_RITIMER_BASE 0x400C0000
bogdanm	20:4263a77256ae	1605
bogdanm	20:4263a77256ae	1606	typedef struct { /!< RITIMER Structure /
bogdanm	20:4263a77256ae	1607	__IO uint32_t COMPVAL; /!< Compare register /
bogdanm	20:4263a77256ae	1608	__IO uint32_t MASK; /!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. /
bogdanm	20:4263a77256ae	1609	__IO uint32_t CTRL; /!< Control register. /
bogdanm	20:4263a77256ae	1610	__IO uint32_t COUNTER; /!< 32-bit counter /
bogdanm	20:4263a77256ae	1611	#if defined(CHIP_LPC1347)
bogdanm	20:4263a77256ae	1612	__IO uint32_t COMPVAL_H; /!< Compare upper register /
bogdanm	20:4263a77256ae	1613	__IO uint32_t MASK_H; /!< Mask upper register /
bogdanm	20:4263a77256ae	1614	__I uint32_t RESERVED0[1];
bogdanm	20:4263a77256ae	1615	__IO uint32_t COUNTER_H; /!< Counter upper register /
bogdanm	20:4263a77256ae	1616	#endif
bogdanm	20:4263a77256ae	1617	} LPC_RITIMER_T;
bogdanm	20:4263a77256ae	1618
bogdanm	20:4263a77256ae	1619	/**
bogdanm	20:4263a77256ae	1620	* @brief Quadrature Encoder Interface register block structure
bogdanm	20:4263a77256ae	1621	*/
bogdanm	20:4263a77256ae	1622	#define LPC_QEI_BASE 0x400C6000
bogdanm	20:4263a77256ae	1623
bogdanm	20:4263a77256ae	1624	typedef struct { /!< QEI Structure /
bogdanm	20:4263a77256ae	1625	__O uint32_t CON; /!< Control register /
bogdanm	20:4263a77256ae	1626	__I uint32_t STAT; /!< Encoder status register /
bogdanm	20:4263a77256ae	1627	__IO uint32_t CONF; /!< Configuration register /
bogdanm	20:4263a77256ae	1628	__I uint32_t POS; /!< Position register /
bogdanm	20:4263a77256ae	1629	__IO uint32_t MAXPOS; /!< Maximum position register /
bogdanm	20:4263a77256ae	1630	__IO uint32_t CMPOS0; /!< position compare register 0 /
bogdanm	20:4263a77256ae	1631	__IO uint32_t CMPOS1; /!< position compare register 1 /
bogdanm	20:4263a77256ae	1632	__IO uint32_t CMPOS2; /!< position compare register 2 /
bogdanm	20:4263a77256ae	1633	__I uint32_t INXCNT; /!< Index count register /
bogdanm	20:4263a77256ae	1634	__IO uint32_t INXCMP0; /!< Index compare register 0 /
bogdanm	20:4263a77256ae	1635	__IO uint32_t LOAD; /!< Velocity timer reload register /
bogdanm	20:4263a77256ae	1636	__I uint32_t TIME; /!< Velocity timer register /
bogdanm	20:4263a77256ae	1637	__I uint32_t VEL; /!< Velocity counter register /
bogdanm	20:4263a77256ae	1638	__I uint32_t CAP; /!< Velocity capture register /
bogdanm	20:4263a77256ae	1639	__IO uint32_t VELCOMP; /!< Velocity compare register /
bogdanm	20:4263a77256ae	1640	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
bogdanm	20:4263a77256ae	1641	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
bogdanm	20:4263a77256ae	1642	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
bogdanm	20:4263a77256ae	1643	__IO uint32_t WINDOW; /!< Index acceptance window register /
bogdanm	20:4263a77256ae	1644	__IO uint32_t INXCMP1; /!< Index compare register 1 /
bogdanm	20:4263a77256ae	1645	__IO uint32_t INXCMP2; /!< Index compare register 2 /
bogdanm	20:4263a77256ae	1646	__I uint32_t RESERVED0[993];
bogdanm	20:4263a77256ae	1647	__O uint32_t IEC; /!< Interrupt enable clear register /
bogdanm	20:4263a77256ae	1648	__O uint32_t IES; /!< Interrupt enable set register /
bogdanm	20:4263a77256ae	1649	__I uint32_t INTSTAT; /!< Interrupt status register /
bogdanm	20:4263a77256ae	1650	__I uint32_t IE; /!< Interrupt enable register /
bogdanm	20:4263a77256ae	1651	__O uint32_t CLR; /!< Interrupt status clear register /
bogdanm	20:4263a77256ae	1652	__O uint32_t SET; /!< Interrupt status set register /
bogdanm	20:4263a77256ae	1653	} LPC_QEI_T;
bogdanm	20:4263a77256ae	1654
bogdanm	20:4263a77256ae	1655	/**
bogdanm	20:4263a77256ae	1656	* @brief Global Input Multiplexer Array (GIMA) register block structure
bogdanm	20:4263a77256ae	1657	*/
bogdanm	20:4263a77256ae	1658	#define LPC_GIMA_BASE 0x400C7000
bogdanm	20:4263a77256ae	1659
bogdanm	20:4263a77256ae	1660	typedef struct { /!< GIMA Structure /
bogdanm	20:4263a77256ae	1661	__IO uint32_t CAP0_IN[4][4]; /!< Timer x CAP0_y capture input multiplexer (GIMA output ((x4)+y)) */
bogdanm	20:4263a77256ae	1662	__IO uint32_t CTIN_IN[8]; /!< SCT CTIN_x capture input multiplexer (GIMA output (16+x)) /
bogdanm	20:4263a77256ae	1663	__IO uint32_t VADC_TRIGGER_IN; /!< VADC trigger input multiplexer (GIMA output 24) /
bogdanm	20:4263a77256ae	1664	__IO uint32_t EVENTROUTER_13_IN; /!< Event router input 13 multiplexer (GIMA output 25) /
bogdanm	20:4263a77256ae	1665	__IO uint32_t EVENTROUTER_14_IN; /!< Event router input 14 multiplexer (GIMA output 26) /
bogdanm	20:4263a77256ae	1666	__IO uint32_t EVENTROUTER_16_IN; /!< Event router input 16 multiplexer (GIMA output 27) /
bogdanm	20:4263a77256ae	1667	__IO uint32_t ADCSTART0_IN; /!< ADC start0 input multiplexer (GIMA output 28) /
bogdanm	20:4263a77256ae	1668	__IO uint32_t ADCSTART1_IN; /!< ADC start1 input multiplexer (GIMA output 29) /
bogdanm	20:4263a77256ae	1669	} LPC_GIMA_T;
bogdanm	20:4263a77256ae	1670
bogdanm	20:4263a77256ae	1671	/**
bogdanm	20:4263a77256ae	1672	* @brief DAC register block structure
bogdanm	20:4263a77256ae	1673	*/
bogdanm	20:4263a77256ae	1674	#define LPC_DAC_BASE 0x400E1000
bogdanm	20:4263a77256ae	1675
bogdanm	20:4263a77256ae	1676	typedef struct { /!< DAC Structure /
bogdanm	20:4263a77256ae	1677	__IO uint32_t CR; /!< DAC register. Holds the conversion data. /
bogdanm	20:4263a77256ae	1678	__IO uint32_t CTRL; /!< DAC control register. /
bogdanm	20:4263a77256ae	1679	__IO uint32_t CNTVAL; /!< DAC counter value register. /
bogdanm	20:4263a77256ae	1680	} LPC_DAC_T;
bogdanm	20:4263a77256ae	1681
bogdanm	20:4263a77256ae	1682	/* After the selected settling time after this field is written with a
bogdanm	20:4263a77256ae	1683	* new VALUE, the voltage on the AOUT pin (with respect to VSSA)
bogdanm	20:4263a77256ae	1684	* is VALUE/1024 ? VREF
bogdanm	20:4263a77256ae	1685	*/
bogdanm	20:4263a77256ae	1686	#define DAC_RANGE 0x3FF
bogdanm	20:4263a77256ae	1687	#define DAC_VALUE(n) ((uint32_t) ((n & DAC_RANGE) << 6))
bogdanm	20:4263a77256ae	1688	/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
bogdanm	20:4263a77256ae	1689	* and the maximum current is 700 microAmpere
bogdanm	20:4263a77256ae	1690	* If this bit = 1: The settling time of the DAC is 2.5 microsecond
bogdanm	20:4263a77256ae	1691	* and the maximum current is 350 microAmpere
bogdanm	20:4263a77256ae	1692	*/
bogdanm	20:4263a77256ae	1693	#define DAC_BIAS_EN ((uint32_t) (1 << 16))
bogdanm	20:4263a77256ae	1694	/* Value to reload interrupt DMA counter */
bogdanm	20:4263a77256ae	1695	#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
bogdanm	20:4263a77256ae	1696
bogdanm	20:4263a77256ae	1697	#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
bogdanm	20:4263a77256ae	1698	#define DAC_CNT_ENA ((uint32_t) (1 << 2))
bogdanm	20:4263a77256ae	1699	#define DAC_DMA_ENA ((uint32_t) (1 << 3))
bogdanm	20:4263a77256ae	1700	#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
bogdanm	20:4263a77256ae	1701
bogdanm	20:4263a77256ae	1702	/* Current option in DAC configuration option */
bogdanm	20:4263a77256ae	1703	typedef enum IP_DAC_CURRENT_OPT {
bogdanm	20:4263a77256ae	1704	DAC_MAX_UPDATE_RATE_1MHz = 0, /*!< Shorter settling times and higher power consumption;
bogdanm	20:4263a77256ae	1705	allows for a maximum update rate of 1 MHz */
bogdanm	20:4263a77256ae	1706	DAC_MAX_UPDATE_RATE_400kHz /*!< Longer settling times and lower power consumption;
bogdanm	20:4263a77256ae	1707	allows for a maximum update rate of 400 kHz */
bogdanm	20:4263a77256ae	1708	} IP_DAC_CURRENT_OPT_T;
bogdanm	20:4263a77256ae	1709
bogdanm	20:4263a77256ae	1710	/**
bogdanm	20:4263a77256ae	1711	* @brief ADC register block structure
bogdanm	20:4263a77256ae	1712	*/
bogdanm	20:4263a77256ae	1713	#define LPC_ADC0_BASE 0x400E3000
bogdanm	20:4263a77256ae	1714	#define LPC_ADC1_BASE 0x400E4000
bogdanm	20:4263a77256ae	1715	#define ADC_ACC_10BITS
bogdanm	20:4263a77256ae	1716
bogdanm	20:4263a77256ae	1717	/**
bogdanm	20:4263a77256ae	1718	* @brief 10 or 12-bit ADC register block structure
bogdanm	20:4263a77256ae	1719	*/
bogdanm	20:4263a77256ae	1720	typedef struct { /!< ADCn Structure /
bogdanm	20:4263a77256ae	1721	__IO uint32_t CR; /!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. /
bogdanm	20:4263a77256ae	1722	__I uint32_t GDR; /!< A/D Global Data Register. Contains the result of the most recent A/D conversion. /
bogdanm	20:4263a77256ae	1723	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	1724	__IO uint32_t INTEN; /!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. /
bogdanm	20:4263a77256ae	1725	__I uint32_t DR[8]; /!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. /
bogdanm	20:4263a77256ae	1726	__I uint32_t STAT; /!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. /
bogdanm	20:4263a77256ae	1727	} LPC_ADC_T;
bogdanm	20:4263a77256ae	1728
bogdanm	20:4263a77256ae	1729	/* ADC register support bitfields and mask */
bogdanm	20:4263a77256ae	1730	#define ADC_RANGE 0x3FF
bogdanm	20:4263a77256ae	1731	#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /!< Mask for getting the 10 bits ADC data read value /
bogdanm	20:4263a77256ae	1732	#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /!< Number of ADC accuracy bits /
bogdanm	20:4263a77256ae	1733	#define ADC_DR_DONE(n) (((n) >> 31)) /!< Mask for reading the ADC done status /
bogdanm	20:4263a77256ae	1734	#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /!< Mask for reading the ADC overrun status /
bogdanm	20:4263a77256ae	1735	#define ADC_CR_CH_SEL(n) ((1UL << (n))) /!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted /
bogdanm	20:4263a77256ae	1736	#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D /
bogdanm	20:4263a77256ae	1737	#define ADC_CR_BURST ((1UL << 16)) /!< Repeated conversions A/D enable bit /
bogdanm	20:4263a77256ae	1738	#define ADC_CR_PDN ((1UL << 21)) /!< ADC convert is operational /
bogdanm	20:4263a77256ae	1739	#define ADC_CR_START_MASK ((7UL << 24)) /!< ADC start mask bits /
bogdanm	20:4263a77256ae	1740	#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /!< Select Start Mode /
bogdanm	20:4263a77256ae	1741	#define ADC_CR_START_NOW ((1UL << 24)) /!< Start conversion now /
bogdanm	20:4263a77256ae	1742	#define ADC_CR_START_CTOUT15 ((2UL << 24)) /!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 /
bogdanm	20:4263a77256ae	1743	#define ADC_CR_START_CTOUT8 ((3UL << 24)) /!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 /
bogdanm	20:4263a77256ae	1744	#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 /
bogdanm	20:4263a77256ae	1745	#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 /
bogdanm	20:4263a77256ae	1746	#define ADC_CR_START_MCOA2 ((6UL << 24)) /!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 /
bogdanm	20:4263a77256ae	1747	#define ADC_CR_EDGE ((1UL << 27)) /!< Start conversion on a falling edge on the selected CAP/MAT signal /
bogdanm	20:4263a77256ae	1748	#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) \| ADC_CR_BITACC(0x07) \| ADC_CR_PDN)
bogdanm	20:4263a77256ae	1749
bogdanm	20:4263a77256ae	1750	/* ADC status register used for IP drivers */
bogdanm	20:4263a77256ae	1751	typedef enum IP_ADC_STATUS {
bogdanm	20:4263a77256ae	1752	ADC_DR_DONE_STAT, /!< ADC data register staus /
bogdanm	20:4263a77256ae	1753	ADC_DR_OVERRUN_STAT,/!< ADC data overrun staus /
bogdanm	20:4263a77256ae	1754	ADC_DR_ADINT_STAT /!< ADC interrupt status /
bogdanm	20:4263a77256ae	1755	} IP_ADC_STATUS_T;
bogdanm	20:4263a77256ae	1756
bogdanm	20:4263a77256ae	1757	/**
bogdanm	20:4263a77256ae	1758	* @brief GPIO port register block structure
bogdanm	20:4263a77256ae	1759	*/
bogdanm	20:4263a77256ae	1760	#define LPC_GPIO_PORT_BASE 0x400F4000
bogdanm	20:4263a77256ae	1761
bogdanm	20:4263a77256ae	1762	typedef struct { /!< GPIO_PORT Structure /
bogdanm	20:4263a77256ae	1763	__IO uint8_t B[128][32]; /!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 /
bogdanm	20:4263a77256ae	1764	__IO uint32_t W[32][32]; /!< Offset 0x1000: Word pin registers port 0 to n /
bogdanm	20:4263a77256ae	1765	__IO uint32_t DIR[32]; /!< Offset 0x2000: Direction registers port n /
bogdanm	20:4263a77256ae	1766	__IO uint32_t MASK[32]; /!< Offset 0x2080: Mask register port n /
bogdanm	20:4263a77256ae	1767	__IO uint32_t PIN[32]; /!< Offset 0x2100: Portpin register port n /
bogdanm	20:4263a77256ae	1768	__IO uint32_t MPIN[32]; /!< Offset 0x2180: Masked port register port n /
bogdanm	20:4263a77256ae	1769	__IO uint32_t SET[32]; /!< Offset 0x2200: Write: Set register for port n Read: output bits for port n /
bogdanm	20:4263a77256ae	1770	__O uint32_t CLR[32]; /!< Offset 0x2280: Clear port n /
bogdanm	20:4263a77256ae	1771	__O uint32_t NOT[32]; /!< Offset 0x2300: Toggle port n /
bogdanm	20:4263a77256ae	1772	} LPC_GPIO_T;
bogdanm	20:4263a77256ae	1773
bogdanm	20:4263a77256ae	1774	/* Calculate GPIO offset and port register address from group and pin number */
bogdanm	20:4263a77256ae	1775	#define GPIO_OFF(port, pin) ((port << 5) + pin)
bogdanm	20:4263a77256ae	1776	#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
bogdanm	20:4263a77256ae	1777
bogdanm	20:4263a77256ae	1778	/**
bogdanm	20:4263a77256ae	1779	* @brief SPI register block structure
bogdanm	20:4263a77256ae	1780	*/
bogdanm	20:4263a77256ae	1781	#define LPC_SPI_BASE 0x40100000
bogdanm	20:4263a77256ae	1782
bogdanm	20:4263a77256ae	1783	typedef struct { /!< SPI Structure /
bogdanm	20:4263a77256ae	1784	__IO uint32_t CR; /!< SPI Control Register. This register controls the operation of the SPI. /
bogdanm	20:4263a77256ae	1785	__I uint32_t SR; /!< SPI Status Register. This register shows the status of the SPI. /
bogdanm	20:4263a77256ae	1786	__IO uint32_t DR; /!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. /
bogdanm	20:4263a77256ae	1787	__IO uint32_t CCR; /!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. /
bogdanm	20:4263a77256ae	1788	__I uint32_t RESERVED0[3];
bogdanm	20:4263a77256ae	1789	__IO uint32_t INT; /!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. /
bogdanm	20:4263a77256ae	1790	} LPC_SPI_T;
bogdanm	20:4263a77256ae	1791
bogdanm	20:4263a77256ae	1792	/* SPI CFG Register BitMask */
bogdanm	20:4263a77256ae	1793	#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
bogdanm	20:4263a77256ae	1794	/* Enable of controlling the number of bits per transfer */
bogdanm	20:4263a77256ae	1795	#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
bogdanm	20:4263a77256ae	1796	/* Mask of field of bit controlling */
bogdanm	20:4263a77256ae	1797	#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
bogdanm	20:4263a77256ae	1798	/* Set the number of bits per a transfer */
bogdanm	20:4263a77256ae	1799	#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
bogdanm	20:4263a77256ae	1800	/* SPI Clock Phase Select*/
bogdanm	20:4263a77256ae	1801	#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /Capture data on the first edge, Change data on the following edge/
bogdanm	20:4263a77256ae	1802	#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /Change data on the first edge, Capture data on the following edge/
bogdanm	20:4263a77256ae	1803	/* SPI Clock Polarity Select*/
bogdanm	20:4263a77256ae	1804	#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
bogdanm	20:4263a77256ae	1805	#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
bogdanm	20:4263a77256ae	1806	/* SPI Slave Mode Select */
bogdanm	20:4263a77256ae	1807	#define SPI_CR_SLAVE_EN ((uint32_t) 0)
bogdanm	20:4263a77256ae	1808	/* SPI Master Mode Select */
bogdanm	20:4263a77256ae	1809	#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
bogdanm	20:4263a77256ae	1810	/* SPI MSB First mode enable */
bogdanm	20:4263a77256ae	1811	#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /Data will be transmitted and received in standard order (MSB first)./
bogdanm	20:4263a77256ae	1812	/* SPI LSB First mode enable */
bogdanm	20:4263a77256ae	1813	#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /Data will be transmitted and received in reverse order (LSB first)./
bogdanm	20:4263a77256ae	1814	/* SPI interrupt enable */
bogdanm	20:4263a77256ae	1815	#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
bogdanm	20:4263a77256ae	1816	/* SPI STAT Register BitMask */
bogdanm	20:4263a77256ae	1817	#define SPI_SR_BITMASK ((uint32_t) 0xF8)
bogdanm	20:4263a77256ae	1818	/* Slave abort Flag */
bogdanm	20:4263a77256ae	1819	#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
bogdanm	20:4263a77256ae	1820	/* Mode fault Flag */
bogdanm	20:4263a77256ae	1821	#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
bogdanm	20:4263a77256ae	1822	/* Read overrun flag*/
bogdanm	20:4263a77256ae	1823	#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
bogdanm	20:4263a77256ae	1824	/* Write collision flag. */
bogdanm	20:4263a77256ae	1825	#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
bogdanm	20:4263a77256ae	1826	/* SPI transfer complete flag. */
bogdanm	20:4263a77256ae	1827	#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
bogdanm	20:4263a77256ae	1828	/*SPI error flag /
bogdanm	20:4263a77256ae	1829	#define SPI_SR_ERROR (SPI_SR_ABRT \| SPI_SR_MODF \| SPI_SR_ROVR \| SPI_SR_WCOL)
bogdanm	20:4263a77256ae	1830	/* Enable SPI Test Mode */
bogdanm	20:4263a77256ae	1831	#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
bogdanm	20:4263a77256ae	1832	/* SPI interrupt flag */
bogdanm	20:4263a77256ae	1833	#define SPI_INT_SPIF ((uint32_t) (1 << 0))
bogdanm	20:4263a77256ae	1834	/* Receiver Data */
bogdanm	20:4263a77256ae	1835	#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
bogdanm	20:4263a77256ae	1836
bogdanm	20:4263a77256ae	1837	/* SPI Mode*/
bogdanm	20:4263a77256ae	1838	typedef enum LPC_SPI_MODE {
bogdanm	20:4263a77256ae	1839	SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
bogdanm	20:4263a77256ae	1840	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
bogdanm	20:4263a77256ae	1841	} LPC_SPI_MODE_T;
bogdanm	20:4263a77256ae	1842
bogdanm	20:4263a77256ae	1843	/* SPI Clock Mode*/
bogdanm	20:4263a77256ae	1844	typedef enum LPC_SPI_CLOCK_MODE {
bogdanm	20:4263a77256ae	1845	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_FIRST, /*< CPHA = 0, CPOL = 0 /
bogdanm	20:4263a77256ae	1846	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_FIRST, /*< CPHA = 0, CPOL = 1 /
bogdanm	20:4263a77256ae	1847	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_SECOND, /*< CPHA = 1, CPOL = 0 /
bogdanm	20:4263a77256ae	1848	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_SECOND, /*< CPHA = 1, CPOL = 1 /
bogdanm	20:4263a77256ae	1849	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /*< alias /
bogdanm	20:4263a77256ae	1850	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /*< alias /
bogdanm	20:4263a77256ae	1851	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /*< alias /
bogdanm	20:4263a77256ae	1852	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /*< alias /
bogdanm	20:4263a77256ae	1853	} LPC_SPI_CLOCK_MODE_T;
bogdanm	20:4263a77256ae	1854
bogdanm	20:4263a77256ae	1855	/* SPI Data Order Mode*/
bogdanm	20:4263a77256ae	1856	typedef enum LPC_SPI_DATA_ORDER {
bogdanm	20:4263a77256ae	1857	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
bogdanm	20:4263a77256ae	1858	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
bogdanm	20:4263a77256ae	1859	} LPC_SPI_DATA_ORDER_T;
bogdanm	20:4263a77256ae	1860
bogdanm	20:4263a77256ae	1861	/**
bogdanm	20:4263a77256ae	1862	* @brief Serial GPIO register block structure
bogdanm	20:4263a77256ae	1863	*/
bogdanm	20:4263a77256ae	1864	#define LPC_SGPIO_BASE 0x40101000
bogdanm	20:4263a77256ae	1865
bogdanm	20:4263a77256ae	1866	typedef struct { /!< SGPIO Structure /
bogdanm	20:4263a77256ae	1867	__IO uint32_t OUT_MUX_CFG[16]; /!< Pin multiplexer configurationregisters. /
bogdanm	20:4263a77256ae	1868	__IO uint32_t SGPIO_MUX_CFG[16]; /!< SGPIO multiplexer configuration registers. /
bogdanm	20:4263a77256ae	1869	__IO uint32_t SLICE_MUX_CFG[16]; /!< Slice multiplexer configuration registers. /
bogdanm	20:4263a77256ae	1870	__IO uint32_t REG[16]; /!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) /
bogdanm	20:4263a77256ae	1871	__IO uint32_t REG_SS[16]; /!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG /
bogdanm	20:4263a77256ae	1872	__IO uint32_t PRESET[16]; /!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 /
bogdanm	20:4263a77256ae	1873	__IO uint32_t COUNT[16]; /!< Down counter, counts down each clock cycle. /
bogdanm	20:4263a77256ae	1874	__IO uint32_t POS[16]; /!< Each time COUNT0 reaches 0x0 /
bogdanm	20:4263a77256ae	1875	__IO uint32_t MASK_A; /!< Mask for pattern match function of slice A /
bogdanm	20:4263a77256ae	1876	__IO uint32_t MASK_H; /!< Mask for pattern match function of slice H /
bogdanm	20:4263a77256ae	1877	__IO uint32_t MASK_I; /!< Mask for pattern match function of slice I /
bogdanm	20:4263a77256ae	1878	__IO uint32_t MASK_P; /!< Mask for pattern match function of slice P /
bogdanm	20:4263a77256ae	1879	__I uint32_t GPIO_INREG; /!< GPIO input status register /
bogdanm	20:4263a77256ae	1880	__IO uint32_t GPIO_OUTREG; /!< GPIO output control register /
bogdanm	20:4263a77256ae	1881	__IO uint32_t GPIO_OENREG; /!< GPIO OE control register /
bogdanm	20:4263a77256ae	1882	__IO uint32_t CTRL_ENABLED; /!< Enables the slice COUNT counter /
bogdanm	20:4263a77256ae	1883	__IO uint32_t CTRL_DISABLED; /!< Disables the slice COUNT counter /
bogdanm	20:4263a77256ae	1884	__I uint32_t RESERVED0[823];
bogdanm	20:4263a77256ae	1885	__O uint32_t CLR_EN_0; /!< Shift clock interrupt clear mask /
bogdanm	20:4263a77256ae	1886	__O uint32_t SET_EN_0; /!< Shift clock interrupt set mask /
bogdanm	20:4263a77256ae	1887	__I uint32_t ENABLE_0; /!< Shift clock interrupt enable /
bogdanm	20:4263a77256ae	1888	__I uint32_t STATUS_0; /!< Shift clock interrupt status /
bogdanm	20:4263a77256ae	1889	__O uint32_t CTR_STATUS_0; /!< Shift clock interrupt clear status /
bogdanm	20:4263a77256ae	1890	__O uint32_t SET_STATUS_0; /!< Shift clock interrupt set status /
bogdanm	20:4263a77256ae	1891	__I uint32_t RESERVED1[2];
bogdanm	20:4263a77256ae	1892	__O uint32_t CLR_EN_1; /!< Capture clock interrupt clear mask /
bogdanm	20:4263a77256ae	1893	__O uint32_t SET_EN_1; /!< Capture clock interrupt set mask /
bogdanm	20:4263a77256ae	1894	__I uint32_t ENABLE_1; /!< Capture clock interrupt enable /
bogdanm	20:4263a77256ae	1895	__I uint32_t STATUS_1; /!< Capture clock interrupt status /
bogdanm	20:4263a77256ae	1896	__O uint32_t CTR_STATUS_1; /!< Capture clock interrupt clear status /
bogdanm	20:4263a77256ae	1897	__O uint32_t SET_STATUS_1; /!< Capture clock interrupt set status /
bogdanm	20:4263a77256ae	1898	__I uint32_t RESERVED2[2];
bogdanm	20:4263a77256ae	1899	__O uint32_t CLR_EN_2; /!< Pattern match interrupt clear mask /
bogdanm	20:4263a77256ae	1900	__O uint32_t SET_EN_2; /!< Pattern match interrupt set mask /
bogdanm	20:4263a77256ae	1901	__I uint32_t ENABLE_2; /!< Pattern match interrupt enable /
bogdanm	20:4263a77256ae	1902	__I uint32_t STATUS_2; /!< Pattern match interrupt status /
bogdanm	20:4263a77256ae	1903	__O uint32_t CTR_STATUS_2; /!< Pattern match interrupt clear status /
bogdanm	20:4263a77256ae	1904	__O uint32_t SET_STATUS_2; /!< Pattern match interrupt set status /
bogdanm	20:4263a77256ae	1905	__I uint32_t RESERVED3[2];
bogdanm	20:4263a77256ae	1906	__O uint32_t CLR_EN_3; /!< Input interrupt clear mask /
bogdanm	20:4263a77256ae	1907	__O uint32_t SET_EN_3; /!< Input bit match interrupt set mask /
bogdanm	20:4263a77256ae	1908	__I uint32_t ENABLE_3; /!< Input bit match interrupt enable /
bogdanm	20:4263a77256ae	1909	__I uint32_t STATUS_3; /!< Input bit match interrupt status /
bogdanm	20:4263a77256ae	1910	__O uint32_t CTR_STATUS_3; /!< Input bit match interrupt clear status /
bogdanm	20:4263a77256ae	1911	__O uint32_t SET_STATUS_3; /!< Shift clock interrupt set status /
bogdanm	20:4263a77256ae	1912	} LPC_SGPIO_T;
bogdanm	20:4263a77256ae	1913
bogdanm	20:4263a77256ae	1914	/* End of section using anonymous unions */
bogdanm	20:4263a77256ae	1915	#if defined(__ARMCC_VERSION)
bogdanm	20:4263a77256ae	1916	#pragma pop
bogdanm	20:4263a77256ae	1917	#elif defined(__CWCC__)
bogdanm	20:4263a77256ae	1918	#pragma pop
bogdanm	20:4263a77256ae	1919	#elif defined(__IAR_SYSTEMS_ICC__)
bogdanm	20:4263a77256ae	1920	//#pragma pop // FIXME not usable for IAR
bogdanm	20:4263a77256ae	1921	#else /* defined(__GNUC__) and others */
bogdanm	20:4263a77256ae	1922	/* Leave anonymous unions enabled */
bogdanm	20:4263a77256ae	1923	#endif
bogdanm	20:4263a77256ae	1924
bogdanm	20:4263a77256ae	1925	/**
bogdanm	20:4263a77256ae	1926	* @brief LPC43xx Peripheral register set declarations
bogdanm	20:4263a77256ae	1927	*/
bogdanm	20:4263a77256ae	1928	#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
bogdanm	20:4263a77256ae	1929	#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
bogdanm	20:4263a77256ae	1930	#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
bogdanm	20:4263a77256ae	1931	#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
bogdanm	20:4263a77256ae	1932	#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
bogdanm	20:4263a77256ae	1933	#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
bogdanm	20:4263a77256ae	1934	#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
bogdanm	20:4263a77256ae	1935	#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
bogdanm	20:4263a77256ae	1936	#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
bogdanm	20:4263a77256ae	1937	#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
bogdanm	20:4263a77256ae	1938	#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
bogdanm	20:4263a77256ae	1939	#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
bogdanm	20:4263a77256ae	1940	#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
bogdanm	20:4263a77256ae	1941	#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
bogdanm	20:4263a77256ae	1942	#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
bogdanm	20:4263a77256ae	1943	#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
bogdanm	20:4263a77256ae	1944	#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
bogdanm	20:4263a77256ae	1945	#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
bogdanm	20:4263a77256ae	1946	#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
bogdanm	20:4263a77256ae	1947	#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
bogdanm	20:4263a77256ae	1948	#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
bogdanm	20:4263a77256ae	1949	#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
bogdanm	20:4263a77256ae	1950	#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
bogdanm	20:4263a77256ae	1951	#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
bogdanm	20:4263a77256ae	1952	#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
bogdanm	20:4263a77256ae	1953	#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
bogdanm	20:4263a77256ae	1954	#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
bogdanm	20:4263a77256ae	1955	#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
bogdanm	20:4263a77256ae	1956	#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
bogdanm	20:4263a77256ae	1957	#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
bogdanm	20:4263a77256ae	1958	#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
bogdanm	20:4263a77256ae	1959	#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
bogdanm	20:4263a77256ae	1960	#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
bogdanm	20:4263a77256ae	1961	#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
bogdanm	20:4263a77256ae	1962	#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
bogdanm	20:4263a77256ae	1963	#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
bogdanm	20:4263a77256ae	1964	#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
bogdanm	20:4263a77256ae	1965	#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
bogdanm	20:4263a77256ae	1966	#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
bogdanm	20:4263a77256ae	1967	#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
bogdanm	20:4263a77256ae	1968	#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
bogdanm	20:4263a77256ae	1969	#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
bogdanm	20:4263a77256ae	1970	#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
bogdanm	20:4263a77256ae	1971	#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
bogdanm	20:4263a77256ae	1972	#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
bogdanm	20:4263a77256ae	1973	#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
bogdanm	20:4263a77256ae	1974	#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
bogdanm	20:4263a77256ae	1975	#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
bogdanm	20:4263a77256ae	1976	#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
bogdanm	20:4263a77256ae	1977	#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
bogdanm	20:4263a77256ae	1978
bogdanm	20:4263a77256ae	1979	/**
bogdanm	20:4263a77256ae	1980	* @}
bogdanm	20:4263a77256ae	1981	*/
bogdanm	20:4263a77256ae	1982
bogdanm	20:4263a77256ae	1983	#ifdef __cplusplus
bogdanm	20:4263a77256ae	1984	}
bogdanm	20:4263a77256ae	1985	#endif
bogdanm	20:4263a77256ae	1986
bogdanm	20:4263a77256ae	1987	#endif /* __LPC43XX_H */

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Type:	Library
Created:	18 Jul 2014
Imports:	22
Forks:	0
Commits:	251
Dependents:	1
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targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@20:4263a77256ae, 2013-09-10 (annotated)

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