Sigve Sebastian Farstad / mbed-src

mbed w/ spi bug fig

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vendor/NXP/LPC11U24/hal/i2c_api.c@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Child:
11:f9e72c209510
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "i2c_api.h"
emilmont 10:3bc89ef62ce7 17 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 18 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 19 #include "error.h"
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 static const PinMap PinMap_I2C_SDA[] = {
emilmont 10:3bc89ef62ce7 22 {P0_5, I2C_0, 1},
emilmont 10:3bc89ef62ce7 23 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 24 };
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 static const PinMap PinMap_I2C_SCL[] = {
emilmont 10:3bc89ef62ce7 27 {P0_4, I2C_0, 1},
emilmont 10:3bc89ef62ce7 28 {NC , NC, 0}
emilmont 10:3bc89ef62ce7 29 };
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 #define I2C_CONSET(x) (x->i2c->CONSET)
emilmont 10:3bc89ef62ce7 32 #define I2C_CONCLR(x) (x->i2c->CONCLR)
emilmont 10:3bc89ef62ce7 33 #define I2C_STAT(x) (x->i2c->STAT)
emilmont 10:3bc89ef62ce7 34 #define I2C_DAT(x) (x->i2c->DAT)
emilmont 10:3bc89ef62ce7 35 #define I2C_SCLL(x, val) (x->i2c->SCLL = val)
emilmont 10:3bc89ef62ce7 36 #define I2C_SCLH(x, val) (x->i2c->SCLH = val)
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 static const uint32_t I2C_addr_offset[2][4] = {
emilmont 10:3bc89ef62ce7 39 {0x0C, 0x20, 0x24, 0x28},
emilmont 10:3bc89ef62ce7 40 {0x30, 0x34, 0x38, 0x3C}
emilmont 10:3bc89ef62ce7 41 };
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
emilmont 10:3bc89ef62ce7 44 I2C_CONCLR(obj) = (start << 5)
emilmont 10:3bc89ef62ce7 45 | (stop << 4)
emilmont 10:3bc89ef62ce7 46 | (interrupt << 3)
emilmont 10:3bc89ef62ce7 47 | (acknowledge << 2);
emilmont 10:3bc89ef62ce7 48 }
emilmont 10:3bc89ef62ce7 49
emilmont 10:3bc89ef62ce7 50 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
emilmont 10:3bc89ef62ce7 51 I2C_CONSET(obj) = (start << 5)
emilmont 10:3bc89ef62ce7 52 | (stop << 4)
emilmont 10:3bc89ef62ce7 53 | (interrupt << 3)
emilmont 10:3bc89ef62ce7 54 | (acknowledge << 2);
emilmont 10:3bc89ef62ce7 55 }
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 // Clear the Serial Interrupt (SI)
emilmont 10:3bc89ef62ce7 58 static inline void i2c_clear_SI(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 59 i2c_conclr(obj, 0, 0, 1, 0);
emilmont 10:3bc89ef62ce7 60 }
emilmont 10:3bc89ef62ce7 61
emilmont 10:3bc89ef62ce7 62 static inline int i2c_status(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 63 return I2C_STAT(obj);
emilmont 10:3bc89ef62ce7 64 }
emilmont 10:3bc89ef62ce7 65
emilmont 10:3bc89ef62ce7 66 // Wait until the Serial Interrupt (SI) is set
emilmont 10:3bc89ef62ce7 67 static int i2c_wait_SI(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 68 int timeout = 0;
emilmont 10:3bc89ef62ce7 69 while (!(I2C_CONSET(obj) & (1 << 3))) {
emilmont 10:3bc89ef62ce7 70 timeout++;
emilmont 10:3bc89ef62ce7 71 if (timeout > 100000) return -1;
emilmont 10:3bc89ef62ce7 72 }
emilmont 10:3bc89ef62ce7 73 return 0;
emilmont 10:3bc89ef62ce7 74 }
emilmont 10:3bc89ef62ce7 75
emilmont 10:3bc89ef62ce7 76 static inline void i2c_interface_enable(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 77 I2C_CONSET(obj) = 0x40;
emilmont 10:3bc89ef62ce7 78 }
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 static inline void i2c_power_enable(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 81 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
emilmont 10:3bc89ef62ce7 82 LPC_SYSCON->PRESETCTRL |= 1 << 1;
emilmont 10:3bc89ef62ce7 83 }
emilmont 10:3bc89ef62ce7 84
emilmont 10:3bc89ef62ce7 85 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
emilmont 10:3bc89ef62ce7 86 // determine the SPI to use
emilmont 10:3bc89ef62ce7 87 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
emilmont 10:3bc89ef62ce7 88 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
emilmont 10:3bc89ef62ce7 89 obj->i2c = (LPC_I2C_Type *)pinmap_merge(i2c_sda, i2c_scl);
emilmont 10:3bc89ef62ce7 90
emilmont 10:3bc89ef62ce7 91 if ((int)obj->i2c == NC) {
emilmont 10:3bc89ef62ce7 92 error("I2C pin mapping failed");
emilmont 10:3bc89ef62ce7 93 }
emilmont 10:3bc89ef62ce7 94
emilmont 10:3bc89ef62ce7 95 // enable power
emilmont 10:3bc89ef62ce7 96 i2c_power_enable(obj);
emilmont 10:3bc89ef62ce7 97
emilmont 10:3bc89ef62ce7 98 // set default frequency at 100k
emilmont 10:3bc89ef62ce7 99 i2c_frequency(obj, 100000);
emilmont 10:3bc89ef62ce7 100 i2c_conclr(obj, 1, 1, 1, 1);
emilmont 10:3bc89ef62ce7 101 i2c_interface_enable(obj);
emilmont 10:3bc89ef62ce7 102
emilmont 10:3bc89ef62ce7 103 pinmap_pinout(sda, PinMap_I2C_SDA);
emilmont 10:3bc89ef62ce7 104 pinmap_pinout(scl, PinMap_I2C_SCL);
emilmont 10:3bc89ef62ce7 105 }
emilmont 10:3bc89ef62ce7 106
emilmont 10:3bc89ef62ce7 107 inline int i2c_start(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 108 int status = 0;
emilmont 10:3bc89ef62ce7 109 // 8.1 Before master mode can be entered, I2CON must be initialised to:
emilmont 10:3bc89ef62ce7 110 // - I2EN STA STO SI AA - -
emilmont 10:3bc89ef62ce7 111 // - 1 0 0 0 x - -
emilmont 10:3bc89ef62ce7 112 // if AA = 0, it can't enter slave mode
emilmont 10:3bc89ef62ce7 113 i2c_conclr(obj, 1, 1, 1, 1);
emilmont 10:3bc89ef62ce7 114
emilmont 10:3bc89ef62ce7 115 // The master mode may now be entered by setting the STA bit
emilmont 10:3bc89ef62ce7 116 // this will generate a start condition when the bus becomes free
emilmont 10:3bc89ef62ce7 117 i2c_conset(obj, 1, 0, 0, 1);
emilmont 10:3bc89ef62ce7 118
emilmont 10:3bc89ef62ce7 119 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 120 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 // Clear start bit now transmitted, and interrupt bit
emilmont 10:3bc89ef62ce7 123 i2c_conclr(obj, 1, 0, 0, 0);
emilmont 10:3bc89ef62ce7 124 return status;
emilmont 10:3bc89ef62ce7 125 }
emilmont 10:3bc89ef62ce7 126
emilmont 10:3bc89ef62ce7 127 inline void i2c_stop(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 128 // write the stop bit
emilmont 10:3bc89ef62ce7 129 i2c_conset(obj, 0, 1, 0, 0);
emilmont 10:3bc89ef62ce7 130 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 131
emilmont 10:3bc89ef62ce7 132 // wait for STO bit to reset
emilmont 10:3bc89ef62ce7 133 while(I2C_CONSET(obj) & (1 << 4));
emilmont 10:3bc89ef62ce7 134 }
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
emilmont 10:3bc89ef62ce7 138 // write the data
emilmont 10:3bc89ef62ce7 139 I2C_DAT(obj) = value;
emilmont 10:3bc89ef62ce7 140
emilmont 10:3bc89ef62ce7 141 // clear SI to init a send
emilmont 10:3bc89ef62ce7 142 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 143
emilmont 10:3bc89ef62ce7 144 // wait and return status
emilmont 10:3bc89ef62ce7 145 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 146 return i2c_status(obj);
emilmont 10:3bc89ef62ce7 147 }
emilmont 10:3bc89ef62ce7 148
emilmont 10:3bc89ef62ce7 149 static inline int i2c_do_read(i2c_t *obj, int last) {
emilmont 10:3bc89ef62ce7 150 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
emilmont 10:3bc89ef62ce7 151 if (last) {
emilmont 10:3bc89ef62ce7 152 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
emilmont 10:3bc89ef62ce7 153 } else {
emilmont 10:3bc89ef62ce7 154 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
emilmont 10:3bc89ef62ce7 155 }
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 // accept byte
emilmont 10:3bc89ef62ce7 158 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 // wait for it to arrive
emilmont 10:3bc89ef62ce7 161 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 162
emilmont 10:3bc89ef62ce7 163 // return the data
emilmont 10:3bc89ef62ce7 164 return (I2C_DAT(obj) & 0xFF);
emilmont 10:3bc89ef62ce7 165 }
emilmont 10:3bc89ef62ce7 166
emilmont 10:3bc89ef62ce7 167 void i2c_frequency(i2c_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 168 // No peripheral clock divider on the M0
emilmont 10:3bc89ef62ce7 169 uint32_t PCLK = SystemCoreClock;
emilmont 10:3bc89ef62ce7 170
emilmont 10:3bc89ef62ce7 171 uint32_t pulse = PCLK / (hz * 2);
emilmont 10:3bc89ef62ce7 172
emilmont 10:3bc89ef62ce7 173 // I2C Rate
emilmont 10:3bc89ef62ce7 174 I2C_SCLL(obj, pulse);
emilmont 10:3bc89ef62ce7 175 I2C_SCLH(obj, pulse);
emilmont 10:3bc89ef62ce7 176 }
emilmont 10:3bc89ef62ce7 177
emilmont 10:3bc89ef62ce7 178 // The I2C does a read or a write as a whole operation
emilmont 10:3bc89ef62ce7 179 // There are two types of error conditions it can encounter
emilmont 10:3bc89ef62ce7 180 // 1) it can not obtain the bus
emilmont 10:3bc89ef62ce7 181 // 2) it gets error responses at part of the transmission
emilmont 10:3bc89ef62ce7 182 //
emilmont 10:3bc89ef62ce7 183 // We tackle them as follows:
emilmont 10:3bc89ef62ce7 184 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
emilmont 10:3bc89ef62ce7 185 // which basically turns it in to a 2)
emilmont 10:3bc89ef62ce7 186 // 2) on error, we use the standard error mechanisms to report/debug
emilmont 10:3bc89ef62ce7 187 //
emilmont 10:3bc89ef62ce7 188 // Therefore an I2C transaction should always complete. If it doesn't it is usually
emilmont 10:3bc89ef62ce7 189 // because something is setup wrong (e.g. wiring), and we don't need to programatically
emilmont 10:3bc89ef62ce7 190 // check for that
emilmont 10:3bc89ef62ce7 191
emilmont 10:3bc89ef62ce7 192 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
emilmont 10:3bc89ef62ce7 193 int count, status;
emilmont 10:3bc89ef62ce7 194
emilmont 10:3bc89ef62ce7 195 status = i2c_start(obj);
emilmont 10:3bc89ef62ce7 196
emilmont 10:3bc89ef62ce7 197 if ((status != 0x10) && (status != 0x08)) {
emilmont 10:3bc89ef62ce7 198 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 199 return status;
emilmont 10:3bc89ef62ce7 200 }
emilmont 10:3bc89ef62ce7 201
emilmont 10:3bc89ef62ce7 202 status = i2c_do_write(obj, (address | 0x01), 1);
emilmont 10:3bc89ef62ce7 203 if (status != 0x40) {
emilmont 10:3bc89ef62ce7 204 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 205 return status;
emilmont 10:3bc89ef62ce7 206 }
emilmont 10:3bc89ef62ce7 207
emilmont 10:3bc89ef62ce7 208 // Read in all except last byte
emilmont 10:3bc89ef62ce7 209 for (count = 0; count < (length - 1); count++) {
emilmont 10:3bc89ef62ce7 210 int value = i2c_do_read(obj, 0);
emilmont 10:3bc89ef62ce7 211 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 212 if (status != 0x50) {
emilmont 10:3bc89ef62ce7 213 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 214 return status;
emilmont 10:3bc89ef62ce7 215 }
emilmont 10:3bc89ef62ce7 216 data[count] = (char) value;
emilmont 10:3bc89ef62ce7 217 }
emilmont 10:3bc89ef62ce7 218
emilmont 10:3bc89ef62ce7 219 // read in last byte
emilmont 10:3bc89ef62ce7 220 int value = i2c_do_read(obj, 1);
emilmont 10:3bc89ef62ce7 221 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 222 if (status != 0x58) {
emilmont 10:3bc89ef62ce7 223 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 224 return status;
emilmont 10:3bc89ef62ce7 225 }
emilmont 10:3bc89ef62ce7 226
emilmont 10:3bc89ef62ce7 227 data[count] = (char) value;
emilmont 10:3bc89ef62ce7 228
emilmont 10:3bc89ef62ce7 229 // If not repeated start, send stop.
emilmont 10:3bc89ef62ce7 230 if (stop) {
emilmont 10:3bc89ef62ce7 231 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 232 }
emilmont 10:3bc89ef62ce7 233
emilmont 10:3bc89ef62ce7 234 return 0;
emilmont 10:3bc89ef62ce7 235 }
emilmont 10:3bc89ef62ce7 236
emilmont 10:3bc89ef62ce7 237 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
emilmont 10:3bc89ef62ce7 238 int i, status;
emilmont 10:3bc89ef62ce7 239
emilmont 10:3bc89ef62ce7 240 status = i2c_start(obj);
emilmont 10:3bc89ef62ce7 241
emilmont 10:3bc89ef62ce7 242 if ((status != 0x10) && (status != 0x08)) {
emilmont 10:3bc89ef62ce7 243 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 244 return status;
emilmont 10:3bc89ef62ce7 245 }
emilmont 10:3bc89ef62ce7 246
emilmont 10:3bc89ef62ce7 247 status = i2c_do_write(obj, (address & 0xFE), 1);
emilmont 10:3bc89ef62ce7 248 if (status != 0x18) {
emilmont 10:3bc89ef62ce7 249 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 250 return status;
emilmont 10:3bc89ef62ce7 251 }
emilmont 10:3bc89ef62ce7 252
emilmont 10:3bc89ef62ce7 253 for (i=0; i<length; i++) {
emilmont 10:3bc89ef62ce7 254 status = i2c_do_write(obj, data[i], 0);
emilmont 10:3bc89ef62ce7 255 if(status != 0x28) {
emilmont 10:3bc89ef62ce7 256 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 257 return status;
emilmont 10:3bc89ef62ce7 258 }
emilmont 10:3bc89ef62ce7 259 }
emilmont 10:3bc89ef62ce7 260
emilmont 10:3bc89ef62ce7 261 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 262
emilmont 10:3bc89ef62ce7 263 // If not repeated start, send stop.
emilmont 10:3bc89ef62ce7 264 if (stop) {
emilmont 10:3bc89ef62ce7 265 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 266 }
emilmont 10:3bc89ef62ce7 267
emilmont 10:3bc89ef62ce7 268 return 0;
emilmont 10:3bc89ef62ce7 269 }
emilmont 10:3bc89ef62ce7 270
emilmont 10:3bc89ef62ce7 271 void i2c_reset(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 272 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 273 }
emilmont 10:3bc89ef62ce7 274
emilmont 10:3bc89ef62ce7 275 int i2c_byte_read(i2c_t *obj, int last) {
emilmont 10:3bc89ef62ce7 276 return (i2c_do_read(obj, last) & 0xFF);
emilmont 10:3bc89ef62ce7 277 }
emilmont 10:3bc89ef62ce7 278
emilmont 10:3bc89ef62ce7 279 int i2c_byte_write(i2c_t *obj, int data) {
emilmont 10:3bc89ef62ce7 280 int ack;
emilmont 10:3bc89ef62ce7 281 int status = i2c_do_write(obj, (data & 0xFF), 0);
emilmont 10:3bc89ef62ce7 282
emilmont 10:3bc89ef62ce7 283 switch(status) {
emilmont 10:3bc89ef62ce7 284 case 0x18: case 0x28: // Master transmit ACKs
emilmont 10:3bc89ef62ce7 285 ack = 1;
emilmont 10:3bc89ef62ce7 286 break;
emilmont 10:3bc89ef62ce7 287 case 0x40: // Master receive address transmitted ACK
emilmont 10:3bc89ef62ce7 288 ack = 1;
emilmont 10:3bc89ef62ce7 289 break;
emilmont 10:3bc89ef62ce7 290 case 0xB8: // Slave transmit ACK
emilmont 10:3bc89ef62ce7 291 ack = 1;
emilmont 10:3bc89ef62ce7 292 break;
emilmont 10:3bc89ef62ce7 293 default:
emilmont 10:3bc89ef62ce7 294 ack = 0;
emilmont 10:3bc89ef62ce7 295 break;
emilmont 10:3bc89ef62ce7 296 }
emilmont 10:3bc89ef62ce7 297
emilmont 10:3bc89ef62ce7 298 return ack;
emilmont 10:3bc89ef62ce7 299 }
emilmont 10:3bc89ef62ce7 300
emilmont 10:3bc89ef62ce7 301 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
emilmont 10:3bc89ef62ce7 302 if (enable_slave != 0) {
emilmont 10:3bc89ef62ce7 303 i2c_conclr(obj, 1, 1, 1, 0);
emilmont 10:3bc89ef62ce7 304 i2c_conset(obj, 0, 0, 0, 1);
emilmont 10:3bc89ef62ce7 305 } else {
emilmont 10:3bc89ef62ce7 306 i2c_conclr(obj, 1, 1, 1, 1);
emilmont 10:3bc89ef62ce7 307 }
emilmont 10:3bc89ef62ce7 308 }
emilmont 10:3bc89ef62ce7 309
emilmont 10:3bc89ef62ce7 310 int i2c_slave_receive(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 311 int status;
emilmont 10:3bc89ef62ce7 312 int retval;
emilmont 10:3bc89ef62ce7 313
emilmont 10:3bc89ef62ce7 314 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 315 switch(status) {
emilmont 10:3bc89ef62ce7 316 case 0x60: retval = 3; break;
emilmont 10:3bc89ef62ce7 317 case 0x70: retval = 2; break;
emilmont 10:3bc89ef62ce7 318 case 0xA8: retval = 1; break;
emilmont 10:3bc89ef62ce7 319 default : retval = 0; break;
emilmont 10:3bc89ef62ce7 320 }
emilmont 10:3bc89ef62ce7 321
emilmont 10:3bc89ef62ce7 322 return(retval);
emilmont 10:3bc89ef62ce7 323 }
emilmont 10:3bc89ef62ce7 324
emilmont 10:3bc89ef62ce7 325 int i2c_slave_read(i2c_t *obj, char *data, int length) {
emilmont 10:3bc89ef62ce7 326 int count = 0;
emilmont 10:3bc89ef62ce7 327 int status;
emilmont 10:3bc89ef62ce7 328
emilmont 10:3bc89ef62ce7 329 do {
emilmont 10:3bc89ef62ce7 330 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 331 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 332 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 333 if((status == 0x80) || (status == 0x90)) {
emilmont 10:3bc89ef62ce7 334 data[count] = I2C_DAT(obj) & 0xFF;
emilmont 10:3bc89ef62ce7 335 }
emilmont 10:3bc89ef62ce7 336 count++;
emilmont 10:3bc89ef62ce7 337 } while (((status == 0x80) || (status == 0x90) ||
emilmont 10:3bc89ef62ce7 338 (status == 0x060) || (status == 0x70)) && (count < length));
emilmont 10:3bc89ef62ce7 339
emilmont 10:3bc89ef62ce7 340 if(status != 0xA0) {
emilmont 10:3bc89ef62ce7 341 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 342 }
emilmont 10:3bc89ef62ce7 343
emilmont 10:3bc89ef62ce7 344 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 345
emilmont 10:3bc89ef62ce7 346 return (count - 1);
emilmont 10:3bc89ef62ce7 347 }
emilmont 10:3bc89ef62ce7 348
emilmont 10:3bc89ef62ce7 349 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
emilmont 10:3bc89ef62ce7 350 int count = 0;
emilmont 10:3bc89ef62ce7 351 int status;
emilmont 10:3bc89ef62ce7 352
emilmont 10:3bc89ef62ce7 353 if(length <= 0) {
emilmont 10:3bc89ef62ce7 354 return(0);
emilmont 10:3bc89ef62ce7 355 }
emilmont 10:3bc89ef62ce7 356
emilmont 10:3bc89ef62ce7 357 do {
emilmont 10:3bc89ef62ce7 358 status = i2c_do_write(obj, data[count], 0);
emilmont 10:3bc89ef62ce7 359 count++;
emilmont 10:3bc89ef62ce7 360 } while ((count < length) && (status == 0xB8));
emilmont 10:3bc89ef62ce7 361
emilmont 10:3bc89ef62ce7 362 if((status != 0xC0) && (status != 0xC8)) {
emilmont 10:3bc89ef62ce7 363 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 364 }
emilmont 10:3bc89ef62ce7 365
emilmont 10:3bc89ef62ce7 366 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 367
emilmont 10:3bc89ef62ce7 368 return(count);
emilmont 10:3bc89ef62ce7 369 }
emilmont 10:3bc89ef62ce7 370
emilmont 10:3bc89ef62ce7 371 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
emilmont 10:3bc89ef62ce7 372 uint32_t addr;
emilmont 10:3bc89ef62ce7 373
emilmont 10:3bc89ef62ce7 374 if ((idx >= 0) && (idx <= 3)) {
emilmont 10:3bc89ef62ce7 375 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
emilmont 10:3bc89ef62ce7 376 *((uint32_t *) addr) = address & 0xFF;
emilmont 10:3bc89ef62ce7 377 }
emilmont 10:3bc89ef62ce7 378 }