Shivanand Gowda / M95M02D

SPI EEPROM 2Mb M95M02 Read Write All functions

Dependents:   SPI_EEPROM_2MB

M95M02D.h@0:dc56262f5ce9, 2018-08-18 (annotated)

Committer:
shivanandgowdakr
Date:
Sat Aug 18 06:35:26 2018 +0000
Revision:
0:dc56262f5ce9
SPI EEPROM  2Mb  M95M02 Read Write All functions

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shivanandgowdakr 0:dc56262f5ce9 1 // M95M02D.h
shivanandgowdakr 0:dc56262f5ce9 2
shivanandgowdakr 0:dc56262f5ce9 3 #ifndef M95M02D_H
shivanandgowdakr 0:dc56262f5ce9 4 #define M95M02D_H
shivanandgowdakr 0:dc56262f5ce9 5
shivanandgowdakr 0:dc56262f5ce9 6 #include "mbed.h"
shivanandgowdakr 0:dc56262f5ce9 7 #include <string>
shivanandgowdakr 0:dc56262f5ce9 8
shivanandgowdakr 0:dc56262f5ce9 9 #define SPI_FREQ 5000000 //Change SPI Frequency Here
shivanandgowdakr 0:dc56262f5ce9 10 #define SPI_MODE 0 // SPI Mode can be 0 or 3 . see data sheet
shivanandgowdakr 0:dc56262f5ce9 11 #define SPI_NBIT 8 // Number of bits 8.
shivanandgowdakr 0:dc56262f5ce9 12
shivanandgowdakr 0:dc56262f5ce9 13
shivanandgowdakr 0:dc56262f5ce9 14
shivanandgowdakr 0:dc56262f5ce9 15 #define DUMMY_ADDR 0x00
shivanandgowdakr 0:dc56262f5ce9 16 #define WAIT_TIME 1
shivanandgowdakr 0:dc56262f5ce9 17
shivanandgowdakr 0:dc56262f5ce9 18 #define ADDR_BMASK3 0xff000000
shivanandgowdakr 0:dc56262f5ce9 19 #define ADDR_BMASK2 0x00ff0000
shivanandgowdakr 0:dc56262f5ce9 20 #define ADDR_BMASK1 0x0000ff00
shivanandgowdakr 0:dc56262f5ce9 21 #define ADDR_BMASK0 0x000000ff
shivanandgowdakr 0:dc56262f5ce9 22
shivanandgowdakr 0:dc56262f5ce9 23 #define ADDR_BSHIFT3 24
shivanandgowdakr 0:dc56262f5ce9 24 #define ADDR_BSHIFT2 16
shivanandgowdakr 0:dc56262f5ce9 25 #define ADDR_BSHIFT1 8
shivanandgowdakr 0:dc56262f5ce9 26 #define ADDR_BSHIFT0 0
shivanandgowdakr 0:dc56262f5ce9 27
shivanandgowdakr 0:dc56262f5ce9 28
shivanandgowdakr 0:dc56262f5ce9 29 #define READ 0x03 //0000 0011 Read data from memory array beginning at selected address
shivanandgowdakr 0:dc56262f5ce9 30 #define WRITE 0x02 //0000 0010 Write data to memory array beginning at selected address
shivanandgowdakr 0:dc56262f5ce9 31 #define WREN 0x06 //0000 0110 Set the write enable latch (enable write operations)
shivanandgowdakr 0:dc56262f5ce9 32 #define WRDI 0x04 //0000 0100 Reset the write enable latch (disable write operations)
shivanandgowdakr 0:dc56262f5ce9 33 #define RDSR 0x05 //0000 0101 Read STATUS register
shivanandgowdakr 0:dc56262f5ce9 34 #define WRSR 0x01 //0000 0001 Write STATUS register
shivanandgowdakr 0:dc56262f5ce9 35 #define PE 0x42 //0100 0010 Page Erase – erase one page in memory array
shivanandgowdakr 0:dc56262f5ce9 36 #define SE 0xD8 //1101 1000 Sector Erase – erase one sector in memory array
shivanandgowdakr 0:dc56262f5ce9 37 #define CE 0xC7 //1100 0111 Chip Erase – erase all sectors in memory array
shivanandgowdakr 0:dc56262f5ce9 38 #define ReadID 0x83 //1000 0011 Read id or electronic signature
shivanandgowdakr 0:dc56262f5ce9 39 #define WriteID 0x82 //1000 0011 Write id or electronic signature
shivanandgowdakr 0:dc56262f5ce9 40
shivanandgowdakr 0:dc56262f5ce9 41 #define DUMMYBYTE 0x00 //Dummy byte for Read Operation
shivanandgowdakr 0:dc56262f5ce9 42
shivanandgowdakr 0:dc56262f5ce9 43 class M95M02D: public SPI {
shivanandgowdakr 0:dc56262f5ce9 44 public:
shivanandgowdakr 0:dc56262f5ce9 45 M95M02D(PinName mosi, PinName miso, PinName sclk, PinName cs,PinName WP,PinName HOLD);
shivanandgowdakr 0:dc56262f5ce9 46
shivanandgowdakr 0:dc56262f5ce9 47
shivanandgowdakr 0:dc56262f5ce9 48
shivanandgowdakr 0:dc56262f5ce9 49
shivanandgowdakr 0:dc56262f5ce9 50 int readByte(int addr); // takes a 24-bit (3 bytes) address and returns the data (1 byte) at that location
shivanandgowdakr 0:dc56262f5ce9 51 void readStream(int addr, char* buf, int count); // takes a 24-bit address, reads count bytes, and stores results in buf
shivanandgowdakr 0:dc56262f5ce9 52 int ReadSignature(void);
shivanandgowdakr 0:dc56262f5ce9 53 void writeByte(int addr, int data); // takes a 24-bit (3 bytes) address and a byte of data to write at that location
shivanandgowdakr 0:dc56262f5ce9 54 void writeStream(int addr, char* buf, int count); // write count bytes of data from buf to memory, starting at addr
shivanandgowdakr 0:dc56262f5ce9 55 void writeString(int add, string str);
shivanandgowdakr 0:dc56262f5ce9 56 void writePage(int pageNo,char *buf,int count);
shivanandgowdakr 0:dc56262f5ce9 57 //erase all data on chip
shivanandgowdakr 0:dc56262f5ce9 58 uint8_t readRegister();
shivanandgowdakr 0:dc56262f5ce9 59 uint8_t checkIfBusy(); // Check if IC is bury writing or erasing
shivanandgowdakr 0:dc56262f5ce9 60 void writeRegister(uint8_t regValue); // Write status register or configuration register
shivanandgowdakr 0:dc56262f5ce9 61 long readLong(int address); // Read long int number
shivanandgowdakr 0:dc56262f5ce9 62 void writeLong(int addr, long value); // Write Long Integer Number
shivanandgowdakr 0:dc56262f5ce9 63 private:
shivanandgowdakr 0:dc56262f5ce9 64 void writeEnable(); // write enable
shivanandgowdakr 0:dc56262f5ce9 65 void writeDisable(); // write disable
shivanandgowdakr 0:dc56262f5ce9 66 void chipEnable(); // chip enable
shivanandgowdakr 0:dc56262f5ce9 67 void chipDisable(); // chip disable
shivanandgowdakr 0:dc56262f5ce9 68 void EnableWriteProtect();
shivanandgowdakr 0:dc56262f5ce9 69 void DisableWriteProtect();
shivanandgowdakr 0:dc56262f5ce9 70 void Hold_ReadWrite();
shivanandgowdakr 0:dc56262f5ce9 71 void ReleaseHold_ReadWrite();
shivanandgowdakr 0:dc56262f5ce9 72
shivanandgowdakr 0:dc56262f5ce9 73
shivanandgowdakr 0:dc56262f5ce9 74 // SPI _spi;
shivanandgowdakr 0:dc56262f5ce9 75 DigitalOut _cs;
shivanandgowdakr 0:dc56262f5ce9 76 DigitalOut _wp;
shivanandgowdakr 0:dc56262f5ce9 77 DigitalOut _hold;
shivanandgowdakr 0:dc56262f5ce9 78
shivanandgowdakr 0:dc56262f5ce9 79 };
shivanandgowdakr 0:dc56262f5ce9 80
shivanandgowdakr 0:dc56262f5ce9 81 #endif