Shivanand Gowda / M95M02D

SPI EEPROM 2Mb M95M02 Read Write All functions

Dependents:   SPI_EEPROM_2MB

M95M02D.cpp@0:dc56262f5ce9, 2018-08-18 (annotated)

Committer:
shivanandgowdakr
Date:
Sat Aug 18 06:35:26 2018 +0000
Revision:
0:dc56262f5ce9
SPI EEPROM  2Mb  M95M02 Read Write All functions

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shivanandgowdakr 0:dc56262f5ce9 1 // M95M02D.cpp
shivanandgowdakr 0:dc56262f5ce9 2 #include "mbed.h"
shivanandgowdakr 0:dc56262f5ce9 3 #include"M95M02D.h"
shivanandgowdakr 0:dc56262f5ce9 4
shivanandgowdakr 0:dc56262f5ce9 5 // CONSTRUCTOR
shivanandgowdakr 0:dc56262f5ce9 6 M95M02D::M95M02D(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName WP, PinName HOLD) : SPI(mosi, miso, sclk), _cs(cs),_wp(WP),_hold(HOLD)
shivanandgowdakr 0:dc56262f5ce9 7 {
shivanandgowdakr 0:dc56262f5ce9 8 this->format(SPI_NBIT, SPI_MODE);
shivanandgowdakr 0:dc56262f5ce9 9 this->frequency(SPI_FREQ);
shivanandgowdakr 0:dc56262f5ce9 10 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 11
shivanandgowdakr 0:dc56262f5ce9 12 }
shivanandgowdakr 0:dc56262f5ce9 13 // READING
shivanandgowdakr 0:dc56262f5ce9 14
shivanandgowdakr 0:dc56262f5ce9 15
shivanandgowdakr 0:dc56262f5ce9 16
shivanandgowdakr 0:dc56262f5ce9 17 int M95M02D::ReadSignature(void)
shivanandgowdakr 0:dc56262f5ce9 18 {
shivanandgowdakr 0:dc56262f5ce9 19 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 20 this->write(ReadID);
shivanandgowdakr 0:dc56262f5ce9 21 this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 22 this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 23 this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 24 int response = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 25 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 26 return response;
shivanandgowdakr 0:dc56262f5ce9 27 }
shivanandgowdakr 0:dc56262f5ce9 28
shivanandgowdakr 0:dc56262f5ce9 29
shivanandgowdakr 0:dc56262f5ce9 30 int M95M02D::readByte(int addr)
shivanandgowdakr 0:dc56262f5ce9 31 {
shivanandgowdakr 0:dc56262f5ce9 32 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 33 this->write(READ);
shivanandgowdakr 0:dc56262f5ce9 34 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 35 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 36 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 37 int response = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 38 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 39 return response;
shivanandgowdakr 0:dc56262f5ce9 40 }
shivanandgowdakr 0:dc56262f5ce9 41
shivanandgowdakr 0:dc56262f5ce9 42 void M95M02D::readStream(int addr, char* buf, int count)
shivanandgowdakr 0:dc56262f5ce9 43 {
shivanandgowdakr 0:dc56262f5ce9 44 if (count < 1)
shivanandgowdakr 0:dc56262f5ce9 45 return;
shivanandgowdakr 0:dc56262f5ce9 46 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 47 this->write(READ);
shivanandgowdakr 0:dc56262f5ce9 48 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 49 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 50 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 51 for (int i = 0; i < count; i++) {
shivanandgowdakr 0:dc56262f5ce9 52 buf[i] = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 53 // printf("i= %d :%c \r\n",i,buf[i]);
shivanandgowdakr 0:dc56262f5ce9 54 }
shivanandgowdakr 0:dc56262f5ce9 55 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 56 // wait_ms(2);
shivanandgowdakr 0:dc56262f5ce9 57 }
shivanandgowdakr 0:dc56262f5ce9 58
shivanandgowdakr 0:dc56262f5ce9 59 // WRITING
shivanandgowdakr 0:dc56262f5ce9 60 void M95M02D::writeByte(int addr, int data)
shivanandgowdakr 0:dc56262f5ce9 61 {
shivanandgowdakr 0:dc56262f5ce9 62 writeEnable();
shivanandgowdakr 0:dc56262f5ce9 63 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 64 this->write(WRITE);
shivanandgowdakr 0:dc56262f5ce9 65 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 66 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 67 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 68 this->write(data);
shivanandgowdakr 0:dc56262f5ce9 69 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 70 writeDisable();
shivanandgowdakr 0:dc56262f5ce9 71 wait_ms(2);
shivanandgowdakr 0:dc56262f5ce9 72 uint8_t busy= checkIfBusy();
shivanandgowdakr 0:dc56262f5ce9 73 while(busy==1)
shivanandgowdakr 0:dc56262f5ce9 74 {
shivanandgowdakr 0:dc56262f5ce9 75 //printf("Busy :%d\r\n",busy);
shivanandgowdakr 0:dc56262f5ce9 76 wait_ms(1);
shivanandgowdakr 0:dc56262f5ce9 77 busy= checkIfBusy();
shivanandgowdakr 0:dc56262f5ce9 78 }
shivanandgowdakr 0:dc56262f5ce9 79 // wait(WAIT_TIME);//instead of wait poll for WIP flag of status reg or use checkIfBusy() function...see main for more dtails
shivanandgowdakr 0:dc56262f5ce9 80 }
shivanandgowdakr 0:dc56262f5ce9 81
shivanandgowdakr 0:dc56262f5ce9 82 void M95M02D::writeStream(int addr, char* buf, int count)
shivanandgowdakr 0:dc56262f5ce9 83 {
shivanandgowdakr 0:dc56262f5ce9 84
shivanandgowdakr 0:dc56262f5ce9 85 if (count < 1)
shivanandgowdakr 0:dc56262f5ce9 86 return;
shivanandgowdakr 0:dc56262f5ce9 87
shivanandgowdakr 0:dc56262f5ce9 88 writeEnable();
shivanandgowdakr 0:dc56262f5ce9 89 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 90 this->write(WRITE);
shivanandgowdakr 0:dc56262f5ce9 91 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 92 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 93 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 94 for (int i = 0; i < count; i++) {
shivanandgowdakr 0:dc56262f5ce9 95 this->write(buf[i]);
shivanandgowdakr 0:dc56262f5ce9 96 }
shivanandgowdakr 0:dc56262f5ce9 97 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 98 writeDisable();
shivanandgowdakr 0:dc56262f5ce9 99 wait_ms(2);
shivanandgowdakr 0:dc56262f5ce9 100 uint8_t busy= checkIfBusy();
shivanandgowdakr 0:dc56262f5ce9 101 while(busy==1)
shivanandgowdakr 0:dc56262f5ce9 102 {
shivanandgowdakr 0:dc56262f5ce9 103 //printf("Busy :%d\r\n",busy);
shivanandgowdakr 0:dc56262f5ce9 104 wait_ms(1);
shivanandgowdakr 0:dc56262f5ce9 105 busy= checkIfBusy();
shivanandgowdakr 0:dc56262f5ce9 106 }
shivanandgowdakr 0:dc56262f5ce9 107 }
shivanandgowdakr 0:dc56262f5ce9 108
shivanandgowdakr 0:dc56262f5ce9 109 void M95M02D::writeString(int addr, string str)
shivanandgowdakr 0:dc56262f5ce9 110 {
shivanandgowdakr 0:dc56262f5ce9 111 if (str.length() < 1)
shivanandgowdakr 0:dc56262f5ce9 112 return;
shivanandgowdakr 0:dc56262f5ce9 113 writeEnable();
shivanandgowdakr 0:dc56262f5ce9 114 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 115 this->write(WRITE);
shivanandgowdakr 0:dc56262f5ce9 116 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 117 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 118 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 119 for (int i = 0; i < str.length(); i++)
shivanandgowdakr 0:dc56262f5ce9 120 this->write(str.at(i));
shivanandgowdakr 0:dc56262f5ce9 121 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 122 writeDisable();
shivanandgowdakr 0:dc56262f5ce9 123 wait_ms(6);//instead of wait poll for WIP flag of status reg or use checkIfBusy() function...see main for more dtails
shivanandgowdakr 0:dc56262f5ce9 124 }
shivanandgowdakr 0:dc56262f5ce9 125
shivanandgowdakr 0:dc56262f5ce9 126 void M95M02D::writePage(int pageNo,char *buf,int count)
shivanandgowdakr 0:dc56262f5ce9 127 {
shivanandgowdakr 0:dc56262f5ce9 128 int addr=0;
shivanandgowdakr 0:dc56262f5ce9 129 if(count >256)
shivanandgowdakr 0:dc56262f5ce9 130 {
shivanandgowdakr 0:dc56262f5ce9 131 printf("Cannot WRITE MORE THAN 256 BYTES Maximum Page Size is 256 bytes \r\n");
shivanandgowdakr 0:dc56262f5ce9 132 return;
shivanandgowdakr 0:dc56262f5ce9 133 }
shivanandgowdakr 0:dc56262f5ce9 134 else if(count <1)
shivanandgowdakr 0:dc56262f5ce9 135 {
shivanandgowdakr 0:dc56262f5ce9 136 printf("No data to Write \r\n");
shivanandgowdakr 0:dc56262f5ce9 137 return;
shivanandgowdakr 0:dc56262f5ce9 138 }
shivanandgowdakr 0:dc56262f5ce9 139
shivanandgowdakr 0:dc56262f5ce9 140 addr=pageNo*256;
shivanandgowdakr 0:dc56262f5ce9 141 writeEnable();
shivanandgowdakr 0:dc56262f5ce9 142 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 143 this->write(WRITE);
shivanandgowdakr 0:dc56262f5ce9 144 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 145 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 146 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 147 for (int i = 0; i < count; i++) {
shivanandgowdakr 0:dc56262f5ce9 148 this->write(buf[i]);
shivanandgowdakr 0:dc56262f5ce9 149 }
shivanandgowdakr 0:dc56262f5ce9 150 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 151 writeDisable();
shivanandgowdakr 0:dc56262f5ce9 152 wait_ms(2);
shivanandgowdakr 0:dc56262f5ce9 153 uint8_t busy= checkIfBusy();
shivanandgowdakr 0:dc56262f5ce9 154 while(busy==1)
shivanandgowdakr 0:dc56262f5ce9 155 {
shivanandgowdakr 0:dc56262f5ce9 156 //printf("Busy :%d\r\n",busy);
shivanandgowdakr 0:dc56262f5ce9 157 wait_ms(1);
shivanandgowdakr 0:dc56262f5ce9 158 busy= checkIfBusy();
shivanandgowdakr 0:dc56262f5ce9 159 }
shivanandgowdakr 0:dc56262f5ce9 160
shivanandgowdakr 0:dc56262f5ce9 161
shivanandgowdakr 0:dc56262f5ce9 162 }
shivanandgowdakr 0:dc56262f5ce9 163
shivanandgowdakr 0:dc56262f5ce9 164 uint8_t M95M02D::readRegister()
shivanandgowdakr 0:dc56262f5ce9 165 {
shivanandgowdakr 0:dc56262f5ce9 166
shivanandgowdakr 0:dc56262f5ce9 167 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 168 this->write(RDSR);
shivanandgowdakr 0:dc56262f5ce9 169 uint8_t val=this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 170 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 171 //wait(WAIT_TIME);//instead of wait poll for WIP flag of status reg or use checkIfBusy() function...see main for more dtails
shivanandgowdakr 0:dc56262f5ce9 172 //printf("value of reg is %X \r\n",val);
shivanandgowdakr 0:dc56262f5ce9 173 return(val);
shivanandgowdakr 0:dc56262f5ce9 174 }
shivanandgowdakr 0:dc56262f5ce9 175 //ERASING
shivanandgowdakr 0:dc56262f5ce9 176
shivanandgowdakr 0:dc56262f5ce9 177 uint8_t M95M02D::checkIfBusy()
shivanandgowdakr 0:dc56262f5ce9 178 {
shivanandgowdakr 0:dc56262f5ce9 179 uint8_t value=readRegister();
shivanandgowdakr 0:dc56262f5ce9 180 // printf("\r\n Value of Status Reg=%X\r\n\r\n",value);
shivanandgowdakr 0:dc56262f5ce9 181 if((value & 0x01)==0x01 )
shivanandgowdakr 0:dc56262f5ce9 182 {
shivanandgowdakr 0:dc56262f5ce9 183 wait_ms(1);
shivanandgowdakr 0:dc56262f5ce9 184 return 1;
shivanandgowdakr 0:dc56262f5ce9 185 }
shivanandgowdakr 0:dc56262f5ce9 186 else
shivanandgowdakr 0:dc56262f5ce9 187 {
shivanandgowdakr 0:dc56262f5ce9 188 wait_ms(1);
shivanandgowdakr 0:dc56262f5ce9 189 return 0;
shivanandgowdakr 0:dc56262f5ce9 190 }
shivanandgowdakr 0:dc56262f5ce9 191 }
shivanandgowdakr 0:dc56262f5ce9 192
shivanandgowdakr 0:dc56262f5ce9 193 void M95M02D::writeRegister(uint8_t regValue)
shivanandgowdakr 0:dc56262f5ce9 194 {
shivanandgowdakr 0:dc56262f5ce9 195 writeEnable();
shivanandgowdakr 0:dc56262f5ce9 196 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 197 this->write(WRSR);
shivanandgowdakr 0:dc56262f5ce9 198 this->write(regValue);
shivanandgowdakr 0:dc56262f5ce9 199 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 200 writeDisable();
shivanandgowdakr 0:dc56262f5ce9 201 wait(WAIT_TIME);//instead of wait poll for WIP flag of status reg or use checkIfBusy() function...see main for more dtails
shivanandgowdakr 0:dc56262f5ce9 202
shivanandgowdakr 0:dc56262f5ce9 203 }
shivanandgowdakr 0:dc56262f5ce9 204
shivanandgowdakr 0:dc56262f5ce9 205
shivanandgowdakr 0:dc56262f5ce9 206 void M95M02D::writeLong(int addr, long value)
shivanandgowdakr 0:dc56262f5ce9 207 {
shivanandgowdakr 0:dc56262f5ce9 208 //Decomposition from a long to 4 bytes by using bitshift.
shivanandgowdakr 0:dc56262f5ce9 209 //One = Most significant -> Four = Least significant byte
shivanandgowdakr 0:dc56262f5ce9 210 uint8_t four = (value & 0xFF);
shivanandgowdakr 0:dc56262f5ce9 211 uint8_t three = ((value >> 8) & 0xFF);
shivanandgowdakr 0:dc56262f5ce9 212 uint8_t two = ((value >> 16) & 0xFF);
shivanandgowdakr 0:dc56262f5ce9 213 uint8_t one = ((value >> 24) & 0xFF);
shivanandgowdakr 0:dc56262f5ce9 214
shivanandgowdakr 0:dc56262f5ce9 215 writeEnable();
shivanandgowdakr 0:dc56262f5ce9 216 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 217 this->write(WRITE);
shivanandgowdakr 0:dc56262f5ce9 218 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 219 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 220 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 221 this->write(four);
shivanandgowdakr 0:dc56262f5ce9 222 this->write(three);
shivanandgowdakr 0:dc56262f5ce9 223 this->write(two);
shivanandgowdakr 0:dc56262f5ce9 224 this->write(one);
shivanandgowdakr 0:dc56262f5ce9 225 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 226 writeDisable();
shivanandgowdakr 0:dc56262f5ce9 227 wait_ms(6);
shivanandgowdakr 0:dc56262f5ce9 228 }
shivanandgowdakr 0:dc56262f5ce9 229
shivanandgowdakr 0:dc56262f5ce9 230 long M95M02D::readLong(int addr)
shivanandgowdakr 0:dc56262f5ce9 231 {
shivanandgowdakr 0:dc56262f5ce9 232 //Read the 4 bytes from the eeprom memory.
shivanandgowdakr 0:dc56262f5ce9 233 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 234 this->write(READ);
shivanandgowdakr 0:dc56262f5ce9 235 this->write((addr & ADDR_BMASK2) >> ADDR_BSHIFT2);
shivanandgowdakr 0:dc56262f5ce9 236 this->write((addr & ADDR_BMASK1) >> ADDR_BSHIFT1);
shivanandgowdakr 0:dc56262f5ce9 237 this->write((addr & ADDR_BMASK0) >> ADDR_BSHIFT0);
shivanandgowdakr 0:dc56262f5ce9 238
shivanandgowdakr 0:dc56262f5ce9 239 long four = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 240 long three = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 241 long two = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 242 long one = this->write(DUMMY_ADDR);
shivanandgowdakr 0:dc56262f5ce9 243 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 244 //Return the recomposed long by using bitshift.
shivanandgowdakr 0:dc56262f5ce9 245 return ((four << 0) & 0xFF) + ((three << 8) & 0xFFFF) + ((two << 16) & 0xFFFFFF) + ((one << 24) & 0xFFFFFFFF);
shivanandgowdakr 0:dc56262f5ce9 246
shivanandgowdakr 0:dc56262f5ce9 247 }
shivanandgowdakr 0:dc56262f5ce9 248
shivanandgowdakr 0:dc56262f5ce9 249
shivanandgowdakr 0:dc56262f5ce9 250 //ENABLE/DISABLE (private functions)
shivanandgowdakr 0:dc56262f5ce9 251 void M95M02D::writeEnable()
shivanandgowdakr 0:dc56262f5ce9 252 {
shivanandgowdakr 0:dc56262f5ce9 253 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 254 this->write(WREN);
shivanandgowdakr 0:dc56262f5ce9 255 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 256 }
shivanandgowdakr 0:dc56262f5ce9 257 void M95M02D::writeDisable()
shivanandgowdakr 0:dc56262f5ce9 258 {
shivanandgowdakr 0:dc56262f5ce9 259 chipEnable();
shivanandgowdakr 0:dc56262f5ce9 260 this->write(WRDI);
shivanandgowdakr 0:dc56262f5ce9 261 chipDisable();
shivanandgowdakr 0:dc56262f5ce9 262 }
shivanandgowdakr 0:dc56262f5ce9 263 void M95M02D::chipEnable()
shivanandgowdakr 0:dc56262f5ce9 264 {
shivanandgowdakr 0:dc56262f5ce9 265 _cs = 0;
shivanandgowdakr 0:dc56262f5ce9 266 }
shivanandgowdakr 0:dc56262f5ce9 267 void M95M02D::chipDisable()
shivanandgowdakr 0:dc56262f5ce9 268 {
shivanandgowdakr 0:dc56262f5ce9 269 _cs = 1;
shivanandgowdakr 0:dc56262f5ce9 270 }
shivanandgowdakr 0:dc56262f5ce9 271
shivanandgowdakr 0:dc56262f5ce9 272 void M95M02D::EnableWriteProtect()
shivanandgowdakr 0:dc56262f5ce9 273 {
shivanandgowdakr 0:dc56262f5ce9 274 _wp = 0;
shivanandgowdakr 0:dc56262f5ce9 275 }
shivanandgowdakr 0:dc56262f5ce9 276 void M95M02D::DisableWriteProtect()
shivanandgowdakr 0:dc56262f5ce9 277 {
shivanandgowdakr 0:dc56262f5ce9 278 _wp = 1;
shivanandgowdakr 0:dc56262f5ce9 279 }
shivanandgowdakr 0:dc56262f5ce9 280
shivanandgowdakr 0:dc56262f5ce9 281 void M95M02D::Hold_ReadWrite()
shivanandgowdakr 0:dc56262f5ce9 282 {
shivanandgowdakr 0:dc56262f5ce9 283 _hold = 0;
shivanandgowdakr 0:dc56262f5ce9 284 }
shivanandgowdakr 0:dc56262f5ce9 285 void M95M02D::ReleaseHold_ReadWrite()
shivanandgowdakr 0:dc56262f5ce9 286 {
shivanandgowdakr 0:dc56262f5ce9 287 _hold = 1;
shivanandgowdakr 0:dc56262f5ce9 288 }