Shivanand Gowda / EE25LC1024

128K Serial EEPROM read write erase chip erase functions SPI EEPROM Nucleo F767ZI

Dependents:   SPI_EEPROM

EE25LC1024.h@2:156c427681f0, 2018-10-23 (annotated)

Committer:
shivanandgowdakr
Date:
Tue Oct 23 10:22:19 2018 +0000
Revision:
2:156c427681f0
Parent:
0:81848bf6dd4a 
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Who changed what in which revision?

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shivanandgowdakr 0:81848bf6dd4a 1 // EE25LC1024.h
shivanandgowdakr 0:81848bf6dd4a 2
shivanandgowdakr 0:81848bf6dd4a 3 #ifndef EE25LC1024_H
shivanandgowdakr 0:81848bf6dd4a 4 #define EE25LC1024_H
shivanandgowdakr 0:81848bf6dd4a 5
shivanandgowdakr 0:81848bf6dd4a 6 #include "mbed.h"
shivanandgowdakr 0:81848bf6dd4a 7 #include <string>
shivanandgowdakr 0:81848bf6dd4a 8
shivanandgowdakr 2:156c427681f0 9 #define SPI_Freq 10000000 //Change SPI Frequency Here
shivanandgowdakr 0:81848bf6dd4a 10 #define SPI_MODE 0 // SPI Mode can be 0 or 3 . see data sheet
shivanandgowdakr 0:81848bf6dd4a 11 #define SPI_NBIT 8 // Number of bits 8.
shivanandgowdakr 0:81848bf6dd4a 12
shivanandgowdakr 0:81848bf6dd4a 13
shivanandgowdakr 0:81848bf6dd4a 14
shivanandgowdakr 0:81848bf6dd4a 15 #define DUMMY_ADDR 0x00
shivanandgowdakr 0:81848bf6dd4a 16 #define WAIT_TIME 1
shivanandgowdakr 0:81848bf6dd4a 17
shivanandgowdakr 0:81848bf6dd4a 18 #define ADDR_BMASK3 0xff000000
shivanandgowdakr 0:81848bf6dd4a 19 #define ADDR_BMASK2 0x00ff0000
shivanandgowdakr 0:81848bf6dd4a 20 #define ADDR_BMASK1 0x0000ff00
shivanandgowdakr 0:81848bf6dd4a 21 #define ADDR_BMASK0 0x000000ff
shivanandgowdakr 0:81848bf6dd4a 22
shivanandgowdakr 0:81848bf6dd4a 23 #define ADDR_BSHIFT3 24
shivanandgowdakr 0:81848bf6dd4a 24 #define ADDR_BSHIFT2 16
shivanandgowdakr 0:81848bf6dd4a 25 #define ADDR_BSHIFT1 8
shivanandgowdakr 0:81848bf6dd4a 26 #define ADDR_BSHIFT0 0
shivanandgowdakr 0:81848bf6dd4a 27
shivanandgowdakr 0:81848bf6dd4a 28
shivanandgowdakr 0:81848bf6dd4a 29 #define READ 0x03 //0000 0011 Read data from memory array beginning at selected address
shivanandgowdakr 0:81848bf6dd4a 30 #define WRITE 0x02 //0000 0010 Write data to memory array beginning at selected address
shivanandgowdakr 0:81848bf6dd4a 31 #define WREN 0x06 //0000 0110 Set the write enable latch (enable write operations)
shivanandgowdakr 0:81848bf6dd4a 32 #define WRDI 0x04 //0000 0100 Reset the write enable latch (disable write operations)
shivanandgowdakr 0:81848bf6dd4a 33 #define RDSR 0x05 //0000 0101 Read STATUS register
shivanandgowdakr 0:81848bf6dd4a 34 #define WRSR 0x01 //0000 0001 Write STATUS register
shivanandgowdakr 0:81848bf6dd4a 35 #define PE 0x42 //0100 0010 Page Erase – erase one page in memory array
shivanandgowdakr 0:81848bf6dd4a 36 #define SE 0xD8 //1101 1000 Sector Erase – erase one sector in memory array
shivanandgowdakr 0:81848bf6dd4a 37 #define CE 0xC7 //1100 0111 Chip Erase – erase all sectors in memory array
shivanandgowdakr 2:156c427681f0 38 #define Readid 0xAB //1010 1011 Release from Deep power-down and read electronic signature
shivanandgowdakr 0:81848bf6dd4a 39 #define DPD 0xB9 //1011 1001 Deep Power-Down mode
shivanandgowdakr 0:81848bf6dd4a 40 #define DUMMYBYTE 0x00 //Dummy byte for Read Operation
shivanandgowdakr 0:81848bf6dd4a 41
shivanandgowdakr 0:81848bf6dd4a 42 class EE25LC1024: public SPI {
shivanandgowdakr 0:81848bf6dd4a 43 public:
shivanandgowdakr 0:81848bf6dd4a 44 EE25LC1024(PinName mosi, PinName miso, PinName sclk, PinName cs);
shivanandgowdakr 0:81848bf6dd4a 45
shivanandgowdakr 0:81848bf6dd4a 46 void deepPowerDown(void);
shivanandgowdakr 0:81848bf6dd4a 47
shivanandgowdakr 0:81848bf6dd4a 48
shivanandgowdakr 0:81848bf6dd4a 49 int readByte(int addr); // takes a 24-bit (3 bytes) address and returns the data (1 byte) at that location
shivanandgowdakr 0:81848bf6dd4a 50 void readStream(int addr, char* buf, int count); // takes a 24-bit address, reads count bytes, and stores results in buf
shivanandgowdakr 0:81848bf6dd4a 51 int ReleaseDPD_ReadSign(void);
shivanandgowdakr 0:81848bf6dd4a 52 void writeByte(int addr, int data); // takes a 24-bit (3 bytes) address and a byte of data to write at that location
shivanandgowdakr 0:81848bf6dd4a 53 void writeStream(int addr, char* buf, int count); // write count bytes of data from buf to memory, starting at addr
shivanandgowdakr 0:81848bf6dd4a 54 void writeString(int add, string str);
shivanandgowdakr 0:81848bf6dd4a 55 void sectorErase(int addr);
shivanandgowdakr 0:81848bf6dd4a 56 void pageErase(int addr);
shivanandgowdakr 0:81848bf6dd4a 57 void chipErase(); //erase all data on chip
shivanandgowdakr 0:81848bf6dd4a 58 uint8_t readRegister();
shivanandgowdakr 0:81848bf6dd4a 59 uint8_t checkIfBusy(); // Check if IC is bury writing or erasing
shivanandgowdakr 0:81848bf6dd4a 60 void writeRegister(uint8_t regValue); // Write status register or configuration register
shivanandgowdakr 2:156c427681f0 61 long readLong(int address); // Read long int number
shivanandgowdakr 0:81848bf6dd4a 62 void writeLong(int addr, long value); // Write Long Integer Number
shivanandgowdakr 0:81848bf6dd4a 63 private:
shivanandgowdakr 0:81848bf6dd4a 64 void writeEnable(); // write enable
shivanandgowdakr 0:81848bf6dd4a 65 void writeDisable(); // write disable
shivanandgowdakr 0:81848bf6dd4a 66 void chipEnable(); // chip enable
shivanandgowdakr 0:81848bf6dd4a 67 void chipDisable();
shivanandgowdakr 0:81848bf6dd4a 68 // chip disable
shivanandgowdakr 0:81848bf6dd4a 69
shivanandgowdakr 0:81848bf6dd4a 70 // SPI _spi;
shivanandgowdakr 0:81848bf6dd4a 71 DigitalOut _cs;
shivanandgowdakr 0:81848bf6dd4a 72 };
shivanandgowdakr 0:81848bf6dd4a 73
shivanandgowdakr 0:81848bf6dd4a 74 #endif