Atsushi Shinbo / Mbed 2 deprecated CS8416_SPI

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Dependencies:   mbed

main.cpp@0:cb6ecbfcf585, 2014-03-30 (annotated)

Committer:
shinbo
Date:
Sun Mar 30 19:34:20 2014 +0000
Revision:
0:cb6ecbfcf585
Child:
1:f468352a5408
this program control CS8416 in software mode(SPI) with LPC1114FN2.; CS8416 : 192 kHz Digital Audio Interface Receiver; http://www.cirrus.com/jp/pubs/proDatasheet/CS8416_F3.pdf;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shinbo 0:cb6ecbfcf585 1 #include "mbed.h"
shinbo 0:cb6ecbfcf585 2
shinbo 0:cb6ecbfcf585 3 // this program control CS8416 in software mode(SPI) with LPC1114FN2.
shinbo 0:cb6ecbfcf585 4
shinbo 0:cb6ecbfcf585 5 // CS8416 : 192 kHz Digital Audio Interface Receiver
shinbo 0:cb6ecbfcf585 6 // http://www.cirrus.com/jp/pubs/proDatasheet/CS8416_F3.pdf
shinbo 0:cb6ecbfcf585 7
shinbo 0:cb6ecbfcf585 8 // FN1242A : 24bit/192KHz/2ch DAC
shinbo 0:cb6ecbfcf585 9 // http://akizukidenshi.com/download/ds/niigataseimitsu/FN1242Ajspec.pdf
shinbo 0:cb6ecbfcf585 10
shinbo 0:cb6ecbfcf585 11
shinbo 0:cb6ecbfcf585 12 // LPC1114FN28 connect to
shinbo 0:cb6ecbfcf585 13 // 1 MISO cs8416 / CDOUT
shinbo 0:cb6ecbfcf585 14 // 2 MOSI cs8416 / CDIN
shinbo 0:cb6ecbfcf585 15 // 3 SWCLK LPC-Link
shinbo 0:cb6ecbfcf585 16 // 4 PIO cs8416 / CS
shinbo 0:cb6ecbfcf585 17 // 6 SCK cs8416 / CCLK
shinbo 0:cb6ecbfcf585 18 // 7 AVIN 3.3V
shinbo 0:cb6ecbfcf585 19 // 8 AGND
shinbo 0:cb6ecbfcf585 20 // 9 PIO toggle switch : input source select.
shinbo 0:cb6ecbfcf585 21 // 12 SWDIO LPC-Link
shinbo 0:cb6ecbfcf585 22 // 14 PIO cs8416 / reset
shinbo 0:cb6ecbfcf585 23 // 15 PIO led1 : left
shinbo 0:cb6ecbfcf585 24 // 16 PIO led2
shinbo 0:cb6ecbfcf585 25 // 17 PIO led3
shinbo 0:cb6ecbfcf585 26 // 18 PIO led4 : right
shinbo 0:cb6ecbfcf585 27 // 21 VIN 3.3V
shinbo 0:cb6ecbfcf585 28 // 22 GND
shinbo 0:cb6ecbfcf585 29 // 23 RESET LPC-Link
shinbo 0:cb6ecbfcf585 30 // 24 PIO fn1242a / ML
shinbo 0:cb6ecbfcf585 31 // 25 PIO fn1242a / MD
shinbo 0:cb6ecbfcf585 32 // 26 PIO fn1242a / MC
shinbo 0:cb6ecbfcf585 33
shinbo 0:cb6ecbfcf585 34 // CS8416
shinbo 0:cb6ecbfcf585 35 // RXP0 : S/PDIF TOSLINK input
shinbo 0:cb6ecbfcf585 36 // RXP1 : S/PDIF COAX input
shinbo 0:cb6ecbfcf585 37 // OMCK : 11.2896 MHz
shinbo 0:cb6ecbfcf585 38
shinbo 0:cb6ecbfcf585 39 SPI spi(dp2, dp1, dp6); // mosi, miso, sclk
shinbo 0:cb6ecbfcf585 40 DigitalOut pin_cs (dp4);
shinbo 0:cb6ecbfcf585 41 DigitalOut pin_rst (dp14);
shinbo 0:cb6ecbfcf585 42 DigitalOut pin_led1(dp15);
shinbo 0:cb6ecbfcf585 43 DigitalOut pin_led2(dp16);
shinbo 0:cb6ecbfcf585 44 DigitalOut pin_led3(dp17);
shinbo 0:cb6ecbfcf585 45 DigitalOut pin_led4(dp18);
shinbo 0:cb6ecbfcf585 46 DigitalIn pin_tgl (dp9);
shinbo 0:cb6ecbfcf585 47 DigitalOut pin_ML (dp24);
shinbo 0:cb6ecbfcf585 48 DigitalOut pin_MD (dp25);
shinbo 0:cb6ecbfcf585 49 DigitalOut pin_MC (dp26);
shinbo 0:cb6ecbfcf585 50
shinbo 0:cb6ecbfcf585 51
shinbo 0:cb6ecbfcf585 52 const uint8_t DEF_REGVAL[10] = {
shinbo 0:cb6ecbfcf585 53 0x00, // 0x00 : Control0
shinbo 0:cb6ecbfcf585 54 0x00, // 0x01 : Control1
shinbo 0:cb6ecbfcf585 55 0x48, // 0x02 : Control2 // EMPH_CNTL[2:0]=deemphasis filter auto select, GPO0SEL[3:0]=(96KHZ)
shinbo 0:cb6ecbfcf585 56 0x00, // 0x03 : Control3
shinbo 0:cb6ecbfcf585 57 0x80, // 0x04 : Control4 // RUN=normal part operation
shinbo 0:cb6ecbfcf585 58 0x85, // 0x05 : Serial Audio Data Format // SOMS=master mode, SODEL=second OSCLK period, SOLRPOL=right channel when OLRCK is high.
shinbo 0:cb6ecbfcf585 59 0x00, // 0x06 : Receiver Error Mask
shinbo 0:cb6ecbfcf585 60 0x00, // 0x07 : Interrupt Mask
shinbo 0:cb6ecbfcf585 61 0x00, // 0x08 : Interrupt Mode MSB
shinbo 0:cb6ecbfcf585 62 0x00 // 0x09 : Interrupt Mode LSB
shinbo 0:cb6ecbfcf585 63 };
shinbo 0:cb6ecbfcf585 64
shinbo 0:cb6ecbfcf585 65 uint32_t g_freq = 0;
shinbo 0:cb6ecbfcf585 66 uint8_t g_cur_frmt = 0;
shinbo 0:cb6ecbfcf585 67 uint32_t g_cur_tgl = 0;
shinbo 0:cb6ecbfcf585 68
shinbo 0:cb6ecbfcf585 69
shinbo 0:cb6ecbfcf585 70 void fn1242_write(uint16_t word) {
shinbo 0:cb6ecbfcf585 71
shinbo 0:cb6ecbfcf585 72 pin_ML = 1;
shinbo 0:cb6ecbfcf585 73
shinbo 0:cb6ecbfcf585 74 for (int iii = 0; iii < 16; iii++) {
shinbo 0:cb6ecbfcf585 75 pin_MC = 0;
shinbo 0:cb6ecbfcf585 76 pin_MD = (word & 0x8000) == 0 ? 0 : 1; // msb first
shinbo 0:cb6ecbfcf585 77 wait_us(10); // us
shinbo 0:cb6ecbfcf585 78
shinbo 0:cb6ecbfcf585 79 pin_MC = 1;
shinbo 0:cb6ecbfcf585 80 wait_us(10); // us
shinbo 0:cb6ecbfcf585 81
shinbo 0:cb6ecbfcf585 82 word = word << 1;
shinbo 0:cb6ecbfcf585 83 }
shinbo 0:cb6ecbfcf585 84
shinbo 0:cb6ecbfcf585 85 pin_MD = 0;
shinbo 0:cb6ecbfcf585 86 pin_MC = 0;
shinbo 0:cb6ecbfcf585 87 pin_ML = 0;
shinbo 0:cb6ecbfcf585 88 wait_us(10); // us
shinbo 0:cb6ecbfcf585 89
shinbo 0:cb6ecbfcf585 90 pin_ML = 1;
shinbo 0:cb6ecbfcf585 91 wait_us(10); // us
shinbo 0:cb6ecbfcf585 92 }
shinbo 0:cb6ecbfcf585 93
shinbo 0:cb6ecbfcf585 94 void fn1242_init() {
shinbo 0:cb6ecbfcf585 95
shinbo 0:cb6ecbfcf585 96 pin_ML = 1;
shinbo 0:cb6ecbfcf585 97 pin_MD = 0;
shinbo 0:cb6ecbfcf585 98 pin_MC = 0;
shinbo 0:cb6ecbfcf585 99 wait_us(10); // us
shinbo 0:cb6ecbfcf585 100
shinbo 0:cb6ecbfcf585 101 fn1242_write(
shinbo 0:cb6ecbfcf585 102 (2 << 11) // MODE2
shinbo 0:cb6ecbfcf585 103 | (0 << 9) // OM (default)
shinbo 0:cb6ecbfcf585 104 | (0 << 8) // RST (OFF/default)
shinbo 0:cb6ecbfcf585 105 | (2 << 6) // BIT (24bit)
shinbo 0:cb6ecbfcf585 106 | (0 << 4) // ZM (default)
shinbo 0:cb6ecbfcf585 107 | (0 << 3) // ATC (default)
shinbo 0:cb6ecbfcf585 108 | (0 << 2) // MUTE (OFF/default)
shinbo 0:cb6ecbfcf585 109 | (0 ) ); // EMPH (OFF/default)
shinbo 0:cb6ecbfcf585 110 }
shinbo 0:cb6ecbfcf585 111
shinbo 0:cb6ecbfcf585 112 void cs8416_write(uint8_t u8_addr, uint8_t u8_data) {
shinbo 0:cb6ecbfcf585 113 uint8_t u8_recv = 0;
shinbo 0:cb6ecbfcf585 114
shinbo 0:cb6ecbfcf585 115 pin_cs = 0;
shinbo 0:cb6ecbfcf585 116 wait_us(10); // us
shinbo 0:cb6ecbfcf585 117 u8_recv = spi.write(0x20);
shinbo 0:cb6ecbfcf585 118 u8_recv = spi.write(u8_addr);
shinbo 0:cb6ecbfcf585 119 u8_recv = spi.write(u8_data);
shinbo 0:cb6ecbfcf585 120 pin_cs = 1;
shinbo 0:cb6ecbfcf585 121 wait_us(10); // us
shinbo 0:cb6ecbfcf585 122 }
shinbo 0:cb6ecbfcf585 123
shinbo 0:cb6ecbfcf585 124
shinbo 0:cb6ecbfcf585 125 uint8_t cs8416_read(uint8_t u8_addr) {
shinbo 0:cb6ecbfcf585 126 uint8_t u8_recv = 0;
shinbo 0:cb6ecbfcf585 127
shinbo 0:cb6ecbfcf585 128 pin_cs = 0;
shinbo 0:cb6ecbfcf585 129 wait_us(10); // us
shinbo 0:cb6ecbfcf585 130 u8_recv = spi.write(0x20);
shinbo 0:cb6ecbfcf585 131 u8_recv = spi.write(u8_addr);
shinbo 0:cb6ecbfcf585 132 pin_cs = 1;
shinbo 0:cb6ecbfcf585 133 wait_us(10); // us
shinbo 0:cb6ecbfcf585 134
shinbo 0:cb6ecbfcf585 135 pin_cs = 0;
shinbo 0:cb6ecbfcf585 136 wait_us(10); // us
shinbo 0:cb6ecbfcf585 137 u8_recv = spi.write(0x21);
shinbo 0:cb6ecbfcf585 138 u8_recv = spi.write(0x00);
shinbo 0:cb6ecbfcf585 139 pin_cs = 1;
shinbo 0:cb6ecbfcf585 140 wait_us(10); // us
shinbo 0:cb6ecbfcf585 141
shinbo 0:cb6ecbfcf585 142 return u8_recv;
shinbo 0:cb6ecbfcf585 143 }
shinbo 0:cb6ecbfcf585 144
shinbo 0:cb6ecbfcf585 145
shinbo 0:cb6ecbfcf585 146 void cs8416_init() {
shinbo 0:cb6ecbfcf585 147
shinbo 0:cb6ecbfcf585 148 pin_rst = 0; // reset
shinbo 0:cb6ecbfcf585 149 wait_ms(100); // ms
shinbo 0:cb6ecbfcf585 150 pin_rst = 1;
shinbo 0:cb6ecbfcf585 151 wait_ms(1); // ms
shinbo 0:cb6ecbfcf585 152
shinbo 0:cb6ecbfcf585 153 // SPI Mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high.
shinbo 0:cb6ecbfcf585 154 pin_cs = 1; wait_ms(1);
shinbo 0:cb6ecbfcf585 155 pin_cs = 0; wait_ms(1); // enter SPI mode
shinbo 0:cb6ecbfcf585 156 pin_cs = 1; wait_ms(1);
shinbo 0:cb6ecbfcf585 157
shinbo 0:cb6ecbfcf585 158 for (int iii = 0; iii < 10; iii++) {
shinbo 0:cb6ecbfcf585 159 uint8_t u8_addr = (uint8_t) iii;
shinbo 0:cb6ecbfcf585 160 uint8_t u8_data = DEF_REGVAL[iii];
shinbo 0:cb6ecbfcf585 161 cs8416_write(u8_addr, u8_data);
shinbo 0:cb6ecbfcf585 162 }
shinbo 0:cb6ecbfcf585 163 }
shinbo 0:cb6ecbfcf585 164
shinbo 0:cb6ecbfcf585 165
shinbo 0:cb6ecbfcf585 166 void decide_freq(uint8_t u8_addr18) {
shinbo 0:cb6ecbfcf585 167
shinbo 0:cb6ecbfcf585 168 switch (u8_addr18) {
shinbo 0:cb6ecbfcf585 169 case 0x59:
shinbo 0:cb6ecbfcf585 170 case 0x58:
shinbo 0:cb6ecbfcf585 171 case 0x57: g_freq = 32; break;
shinbo 0:cb6ecbfcf585 172
shinbo 0:cb6ecbfcf585 173 case 0x40:
shinbo 0:cb6ecbfcf585 174 case 0x3f: g_freq = 44; break;
shinbo 0:cb6ecbfcf585 175
shinbo 0:cb6ecbfcf585 176 case 0x3b:
shinbo 0:cb6ecbfcf585 177 case 0x3a: g_freq = 48; break;
shinbo 0:cb6ecbfcf585 178
shinbo 0:cb6ecbfcf585 179 case 0x20:
shinbo 0:cb6ecbfcf585 180 case 0x1f: g_freq = 88; break;
shinbo 0:cb6ecbfcf585 181
shinbo 0:cb6ecbfcf585 182 case 0x1d:
shinbo 0:cb6ecbfcf585 183 case 0x1c: g_freq = 96; break;
shinbo 0:cb6ecbfcf585 184
shinbo 0:cb6ecbfcf585 185 case 0x10:
shinbo 0:cb6ecbfcf585 186 case 0x0f: g_freq = 176; break;
shinbo 0:cb6ecbfcf585 187
shinbo 0:cb6ecbfcf585 188 case 0x0e: g_freq = 192; break;
shinbo 0:cb6ecbfcf585 189
shinbo 0:cb6ecbfcf585 190 default: g_freq = 0; break;
shinbo 0:cb6ecbfcf585 191 }
shinbo 0:cb6ecbfcf585 192 }
shinbo 0:cb6ecbfcf585 193
shinbo 0:cb6ecbfcf585 194
shinbo 0:cb6ecbfcf585 195 void set_led() {
shinbo 0:cb6ecbfcf585 196 uint32_t u32_val = 0;
shinbo 0:cb6ecbfcf585 197
shinbo 0:cb6ecbfcf585 198 switch (g_freq) {
shinbo 0:cb6ecbfcf585 199 case 32: u32_val = 0x01; break; // 0001
shinbo 0:cb6ecbfcf585 200 case 44: u32_val = 0x02; break; // 0010
shinbo 0:cb6ecbfcf585 201 case 48: u32_val = 0x03; break; // 0011
shinbo 0:cb6ecbfcf585 202 case 88: u32_val = 0x04; break; // 0100
shinbo 0:cb6ecbfcf585 203 case 96: u32_val = 0x05; break; // 0101
shinbo 0:cb6ecbfcf585 204 case 176: u32_val = 0x06; break; // 0110
shinbo 0:cb6ecbfcf585 205 case 192: u32_val = 0x07; break; // 0111
shinbo 0:cb6ecbfcf585 206 }
shinbo 0:cb6ecbfcf585 207
shinbo 0:cb6ecbfcf585 208 pin_led4 = (u32_val & 1); u32_val = u32_val >> 1;
shinbo 0:cb6ecbfcf585 209 pin_led3 = (u32_val & 1); u32_val = u32_val >> 1;
shinbo 0:cb6ecbfcf585 210 pin_led2 = (u32_val & 1); u32_val = u32_val >> 1;
shinbo 0:cb6ecbfcf585 211 }
shinbo 0:cb6ecbfcf585 212
shinbo 0:cb6ecbfcf585 213
shinbo 0:cb6ecbfcf585 214 void set_rmckf() {
shinbo 0:cb6ecbfcf585 215 uint8_t u8_data = 0;
shinbo 0:cb6ecbfcf585 216
shinbo 0:cb6ecbfcf585 217 if (g_cur_frmt & 1) { // (0Bh)[0] 96KHZ - If the input sample rate is <= 48 kHz, outputs a "0". Outputs a "1" if the sample rate is >= 88.1 kHz. Otherwise the output is indeterminate.
shinbo 0:cb6ecbfcf585 218 pin_led1 = 1;
shinbo 0:cb6ecbfcf585 219 u8_data = 0x02; // (01h)[1] RMCKF - Recovered Master Clock Frequency @ 1 : 128 Fs
shinbo 0:cb6ecbfcf585 220 } else {
shinbo 0:cb6ecbfcf585 221 pin_led1 = 0;
shinbo 0:cb6ecbfcf585 222 u8_data = 0x00; // (01h)[1] RMCKF - Recovered Master Clock Frequency @ 0 : 256 Fs
shinbo 0:cb6ecbfcf585 223 }
shinbo 0:cb6ecbfcf585 224 cs8416_write(0x01, DEF_REGVAL[1] + u8_data); // (01h) : Control1
shinbo 0:cb6ecbfcf585 225 }
shinbo 0:cb6ecbfcf585 226
shinbo 0:cb6ecbfcf585 227
shinbo 0:cb6ecbfcf585 228 void set_source() {
shinbo 0:cb6ecbfcf585 229 uint8_t u8_data = 0;
shinbo 0:cb6ecbfcf585 230
shinbo 0:cb6ecbfcf585 231 if (g_cur_tgl & 1) {
shinbo 0:cb6ecbfcf585 232 u8_data = 0x08; // (04h)[5:3] RXSEL2:0
shinbo 0:cb6ecbfcf585 233 } else {
shinbo 0:cb6ecbfcf585 234 u8_data = 0x00; // (04h)[5:3] RXSEL2:0
shinbo 0:cb6ecbfcf585 235 }
shinbo 0:cb6ecbfcf585 236 cs8416_write(0x04, DEF_REGVAL[4] + u8_data); // (04h) : Control4
shinbo 0:cb6ecbfcf585 237 }
shinbo 0:cb6ecbfcf585 238
shinbo 0:cb6ecbfcf585 239
shinbo 0:cb6ecbfcf585 240 int main() {
shinbo 0:cb6ecbfcf585 241
shinbo 0:cb6ecbfcf585 242 spi.format(8, 3); // 8bit, mode3
shinbo 0:cb6ecbfcf585 243 spi.frequency(1000000); // 1MHz : default
shinbo 0:cb6ecbfcf585 244
shinbo 0:cb6ecbfcf585 245 cs8416_init();
shinbo 0:cb6ecbfcf585 246 fn1242_init();
shinbo 0:cb6ecbfcf585 247
shinbo 0:cb6ecbfcf585 248 while (1) {
shinbo 0:cb6ecbfcf585 249 uint8_t u8_addr18 = cs8416_read(0x18); // (18h) : OMCK/RMCK Ratio
shinbo 0:cb6ecbfcf585 250 decide_freq(u8_addr18);
shinbo 0:cb6ecbfcf585 251 set_led();
shinbo 0:cb6ecbfcf585 252
shinbo 0:cb6ecbfcf585 253 uint8_t u8_addr0B = cs8416_read(0x0b); // (0Bh) : Format Detect Status
shinbo 0:cb6ecbfcf585 254 if (g_cur_frmt != u8_addr0B) {
shinbo 0:cb6ecbfcf585 255 g_cur_frmt = u8_addr0B;
shinbo 0:cb6ecbfcf585 256 set_rmckf();
shinbo 0:cb6ecbfcf585 257 }
shinbo 0:cb6ecbfcf585 258
shinbo 0:cb6ecbfcf585 259 uint32_t u32_tgl = pin_tgl;
shinbo 0:cb6ecbfcf585 260 if (g_cur_tgl != u32_tgl) {
shinbo 0:cb6ecbfcf585 261 g_cur_tgl = u32_tgl;
shinbo 0:cb6ecbfcf585 262 set_source();
shinbo 0:cb6ecbfcf585 263 }
shinbo 0:cb6ecbfcf585 264
shinbo 0:cb6ecbfcf585 265 wait_ms(200); // ms
shinbo 0:cb6ecbfcf585 266 }
shinbo 0:cb6ecbfcf585 267 }