Angel David Yaguana Hernandez / USBDevice2

library

Dependents:   USB_CDC_MSD_Hello

USBDevice/USBBusInterface_LPC11U.cpp@0:d5bb9a9c3e24, 2012-08-24 (annotated)

Committer:
sherckuith
Date:
Fri Aug 24 02:01:51 2012 +0000
Revision:
0:d5bb9a9c3e24
[mbed] converted /USB_CDC_MSD_Hello/USBDevice

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sherckuith 0:d5bb9a9c3e24 1 // USBBusInterface_LPC11U.c
sherckuith 0:d5bb9a9c3e24 2 // USB Bus Interface for NXP LPC11Uxx
sherckuith 0:d5bb9a9c3e24 3 // Copyright (c) 2011 ARM Limited. All rights reserved.
sherckuith 0:d5bb9a9c3e24 4
sherckuith 0:d5bb9a9c3e24 5 // Reference:
sherckuith 0:d5bb9a9c3e24 6 // NXP UM10462 LPC11U1x User manual Rev. 1 � 14 April 2011
sherckuith 0:d5bb9a9c3e24 7
sherckuith 0:d5bb9a9c3e24 8 #ifdef TARGET_LPC11U24
sherckuith 0:d5bb9a9c3e24 9
sherckuith 0:d5bb9a9c3e24 10 #include "USBBusInterface.h"
sherckuith 0:d5bb9a9c3e24 11
sherckuith 0:d5bb9a9c3e24 12 USBHAL * USBHAL::instance;
sherckuith 0:d5bb9a9c3e24 13
sherckuith 0:d5bb9a9c3e24 14
sherckuith 0:d5bb9a9c3e24 15 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
sherckuith 0:d5bb9a9c3e24 16 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
sherckuith 0:d5bb9a9c3e24 17
sherckuith 0:d5bb9a9c3e24 18 // Convert physical endpoint number to register bit
sherckuith 0:d5bb9a9c3e24 19 #define EP(endpoint) (1UL<<endpoint)
sherckuith 0:d5bb9a9c3e24 20
sherckuith 0:d5bb9a9c3e24 21 // Convert physical to logical
sherckuith 0:d5bb9a9c3e24 22 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
sherckuith 0:d5bb9a9c3e24 23
sherckuith 0:d5bb9a9c3e24 24 // Get endpoint direction
sherckuith 0:d5bb9a9c3e24 25 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
sherckuith 0:d5bb9a9c3e24 26 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
sherckuith 0:d5bb9a9c3e24 27
sherckuith 0:d5bb9a9c3e24 28 // USB RAM
sherckuith 0:d5bb9a9c3e24 29 #define USB_RAM_START (0x20004000)
sherckuith 0:d5bb9a9c3e24 30 #define USB_RAM_SIZE (0x00000800)
sherckuith 0:d5bb9a9c3e24 31
sherckuith 0:d5bb9a9c3e24 32 // SYSAHBCLKCTRL
sherckuith 0:d5bb9a9c3e24 33 #define CLK_USB (1UL<<14)
sherckuith 0:d5bb9a9c3e24 34 #define CLK_USBRAM (1UL<<27)
sherckuith 0:d5bb9a9c3e24 35
sherckuith 0:d5bb9a9c3e24 36 // USB Information register
sherckuith 0:d5bb9a9c3e24 37 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
sherckuith 0:d5bb9a9c3e24 38
sherckuith 0:d5bb9a9c3e24 39 // USB Device Command/Status register
sherckuith 0:d5bb9a9c3e24 40 #define DEV_ADDR_MASK (0x7f) // Device address
sherckuith 0:d5bb9a9c3e24 41 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
sherckuith 0:d5bb9a9c3e24 42 #define DEV_EN (1UL<<7) // Device enable
sherckuith 0:d5bb9a9c3e24 43 #define SETUP (1UL<<8) // SETUP token received
sherckuith 0:d5bb9a9c3e24 44 #define PLL_ON (1UL<<9) // PLL enabled in suspend
sherckuith 0:d5bb9a9c3e24 45 #define DCON (1UL<<16) // Device status - connect
sherckuith 0:d5bb9a9c3e24 46 #define DSUS (1UL<<17) // Device status - suspend
sherckuith 0:d5bb9a9c3e24 47 #define DCON_C (1UL<<24) // Connect change
sherckuith 0:d5bb9a9c3e24 48 #define DSUS_C (1UL<<25) // Suspend change
sherckuith 0:d5bb9a9c3e24 49 #define DRES_C (1UL<<26) // Reset change
sherckuith 0:d5bb9a9c3e24 50 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
sherckuith 0:d5bb9a9c3e24 51
sherckuith 0:d5bb9a9c3e24 52 // Endpoint Command/Status list
sherckuith 0:d5bb9a9c3e24 53 #define CMDSTS_A (1UL<<31) // Active
sherckuith 0:d5bb9a9c3e24 54 #define CMDSTS_D (1UL<<30) // Disable
sherckuith 0:d5bb9a9c3e24 55 #define CMDSTS_S (1UL<<29) // Stall
sherckuith 0:d5bb9a9c3e24 56 #define CMDSTS_TR (1UL<<28) // Toggle Reset
sherckuith 0:d5bb9a9c3e24 57 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
sherckuith 0:d5bb9a9c3e24 58 #define CMDSTS_TV (1UL<<27) // Toggle Value
sherckuith 0:d5bb9a9c3e24 59 #define CMDSTS_T (1UL<<26) // Endpoint Type
sherckuith 0:d5bb9a9c3e24 60 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
sherckuith 0:d5bb9a9c3e24 61 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
sherckuith 0:d5bb9a9c3e24 62
sherckuith 0:d5bb9a9c3e24 63 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
sherckuith 0:d5bb9a9c3e24 64
sherckuith 0:d5bb9a9c3e24 65 // USB Non-endpoint interrupt sources
sherckuith 0:d5bb9a9c3e24 66 #define FRAME_INT (1UL<<30)
sherckuith 0:d5bb9a9c3e24 67 #define DEV_INT (1UL<<31)
sherckuith 0:d5bb9a9c3e24 68
sherckuith 0:d5bb9a9c3e24 69 static volatile int epComplete = 0;
sherckuith 0:d5bb9a9c3e24 70
sherckuith 0:d5bb9a9c3e24 71 // One entry for a double-buffered logical endpoint in the endpoint
sherckuith 0:d5bb9a9c3e24 72 // command/status list. Endpoint 0 is single buffered, out[1] is used
sherckuith 0:d5bb9a9c3e24 73 // for the SETUP packet and in[1] is not used
sherckuith 0:d5bb9a9c3e24 74 typedef __packed struct {
sherckuith 0:d5bb9a9c3e24 75 uint32_t out[2];
sherckuith 0:d5bb9a9c3e24 76 uint32_t in[2];
sherckuith 0:d5bb9a9c3e24 77 } EP_COMMAND_STATUS;
sherckuith 0:d5bb9a9c3e24 78
sherckuith 0:d5bb9a9c3e24 79 typedef __packed struct {
sherckuith 0:d5bb9a9c3e24 80 uint8_t out[MAX_PACKET_SIZE_EP0];
sherckuith 0:d5bb9a9c3e24 81 uint8_t in[MAX_PACKET_SIZE_EP0];
sherckuith 0:d5bb9a9c3e24 82 uint8_t setup[SETUP_PACKET_SIZE];
sherckuith 0:d5bb9a9c3e24 83 } CONTROL_TRANSFER;
sherckuith 0:d5bb9a9c3e24 84
sherckuith 0:d5bb9a9c3e24 85 typedef __packed struct {
sherckuith 0:d5bb9a9c3e24 86 uint32_t maxPacket;
sherckuith 0:d5bb9a9c3e24 87 uint32_t buffer[2];
sherckuith 0:d5bb9a9c3e24 88 uint32_t options;
sherckuith 0:d5bb9a9c3e24 89 } EP_STATE;
sherckuith 0:d5bb9a9c3e24 90
sherckuith 0:d5bb9a9c3e24 91 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
sherckuith 0:d5bb9a9c3e24 92
sherckuith 0:d5bb9a9c3e24 93 // Pointer to the endpoint command/status list
sherckuith 0:d5bb9a9c3e24 94 static EP_COMMAND_STATUS *ep = NULL;
sherckuith 0:d5bb9a9c3e24 95
sherckuith 0:d5bb9a9c3e24 96 // Pointer to endpoint 0 data (IN/OUT and SETUP)
sherckuith 0:d5bb9a9c3e24 97 static CONTROL_TRANSFER *ct = NULL;
sherckuith 0:d5bb9a9c3e24 98
sherckuith 0:d5bb9a9c3e24 99 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
sherckuith 0:d5bb9a9c3e24 100 // initiating a remote wakeup event.
sherckuith 0:d5bb9a9c3e24 101 static volatile uint32_t devCmdStat;
sherckuith 0:d5bb9a9c3e24 102
sherckuith 0:d5bb9a9c3e24 103 // Pointers used to allocate USB RAM
sherckuith 0:d5bb9a9c3e24 104 static uint32_t usbRamPtr = USB_RAM_START;
sherckuith 0:d5bb9a9c3e24 105 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
sherckuith 0:d5bb9a9c3e24 106
sherckuith 0:d5bb9a9c3e24 107 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
sherckuith 0:d5bb9a9c3e24 108
sherckuith 0:d5bb9a9c3e24 109 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
sherckuith 0:d5bb9a9c3e24 110 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
sherckuith 0:d5bb9a9c3e24 111 if (size > 0) {
sherckuith 0:d5bb9a9c3e24 112 do {
sherckuith 0:d5bb9a9c3e24 113 *dst++ = *src++;
sherckuith 0:d5bb9a9c3e24 114 } while (--size > 0);
sherckuith 0:d5bb9a9c3e24 115 }
sherckuith 0:d5bb9a9c3e24 116 }
sherckuith 0:d5bb9a9c3e24 117
sherckuith 0:d5bb9a9c3e24 118
sherckuith 0:d5bb9a9c3e24 119 USBHAL::USBHAL(void) {
sherckuith 0:d5bb9a9c3e24 120 NVIC_DisableIRQ(USB_IRQn);
sherckuith 0:d5bb9a9c3e24 121
sherckuith 0:d5bb9a9c3e24 122 // nUSB_CONNECT output
sherckuith 0:d5bb9a9c3e24 123 LPC_IOCON->PIO0_6 = 0x00000001;
sherckuith 0:d5bb9a9c3e24 124
sherckuith 0:d5bb9a9c3e24 125 // Enable clocks (USB registers, USB RAM)
sherckuith 0:d5bb9a9c3e24 126 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
sherckuith 0:d5bb9a9c3e24 127
sherckuith 0:d5bb9a9c3e24 128 // Ensure device disconnected (DCON not set)
sherckuith 0:d5bb9a9c3e24 129 LPC_USB->DEVCMDSTAT = 0;
sherckuith 0:d5bb9a9c3e24 130
sherckuith 0:d5bb9a9c3e24 131 // to ensure that the USB host sees the device as
sherckuith 0:d5bb9a9c3e24 132 // disconnected if the target CPU is reset.
sherckuith 0:d5bb9a9c3e24 133 wait(0.3);
sherckuith 0:d5bb9a9c3e24 134
sherckuith 0:d5bb9a9c3e24 135 // Reserve space in USB RAM for endpoint command/status list
sherckuith 0:d5bb9a9c3e24 136 // Must be 256 byte aligned
sherckuith 0:d5bb9a9c3e24 137 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
sherckuith 0:d5bb9a9c3e24 138 ep = (EP_COMMAND_STATUS *)usbRamPtr;
sherckuith 0:d5bb9a9c3e24 139 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
sherckuith 0:d5bb9a9c3e24 140 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
sherckuith 0:d5bb9a9c3e24 141
sherckuith 0:d5bb9a9c3e24 142 // Reserve space in USB RAM for Endpoint 0
sherckuith 0:d5bb9a9c3e24 143 // Must be 64 byte aligned
sherckuith 0:d5bb9a9c3e24 144 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
sherckuith 0:d5bb9a9c3e24 145 ct = (CONTROL_TRANSFER *)usbRamPtr;
sherckuith 0:d5bb9a9c3e24 146 usbRamPtr += sizeof(CONTROL_TRANSFER);
sherckuith 0:d5bb9a9c3e24 147 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
sherckuith 0:d5bb9a9c3e24 148
sherckuith 0:d5bb9a9c3e24 149 // Setup command/status list for EP0
sherckuith 0:d5bb9a9c3e24 150 ep[0].out[0] = 0;
sherckuith 0:d5bb9a9c3e24 151 ep[0].in[0] = 0;
sherckuith 0:d5bb9a9c3e24 152 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
sherckuith 0:d5bb9a9c3e24 153
sherckuith 0:d5bb9a9c3e24 154 // Route all interrupts to IRQ, some can be routed to
sherckuith 0:d5bb9a9c3e24 155 // USB_FIQ if you wish.
sherckuith 0:d5bb9a9c3e24 156 LPC_USB->INTROUTING = 0;
sherckuith 0:d5bb9a9c3e24 157
sherckuith 0:d5bb9a9c3e24 158 // Set device address 0, enable USB device, no remote wakeup
sherckuith 0:d5bb9a9c3e24 159 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
sherckuith 0:d5bb9a9c3e24 160 LPC_USB->DEVCMDSTAT = devCmdStat;
sherckuith 0:d5bb9a9c3e24 161
sherckuith 0:d5bb9a9c3e24 162 // Enable interrupts for device events and EP0
sherckuith 0:d5bb9a9c3e24 163 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
sherckuith 0:d5bb9a9c3e24 164 instance = this;
sherckuith 0:d5bb9a9c3e24 165
sherckuith 0:d5bb9a9c3e24 166 //attach IRQ handler and enable interrupts
sherckuith 0:d5bb9a9c3e24 167 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
sherckuith 0:d5bb9a9c3e24 168 NVIC_EnableIRQ(USB_IRQn);
sherckuith 0:d5bb9a9c3e24 169 }
sherckuith 0:d5bb9a9c3e24 170
sherckuith 0:d5bb9a9c3e24 171 USBHAL::~USBHAL(void) {
sherckuith 0:d5bb9a9c3e24 172 // Ensure device disconnected (DCON not set)
sherckuith 0:d5bb9a9c3e24 173 LPC_USB->DEVCMDSTAT = 0;
sherckuith 0:d5bb9a9c3e24 174
sherckuith 0:d5bb9a9c3e24 175 // Disable USB interrupts
sherckuith 0:d5bb9a9c3e24 176 NVIC_DisableIRQ(USB_IRQn);
sherckuith 0:d5bb9a9c3e24 177 }
sherckuith 0:d5bb9a9c3e24 178
sherckuith 0:d5bb9a9c3e24 179 void USBHAL::connect(void) {
sherckuith 0:d5bb9a9c3e24 180 devCmdStat |= DCON;
sherckuith 0:d5bb9a9c3e24 181 LPC_USB->DEVCMDSTAT = devCmdStat;
sherckuith 0:d5bb9a9c3e24 182 }
sherckuith 0:d5bb9a9c3e24 183
sherckuith 0:d5bb9a9c3e24 184 void USBHAL::disconnect(void) {
sherckuith 0:d5bb9a9c3e24 185 devCmdStat &= ~DCON;
sherckuith 0:d5bb9a9c3e24 186 LPC_USB->DEVCMDSTAT = devCmdStat;
sherckuith 0:d5bb9a9c3e24 187 }
sherckuith 0:d5bb9a9c3e24 188
sherckuith 0:d5bb9a9c3e24 189 void USBHAL::configureDevice(void) {
sherckuith 0:d5bb9a9c3e24 190 }
sherckuith 0:d5bb9a9c3e24 191
sherckuith 0:d5bb9a9c3e24 192 void USBHAL::unconfigureDevice(void) {
sherckuith 0:d5bb9a9c3e24 193 }
sherckuith 0:d5bb9a9c3e24 194
sherckuith 0:d5bb9a9c3e24 195 void USBHAL::EP0setup(uint8_t *buffer) {
sherckuith 0:d5bb9a9c3e24 196 // Copy setup packet data
sherckuith 0:d5bb9a9c3e24 197 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
sherckuith 0:d5bb9a9c3e24 198 }
sherckuith 0:d5bb9a9c3e24 199
sherckuith 0:d5bb9a9c3e24 200 void USBHAL::EP0read(void) {
sherckuith 0:d5bb9a9c3e24 201 // Start an endpoint 0 read
sherckuith 0:d5bb9a9c3e24 202
sherckuith 0:d5bb9a9c3e24 203 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
sherckuith 0:d5bb9a9c3e24 204 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
sherckuith 0:d5bb9a9c3e24 205 // read the data.
sherckuith 0:d5bb9a9c3e24 206
sherckuith 0:d5bb9a9c3e24 207 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
sherckuith 0:d5bb9a9c3e24 208 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
sherckuith 0:d5bb9a9c3e24 209 }
sherckuith 0:d5bb9a9c3e24 210
sherckuith 0:d5bb9a9c3e24 211 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
sherckuith 0:d5bb9a9c3e24 212 // Complete an endpoint 0 read
sherckuith 0:d5bb9a9c3e24 213 uint32_t bytesRead;
sherckuith 0:d5bb9a9c3e24 214
sherckuith 0:d5bb9a9c3e24 215 // Find how many bytes were read
sherckuith 0:d5bb9a9c3e24 216 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
sherckuith 0:d5bb9a9c3e24 217
sherckuith 0:d5bb9a9c3e24 218 // Copy data
sherckuith 0:d5bb9a9c3e24 219 USBMemCopy(buffer, ct->out, bytesRead);
sherckuith 0:d5bb9a9c3e24 220 return bytesRead;
sherckuith 0:d5bb9a9c3e24 221 }
sherckuith 0:d5bb9a9c3e24 222
sherckuith 0:d5bb9a9c3e24 223 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
sherckuith 0:d5bb9a9c3e24 224 // Start and endpoint 0 write
sherckuith 0:d5bb9a9c3e24 225
sherckuith 0:d5bb9a9c3e24 226 // The USB ISR will call USBDevice_EP0in() when the data has
sherckuith 0:d5bb9a9c3e24 227 // been written, the USBDevice layer then calls
sherckuith 0:d5bb9a9c3e24 228 // USBBusInterface_EP0getWriteResult() to complete the transaction.
sherckuith 0:d5bb9a9c3e24 229
sherckuith 0:d5bb9a9c3e24 230 // Copy data
sherckuith 0:d5bb9a9c3e24 231 USBMemCopy(ct->in, buffer, size);
sherckuith 0:d5bb9a9c3e24 232
sherckuith 0:d5bb9a9c3e24 233 // Start transfer
sherckuith 0:d5bb9a9c3e24 234 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
sherckuith 0:d5bb9a9c3e24 235 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
sherckuith 0:d5bb9a9c3e24 236 }
sherckuith 0:d5bb9a9c3e24 237
sherckuith 0:d5bb9a9c3e24 238
sherckuith 0:d5bb9a9c3e24 239 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
sherckuith 0:d5bb9a9c3e24 240 uint8_t bf = 0;
sherckuith 0:d5bb9a9c3e24 241 uint32_t flags = 0;
sherckuith 0:d5bb9a9c3e24 242
sherckuith 0:d5bb9a9c3e24 243 //check which buffer must be filled
sherckuith 0:d5bb9a9c3e24 244 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 245 // Double buffered
sherckuith 0:d5bb9a9c3e24 246 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 247 bf = 1;
sherckuith 0:d5bb9a9c3e24 248 } else {
sherckuith 0:d5bb9a9c3e24 249 bf = 0;
sherckuith 0:d5bb9a9c3e24 250 }
sherckuith 0:d5bb9a9c3e24 251 }
sherckuith 0:d5bb9a9c3e24 252
sherckuith 0:d5bb9a9c3e24 253 // if isochronous endpoint, T = 1
sherckuith 0:d5bb9a9c3e24 254 if(endpointState[endpoint].options & ISOCHRONOUS)
sherckuith 0:d5bb9a9c3e24 255 {
sherckuith 0:d5bb9a9c3e24 256 flags |= CMDSTS_T;
sherckuith 0:d5bb9a9c3e24 257 }
sherckuith 0:d5bb9a9c3e24 258
sherckuith 0:d5bb9a9c3e24 259 //Active the endpoint for reading
sherckuith 0:d5bb9a9c3e24 260 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
sherckuith 0:d5bb9a9c3e24 261 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
sherckuith 0:d5bb9a9c3e24 262 return EP_PENDING;
sherckuith 0:d5bb9a9c3e24 263 }
sherckuith 0:d5bb9a9c3e24 264
sherckuith 0:d5bb9a9c3e24 265 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
sherckuith 0:d5bb9a9c3e24 266
sherckuith 0:d5bb9a9c3e24 267 uint8_t bf = 0;
sherckuith 0:d5bb9a9c3e24 268
sherckuith 0:d5bb9a9c3e24 269 if (!(epComplete & EP(endpoint)))
sherckuith 0:d5bb9a9c3e24 270 return EP_PENDING;
sherckuith 0:d5bb9a9c3e24 271 else {
sherckuith 0:d5bb9a9c3e24 272 epComplete &= ~EP(endpoint);
sherckuith 0:d5bb9a9c3e24 273
sherckuith 0:d5bb9a9c3e24 274 //check which buffer has been filled
sherckuith 0:d5bb9a9c3e24 275 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 276 // Double buffered (here we read the previous buffer which was used)
sherckuith 0:d5bb9a9c3e24 277 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 278 bf = 0;
sherckuith 0:d5bb9a9c3e24 279 } else {
sherckuith 0:d5bb9a9c3e24 280 bf = 1;
sherckuith 0:d5bb9a9c3e24 281 }
sherckuith 0:d5bb9a9c3e24 282 }
sherckuith 0:d5bb9a9c3e24 283
sherckuith 0:d5bb9a9c3e24 284 // Find how many bytes were read
sherckuith 0:d5bb9a9c3e24 285 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
sherckuith 0:d5bb9a9c3e24 286
sherckuith 0:d5bb9a9c3e24 287 // Copy data
sherckuith 0:d5bb9a9c3e24 288 USBMemCopy(data, ct->out, *bytesRead);
sherckuith 0:d5bb9a9c3e24 289 return EP_COMPLETED;
sherckuith 0:d5bb9a9c3e24 290 }
sherckuith 0:d5bb9a9c3e24 291 }
sherckuith 0:d5bb9a9c3e24 292
sherckuith 0:d5bb9a9c3e24 293 void USBHAL::EP0getWriteResult(void) {
sherckuith 0:d5bb9a9c3e24 294 // Complete an endpoint 0 write
sherckuith 0:d5bb9a9c3e24 295
sherckuith 0:d5bb9a9c3e24 296 // Nothing required for this target
sherckuith 0:d5bb9a9c3e24 297 return;
sherckuith 0:d5bb9a9c3e24 298 }
sherckuith 0:d5bb9a9c3e24 299
sherckuith 0:d5bb9a9c3e24 300 void USBHAL::EP0stall(void) {
sherckuith 0:d5bb9a9c3e24 301 ep[0].in[0] = CMDSTS_S;
sherckuith 0:d5bb9a9c3e24 302 ep[0].out[0] = CMDSTS_S;
sherckuith 0:d5bb9a9c3e24 303 }
sherckuith 0:d5bb9a9c3e24 304
sherckuith 0:d5bb9a9c3e24 305 void USBHAL::setAddress(uint8_t address) {
sherckuith 0:d5bb9a9c3e24 306 devCmdStat &= ~DEV_ADDR_MASK;
sherckuith 0:d5bb9a9c3e24 307 devCmdStat |= DEV_ADDR(address);
sherckuith 0:d5bb9a9c3e24 308 LPC_USB->DEVCMDSTAT = devCmdStat;
sherckuith 0:d5bb9a9c3e24 309 }
sherckuith 0:d5bb9a9c3e24 310
sherckuith 0:d5bb9a9c3e24 311 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
sherckuith 0:d5bb9a9c3e24 312 uint32_t flags = 0;
sherckuith 0:d5bb9a9c3e24 313 uint32_t bf;
sherckuith 0:d5bb9a9c3e24 314
sherckuith 0:d5bb9a9c3e24 315 // Validate parameters
sherckuith 0:d5bb9a9c3e24 316 if (data == NULL) {
sherckuith 0:d5bb9a9c3e24 317 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 318 }
sherckuith 0:d5bb9a9c3e24 319
sherckuith 0:d5bb9a9c3e24 320 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
sherckuith 0:d5bb9a9c3e24 321 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 322 }
sherckuith 0:d5bb9a9c3e24 323
sherckuith 0:d5bb9a9c3e24 324 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
sherckuith 0:d5bb9a9c3e24 325 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 326 }
sherckuith 0:d5bb9a9c3e24 327
sherckuith 0:d5bb9a9c3e24 328 if (size > endpointState[endpoint].maxPacket) {
sherckuith 0:d5bb9a9c3e24 329 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 330 }
sherckuith 0:d5bb9a9c3e24 331
sherckuith 0:d5bb9a9c3e24 332 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 333 // Double buffered
sherckuith 0:d5bb9a9c3e24 334 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 335 bf = 1;
sherckuith 0:d5bb9a9c3e24 336 } else {
sherckuith 0:d5bb9a9c3e24 337 bf = 0;
sherckuith 0:d5bb9a9c3e24 338 }
sherckuith 0:d5bb9a9c3e24 339 } else {
sherckuith 0:d5bb9a9c3e24 340 // Single buffered
sherckuith 0:d5bb9a9c3e24 341 bf = 0;
sherckuith 0:d5bb9a9c3e24 342 }
sherckuith 0:d5bb9a9c3e24 343
sherckuith 0:d5bb9a9c3e24 344 // Check if already active
sherckuith 0:d5bb9a9c3e24 345 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
sherckuith 0:d5bb9a9c3e24 346 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 347 }
sherckuith 0:d5bb9a9c3e24 348
sherckuith 0:d5bb9a9c3e24 349 // Check if stalled
sherckuith 0:d5bb9a9c3e24 350 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
sherckuith 0:d5bb9a9c3e24 351 return EP_STALLED;
sherckuith 0:d5bb9a9c3e24 352 }
sherckuith 0:d5bb9a9c3e24 353
sherckuith 0:d5bb9a9c3e24 354 // Copy data to USB RAM
sherckuith 0:d5bb9a9c3e24 355 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
sherckuith 0:d5bb9a9c3e24 356
sherckuith 0:d5bb9a9c3e24 357 // Add options
sherckuith 0:d5bb9a9c3e24 358 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
sherckuith 0:d5bb9a9c3e24 359 flags |= CMDSTS_RF;
sherckuith 0:d5bb9a9c3e24 360 }
sherckuith 0:d5bb9a9c3e24 361
sherckuith 0:d5bb9a9c3e24 362 if (endpointState[endpoint].options & ISOCHRONOUS) {
sherckuith 0:d5bb9a9c3e24 363 flags |= CMDSTS_T;
sherckuith 0:d5bb9a9c3e24 364 }
sherckuith 0:d5bb9a9c3e24 365
sherckuith 0:d5bb9a9c3e24 366 // Add transfer
sherckuith 0:d5bb9a9c3e24 367 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
sherckuith 0:d5bb9a9c3e24 368 endpointState[endpoint].buffer[bf]) \
sherckuith 0:d5bb9a9c3e24 369 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
sherckuith 0:d5bb9a9c3e24 370
sherckuith 0:d5bb9a9c3e24 371 return EP_PENDING;
sherckuith 0:d5bb9a9c3e24 372 }
sherckuith 0:d5bb9a9c3e24 373
sherckuith 0:d5bb9a9c3e24 374 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
sherckuith 0:d5bb9a9c3e24 375 uint32_t bf;
sherckuith 0:d5bb9a9c3e24 376 // Validate parameters
sherckuith 0:d5bb9a9c3e24 377
sherckuith 0:d5bb9a9c3e24 378 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
sherckuith 0:d5bb9a9c3e24 379 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 380 }
sherckuith 0:d5bb9a9c3e24 381
sherckuith 0:d5bb9a9c3e24 382 if (OUT_EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 383 return EP_INVALID;
sherckuith 0:d5bb9a9c3e24 384 }
sherckuith 0:d5bb9a9c3e24 385
sherckuith 0:d5bb9a9c3e24 386 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 387 // Double buffered // TODO: FIX THIS
sherckuith 0:d5bb9a9c3e24 388 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 389 bf = 1;
sherckuith 0:d5bb9a9c3e24 390 } else {
sherckuith 0:d5bb9a9c3e24 391 bf = 0;
sherckuith 0:d5bb9a9c3e24 392 }
sherckuith 0:d5bb9a9c3e24 393 } else {
sherckuith 0:d5bb9a9c3e24 394 // Single buffered
sherckuith 0:d5bb9a9c3e24 395 bf = 0;
sherckuith 0:d5bb9a9c3e24 396 }
sherckuith 0:d5bb9a9c3e24 397
sherckuith 0:d5bb9a9c3e24 398 // Check if endpoint still active
sherckuith 0:d5bb9a9c3e24 399 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
sherckuith 0:d5bb9a9c3e24 400 return EP_PENDING;
sherckuith 0:d5bb9a9c3e24 401 }
sherckuith 0:d5bb9a9c3e24 402
sherckuith 0:d5bb9a9c3e24 403 // Check if stalled
sherckuith 0:d5bb9a9c3e24 404 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
sherckuith 0:d5bb9a9c3e24 405 return EP_STALLED;
sherckuith 0:d5bb9a9c3e24 406 }
sherckuith 0:d5bb9a9c3e24 407
sherckuith 0:d5bb9a9c3e24 408 return EP_COMPLETED;
sherckuith 0:d5bb9a9c3e24 409 }
sherckuith 0:d5bb9a9c3e24 410
sherckuith 0:d5bb9a9c3e24 411 void USBHAL::stallEndpoint(uint8_t endpoint) {
sherckuith 0:d5bb9a9c3e24 412
sherckuith 0:d5bb9a9c3e24 413 // TODO: should this clear active bit?
sherckuith 0:d5bb9a9c3e24 414
sherckuith 0:d5bb9a9c3e24 415 if (IN_EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 416 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
sherckuith 0:d5bb9a9c3e24 417 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
sherckuith 0:d5bb9a9c3e24 418 } else {
sherckuith 0:d5bb9a9c3e24 419 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
sherckuith 0:d5bb9a9c3e24 420 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
sherckuith 0:d5bb9a9c3e24 421 }
sherckuith 0:d5bb9a9c3e24 422 }
sherckuith 0:d5bb9a9c3e24 423
sherckuith 0:d5bb9a9c3e24 424 void USBHAL::unstallEndpoint(uint8_t endpoint) {
sherckuith 0:d5bb9a9c3e24 425 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 426 // Double buffered
sherckuith 0:d5bb9a9c3e24 427 if (IN_EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 428 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
sherckuith 0:d5bb9a9c3e24 429 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
sherckuith 0:d5bb9a9c3e24 430
sherckuith 0:d5bb9a9c3e24 431 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 432 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S =0, TR=1, TV = 0
sherckuith 0:d5bb9a9c3e24 433 } else {
sherckuith 0:d5bb9a9c3e24 434 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S =0, TR=1, TV = 0
sherckuith 0:d5bb9a9c3e24 435 }
sherckuith 0:d5bb9a9c3e24 436 } else {
sherckuith 0:d5bb9a9c3e24 437 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
sherckuith 0:d5bb9a9c3e24 438 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
sherckuith 0:d5bb9a9c3e24 439
sherckuith 0:d5bb9a9c3e24 440 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 441 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S =0, TR=1, TV = 0
sherckuith 0:d5bb9a9c3e24 442 } else {
sherckuith 0:d5bb9a9c3e24 443 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S =0, TR=1, TV = 0
sherckuith 0:d5bb9a9c3e24 444 }
sherckuith 0:d5bb9a9c3e24 445 }
sherckuith 0:d5bb9a9c3e24 446 } else {
sherckuith 0:d5bb9a9c3e24 447 // Single buffered
sherckuith 0:d5bb9a9c3e24 448 if (IN_EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 449 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S=0, TR=1, TV = 0
sherckuith 0:d5bb9a9c3e24 450 } else {
sherckuith 0:d5bb9a9c3e24 451 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S=0, TR=1, TV = 0
sherckuith 0:d5bb9a9c3e24 452 }
sherckuith 0:d5bb9a9c3e24 453 }
sherckuith 0:d5bb9a9c3e24 454 }
sherckuith 0:d5bb9a9c3e24 455
sherckuith 0:d5bb9a9c3e24 456 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
sherckuith 0:d5bb9a9c3e24 457 if (IN_EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 458 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 459 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
sherckuith 0:d5bb9a9c3e24 460 return true;
sherckuith 0:d5bb9a9c3e24 461 }
sherckuith 0:d5bb9a9c3e24 462 } else {
sherckuith 0:d5bb9a9c3e24 463 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
sherckuith 0:d5bb9a9c3e24 464 return true;
sherckuith 0:d5bb9a9c3e24 465 }
sherckuith 0:d5bb9a9c3e24 466 }
sherckuith 0:d5bb9a9c3e24 467 } else {
sherckuith 0:d5bb9a9c3e24 468 if (LPC_USB->EPINUSE & EP(endpoint)) {
sherckuith 0:d5bb9a9c3e24 469 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
sherckuith 0:d5bb9a9c3e24 470 return true;
sherckuith 0:d5bb9a9c3e24 471 }
sherckuith 0:d5bb9a9c3e24 472 } else {
sherckuith 0:d5bb9a9c3e24 473 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
sherckuith 0:d5bb9a9c3e24 474 return true;
sherckuith 0:d5bb9a9c3e24 475 }
sherckuith 0:d5bb9a9c3e24 476 }
sherckuith 0:d5bb9a9c3e24 477 }
sherckuith 0:d5bb9a9c3e24 478
sherckuith 0:d5bb9a9c3e24 479 return false;
sherckuith 0:d5bb9a9c3e24 480 }
sherckuith 0:d5bb9a9c3e24 481
sherckuith 0:d5bb9a9c3e24 482 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
sherckuith 0:d5bb9a9c3e24 483 uint32_t tmpEpRamPtr;
sherckuith 0:d5bb9a9c3e24 484
sherckuith 0:d5bb9a9c3e24 485 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
sherckuith 0:d5bb9a9c3e24 486 return false;
sherckuith 0:d5bb9a9c3e24 487 }
sherckuith 0:d5bb9a9c3e24 488
sherckuith 0:d5bb9a9c3e24 489 // Not applicable to the control endpoints
sherckuith 0:d5bb9a9c3e24 490 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
sherckuith 0:d5bb9a9c3e24 491 return false;
sherckuith 0:d5bb9a9c3e24 492 }
sherckuith 0:d5bb9a9c3e24 493
sherckuith 0:d5bb9a9c3e24 494 // Allocate buffers in USB RAM
sherckuith 0:d5bb9a9c3e24 495 tmpEpRamPtr = epRamPtr;
sherckuith 0:d5bb9a9c3e24 496
sherckuith 0:d5bb9a9c3e24 497 // Must be 64 byte aligned
sherckuith 0:d5bb9a9c3e24 498 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
sherckuith 0:d5bb9a9c3e24 499
sherckuith 0:d5bb9a9c3e24 500 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
sherckuith 0:d5bb9a9c3e24 501 // Out of memory
sherckuith 0:d5bb9a9c3e24 502 return false;
sherckuith 0:d5bb9a9c3e24 503 }
sherckuith 0:d5bb9a9c3e24 504
sherckuith 0:d5bb9a9c3e24 505 // Allocate first buffer
sherckuith 0:d5bb9a9c3e24 506 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
sherckuith 0:d5bb9a9c3e24 507 tmpEpRamPtr += maxPacket;
sherckuith 0:d5bb9a9c3e24 508
sherckuith 0:d5bb9a9c3e24 509 if (!(options & SINGLE_BUFFERED)) {
sherckuith 0:d5bb9a9c3e24 510 // Must be 64 byte aligned
sherckuith 0:d5bb9a9c3e24 511 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
sherckuith 0:d5bb9a9c3e24 512
sherckuith 0:d5bb9a9c3e24 513 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
sherckuith 0:d5bb9a9c3e24 514 // Out of memory
sherckuith 0:d5bb9a9c3e24 515 return false;
sherckuith 0:d5bb9a9c3e24 516 }
sherckuith 0:d5bb9a9c3e24 517
sherckuith 0:d5bb9a9c3e24 518 // Allocate second buffer
sherckuith 0:d5bb9a9c3e24 519 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
sherckuith 0:d5bb9a9c3e24 520 tmpEpRamPtr += maxPacket;
sherckuith 0:d5bb9a9c3e24 521 }
sherckuith 0:d5bb9a9c3e24 522
sherckuith 0:d5bb9a9c3e24 523 // Commit to this USB RAM allocation
sherckuith 0:d5bb9a9c3e24 524 epRamPtr = tmpEpRamPtr;
sherckuith 0:d5bb9a9c3e24 525
sherckuith 0:d5bb9a9c3e24 526 // Remaining endpoint state values
sherckuith 0:d5bb9a9c3e24 527 endpointState[endpoint].maxPacket = maxPacket;
sherckuith 0:d5bb9a9c3e24 528 endpointState[endpoint].options = options;
sherckuith 0:d5bb9a9c3e24 529
sherckuith 0:d5bb9a9c3e24 530 // Enable double buffering if required
sherckuith 0:d5bb9a9c3e24 531 if (options & SINGLE_BUFFERED) {
sherckuith 0:d5bb9a9c3e24 532 LPC_USB->EPBUFCFG &= ~EP(endpoint);
sherckuith 0:d5bb9a9c3e24 533 } else {
sherckuith 0:d5bb9a9c3e24 534 // Double buffered
sherckuith 0:d5bb9a9c3e24 535 LPC_USB->EPBUFCFG |= EP(endpoint);
sherckuith 0:d5bb9a9c3e24 536 }
sherckuith 0:d5bb9a9c3e24 537
sherckuith 0:d5bb9a9c3e24 538 // Enable interrupt
sherckuith 0:d5bb9a9c3e24 539 LPC_USB->INTEN |= EP(endpoint);
sherckuith 0:d5bb9a9c3e24 540
sherckuith 0:d5bb9a9c3e24 541 // Enable endpoint
sherckuith 0:d5bb9a9c3e24 542 unstallEndpoint(endpoint);
sherckuith 0:d5bb9a9c3e24 543 return true;
sherckuith 0:d5bb9a9c3e24 544 }
sherckuith 0:d5bb9a9c3e24 545
sherckuith 0:d5bb9a9c3e24 546 void USBHAL::remoteWakeup(void) {
sherckuith 0:d5bb9a9c3e24 547 // Clearing DSUS bit initiates a remote wakeup if the
sherckuith 0:d5bb9a9c3e24 548 // device is currently enabled and suspended - otherwise
sherckuith 0:d5bb9a9c3e24 549 // it has no effect.
sherckuith 0:d5bb9a9c3e24 550 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
sherckuith 0:d5bb9a9c3e24 551 }
sherckuith 0:d5bb9a9c3e24 552
sherckuith 0:d5bb9a9c3e24 553
sherckuith 0:d5bb9a9c3e24 554 static void disableEndpoints(void) {
sherckuith 0:d5bb9a9c3e24 555 uint32_t logEp;
sherckuith 0:d5bb9a9c3e24 556
sherckuith 0:d5bb9a9c3e24 557 // Ref. Table 158 "When a bus reset is received, software
sherckuith 0:d5bb9a9c3e24 558 // must set the disable bit of all endpoints to 1".
sherckuith 0:d5bb9a9c3e24 559
sherckuith 0:d5bb9a9c3e24 560 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
sherckuith 0:d5bb9a9c3e24 561 ep[logEp].out[0] = CMDSTS_D;
sherckuith 0:d5bb9a9c3e24 562 ep[logEp].out[1] = CMDSTS_D;
sherckuith 0:d5bb9a9c3e24 563 ep[logEp].in[0] = CMDSTS_D;
sherckuith 0:d5bb9a9c3e24 564 ep[logEp].in[1] = CMDSTS_D;
sherckuith 0:d5bb9a9c3e24 565 }
sherckuith 0:d5bb9a9c3e24 566
sherckuith 0:d5bb9a9c3e24 567 // Start of USB RAM for endpoints > 0
sherckuith 0:d5bb9a9c3e24 568 epRamPtr = usbRamPtr;
sherckuith 0:d5bb9a9c3e24 569 }
sherckuith 0:d5bb9a9c3e24 570
sherckuith 0:d5bb9a9c3e24 571
sherckuith 0:d5bb9a9c3e24 572
sherckuith 0:d5bb9a9c3e24 573 void USBHAL::_usbisr(void) {
sherckuith 0:d5bb9a9c3e24 574 instance->usbisr();
sherckuith 0:d5bb9a9c3e24 575 }
sherckuith 0:d5bb9a9c3e24 576
sherckuith 0:d5bb9a9c3e24 577
sherckuith 0:d5bb9a9c3e24 578 void USBHAL::usbisr(void) {
sherckuith 0:d5bb9a9c3e24 579 // Start of frame
sherckuith 0:d5bb9a9c3e24 580 if (LPC_USB->INTSTAT & FRAME_INT) {
sherckuith 0:d5bb9a9c3e24 581 // Clear SOF interrupt
sherckuith 0:d5bb9a9c3e24 582 LPC_USB->INTSTAT = FRAME_INT;
sherckuith 0:d5bb9a9c3e24 583
sherckuith 0:d5bb9a9c3e24 584 // SOF event, read frame number
sherckuith 0:d5bb9a9c3e24 585 SOF(FRAME_NR(LPC_USB->INFO));
sherckuith 0:d5bb9a9c3e24 586 }
sherckuith 0:d5bb9a9c3e24 587
sherckuith 0:d5bb9a9c3e24 588 // Device state
sherckuith 0:d5bb9a9c3e24 589 if (LPC_USB->INTSTAT & DEV_INT) {
sherckuith 0:d5bb9a9c3e24 590 LPC_USB->INTSTAT = DEV_INT;
sherckuith 0:d5bb9a9c3e24 591
sherckuith 0:d5bb9a9c3e24 592 if (LPC_USB->DEVCMDSTAT & DCON_C) {
sherckuith 0:d5bb9a9c3e24 593 // Connect status changed
sherckuith 0:d5bb9a9c3e24 594 LPC_USB->DEVCMDSTAT = devCmdStat | DCON_C;
sherckuith 0:d5bb9a9c3e24 595
sherckuith 0:d5bb9a9c3e24 596 connectStateChanged((LPC_USB->DEVCMDSTAT & DCON) != 0);
sherckuith 0:d5bb9a9c3e24 597 }
sherckuith 0:d5bb9a9c3e24 598
sherckuith 0:d5bb9a9c3e24 599 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
sherckuith 0:d5bb9a9c3e24 600 // Suspend status changed
sherckuith 0:d5bb9a9c3e24 601 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
sherckuith 0:d5bb9a9c3e24 602
sherckuith 0:d5bb9a9c3e24 603 suspendStateChanged((LPC_USB->DEVCMDSTAT & DSUS) != 0);
sherckuith 0:d5bb9a9c3e24 604 }
sherckuith 0:d5bb9a9c3e24 605
sherckuith 0:d5bb9a9c3e24 606 if (LPC_USB->DEVCMDSTAT & DRES_C) {
sherckuith 0:d5bb9a9c3e24 607 // Bus reset
sherckuith 0:d5bb9a9c3e24 608 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
sherckuith 0:d5bb9a9c3e24 609
sherckuith 0:d5bb9a9c3e24 610 // Disable endpoints > 0
sherckuith 0:d5bb9a9c3e24 611 disableEndpoints();
sherckuith 0:d5bb9a9c3e24 612
sherckuith 0:d5bb9a9c3e24 613 // Bus reset event
sherckuith 0:d5bb9a9c3e24 614 busReset();
sherckuith 0:d5bb9a9c3e24 615 }
sherckuith 0:d5bb9a9c3e24 616 }
sherckuith 0:d5bb9a9c3e24 617
sherckuith 0:d5bb9a9c3e24 618 // Endpoint 0
sherckuith 0:d5bb9a9c3e24 619 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
sherckuith 0:d5bb9a9c3e24 620 // Clear EP0OUT/SETUP interrupt
sherckuith 0:d5bb9a9c3e24 621 LPC_USB->INTSTAT = EP(EP0OUT);
sherckuith 0:d5bb9a9c3e24 622
sherckuith 0:d5bb9a9c3e24 623 // Check if SETUP
sherckuith 0:d5bb9a9c3e24 624 if (LPC_USB->DEVCMDSTAT & SETUP) {
sherckuith 0:d5bb9a9c3e24 625 // Clear Active and Stall bits for EP0
sherckuith 0:d5bb9a9c3e24 626 // Documentation does not make it clear if we must use the
sherckuith 0:d5bb9a9c3e24 627 // EPSKIP register to achieve this, Fig. 16 and NXP reference
sherckuith 0:d5bb9a9c3e24 628 // code suggests we can just clear the Active bits - check with
sherckuith 0:d5bb9a9c3e24 629 // NXP to be sure.
sherckuith 0:d5bb9a9c3e24 630 ep[0].in[0] = 0;
sherckuith 0:d5bb9a9c3e24 631 ep[0].out[0] = 0;
sherckuith 0:d5bb9a9c3e24 632
sherckuith 0:d5bb9a9c3e24 633 // Clear EP0IN interrupt
sherckuith 0:d5bb9a9c3e24 634 LPC_USB->INTSTAT = EP(EP0IN);
sherckuith 0:d5bb9a9c3e24 635
sherckuith 0:d5bb9a9c3e24 636 // Clear SETUP (and INTONNAK_CI/O) in device status register
sherckuith 0:d5bb9a9c3e24 637 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
sherckuith 0:d5bb9a9c3e24 638
sherckuith 0:d5bb9a9c3e24 639 // EP0 SETUP event (SETUP data received)
sherckuith 0:d5bb9a9c3e24 640 EP0setupCallback();
sherckuith 0:d5bb9a9c3e24 641 } else {
sherckuith 0:d5bb9a9c3e24 642 // EP0OUT ACK event (OUT data received)
sherckuith 0:d5bb9a9c3e24 643 EP0out();
sherckuith 0:d5bb9a9c3e24 644 }
sherckuith 0:d5bb9a9c3e24 645 }
sherckuith 0:d5bb9a9c3e24 646
sherckuith 0:d5bb9a9c3e24 647 if (LPC_USB->INTSTAT & EP(EP0IN)) {
sherckuith 0:d5bb9a9c3e24 648 // Clear EP0IN interrupt
sherckuith 0:d5bb9a9c3e24 649 LPC_USB->INTSTAT = EP(EP0IN);
sherckuith 0:d5bb9a9c3e24 650
sherckuith 0:d5bb9a9c3e24 651 // EP0IN ACK event (IN data sent)
sherckuith 0:d5bb9a9c3e24 652 EP0in();
sherckuith 0:d5bb9a9c3e24 653 }
sherckuith 0:d5bb9a9c3e24 654
sherckuith 0:d5bb9a9c3e24 655 if (LPC_USB->INTSTAT & EP(EP1IN)) {
sherckuith 0:d5bb9a9c3e24 656 // Clear EP1IN interrupt
sherckuith 0:d5bb9a9c3e24 657 LPC_USB->INTSTAT = EP(EP1IN);
sherckuith 0:d5bb9a9c3e24 658 epComplete |= EP(EP1IN);
sherckuith 0:d5bb9a9c3e24 659 if (EP1_IN_callback())
sherckuith 0:d5bb9a9c3e24 660 epComplete &= ~EP(EP1IN);
sherckuith 0:d5bb9a9c3e24 661 }
sherckuith 0:d5bb9a9c3e24 662
sherckuith 0:d5bb9a9c3e24 663 if (LPC_USB->INTSTAT & EP(EP1OUT)) {
sherckuith 0:d5bb9a9c3e24 664 // Clear EP1OUT interrupt
sherckuith 0:d5bb9a9c3e24 665 LPC_USB->INTSTAT = EP(EP1OUT);
sherckuith 0:d5bb9a9c3e24 666 epComplete |= EP(EP1OUT);
sherckuith 0:d5bb9a9c3e24 667 if (EP1_OUT_callback())
sherckuith 0:d5bb9a9c3e24 668 epComplete &= ~EP(EP1OUT);
sherckuith 0:d5bb9a9c3e24 669 }
sherckuith 0:d5bb9a9c3e24 670
sherckuith 0:d5bb9a9c3e24 671 if (LPC_USB->INTSTAT & EP(EP2IN)) {
sherckuith 0:d5bb9a9c3e24 672 // Clear EPBULK_IN interrupt
sherckuith 0:d5bb9a9c3e24 673 LPC_USB->INTSTAT = EP(EP2IN);
sherckuith 0:d5bb9a9c3e24 674 epComplete |= EP(EP2IN);
sherckuith 0:d5bb9a9c3e24 675 if (EP2_IN_callback())
sherckuith 0:d5bb9a9c3e24 676 epComplete &= ~EP(EP2IN);
sherckuith 0:d5bb9a9c3e24 677 }
sherckuith 0:d5bb9a9c3e24 678
sherckuith 0:d5bb9a9c3e24 679 if (LPC_USB->INTSTAT & EP(EP2OUT)) {
sherckuith 0:d5bb9a9c3e24 680 // Clear EPBULK_OUT interrupt
sherckuith 0:d5bb9a9c3e24 681 LPC_USB->INTSTAT = EP(EP2OUT);
sherckuith 0:d5bb9a9c3e24 682 epComplete |= EP(EP2OUT);
sherckuith 0:d5bb9a9c3e24 683 //Call callback function. If true, clear epComplete
sherckuith 0:d5bb9a9c3e24 684 if (EP2_OUT_callback())
sherckuith 0:d5bb9a9c3e24 685 epComplete &= ~EP(EP2OUT);
sherckuith 0:d5bb9a9c3e24 686 }
sherckuith 0:d5bb9a9c3e24 687
sherckuith 0:d5bb9a9c3e24 688 if (LPC_USB->INTSTAT & EP(EP3IN)) {
sherckuith 0:d5bb9a9c3e24 689 // Clear EP3_IN interrupt
sherckuith 0:d5bb9a9c3e24 690 LPC_USB->INTSTAT = EP(EP3IN);
sherckuith 0:d5bb9a9c3e24 691 epComplete |= EP(EP3IN);
sherckuith 0:d5bb9a9c3e24 692 if (EP3_IN_callback())
sherckuith 0:d5bb9a9c3e24 693 epComplete &= ~EP(EP3IN);
sherckuith 0:d5bb9a9c3e24 694 }
sherckuith 0:d5bb9a9c3e24 695
sherckuith 0:d5bb9a9c3e24 696 if (LPC_USB->INTSTAT & EP(EP3OUT)) {
sherckuith 0:d5bb9a9c3e24 697 // Clear EP3_OUT interrupt
sherckuith 0:d5bb9a9c3e24 698 LPC_USB->INTSTAT = EP(EP3OUT);
sherckuith 0:d5bb9a9c3e24 699 epComplete |= EP(EP3OUT);
sherckuith 0:d5bb9a9c3e24 700 //Call callback function. If true, clear epComplete
sherckuith 0:d5bb9a9c3e24 701 if (EP3_OUT_callback())
sherckuith 0:d5bb9a9c3e24 702 epComplete &= ~EP(EP3OUT);
sherckuith 0:d5bb9a9c3e24 703 }
sherckuith 0:d5bb9a9c3e24 704 }
sherckuith 0:d5bb9a9c3e24 705
sherckuith 0:d5bb9a9c3e24 706 #endif