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Code used earlier for testing the peak power output
main.cpp@0:8e29aadf305d, 2015-10-26 (annotated)
- Committer:
- shekhar
- Date:
- Mon Oct 26 10:39:16 2015 +0000
- Revision:
- 0:8e29aadf305d
Code used for Power testings
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
shekhar | 0:8e29aadf305d | 1 | #include "beacon.h" |
shekhar | 0:8e29aadf305d | 2 | Serial pc(USBTX, USBRX); // tx, rx |
shekhar | 0:8e29aadf305d | 3 | SPI spi(D11, D12, D13); // mosi, miso, sclk |
shekhar | 0:8e29aadf305d | 4 | DigitalOut cs(D10); //slave select or chip select |
shekhar | 0:8e29aadf305d | 5 | |
shekhar | 0:8e29aadf305d | 6 | void writereg(uint8_t reg,uint8_t val) |
shekhar | 0:8e29aadf305d | 7 | { |
shekhar | 0:8e29aadf305d | 8 | cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1; |
shekhar | 0:8e29aadf305d | 9 | } |
shekhar | 0:8e29aadf305d | 10 | uint8_t readreg(uint8_t reg) |
shekhar | 0:8e29aadf305d | 11 | { |
shekhar | 0:8e29aadf305d | 12 | int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val; |
shekhar | 0:8e29aadf305d | 13 | } |
shekhar | 0:8e29aadf305d | 14 | void clearTxBuf() |
shekhar | 0:8e29aadf305d | 15 | { |
shekhar | 0:8e29aadf305d | 16 | writereg(RF22_REG_08_OPERATING_MODE2,0x01); |
shekhar | 0:8e29aadf305d | 17 | writereg(RF22_REG_08_OPERATING_MODE2,0x00); |
shekhar | 0:8e29aadf305d | 18 | } |
shekhar | 0:8e29aadf305d | 19 | void clearRxBuf() |
shekhar | 0:8e29aadf305d | 20 | { |
shekhar | 0:8e29aadf305d | 21 | writereg(RF22_REG_08_OPERATING_MODE2,0x02); |
shekhar | 0:8e29aadf305d | 22 | writereg(RF22_REG_08_OPERATING_MODE2,0x00); |
shekhar | 0:8e29aadf305d | 23 | } |
shekhar | 0:8e29aadf305d | 24 | int setFrequency(float centre,float afcPullInRange) |
shekhar | 0:8e29aadf305d | 25 | { |
shekhar | 0:8e29aadf305d | 26 | //freq setting begins |
shekhar | 0:8e29aadf305d | 27 | uint8_t fbsel = 0x40; |
shekhar | 0:8e29aadf305d | 28 | uint8_t afclimiter; |
shekhar | 0:8e29aadf305d | 29 | if (centre >= 480.0) { |
shekhar | 0:8e29aadf305d | 30 | centre /= 2; |
shekhar | 0:8e29aadf305d | 31 | fbsel |= 0x20; |
shekhar | 0:8e29aadf305d | 32 | afclimiter = afcPullInRange * 1000000.0 / 1250.0; |
shekhar | 0:8e29aadf305d | 33 | } else { |
shekhar | 0:8e29aadf305d | 34 | if (afcPullInRange < 0.0 || afcPullInRange > 0.159375) |
shekhar | 0:8e29aadf305d | 35 | return false; |
shekhar | 0:8e29aadf305d | 36 | afclimiter = afcPullInRange * 1000000.0 / 625.0; |
shekhar | 0:8e29aadf305d | 37 | } |
shekhar | 0:8e29aadf305d | 38 | centre /= 10.0; |
shekhar | 0:8e29aadf305d | 39 | float integerPart = floor(centre); |
shekhar | 0:8e29aadf305d | 40 | float fractionalPart = centre - integerPart; |
shekhar | 0:8e29aadf305d | 41 | |
shekhar | 0:8e29aadf305d | 42 | uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23 |
shekhar | 0:8e29aadf305d | 43 | fbsel |= fb; |
shekhar | 0:8e29aadf305d | 44 | uint16_t fc = fractionalPart * 64000; |
shekhar | 0:8e29aadf305d | 45 | writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT |
shekhar | 0:8e29aadf305d | 46 | writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0); |
shekhar | 0:8e29aadf305d | 47 | writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel); |
shekhar | 0:8e29aadf305d | 48 | writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8); |
shekhar | 0:8e29aadf305d | 49 | writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff); |
shekhar | 0:8e29aadf305d | 50 | writereg(RF22_REG_2A_AFC_LIMITER, afclimiter); |
shekhar | 0:8e29aadf305d | 51 | return 0; |
shekhar | 0:8e29aadf305d | 52 | } |
shekhar | 0:8e29aadf305d | 53 | |
shekhar | 0:8e29aadf305d | 54 | void init() |
shekhar | 0:8e29aadf305d | 55 | { |
shekhar | 0:8e29aadf305d | 56 | //reset() |
shekhar | 0:8e29aadf305d | 57 | writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset |
shekhar | 0:8e29aadf305d | 58 | wait(1); //takes time to reset |
shekhar | 0:8e29aadf305d | 59 | |
shekhar | 0:8e29aadf305d | 60 | clearTxBuf(); |
shekhar | 0:8e29aadf305d | 61 | clearRxBuf(); |
shekhar | 0:8e29aadf305d | 62 | //txfifoalmostempty |
shekhar | 0:8e29aadf305d | 63 | writereg(RF22_REG_7D_TX_FIFO_CONTROL2,5); |
shekhar | 0:8e29aadf305d | 64 | //rxfifoalmostfull |
shekhar | 0:8e29aadf305d | 65 | writereg(RF22_REG_7E_RX_FIFO_CONTROL,20); |
shekhar | 0:8e29aadf305d | 66 | //Packet-engine registers |
shekhar | 0:8e29aadf305d | 67 | writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM |
shekhar | 0:8e29aadf305d | 68 | //&0x77 = diasable packet rx-tx handling |
shekhar | 0:8e29aadf305d | 69 | writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3 |
shekhar | 0:8e29aadf305d | 70 | writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2 |
shekhar | 0:8e29aadf305d | 71 | writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8; |
shekhar | 0:8e29aadf305d | 72 | writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D |
shekhar | 0:8e29aadf305d | 73 | writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4 |
shekhar | 0:8e29aadf305d | 74 | writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS |
shekhar | 0:8e29aadf305d | 75 | writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to |
shekhar | 0:8e29aadf305d | 76 | writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from |
shekhar | 0:8e29aadf305d | 77 | writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids |
shekhar | 0:8e29aadf305d | 78 | writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags |
shekhar | 0:8e29aadf305d | 79 | writereg(RF22_REG_3F_CHECK_HEADER3,0xab); |
shekhar | 0:8e29aadf305d | 80 | writereg(RF22_REG_40_CHECK_HEADER2,0xbc); |
shekhar | 0:8e29aadf305d | 81 | writereg(RF22_REG_41_CHECK_HEADER1,0xcd); |
shekhar | 0:8e29aadf305d | 82 | writereg(RF22_REG_42_CHECK_HEADER0,0xde); |
shekhar | 0:8e29aadf305d | 83 | |
shekhar | 0:8e29aadf305d | 84 | //RSSI threshold for clear channel indicator |
shekhar | 0:8e29aadf305d | 85 | writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm |
shekhar | 0:8e29aadf305d | 86 | |
shekhar | 0:8e29aadf305d | 87 | writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ?? |
shekhar | 0:8e29aadf305d | 88 | writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ?? |
shekhar | 0:8e29aadf305d | 89 | |
shekhar | 0:8e29aadf305d | 90 | //interrupts |
shekhar | 0:8e29aadf305d | 91 | // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR); |
shekhar | 0:8e29aadf305d | 92 | // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL); |
shekhar | 0:8e29aadf305d | 93 | |
shekhar | 0:8e29aadf305d | 94 | setFrequency(435.0, 0.05); |
shekhar | 0:8e29aadf305d | 95 | |
shekhar | 0:8e29aadf305d | 96 | //return !(statusRead() & RF22_FREQERR); |
shekhar | 0:8e29aadf305d | 97 | if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00) |
shekhar | 0:8e29aadf305d | 98 | pc.printf("frequency not set properly\n"); |
shekhar | 0:8e29aadf305d | 99 | //frequency set |
shekhar | 0:8e29aadf305d | 100 | |
shekhar | 0:8e29aadf305d | 101 | //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz |
shekhar | 0:8e29aadf305d | 102 | //setmodemregisters |
shekhar | 0:8e29aadf305d | 103 | //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36 |
shekhar | 0:8e29aadf305d | 104 | //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335 |
shekhar | 0:8e29aadf305d | 105 | /* writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0x2B); |
shekhar | 0:8e29aadf305d | 106 | writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03); |
shekhar | 0:8e29aadf305d | 107 | writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x41); |
shekhar | 0:8e29aadf305d | 108 | writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x60); |
shekhar | 0:8e29aadf305d | 109 | writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x27); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk |
shekhar | 0:8e29aadf305d | 110 | writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0x52); |
shekhar | 0:8e29aadf305d | 111 | writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00); |
shekhar | 0:8e29aadf305d | 112 | writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x99); |
shekhar | 0:8e29aadf305d | 113 | /*writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2a); |
shekhar | 0:8e29aadf305d | 114 | writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x08);*/ //not required for fsk (OOK counter value) |
shekhar | 0:8e29aadf305d | 115 | /* writereg(RF22_REG_1D_AFC_LOOP_GEARSHIFT_OVERRIDE,0x40); |
shekhar | 0:8e29aadf305d | 116 | writereg(RF22_REG_1E_AFC_TIMING_CONTROL,0x0A); |
shekhar | 0:8e29aadf305d | 117 | writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x1e); //?? |
shekhar | 0:8e29aadf305d | 118 | writereg(RF22_REG_58,0x80); |
shekhar | 0:8e29aadf305d | 119 | writereg(RF22_REG_69_AGC_OVERRIDE1,0x60); |
shekhar | 0:8e29aadf305d | 120 | writereg(RF22_REG_6E_TX_DATA_RATE1,0x09); |
shekhar | 0:8e29aadf305d | 121 | writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5); |
shekhar | 0:8e29aadf305d | 122 | writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c); |
shekhar | 0:8e29aadf305d | 123 | writereg(RF22_REG_71_MODULATION_CONTROL2,0x22);//ook = 0x21 //fsk = 0x22 |
shekhar | 0:8e29aadf305d | 124 | writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x01);*/ |
shekhar | 0:8e29aadf305d | 125 | writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0x2B); |
shekhar | 0:8e29aadf305d | 126 | writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03); |
shekhar | 0:8e29aadf305d | 127 | writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x83); |
shekhar | 0:8e29aadf305d | 128 | writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0xC0); |
shekhar | 0:8e29aadf305d | 129 | writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x13); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk |
shekhar | 0:8e29aadf305d | 130 | writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xA9); |
shekhar | 0:8e29aadf305d | 131 | writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00); |
shekhar | 0:8e29aadf305d | 132 | writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x28); |
shekhar | 0:8e29aadf305d | 133 | /*writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2a); |
shekhar | 0:8e29aadf305d | 134 | writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x08);*/ //not required for fsk (OOK counter value) |
shekhar | 0:8e29aadf305d | 135 | writereg(RF22_REG_1D_AFC_LOOP_GEARSHIFT_OVERRIDE,0x40); |
shekhar | 0:8e29aadf305d | 136 | writereg(RF22_REG_1E_AFC_TIMING_CONTROL,0x0A); |
shekhar | 0:8e29aadf305d | 137 | writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x1e); //?? |
shekhar | 0:8e29aadf305d | 138 | writereg(RF22_REG_58,0x80); |
shekhar | 0:8e29aadf305d | 139 | writereg(RF22_REG_69_AGC_OVERRIDE1,0x60); |
shekhar | 0:8e29aadf305d | 140 | writereg(RF22_REG_6E_TX_DATA_RATE1,0x04); |
shekhar | 0:8e29aadf305d | 141 | writereg(RF22_REG_6F_TX_DATA_RATE0,0xEA); |
shekhar | 0:8e29aadf305d | 142 | writereg(RF22_REG_70_MODULATION_CONTROL1,0x20); |
shekhar | 0:8e29aadf305d | 143 | writereg(RF22_REG_71_MODULATION_CONTROL2,0x22);//ook = 0x21 //fsk = 0x22 |
shekhar | 0:8e29aadf305d | 144 | writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x01); |
shekhar | 0:8e29aadf305d | 145 | //set tx power |
shekhar | 0:8e29aadf305d | 146 | writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm |
shekhar | 0:8e29aadf305d | 147 | writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length |
shekhar | 0:8e29aadf305d | 148 | } |
shekhar | 0:8e29aadf305d | 149 | int main() |
shekhar | 0:8e29aadf305d | 150 | { |
shekhar | 0:8e29aadf305d | 151 | wait(1); // wait for POR to complete //change the timing later |
shekhar | 0:8e29aadf305d | 152 | cs=1; // chip must be deselected |
shekhar | 0:8e29aadf305d | 153 | wait(1); //change the time later |
shekhar | 0:8e29aadf305d | 154 | spi.format(8,0); |
shekhar | 0:8e29aadf305d | 155 | spi.frequency(10000000); //10MHz SCLK |
shekhar | 0:8e29aadf305d | 156 | if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n"); |
shekhar | 0:8e29aadf305d | 157 | else pc.printf("error in spi connection\n"); |
shekhar | 0:8e29aadf305d | 158 | |
shekhar | 0:8e29aadf305d | 159 | init(); |
shekhar | 0:8e29aadf305d | 160 | |
shekhar | 0:8e29aadf305d | 161 | |
shekhar | 0:8e29aadf305d | 162 | //init complete |
shekhar | 0:8e29aadf305d | 163 | pc.printf("init complete.....press t to send\n"); |
shekhar | 0:8e29aadf305d | 164 | |
shekhar | 0:8e29aadf305d | 165 | |
shekhar | 0:8e29aadf305d | 166 | //******** |
shekhar | 0:8e29aadf305d | 167 | |
shekhar | 0:8e29aadf305d | 168 | while(1)//pc.getc()=='t') //1 |
shekhar | 0:8e29aadf305d | 169 | { |
shekhar | 0:8e29aadf305d | 170 | /*uint8_t data[] = "Hello World!"; |
shekhar | 0:8e29aadf305d | 171 | pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/ |
shekhar | 0:8e29aadf305d | 172 | |
shekhar | 0:8e29aadf305d | 173 | uint8_t data[255]; //starts from 0,1,2,3,4!!!; |
shekhar | 0:8e29aadf305d | 174 | int i = 0; //for loops |
shekhar | 0:8e29aadf305d | 175 | int u = 0; //universal count for hk array |
shekhar | 0:8e29aadf305d | 176 | int bar = 0; |
shekhar | 0:8e29aadf305d | 177 | //filling hk data |
shekhar | 0:8e29aadf305d | 178 | /* for(int n=0; n<1; n++) |
shekhar | 0:8e29aadf305d | 179 | data[n] = 0xAA; |
shekhar | 0:8e29aadf305d | 180 | data[1] = 0x3A; |
shekhar | 0:8e29aadf305d | 181 | for(int n=0; n<60; n++) |
shekhar | 0:8e29aadf305d | 182 | data[n] = 0x5A; |
shekhar | 0:8e29aadf305d | 183 | for(int n=2; n<60; n++) |
shekhar | 0:8e29aadf305d | 184 | data[n] = n; |
shekhar | 0:8e29aadf305d | 185 | for(int n=60; n<75; n++) |
shekhar | 0:8e29aadf305d | 186 | data[n] = 0xCC; |
shekhar | 0:8e29aadf305d | 187 | for(int n=75; n<95; n++) |
shekhar | 0:8e29aadf305d | 188 | data[n] = 0xBC; |
shekhar | 0:8e29aadf305d | 189 | for(int n=95; n<110; n++) |
shekhar | 0:8e29aadf305d | 190 | data[n] = 0xEC; |
shekhar | 0:8e29aadf305d | 191 | for(int n=110; n<120; n++) |
shekhar | 0:8e29aadf305d | 192 | data[n] = 0xFC; |
shekhar | 0:8e29aadf305d | 193 | for(int n=120; n<150; n++) |
shekhar | 0:8e29aadf305d | 194 | data[n] = 0xAF;*/ |
shekhar | 0:8e29aadf305d | 195 | for(int n=0; n<TX_DATA; n++) |
shekhar | 0:8e29aadf305d | 196 | data[n] = 0xFF; |
shekhar | 0:8e29aadf305d | 197 | //tx settings begin |
shekhar | 0:8e29aadf305d | 198 | |
shekhar | 0:8e29aadf305d | 199 | //setModeIdle(); |
shekhar | 0:8e29aadf305d | 200 | writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode |
shekhar | 0:8e29aadf305d | 201 | //fillTxBuf(data, len); |
shekhar | 0:8e29aadf305d | 202 | clearTxBuf(); |
shekhar | 0:8e29aadf305d | 203 | //Filling Data into FIFO for the first time |
shekhar | 0:8e29aadf305d | 204 | cs = 0; |
shekhar | 0:8e29aadf305d | 205 | spi.write(0xFF); //fifo write access |
shekhar | 0:8e29aadf305d | 206 | for(i=0; i< 20; i++) { //datalen; i++){ |
shekhar | 0:8e29aadf305d | 207 | spi.write(data[i]); |
shekhar | 0:8e29aadf305d | 208 | pc.printf("0x%X \n",data[u+i]); |
shekhar | 0:8e29aadf305d | 209 | } |
shekhar | 0:8e29aadf305d | 210 | u=i;//check its 64 |
shekhar | 0:8e29aadf305d | 211 | cs = 1; |
shekhar | 0:8e29aadf305d | 212 | |
shekhar | 0:8e29aadf305d | 213 | //Set to Tx mode |
shekhar | 0:8e29aadf305d | 214 | writereg(RF22_REG_07_OPERATING_MODE1,0x09); |
shekhar | 0:8e29aadf305d | 215 | |
shekhar | 0:8e29aadf305d | 216 | //Check for fifoempty Thresh |
shekhar | 0:8e29aadf305d | 217 | while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20); |
shekhar | 0:8e29aadf305d | 218 | |
shekhar | 0:8e29aadf305d | 219 | while(u!=TX_DATA) { |
shekhar | 0:8e29aadf305d | 220 | if((TX_DATA - u) >= TIMES) |
shekhar | 0:8e29aadf305d | 221 | bar = TIMES; |
shekhar | 0:8e29aadf305d | 222 | else |
shekhar | 0:8e29aadf305d | 223 | bar = (TX_DATA - u); |
shekhar | 0:8e29aadf305d | 224 | |
shekhar | 0:8e29aadf305d | 225 | //writing again |
shekhar | 0:8e29aadf305d | 226 | cs = 0; |
shekhar | 0:8e29aadf305d | 227 | spi.write(0xFF); //FIFO write access |
shekhar | 0:8e29aadf305d | 228 | for(i=0; i<bar; i++){ |
shekhar | 0:8e29aadf305d | 229 | spi.write(data[u + i]); |
shekhar | 0:8e29aadf305d | 230 | pc.printf("0x%X \n",data[u+i]); |
shekhar | 0:8e29aadf305d | 231 | } |
shekhar | 0:8e29aadf305d | 232 | u = u + i; |
shekhar | 0:8e29aadf305d | 233 | cs = 1; |
shekhar | 0:8e29aadf305d | 234 | //Check for fifoThresh |
shekhar | 0:8e29aadf305d | 235 | while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20); |
shekhar | 0:8e29aadf305d | 236 | } |
shekhar | 0:8e29aadf305d | 237 | //rf22.waitPacketSent(); |
shekhar | 0:8e29aadf305d | 238 | while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n"); |
shekhar | 0:8e29aadf305d | 239 | pc.printf(" packet sent "); |
shekhar | 0:8e29aadf305d | 240 | |
shekhar | 0:8e29aadf305d | 241 | } |
shekhar | 0:8e29aadf305d | 242 | } |