pradeep shekhar / Mbed 2 deprecated adf_code_testing_24_12_15

Repository for testing ADF code of COM_TMTC_SIMPLE

Dependencies:   mbed-rtos mbed

Fork of COM_MNG_TMTC_SIMPLE by Shreesha S

adf.h@4:e37674541504, 2015-12-24 (annotated)

Committer:
shekhar
Date:
Thu Dec 24 18:38:12 2015 +0000
Revision:
4:e37674541504
Parent:
3:6c81fc8834e2 
ADF code to be tested

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shreeshas95 1:a0055b3280c8 1 //without reset feature , with state checks.
shreeshas95 2:2caf2a9a13aa 2 InterruptIn IRQ(ADF_IRQ);
shreeshas95 1:a0055b3280c8 3 Ticker ticker;
shreeshas95 1:a0055b3280c8 4
shreeshas95 1:a0055b3280c8 5 bool sent_tmfrom_SDcard;
shreeshas95 1:a0055b3280c8 6 bool loop_on;
shreeshas95 1:a0055b3280c8 7 bool ADF_off;
shreeshas95 1:a0055b3280c8 8 bool buffer_state;
shreeshas95 1:a0055b3280c8 9 uint8_t signal = 0x00;
shreeshas95 1:a0055b3280c8 10 unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x10,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00};
shreeshas95 1:a0055b3280c8 11
shreeshas95 2:2caf2a9a13aa 12 //int initialise_card();
shreeshas95 2:2caf2a9a13aa 13 //int disk_initialize();
shreeshas95 1:a0055b3280c8 14
shekhar 4:e37674541504 15 #define bbram_write {\//SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 16 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 17 spi.write(0xB0);\
shreeshas95 1:a0055b3280c8 18 wait_us(300);\
shreeshas95 1:a0055b3280c8 19 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 20 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 21 for(int i=0;i<66;i++){\
shreeshas95 1:a0055b3280c8 22 spi.write(bbram_buffer[i]);\
shreeshas95 1:a0055b3280c8 23 }\
shekhar 4:e37674541504 24 gCS_ADF=1;\//SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 25 }
shreeshas95 1:a0055b3280c8 26 //------------------------------------------------------------------------
shreeshas95 1:a0055b3280c8 27 // state checking functions
shreeshas95 1:a0055b3280c8 28 //bool assrt_phy_off( int, int, int);
shreeshas95 1:a0055b3280c8 29 //bool assrt_phy_on( int,int,int);
shreeshas95 1:a0055b3280c8 30 //bool assrt_phy_tx(int,int,int);
shreeshas95 1:a0055b3280c8 31
shreeshas95 1:a0055b3280c8 32 #define START_ADDRESS 0x020;
shreeshas95 1:a0055b3280c8 33 #define MISO_PIN PTE3
shreeshas95 1:a0055b3280c8 34 /**************Defining Counter Limits**************/
shreeshas95 1:a0055b3280c8 35 #define THRS 20
shreeshas95 1:a0055b3280c8 36 #define STATE_ERR_THRS 20
shreeshas95 1:a0055b3280c8 37 #define PHY_OFF_EXEC_TIME 300
shreeshas95 1:a0055b3280c8 38 #define PHY_ON_EXEC_TIME 300
shreeshas95 1:a0055b3280c8 39 #define PHY_TX_EXEC_TIME 600
shreeshas95 1:a0055b3280c8 40 /******DEFINING COMMANDS*********/
shreeshas95 1:a0055b3280c8 41 #define CMD_HW_RESET 0xC8
shreeshas95 1:a0055b3280c8 42 #define CMD_PHY_ON 0xB1
shreeshas95 1:a0055b3280c8 43 #define CMD_PHY_OFF 0xB0
shreeshas95 1:a0055b3280c8 44 #define CMD_PHY_TX 0xB5
shreeshas95 1:a0055b3280c8 45 #define CMD_CONFIG_DEV 0xBB
shreeshas95 1:a0055b3280c8 46
shreeshas95 1:a0055b3280c8 47 #define check_status {\
shreeshas95 1:a0055b3280c8 48 unsigned char stat=0;\
shreeshas95 1:a0055b3280c8 49 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 50 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 51 stat = spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 52 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 53 status = stat;\
shreeshas95 1:a0055b3280c8 54 }
shreeshas95 1:a0055b3280c8 55
shreeshas95 1:a0055b3280c8 56 // all three arguments are int
shreeshas95 1:a0055b3280c8 57 #define assrt_phy_off(return_this) {\
shreeshas95 1:a0055b3280c8 58 int cmd_err_cnt = 0;\
shreeshas95 1:a0055b3280c8 59 int spi_err_cnt = 0;\
shreeshas95 1:a0055b3280c8 60 int state_err_cnt = 0;\
shreeshas95 1:a0055b3280c8 61 for(int i = 0 ; i < 40 ;i++){\
shreeshas95 1:a0055b3280c8 62 check_status;\
shreeshas95 1:a0055b3280c8 63 if(status == 0xB1){\
shreeshas95 1:a0055b3280c8 64 return_this = 0;\
shreeshas95 1:a0055b3280c8 65 break;\
shreeshas95 1:a0055b3280c8 66 }\
shreeshas95 1:a0055b3280c8 67 else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){\
shreeshas95 1:a0055b3280c8 68 return_this = 1;\
shreeshas95 1:a0055b3280c8 69 break;\
shreeshas95 1:a0055b3280c8 70 }\
shreeshas95 1:a0055b3280c8 71 else if(state_err_cnt>STATE_ERR_THRS){\
shreeshas95 1:a0055b3280c8 72 return_this = 1;\
shreeshas95 1:a0055b3280c8 73 break;\
shreeshas95 1:a0055b3280c8 74 }\
shreeshas95 1:a0055b3280c8 75 else if( (status & 0xA0) == 0xA0 ){\
shreeshas95 1:a0055b3280c8 76 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 77 spi.write(CMD_PHY_OFF);\
shreeshas95 1:a0055b3280c8 78 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 79 wait_us(PHY_OFF_EXEC_TIME);\
shreeshas95 1:a0055b3280c8 80 state_err_cnt++;\
shreeshas95 1:a0055b3280c8 81 }\
shreeshas95 1:a0055b3280c8 82 else if(status&0x80==0x00){\
shreeshas95 1:a0055b3280c8 83 wait_ms(5);\
shreeshas95 1:a0055b3280c8 84 spi_err_cnt++;\
shreeshas95 1:a0055b3280c8 85 }\
shreeshas95 1:a0055b3280c8 86 else {\
shreeshas95 1:a0055b3280c8 87 wait_ms(1);\
shreeshas95 1:a0055b3280c8 88 cmd_err_cnt++;\
shreeshas95 1:a0055b3280c8 89 }\
shreeshas95 1:a0055b3280c8 90 }\
shreeshas95 1:a0055b3280c8 91 }
shreeshas95 1:a0055b3280c8 92
shreeshas95 1:a0055b3280c8 93
shreeshas95 1:a0055b3280c8 94 //#define assrt_phy_on(cmd_err_cnt, spi_err_cnt, state_err_cnt, return_this){\
shreeshas95 1:a0055b3280c8 95 // status=check_status();\
shreeshas95 1:a0055b3280c8 96 // if((status&0x1F)==0x12){\
shreeshas95 1:a0055b3280c8 97 // return 0;\
shreeshas95 1:a0055b3280c8 98 // }\
shreeshas95 1:a0055b3280c8 99 // else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){\
shreeshas95 1:a0055b3280c8 100 // return 1;\
shreeshas95 1:a0055b3280c8 101 // }\
shreeshas95 1:a0055b3280c8 102 // else if(state_err_cnt>STATE_ERR_THRS){\
shreeshas95 1:a0055b3280c8 103 // return 1;\
shreeshas95 1:a0055b3280c8 104 // }\
shreeshas95 1:a0055b3280c8 105 // else if((status&0xA0)==0xA0){\
shreeshas95 1:a0055b3280c8 106 // cs_adf=0;\
shreeshas95 1:a0055b3280c8 107 // spi.write(0xB1);\
shreeshas95 1:a0055b3280c8 108 // cs_adf=1;\
shreeshas95 1:a0055b3280c8 109 // wait_us(PHY_ON_EXEC_TIME);\
shreeshas95 1:a0055b3280c8 110 // return assrt_phy_on(cmd_err_cnt,spi_err_cnt,state_err_cnt+1);\
shreeshas95 1:a0055b3280c8 111 // }\
shreeshas95 1:a0055b3280c8 112 // else if(status&0x80==0x00){\
shreeshas95 1:a0055b3280c8 113 // wait_ms(5);\
shreeshas95 1:a0055b3280c8 114 // //Error: SPI=0 Not ready CMD= Dont care
shreeshas95 1:a0055b3280c8 115 // return assrt_phy_on(cmd_err_cnt,spi_err_cnt+1,state_err_cnt);\
shreeshas95 1:a0055b3280c8 116 // }\
shreeshas95 1:a0055b3280c8 117 // else{\
shreeshas95 1:a0055b3280c8 118 // if(status&0xA0==0x80){\
shreeshas95 1:a0055b3280c8 119 // wait_ms(1);\
shreeshas95 1:a0055b3280c8 120 // //Error: Command Not ready SPI Ready cmd_err_cnt is a global variable
shreeshas95 1:a0055b3280c8 121 // return assrt_phy_on(cmd_err_cnt+1,spi_err_cnt,state_err_cnt);\
shreeshas95 1:a0055b3280c8 122 // }\
shreeshas95 1:a0055b3280c8 123 // }\
shreeshas95 1:a0055b3280c8 124 //}
shreeshas95 1:a0055b3280c8 125
shreeshas95 1:a0055b3280c8 126
shreeshas95 1:a0055b3280c8 127
shreeshas95 1:a0055b3280c8 128
shreeshas95 1:a0055b3280c8 129 #define initial_adf_check {\
shreeshas95 1:a0055b3280c8 130 spi.write(CMD_PHY_OFF);\
shreeshas95 1:a0055b3280c8 131 int tempReturn = 0;\
shreeshas95 2:2caf2a9a13aa 132 bool flag = false;\
shreeshas95 1:a0055b3280c8 133 while( hw_reset_err_cnt < 2 ){\
shreeshas95 1:a0055b3280c8 134 assrt_phy_off( tempReturn);\
shreeshas95 1:a0055b3280c8 135 if( !tempReturn ){\
shreeshas95 1:a0055b3280c8 136 bbram_write;\
shreeshas95 1:a0055b3280c8 137 bbram_flag=1;\
shreeshas95 2:2caf2a9a13aa 138 flag = true;\
shreeshas95 1:a0055b3280c8 139 break;\
shreeshas95 1:a0055b3280c8 140 }\
shreeshas95 1:a0055b3280c8 141 else{\
shreeshas95 1:a0055b3280c8 142 hardware_reset(0);\
shreeshas95 1:a0055b3280c8 143 hw_reset_err_cnt++;\
shreeshas95 2:2caf2a9a13aa 144 gPC.puts("Resetting hardware\r\n");\
shreeshas95 1:a0055b3280c8 145 }\
shreeshas95 1:a0055b3280c8 146 }\
shreeshas95 2:2caf2a9a13aa 147 if( flag == false ){\
shreeshas95 2:2caf2a9a13aa 148 gPC.puts("Seems to be SPI problem\r\n");\
shreeshas95 2:2caf2a9a13aa 149 }\
shreeshas95 1:a0055b3280c8 150 assrt_phy_off(tempReturn);\
shreeshas95 1:a0055b3280c8 151 if(!bbram_flag){\
shreeshas95 1:a0055b3280c8 152 bcn_flag=1;\
shreeshas95 1:a0055b3280c8 153 }\
shreeshas95 1:a0055b3280c8 154 }
shreeshas95 1:a0055b3280c8 155
shreeshas95 1:a0055b3280c8 156 unsigned char status =0;
shreeshas95 1:a0055b3280c8 157 unsigned int cmd_err_cnt=0;
shreeshas95 1:a0055b3280c8 158 unsigned int state_err_cnt=0;
shreeshas95 1:a0055b3280c8 159 unsigned int miso_err_cnt=0;
shreeshas95 1:a0055b3280c8 160 unsigned int hw_reset_err_cnt=0;
shreeshas95 1:a0055b3280c8 161 bool bcn_flag=0;
shreeshas95 1:a0055b3280c8 162 bool bbram_flag=0;
shreeshas95 1:a0055b3280c8 163
shreeshas95 1:a0055b3280c8 164 //bool assrt_phy_off(int cmd_err_cnt,int spi_err_cnt,int state_err_cnt){
shreeshas95 1:a0055b3280c8 165 // status=check_status();
shreeshas95 1:a0055b3280c8 166 // if(status==0xB1){
shreeshas95 1:a0055b3280c8 167 // return 0;
shreeshas95 1:a0055b3280c8 168 // }
shreeshas95 1:a0055b3280c8 169 // else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){
shreeshas95 1:a0055b3280c8 170 // return 1;//You need to Reset the hardware
shreeshas95 1:a0055b3280c8 171 // }
shreeshas95 1:a0055b3280c8 172 // else if(state_err_cnt>STATE_ERR_THRS){
shreeshas95 1:a0055b3280c8 173 // return 1;//Again reset the hardware
shreeshas95 1:a0055b3280c8 174 // }
shreeshas95 1:a0055b3280c8 175 // else if((status&0xA0)==0xA0){ //If Status' first three bit ore 0b1X1 =>SPI ready, Dont care interrupt and CMD Ready.
shreeshas95 1:a0055b3280c8 176 // cs_adf=0;
shreeshas95 1:a0055b3280c8 177 // spi.write(CMD_PHY_OFF); //CMD_PHY_OFF=0xB0
shreeshas95 1:a0055b3280c8 178 // cs_adf=1;
shreeshas95 1:a0055b3280c8 179 // wait_us(PHY_OFF_EXEC_TIME);// Typical = 24us We are giving 300us
shreeshas95 1:a0055b3280c8 180 // return assrt_phy_off(cmd_err_cnt,spi_err_cnt,state_err_cnt+1);
shreeshas95 1:a0055b3280c8 181 // }
shreeshas95 1:a0055b3280c8 182 // else if(status&0x80==0x00){
shreeshas95 1:a0055b3280c8 183 // wait_ms(5);
shreeshas95 1:a0055b3280c8 184 // //Error: SPI=0 Not ready CMD= Dont care
shreeshas95 1:a0055b3280c8 185 // return assrt_phy_off(cmd_err_cnt,spi_err_cnt+1,state_err_cnt);
shreeshas95 1:a0055b3280c8 186 // }
shreeshas95 1:a0055b3280c8 187 // else {//if(status&0xA0==0x80){
shreeshas95 1:a0055b3280c8 188 // wait_ms(1);
shreeshas95 1:a0055b3280c8 189 // //Error: Command Not ready SPI Ready cmd_err_cnt is a global variable
shreeshas95 1:a0055b3280c8 190 // return assrt_phy_off(cmd_err_cnt+1,spi_err_cnt,state_err_cnt);
shreeshas95 1:a0055b3280c8 191 // }
shreeshas95 1:a0055b3280c8 192 //}
shreeshas95 1:a0055b3280c8 193
shreeshas95 1:a0055b3280c8 194 //bool assrt_phy_on(int cmd_err_cnt,int spi_err_cnt,int state_err_cnt){
shreeshas95 1:a0055b3280c8 195 // status=check_status();
shreeshas95 1:a0055b3280c8 196 // if((status&0x1F)==0x12){
shreeshas95 1:a0055b3280c8 197 // return 0;
shreeshas95 1:a0055b3280c8 198 // }
shreeshas95 1:a0055b3280c8 199 // else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){
shreeshas95 1:a0055b3280c8 200 // return 1;//You need to Reset the hardware
shreeshas95 1:a0055b3280c8 201 // }
shreeshas95 1:a0055b3280c8 202 // else if(state_err_cnt>STATE_ERR_THRS){
shreeshas95 1:a0055b3280c8 203 // return 1;//Again reset the hardware
shreeshas95 1:a0055b3280c8 204 // }
shreeshas95 1:a0055b3280c8 205 // else if((status&0xA0)==0xA0){ //If Status' first three bit ore 0b1X1 =>SPI ready, Dont care interrupt and CMD Ready.
shreeshas95 1:a0055b3280c8 206 // cs_adf=0;
shreeshas95 1:a0055b3280c8 207 // spi.write(0xB1); //CMD_PHY_OFF
shreeshas95 1:a0055b3280c8 208 // cs_adf=1;
shreeshas95 1:a0055b3280c8 209 // wait_us(PHY_ON_EXEC_TIME);// Typical = 24us We are giving 300us
shreeshas95 1:a0055b3280c8 210 // return assrt_phy_on(cmd_err_cnt,spi_err_cnt,state_err_cnt+1);
shreeshas95 1:a0055b3280c8 211 // }
shreeshas95 1:a0055b3280c8 212 // else if(status&0x80==0x00){
shreeshas95 1:a0055b3280c8 213 // wait_ms(5);
shreeshas95 1:a0055b3280c8 214 // //Error: SPI=0 Not ready CMD= Dont care
shreeshas95 1:a0055b3280c8 215 // return assrt_phy_on(cmd_err_cnt,spi_err_cnt+1,state_err_cnt);
shreeshas95 1:a0055b3280c8 216 // }
shreeshas95 1:a0055b3280c8 217 // else{
shreeshas95 1:a0055b3280c8 218 // if(status&0xA0==0x80){
shreeshas95 1:a0055b3280c8 219 // wait_ms(1);
shreeshas95 1:a0055b3280c8 220 // //Error: Command Not ready SPI Ready cmd_err_cnt is a global variable
shreeshas95 1:a0055b3280c8 221 // return assrt_phy_on(cmd_err_cnt+1,spi_err_cnt,state_err_cnt);
shreeshas95 1:a0055b3280c8 222 // }
shreeshas95 1:a0055b3280c8 223 // }
shreeshas95 1:a0055b3280c8 224 //}
shreeshas95 1:a0055b3280c8 225
shreeshas95 1:a0055b3280c8 226
shreeshas95 1:a0055b3280c8 227 // bool assrt_phy_tx(int cmd_err_cnt,int spi_err_cnt,int state_err_cnt){
shreeshas95 1:a0055b3280c8 228 // status=check_status();
shreeshas95 1:a0055b3280c8 229 // if((status & 0x1F) == 0x14){
shreeshas95 1:a0055b3280c8 230 // return 0;
shreeshas95 1:a0055b3280c8 231 // }
shreeshas95 1:a0055b3280c8 232 // else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){
shreeshas95 1:a0055b3280c8 233 // return 1;//You need to Reset the hardware
shreeshas95 1:a0055b3280c8 234 // }
shreeshas95 1:a0055b3280c8 235 // else if(state_err_cnt>STATE_ERR_THRS){
shreeshas95 1:a0055b3280c8 236 // return 1;//Again reset the hardware
shreeshas95 1:a0055b3280c8 237 // }
shreeshas95 1:a0055b3280c8 238 // else if((status&0xA0)==0xA0){ //If Status' first three bit ore 0b1X1 =>SPI ready, Dont care interrupt and CMD Ready.
shreeshas95 1:a0055b3280c8 239 // cs_adf=0;
shreeshas95 1:a0055b3280c8 240 // spi.write(0xB1); //CMD_PHY_OFF
shreeshas95 1:a0055b3280c8 241 // cs_adf=1;
shreeshas95 1:a0055b3280c8 242 // wait_us(PHY_TX_EXEC_TIME);// Typical = 24us We are giving 300us
shreeshas95 1:a0055b3280c8 243 // return assrt_phy_tx(cmd_err_cnt,spi_err_cnt,state_err_cnt+1);
shreeshas95 1:a0055b3280c8 244 // }
shreeshas95 1:a0055b3280c8 245 // else if(status&0x80==0x00){
shreeshas95 1:a0055b3280c8 246 // wait_ms(1);
shreeshas95 1:a0055b3280c8 247 // //Error: SPI=0 Not ready CMD= Dont care
shreeshas95 1:a0055b3280c8 248 // return assrt_phy_tx(cmd_err_cnt,spi_err_cnt+1,state_err_cnt);
shreeshas95 1:a0055b3280c8 249 // }
shreeshas95 1:a0055b3280c8 250 // else {
shreeshas95 1:a0055b3280c8 251 // if(status&0xA0==0x80){
shreeshas95 1:a0055b3280c8 252 // wait_us(50);
shreeshas95 1:a0055b3280c8 253 // //Error: Command Not ready SPI Ready cmd_err_cnt is a global variable
shreeshas95 1:a0055b3280c8 254 // return assrt_phy_tx(cmd_err_cnt+1,spi_err_cnt,state_err_cnt);
shreeshas95 1:a0055b3280c8 255 // }
shreeshas95 1:a0055b3280c8 256 // }
shreeshas95 1:a0055b3280c8 257 //}
shreeshas95 1:a0055b3280c8 258
shreeshas95 1:a0055b3280c8 259 bool hardware_reset(int bcn_call){
shreeshas95 1:a0055b3280c8 260 for(int i= 0; i < 20 ; i++){
shreeshas95 1:a0055b3280c8 261 gCS_ADF=0;
shreeshas95 1:a0055b3280c8 262 spi.write(CMD_HW_RESET);
shreeshas95 1:a0055b3280c8 263 gCS_ADF=1;
shreeshas95 1:a0055b3280c8 264 wait_ms(2);// Typically 1 ms
shreeshas95 1:a0055b3280c8 265 int count=0;
shreeshas95 1:a0055b3280c8 266 int temp_return = 0;
shreeshas95 1:a0055b3280c8 267 while(count<10 && miso_err_cnt<10){
shreeshas95 1:a0055b3280c8 268 if(MISO_PIN){
shreeshas95 1:a0055b3280c8 269 assrt_phy_off(temp_return);
shreeshas95 1:a0055b3280c8 270 if(!temp_return){
shreeshas95 1:a0055b3280c8 271 return 0;
shreeshas95 1:a0055b3280c8 272 }
shreeshas95 1:a0055b3280c8 273 count++;
shreeshas95 1:a0055b3280c8 274 }
shreeshas95 1:a0055b3280c8 275 else{
shreeshas95 1:a0055b3280c8 276 wait_us(50);
shreeshas95 1:a0055b3280c8 277 miso_err_cnt++;
shreeshas95 1:a0055b3280c8 278 }
shreeshas95 1:a0055b3280c8 279 }
shreeshas95 1:a0055b3280c8 280 }
shreeshas95 1:a0055b3280c8 281 return 1;
shreeshas95 1:a0055b3280c8 282 }
shreeshas95 1:a0055b3280c8 283
shreeshas95 1:a0055b3280c8 284 //bool hardware_reset(int bcn_call){
shreeshas95 1:a0055b3280c8 285 // if (bcn_call>20){//Worst Case 20seconds will be lost !
shreeshas95 1:a0055b3280c8 286 // return 1;
shreeshas95 1:a0055b3280c8 287 // }
shreeshas95 1:a0055b3280c8 288 // int count=0;
shreeshas95 1:a0055b3280c8 289 // cs_adf=0;
shreeshas95 1:a0055b3280c8 290 // spi.write(CMD_HW_RESET);
shreeshas95 1:a0055b3280c8 291 // cs_adf=1;
shreeshas95 1:a0055b3280c8 292 // wait_ms(2);// Typically 1 ms
shreeshas95 1:a0055b3280c8 293 // while(count<10 && miso_err_cnt<10){
shreeshas95 1:a0055b3280c8 294 // if(MISO_PIN){
shreeshas95 1:a0055b3280c8 295 // int temp_return;
shreeshas95 1:a0055b3280c8 296 // assrt_phy_off(0,0,0,temp_return);
shreeshas95 1:a0055b3280c8 297 // if(!temp_return){
shreeshas95 1:a0055b3280c8 298 // break;
shreeshas95 1:a0055b3280c8 299 // }
shreeshas95 1:a0055b3280c8 300 // count++;
shreeshas95 1:a0055b3280c8 301 // }
shreeshas95 1:a0055b3280c8 302 // else{
shreeshas95 1:a0055b3280c8 303 // wait_us(50);
shreeshas95 1:a0055b3280c8 304 // miso_err_cnt++;
shreeshas95 1:a0055b3280c8 305 // }
shreeshas95 1:a0055b3280c8 306 // }
shreeshas95 1:a0055b3280c8 307 // if(count==10 ||miso_err_cnt==10){
shreeshas95 1:a0055b3280c8 308 // return hardware_reset(bcn_call+1);
shreeshas95 1:a0055b3280c8 309 // }
shreeshas95 1:a0055b3280c8 310 // else
shreeshas95 1:a0055b3280c8 311 // return 0;
shreeshas95 1:a0055b3280c8 312 //
shreeshas95 1:a0055b3280c8 313 //}
shreeshas95 1:a0055b3280c8 314
shreeshas95 1:a0055b3280c8 315
shreeshas95 1:a0055b3280c8 316
shreeshas95 1:a0055b3280c8 317
shreeshas95 1:a0055b3280c8 318 //void initial_adf_check(){
shreeshas95 1:a0055b3280c8 319 // spi.write(CMD_PHY_OFF); //0xB0
shreeshas95 1:a0055b3280c8 320 // while(hw_reset_err_cnt<2){
shreeshas95 1:a0055b3280c8 321 //
shreeshas95 1:a0055b3280c8 322 // if(!assrt_phy_off(0,0,0)){ //assrt_phy_off () returns 0 if state is PHY_OFF , returns 1 if couldn't go to PHY_OFF
shreeshas95 1:a0055b3280c8 323 // bbram_write();
shreeshas95 1:a0055b3280c8 324 // bbram_flag=1;
shreeshas95 1:a0055b3280c8 325 // break;
shreeshas95 1:a0055b3280c8 326 // }
shreeshas95 1:a0055b3280c8 327 // else{
shreeshas95 1:a0055b3280c8 328 // hardware_reset(0); // Asserts Hardware for 20sec(20times). PHY_OFF for 20,000 times
shreeshas95 1:a0055b3280c8 329 // hw_reset_err_cnt++;
shreeshas95 1:a0055b3280c8 330 // }
shreeshas95 1:a0055b3280c8 331 // }
shreeshas95 1:a0055b3280c8 332 // assrt_phy_off(0,0,0);// We actually do not need this but make sure "we do not need this"
shreeshas95 1:a0055b3280c8 333 // if(!bbram_flag){
shreeshas95 1:a0055b3280c8 334 // //Switch to beacon
shreeshas95 1:a0055b3280c8 335 // bcn_flag=1;
shreeshas95 1:a0055b3280c8 336 // }
shreeshas95 1:a0055b3280c8 337 //}
shreeshas95 1:a0055b3280c8 338
shreeshas95 1:a0055b3280c8 339 //for reseting the transmission call assert function after b5 and b1. after b1 assert_phi_on and after b5 assert_phi_tx.
shreeshas95 1:a0055b3280c8 340 //----------------------------------------------------------------------------
shreeshas95 1:a0055b3280c8 341
shekhar 4:e37674541504 342 # define initiate {\//SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 343 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 344 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 345 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 346 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 347 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 348 spi.write(0x08);\
shreeshas95 1:a0055b3280c8 349 spi.write(0x14);\
shreeshas95 1:a0055b3280c8 350 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 351 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 352 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 353 spi.write(0x08);\
shreeshas95 1:a0055b3280c8 354 spi.write(0x15);\
shreeshas95 1:a0055b3280c8 355 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 356 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 357 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 358 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 359 spi.write(0x24);\
shreeshas95 1:a0055b3280c8 360 spi.write(0x20);\
shreeshas95 1:a0055b3280c8 361 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 362 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 363 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 364 spi.write(0x37);\
shreeshas95 1:a0055b3280c8 365 spi.write(0xE0);\
shreeshas95 1:a0055b3280c8 366 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 367 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 368 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 369 spi.write(0x36);\
shreeshas95 1:a0055b3280c8 370 spi.write(0x70);\
shreeshas95 1:a0055b3280c8 371 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 372 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 373 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 374 spi.write(0x39);\
shreeshas95 1:a0055b3280c8 375 spi.write(0x10);\
shekhar 4:e37674541504 376 gCS_ADF=1;\//SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 377 }
shreeshas95 1:a0055b3280c8 378
shreeshas95 1:a0055b3280c8 379
shekhar 4:e37674541504 380 #define write_data {\//SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 381 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 382 spi.write(0x0B);\
shreeshas95 1:a0055b3280c8 383 spi.write(0x36);\
shreeshas95 1:a0055b3280c8 384 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 385 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 386 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 387 if(buffer_state){\
shreeshas95 1:a0055b3280c8 388 spi.write(0x18);\
shreeshas95 1:a0055b3280c8 389 spi.write(0x20);\
shreeshas95 1:a0055b3280c8 390 for(unsigned char i=0; i<112;i++){\
shreeshas95 1:a0055b3280c8 391 spi.write(buffer_112[i]);\
shreeshas95 1:a0055b3280c8 392 }\
shreeshas95 1:a0055b3280c8 393 }\
shreeshas95 1:a0055b3280c8 394 else{\
shreeshas95 1:a0055b3280c8 395 spi.write(0x18);\
shreeshas95 1:a0055b3280c8 396 spi.write(0x90);\
shreeshas95 1:a0055b3280c8 397 for(unsigned char i=0; i<112;i++){\
shreeshas95 1:a0055b3280c8 398 spi.write(buffer_112[i]);\
shreeshas95 1:a0055b3280c8 399 }\
shreeshas95 1:a0055b3280c8 400 }\
shekhar 4:e37674541504 401 gCS_ADF=1;\//SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 402 buffer_state = !buffer_state;\
shreeshas95 1:a0055b3280c8 403 if(last_buffer){\
shreeshas95 1:a0055b3280c8 404 ADF_off = true;\
shreeshas95 1:a0055b3280c8 405 gPC.puts("adf_off\r\n");\
shreeshas95 1:a0055b3280c8 406 }\
shreeshas95 1:a0055b3280c8 407 }
shreeshas95 1:a0055b3280c8 408
shreeshas95 1:a0055b3280c8 409
shreeshas95 1:a0055b3280c8 410 void check(){
shreeshas95 1:a0055b3280c8 411 if(IRQ){
shreeshas95 1:a0055b3280c8 412 gCOM_MNG_TMTC_THREAD->signal_set(signal);
shreeshas95 1:a0055b3280c8 413 }
shreeshas95 1:a0055b3280c8 414 }
shreeshas95 1:a0055b3280c8 415
shreeshas95 1:a0055b3280c8 416
shekhar 4:e37674541504 417 #define send_data {\ // SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 418 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 419 spi.write(0xBB);\
shreeshas95 1:a0055b3280c8 420 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 421 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 422 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 423 spi.write(0xFF);\
shekhar 4:e37674541504 424 gCS_ADF=1;\ // SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 425 if(sent_tmfrom_SDcard){\
shreeshas95 1:a0055b3280c8 426 send_tm_from_SD_card();\
shreeshas95 1:a0055b3280c8 427 }else{\
shreeshas95 1:a0055b3280c8 428 snd_tm.transmit_data(buffer_112,&last_buffer);\
shreeshas95 1:a0055b3280c8 429 }\
shreeshas95 1:a0055b3280c8 430 write_data;\
shreeshas95 1:a0055b3280c8 431 if(sent_tmfrom_SDcard){\
shreeshas95 1:a0055b3280c8 432 send_tm_from_SD_card();\
shreeshas95 1:a0055b3280c8 433 }else{\
shreeshas95 1:a0055b3280c8 434 snd_tm.transmit_data(buffer_112,&last_buffer);\
shreeshas95 1:a0055b3280c8 435 }\
shreeshas95 1:a0055b3280c8 436 write_data;\
shreeshas95 1:a0055b3280c8 437 if(sent_tmfrom_SDcard){\
shreeshas95 1:a0055b3280c8 438 send_tm_from_SD_card();\
shreeshas95 1:a0055b3280c8 439 }else{\
shreeshas95 1:a0055b3280c8 440 snd_tm.transmit_data(buffer_112,&last_buffer);\
shekhar 4:e37674541504 441 }\ //SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 442 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 443 spi.write(0xB1);\
shreeshas95 1:a0055b3280c8 444 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 445 wait_us(300);\
shreeshas95 1:a0055b3280c8 446 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 447 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 448 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 449 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 450 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 451 spi.write(0xB5);\
shreeshas95 1:a0055b3280c8 452 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 453 wait_us(300);\
shreeshas95 1:a0055b3280c8 454 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 455 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 456 spi.write(0xFF);\
shekhar 4:e37674541504 457 gCS_ADF=1;\ //SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 458 ticker.attach_us(&check,32000);\
shreeshas95 1:a0055b3280c8 459 }
shreeshas95 1:a0055b3280c8 460
shreeshas95 1:a0055b3280c8 461
shreeshas95 1:a0055b3280c8 462
shekhar 4:e37674541504 463 //#define adf_SND_SDCard {\
shekhar 4:e37674541504 464 // buffer_state = true;\
shekhar 4:e37674541504 465 // last_buffer = false;\
shekhar 4:e37674541504 466 // loop_on = true;\
shekhar 4:e37674541504 467 // ADF_off = false;\
shekhar 4:e37674541504 468 // sent_tmfrom_SDcard = true;\
shekhar 4:e37674541504 469 // signal = COM_MNG_TMTC_SIGNAL_ADF_SD;\
shekhar 4:e37674541504 470 // start_block_num = starting_add;\
shekhar 4:e37674541504 471 // end_block_num = ending_add;\
shekhar 4:e37674541504 472 // initial_adf_check;\
shekhar 4:e37674541504 473 // initiate;\
shekhar 4:e37674541504 474 // send_data;\
shekhar 4:e37674541504 475 // while(loop_on){\
shekhar 4:e37674541504 476 // /*led2=!led2;*/\
shekhar 4:e37674541504 477 // gCOM_MNG_TMTC_THREAD->signal_wait(COM_MNG_TMTC_SIGNAL_ADF_SD);\
shekhar 4:e37674541504 478 // if(ADF_off){\
shekhar 4:e37674541504 479 // SPI_mutex.lock();\
shekhar 4:e37674541504 480 // ticker.detach();\
shekhar 4:e37674541504 481 // gCS_ADF=0;\
shekhar 4:e37674541504 482 // spi.write(0xB1);\
shekhar 4:e37674541504 483 // gCS_ADF=1;\
shekhar 4:e37674541504 484 // SPI_mutex.unlock();\
shekhar 4:e37674541504 485 // gPC.puts("transmission done\r\n");\
shekhar 4:e37674541504 486 // loop_on = false;\
shekhar 4:e37674541504 487 // }else{\
shekhar 4:e37674541504 488 // write_data;\
shekhar 4:e37674541504 489 // if(!last_buffer)\
shekhar 4:e37674541504 490 // send_tm_from_SD_card();\
shekhar 4:e37674541504 491 // }\
shekhar 4:e37674541504 492 // }\
shekhar 4:e37674541504 493 //}
shreeshas95 1:a0055b3280c8 494
shekhar 4:e37674541504 495 //void read_TC(Base_tc* TC_ptr){
shekhar 4:e37674541504 496 // gPC.puts("Inside sd card sending\r\n");
shekhar 4:e37674541504 497 // unsigned char service_subtype = 0;
shekhar 4:e37674541504 498 // uint64_t starting_add = 0, ending_add = 0;
shekhar 4:e37674541504 499 // service_subtype = (TC_ptr->TC_string[2])&0x0f;
shekhar 4:e37674541504 500 // starting_add = (TC_ptr->TC_string[5]) + ( (TC_ptr->TC_string[4])<<8 ) + ( (TC_ptr->TC_string[3]) <<16);
shekhar 4:e37674541504 501 // ending_add = (TC_ptr->TC_string[8]) + ( (TC_ptr->TC_string[7])<<8 ) + ( (TC_ptr->TC_string[6]) <<16);
shekhar 4:e37674541504 502 // starting_add = 10; // for now
shekhar 4:e37674541504 503 // ending_add = 20;
shekhar 4:e37674541504 504 //// adf_SND_SDCard(starting_add , ending_add);
shekhar 4:e37674541504 505 // gPC.puts("sending from sd card\r\n");
shekhar 4:e37674541504 506 // adf_SND_SDCard;
shekhar 4:e37674541504 507 //}
shreeshas95 2:2caf2a9a13aa 508
shreeshas95 2:2caf2a9a13aa 509 //Timeout ADF_non_responsive_timeout;
shreeshas95 2:2caf2a9a13aa 510 //bool ADF_non_responsive_flag = false;
shreeshas95 2:2caf2a9a13aa 511 //
shreeshas95 2:2caf2a9a13aa 512 //void ADF_non_responsive_fun(){
shreeshas95 2:2caf2a9a13aa 513 // ADF_non_responsive_flag = true;
shreeshas95 2:2caf2a9a13aa 514 // gCOM_MNG_TMTC_THREAD->signal_set(signal);
shreeshas95 2:2caf2a9a13aa 515 //}
shreeshas95 1:a0055b3280c8 516
shreeshas95 1:a0055b3280c8 517 void adf_not_SDcard(){
shreeshas95 1:a0055b3280c8 518 buffer_state = true;
shreeshas95 1:a0055b3280c8 519 last_buffer = false;
shreeshas95 1:a0055b3280c8 520 loop_on = true;
shreeshas95 1:a0055b3280c8 521 ADF_off = false;
shreeshas95 1:a0055b3280c8 522 sent_tmfrom_SDcard = false;
shreeshas95 1:a0055b3280c8 523
shekhar 4:e37674541504 524 // signal = COM_MNG_TMTC_SIGNAL_ADF_NSD;
shreeshas95 1:a0055b3280c8 525 initial_adf_check;
shreeshas95 1:a0055b3280c8 526 initiate;
shreeshas95 1:a0055b3280c8 527 send_data;
shreeshas95 2:2caf2a9a13aa 528
shreeshas95 2:2caf2a9a13aa 529 // gPC.puts("Inside adf transmission\r\n");
shreeshas95 2:2caf2a9a13aa 530 // ADF_non_responsive_timeout.attach(&ADF_non_responsive_fun, 10);
shreeshas95 1:a0055b3280c8 531
shreeshas95 1:a0055b3280c8 532 while(loop_on){
shreeshas95 3:6c81fc8834e2 533 gCOM_MNG_TMTC_THREAD->signal_wait(COM_MNG_TMTC_SIGNAL_ADF_NSD);
shreeshas95 2:2caf2a9a13aa 534 // if( ADF_non_responsive_flag == false ){
shreeshas95 2:2caf2a9a13aa 535 if(ADF_off){
shreeshas95 2:2caf2a9a13aa 536 SPI_mutex.lock();
shreeshas95 2:2caf2a9a13aa 537 ticker.detach();
shreeshas95 2:2caf2a9a13aa 538 // wait_ms(35);
shreeshas95 2:2caf2a9a13aa 539 gCS_ADF=0;
shreeshas95 2:2caf2a9a13aa 540 spi.write(0xB1);
shreeshas95 2:2caf2a9a13aa 541 gCS_ADF=1;
shreeshas95 2:2caf2a9a13aa 542 SPI_mutex.unlock();
shreeshas95 2:2caf2a9a13aa 543 loop_on = false;
shreeshas95 2:2caf2a9a13aa 544 }else{
shreeshas95 2:2caf2a9a13aa 545 write_data;
shreeshas95 2:2caf2a9a13aa 546 snd_tm.transmit_data(buffer_112,&last_buffer);
shreeshas95 2:2caf2a9a13aa 547 }
shreeshas95 2:2caf2a9a13aa 548 // }
shreeshas95 2:2caf2a9a13aa 549 // else{
shreeshas95 2:2caf2a9a13aa 550 // gPC.puts("ADF non responsive\r\n");
shreeshas95 2:2caf2a9a13aa 551 // break;
shreeshas95 2:2caf2a9a13aa 552 // }
shreeshas95 1:a0055b3280c8 553 }
shreeshas95 1:a0055b3280c8 554 }
shreeshas95 1:a0055b3280c8 555