pradeep shekhar / Mbed 2 deprecated Beacon_BAE_intergration_test_3

General testings

Dependencies:   mbed

Fork of BEACON_CODE_NEW by Mohamed Azad

Files at this revision

API Documentation at this revision

Revision 33:27c84141086d, committed 2016-05-18

Comitter:
shekhar
Date:
Wed May 18 18:49:26 2016 +0000
Parent:
32:e5d6c0cffa82
Commit message:
added fifoaf check

Changed in this revision

BCN.cpp Show annotated file Show diff for this revision Revisions of this file 
diff -r e5d6c0cffa82 -r 27c84141086d BCN.cpp
--- a/BCN.cpp	Tue May 17 15:13:49 2016 +0000
+++ b/BCN.cpp	Wed May 18 18:49:26 2016 +0000
@@ -216,34 +216,30 @@
             //pc_bcn.printf("Time taken to write one byte = %d\r\n",spi_end-spi_start);
         }     
         
-        if(byte_counter % 2 == 1)
+        if(byte_counter == 1)
         {
            
             //Set to Tx mode
             writereg(RF22_REG_07_OPERATING_MODE1,0x08);       //txon
             wait(0.1);// takes time to set to tx mode hence the delay of 0.1.  
-            
-            //Check for fifoThresh
-            while(timeout_count--)if((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) == 0x20)break;else if(timeout_count == 1)
-            {
-                pc_bcn.printf("Reset\n");
-                 reset_rfm(1);}
-            timeout_count=10e5;
-            
+
         }
         
+        //Check for fifoThresh
+        if(!byte_counter)
+        while(timeout_count--)if((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) == 0x20)break;else if(timeout_count == 1)
+        {
+            pc_bcn.printf("Reset\n");
+            reset_rfm(1);
+        }
+        timeout_count=10e5;
+                
     }   
-     
-    //Set to Tx mode
-    writereg(RF22_REG_07_OPERATING_MODE1,0x08);       //txon
-    wait(0.1);// takes time to set to tx mode hence the delay of 0.1.  
     
     //Check for fifoThresh
-    while(timeout_count--)if((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) == 0x20)break;else if(timeout_count == 1) 
+    while(1)if((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x40) == 0x00)break;else 
     {
-        pc_bcn.printf("Reset\n");
-    reset_rfm(1);}
-    timeout_count=10e5;
+        pc_bcn.printf("Waiting for fifo to empty\n");}
     
     //Check for packetsent interrupt
     while(timeout_count--)if((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) == 0x04)break;else if(timeout_count == 1) reset_rfm(1);
@@ -414,6 +410,10 @@
        
     //txfifoalmostempty
     writereg(RF22_REG_7D_TX_FIFO_CONTROL2,30);
+    
+    //txfifoalmostfull
+    writereg(RF22_REG_7C_TX_FIFO_CONTROL1,1);
+    
 
     //Packet-engine registers
     writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x00);