pradeep shekhar / Mbed 2 deprecated 14-8-15_beacon_testing

Repo for beacon testing

Dependencies:   mbed

main.cpp@2:298924eb2b41, 2015-08-15 (annotated)

Committer:
shekhar
Date:
Sat Aug 15 14:12:27 2015 +0000
Revision:
2:298924eb2b41
Parent:
1:91c435a6966b
Child:
3:b2acafb06072
Code corrected...ready to be tested on USRP;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shekhar 0:15b2487c185c 1 #include "beacon.h"
shekhar 0:15b2487c185c 2 Serial pc(USBTX, USBRX); // tx, rx
shekhar 0:15b2487c185c 3 SPI spi(D11, D12, D13); // mosi, miso, sclk
shekhar 0:15b2487c185c 4 //SPI spi(PTA16, PTA17, PTA15); // mosi, miso, sclk
shekhar 0:15b2487c185c 5 DigitalOut cs(D10); //slave select or chip select
shekhar 0:15b2487c185c 6
shekhar 0:15b2487c185c 7 void writereg(uint8_t reg,uint8_t val)
shekhar 0:15b2487c185c 8 {
shekhar 0:15b2487c185c 9 cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1;
shekhar 0:15b2487c185c 10 }
shekhar 0:15b2487c185c 11 uint8_t readreg(uint8_t reg)
shekhar 0:15b2487c185c 12 {
shekhar 0:15b2487c185c 13 int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val;
shekhar 0:15b2487c185c 14 }
shekhar 0:15b2487c185c 15 void clearTxBuf()
shekhar 0:15b2487c185c 16 {
shekhar 0:15b2487c185c 17 writereg(RF22_REG_08_OPERATING_MODE2,0x01);
shekhar 0:15b2487c185c 18 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
shekhar 0:15b2487c185c 19 }
shekhar 0:15b2487c185c 20 void clearRxBuf()
shekhar 0:15b2487c185c 21 {
shekhar 0:15b2487c185c 22 writereg(RF22_REG_08_OPERATING_MODE2,0x02);
shekhar 0:15b2487c185c 23 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
shekhar 0:15b2487c185c 24 }
shekhar 0:15b2487c185c 25 int setFrequency(float centre,float afcPullInRange)
shekhar 0:15b2487c185c 26 {
shekhar 0:15b2487c185c 27 //freq setting begins
shekhar 0:15b2487c185c 28 uint8_t fbsel = 0x40;
shekhar 0:15b2487c185c 29 uint8_t afclimiter;
shekhar 0:15b2487c185c 30 if (centre >= 480.0) {
shekhar 0:15b2487c185c 31 centre /= 2;
shekhar 0:15b2487c185c 32 fbsel |= 0x20;
shekhar 0:15b2487c185c 33 afclimiter = afcPullInRange * 1000000.0 / 1250.0;
shekhar 0:15b2487c185c 34 } else {
shekhar 0:15b2487c185c 35 if (afcPullInRange < 0.0 || afcPullInRange > 0.159375)
shekhar 0:15b2487c185c 36 return false;
shekhar 0:15b2487c185c 37 afclimiter = afcPullInRange * 1000000.0 / 625.0;
shekhar 0:15b2487c185c 38 }
shekhar 0:15b2487c185c 39 centre /= 10.0;
shekhar 0:15b2487c185c 40 float integerPart = floor(centre);
shekhar 0:15b2487c185c 41 float fractionalPart = centre - integerPart;
shekhar 0:15b2487c185c 42
shekhar 0:15b2487c185c 43 uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23
shekhar 0:15b2487c185c 44 fbsel |= fb;
shekhar 0:15b2487c185c 45 uint16_t fc = fractionalPart * 64000;
shekhar 0:15b2487c185c 46 writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT
shekhar 0:15b2487c185c 47 writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0);
shekhar 0:15b2487c185c 48 writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel);
shekhar 0:15b2487c185c 49 writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8);
shekhar 0:15b2487c185c 50 writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff);
shekhar 0:15b2487c185c 51 writereg(RF22_REG_2A_AFC_LIMITER, afclimiter);
shekhar 0:15b2487c185c 52 return 0;
shekhar 0:15b2487c185c 53 }
shekhar 0:15b2487c185c 54
shekhar 0:15b2487c185c 55 void init()
shekhar 0:15b2487c185c 56 {
shekhar 0:15b2487c185c 57 //reset()
shekhar 0:15b2487c185c 58 writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset
shekhar 0:15b2487c185c 59 wait(1); //takes time to reset
shekhar 0:15b2487c185c 60
shekhar 0:15b2487c185c 61 clearTxBuf();
shekhar 0:15b2487c185c 62 clearRxBuf();
shekhar 0:15b2487c185c 63 //txfifoalmostempty
shekhar 0:15b2487c185c 64 writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10);
shekhar 0:15b2487c185c 65 //rxfifoalmostfull
shekhar 0:15b2487c185c 66 writereg(RF22_REG_7E_RX_FIFO_CONTROL,20);
shekhar 0:15b2487c185c 67 //Packet-engine registers
shekhar 2:298924eb2b41 68 writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x00); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
shekhar 2:298924eb2b41 69 //0x00
shekhar 1:91c435a6966b 70
shekhar 1:91c435a6966b 71
shekhar 2:298924eb2b41 72 //writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3 //not reqiured for tx
shekhar 2:298924eb2b41 73 writereg(RF22_REG_33_HEADER_CONTROL2,0x08); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
shekhar 2:298924eb2b41 74 //why 0x42 //or 0x00??
shekhar 2:298924eb2b41 75
shekhar 2:298924eb2b41 76 writereg(RF22_REG_34_PREAMBLE_LENGTH,0x00); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
shekhar 1:91c435a6966b 77 //why is preamble used??
shekhar 1:91c435a6966b 78
shekhar 2:298924eb2b41 79 //writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D
shekhar 1:91c435a6966b 80 //why??
shekhar 1:91c435a6966b 81
shekhar 2:298924eb2b41 82 //writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4
shekhar 1:91c435a6966b 83 //why??
shekhar 1:91c435a6966b 84
shekhar 2:298924eb2b41 85 //writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
shekhar 1:91c435a6966b 86
shekhar 1:91c435a6966b 87
shekhar 1:91c435a6966b 88 //why all these headers
shekhar 2:298924eb2b41 89 //writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to
shekhar 2:298924eb2b41 90 //writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from
shekhar 2:298924eb2b41 91 //writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids
shekhar 2:298924eb2b41 92 //writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags
shekhar 2:298924eb2b41 93 //writereg(RF22_REG_3F_CHECK_HEADER3,0xab);
shekhar 2:298924eb2b41 94 //writereg(RF22_REG_40_CHECK_HEADER2,0xbc);
shekhar 2:298924eb2b41 95 //writereg(RF22_REG_41_CHECK_HEADER1,0xcd);
shekhar 2:298924eb2b41 96 //writereg(RF22_REG_42_CHECK_HEADER0,0xde);
shekhar 0:15b2487c185c 97
shekhar 1:91c435a6966b 98 //RSSI threshold for clear channel indicator //rx
shekhar 2:298924eb2b41 99 //writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
shekhar 0:15b2487c185c 100
shekhar 0:15b2487c185c 101 writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ??
shekhar 0:15b2487c185c 102 writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ??
shekhar 0:15b2487c185c 103
shekhar 0:15b2487c185c 104 //interrupts
shekhar 0:15b2487c185c 105 // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
shekhar 0:15b2487c185c 106 // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
shekhar 0:15b2487c185c 107
shekhar 1:91c435a6966b 108 setFrequency(435.0, 0.05);//check
shekhar 0:15b2487c185c 109
shekhar 0:15b2487c185c 110 //return !(statusRead() & RF22_FREQERR);
shekhar 0:15b2487c185c 111 if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
shekhar 0:15b2487c185c 112 pc.printf("frequency not set properly\n");
shekhar 0:15b2487c185c 113 //frequency set
shekhar 0:15b2487c185c 114
shekhar 0:15b2487c185c 115 //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz
shekhar 0:15b2487c185c 116 //setmodemregisters
shekhar 0:15b2487c185c 117 //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36
shekhar 0:15b2487c185c 118 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335
shekhar 0:15b2487c185c 119 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf);
shekhar 0:15b2487c185c 120 writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03);
shekhar 0:15b2487c185c 121 writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39);
shekhar 0:15b2487c185c 122 writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20);
shekhar 0:15b2487c185c 123 writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk
shekhar 0:15b2487c185c 124 writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc);
shekhar 0:15b2487c185c 125 writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00);
shekhar 0:15b2487c185c 126 writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B);
shekhar 0:15b2487c185c 127 writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C);
shekhar 0:15b2487c185c 128 writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11); //not required for fsk (OOK counter value)
shekhar 0:15b2487c185c 129 writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A); //??
shekhar 0:15b2487c185c 130 writereg(RF22_REG_58,0x80);
shekhar 0:15b2487c185c 131 writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
shekhar 1:91c435a6966b 132
shekhar 2:298924eb2b41 133 //check...//also depends on 0x70[5]
shekhar 0:15b2487c185c 134 writereg(RF22_REG_6E_TX_DATA_RATE1,0x09);//TX at 0.123kbps=:6E=0x01; 6F=0x02
shekhar 2:298924eb2b41 135 writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5);//TX at 1.2kbps: 6E=0x09; 6F=0xd5 //Formula: tx_datarate*(2^21)/10^6
shekhar 2:298924eb2b41 136 //
shekhar 1:91c435a6966b 137
shekhar 0:15b2487c185c 138 writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
shekhar 0:15b2487c185c 139 writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22
shekhar 1:91c435a6966b 140
shekhar 2:298924eb2b41 141 //writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50);
shekhar 1:91c435a6966b 142 //required for OOK???
shekhar 1:91c435a6966b 143
shekhar 0:15b2487c185c 144 //set tx power
shekhar 2:298924eb2b41 145 writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm
shekhar 2:298924eb2b41 146 //why 0x06?? 0x07 is for max//is the previous bits required?
shekhar 1:91c435a6966b 147
shekhar 0:15b2487c185c 148 //writereg(RF22_REG_6D_TX_POWER,0x00); //-1dbm
shekhar 2:298924eb2b41 149 //writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length
shekhar 1:91c435a6966b 150 //packet length not required
shekhar 1:91c435a6966b 151
shekhar 0:15b2487c185c 152 }
shekhar 0:15b2487c185c 153 int main()
shekhar 0:15b2487c185c 154 {
shekhar 0:15b2487c185c 155 wait(1); // wait for POR to complete //change the timing later
shekhar 0:15b2487c185c 156 cs=1; // chip must be deselected
shekhar 0:15b2487c185c 157 wait(1); //change the time later
shekhar 0:15b2487c185c 158 spi.format(8,0);
shekhar 0:15b2487c185c 159 spi.frequency(10000000); //10MHz SCLK
shekhar 0:15b2487c185c 160 if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n");
shekhar 0:15b2487c185c 161 else pc.printf("error in spi connection\n");
shekhar 0:15b2487c185c 162
shekhar 0:15b2487c185c 163 init();
shekhar 0:15b2487c185c 164
shekhar 0:15b2487c185c 165
shekhar 0:15b2487c185c 166 //init complete
shekhar 0:15b2487c185c 167 pc.printf("init complete.....press t to send\n");
shekhar 0:15b2487c185c 168
shekhar 0:15b2487c185c 169
shekhar 0:15b2487c185c 170 //********
shekhar 0:15b2487c185c 171
shekhar 0:15b2487c185c 172 while(pc.getc()=='t') //1
shekhar 0:15b2487c185c 173 {
shekhar 0:15b2487c185c 174 /*uint8_t data[] = "Hello World!";
shekhar 0:15b2487c185c 175 pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/
shekhar 0:15b2487c185c 176
shekhar 0:15b2487c185c 177 uint8_t data[255]; //starts from 0,1,2,3,4!!!;
shekhar 0:15b2487c185c 178 int i = 0; //for loops
shekhar 0:15b2487c185c 179 int u = 0; //universal count for hk array
shekhar 0:15b2487c185c 180 int bar = 0;
shekhar 0:15b2487c185c 181 //filling hk data
shekhar 0:15b2487c185c 182 /*for(int n=0; n<1; n++)
shekhar 0:15b2487c185c 183 data[n] = 0xAA;
shekhar 0:15b2487c185c 184 data[1] = 0x3A; */
shekhar 0:15b2487c185c 185 //for(int n=0; n<15; n++)
shekhar 0:15b2487c185c 186 /*data[0] = 0xAB;
shekhar 0:15b2487c185c 187 data[1] = 0x8A;
shekhar 0:15b2487c185c 188 data[2] = 0xE2;
shekhar 0:15b2487c185c 189 data[3] = 0xBB;
shekhar 0:15b2487c185c 190 data[4] = 0xB8;
shekhar 0:15b2487c185c 191 data[5] = 0xA2;
shekhar 0:15b2487c185c 192 data[6] = 0x8E;
shekhar 0:15b2487c185c 193 data[7] = 0x88;
shekhar 0:15b2487c185c 194 data[8] = 0x99;
shekhar 0:15b2487c185c 195 data[9] = 0xAA;
shekhar 0:15b2487c185c 196 data[10] = 0xAA;
shekhar 0:15b2487c185c 197 data[11] = 0xAA;
shekhar 0:15b2487c185c 198 data[12] = 0xDD;
shekhar 0:15b2487c185c 199 data[13] = 0xEE;
shekhar 0:15b2487c185c 200 data[14] = 0x00;
shekhar 0:15b2487c185c 201 */
shekhar 0:15b2487c185c 202 /*for(int n=50; n<60; n++)
shekhar 0:15b2487c185c 203 data[n] = n; */
shekhar 0:15b2487c185c 204 //for(int n=60; n<120; n++)
shekhar 0:15b2487c185c 205 // data[n] = 0x11;
shekhar 0:15b2487c185c 206 /*for(int n=75; n<97; n++)
shekhar 0:15b2487c185c 207 data[n] = 0xBC;
shekhar 0:15b2487c185c 208 for(int n=97; n<110; n++)
shekhar 0:15b2487c185c 209 data[n] = 0xEC;
shekhar 0:15b2487c185c 210 for(int n=110; n<120; n++)
shekhar 0:15b2487c185c 211 data[n] = 0xFC; */
shekhar 0:15b2487c185c 212 for(int n=0; n<255; n++)
shekhar 0:15b2487c185c 213 data[n] = 0xAB;
shekhar 0:15b2487c185c 214 /*uint8_t stuff[] = "IITMSAT IITMSAT";
shekhar 0:15b2487c185c 215 for(int i = 0 ; i < 15 ; ++i){
shekhar 0:15b2487c185c 216 data[i] = stuff[i];
shekhar 0:15b2487c185c 217 }*/
shekhar 0:15b2487c185c 218
shekhar 0:15b2487c185c 219 //for(int n=150; n<TX_DATA; n++)
shekhar 0:15b2487c185c 220 // data[n] = 0x11;
shekhar 0:15b2487c185c 221 //tx settings begin
shekhar 0:15b2487c185c 222
shekhar 0:15b2487c185c 223 //setModeIdle();
shekhar 0:15b2487c185c 224 writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode
shekhar 0:15b2487c185c 225 //fillTxBuf(data, len);
shekhar 0:15b2487c185c 226 clearTxBuf();
shekhar 0:15b2487c185c 227 //Filling Data into FIFO for the first time
shekhar 0:15b2487c185c 228 /*cs = 0;
shekhar 0:15b2487c185c 229 spi.write(0xFF); //fifo write access
shekhar 0:15b2487c185c 230 for(i=0; i<datalen; i++){
shekhar 0:15b2487c185c 231 spi.write(data[i]);
shekhar 0:15b2487c185c 232 pc.printf("0x%X \n",data[u+i]);
shekhar 0:15b2487c185c 233 }
shekhar 0:15b2487c185c 234 u=i;//check its 64
shekhar 0:15b2487c185c 235 cs = 1; */
shekhar 0:15b2487c185c 236
shekhar 0:15b2487c185c 237 //Set to Tx mode
shekhar 0:15b2487c185c 238 writereg(RF22_REG_07_OPERATING_MODE1,0x09);
shekhar 0:15b2487c185c 239
shekhar 0:15b2487c185c 240 //Check for fifoempty Thresh
shekhar 0:15b2487c185c 241 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20);
shekhar 0:15b2487c185c 242
shekhar 0:15b2487c185c 243 while(u!=TX_DATA) {
shekhar 0:15b2487c185c 244 if((TX_DATA - u) >= TIMES)
shekhar 0:15b2487c185c 245 bar = TIMES;
shekhar 0:15b2487c185c 246 else
shekhar 0:15b2487c185c 247 bar = (TX_DATA - u);
shekhar 0:15b2487c185c 248
shekhar 0:15b2487c185c 249 //writing again
shekhar 0:15b2487c185c 250 cs = 0;
shekhar 0:15b2487c185c 251 spi.write(0xFF); //FIFO write access
shekhar 0:15b2487c185c 252 for(i=0; i<bar; i++,u++)
shekhar 0:15b2487c185c 253 {
shekhar 0:15b2487c185c 254
shekhar 0:15b2487c185c 255 //spi.write(data[i]);
shekhar 0:15b2487c185c 256 spi.write(0xAA) ;
shekhar 0:15b2487c185c 257 //pc.printf("0x%X 0x%X \r\n",data[i],u);
shekhar 0:15b2487c185c 258 }
shekhar 0:15b2487c185c 259 //u = u + i;
shekhar 0:15b2487c185c 260 cs = 1;
shekhar 0:15b2487c185c 261 //Check for fifoThresh
shekhar 0:15b2487c185c 262 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20);
shekhar 0:15b2487c185c 263 }
shekhar 0:15b2487c185c 264 //rf22.waitPacketSent();
shekhar 0:15b2487c185c 265 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n");
shekhar 0:15b2487c185c 266 pc.printf(" packet sent ");
shekhar 0:15b2487c185c 267
shekhar 0:15b2487c185c 268 }
shekhar 0:15b2487c185c 269 }