pradeep shekhar / Mbed 2 deprecated 13_7_2015_1

Test codes for RFM22B

Dependencies:   mbed

main.cpp@0:cc2af8aa4091, 2015-08-15 (annotated)

Committer:
shekhar
Date:
Sat Aug 15 11:48:59 2015 +0000
Revision:
0:cc2af8aa4091
Original RFM22B code.; Able to transmit successfully.; Not sure if transmitted info is correct.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shekhar 0:cc2af8aa4091 1 #include "beacon.h"
shekhar 0:cc2af8aa4091 2 Serial pc(USBTX, USBRX); // tx, rx
shekhar 0:cc2af8aa4091 3 SPI spi(D11, D12, D13); // mosi, miso, sclk
shekhar 0:cc2af8aa4091 4 //SPI spi(PTA16, PTA17, PTA15); // mosi, miso, sclk
shekhar 0:cc2af8aa4091 5 DigitalOut cs(D10); //slave select or chip select
shekhar 0:cc2af8aa4091 6
shekhar 0:cc2af8aa4091 7 void writereg(uint8_t reg,uint8_t val)
shekhar 0:cc2af8aa4091 8 {
shekhar 0:cc2af8aa4091 9 cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1;
shekhar 0:cc2af8aa4091 10 }
shekhar 0:cc2af8aa4091 11 uint8_t readreg(uint8_t reg)
shekhar 0:cc2af8aa4091 12 {
shekhar 0:cc2af8aa4091 13 int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val;
shekhar 0:cc2af8aa4091 14 }
shekhar 0:cc2af8aa4091 15 void clearTxBuf()
shekhar 0:cc2af8aa4091 16 {
shekhar 0:cc2af8aa4091 17 writereg(RF22_REG_08_OPERATING_MODE2,0x01);
shekhar 0:cc2af8aa4091 18 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
shekhar 0:cc2af8aa4091 19 }
shekhar 0:cc2af8aa4091 20 void clearRxBuf()
shekhar 0:cc2af8aa4091 21 {
shekhar 0:cc2af8aa4091 22 writereg(RF22_REG_08_OPERATING_MODE2,0x02);
shekhar 0:cc2af8aa4091 23 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
shekhar 0:cc2af8aa4091 24 }
shekhar 0:cc2af8aa4091 25 int setFrequency(float centre,float afcPullInRange)
shekhar 0:cc2af8aa4091 26 {
shekhar 0:cc2af8aa4091 27 //freq setting begins
shekhar 0:cc2af8aa4091 28 uint8_t fbsel = 0x40;
shekhar 0:cc2af8aa4091 29 uint8_t afclimiter;
shekhar 0:cc2af8aa4091 30 if (centre >= 480.0) {
shekhar 0:cc2af8aa4091 31 centre /= 2;
shekhar 0:cc2af8aa4091 32 fbsel |= 0x20;
shekhar 0:cc2af8aa4091 33 afclimiter = afcPullInRange * 1000000.0 / 1250.0;
shekhar 0:cc2af8aa4091 34 } else {
shekhar 0:cc2af8aa4091 35 if (afcPullInRange < 0.0 || afcPullInRange > 0.159375)
shekhar 0:cc2af8aa4091 36 return false;
shekhar 0:cc2af8aa4091 37 afclimiter = afcPullInRange * 1000000.0 / 625.0;
shekhar 0:cc2af8aa4091 38 }
shekhar 0:cc2af8aa4091 39 centre /= 10.0;
shekhar 0:cc2af8aa4091 40 float integerPart = floor(centre);
shekhar 0:cc2af8aa4091 41 float fractionalPart = centre - integerPart;
shekhar 0:cc2af8aa4091 42
shekhar 0:cc2af8aa4091 43 uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23
shekhar 0:cc2af8aa4091 44 fbsel |= fb;
shekhar 0:cc2af8aa4091 45 uint16_t fc = fractionalPart * 64000;
shekhar 0:cc2af8aa4091 46 writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT
shekhar 0:cc2af8aa4091 47 writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0);
shekhar 0:cc2af8aa4091 48 writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel);
shekhar 0:cc2af8aa4091 49 writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8);
shekhar 0:cc2af8aa4091 50 writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff);
shekhar 0:cc2af8aa4091 51 writereg(RF22_REG_2A_AFC_LIMITER, afclimiter);
shekhar 0:cc2af8aa4091 52 return 0;
shekhar 0:cc2af8aa4091 53 }
shekhar 0:cc2af8aa4091 54
shekhar 0:cc2af8aa4091 55 void init()
shekhar 0:cc2af8aa4091 56 {
shekhar 0:cc2af8aa4091 57 //reset()
shekhar 0:cc2af8aa4091 58 writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset
shekhar 0:cc2af8aa4091 59 wait(1); //takes time to reset
shekhar 0:cc2af8aa4091 60
shekhar 0:cc2af8aa4091 61 clearTxBuf();
shekhar 0:cc2af8aa4091 62 clearRxBuf();
shekhar 0:cc2af8aa4091 63 //txfifoalmostempty
shekhar 0:cc2af8aa4091 64 writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10);
shekhar 0:cc2af8aa4091 65 //rxfifoalmostfull
shekhar 0:cc2af8aa4091 66 writereg(RF22_REG_7E_RX_FIFO_CONTROL,20);
shekhar 0:cc2af8aa4091 67 //Packet-engine registers
shekhar 0:cc2af8aa4091 68 writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
shekhar 0:cc2af8aa4091 69 //&0x77 = diasable packet rx-tx handling
shekhar 0:cc2af8aa4091 70 writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3
shekhar 0:cc2af8aa4091 71 writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
shekhar 0:cc2af8aa4091 72 writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
shekhar 0:cc2af8aa4091 73 writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D
shekhar 0:cc2af8aa4091 74 writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4
shekhar 0:cc2af8aa4091 75 writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
shekhar 0:cc2af8aa4091 76 writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to
shekhar 0:cc2af8aa4091 77 writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from
shekhar 0:cc2af8aa4091 78 writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids
shekhar 0:cc2af8aa4091 79 writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags
shekhar 0:cc2af8aa4091 80 writereg(RF22_REG_3F_CHECK_HEADER3,0xab);
shekhar 0:cc2af8aa4091 81 writereg(RF22_REG_40_CHECK_HEADER2,0xbc);
shekhar 0:cc2af8aa4091 82 writereg(RF22_REG_41_CHECK_HEADER1,0xcd);
shekhar 0:cc2af8aa4091 83 writereg(RF22_REG_42_CHECK_HEADER0,0xde);
shekhar 0:cc2af8aa4091 84
shekhar 0:cc2af8aa4091 85 //RSSI threshold for clear channel indicator
shekhar 0:cc2af8aa4091 86 writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
shekhar 0:cc2af8aa4091 87
shekhar 0:cc2af8aa4091 88 writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ??
shekhar 0:cc2af8aa4091 89 writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ??
shekhar 0:cc2af8aa4091 90
shekhar 0:cc2af8aa4091 91 //interrupts
shekhar 0:cc2af8aa4091 92 // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
shekhar 0:cc2af8aa4091 93 // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
shekhar 0:cc2af8aa4091 94
shekhar 0:cc2af8aa4091 95 setFrequency(435.0, 0.05);
shekhar 0:cc2af8aa4091 96
shekhar 0:cc2af8aa4091 97 //return !(statusRead() & RF22_FREQERR);
shekhar 0:cc2af8aa4091 98 if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
shekhar 0:cc2af8aa4091 99 pc.printf("frequency not set properly\n");
shekhar 0:cc2af8aa4091 100 //frequency set
shekhar 0:cc2af8aa4091 101
shekhar 0:cc2af8aa4091 102 //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz
shekhar 0:cc2af8aa4091 103 //setmodemregisters
shekhar 0:cc2af8aa4091 104 //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36
shekhar 0:cc2af8aa4091 105 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335
shekhar 0:cc2af8aa4091 106 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf);
shekhar 0:cc2af8aa4091 107 writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03);
shekhar 0:cc2af8aa4091 108 writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39);
shekhar 0:cc2af8aa4091 109 writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20);
shekhar 0:cc2af8aa4091 110 writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk
shekhar 0:cc2af8aa4091 111 writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc);
shekhar 0:cc2af8aa4091 112 writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00);
shekhar 0:cc2af8aa4091 113 writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B);
shekhar 0:cc2af8aa4091 114 writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C);
shekhar 0:cc2af8aa4091 115 writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11); //not required for fsk (OOK counter value)
shekhar 0:cc2af8aa4091 116 writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A); //??
shekhar 0:cc2af8aa4091 117 writereg(RF22_REG_58,0x80);
shekhar 0:cc2af8aa4091 118 writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
shekhar 0:cc2af8aa4091 119 writereg(RF22_REG_6E_TX_DATA_RATE1,0x01);//TX at 0.123kbps=:6E=0x01; 6F=0x02
shekhar 0:cc2af8aa4091 120 writereg(RF22_REG_6F_TX_DATA_RATE0,0x06);//TX at 1.2kbps: 6E=0x09; 6F=0xd5
shekhar 0:cc2af8aa4091 121 writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
shekhar 0:cc2af8aa4091 122 writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22
shekhar 0:cc2af8aa4091 123 writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50);
shekhar 0:cc2af8aa4091 124 //set tx power
shekhar 0:cc2af8aa4091 125 writereg(RF22_REG_6D_TX_POWER,0x06); //20dbm
shekhar 0:cc2af8aa4091 126 //writereg(RF22_REG_6D_TX_POWER,0x00); //-1dbm
shekhar 0:cc2af8aa4091 127 writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length
shekhar 0:cc2af8aa4091 128 }
shekhar 0:cc2af8aa4091 129 int main()
shekhar 0:cc2af8aa4091 130 {
shekhar 0:cc2af8aa4091 131 wait(1); // wait for POR to complete //change the timing later
shekhar 0:cc2af8aa4091 132 cs=1; // chip must be deselected
shekhar 0:cc2af8aa4091 133 wait(1); //change the time later
shekhar 0:cc2af8aa4091 134 spi.format(8,0);
shekhar 0:cc2af8aa4091 135 spi.frequency(10000000); //10MHz SCLK
shekhar 0:cc2af8aa4091 136 if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n");
shekhar 0:cc2af8aa4091 137 else pc.printf("error in spi connection\n");
shekhar 0:cc2af8aa4091 138
shekhar 0:cc2af8aa4091 139 init();
shekhar 0:cc2af8aa4091 140
shekhar 0:cc2af8aa4091 141
shekhar 0:cc2af8aa4091 142 //init complete
shekhar 0:cc2af8aa4091 143 pc.printf("init complete.....press t to send\n");
shekhar 0:cc2af8aa4091 144
shekhar 0:cc2af8aa4091 145
shekhar 0:cc2af8aa4091 146 //********
shekhar 0:cc2af8aa4091 147
shekhar 0:cc2af8aa4091 148 while(pc.getc()=='t') //1
shekhar 0:cc2af8aa4091 149 {
shekhar 0:cc2af8aa4091 150 /*uint8_t data[] = "Hello World!";
shekhar 0:cc2af8aa4091 151 pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/
shekhar 0:cc2af8aa4091 152
shekhar 0:cc2af8aa4091 153 uint8_t data[255]; //starts from 0,1,2,3,4!!!;
shekhar 0:cc2af8aa4091 154 int i = 0; //for loops
shekhar 0:cc2af8aa4091 155 int u = 0; //universal count for hk array
shekhar 0:cc2af8aa4091 156 int bar = 0;
shekhar 0:cc2af8aa4091 157 //filling hk data
shekhar 0:cc2af8aa4091 158 /*for(int n=0; n<1; n++)
shekhar 0:cc2af8aa4091 159 data[n] = 0xAA;
shekhar 0:cc2af8aa4091 160 data[1] = 0x3A; */
shekhar 0:cc2af8aa4091 161 //for(int n=0; n<15; n++)
shekhar 0:cc2af8aa4091 162 /*data[0] = 0xAB;
shekhar 0:cc2af8aa4091 163 data[1] = 0x8A;
shekhar 0:cc2af8aa4091 164 data[2] = 0xE2;
shekhar 0:cc2af8aa4091 165 data[3] = 0xBB;
shekhar 0:cc2af8aa4091 166 data[4] = 0xB8;
shekhar 0:cc2af8aa4091 167 data[5] = 0xA2;
shekhar 0:cc2af8aa4091 168 data[6] = 0x8E;
shekhar 0:cc2af8aa4091 169 data[7] = 0x88;
shekhar 0:cc2af8aa4091 170 data[8] = 0x99;
shekhar 0:cc2af8aa4091 171 data[9] = 0xAA;
shekhar 0:cc2af8aa4091 172 data[10] = 0xAA;
shekhar 0:cc2af8aa4091 173 data[11] = 0xAA;
shekhar 0:cc2af8aa4091 174 data[12] = 0xDD;
shekhar 0:cc2af8aa4091 175 data[13] = 0xEE;
shekhar 0:cc2af8aa4091 176 data[14] = 0x00;
shekhar 0:cc2af8aa4091 177 */
shekhar 0:cc2af8aa4091 178 /*for(int n=50; n<60; n++)
shekhar 0:cc2af8aa4091 179 data[n] = n; */
shekhar 0:cc2af8aa4091 180 //for(int n=60; n<120; n++)
shekhar 0:cc2af8aa4091 181 // data[n] = 0x11;
shekhar 0:cc2af8aa4091 182 /*for(int n=75; n<97; n++)
shekhar 0:cc2af8aa4091 183 data[n] = 0xBC;
shekhar 0:cc2af8aa4091 184 for(int n=97; n<110; n++)
shekhar 0:cc2af8aa4091 185 data[n] = 0xEC;
shekhar 0:cc2af8aa4091 186 for(int n=110; n<120; n++)
shekhar 0:cc2af8aa4091 187 data[n] = 0xFC; */
shekhar 0:cc2af8aa4091 188 for(int n=0; n<255; n++)
shekhar 0:cc2af8aa4091 189 data[n] = 0xAB;
shekhar 0:cc2af8aa4091 190 /*uint8_t stuff[] = "IITMSAT IITMSAT";
shekhar 0:cc2af8aa4091 191 for(int i = 0 ; i < 15 ; ++i){
shekhar 0:cc2af8aa4091 192 data[i] = stuff[i];
shekhar 0:cc2af8aa4091 193 }*/
shekhar 0:cc2af8aa4091 194
shekhar 0:cc2af8aa4091 195 //for(int n=150; n<TX_DATA; n++)
shekhar 0:cc2af8aa4091 196 // data[n] = 0x11;
shekhar 0:cc2af8aa4091 197 //tx settings begin
shekhar 0:cc2af8aa4091 198
shekhar 0:cc2af8aa4091 199 //setModeIdle();
shekhar 0:cc2af8aa4091 200 writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode
shekhar 0:cc2af8aa4091 201 //fillTxBuf(data, len);
shekhar 0:cc2af8aa4091 202 clearTxBuf();
shekhar 0:cc2af8aa4091 203 //Filling Data into FIFO for the first time
shekhar 0:cc2af8aa4091 204 /*cs = 0;
shekhar 0:cc2af8aa4091 205 spi.write(0xFF); //fifo write access
shekhar 0:cc2af8aa4091 206 for(i=0; i<datalen; i++){
shekhar 0:cc2af8aa4091 207 spi.write(data[i]);
shekhar 0:cc2af8aa4091 208 pc.printf("0x%X \n",data[u+i]);
shekhar 0:cc2af8aa4091 209 }
shekhar 0:cc2af8aa4091 210 u=i;//check its 64
shekhar 0:cc2af8aa4091 211 cs = 1; */
shekhar 0:cc2af8aa4091 212
shekhar 0:cc2af8aa4091 213 //Set to Tx mode
shekhar 0:cc2af8aa4091 214 writereg(RF22_REG_07_OPERATING_MODE1,0x09);
shekhar 0:cc2af8aa4091 215
shekhar 0:cc2af8aa4091 216 //Check for fifoempty Thresh
shekhar 0:cc2af8aa4091 217 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20);
shekhar 0:cc2af8aa4091 218
shekhar 0:cc2af8aa4091 219 while(u!=TX_DATA) {
shekhar 0:cc2af8aa4091 220 if((TX_DATA - u) >= TIMES)
shekhar 0:cc2af8aa4091 221 bar = TIMES;
shekhar 0:cc2af8aa4091 222 else
shekhar 0:cc2af8aa4091 223 bar = (TX_DATA - u);
shekhar 0:cc2af8aa4091 224
shekhar 0:cc2af8aa4091 225 //writing again
shekhar 0:cc2af8aa4091 226 cs = 0;
shekhar 0:cc2af8aa4091 227 spi.write(0xFF); //FIFO write access
shekhar 0:cc2af8aa4091 228 for(i=0; i<bar; i++,u++)
shekhar 0:cc2af8aa4091 229 {
shekhar 0:cc2af8aa4091 230 //spi.write(data[u + i]);
shekhar 0:cc2af8aa4091 231 spi.write(data[i]);
shekhar 0:cc2af8aa4091 232 pc.printf("0x%X 0x%X \r\n",data[i],u);
shekhar 0:cc2af8aa4091 233 }
shekhar 0:cc2af8aa4091 234 //u = u + i;
shekhar 0:cc2af8aa4091 235 cs = 1;
shekhar 0:cc2af8aa4091 236 //Check for fifoThresh
shekhar 0:cc2af8aa4091 237 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20);
shekhar 0:cc2af8aa4091 238 }
shekhar 0:cc2af8aa4091 239 //rf22.waitPacketSent();
shekhar 0:cc2af8aa4091 240 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n");
shekhar 0:cc2af8aa4091 241 pc.printf(" packet sent ");
shekhar 0:cc2af8aa4091 242
shekhar 0:cc2af8aa4091 243 }
shekhar 0:cc2af8aa4091 244 }