Diff: targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c

Revision:

216:577900467c9e

Parent:

200:a6b296b34609

Child:

227:7bd0639b8911

diff -r 83cf97a28428 -r 577900467c9e targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c	Tue May 27 08:30:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c	Tue May 27 10:00:08 2014 +0100
@@ -125,6 +125,11 @@
     obj->cpha = SPI_CPHA_1Edge;
     obj->br_presc = SPI_BaudRatePrescaler_256;
 
+    obj->pin_miso = miso;
+    obj->pin_mosi = mosi;
+    obj->pin_sclk = sclk;
+    obj->pin_ssel = ssel;
+
     if (ssel == NC) { // Master
         obj->mode = SPI_Mode_Master;
         obj->nss = SPI_NSS_Soft;
@@ -138,8 +143,23 @@
 }
 
 void spi_free(spi_t *obj) {
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    SPI_I2S_DeInit(spi);
+    // Reset SPI and disable clock
+    if (obj->spi == SPI_2) {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+    if (obj->spi == SPI_3) {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, DISABLE);
+    }
+
+    // Configure GPIOs
+    pin_function(obj->pin_miso, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+    pin_function(obj->pin_mosi, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+    pin_function(obj->pin_sclk, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
+    pin_function(obj->pin_ssel, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
 }
 
 void spi_format(spi_t *obj, int bits, int mode, int slave) {