shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_fsmc.h@52:a51c77007319, 2013-12-02 (annotated)

Committer:
mbed_official
Date:
Mon Dec 02 11:30:05 2013 +0000
Revision:
52:a51c77007319
Child:
70:c1fbde68b492
Synchronized with git revision 49df530ae72ce97ccc773d1f2c13b38e868e6abd



Full URL: https://github.com/mbedmicro/mbed/commit/49df530ae72ce97ccc773d1f2c13b38e868e6abd/



Add STMicroelectronics NUCLEO_F103RB target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 52:a51c77007319 1 /**
mbed_official 52:a51c77007319 2 ******************************************************************************
mbed_official 52:a51c77007319 3 * @file stm32f10x_fsmc.h
mbed_official 52:a51c77007319 4 * @author MCD Application Team
mbed_official 52:a51c77007319 5 * @version V3.5.0
mbed_official 52:a51c77007319 6 * @date 11-March-2011
mbed_official 52:a51c77007319 7 * @brief This file contains all the functions prototypes for the FSMC firmware
mbed_official 52:a51c77007319 8 * library.
mbed_official 52:a51c77007319 9 ******************************************************************************
mbed_official 52:a51c77007319 10 * @attention
mbed_official 52:a51c77007319 11 *
mbed_official 52:a51c77007319 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
mbed_official 52:a51c77007319 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
mbed_official 52:a51c77007319 14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
mbed_official 52:a51c77007319 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
mbed_official 52:a51c77007319 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
mbed_official 52:a51c77007319 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
mbed_official 52:a51c77007319 18 *
mbed_official 52:a51c77007319 19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
mbed_official 52:a51c77007319 20 ******************************************************************************
mbed_official 52:a51c77007319 21 */
mbed_official 52:a51c77007319 22
mbed_official 52:a51c77007319 23 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 52:a51c77007319 24 #ifndef __STM32F10x_FSMC_H
mbed_official 52:a51c77007319 25 #define __STM32F10x_FSMC_H
mbed_official 52:a51c77007319 26
mbed_official 52:a51c77007319 27 #ifdef __cplusplus
mbed_official 52:a51c77007319 28 extern "C" {
mbed_official 52:a51c77007319 29 #endif
mbed_official 52:a51c77007319 30
mbed_official 52:a51c77007319 31 /* Includes ------------------------------------------------------------------*/
mbed_official 52:a51c77007319 32 #include "stm32f10x.h"
mbed_official 52:a51c77007319 33
mbed_official 52:a51c77007319 34 /** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official 52:a51c77007319 35 * @{
mbed_official 52:a51c77007319 36 */
mbed_official 52:a51c77007319 37
mbed_official 52:a51c77007319 38 /** @addtogroup FSMC
mbed_official 52:a51c77007319 39 * @{
mbed_official 52:a51c77007319 40 */
mbed_official 52:a51c77007319 41
mbed_official 52:a51c77007319 42 /** @defgroup FSMC_Exported_Types
mbed_official 52:a51c77007319 43 * @{
mbed_official 52:a51c77007319 44 */
mbed_official 52:a51c77007319 45
mbed_official 52:a51c77007319 46 /**
mbed_official 52:a51c77007319 47 * @brief Timing parameters For NOR/SRAM Banks
mbed_official 52:a51c77007319 48 */
mbed_official 52:a51c77007319 49
mbed_official 52:a51c77007319 50 typedef struct
mbed_official 52:a51c77007319 51 {
mbed_official 52:a51c77007319 52 uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 52:a51c77007319 53 the duration of the address setup time.
mbed_official 52:a51c77007319 54 This parameter can be a value between 0 and 0xF.
mbed_official 52:a51c77007319 55 @note: It is not used with synchronous NOR Flash memories. */
mbed_official 52:a51c77007319 56
mbed_official 52:a51c77007319 57 uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 52:a51c77007319 58 the duration of the address hold time.
mbed_official 52:a51c77007319 59 This parameter can be a value between 0 and 0xF.
mbed_official 52:a51c77007319 60 @note: It is not used with synchronous NOR Flash memories.*/
mbed_official 52:a51c77007319 61
mbed_official 52:a51c77007319 62 uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 52:a51c77007319 63 the duration of the data setup time.
mbed_official 52:a51c77007319 64 This parameter can be a value between 0 and 0xFF.
mbed_official 52:a51c77007319 65 @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
mbed_official 52:a51c77007319 66
mbed_official 52:a51c77007319 67 uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official 52:a51c77007319 68 the duration of the bus turnaround.
mbed_official 52:a51c77007319 69 This parameter can be a value between 0 and 0xF.
mbed_official 52:a51c77007319 70 @note: It is only used for multiplexed NOR Flash memories. */
mbed_official 52:a51c77007319 71
mbed_official 52:a51c77007319 72 uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
mbed_official 52:a51c77007319 73 This parameter can be a value between 1 and 0xF.
mbed_official 52:a51c77007319 74 @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
mbed_official 52:a51c77007319 75
mbed_official 52:a51c77007319 76 uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official 52:a51c77007319 77 to the memory before getting the first data.
mbed_official 52:a51c77007319 78 The value of this parameter depends on the memory type as shown below:
mbed_official 52:a51c77007319 79 - It must be set to 0 in case of a CRAM
mbed_official 52:a51c77007319 80 - It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official 52:a51c77007319 81 - It may assume a value between 0 and 0xF in NOR Flash memories
mbed_official 52:a51c77007319 82 with synchronous burst mode enable */
mbed_official 52:a51c77007319 83
mbed_official 52:a51c77007319 84 uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official 52:a51c77007319 85 This parameter can be a value of @ref FSMC_Access_Mode */
mbed_official 52:a51c77007319 86 }FSMC_NORSRAMTimingInitTypeDef;
mbed_official 52:a51c77007319 87
mbed_official 52:a51c77007319 88 /**
mbed_official 52:a51c77007319 89 * @brief FSMC NOR/SRAM Init structure definition
mbed_official 52:a51c77007319 90 */
mbed_official 52:a51c77007319 91
mbed_official 52:a51c77007319 92 typedef struct
mbed_official 52:a51c77007319 93 {
mbed_official 52:a51c77007319 94 uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
mbed_official 52:a51c77007319 95 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
mbed_official 52:a51c77007319 96
mbed_official 52:a51c77007319 97 uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official 52:a51c77007319 98 multiplexed on the databus or not.
mbed_official 52:a51c77007319 99 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
mbed_official 52:a51c77007319 100
mbed_official 52:a51c77007319 101 uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
mbed_official 52:a51c77007319 102 the corresponding memory bank.
mbed_official 52:a51c77007319 103 This parameter can be a value of @ref FSMC_Memory_Type */
mbed_official 52:a51c77007319 104
mbed_official 52:a51c77007319 105 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official 52:a51c77007319 106 This parameter can be a value of @ref FSMC_Data_Width */
mbed_official 52:a51c77007319 107
mbed_official 52:a51c77007319 108 uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official 52:a51c77007319 109 valid only with synchronous burst Flash memories.
mbed_official 52:a51c77007319 110 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
mbed_official 52:a51c77007319 111
mbed_official 52:a51c77007319 112 uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official 52:a51c77007319 113 valid only with asynchronous Flash memories.
mbed_official 52:a51c77007319 114 This parameter can be a value of @ref FSMC_AsynchronousWait */
mbed_official 52:a51c77007319 115
mbed_official 52:a51c77007319 116 uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official 52:a51c77007319 117 the Flash memory in burst mode.
mbed_official 52:a51c77007319 118 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
mbed_official 52:a51c77007319 119
mbed_official 52:a51c77007319 120 uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official 52:a51c77007319 121 memory, valid only when accessing Flash memories in burst mode.
mbed_official 52:a51c77007319 122 This parameter can be a value of @ref FSMC_Wrap_Mode */
mbed_official 52:a51c77007319 123
mbed_official 52:a51c77007319 124 uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official 52:a51c77007319 125 clock cycle before the wait state or during the wait state,
mbed_official 52:a51c77007319 126 valid only when accessing memories in burst mode.
mbed_official 52:a51c77007319 127 This parameter can be a value of @ref FSMC_Wait_Timing */
mbed_official 52:a51c77007319 128
mbed_official 52:a51c77007319 129 uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
mbed_official 52:a51c77007319 130 This parameter can be a value of @ref FSMC_Write_Operation */
mbed_official 52:a51c77007319 131
mbed_official 52:a51c77007319 132 uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
mbed_official 52:a51c77007319 133 signal, valid for Flash memory access in burst mode.
mbed_official 52:a51c77007319 134 This parameter can be a value of @ref FSMC_Wait_Signal */
mbed_official 52:a51c77007319 135
mbed_official 52:a51c77007319 136 uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official 52:a51c77007319 137 This parameter can be a value of @ref FSMC_Extended_Mode */
mbed_official 52:a51c77007319 138
mbed_official 52:a51c77007319 139 uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official 52:a51c77007319 140 This parameter can be a value of @ref FSMC_Write_Burst */
mbed_official 52:a51c77007319 141
mbed_official 52:a51c77007319 142 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
mbed_official 52:a51c77007319 143
mbed_official 52:a51c77007319 144 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
mbed_official 52:a51c77007319 145 }FSMC_NORSRAMInitTypeDef;
mbed_official 52:a51c77007319 146
mbed_official 52:a51c77007319 147 /**
mbed_official 52:a51c77007319 148 * @brief Timing parameters For FSMC NAND and PCCARD Banks
mbed_official 52:a51c77007319 149 */
mbed_official 52:a51c77007319 150
mbed_official 52:a51c77007319 151 typedef struct
mbed_official 52:a51c77007319 152 {
mbed_official 52:a51c77007319 153 uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official 52:a51c77007319 154 the command assertion for NAND-Flash read or write access
mbed_official 52:a51c77007319 155 to common/Attribute or I/O memory space (depending on
mbed_official 52:a51c77007319 156 the memory space timing to be configured).
mbed_official 52:a51c77007319 157 This parameter can be a value between 0 and 0xFF.*/
mbed_official 52:a51c77007319 158
mbed_official 52:a51c77007319 159 uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official 52:a51c77007319 160 command for NAND-Flash read or write access to
mbed_official 52:a51c77007319 161 common/Attribute or I/O memory space (depending on the
mbed_official 52:a51c77007319 162 memory space timing to be configured).
mbed_official 52:a51c77007319 163 This parameter can be a number between 0x00 and 0xFF */
mbed_official 52:a51c77007319 164
mbed_official 52:a51c77007319 165 uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official 52:a51c77007319 166 (and data for write access) after the command deassertion
mbed_official 52:a51c77007319 167 for NAND-Flash read or write access to common/Attribute
mbed_official 52:a51c77007319 168 or I/O memory space (depending on the memory space timing
mbed_official 52:a51c77007319 169 to be configured).
mbed_official 52:a51c77007319 170 This parameter can be a number between 0x00 and 0xFF */
mbed_official 52:a51c77007319 171
mbed_official 52:a51c77007319 172 uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official 52:a51c77007319 173 databus is kept in HiZ after the start of a NAND-Flash
mbed_official 52:a51c77007319 174 write access to common/Attribute or I/O memory space (depending
mbed_official 52:a51c77007319 175 on the memory space timing to be configured).
mbed_official 52:a51c77007319 176 This parameter can be a number between 0x00 and 0xFF */
mbed_official 52:a51c77007319 177 }FSMC_NAND_PCCARDTimingInitTypeDef;
mbed_official 52:a51c77007319 178
mbed_official 52:a51c77007319 179 /**
mbed_official 52:a51c77007319 180 * @brief FSMC NAND Init structure definition
mbed_official 52:a51c77007319 181 */
mbed_official 52:a51c77007319 182
mbed_official 52:a51c77007319 183 typedef struct
mbed_official 52:a51c77007319 184 {
mbed_official 52:a51c77007319 185 uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
mbed_official 52:a51c77007319 186 This parameter can be a value of @ref FSMC_NAND_Bank */
mbed_official 52:a51c77007319 187
mbed_official 52:a51c77007319 188 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
mbed_official 52:a51c77007319 189 This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official 52:a51c77007319 190
mbed_official 52:a51c77007319 191 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official 52:a51c77007319 192 This parameter can be any value of @ref FSMC_Data_Width */
mbed_official 52:a51c77007319 193
mbed_official 52:a51c77007319 194 uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
mbed_official 52:a51c77007319 195 This parameter can be any value of @ref FSMC_ECC */
mbed_official 52:a51c77007319 196
mbed_official 52:a51c77007319 197 uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official 52:a51c77007319 198 This parameter can be any value of @ref FSMC_ECC_Page_Size */
mbed_official 52:a51c77007319 199
mbed_official 52:a51c77007319 200 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 52:a51c77007319 201 delay between CLE low and RE low.
mbed_official 52:a51c77007319 202 This parameter can be a value between 0 and 0xFF. */
mbed_official 52:a51c77007319 203
mbed_official 52:a51c77007319 204 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 52:a51c77007319 205 delay between ALE low and RE low.
mbed_official 52:a51c77007319 206 This parameter can be a number between 0x0 and 0xFF */
mbed_official 52:a51c77007319 207
mbed_official 52:a51c77007319 208 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
mbed_official 52:a51c77007319 209
mbed_official 52:a51c77007319 210 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
mbed_official 52:a51c77007319 211 }FSMC_NANDInitTypeDef;
mbed_official 52:a51c77007319 212
mbed_official 52:a51c77007319 213 /**
mbed_official 52:a51c77007319 214 * @brief FSMC PCCARD Init structure definition
mbed_official 52:a51c77007319 215 */
mbed_official 52:a51c77007319 216
mbed_official 52:a51c77007319 217 typedef struct
mbed_official 52:a51c77007319 218 {
mbed_official 52:a51c77007319 219 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
mbed_official 52:a51c77007319 220 This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official 52:a51c77007319 221
mbed_official 52:a51c77007319 222 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 52:a51c77007319 223 delay between CLE low and RE low.
mbed_official 52:a51c77007319 224 This parameter can be a value between 0 and 0xFF. */
mbed_official 52:a51c77007319 225
mbed_official 52:a51c77007319 226 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 52:a51c77007319 227 delay between ALE low and RE low.
mbed_official 52:a51c77007319 228 This parameter can be a number between 0x0 and 0xFF */
mbed_official 52:a51c77007319 229
mbed_official 52:a51c77007319 230
mbed_official 52:a51c77007319 231 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
mbed_official 52:a51c77007319 232
mbed_official 52:a51c77007319 233 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
mbed_official 52:a51c77007319 234
mbed_official 52:a51c77007319 235 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
mbed_official 52:a51c77007319 236 }FSMC_PCCARDInitTypeDef;
mbed_official 52:a51c77007319 237
mbed_official 52:a51c77007319 238 /**
mbed_official 52:a51c77007319 239 * @}
mbed_official 52:a51c77007319 240 */
mbed_official 52:a51c77007319 241
mbed_official 52:a51c77007319 242 /** @defgroup FSMC_Exported_Constants
mbed_official 52:a51c77007319 243 * @{
mbed_official 52:a51c77007319 244 */
mbed_official 52:a51c77007319 245
mbed_official 52:a51c77007319 246 /** @defgroup FSMC_NORSRAM_Bank
mbed_official 52:a51c77007319 247 * @{
mbed_official 52:a51c77007319 248 */
mbed_official 52:a51c77007319 249 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 250 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
mbed_official 52:a51c77007319 251 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
mbed_official 52:a51c77007319 252 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
mbed_official 52:a51c77007319 253 /**
mbed_official 52:a51c77007319 254 * @}
mbed_official 52:a51c77007319 255 */
mbed_official 52:a51c77007319 256
mbed_official 52:a51c77007319 257 /** @defgroup FSMC_NAND_Bank
mbed_official 52:a51c77007319 258 * @{
mbed_official 52:a51c77007319 259 */
mbed_official 52:a51c77007319 260 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
mbed_official 52:a51c77007319 261 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
mbed_official 52:a51c77007319 262 /**
mbed_official 52:a51c77007319 263 * @}
mbed_official 52:a51c77007319 264 */
mbed_official 52:a51c77007319 265
mbed_official 52:a51c77007319 266 /** @defgroup FSMC_PCCARD_Bank
mbed_official 52:a51c77007319 267 * @{
mbed_official 52:a51c77007319 268 */
mbed_official 52:a51c77007319 269 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
mbed_official 52:a51c77007319 270 /**
mbed_official 52:a51c77007319 271 * @}
mbed_official 52:a51c77007319 272 */
mbed_official 52:a51c77007319 273
mbed_official 52:a51c77007319 274 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
mbed_official 52:a51c77007319 275 ((BANK) == FSMC_Bank1_NORSRAM2) || \
mbed_official 52:a51c77007319 276 ((BANK) == FSMC_Bank1_NORSRAM3) || \
mbed_official 52:a51c77007319 277 ((BANK) == FSMC_Bank1_NORSRAM4))
mbed_official 52:a51c77007319 278
mbed_official 52:a51c77007319 279 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
mbed_official 52:a51c77007319 280 ((BANK) == FSMC_Bank3_NAND))
mbed_official 52:a51c77007319 281
mbed_official 52:a51c77007319 282 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
mbed_official 52:a51c77007319 283 ((BANK) == FSMC_Bank3_NAND) || \
mbed_official 52:a51c77007319 284 ((BANK) == FSMC_Bank4_PCCARD))
mbed_official 52:a51c77007319 285
mbed_official 52:a51c77007319 286 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
mbed_official 52:a51c77007319 287 ((BANK) == FSMC_Bank3_NAND) || \
mbed_official 52:a51c77007319 288 ((BANK) == FSMC_Bank4_PCCARD))
mbed_official 52:a51c77007319 289
mbed_official 52:a51c77007319 290 /** @defgroup NOR_SRAM_Controller
mbed_official 52:a51c77007319 291 * @{
mbed_official 52:a51c77007319 292 */
mbed_official 52:a51c77007319 293
mbed_official 52:a51c77007319 294 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
mbed_official 52:a51c77007319 295 * @{
mbed_official 52:a51c77007319 296 */
mbed_official 52:a51c77007319 297
mbed_official 52:a51c77007319 298 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 299 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
mbed_official 52:a51c77007319 300 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
mbed_official 52:a51c77007319 301 ((MUX) == FSMC_DataAddressMux_Enable))
mbed_official 52:a51c77007319 302
mbed_official 52:a51c77007319 303 /**
mbed_official 52:a51c77007319 304 * @}
mbed_official 52:a51c77007319 305 */
mbed_official 52:a51c77007319 306
mbed_official 52:a51c77007319 307 /** @defgroup FSMC_Memory_Type
mbed_official 52:a51c77007319 308 * @{
mbed_official 52:a51c77007319 309 */
mbed_official 52:a51c77007319 310
mbed_official 52:a51c77007319 311 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 312 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
mbed_official 52:a51c77007319 313 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
mbed_official 52:a51c77007319 314 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
mbed_official 52:a51c77007319 315 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
mbed_official 52:a51c77007319 316 ((MEMORY) == FSMC_MemoryType_NOR))
mbed_official 52:a51c77007319 317
mbed_official 52:a51c77007319 318 /**
mbed_official 52:a51c77007319 319 * @}
mbed_official 52:a51c77007319 320 */
mbed_official 52:a51c77007319 321
mbed_official 52:a51c77007319 322 /** @defgroup FSMC_Data_Width
mbed_official 52:a51c77007319 323 * @{
mbed_official 52:a51c77007319 324 */
mbed_official 52:a51c77007319 325
mbed_official 52:a51c77007319 326 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 327 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
mbed_official 52:a51c77007319 328 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
mbed_official 52:a51c77007319 329 ((WIDTH) == FSMC_MemoryDataWidth_16b))
mbed_official 52:a51c77007319 330
mbed_official 52:a51c77007319 331 /**
mbed_official 52:a51c77007319 332 * @}
mbed_official 52:a51c77007319 333 */
mbed_official 52:a51c77007319 334
mbed_official 52:a51c77007319 335 /** @defgroup FSMC_Burst_Access_Mode
mbed_official 52:a51c77007319 336 * @{
mbed_official 52:a51c77007319 337 */
mbed_official 52:a51c77007319 338
mbed_official 52:a51c77007319 339 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 340 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
mbed_official 52:a51c77007319 341 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
mbed_official 52:a51c77007319 342 ((STATE) == FSMC_BurstAccessMode_Enable))
mbed_official 52:a51c77007319 343 /**
mbed_official 52:a51c77007319 344 * @}
mbed_official 52:a51c77007319 345 */
mbed_official 52:a51c77007319 346
mbed_official 52:a51c77007319 347 /** @defgroup FSMC_AsynchronousWait
mbed_official 52:a51c77007319 348 * @{
mbed_official 52:a51c77007319 349 */
mbed_official 52:a51c77007319 350 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 351 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
mbed_official 52:a51c77007319 352 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
mbed_official 52:a51c77007319 353 ((STATE) == FSMC_AsynchronousWait_Enable))
mbed_official 52:a51c77007319 354
mbed_official 52:a51c77007319 355 /**
mbed_official 52:a51c77007319 356 * @}
mbed_official 52:a51c77007319 357 */
mbed_official 52:a51c77007319 358
mbed_official 52:a51c77007319 359 /** @defgroup FSMC_Wait_Signal_Polarity
mbed_official 52:a51c77007319 360 * @{
mbed_official 52:a51c77007319 361 */
mbed_official 52:a51c77007319 362
mbed_official 52:a51c77007319 363 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 364 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
mbed_official 52:a51c77007319 365 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
mbed_official 52:a51c77007319 366 ((POLARITY) == FSMC_WaitSignalPolarity_High))
mbed_official 52:a51c77007319 367
mbed_official 52:a51c77007319 368 /**
mbed_official 52:a51c77007319 369 * @}
mbed_official 52:a51c77007319 370 */
mbed_official 52:a51c77007319 371
mbed_official 52:a51c77007319 372 /** @defgroup FSMC_Wrap_Mode
mbed_official 52:a51c77007319 373 * @{
mbed_official 52:a51c77007319 374 */
mbed_official 52:a51c77007319 375
mbed_official 52:a51c77007319 376 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 377 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
mbed_official 52:a51c77007319 378 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
mbed_official 52:a51c77007319 379 ((MODE) == FSMC_WrapMode_Enable))
mbed_official 52:a51c77007319 380
mbed_official 52:a51c77007319 381 /**
mbed_official 52:a51c77007319 382 * @}
mbed_official 52:a51c77007319 383 */
mbed_official 52:a51c77007319 384
mbed_official 52:a51c77007319 385 /** @defgroup FSMC_Wait_Timing
mbed_official 52:a51c77007319 386 * @{
mbed_official 52:a51c77007319 387 */
mbed_official 52:a51c77007319 388
mbed_official 52:a51c77007319 389 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 390 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
mbed_official 52:a51c77007319 391 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
mbed_official 52:a51c77007319 392 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
mbed_official 52:a51c77007319 393
mbed_official 52:a51c77007319 394 /**
mbed_official 52:a51c77007319 395 * @}
mbed_official 52:a51c77007319 396 */
mbed_official 52:a51c77007319 397
mbed_official 52:a51c77007319 398 /** @defgroup FSMC_Write_Operation
mbed_official 52:a51c77007319 399 * @{
mbed_official 52:a51c77007319 400 */
mbed_official 52:a51c77007319 401
mbed_official 52:a51c77007319 402 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 403 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
mbed_official 52:a51c77007319 404 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
mbed_official 52:a51c77007319 405 ((OPERATION) == FSMC_WriteOperation_Enable))
mbed_official 52:a51c77007319 406
mbed_official 52:a51c77007319 407 /**
mbed_official 52:a51c77007319 408 * @}
mbed_official 52:a51c77007319 409 */
mbed_official 52:a51c77007319 410
mbed_official 52:a51c77007319 411 /** @defgroup FSMC_Wait_Signal
mbed_official 52:a51c77007319 412 * @{
mbed_official 52:a51c77007319 413 */
mbed_official 52:a51c77007319 414
mbed_official 52:a51c77007319 415 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 416 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
mbed_official 52:a51c77007319 417 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
mbed_official 52:a51c77007319 418 ((SIGNAL) == FSMC_WaitSignal_Enable))
mbed_official 52:a51c77007319 419 /**
mbed_official 52:a51c77007319 420 * @}
mbed_official 52:a51c77007319 421 */
mbed_official 52:a51c77007319 422
mbed_official 52:a51c77007319 423 /** @defgroup FSMC_Extended_Mode
mbed_official 52:a51c77007319 424 * @{
mbed_official 52:a51c77007319 425 */
mbed_official 52:a51c77007319 426
mbed_official 52:a51c77007319 427 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 428 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
mbed_official 52:a51c77007319 429
mbed_official 52:a51c77007319 430 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
mbed_official 52:a51c77007319 431 ((MODE) == FSMC_ExtendedMode_Enable))
mbed_official 52:a51c77007319 432
mbed_official 52:a51c77007319 433 /**
mbed_official 52:a51c77007319 434 * @}
mbed_official 52:a51c77007319 435 */
mbed_official 52:a51c77007319 436
mbed_official 52:a51c77007319 437 /** @defgroup FSMC_Write_Burst
mbed_official 52:a51c77007319 438 * @{
mbed_official 52:a51c77007319 439 */
mbed_official 52:a51c77007319 440
mbed_official 52:a51c77007319 441 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 442 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
mbed_official 52:a51c77007319 443 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
mbed_official 52:a51c77007319 444 ((BURST) == FSMC_WriteBurst_Enable))
mbed_official 52:a51c77007319 445 /**
mbed_official 52:a51c77007319 446 * @}
mbed_official 52:a51c77007319 447 */
mbed_official 52:a51c77007319 448
mbed_official 52:a51c77007319 449 /** @defgroup FSMC_Address_Setup_Time
mbed_official 52:a51c77007319 450 * @{
mbed_official 52:a51c77007319 451 */
mbed_official 52:a51c77007319 452
mbed_official 52:a51c77007319 453 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
mbed_official 52:a51c77007319 454
mbed_official 52:a51c77007319 455 /**
mbed_official 52:a51c77007319 456 * @}
mbed_official 52:a51c77007319 457 */
mbed_official 52:a51c77007319 458
mbed_official 52:a51c77007319 459 /** @defgroup FSMC_Address_Hold_Time
mbed_official 52:a51c77007319 460 * @{
mbed_official 52:a51c77007319 461 */
mbed_official 52:a51c77007319 462
mbed_official 52:a51c77007319 463 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
mbed_official 52:a51c77007319 464
mbed_official 52:a51c77007319 465 /**
mbed_official 52:a51c77007319 466 * @}
mbed_official 52:a51c77007319 467 */
mbed_official 52:a51c77007319 468
mbed_official 52:a51c77007319 469 /** @defgroup FSMC_Data_Setup_Time
mbed_official 52:a51c77007319 470 * @{
mbed_official 52:a51c77007319 471 */
mbed_official 52:a51c77007319 472
mbed_official 52:a51c77007319 473 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
mbed_official 52:a51c77007319 474
mbed_official 52:a51c77007319 475 /**
mbed_official 52:a51c77007319 476 * @}
mbed_official 52:a51c77007319 477 */
mbed_official 52:a51c77007319 478
mbed_official 52:a51c77007319 479 /** @defgroup FSMC_Bus_Turn_around_Duration
mbed_official 52:a51c77007319 480 * @{
mbed_official 52:a51c77007319 481 */
mbed_official 52:a51c77007319 482
mbed_official 52:a51c77007319 483 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
mbed_official 52:a51c77007319 484
mbed_official 52:a51c77007319 485 /**
mbed_official 52:a51c77007319 486 * @}
mbed_official 52:a51c77007319 487 */
mbed_official 52:a51c77007319 488
mbed_official 52:a51c77007319 489 /** @defgroup FSMC_CLK_Division
mbed_official 52:a51c77007319 490 * @{
mbed_official 52:a51c77007319 491 */
mbed_official 52:a51c77007319 492
mbed_official 52:a51c77007319 493 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
mbed_official 52:a51c77007319 494
mbed_official 52:a51c77007319 495 /**
mbed_official 52:a51c77007319 496 * @}
mbed_official 52:a51c77007319 497 */
mbed_official 52:a51c77007319 498
mbed_official 52:a51c77007319 499 /** @defgroup FSMC_Data_Latency
mbed_official 52:a51c77007319 500 * @{
mbed_official 52:a51c77007319 501 */
mbed_official 52:a51c77007319 502
mbed_official 52:a51c77007319 503 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
mbed_official 52:a51c77007319 504
mbed_official 52:a51c77007319 505 /**
mbed_official 52:a51c77007319 506 * @}
mbed_official 52:a51c77007319 507 */
mbed_official 52:a51c77007319 508
mbed_official 52:a51c77007319 509 /** @defgroup FSMC_Access_Mode
mbed_official 52:a51c77007319 510 * @{
mbed_official 52:a51c77007319 511 */
mbed_official 52:a51c77007319 512
mbed_official 52:a51c77007319 513 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 514 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
mbed_official 52:a51c77007319 515 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
mbed_official 52:a51c77007319 516 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
mbed_official 52:a51c77007319 517 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
mbed_official 52:a51c77007319 518 ((MODE) == FSMC_AccessMode_B) || \
mbed_official 52:a51c77007319 519 ((MODE) == FSMC_AccessMode_C) || \
mbed_official 52:a51c77007319 520 ((MODE) == FSMC_AccessMode_D))
mbed_official 52:a51c77007319 521
mbed_official 52:a51c77007319 522 /**
mbed_official 52:a51c77007319 523 * @}
mbed_official 52:a51c77007319 524 */
mbed_official 52:a51c77007319 525
mbed_official 52:a51c77007319 526 /**
mbed_official 52:a51c77007319 527 * @}
mbed_official 52:a51c77007319 528 */
mbed_official 52:a51c77007319 529
mbed_official 52:a51c77007319 530 /** @defgroup NAND_PCCARD_Controller
mbed_official 52:a51c77007319 531 * @{
mbed_official 52:a51c77007319 532 */
mbed_official 52:a51c77007319 533
mbed_official 52:a51c77007319 534 /** @defgroup FSMC_Wait_feature
mbed_official 52:a51c77007319 535 * @{
mbed_official 52:a51c77007319 536 */
mbed_official 52:a51c77007319 537
mbed_official 52:a51c77007319 538 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 539 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
mbed_official 52:a51c77007319 540 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
mbed_official 52:a51c77007319 541 ((FEATURE) == FSMC_Waitfeature_Enable))
mbed_official 52:a51c77007319 542
mbed_official 52:a51c77007319 543 /**
mbed_official 52:a51c77007319 544 * @}
mbed_official 52:a51c77007319 545 */
mbed_official 52:a51c77007319 546
mbed_official 52:a51c77007319 547
mbed_official 52:a51c77007319 548 /** @defgroup FSMC_ECC
mbed_official 52:a51c77007319 549 * @{
mbed_official 52:a51c77007319 550 */
mbed_official 52:a51c77007319 551
mbed_official 52:a51c77007319 552 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 553 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
mbed_official 52:a51c77007319 554 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
mbed_official 52:a51c77007319 555 ((STATE) == FSMC_ECC_Enable))
mbed_official 52:a51c77007319 556
mbed_official 52:a51c77007319 557 /**
mbed_official 52:a51c77007319 558 * @}
mbed_official 52:a51c77007319 559 */
mbed_official 52:a51c77007319 560
mbed_official 52:a51c77007319 561 /** @defgroup FSMC_ECC_Page_Size
mbed_official 52:a51c77007319 562 * @{
mbed_official 52:a51c77007319 563 */
mbed_official 52:a51c77007319 564
mbed_official 52:a51c77007319 565 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
mbed_official 52:a51c77007319 566 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
mbed_official 52:a51c77007319 567 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
mbed_official 52:a51c77007319 568 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
mbed_official 52:a51c77007319 569 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
mbed_official 52:a51c77007319 570 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
mbed_official 52:a51c77007319 571 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
mbed_official 52:a51c77007319 572 ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
mbed_official 52:a51c77007319 573 ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
mbed_official 52:a51c77007319 574 ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
mbed_official 52:a51c77007319 575 ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
mbed_official 52:a51c77007319 576 ((SIZE) == FSMC_ECCPageSize_8192Bytes))
mbed_official 52:a51c77007319 577
mbed_official 52:a51c77007319 578 /**
mbed_official 52:a51c77007319 579 * @}
mbed_official 52:a51c77007319 580 */
mbed_official 52:a51c77007319 581
mbed_official 52:a51c77007319 582 /** @defgroup FSMC_TCLR_Setup_Time
mbed_official 52:a51c77007319 583 * @{
mbed_official 52:a51c77007319 584 */
mbed_official 52:a51c77007319 585
mbed_official 52:a51c77007319 586 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 52:a51c77007319 587
mbed_official 52:a51c77007319 588 /**
mbed_official 52:a51c77007319 589 * @}
mbed_official 52:a51c77007319 590 */
mbed_official 52:a51c77007319 591
mbed_official 52:a51c77007319 592 /** @defgroup FSMC_TAR_Setup_Time
mbed_official 52:a51c77007319 593 * @{
mbed_official 52:a51c77007319 594 */
mbed_official 52:a51c77007319 595
mbed_official 52:a51c77007319 596 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 52:a51c77007319 597
mbed_official 52:a51c77007319 598 /**
mbed_official 52:a51c77007319 599 * @}
mbed_official 52:a51c77007319 600 */
mbed_official 52:a51c77007319 601
mbed_official 52:a51c77007319 602 /** @defgroup FSMC_Setup_Time
mbed_official 52:a51c77007319 603 * @{
mbed_official 52:a51c77007319 604 */
mbed_official 52:a51c77007319 605
mbed_official 52:a51c77007319 606 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 52:a51c77007319 607
mbed_official 52:a51c77007319 608 /**
mbed_official 52:a51c77007319 609 * @}
mbed_official 52:a51c77007319 610 */
mbed_official 52:a51c77007319 611
mbed_official 52:a51c77007319 612 /** @defgroup FSMC_Wait_Setup_Time
mbed_official 52:a51c77007319 613 * @{
mbed_official 52:a51c77007319 614 */
mbed_official 52:a51c77007319 615
mbed_official 52:a51c77007319 616 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 52:a51c77007319 617
mbed_official 52:a51c77007319 618 /**
mbed_official 52:a51c77007319 619 * @}
mbed_official 52:a51c77007319 620 */
mbed_official 52:a51c77007319 621
mbed_official 52:a51c77007319 622 /** @defgroup FSMC_Hold_Setup_Time
mbed_official 52:a51c77007319 623 * @{
mbed_official 52:a51c77007319 624 */
mbed_official 52:a51c77007319 625
mbed_official 52:a51c77007319 626 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 52:a51c77007319 627
mbed_official 52:a51c77007319 628 /**
mbed_official 52:a51c77007319 629 * @}
mbed_official 52:a51c77007319 630 */
mbed_official 52:a51c77007319 631
mbed_official 52:a51c77007319 632 /** @defgroup FSMC_HiZ_Setup_Time
mbed_official 52:a51c77007319 633 * @{
mbed_official 52:a51c77007319 634 */
mbed_official 52:a51c77007319 635
mbed_official 52:a51c77007319 636 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 52:a51c77007319 637
mbed_official 52:a51c77007319 638 /**
mbed_official 52:a51c77007319 639 * @}
mbed_official 52:a51c77007319 640 */
mbed_official 52:a51c77007319 641
mbed_official 52:a51c77007319 642 /** @defgroup FSMC_Interrupt_sources
mbed_official 52:a51c77007319 643 * @{
mbed_official 52:a51c77007319 644 */
mbed_official 52:a51c77007319 645
mbed_official 52:a51c77007319 646 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
mbed_official 52:a51c77007319 647 #define FSMC_IT_Level ((uint32_t)0x00000010)
mbed_official 52:a51c77007319 648 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
mbed_official 52:a51c77007319 649 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official 52:a51c77007319 650 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
mbed_official 52:a51c77007319 651 ((IT) == FSMC_IT_Level) || \
mbed_official 52:a51c77007319 652 ((IT) == FSMC_IT_FallingEdge))
mbed_official 52:a51c77007319 653 /**
mbed_official 52:a51c77007319 654 * @}
mbed_official 52:a51c77007319 655 */
mbed_official 52:a51c77007319 656
mbed_official 52:a51c77007319 657 /** @defgroup FSMC_Flags
mbed_official 52:a51c77007319 658 * @{
mbed_official 52:a51c77007319 659 */
mbed_official 52:a51c77007319 660
mbed_official 52:a51c77007319 661 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
mbed_official 52:a51c77007319 662 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
mbed_official 52:a51c77007319 663 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
mbed_official 52:a51c77007319 664 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official 52:a51c77007319 665 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
mbed_official 52:a51c77007319 666 ((FLAG) == FSMC_FLAG_Level) || \
mbed_official 52:a51c77007319 667 ((FLAG) == FSMC_FLAG_FallingEdge) || \
mbed_official 52:a51c77007319 668 ((FLAG) == FSMC_FLAG_FEMPT))
mbed_official 52:a51c77007319 669
mbed_official 52:a51c77007319 670 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official 52:a51c77007319 671
mbed_official 52:a51c77007319 672 /**
mbed_official 52:a51c77007319 673 * @}
mbed_official 52:a51c77007319 674 */
mbed_official 52:a51c77007319 675
mbed_official 52:a51c77007319 676 /**
mbed_official 52:a51c77007319 677 * @}
mbed_official 52:a51c77007319 678 */
mbed_official 52:a51c77007319 679
mbed_official 52:a51c77007319 680 /**
mbed_official 52:a51c77007319 681 * @}
mbed_official 52:a51c77007319 682 */
mbed_official 52:a51c77007319 683
mbed_official 52:a51c77007319 684 /** @defgroup FSMC_Exported_Macros
mbed_official 52:a51c77007319 685 * @{
mbed_official 52:a51c77007319 686 */
mbed_official 52:a51c77007319 687
mbed_official 52:a51c77007319 688 /**
mbed_official 52:a51c77007319 689 * @}
mbed_official 52:a51c77007319 690 */
mbed_official 52:a51c77007319 691
mbed_official 52:a51c77007319 692 /** @defgroup FSMC_Exported_Functions
mbed_official 52:a51c77007319 693 * @{
mbed_official 52:a51c77007319 694 */
mbed_official 52:a51c77007319 695
mbed_official 52:a51c77007319 696 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
mbed_official 52:a51c77007319 697 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
mbed_official 52:a51c77007319 698 void FSMC_PCCARDDeInit(void);
mbed_official 52:a51c77007319 699 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
mbed_official 52:a51c77007319 700 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
mbed_official 52:a51c77007319 701 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
mbed_official 52:a51c77007319 702 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
mbed_official 52:a51c77007319 703 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
mbed_official 52:a51c77007319 704 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
mbed_official 52:a51c77007319 705 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official 52:a51c77007319 706 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official 52:a51c77007319 707 void FSMC_PCCARDCmd(FunctionalState NewState);
mbed_official 52:a51c77007319 708 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official 52:a51c77007319 709 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
mbed_official 52:a51c77007319 710 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
mbed_official 52:a51c77007319 711 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
mbed_official 52:a51c77007319 712 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
mbed_official 52:a51c77007319 713 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
mbed_official 52:a51c77007319 714 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
mbed_official 52:a51c77007319 715
mbed_official 52:a51c77007319 716 #ifdef __cplusplus
mbed_official 52:a51c77007319 717 }
mbed_official 52:a51c77007319 718 #endif
mbed_official 52:a51c77007319 719
mbed_official 52:a51c77007319 720 #endif /*__STM32F10x_FSMC_H */
mbed_official 52:a51c77007319 721 /**
mbed_official 52:a51c77007319 722 * @}
mbed_official 52:a51c77007319 723 */
mbed_official 52:a51c77007319 724
mbed_official 52:a51c77007319 725 /**
mbed_official 52:a51c77007319 726 * @}
mbed_official 52:a51c77007319 727 */
mbed_official 52:a51c77007319 728
mbed_official 52:a51c77007319 729 /**
mbed_official 52:a51c77007319 730 * @}
mbed_official 52:a51c77007319 731 */
mbed_official 52:a51c77007319 732
mbed_official 52:a51c77007319 733 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/