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mbed library sources

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/system_stm32l0xx.c@181:a4cbdfbbd2f4, 2014-05-07 (annotated)

Committer:
mbed_official
Date:
Wed May 07 13:15:08 2014 +0100
Revision:
181:a4cbdfbbd2f4
Synchronized with git revision 7751e759576c6fd68deccb81ea82bac19ed41745



Full URL: https://github.com/mbedmicro/mbed/commit/7751e759576c6fd68deccb81ea82bac19ed41745/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 181:a4cbdfbbd2f4 1 /**
mbed_official 181:a4cbdfbbd2f4 2 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 3 * @file system_stm32l0xx.c
mbed_official 181:a4cbdfbbd2f4 4 * @author MCD Application Team
mbed_official 181:a4cbdfbbd2f4 5 * @version V1.0.0
mbed_official 181:a4cbdfbbd2f4 6 * @date 22-April-2014
mbed_official 181:a4cbdfbbd2f4 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
mbed_official 181:a4cbdfbbd2f4 8 *
mbed_official 181:a4cbdfbbd2f4 9 * This file provides two functions and one global variable to be called from
mbed_official 181:a4cbdfbbd2f4 10 * user application:
mbed_official 181:a4cbdfbbd2f4 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 181:a4cbdfbbd2f4 12 * before branch to main program. This call is made inside
mbed_official 181:a4cbdfbbd2f4 13 * the "startup_stm32l0xx.s" file.
mbed_official 181:a4cbdfbbd2f4 14 *
mbed_official 181:a4cbdfbbd2f4 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 181:a4cbdfbbd2f4 16 * by the user application to setup the SysTick
mbed_official 181:a4cbdfbbd2f4 17 * timer or configure other parameters.
mbed_official 181:a4cbdfbbd2f4 18 *
mbed_official 181:a4cbdfbbd2f4 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 181:a4cbdfbbd2f4 20 * be called whenever the core clock is changed
mbed_official 181:a4cbdfbbd2f4 21 * during program execution.
mbed_official 181:a4cbdfbbd2f4 22 *
mbed_official 181:a4cbdfbbd2f4 23 * This file configures the system clock as follows:
mbed_official 181:a4cbdfbbd2f4 24 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 181:a4cbdfbbd2f4 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 181:a4cbdfbbd2f4 27 * | 2- PLL_HSE_XTAL |
mbed_official 181:a4cbdfbbd2f4 28 * | (external 8 MHz xtal) |
mbed_official 181:a4cbdfbbd2f4 29 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 30 * SYSCLK(MHz) | 32 | 32
mbed_official 181:a4cbdfbbd2f4 31 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 32 * AHBCLK (MHz) | 32 | 32
mbed_official 181:a4cbdfbbd2f4 33 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 34 * APB1CLK (MHz) | 32 | 32
mbed_official 181:a4cbdfbbd2f4 35 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 36 * APB2CLK (MHz) | 32 | 32
mbed_official 181:a4cbdfbbd2f4 37 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 38 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 181:a4cbdfbbd2f4 39 *-----------------------------------------------------------------------------
mbed_official 181:a4cbdfbbd2f4 40 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 41 * @attention
mbed_official 181:a4cbdfbbd2f4 42 *
mbed_official 181:a4cbdfbbd2f4 43 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 181:a4cbdfbbd2f4 44 *
mbed_official 181:a4cbdfbbd2f4 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 181:a4cbdfbbd2f4 46 * are permitted provided that the following conditions are met:
mbed_official 181:a4cbdfbbd2f4 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 48 * this list of conditions and the following disclaimer.
mbed_official 181:a4cbdfbbd2f4 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 181:a4cbdfbbd2f4 51 * and/or other materials provided with the distribution.
mbed_official 181:a4cbdfbbd2f4 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 181:a4cbdfbbd2f4 53 * may be used to endorse or promote products derived from this software
mbed_official 181:a4cbdfbbd2f4 54 * without specific prior written permission.
mbed_official 181:a4cbdfbbd2f4 55 *
mbed_official 181:a4cbdfbbd2f4 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 181:a4cbdfbbd2f4 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 181:a4cbdfbbd2f4 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 181:a4cbdfbbd2f4 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 181:a4cbdfbbd2f4 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 181:a4cbdfbbd2f4 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 181:a4cbdfbbd2f4 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 181:a4cbdfbbd2f4 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 181:a4cbdfbbd2f4 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 181:a4cbdfbbd2f4 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 181:a4cbdfbbd2f4 66 *
mbed_official 181:a4cbdfbbd2f4 67 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 68 */
mbed_official 181:a4cbdfbbd2f4 69
mbed_official 181:a4cbdfbbd2f4 70 /** @addtogroup CMSIS
mbed_official 181:a4cbdfbbd2f4 71 * @{
mbed_official 181:a4cbdfbbd2f4 72 */
mbed_official 181:a4cbdfbbd2f4 73
mbed_official 181:a4cbdfbbd2f4 74 /** @addtogroup stm32l0xx_system
mbed_official 181:a4cbdfbbd2f4 75 * @{
mbed_official 181:a4cbdfbbd2f4 76 */
mbed_official 181:a4cbdfbbd2f4 77
mbed_official 181:a4cbdfbbd2f4 78 /** @addtogroup STM32L0xx_System_Private_Includes
mbed_official 181:a4cbdfbbd2f4 79 * @{
mbed_official 181:a4cbdfbbd2f4 80 */
mbed_official 181:a4cbdfbbd2f4 81
mbed_official 181:a4cbdfbbd2f4 82 #include "stm32l0xx.h"
mbed_official 181:a4cbdfbbd2f4 83
mbed_official 181:a4cbdfbbd2f4 84 #if !defined (HSE_VALUE)
mbed_official 181:a4cbdfbbd2f4 85 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
mbed_official 181:a4cbdfbbd2f4 86 #endif /* HSE_VALUE */
mbed_official 181:a4cbdfbbd2f4 87
mbed_official 181:a4cbdfbbd2f4 88 #if !defined (MSI_VALUE)
mbed_official 181:a4cbdfbbd2f4 89 #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 181:a4cbdfbbd2f4 90 #endif /* MSI_VALUE */
mbed_official 181:a4cbdfbbd2f4 91
mbed_official 181:a4cbdfbbd2f4 92 #if !defined (HSI_VALUE)
mbed_official 181:a4cbdfbbd2f4 93 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 181:a4cbdfbbd2f4 94 #endif /* HSI_VALUE */
mbed_official 181:a4cbdfbbd2f4 95
mbed_official 181:a4cbdfbbd2f4 96
mbed_official 181:a4cbdfbbd2f4 97 /**
mbed_official 181:a4cbdfbbd2f4 98 * @}
mbed_official 181:a4cbdfbbd2f4 99 */
mbed_official 181:a4cbdfbbd2f4 100
mbed_official 181:a4cbdfbbd2f4 101 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
mbed_official 181:a4cbdfbbd2f4 102 * @{
mbed_official 181:a4cbdfbbd2f4 103 */
mbed_official 181:a4cbdfbbd2f4 104
mbed_official 181:a4cbdfbbd2f4 105 /**
mbed_official 181:a4cbdfbbd2f4 106 * @}
mbed_official 181:a4cbdfbbd2f4 107 */
mbed_official 181:a4cbdfbbd2f4 108
mbed_official 181:a4cbdfbbd2f4 109 /** @addtogroup STM32L0xx_System_Private_Defines
mbed_official 181:a4cbdfbbd2f4 110 * @{
mbed_official 181:a4cbdfbbd2f4 111 */
mbed_official 181:a4cbdfbbd2f4 112 /************************* Miscellaneous Configuration ************************/
mbed_official 181:a4cbdfbbd2f4 113
mbed_official 181:a4cbdfbbd2f4 114 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 181:a4cbdfbbd2f4 115 Internal SRAM. */
mbed_official 181:a4cbdfbbd2f4 116 /* #define VECT_TAB_SRAM */
mbed_official 181:a4cbdfbbd2f4 117 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 181:a4cbdfbbd2f4 118 This value must be a multiple of 0x200. */
mbed_official 181:a4cbdfbbd2f4 119 /******************************************************************************/
mbed_official 181:a4cbdfbbd2f4 120 /**
mbed_official 181:a4cbdfbbd2f4 121 * @}
mbed_official 181:a4cbdfbbd2f4 122 */
mbed_official 181:a4cbdfbbd2f4 123
mbed_official 181:a4cbdfbbd2f4 124 /** @addtogroup STM32L0xx_System_Private_Macros
mbed_official 181:a4cbdfbbd2f4 125 * @{
mbed_official 181:a4cbdfbbd2f4 126 */
mbed_official 181:a4cbdfbbd2f4 127
mbed_official 181:a4cbdfbbd2f4 128 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 181:a4cbdfbbd2f4 129 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 181:a4cbdfbbd2f4 130 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 181:a4cbdfbbd2f4 131
mbed_official 181:a4cbdfbbd2f4 132 /**
mbed_official 181:a4cbdfbbd2f4 133 * @}
mbed_official 181:a4cbdfbbd2f4 134 */
mbed_official 181:a4cbdfbbd2f4 135
mbed_official 181:a4cbdfbbd2f4 136 /** @addtogroup STM32L0xx_System_Private_Variables
mbed_official 181:a4cbdfbbd2f4 137 * @{
mbed_official 181:a4cbdfbbd2f4 138 */
mbed_official 181:a4cbdfbbd2f4 139 /* This variable is updated in three ways:
mbed_official 181:a4cbdfbbd2f4 140 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 181:a4cbdfbbd2f4 141 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 181:a4cbdfbbd2f4 142 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 181:a4cbdfbbd2f4 143 Note: If you use this function to configure the system clock; then there
mbed_official 181:a4cbdfbbd2f4 144 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 181:a4cbdfbbd2f4 145 variable is updated automatically.
mbed_official 181:a4cbdfbbd2f4 146 */
mbed_official 181:a4cbdfbbd2f4 147 uint32_t SystemCoreClock = 32000000;
mbed_official 181:a4cbdfbbd2f4 148
mbed_official 181:a4cbdfbbd2f4 149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 181:a4cbdfbbd2f4 150 const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official 181:a4cbdfbbd2f4 151 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 181:a4cbdfbbd2f4 152 const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000};
mbed_official 181:a4cbdfbbd2f4 153
mbed_official 181:a4cbdfbbd2f4 154 /**
mbed_official 181:a4cbdfbbd2f4 155 * @}
mbed_official 181:a4cbdfbbd2f4 156 */
mbed_official 181:a4cbdfbbd2f4 157
mbed_official 181:a4cbdfbbd2f4 158 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
mbed_official 181:a4cbdfbbd2f4 159 * @{
mbed_official 181:a4cbdfbbd2f4 160 */
mbed_official 181:a4cbdfbbd2f4 161
mbed_official 181:a4cbdfbbd2f4 162 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 181:a4cbdfbbd2f4 163 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 181:a4cbdfbbd2f4 164 #endif
mbed_official 181:a4cbdfbbd2f4 165
mbed_official 181:a4cbdfbbd2f4 166 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 181:a4cbdfbbd2f4 167
mbed_official 181:a4cbdfbbd2f4 168 /**
mbed_official 181:a4cbdfbbd2f4 169 * @}
mbed_official 181:a4cbdfbbd2f4 170 */
mbed_official 181:a4cbdfbbd2f4 171
mbed_official 181:a4cbdfbbd2f4 172 /** @addtogroup STM32L0xx_System_Private_Functions
mbed_official 181:a4cbdfbbd2f4 173 * @{
mbed_official 181:a4cbdfbbd2f4 174 */
mbed_official 181:a4cbdfbbd2f4 175
mbed_official 181:a4cbdfbbd2f4 176 /**
mbed_official 181:a4cbdfbbd2f4 177 * @brief Setup the microcontroller system.
mbed_official 181:a4cbdfbbd2f4 178 * @param None
mbed_official 181:a4cbdfbbd2f4 179 * @retval None
mbed_official 181:a4cbdfbbd2f4 180 */
mbed_official 181:a4cbdfbbd2f4 181 void SystemInit (void)
mbed_official 181:a4cbdfbbd2f4 182 {
mbed_official 181:a4cbdfbbd2f4 183 /*!< Set MSION bit */
mbed_official 181:a4cbdfbbd2f4 184 RCC->CR |= (uint32_t)0x00000100;
mbed_official 181:a4cbdfbbd2f4 185
mbed_official 181:a4cbdfbbd2f4 186 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official 181:a4cbdfbbd2f4 187 RCC->CFGR &= (uint32_t) 0x88FF400C;
mbed_official 181:a4cbdfbbd2f4 188
mbed_official 181:a4cbdfbbd2f4 189 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
mbed_official 181:a4cbdfbbd2f4 190 RCC->CR &= (uint32_t)0xFEF6FFF6;
mbed_official 181:a4cbdfbbd2f4 191
mbed_official 181:a4cbdfbbd2f4 192 /*!< Reset HSI48ON bit */
mbed_official 181:a4cbdfbbd2f4 193 RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
mbed_official 181:a4cbdfbbd2f4 194
mbed_official 181:a4cbdfbbd2f4 195 /*!< Reset HSEBYP bit */
mbed_official 181:a4cbdfbbd2f4 196 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 181:a4cbdfbbd2f4 197
mbed_official 181:a4cbdfbbd2f4 198 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official 181:a4cbdfbbd2f4 199 RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official 181:a4cbdfbbd2f4 200
mbed_official 181:a4cbdfbbd2f4 201 /*!< Disable all interrupts */
mbed_official 181:a4cbdfbbd2f4 202 RCC->CIER = 0x00000000;
mbed_official 181:a4cbdfbbd2f4 203
mbed_official 181:a4cbdfbbd2f4 204 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 181:a4cbdfbbd2f4 205 #ifdef VECT_TAB_SRAM
mbed_official 181:a4cbdfbbd2f4 206 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 181:a4cbdfbbd2f4 207 #else
mbed_official 181:a4cbdfbbd2f4 208 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 181:a4cbdfbbd2f4 209 #endif
mbed_official 181:a4cbdfbbd2f4 210
mbed_official 181:a4cbdfbbd2f4 211 /* Configure the Cube driver */
mbed_official 181:a4cbdfbbd2f4 212 HAL_Init();
mbed_official 181:a4cbdfbbd2f4 213
mbed_official 181:a4cbdfbbd2f4 214 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 181:a4cbdfbbd2f4 215 AHB/APBx prescalers and Flash settings */
mbed_official 181:a4cbdfbbd2f4 216 SetSysClock();
mbed_official 181:a4cbdfbbd2f4 217 }
mbed_official 181:a4cbdfbbd2f4 218
mbed_official 181:a4cbdfbbd2f4 219 /**
mbed_official 181:a4cbdfbbd2f4 220 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 181:a4cbdfbbd2f4 221 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 181:a4cbdfbbd2f4 222 * be used by the user application to setup the SysTick timer or configure
mbed_official 181:a4cbdfbbd2f4 223 * other parameters.
mbed_official 181:a4cbdfbbd2f4 224 *
mbed_official 181:a4cbdfbbd2f4 225 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 181:a4cbdfbbd2f4 226 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 181:a4cbdfbbd2f4 227 * based on this variable will be incorrect.
mbed_official 181:a4cbdfbbd2f4 228 *
mbed_official 181:a4cbdfbbd2f4 229 * @note - The system frequency computed by this function is not the real
mbed_official 181:a4cbdfbbd2f4 230 * frequency in the chip. It is calculated based on the predefined
mbed_official 181:a4cbdfbbd2f4 231 * constant and the selected clock source:
mbed_official 181:a4cbdfbbd2f4 232 *
mbed_official 181:a4cbdfbbd2f4 233 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official 181:a4cbdfbbd2f4 234 * value as defined by the MSI range.
mbed_official 181:a4cbdfbbd2f4 235 *
mbed_official 181:a4cbdfbbd2f4 236 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 181:a4cbdfbbd2f4 237 *
mbed_official 181:a4cbdfbbd2f4 238 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 181:a4cbdfbbd2f4 239 *
mbed_official 181:a4cbdfbbd2f4 240 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 181:a4cbdfbbd2f4 241 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 181:a4cbdfbbd2f4 242 *
mbed_official 181:a4cbdfbbd2f4 243 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 181:a4cbdfbbd2f4 244 * 16 MHz) but the real value may vary depending on the variations
mbed_official 181:a4cbdfbbd2f4 245 * in voltage and temperature.
mbed_official 181:a4cbdfbbd2f4 246 *
mbed_official 181:a4cbdfbbd2f4 247 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 181:a4cbdfbbd2f4 248 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 181:a4cbdfbbd2f4 249 * frequency of the crystal used. Otherwise, this function may
mbed_official 181:a4cbdfbbd2f4 250 * have wrong result.
mbed_official 181:a4cbdfbbd2f4 251 *
mbed_official 181:a4cbdfbbd2f4 252 * - The result of this function could be not correct when using fractional
mbed_official 181:a4cbdfbbd2f4 253 * value for HSE crystal.
mbed_official 181:a4cbdfbbd2f4 254 * @param None
mbed_official 181:a4cbdfbbd2f4 255 * @retval None
mbed_official 181:a4cbdfbbd2f4 256 */
mbed_official 181:a4cbdfbbd2f4 257 void SystemCoreClockUpdate (void)
mbed_official 181:a4cbdfbbd2f4 258 {
mbed_official 181:a4cbdfbbd2f4 259 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official 181:a4cbdfbbd2f4 260
mbed_official 181:a4cbdfbbd2f4 261 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 262 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 181:a4cbdfbbd2f4 263
mbed_official 181:a4cbdfbbd2f4 264 switch (tmp)
mbed_official 181:a4cbdfbbd2f4 265 {
mbed_official 181:a4cbdfbbd2f4 266 case 0x00: /* MSI used as system clock */
mbed_official 181:a4cbdfbbd2f4 267 SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000);
mbed_official 181:a4cbdfbbd2f4 268 break;
mbed_official 181:a4cbdfbbd2f4 269 case 0x04: /* HSI used as system clock */
mbed_official 181:a4cbdfbbd2f4 270 SystemCoreClock = HSI_VALUE;
mbed_official 181:a4cbdfbbd2f4 271 break;
mbed_official 181:a4cbdfbbd2f4 272 case 0x08: /* HSE used as system clock */
mbed_official 181:a4cbdfbbd2f4 273 SystemCoreClock = HSE_VALUE;
mbed_official 181:a4cbdfbbd2f4 274 break;
mbed_official 181:a4cbdfbbd2f4 275 case 0x0C: /* PLL used as system clock */
mbed_official 181:a4cbdfbbd2f4 276 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 181:a4cbdfbbd2f4 277 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 181:a4cbdfbbd2f4 278 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official 181:a4cbdfbbd2f4 279 pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official 181:a4cbdfbbd2f4 280 plldiv = (plldiv >> 22) + 1;
mbed_official 181:a4cbdfbbd2f4 281
mbed_official 181:a4cbdfbbd2f4 282 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 181:a4cbdfbbd2f4 283
mbed_official 181:a4cbdfbbd2f4 284 if (pllsource == 0x00)
mbed_official 181:a4cbdfbbd2f4 285 {
mbed_official 181:a4cbdfbbd2f4 286 /* HSI oscillator clock selected as PLL clock entry */
mbed_official 181:a4cbdfbbd2f4 287 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 181:a4cbdfbbd2f4 288 }
mbed_official 181:a4cbdfbbd2f4 289 else
mbed_official 181:a4cbdfbbd2f4 290 {
mbed_official 181:a4cbdfbbd2f4 291 /* HSE selected as PLL clock entry */
mbed_official 181:a4cbdfbbd2f4 292 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 181:a4cbdfbbd2f4 293 }
mbed_official 181:a4cbdfbbd2f4 294 break;
mbed_official 181:a4cbdfbbd2f4 295 default: /* MSI used as system clock */
mbed_official 181:a4cbdfbbd2f4 296 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 181:a4cbdfbbd2f4 297 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 181:a4cbdfbbd2f4 298 break;
mbed_official 181:a4cbdfbbd2f4 299 }
mbed_official 181:a4cbdfbbd2f4 300 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 301 /* Get HCLK prescaler */
mbed_official 181:a4cbdfbbd2f4 302 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 181:a4cbdfbbd2f4 303 /* HCLK clock frequency */
mbed_official 181:a4cbdfbbd2f4 304 SystemCoreClock >>= tmp;
mbed_official 181:a4cbdfbbd2f4 305 }
mbed_official 181:a4cbdfbbd2f4 306
mbed_official 181:a4cbdfbbd2f4 307 /**
mbed_official 181:a4cbdfbbd2f4 308 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 181:a4cbdfbbd2f4 309 * AHB/APBx prescalers and Flash settings
mbed_official 181:a4cbdfbbd2f4 310 * @note This function should be called only once the RCC clock configuration
mbed_official 181:a4cbdfbbd2f4 311 * is reset to the default reset state (done in SystemInit() function).
mbed_official 181:a4cbdfbbd2f4 312 * @param None
mbed_official 181:a4cbdfbbd2f4 313 * @retval None
mbed_official 181:a4cbdfbbd2f4 314 */
mbed_official 181:a4cbdfbbd2f4 315 void SetSysClock(void)
mbed_official 181:a4cbdfbbd2f4 316 {
mbed_official 181:a4cbdfbbd2f4 317 /* 1- Try to start with HSE and external clock */
mbed_official 181:a4cbdfbbd2f4 318 #if USE_PLL_HSE_EXTC != 0
mbed_official 181:a4cbdfbbd2f4 319 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 181:a4cbdfbbd2f4 320 #endif
mbed_official 181:a4cbdfbbd2f4 321 {
mbed_official 181:a4cbdfbbd2f4 322 /* 2- If fail try to start with HSE and external xtal */
mbed_official 181:a4cbdfbbd2f4 323 #if USE_PLL_HSE_XTAL != 0
mbed_official 181:a4cbdfbbd2f4 324 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 181:a4cbdfbbd2f4 325 #endif
mbed_official 181:a4cbdfbbd2f4 326 {
mbed_official 181:a4cbdfbbd2f4 327 /* 3- If fail start with HSI clock */
mbed_official 181:a4cbdfbbd2f4 328 if (SetSysClock_PLL_HSI() == 0)
mbed_official 181:a4cbdfbbd2f4 329 {
mbed_official 181:a4cbdfbbd2f4 330 while(1)
mbed_official 181:a4cbdfbbd2f4 331 {
mbed_official 181:a4cbdfbbd2f4 332 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 181:a4cbdfbbd2f4 333 }
mbed_official 181:a4cbdfbbd2f4 334 }
mbed_official 181:a4cbdfbbd2f4 335 }
mbed_official 181:a4cbdfbbd2f4 336 }
mbed_official 181:a4cbdfbbd2f4 337
mbed_official 181:a4cbdfbbd2f4 338 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 181:a4cbdfbbd2f4 339 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official 181:a4cbdfbbd2f4 340 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
mbed_official 181:a4cbdfbbd2f4 341 }
mbed_official 181:a4cbdfbbd2f4 342
mbed_official 181:a4cbdfbbd2f4 343 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 181:a4cbdfbbd2f4 344 /******************************************************************************/
mbed_official 181:a4cbdfbbd2f4 345 /* PLL (clocked by HSE) used as System clock source */
mbed_official 181:a4cbdfbbd2f4 346 /******************************************************************************/
mbed_official 181:a4cbdfbbd2f4 347 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 181:a4cbdfbbd2f4 348 {
mbed_official 181:a4cbdfbbd2f4 349 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 181:a4cbdfbbd2f4 350 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 181:a4cbdfbbd2f4 351
mbed_official 181:a4cbdfbbd2f4 352 /* Used to gain time after DeepSleep in case HSI is used */
mbed_official 181:a4cbdfbbd2f4 353 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 181:a4cbdfbbd2f4 354 {
mbed_official 181:a4cbdfbbd2f4 355 return 0;
mbed_official 181:a4cbdfbbd2f4 356 }
mbed_official 181:a4cbdfbbd2f4 357
mbed_official 181:a4cbdfbbd2f4 358 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 181:a4cbdfbbd2f4 359 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 181:a4cbdfbbd2f4 360 regarding system frequency refer to product datasheet. */
mbed_official 181:a4cbdfbbd2f4 361 __PWR_CLK_ENABLE();
mbed_official 181:a4cbdfbbd2f4 362 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 181:a4cbdfbbd2f4 363
mbed_official 181:a4cbdfbbd2f4 364 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official 181:a4cbdfbbd2f4 365 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
mbed_official 181:a4cbdfbbd2f4 366 if (bypass == 0)
mbed_official 181:a4cbdfbbd2f4 367 {
mbed_official 181:a4cbdfbbd2f4 368 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 181:a4cbdfbbd2f4 369 }
mbed_official 181:a4cbdfbbd2f4 370 else
mbed_official 181:a4cbdfbbd2f4 371 {
mbed_official 181:a4cbdfbbd2f4 372 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 181:a4cbdfbbd2f4 373 }
mbed_official 181:a4cbdfbbd2f4 374 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official 181:a4cbdfbbd2f4 375 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 181:a4cbdfbbd2f4 376 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
mbed_official 181:a4cbdfbbd2f4 377 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 181:a4cbdfbbd2f4 378 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 181:a4cbdfbbd2f4 379 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
mbed_official 181:a4cbdfbbd2f4 380 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 181:a4cbdfbbd2f4 381 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 181:a4cbdfbbd2f4 382 {
mbed_official 181:a4cbdfbbd2f4 383 return 0; // FAIL
mbed_official 181:a4cbdfbbd2f4 384 }
mbed_official 181:a4cbdfbbd2f4 385
mbed_official 181:a4cbdfbbd2f4 386 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 181:a4cbdfbbd2f4 387 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 181:a4cbdfbbd2f4 388 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 389 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 390 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 391 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 392 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 181:a4cbdfbbd2f4 393 {
mbed_official 181:a4cbdfbbd2f4 394 return 0; // FAIL
mbed_official 181:a4cbdfbbd2f4 395 }
mbed_official 181:a4cbdfbbd2f4 396
mbed_official 181:a4cbdfbbd2f4 397 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 181:a4cbdfbbd2f4 398 //if (bypass == 0)
mbed_official 181:a4cbdfbbd2f4 399 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 181:a4cbdfbbd2f4 400 //else
mbed_official 181:a4cbdfbbd2f4 401 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 181:a4cbdfbbd2f4 402
mbed_official 181:a4cbdfbbd2f4 403 return 1; // OK
mbed_official 181:a4cbdfbbd2f4 404 }
mbed_official 181:a4cbdfbbd2f4 405 #endif
mbed_official 181:a4cbdfbbd2f4 406
mbed_official 181:a4cbdfbbd2f4 407 /******************************************************************************/
mbed_official 181:a4cbdfbbd2f4 408 /* PLL (clocked by HSI) used as System clock source */
mbed_official 181:a4cbdfbbd2f4 409 /******************************************************************************/
mbed_official 181:a4cbdfbbd2f4 410 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 181:a4cbdfbbd2f4 411 {
mbed_official 181:a4cbdfbbd2f4 412 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 181:a4cbdfbbd2f4 413 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 181:a4cbdfbbd2f4 414
mbed_official 181:a4cbdfbbd2f4 415 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 181:a4cbdfbbd2f4 416 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 181:a4cbdfbbd2f4 417 regarding system frequency refer to product datasheet. */
mbed_official 181:a4cbdfbbd2f4 418 __PWR_CLK_ENABLE();
mbed_official 181:a4cbdfbbd2f4 419 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 181:a4cbdfbbd2f4 420
mbed_official 181:a4cbdfbbd2f4 421 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
mbed_official 181:a4cbdfbbd2f4 422 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 181:a4cbdfbbd2f4 423 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 181:a4cbdfbbd2f4 424 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 181:a4cbdfbbd2f4 425 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 181:a4cbdfbbd2f4 426 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
mbed_official 181:a4cbdfbbd2f4 427 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 181:a4cbdfbbd2f4 428 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 181:a4cbdfbbd2f4 429 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
mbed_official 181:a4cbdfbbd2f4 430 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 181:a4cbdfbbd2f4 431 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 181:a4cbdfbbd2f4 432 {
mbed_official 181:a4cbdfbbd2f4 433 return 0; // FAIL
mbed_official 181:a4cbdfbbd2f4 434 }
mbed_official 181:a4cbdfbbd2f4 435
mbed_official 181:a4cbdfbbd2f4 436 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 181:a4cbdfbbd2f4 437 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 181:a4cbdfbbd2f4 438 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 439 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 440 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 441 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 181:a4cbdfbbd2f4 442 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 181:a4cbdfbbd2f4 443 {
mbed_official 181:a4cbdfbbd2f4 444 return 0; // FAIL
mbed_official 181:a4cbdfbbd2f4 445 }
mbed_official 181:a4cbdfbbd2f4 446
mbed_official 181:a4cbdfbbd2f4 447 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 181:a4cbdfbbd2f4 448 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 181:a4cbdfbbd2f4 449
mbed_official 181:a4cbdfbbd2f4 450 return 1; // OK
mbed_official 181:a4cbdfbbd2f4 451 }
mbed_official 181:a4cbdfbbd2f4 452
mbed_official 181:a4cbdfbbd2f4 453 /* Used for the different timeouts in the HAL */
mbed_official 181:a4cbdfbbd2f4 454 void SysTick_Handler(void)
mbed_official 181:a4cbdfbbd2f4 455 {
mbed_official 181:a4cbdfbbd2f4 456 HAL_IncTick();
mbed_official 181:a4cbdfbbd2f4 457 }
mbed_official 181:a4cbdfbbd2f4 458
mbed_official 181:a4cbdfbbd2f4 459 /**
mbed_official 181:a4cbdfbbd2f4 460 * @}
mbed_official 181:a4cbdfbbd2f4 461 */
mbed_official 181:a4cbdfbbd2f4 462
mbed_official 181:a4cbdfbbd2f4 463 /**
mbed_official 181:a4cbdfbbd2f4 464 * @}
mbed_official 181:a4cbdfbbd2f4 465 */
mbed_official 181:a4cbdfbbd2f4 466
mbed_official 181:a4cbdfbbd2f4 467 /**
mbed_official 181:a4cbdfbbd2f4 468 * @}
mbed_official 181:a4cbdfbbd2f4 469 */
mbed_official 181:a4cbdfbbd2f4 470
mbed_official 181:a4cbdfbbd2f4 471 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/