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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc.h@181:a4cbdfbbd2f4, 2014-05-07 (annotated)

Committer:: mbed_official
Date:: Wed May 07 13:15:08 2014 +0100
Revision:: 181:a4cbdfbbd2f4
Child:: 217:d0ccc61c1fd4

Synchronized with git revision 7751e759576c6fd68deccb81ea82bac19ed41745



Full URL: https://github.com/mbedmicro/mbed/commit/7751e759576c6fd68deccb81ea82bac19ed41745/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	181:a4cbdfbbd2f4	1	/**
mbed_official	181:a4cbdfbbd2f4	2	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	3	* @file stm32l0xx_hal_rcc.h
mbed_official	181:a4cbdfbbd2f4	4	* @author MCD Application Team
mbed_official	181:a4cbdfbbd2f4	5	* @version V1.0.0
mbed_official	181:a4cbdfbbd2f4	6	* @date 22-April-2014
mbed_official	181:a4cbdfbbd2f4	7	* @brief Header file of RCC HAL module.
mbed_official	181:a4cbdfbbd2f4	8	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	9	* @attention
mbed_official	181:a4cbdfbbd2f4	10	*
mbed_official	181:a4cbdfbbd2f4	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	181:a4cbdfbbd2f4	12	*
mbed_official	181:a4cbdfbbd2f4	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	181:a4cbdfbbd2f4	14	* are permitted provided that the following conditions are met:
mbed_official	181:a4cbdfbbd2f4	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	181:a4cbdfbbd2f4	16	* this list of conditions and the following disclaimer.
mbed_official	181:a4cbdfbbd2f4	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	181:a4cbdfbbd2f4	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	181:a4cbdfbbd2f4	19	* and/or other materials provided with the distribution.
mbed_official	181:a4cbdfbbd2f4	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	181:a4cbdfbbd2f4	21	* may be used to endorse or promote products derived from this software
mbed_official	181:a4cbdfbbd2f4	22	* without specific prior written permission.
mbed_official	181:a4cbdfbbd2f4	23	*
mbed_official	181:a4cbdfbbd2f4	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	181:a4cbdfbbd2f4	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	181:a4cbdfbbd2f4	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	181:a4cbdfbbd2f4	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	181:a4cbdfbbd2f4	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	181:a4cbdfbbd2f4	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	181:a4cbdfbbd2f4	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	181:a4cbdfbbd2f4	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	181:a4cbdfbbd2f4	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	181:a4cbdfbbd2f4	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	181:a4cbdfbbd2f4	34	*
mbed_official	181:a4cbdfbbd2f4	35	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	36	*/
mbed_official	181:a4cbdfbbd2f4	37
mbed_official	181:a4cbdfbbd2f4	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	39	#ifndef __STM32L0xx_HAL_RCC_H
mbed_official	181:a4cbdfbbd2f4	40	#define __STM32L0xx_HAL_RCC_H
mbed_official	181:a4cbdfbbd2f4	41
mbed_official	181:a4cbdfbbd2f4	42	#ifdef __cplusplus
mbed_official	181:a4cbdfbbd2f4	43	extern "C" {
mbed_official	181:a4cbdfbbd2f4	44	#endif
mbed_official	181:a4cbdfbbd2f4	45
mbed_official	181:a4cbdfbbd2f4	46	/* Includes ------------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	47	#include "stm32l0xx_hal_def.h"
mbed_official	181:a4cbdfbbd2f4	48
mbed_official	181:a4cbdfbbd2f4	49	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	181:a4cbdfbbd2f4	50	* @{
mbed_official	181:a4cbdfbbd2f4	51	*/
mbed_official	181:a4cbdfbbd2f4	52
mbed_official	181:a4cbdfbbd2f4	53	/** @addtogroup RCC
mbed_official	181:a4cbdfbbd2f4	54	* @{
mbed_official	181:a4cbdfbbd2f4	55	*/
mbed_official	181:a4cbdfbbd2f4	56
mbed_official	181:a4cbdfbbd2f4	57	/* Exported types ------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	58
mbed_official	181:a4cbdfbbd2f4	59	/**
mbed_official	181:a4cbdfbbd2f4	60	* @brief RCC PLL configuration structure definition
mbed_official	181:a4cbdfbbd2f4	61	*/
mbed_official	181:a4cbdfbbd2f4	62	typedef struct
mbed_official	181:a4cbdfbbd2f4	63	{
mbed_official	181:a4cbdfbbd2f4	64	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	181:a4cbdfbbd2f4	65	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	181:a4cbdfbbd2f4	66
mbed_official	181:a4cbdfbbd2f4	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	181:a4cbdfbbd2f4	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	181:a4cbdfbbd2f4	69
mbed_official	181:a4cbdfbbd2f4	70	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
mbed_official	181:a4cbdfbbd2f4	71	This parameter must of RCC_PLLMultiplication_Factor */
mbed_official	181:a4cbdfbbd2f4	72
mbed_official	181:a4cbdfbbd2f4	73	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
mbed_official	181:a4cbdfbbd2f4	74	This parameter must be a value of @ref RCC_PLLDivider_Factor */
mbed_official	181:a4cbdfbbd2f4	75
mbed_official	181:a4cbdfbbd2f4	76	}RCC_PLLInitTypeDef;
mbed_official	181:a4cbdfbbd2f4	77
mbed_official	181:a4cbdfbbd2f4	78	/**
mbed_official	181:a4cbdfbbd2f4	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	181:a4cbdfbbd2f4	80	*/
mbed_official	181:a4cbdfbbd2f4	81	typedef struct
mbed_official	181:a4cbdfbbd2f4	82	{
mbed_official	181:a4cbdfbbd2f4	83	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	181:a4cbdfbbd2f4	84	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	181:a4cbdfbbd2f4	85
mbed_official	181:a4cbdfbbd2f4	86	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	181:a4cbdfbbd2f4	87	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	181:a4cbdfbbd2f4	88
mbed_official	181:a4cbdfbbd2f4	89	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	181:a4cbdfbbd2f4	90	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	181:a4cbdfbbd2f4	91
mbed_official	181:a4cbdfbbd2f4	92	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	181:a4cbdfbbd2f4	93	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	181:a4cbdfbbd2f4	94
mbed_official	181:a4cbdfbbd2f4	95	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	181:a4cbdfbbd2f4	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	181:a4cbdfbbd2f4	97
mbed_official	181:a4cbdfbbd2f4	98	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	181:a4cbdfbbd2f4	99	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	181:a4cbdfbbd2f4	100
mbed_official	181:a4cbdfbbd2f4	101	uint32_t HSI48State; /*!< The new state of the HSI48.
mbed_official	181:a4cbdfbbd2f4	102	This parameter can be a value of @ref RCC_HSI48_Config */
mbed_official	181:a4cbdfbbd2f4	103
mbed_official	181:a4cbdfbbd2f4	104	uint32_t MSIState; /*!< The new state of the MSI.
mbed_official	181:a4cbdfbbd2f4	105	This parameter can be a value of @ref RCC_MSI_Config */
mbed_official	181:a4cbdfbbd2f4	106
mbed_official	181:a4cbdfbbd2f4	107	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
mbed_official	181:a4cbdfbbd2f4	108	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official	181:a4cbdfbbd2f4	109
mbed_official	181:a4cbdfbbd2f4	110	uint32_t MSIClockRange; /*!< The MSI frequency range.
mbed_official	181:a4cbdfbbd2f4	111	This parameter can be a value of @ref RCC_MSI_Clock_Range */
mbed_official	181:a4cbdfbbd2f4	112
mbed_official	181:a4cbdfbbd2f4	113	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	181:a4cbdfbbd2f4	114
mbed_official	181:a4cbdfbbd2f4	115	}RCC_OscInitTypeDef;
mbed_official	181:a4cbdfbbd2f4	116
mbed_official	181:a4cbdfbbd2f4	117	/**
mbed_official	181:a4cbdfbbd2f4	118	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	181:a4cbdfbbd2f4	119	*/
mbed_official	181:a4cbdfbbd2f4	120	typedef struct
mbed_official	181:a4cbdfbbd2f4	121	{
mbed_official	181:a4cbdfbbd2f4	122	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	181:a4cbdfbbd2f4	123	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	181:a4cbdfbbd2f4	124
mbed_official	181:a4cbdfbbd2f4	125	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	181:a4cbdfbbd2f4	126	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	181:a4cbdfbbd2f4	127
mbed_official	181:a4cbdfbbd2f4	128	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	181:a4cbdfbbd2f4	129	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	181:a4cbdfbbd2f4	130
mbed_official	181:a4cbdfbbd2f4	131	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	181:a4cbdfbbd2f4	132	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	181:a4cbdfbbd2f4	133
mbed_official	181:a4cbdfbbd2f4	134	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	181:a4cbdfbbd2f4	135	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	181:a4cbdfbbd2f4	136
mbed_official	181:a4cbdfbbd2f4	137	}RCC_ClkInitTypeDef;
mbed_official	181:a4cbdfbbd2f4	138
mbed_official	181:a4cbdfbbd2f4	139	/* Exported constants --------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	140	/** @defgroup RCC_Exported_Constants
mbed_official	181:a4cbdfbbd2f4	141	* @{
mbed_official	181:a4cbdfbbd2f4	142	*/
mbed_official	181:a4cbdfbbd2f4	143
mbed_official	181:a4cbdfbbd2f4	144	/** @defgroup RCC_BitAddress_AliasRegion
mbed_official	181:a4cbdfbbd2f4	145	* @brief RCC registers bit address in the alias region
mbed_official	181:a4cbdfbbd2f4	146	* @{
mbed_official	181:a4cbdfbbd2f4	147	*/
mbed_official	181:a4cbdfbbd2f4	148	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	181:a4cbdfbbd2f4	149	/* --- CR Register ---*/
mbed_official	181:a4cbdfbbd2f4	150	/* Alias word address of HSION bit */
mbed_official	181:a4cbdfbbd2f4	151	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	181:a4cbdfbbd2f4	152	/* --- CFGR Register ---*/
mbed_official	181:a4cbdfbbd2f4	153	/* Alias word address of I2SSRC bit */
mbed_official	181:a4cbdfbbd2f4	154	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	181:a4cbdfbbd2f4	155	/* --- CSR Register ---*/
mbed_official	181:a4cbdfbbd2f4	156	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official	181:a4cbdfbbd2f4	157
mbed_official	181:a4cbdfbbd2f4	158	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	181:a4cbdfbbd2f4	159	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official	181:a4cbdfbbd2f4	160
mbed_official	181:a4cbdfbbd2f4	161	/* CIER register byte 0 (Bits[0:8]) base address */
mbed_official	181:a4cbdfbbd2f4	162	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
mbed_official	181:a4cbdfbbd2f4	163
mbed_official	181:a4cbdfbbd2f4	164	#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	181:a4cbdfbbd2f4	165	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	181:a4cbdfbbd2f4	166
mbed_official	181:a4cbdfbbd2f4	167	/**
mbed_official	181:a4cbdfbbd2f4	168	* @}
mbed_official	181:a4cbdfbbd2f4	169	*/
mbed_official	181:a4cbdfbbd2f4	170
mbed_official	181:a4cbdfbbd2f4	171	/** @defgroup RCC_Oscillator_Type
mbed_official	181:a4cbdfbbd2f4	172	* @{
mbed_official	181:a4cbdfbbd2f4	173	*/
mbed_official	181:a4cbdfbbd2f4	174	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	181:a4cbdfbbd2f4	175	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	181:a4cbdfbbd2f4	176	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	181:a4cbdfbbd2f4	177	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	181:a4cbdfbbd2f4	178	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	181:a4cbdfbbd2f4	179	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
mbed_official	181:a4cbdfbbd2f4	180	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
mbed_official	181:a4cbdfbbd2f4	181
mbed_official	181:a4cbdfbbd2f4	182	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	181:a4cbdfbbd2f4	183	((OSCILLATOR) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	181:a4cbdfbbd2f4	184	((OSCILLATOR) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	185	((OSCILLATOR) == RCC_OSCILLATORTYPE_LSE) \|\| \
mbed_official	181:a4cbdfbbd2f4	186	((OSCILLATOR) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	187	((OSCILLATOR) == RCC_OSCILLATORTYPE_MSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	188	((OSCILLATOR) == RCC_OSCILLATORTYPE_HSI48))
mbed_official	181:a4cbdfbbd2f4	189	/**
mbed_official	181:a4cbdfbbd2f4	190	* @}
mbed_official	181:a4cbdfbbd2f4	191	*/
mbed_official	181:a4cbdfbbd2f4	192
mbed_official	181:a4cbdfbbd2f4	193	/** @defgroup RCC_HSE_Config
mbed_official	181:a4cbdfbbd2f4	194	* @{
mbed_official	181:a4cbdfbbd2f4	195	*/
mbed_official	181:a4cbdfbbd2f4	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
mbed_official	181:a4cbdfbbd2f4	197	#define RCC_HSE_ON RCC_CR_HSEON
mbed_official	181:a4cbdfbbd2f4	198	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
mbed_official	181:a4cbdfbbd2f4	199
mbed_official	181:a4cbdfbbd2f4	200	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
mbed_official	181:a4cbdfbbd2f4	201	((HSE) == RCC_HSE_BYPASS))
mbed_official	181:a4cbdfbbd2f4	202	/**
mbed_official	181:a4cbdfbbd2f4	203	* @}
mbed_official	181:a4cbdfbbd2f4	204	*/
mbed_official	181:a4cbdfbbd2f4	205
mbed_official	181:a4cbdfbbd2f4	206	/** @defgroup RCC_LSE_Config
mbed_official	181:a4cbdfbbd2f4	207	* @{
mbed_official	181:a4cbdfbbd2f4	208	*/
mbed_official	181:a4cbdfbbd2f4	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
mbed_official	181:a4cbdfbbd2f4	210	#define RCC_LSE_ON RCC_CSR_LSEON
mbed_official	181:a4cbdfbbd2f4	211	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
mbed_official	181:a4cbdfbbd2f4	212
mbed_official	181:a4cbdfbbd2f4	213	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
mbed_official	181:a4cbdfbbd2f4	214	((LSE) == RCC_LSE_BYPASS))
mbed_official	181:a4cbdfbbd2f4	215	/**
mbed_official	181:a4cbdfbbd2f4	216	* @}
mbed_official	181:a4cbdfbbd2f4	217	*/
mbed_official	181:a4cbdfbbd2f4	218
mbed_official	181:a4cbdfbbd2f4	219	/** @defgroup RCC_HSI_Config
mbed_official	181:a4cbdfbbd2f4	220	* @{
mbed_official	181:a4cbdfbbd2f4	221	*/
mbed_official	181:a4cbdfbbd2f4	222	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	181:a4cbdfbbd2f4	223	#define RCC_HSI_ON ((uint8_t)0x01)
mbed_official	181:a4cbdfbbd2f4	224	#define RCC_HSI_DIV4 ((uint8_t)0x09)
mbed_official	181:a4cbdfbbd2f4	225	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON) \|\| \
mbed_official	181:a4cbdfbbd2f4	226	((HSI) == RCC_HSI_DIV4))
mbed_official	181:a4cbdfbbd2f4	227
mbed_official	181:a4cbdfbbd2f4	228	/**
mbed_official	181:a4cbdfbbd2f4	229	* @}
mbed_official	181:a4cbdfbbd2f4	230	*/
mbed_official	181:a4cbdfbbd2f4	231
mbed_official	181:a4cbdfbbd2f4	232	/** @defgroup RCC_MSI_Clock_Range
mbed_official	181:a4cbdfbbd2f4	233	* @{
mbed_official	181:a4cbdfbbd2f4	234	*/
mbed_official	181:a4cbdfbbd2f4	235
mbed_official	181:a4cbdfbbd2f4	236	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
mbed_official	181:a4cbdfbbd2f4	237	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
mbed_official	181:a4cbdfbbd2f4	238	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
mbed_official	181:a4cbdfbbd2f4	239	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
mbed_official	181:a4cbdfbbd2f4	240	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
mbed_official	181:a4cbdfbbd2f4	241	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
mbed_official	181:a4cbdfbbd2f4	242	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
mbed_official	181:a4cbdfbbd2f4	243
mbed_official	181:a4cbdfbbd2f4	244	#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRANGE_0) \|\| \
mbed_official	181:a4cbdfbbd2f4	245	((RANGE) == RCC_MSIRANGE_1) \|\| \
mbed_official	181:a4cbdfbbd2f4	246	((RANGE) == RCC_MSIRANGE_2) \|\| \
mbed_official	181:a4cbdfbbd2f4	247	((RANGE) == RCC_MSIRANGE_3) \|\| \
mbed_official	181:a4cbdfbbd2f4	248	((RANGE) == RCC_MSIRANGE_4) \|\| \
mbed_official	181:a4cbdfbbd2f4	249	((RANGE) == RCC_MSIRANGE_5) \|\| \
mbed_official	181:a4cbdfbbd2f4	250	((RANGE) == RCC_MSIRANGE_6))
mbed_official	181:a4cbdfbbd2f4	251
mbed_official	181:a4cbdfbbd2f4	252	/**
mbed_official	181:a4cbdfbbd2f4	253	* @}
mbed_official	181:a4cbdfbbd2f4	254	*/
mbed_official	181:a4cbdfbbd2f4	255
mbed_official	181:a4cbdfbbd2f4	256	/** @defgroup RCC_LSI_Config
mbed_official	181:a4cbdfbbd2f4	257	* @{
mbed_official	181:a4cbdfbbd2f4	258	*/
mbed_official	181:a4cbdfbbd2f4	259	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	181:a4cbdfbbd2f4	260	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	181:a4cbdfbbd2f4	261
mbed_official	181:a4cbdfbbd2f4	262	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
mbed_official	181:a4cbdfbbd2f4	263	/**
mbed_official	181:a4cbdfbbd2f4	264	* @}
mbed_official	181:a4cbdfbbd2f4	265	*/
mbed_official	181:a4cbdfbbd2f4	266
mbed_official	181:a4cbdfbbd2f4	267
mbed_official	181:a4cbdfbbd2f4	268	/** @defgroup RCC_MSI_Config
mbed_official	181:a4cbdfbbd2f4	269	* @{
mbed_official	181:a4cbdfbbd2f4	270	*/
mbed_official	181:a4cbdfbbd2f4	271	#define RCC_MSI_OFF ((uint8_t)0x00)
mbed_official	181:a4cbdfbbd2f4	272	#define RCC_MSI_ON ((uint8_t)0x01)
mbed_official	181:a4cbdfbbd2f4	273
mbed_official	181:a4cbdfbbd2f4	274	#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_OFF) \|\| ((MSI) == RCC_MSI_ON))
mbed_official	181:a4cbdfbbd2f4	275	/**
mbed_official	181:a4cbdfbbd2f4	276	* @}
mbed_official	181:a4cbdfbbd2f4	277	*/
mbed_official	181:a4cbdfbbd2f4	278
mbed_official	181:a4cbdfbbd2f4	279	/** @defgroup RCC_HSI48_Config
mbed_official	181:a4cbdfbbd2f4	280	* @{
mbed_official	181:a4cbdfbbd2f4	281	*/
mbed_official	181:a4cbdfbbd2f4	282	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	181:a4cbdfbbd2f4	283	#define RCC_HSI48_ON ((uint8_t)0x01)
mbed_official	181:a4cbdfbbd2f4	284
mbed_official	181:a4cbdfbbd2f4	285	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
mbed_official	181:a4cbdfbbd2f4	286	/**
mbed_official	181:a4cbdfbbd2f4	287	* @}
mbed_official	181:a4cbdfbbd2f4	288	*/
mbed_official	181:a4cbdfbbd2f4	289
mbed_official	181:a4cbdfbbd2f4	290	/** @defgroup RCC_PLL_Config
mbed_official	181:a4cbdfbbd2f4	291	* @{
mbed_official	181:a4cbdfbbd2f4	292	*/
mbed_official	181:a4cbdfbbd2f4	293	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	181:a4cbdfbbd2f4	294	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	181:a4cbdfbbd2f4	295	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	181:a4cbdfbbd2f4	296
mbed_official	181:a4cbdfbbd2f4	297	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
mbed_official	181:a4cbdfbbd2f4	298	/**
mbed_official	181:a4cbdfbbd2f4	299	* @}
mbed_official	181:a4cbdfbbd2f4	300	*/
mbed_official	181:a4cbdfbbd2f4	301
mbed_official	181:a4cbdfbbd2f4	302	/** @defgroup RCC_PLL_Clock_Source
mbed_official	181:a4cbdfbbd2f4	303	* @{
mbed_official	181:a4cbdfbbd2f4	304	*/
mbed_official	181:a4cbdfbbd2f4	305	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
mbed_official	181:a4cbdfbbd2f4	306	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
mbed_official	181:a4cbdfbbd2f4	307
mbed_official	181:a4cbdfbbd2f4	308	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	309	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	181:a4cbdfbbd2f4	310
mbed_official	181:a4cbdfbbd2f4	311	/**
mbed_official	181:a4cbdfbbd2f4	312	* @}
mbed_official	181:a4cbdfbbd2f4	313	*/
mbed_official	181:a4cbdfbbd2f4	314
mbed_official	181:a4cbdfbbd2f4	315	/** @defgroup RCC_PLLMultiplication_Factor
mbed_official	181:a4cbdfbbd2f4	316	* @{
mbed_official	181:a4cbdfbbd2f4	317	*/
mbed_official	181:a4cbdfbbd2f4	318
mbed_official	181:a4cbdfbbd2f4	319	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
mbed_official	181:a4cbdfbbd2f4	320	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
mbed_official	181:a4cbdfbbd2f4	321	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
mbed_official	181:a4cbdfbbd2f4	322	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
mbed_official	181:a4cbdfbbd2f4	323	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
mbed_official	181:a4cbdfbbd2f4	324	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
mbed_official	181:a4cbdfbbd2f4	325	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
mbed_official	181:a4cbdfbbd2f4	326	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
mbed_official	181:a4cbdfbbd2f4	327	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
mbed_official	181:a4cbdfbbd2f4	328	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMUL_3) \|\| ((MUL) == RCC_PLLMUL_4) \|\| \
mbed_official	181:a4cbdfbbd2f4	329	((MUL) == RCC_PLLMUL_6) \|\| ((MUL) == RCC_PLLMUL_8) \|\| \
mbed_official	181:a4cbdfbbd2f4	330	((MUL) == RCC_PLLMUL_12) \|\| ((MUL) == RCC_PLLMUL_16) \|\| \
mbed_official	181:a4cbdfbbd2f4	331	((MUL) == RCC_PLLMUL_24) \|\| ((MUL) == RCC_PLLMUL_32) \|\| \
mbed_official	181:a4cbdfbbd2f4	332	((MUL) == RCC_PLLMUL_48))
mbed_official	181:a4cbdfbbd2f4	333	/**
mbed_official	181:a4cbdfbbd2f4	334	* @}
mbed_official	181:a4cbdfbbd2f4	335	*/
mbed_official	181:a4cbdfbbd2f4	336
mbed_official	181:a4cbdfbbd2f4	337	/** @defgroup RCC_PLLDivider_Factor
mbed_official	181:a4cbdfbbd2f4	338	* @{
mbed_official	181:a4cbdfbbd2f4	339	*/
mbed_official	181:a4cbdfbbd2f4	340
mbed_official	181:a4cbdfbbd2f4	341	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
mbed_official	181:a4cbdfbbd2f4	342	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
mbed_official	181:a4cbdfbbd2f4	343	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
mbed_official	181:a4cbdfbbd2f4	344	#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDIV_2) \|\| ((DIV) == RCC_PLLDIV_3) \|\| \
mbed_official	181:a4cbdfbbd2f4	345	((DIV) == RCC_PLLDIV_4))
mbed_official	181:a4cbdfbbd2f4	346	/**
mbed_official	181:a4cbdfbbd2f4	347	* @}
mbed_official	181:a4cbdfbbd2f4	348	*/
mbed_official	181:a4cbdfbbd2f4	349
mbed_official	181:a4cbdfbbd2f4	350	/** @defgroup RCC_System_Clock_Type
mbed_official	181:a4cbdfbbd2f4	351	* @{
mbed_official	181:a4cbdfbbd2f4	352	*/
mbed_official	181:a4cbdfbbd2f4	353	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	181:a4cbdfbbd2f4	354	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	181:a4cbdfbbd2f4	355	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	181:a4cbdfbbd2f4	356	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	181:a4cbdfbbd2f4	357
mbed_official	181:a4cbdfbbd2f4	358	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
mbed_official	181:a4cbdfbbd2f4	359	/**
mbed_official	181:a4cbdfbbd2f4	360	* @}
mbed_official	181:a4cbdfbbd2f4	361	*/
mbed_official	181:a4cbdfbbd2f4	362
mbed_official	181:a4cbdfbbd2f4	363	/** @defgroup RCC_System_Clock_Source
mbed_official	181:a4cbdfbbd2f4	364	* @{
mbed_official	181:a4cbdfbbd2f4	365	*/
mbed_official	181:a4cbdfbbd2f4	366	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
mbed_official	181:a4cbdfbbd2f4	367	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	181:a4cbdfbbd2f4	368	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	181:a4cbdfbbd2f4	369	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	181:a4cbdfbbd2f4	370
mbed_official	181:a4cbdfbbd2f4	371	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	372	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	181:a4cbdfbbd2f4	373	((SOURCE) == RCC_SYSCLKSOURCE_MSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	374	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	181:a4cbdfbbd2f4	375	/**
mbed_official	181:a4cbdfbbd2f4	376	* @}
mbed_official	181:a4cbdfbbd2f4	377	*/
mbed_official	181:a4cbdfbbd2f4	378
mbed_official	181:a4cbdfbbd2f4	379	/** @defgroup RCC_AHB_Clock_Source
mbed_official	181:a4cbdfbbd2f4	380	* @{
mbed_official	181:a4cbdfbbd2f4	381	*/
mbed_official	181:a4cbdfbbd2f4	382	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	181:a4cbdfbbd2f4	383	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	181:a4cbdfbbd2f4	384	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	181:a4cbdfbbd2f4	385	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	181:a4cbdfbbd2f4	386	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	181:a4cbdfbbd2f4	387	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	181:a4cbdfbbd2f4	388	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	181:a4cbdfbbd2f4	389	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	181:a4cbdfbbd2f4	390	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	181:a4cbdfbbd2f4	391
mbed_official	181:a4cbdfbbd2f4	392	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	393	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	181:a4cbdfbbd2f4	394	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	181:a4cbdfbbd2f4	395	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	181:a4cbdfbbd2f4	396	((HCLK) == RCC_SYSCLK_DIV512))
mbed_official	181:a4cbdfbbd2f4	397	/**
mbed_official	181:a4cbdfbbd2f4	398	* @}
mbed_official	181:a4cbdfbbd2f4	399	*/
mbed_official	181:a4cbdfbbd2f4	400
mbed_official	181:a4cbdfbbd2f4	401	/** @defgroup RCC_APB1_APB2_Clock_Source
mbed_official	181:a4cbdfbbd2f4	402	* @{
mbed_official	181:a4cbdfbbd2f4	403	*/
mbed_official	181:a4cbdfbbd2f4	404	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official	181:a4cbdfbbd2f4	405	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official	181:a4cbdfbbd2f4	406	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official	181:a4cbdfbbd2f4	407	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official	181:a4cbdfbbd2f4	408	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official	181:a4cbdfbbd2f4	409
mbed_official	181:a4cbdfbbd2f4	410	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	411	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
mbed_official	181:a4cbdfbbd2f4	412	((PCLK) == RCC_HCLK_DIV16))
mbed_official	181:a4cbdfbbd2f4	413	/**
mbed_official	181:a4cbdfbbd2f4	414	* @}
mbed_official	181:a4cbdfbbd2f4	415	*/
mbed_official	181:a4cbdfbbd2f4	416
mbed_official	181:a4cbdfbbd2f4	417	/** @defgroup RCC_RTC_Clock_Source
mbed_official	181:a4cbdfbbd2f4	418	* @{
mbed_official	181:a4cbdfbbd2f4	419	*/
mbed_official	181:a4cbdfbbd2f4	420	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
mbed_official	181:a4cbdfbbd2f4	421	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
mbed_official	181:a4cbdfbbd2f4	422	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
mbed_official	181:a4cbdfbbd2f4	423	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
mbed_official	181:a4cbdfbbd2f4	424	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
mbed_official	181:a4cbdfbbd2f4	425	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
mbed_official	181:a4cbdfbbd2f4	426	#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	181:a4cbdfbbd2f4	427	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	428	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	429	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
mbed_official	181:a4cbdfbbd2f4	430	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
mbed_official	181:a4cbdfbbd2f4	431	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16))
mbed_official	181:a4cbdfbbd2f4	432	/**
mbed_official	181:a4cbdfbbd2f4	433	* @}
mbed_official	181:a4cbdfbbd2f4	434	*/
mbed_official	181:a4cbdfbbd2f4	435
mbed_official	181:a4cbdfbbd2f4	436	/** @defgroup RCC_MCO_Clock_Source
mbed_official	181:a4cbdfbbd2f4	437	* @{
mbed_official	181:a4cbdfbbd2f4	438	*/
mbed_official	181:a4cbdfbbd2f4	439	#define RCC_MCO1SOURCE_NOCLOCK ((uint8_t)0x00)
mbed_official	181:a4cbdfbbd2f4	440	#define RCC_MCO1SOURCE_SYSCLK ((uint8_t)0x01)
mbed_official	181:a4cbdfbbd2f4	441	#define RCC_MCO1SOURCE_HSI ((uint8_t)0x02)
mbed_official	181:a4cbdfbbd2f4	442	#define RCC_MCO1SOURCE_MSI ((uint8_t)0x03)
mbed_official	181:a4cbdfbbd2f4	443	#define RCC_MCO1SOURCE_HSE ((uint8_t)0x04)
mbed_official	181:a4cbdfbbd2f4	444	#define RCC_MCO1SOURCE_PLLCLK ((uint8_t)0x05)
mbed_official	181:a4cbdfbbd2f4	445	#define RCC_MCO1SOURCE_LSI ((uint8_t)0x06)
mbed_official	181:a4cbdfbbd2f4	446	#define RCC_MCO1SOURCE_LSE ((uint8_t)0x07)
mbed_official	181:a4cbdfbbd2f4	447	#define RCC_MCO1SOURCE_HSI48 ((uint8_t)0x08)
mbed_official	181:a4cbdfbbd2f4	448
mbed_official	181:a4cbdfbbd2f4	449	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	181:a4cbdfbbd2f4	450	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	181:a4cbdfbbd2f4	451	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	181:a4cbdfbbd2f4	452	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	181:a4cbdfbbd2f4	453	((SOURCE) == RCC_MCO1SOURCE_HSI48))
mbed_official	181:a4cbdfbbd2f4	454	/**
mbed_official	181:a4cbdfbbd2f4	455	* @}
mbed_official	181:a4cbdfbbd2f4	456	*/
mbed_official	181:a4cbdfbbd2f4	457
mbed_official	181:a4cbdfbbd2f4	458	/** @defgroup RCC_MCOPrescaler
mbed_official	181:a4cbdfbbd2f4	459	* @{
mbed_official	181:a4cbdfbbd2f4	460	*/
mbed_official	181:a4cbdfbbd2f4	461
mbed_official	181:a4cbdfbbd2f4	462	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
mbed_official	181:a4cbdfbbd2f4	463	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
mbed_official	181:a4cbdfbbd2f4	464	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
mbed_official	181:a4cbdfbbd2f4	465	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
mbed_official	181:a4cbdfbbd2f4	466	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
mbed_official	181:a4cbdfbbd2f4	467
mbed_official	181:a4cbdfbbd2f4	468	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| \
mbed_official	181:a4cbdfbbd2f4	469	((DIV) == RCC_MCODIV_2) \|\| \
mbed_official	181:a4cbdfbbd2f4	470	((DIV) == RCC_MCODIV_4) \|\| \
mbed_official	181:a4cbdfbbd2f4	471	((DIV) == RCC_MCODIV_8) \|\| \
mbed_official	181:a4cbdfbbd2f4	472	((DIV) == RCC_MCODIV_16))
mbed_official	181:a4cbdfbbd2f4	473	/**
mbed_official	181:a4cbdfbbd2f4	474	* @}
mbed_official	181:a4cbdfbbd2f4	475	*/
mbed_official	181:a4cbdfbbd2f4	476
mbed_official	181:a4cbdfbbd2f4	477	/** @defgroup RCC_MCO_Index
mbed_official	181:a4cbdfbbd2f4	478	* @{
mbed_official	181:a4cbdfbbd2f4	479	*/
mbed_official	181:a4cbdfbbd2f4	480	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	181:a4cbdfbbd2f4	481	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	181:a4cbdfbbd2f4	482
mbed_official	181:a4cbdfbbd2f4	483	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
mbed_official	181:a4cbdfbbd2f4	484	/**
mbed_official	181:a4cbdfbbd2f4	485	* @}
mbed_official	181:a4cbdfbbd2f4	486	*/
mbed_official	181:a4cbdfbbd2f4	487
mbed_official	181:a4cbdfbbd2f4	488	/** @defgroup RCC_Interrupt
mbed_official	181:a4cbdfbbd2f4	489	* @{
mbed_official	181:a4cbdfbbd2f4	490	*/
mbed_official	181:a4cbdfbbd2f4	491	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
mbed_official	181:a4cbdfbbd2f4	492	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
mbed_official	181:a4cbdfbbd2f4	493	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
mbed_official	181:a4cbdfbbd2f4	494	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
mbed_official	181:a4cbdfbbd2f4	495	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
mbed_official	181:a4cbdfbbd2f4	496	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
mbed_official	181:a4cbdfbbd2f4	497	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
mbed_official	181:a4cbdfbbd2f4	498	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
mbed_official	181:a4cbdfbbd2f4	499	#define RCC_IT_CSS RCC_CIFR_CSSF
mbed_official	181:a4cbdfbbd2f4	500
mbed_official	181:a4cbdfbbd2f4	501	#define IS_RCC_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	502	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	503	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	504	((IT) == RCC_IT_HSI48RDY) \|\| ((IT) == RCC_IT_LSECSS))
mbed_official	181:a4cbdfbbd2f4	505
mbed_official	181:a4cbdfbbd2f4	506	#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	507	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	508	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	509	((IT) == RCC_IT_CSS) \|\| ((IT) == RCC_IT_HSI48RDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	510	((IT) == RCC_IT_LSECSS))
mbed_official	181:a4cbdfbbd2f4	511
mbed_official	181:a4cbdfbbd2f4	512	#define IS_RCC_CLEAR_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	513	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	514	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	515	((IT) == RCC_IT_CSS) \|\| ((IT) == RCC_IT_HSI48RDY) \|\| \
mbed_official	181:a4cbdfbbd2f4	516	((IT) == RCC_IT_LSECSS))
mbed_official	181:a4cbdfbbd2f4	517
mbed_official	181:a4cbdfbbd2f4	518	/**
mbed_official	181:a4cbdfbbd2f4	519	* @}
mbed_official	181:a4cbdfbbd2f4	520	*/
mbed_official	181:a4cbdfbbd2f4	521
mbed_official	181:a4cbdfbbd2f4	522	/** @defgroup RCC_Flag
mbed_official	181:a4cbdfbbd2f4	523	* Elements values convention: 0XXYYYYYb
mbed_official	181:a4cbdfbbd2f4	524	* - YYYYY : Flag position in the register
mbed_official	181:a4cbdfbbd2f4	525	* - 0XX : Register index
mbed_official	181:a4cbdfbbd2f4	526	* - 01: CR register
mbed_official	181:a4cbdfbbd2f4	527	* - 10: CSR register
mbed_official	181:a4cbdfbbd2f4	528	* - 11: CRRCR register
mbed_official	181:a4cbdfbbd2f4	529	* @{
mbed_official	181:a4cbdfbbd2f4	530	*/
mbed_official	181:a4cbdfbbd2f4	531	/* Flags in the CR register */
mbed_official	181:a4cbdfbbd2f4	532	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
mbed_official	181:a4cbdfbbd2f4	533	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
mbed_official	181:a4cbdfbbd2f4	534	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
mbed_official	181:a4cbdfbbd2f4	535	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official	181:a4cbdfbbd2f4	536	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official	181:a4cbdfbbd2f4	537
mbed_official	181:a4cbdfbbd2f4	538	/* Flags in the CSR register */
mbed_official	181:a4cbdfbbd2f4	539	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
mbed_official	181:a4cbdfbbd2f4	540	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
mbed_official	181:a4cbdfbbd2f4	541	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
mbed_official	181:a4cbdfbbd2f4	542	#define RCC_FLAG_FIREWALLRST ((uint8_t)0x58)
mbed_official	181:a4cbdfbbd2f4	543	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
mbed_official	181:a4cbdfbbd2f4	544	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
mbed_official	181:a4cbdfbbd2f4	545	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
mbed_official	181:a4cbdfbbd2f4	546	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
mbed_official	181:a4cbdfbbd2f4	547	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
mbed_official	181:a4cbdfbbd2f4	548	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
mbed_official	181:a4cbdfbbd2f4	549	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
mbed_official	181:a4cbdfbbd2f4	550
mbed_official	181:a4cbdfbbd2f4	551	/* Flags in the CRRCR register */
mbed_official	181:a4cbdfbbd2f4	552	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
mbed_official	181:a4cbdfbbd2f4	553
mbed_official	181:a4cbdfbbd2f4	554
mbed_official	181:a4cbdfbbd2f4	555
mbed_official	181:a4cbdfbbd2f4	556	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official	181:a4cbdfbbd2f4	557	/**
mbed_official	181:a4cbdfbbd2f4	558	* @}
mbed_official	181:a4cbdfbbd2f4	559	*/
mbed_official	181:a4cbdfbbd2f4	560
mbed_official	181:a4cbdfbbd2f4	561	/**
mbed_official	181:a4cbdfbbd2f4	562	* @}
mbed_official	181:a4cbdfbbd2f4	563	*/
mbed_official	181:a4cbdfbbd2f4	564	/* Exported macro ------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	565	/** @defgroup RCC_Exported macro
mbed_official	181:a4cbdfbbd2f4	566	* @{
mbed_official	181:a4cbdfbbd2f4	567	*/
mbed_official	181:a4cbdfbbd2f4	568
mbed_official	181:a4cbdfbbd2f4	569	/** @brief Enable or disable the AHB peripheral clock.
mbed_official	181:a4cbdfbbd2f4	570	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	181:a4cbdfbbd2f4	571	* is disabled and the application software has to enable this clock before
mbed_official	181:a4cbdfbbd2f4	572	* using it.
mbed_official	181:a4cbdfbbd2f4	573	*/
mbed_official	181:a4cbdfbbd2f4	574	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
mbed_official	181:a4cbdfbbd2f4	575	#define __MIF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_MIFEN))
mbed_official	181:a4cbdfbbd2f4	576	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
mbed_official	181:a4cbdfbbd2f4	577
mbed_official	181:a4cbdfbbd2f4	578
mbed_official	181:a4cbdfbbd2f4	579	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
mbed_official	181:a4cbdfbbd2f4	580	#define __MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
mbed_official	181:a4cbdfbbd2f4	581	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
mbed_official	181:a4cbdfbbd2f4	582
mbed_official	181:a4cbdfbbd2f4	583
mbed_official	181:a4cbdfbbd2f4	584	/** @brief Enable or disable the IOPORT peripheral clock.
mbed_official	181:a4cbdfbbd2f4	585	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	181:a4cbdfbbd2f4	586	* is disabled and the application software has to enable this clock before
mbed_official	181:a4cbdfbbd2f4	587	* using it.
mbed_official	181:a4cbdfbbd2f4	588	*/
mbed_official	181:a4cbdfbbd2f4	589	#define __GPIOA_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOAEN))
mbed_official	181:a4cbdfbbd2f4	590	#define __GPIOB_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOBEN))
mbed_official	181:a4cbdfbbd2f4	591	#define __GPIOC_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOCEN))
mbed_official	181:a4cbdfbbd2f4	592	#define __GPIOD_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIODEN))
mbed_official	181:a4cbdfbbd2f4	593	#define __GPIOH_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOHEN))
mbed_official	181:a4cbdfbbd2f4	594
mbed_official	181:a4cbdfbbd2f4	595	#define __GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
mbed_official	181:a4cbdfbbd2f4	596	#define __GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
mbed_official	181:a4cbdfbbd2f4	597	#define __GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
mbed_official	181:a4cbdfbbd2f4	598	#define __GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
mbed_official	181:a4cbdfbbd2f4	599	#define __GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
mbed_official	181:a4cbdfbbd2f4	600
mbed_official	181:a4cbdfbbd2f4	601
mbed_official	181:a4cbdfbbd2f4	602	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	181:a4cbdfbbd2f4	603	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	181:a4cbdfbbd2f4	604	* is disabled and the application software has to enable this clock before
mbed_official	181:a4cbdfbbd2f4	605	* using it.
mbed_official	181:a4cbdfbbd2f4	606	*/
mbed_official	181:a4cbdfbbd2f4	607	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	181:a4cbdfbbd2f4	608	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	181:a4cbdfbbd2f4	609
mbed_official	181:a4cbdfbbd2f4	610	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
mbed_official	181:a4cbdfbbd2f4	611	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
mbed_official	181:a4cbdfbbd2f4	612
mbed_official	181:a4cbdfbbd2f4	613	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	181:a4cbdfbbd2f4	614	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	181:a4cbdfbbd2f4	615	* is disabled and the application software has to enable this clock before
mbed_official	181:a4cbdfbbd2f4	616	* using it.
mbed_official	181:a4cbdfbbd2f4	617	*/
mbed_official	181:a4cbdfbbd2f4	618	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	181:a4cbdfbbd2f4	619	#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
mbed_official	181:a4cbdfbbd2f4	620
mbed_official	181:a4cbdfbbd2f4	621	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
mbed_official	181:a4cbdfbbd2f4	622	#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
mbed_official	181:a4cbdfbbd2f4	623
mbed_official	181:a4cbdfbbd2f4	624	/** @brief Force or release AHB peripheral reset.
mbed_official	181:a4cbdfbbd2f4	625	*/
mbed_official	181:a4cbdfbbd2f4	626	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	181:a4cbdfbbd2f4	627	#define __DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
mbed_official	181:a4cbdfbbd2f4	628	#define __MIF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_MIFRST))
mbed_official	181:a4cbdfbbd2f4	629	#define __CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
mbed_official	181:a4cbdfbbd2f4	630
mbed_official	181:a4cbdfbbd2f4	631	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	181:a4cbdfbbd2f4	632	#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
mbed_official	181:a4cbdfbbd2f4	633	#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
mbed_official	181:a4cbdfbbd2f4	634	#define __MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
mbed_official	181:a4cbdfbbd2f4	635
mbed_official	181:a4cbdfbbd2f4	636
mbed_official	181:a4cbdfbbd2f4	637	/** @brief Force or release IOPORT peripheral reset.
mbed_official	181:a4cbdfbbd2f4	638	*/
mbed_official	181:a4cbdfbbd2f4	639	#define __IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
mbed_official	181:a4cbdfbbd2f4	640	#define __GPIOA_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOARST))
mbed_official	181:a4cbdfbbd2f4	641	#define __GPIOB_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOBRST))
mbed_official	181:a4cbdfbbd2f4	642	#define __GPIOC_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOCRST))
mbed_official	181:a4cbdfbbd2f4	643	#define __GPIOD_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIODRST))
mbed_official	181:a4cbdfbbd2f4	644	#define __GPIOH_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOHRST))
mbed_official	181:a4cbdfbbd2f4	645
mbed_official	181:a4cbdfbbd2f4	646	#define __IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
mbed_official	181:a4cbdfbbd2f4	647	#define __GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
mbed_official	181:a4cbdfbbd2f4	648	#define __GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
mbed_official	181:a4cbdfbbd2f4	649	#define __GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
mbed_official	181:a4cbdfbbd2f4	650	#define __GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
mbed_official	181:a4cbdfbbd2f4	651	#define __GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
mbed_official	181:a4cbdfbbd2f4	652
mbed_official	181:a4cbdfbbd2f4	653	/** @brief Force or release APB1 peripheral reset.
mbed_official	181:a4cbdfbbd2f4	654	*/
mbed_official	181:a4cbdfbbd2f4	655	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	181:a4cbdfbbd2f4	656	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	181:a4cbdfbbd2f4	657	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	181:a4cbdfbbd2f4	658
mbed_official	181:a4cbdfbbd2f4	659	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	181:a4cbdfbbd2f4	660	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
mbed_official	181:a4cbdfbbd2f4	661	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
mbed_official	181:a4cbdfbbd2f4	662
mbed_official	181:a4cbdfbbd2f4	663	/** @brief Force or release APB2 peripheral reset.
mbed_official	181:a4cbdfbbd2f4	664	*/
mbed_official	181:a4cbdfbbd2f4	665	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	181:a4cbdfbbd2f4	666	#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
mbed_official	181:a4cbdfbbd2f4	667	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	181:a4cbdfbbd2f4	668
mbed_official	181:a4cbdfbbd2f4	669	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	181:a4cbdfbbd2f4	670	#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
mbed_official	181:a4cbdfbbd2f4	671	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
mbed_official	181:a4cbdfbbd2f4	672
mbed_official	181:a4cbdfbbd2f4	673	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
mbed_official	181:a4cbdfbbd2f4	674	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	181:a4cbdfbbd2f4	675	* power consumption.
mbed_official	181:a4cbdfbbd2f4	676	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	181:a4cbdfbbd2f4	677	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	181:a4cbdfbbd2f4	678	*/
mbed_official	181:a4cbdfbbd2f4	679	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_CRCSMEN))
mbed_official	181:a4cbdfbbd2f4	680	#define __MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_MIFSMEN))
mbed_official	181:a4cbdfbbd2f4	681	#define __SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_SRAMSMEN))
mbed_official	181:a4cbdfbbd2f4	682	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_DMA1SMEN))
mbed_official	181:a4cbdfbbd2f4	683
mbed_official	181:a4cbdfbbd2f4	684	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
mbed_official	181:a4cbdfbbd2f4	685	#define __MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
mbed_official	181:a4cbdfbbd2f4	686	#define __SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
mbed_official	181:a4cbdfbbd2f4	687	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
mbed_official	181:a4cbdfbbd2f4	688
mbed_official	181:a4cbdfbbd2f4	689	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
mbed_official	181:a4cbdfbbd2f4	690	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	181:a4cbdfbbd2f4	691	* power consumption.
mbed_official	181:a4cbdfbbd2f4	692	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	181:a4cbdfbbd2f4	693	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	181:a4cbdfbbd2f4	694	*/
mbed_official	181:a4cbdfbbd2f4	695
mbed_official	181:a4cbdfbbd2f4	696	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOASMEN))
mbed_official	181:a4cbdfbbd2f4	697	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOBSMEN))
mbed_official	181:a4cbdfbbd2f4	698	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOCSMEN))
mbed_official	181:a4cbdfbbd2f4	699	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIODSMEN))
mbed_official	181:a4cbdfbbd2f4	700	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOHSMEN))
mbed_official	181:a4cbdfbbd2f4	701
mbed_official	181:a4cbdfbbd2f4	702	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
mbed_official	181:a4cbdfbbd2f4	703	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
mbed_official	181:a4cbdfbbd2f4	704	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
mbed_official	181:a4cbdfbbd2f4	705	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
mbed_official	181:a4cbdfbbd2f4	706	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
mbed_official	181:a4cbdfbbd2f4	707
mbed_official	181:a4cbdfbbd2f4	708	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	181:a4cbdfbbd2f4	709	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	181:a4cbdfbbd2f4	710	* power consumption.
mbed_official	181:a4cbdfbbd2f4	711	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	181:a4cbdfbbd2f4	712	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	181:a4cbdfbbd2f4	713	*/
mbed_official	181:a4cbdfbbd2f4	714	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_WWDGSMEN))
mbed_official	181:a4cbdfbbd2f4	715	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_PWRSMEN))
mbed_official	181:a4cbdfbbd2f4	716
mbed_official	181:a4cbdfbbd2f4	717	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
mbed_official	181:a4cbdfbbd2f4	718	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
mbed_official	181:a4cbdfbbd2f4	719
mbed_official	181:a4cbdfbbd2f4	720	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	181:a4cbdfbbd2f4	721	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	181:a4cbdfbbd2f4	722	* power consumption.
mbed_official	181:a4cbdfbbd2f4	723	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	181:a4cbdfbbd2f4	724	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	181:a4cbdfbbd2f4	725	*/
mbed_official	181:a4cbdfbbd2f4	726	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	181:a4cbdfbbd2f4	727	#define __DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	181:a4cbdfbbd2f4	728
mbed_official	181:a4cbdfbbd2f4	729	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	181:a4cbdfbbd2f4	730	#define __DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	181:a4cbdfbbd2f4	731
mbed_official	181:a4cbdfbbd2f4	732	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	181:a4cbdfbbd2f4	733	* @note After enabling the HSI, the application software should wait on
mbed_official	181:a4cbdfbbd2f4	734	* HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official	181:a4cbdfbbd2f4	735	* be used to clock the PLL and/or system clock.
mbed_official	181:a4cbdfbbd2f4	736	* @note HSI can not be stopped if it is used directly or through the PLL
mbed_official	181:a4cbdfbbd2f4	737	* as system clock. In this case, you have to select another source
mbed_official	181:a4cbdfbbd2f4	738	* of the system clock then stop the HSI.
mbed_official	181:a4cbdfbbd2f4	739	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	740	* @param __STATE__: specifies the new state of the HSI.
mbed_official	181:a4cbdfbbd2f4	741	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	742	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
mbed_official	181:a4cbdfbbd2f4	743	* @arg RCC_HSI_ON: turn ON the HSI oscillator
mbed_official	181:a4cbdfbbd2f4	744	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
mbed_official	181:a4cbdfbbd2f4	745	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	181:a4cbdfbbd2f4	746	* clock cycles.
mbed_official	181:a4cbdfbbd2f4	747	*/
mbed_official	181:a4cbdfbbd2f4	748	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
mbed_official	181:a4cbdfbbd2f4	749	MODIFY_REG(RCC->CR, RCC_CR_HSION\|RCC_CR_HSIDIVEN, (uint32_t)(__STATE__))
mbed_official	181:a4cbdfbbd2f4	750
mbed_official	181:a4cbdfbbd2f4	751	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	181:a4cbdfbbd2f4	752	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	753	* It is used (enabled by hardware) as system clock source after startup
mbed_official	181:a4cbdfbbd2f4	754	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	181:a4cbdfbbd2f4	755	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	181:a4cbdfbbd2f4	756	* Security System CSS is enabled).
mbed_official	181:a4cbdfbbd2f4	757	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	181:a4cbdfbbd2f4	758	* you have to select another source of the system clock then stop the HSI.
mbed_official	181:a4cbdfbbd2f4	759	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	181:a4cbdfbbd2f4	760	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	181:a4cbdfbbd2f4	761	* system clock source.
mbed_official	181:a4cbdfbbd2f4	762	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	181:a4cbdfbbd2f4	763	* clock cycles.
mbed_official	181:a4cbdfbbd2f4	764	*/
mbed_official	181:a4cbdfbbd2f4	765	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	181:a4cbdfbbd2f4	766	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	181:a4cbdfbbd2f4	767
mbed_official	181:a4cbdfbbd2f4	768	/**
mbed_official	181:a4cbdfbbd2f4	769	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
mbed_official	181:a4cbdfbbd2f4	770	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	771	* It is used (enabled by hardware) as system clock source after
mbed_official	181:a4cbdfbbd2f4	772	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
mbed_official	181:a4cbdfbbd2f4	773	* of failure of the HSE used directly or indirectly as system clock
mbed_official	181:a4cbdfbbd2f4	774	* (if the Clock Security System CSS is enabled).
mbed_official	181:a4cbdfbbd2f4	775	* @note MSI can not be stopped if it is used as system clock source.
mbed_official	181:a4cbdfbbd2f4	776	* In this case, you have to select another source of the system
mbed_official	181:a4cbdfbbd2f4	777	* clock then stop the MSI.
mbed_official	181:a4cbdfbbd2f4	778	* @note After enabling the MSI, the application software should wait on
mbed_official	181:a4cbdfbbd2f4	779	* MSIRDY flag to be set indicating that MSI clock is stable and can
mbed_official	181:a4cbdfbbd2f4	780	* be used as system clock source.
mbed_official	181:a4cbdfbbd2f4	781	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official	181:a4cbdfbbd2f4	782	* clock cycles.
mbed_official	181:a4cbdfbbd2f4	783	*/
mbed_official	181:a4cbdfbbd2f4	784	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	181:a4cbdfbbd2f4	785	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	181:a4cbdfbbd2f4	786
mbed_official	181:a4cbdfbbd2f4	787	/**
mbed_official	181:a4cbdfbbd2f4	788	* @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
mbed_official	181:a4cbdfbbd2f4	789	* @note After enabling the HSI48, the application software should wait on
mbed_official	181:a4cbdfbbd2f4	790	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
mbed_official	181:a4cbdfbbd2f4	791	* be used to clock the USB.
mbed_official	181:a4cbdfbbd2f4	792	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	793	*/
mbed_official	181:a4cbdfbbd2f4	794	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
mbed_official	181:a4cbdfbbd2f4	795	RCC->APB2ENR \|= RCC_APB2ENR_SYSCFGEN; \
mbed_official	181:a4cbdfbbd2f4	796	SYSCFG->CFGR3 \|= (SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT); \
mbed_official	181:a4cbdfbbd2f4	797	} while (0)
mbed_official	181:a4cbdfbbd2f4	798	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
mbed_official	181:a4cbdfbbd2f4	799	SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT)); \
mbed_official	181:a4cbdfbbd2f4	800	} while (0)
mbed_official	181:a4cbdfbbd2f4	801
mbed_official	181:a4cbdfbbd2f4	802	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	181:a4cbdfbbd2f4	803	* @note The calibration is used to compensate for the variations in voltage
mbed_official	181:a4cbdfbbd2f4	804	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	181:a4cbdfbbd2f4	805	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	181:a4cbdfbbd2f4	806	* This parameter must be a number between 0 and 0x1F.
mbed_official	181:a4cbdfbbd2f4	807	*/
mbed_official	181:a4cbdfbbd2f4	808	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	181:a4cbdfbbd2f4	809	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
mbed_official	181:a4cbdfbbd2f4	810
mbed_official	181:a4cbdfbbd2f4	811	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official	181:a4cbdfbbd2f4	812	* @note The calibration is used to compensate for the variations in voltage
mbed_official	181:a4cbdfbbd2f4	813	* and temperature that influence the frequency of the internal MSI RC.
mbed_official	181:a4cbdfbbd2f4	814	* Refer to the Application Note AN3300 for more details on how to
mbed_official	181:a4cbdfbbd2f4	815	* calibrate the MSI.
mbed_official	181:a4cbdfbbd2f4	816	* @param __MSICalibrationValue__: specifies the calibration trimming value.
mbed_official	181:a4cbdfbbd2f4	817	* This parameter must be a number between 0 and 0xFF.
mbed_official	181:a4cbdfbbd2f4	818	*/
mbed_official	181:a4cbdfbbd2f4	819	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	181:a4cbdfbbd2f4	820	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
mbed_official	181:a4cbdfbbd2f4	821
mbed_official	181:a4cbdfbbd2f4	822	/**
mbed_official	181:a4cbdfbbd2f4	823	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
mbed_official	181:a4cbdfbbd2f4	824	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
mbed_official	181:a4cbdfbbd2f4	825	* around 2.097 MHz. The MSI clock does not change after wake-up from
mbed_official	181:a4cbdfbbd2f4	826	* STOP mode.
mbed_official	181:a4cbdfbbd2f4	827	* @note The MSI clock range can be modified on the fly.
mbed_official	181:a4cbdfbbd2f4	828	* @param RCC_MSIRange: specifies the MSI Clock range.
mbed_official	181:a4cbdfbbd2f4	829	* This parameter must be one of the following values:
mbed_official	181:a4cbdfbbd2f4	830	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
mbed_official	181:a4cbdfbbd2f4	831	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
mbed_official	181:a4cbdfbbd2f4	832	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
mbed_official	181:a4cbdfbbd2f4	833	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
mbed_official	181:a4cbdfbbd2f4	834	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
mbed_official	181:a4cbdfbbd2f4	835	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official	181:a4cbdfbbd2f4	836	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
mbed_official	181:a4cbdfbbd2f4	837	*/
mbed_official	181:a4cbdfbbd2f4	838	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	181:a4cbdfbbd2f4	839	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
mbed_official	181:a4cbdfbbd2f4	840
mbed_official	181:a4cbdfbbd2f4	841	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	181:a4cbdfbbd2f4	842	* @note After enabling the LSI, the application software should wait on
mbed_official	181:a4cbdfbbd2f4	843	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	181:a4cbdfbbd2f4	844	* be used to clock the IWDG and/or the RTC.
mbed_official	181:a4cbdfbbd2f4	845	* @note LSI can not be disabled if the IWDG is running.
mbed_official	181:a4cbdfbbd2f4	846	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	181:a4cbdfbbd2f4	847	* clock cycles.
mbed_official	181:a4cbdfbbd2f4	848	*/
mbed_official	181:a4cbdfbbd2f4	849	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	181:a4cbdfbbd2f4	850	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	181:a4cbdfbbd2f4	851
mbed_official	181:a4cbdfbbd2f4	852	/**
mbed_official	181:a4cbdfbbd2f4	853	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	181:a4cbdfbbd2f4	854	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	181:a4cbdfbbd2f4	855	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	181:a4cbdfbbd2f4	856	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	181:a4cbdfbbd2f4	857	* @note HSE state can not be changed if it is used directly or through the
mbed_official	181:a4cbdfbbd2f4	858	* PLL as system clock. In this case, you have to select another source
mbed_official	181:a4cbdfbbd2f4	859	* of the system clock then change the HSE state (ex. disable it).
mbed_official	181:a4cbdfbbd2f4	860	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	861	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	181:a4cbdfbbd2f4	862	* was previously enabled you have to enable it again after calling this
mbed_official	181:a4cbdfbbd2f4	863	* function.
mbed_official	181:a4cbdfbbd2f4	864	* @param __STATE__: specifies the new state of the HSE.
mbed_official	181:a4cbdfbbd2f4	865	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	866	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	181:a4cbdfbbd2f4	867	* 6 HSE oscillator clock cycles.
mbed_official	181:a4cbdfbbd2f4	868	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	181:a4cbdfbbd2f4	869	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	181:a4cbdfbbd2f4	870	*/
mbed_official	181:a4cbdfbbd2f4	871	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	181:a4cbdfbbd2f4	872	MODIFY_REG(RCC->CR, RCC_CR_HSEON\|RCC_CR_HSEBYP, (uint32_t)(__STATE__))
mbed_official	181:a4cbdfbbd2f4	873
mbed_official	181:a4cbdfbbd2f4	874	/**
mbed_official	181:a4cbdfbbd2f4	875	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	181:a4cbdfbbd2f4	876	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	181:a4cbdfbbd2f4	877	* this domain after reset, you have to enable write access using
mbed_official	181:a4cbdfbbd2f4	878	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	181:a4cbdfbbd2f4	879	* (to be done once after reset).
mbed_official	181:a4cbdfbbd2f4	880	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	181:a4cbdfbbd2f4	881	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	181:a4cbdfbbd2f4	882	* is stable and can be used to clock the RTC.
mbed_official	181:a4cbdfbbd2f4	883	* @param __STATE__: specifies the new state of the LSE.
mbed_official	181:a4cbdfbbd2f4	884	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	885	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	181:a4cbdfbbd2f4	886	* 6 LSE oscillator clock cycles.
mbed_official	181:a4cbdfbbd2f4	887	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	181:a4cbdfbbd2f4	888	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	181:a4cbdfbbd2f4	889	*/
mbed_official	181:a4cbdfbbd2f4	890	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	181:a4cbdfbbd2f4	891	MODIFY_REG(RCC->CSR, RCC_CSR_LSEON\|RCC_CSR_LSEBYP, (uint32_t)(__STATE__))
mbed_official	181:a4cbdfbbd2f4	892
mbed_official	181:a4cbdfbbd2f4	893	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	181:a4cbdfbbd2f4	894	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	181:a4cbdfbbd2f4	895	*/
mbed_official	181:a4cbdfbbd2f4	896	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	181:a4cbdfbbd2f4	897	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	181:a4cbdfbbd2f4	898
mbed_official	181:a4cbdfbbd2f4	899	/**
mbed_official	181:a4cbdfbbd2f4	900	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
mbed_official	181:a4cbdfbbd2f4	901	* @note As the RTC clock configuration bits are in the RTC domain and write
mbed_official	181:a4cbdfbbd2f4	902	* access is denied to this domain after reset, you have to enable write
mbed_official	181:a4cbdfbbd2f4	903	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
mbed_official	181:a4cbdfbbd2f4	904	* the RTC clock source (to be done once after reset).
mbed_official	181:a4cbdfbbd2f4	905	* @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official	181:a4cbdfbbd2f4	906	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
mbed_official	181:a4cbdfbbd2f4	907	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
mbed_official	181:a4cbdfbbd2f4	908	*
mbed_official	181:a4cbdfbbd2f4	909	* @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official	181:a4cbdfbbd2f4	910	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	911	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	181:a4cbdfbbd2f4	912	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	181:a4cbdfbbd2f4	913	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
mbed_official	181:a4cbdfbbd2f4	914	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
mbed_official	181:a4cbdfbbd2f4	915	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
mbed_official	181:a4cbdfbbd2f4	916	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
mbed_official	181:a4cbdfbbd2f4	917	*
mbed_official	181:a4cbdfbbd2f4	918	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	181:a4cbdfbbd2f4	919	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	181:a4cbdfbbd2f4	920	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	181:a4cbdfbbd2f4	921	* cannot be used in STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	922	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	181:a4cbdfbbd2f4	923	* RTC clock source).
mbed_official	181:a4cbdfbbd2f4	924	*/
mbed_official	181:a4cbdfbbd2f4	925	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
mbed_official	181:a4cbdfbbd2f4	926	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
mbed_official	181:a4cbdfbbd2f4	927
mbed_official	181:a4cbdfbbd2f4	928	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official	181:a4cbdfbbd2f4	929	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
mbed_official	181:a4cbdfbbd2f4	930	} while (0)
mbed_official	181:a4cbdfbbd2f4	931
mbed_official	181:a4cbdfbbd2f4	932	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CSR_RTCSEL)))
mbed_official	181:a4cbdfbbd2f4	933
mbed_official	181:a4cbdfbbd2f4	934	/** @brief Macros to force or release the Backup domain reset.
mbed_official	181:a4cbdfbbd2f4	935	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	181:a4cbdfbbd2f4	936	* and the RTC clock source selection in RCC_CSR register.
mbed_official	181:a4cbdfbbd2f4	937	* @note The BKPSRAM is not affected by this reset.
mbed_official	181:a4cbdfbbd2f4	938	*/
mbed_official	181:a4cbdfbbd2f4	939	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	181:a4cbdfbbd2f4	940	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	181:a4cbdfbbd2f4	941
mbed_official	181:a4cbdfbbd2f4	942	/** @brief Macros to enable or disable the main PLL.
mbed_official	181:a4cbdfbbd2f4	943	* @note After enabling the main PLL, the application software should wait on
mbed_official	181:a4cbdfbbd2f4	944	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	181:a4cbdfbbd2f4	945	* be used as system clock source.
mbed_official	181:a4cbdfbbd2f4	946	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	181:a4cbdfbbd2f4	947	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	181:a4cbdfbbd2f4	948	*/
mbed_official	181:a4cbdfbbd2f4	949	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	181:a4cbdfbbd2f4	950	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	181:a4cbdfbbd2f4	951
mbed_official	181:a4cbdfbbd2f4	952	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	181:a4cbdfbbd2f4	953	* @note This function must be used only when the main PLL is disabled.
mbed_official	181:a4cbdfbbd2f4	954	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	181:a4cbdfbbd2f4	955	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	956	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	181:a4cbdfbbd2f4	957	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	181:a4cbdfbbd2f4	958	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
mbed_official	181:a4cbdfbbd2f4	959	* This parameter must be one of the following values:
mbed_official	181:a4cbdfbbd2f4	960	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
mbed_official	181:a4cbdfbbd2f4	961	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
mbed_official	181:a4cbdfbbd2f4	962	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
mbed_official	181:a4cbdfbbd2f4	963	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
mbed_official	181:a4cbdfbbd2f4	964	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
mbed_official	181:a4cbdfbbd2f4	965	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
mbed_official	181:a4cbdfbbd2f4	966	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
mbed_official	181:a4cbdfbbd2f4	967	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
mbed_official	181:a4cbdfbbd2f4	968	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
mbed_official	181:a4cbdfbbd2f4	969	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
mbed_official	181:a4cbdfbbd2f4	970	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
mbed_official	181:a4cbdfbbd2f4	971	* in Range 3.
mbed_official	181:a4cbdfbbd2f4	972	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
mbed_official	181:a4cbdfbbd2f4	973	* This parameter must be one of the following values:
mbed_official	181:a4cbdfbbd2f4	974	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
mbed_official	181:a4cbdfbbd2f4	975	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
mbed_official	181:a4cbdfbbd2f4	976	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
mbed_official	181:a4cbdfbbd2f4	977	*/
mbed_official	181:a4cbdfbbd2f4	978
mbed_official	181:a4cbdfbbd2f4	979	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
mbed_official	181:a4cbdfbbd2f4	980	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSource__)))
mbed_official	181:a4cbdfbbd2f4	981
mbed_official	181:a4cbdfbbd2f4	982	/** @brief Macro to get the clock source used as system clock.
mbed_official	181:a4cbdfbbd2f4	983	* @retval The clock source used as system clock. The returned value can be one
mbed_official	181:a4cbdfbbd2f4	984	* of the following:
mbed_official	181:a4cbdfbbd2f4	985	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
mbed_official	181:a4cbdfbbd2f4	986	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
mbed_official	181:a4cbdfbbd2f4	987	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
mbed_official	181:a4cbdfbbd2f4	988	*/
mbed_official	181:a4cbdfbbd2f4	989	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	181:a4cbdfbbd2f4	990
mbed_official	181:a4cbdfbbd2f4	991	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	181:a4cbdfbbd2f4	992	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	181:a4cbdfbbd2f4	993	* of the following:
mbed_official	181:a4cbdfbbd2f4	994	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	181:a4cbdfbbd2f4	995	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	181:a4cbdfbbd2f4	996	*/
mbed_official	181:a4cbdfbbd2f4	997	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
mbed_official	181:a4cbdfbbd2f4	998
mbed_official	181:a4cbdfbbd2f4	999	/** @defgroup RCC_Flags_Interrupts_Management
mbed_official	181:a4cbdfbbd2f4	1000	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	181:a4cbdfbbd2f4	1001	* @{
mbed_official	181:a4cbdfbbd2f4	1002	*/
mbed_official	181:a4cbdfbbd2f4	1003
mbed_official	181:a4cbdfbbd2f4	1004	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
mbed_official	181:a4cbdfbbd2f4	1005	* the selected interrupts).
mbed_official	181:a4cbdfbbd2f4	1006	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	181:a4cbdfbbd2f4	1007	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	181:a4cbdfbbd2f4	1008	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	181:a4cbdfbbd2f4	1009	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	181:a4cbdfbbd2f4	1010	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	181:a4cbdfbbd2f4	1011	* pending bit is cleared.
mbed_official	181:a4cbdfbbd2f4	1012	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	181:a4cbdfbbd2f4	1013	* This parameter can be any combination of the following values:
mbed_official	181:a4cbdfbbd2f4	1014	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1015	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1016	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1017	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1018	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	181:a4cbdfbbd2f4	1019	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1020	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	181:a4cbdfbbd2f4	1021	*/
mbed_official	181:a4cbdfbbd2f4	1022	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIER_BYTE0_ADDRESS \|= (__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	1023
mbed_official	181:a4cbdfbbd2f4	1024	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
mbed_official	181:a4cbdfbbd2f4	1025	* the selected interrupts).
mbed_official	181:a4cbdfbbd2f4	1026	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	181:a4cbdfbbd2f4	1027	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	181:a4cbdfbbd2f4	1028	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	181:a4cbdfbbd2f4	1029	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	181:a4cbdfbbd2f4	1030	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	181:a4cbdfbbd2f4	1031	* pending bit is cleared.
mbed_official	181:a4cbdfbbd2f4	1032	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	181:a4cbdfbbd2f4	1033	* This parameter can be any combination of the following values:
mbed_official	181:a4cbdfbbd2f4	1034	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1035	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1036	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1037	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1038	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	181:a4cbdfbbd2f4	1039	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1040	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	181:a4cbdfbbd2f4	1041	*/
mbed_official	181:a4cbdfbbd2f4	1042	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIER_BYTE0_ADDRESS &= ~(__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	1043
mbed_official	181:a4cbdfbbd2f4	1044	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	181:a4cbdfbbd2f4	1045	* bits to clear the selected interrupt pending bits.
mbed_official	181:a4cbdfbbd2f4	1046	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	181:a4cbdfbbd2f4	1047	* This parameter can be any combination of the following values:
mbed_official	181:a4cbdfbbd2f4	1048	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1049	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1050	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1051	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1052	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	181:a4cbdfbbd2f4	1053	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1054	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	181:a4cbdfbbd2f4	1055	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	181:a4cbdfbbd2f4	1056	*/
mbed_official	181:a4cbdfbbd2f4	1057	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) SET_BIT(RCC->CICR, (__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	1058
mbed_official	181:a4cbdfbbd2f4	1059	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	181:a4cbdfbbd2f4	1060	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	181:a4cbdfbbd2f4	1061	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1062	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1063	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1064	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1065	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	181:a4cbdfbbd2f4	1066	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	181:a4cbdfbbd2f4	1067	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	181:a4cbdfbbd2f4	1068	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	181:a4cbdfbbd2f4	1069	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	181:a4cbdfbbd2f4	1070	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	181:a4cbdfbbd2f4	1071	*/
mbed_official	181:a4cbdfbbd2f4	1072	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	1073
mbed_official	181:a4cbdfbbd2f4	1074	/** @brief Set RMVF bit to clear the reset flags.
mbed_official	181:a4cbdfbbd2f4	1075	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	181:a4cbdfbbd2f4	1076	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
mbed_official	181:a4cbdfbbd2f4	1077	*/
mbed_official	181:a4cbdfbbd2f4	1078	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	181:a4cbdfbbd2f4	1079
mbed_official	181:a4cbdfbbd2f4	1080	/** @brief Check RCC flag is set or not.
mbed_official	181:a4cbdfbbd2f4	1081	* @param __FLAG__: specifies the flag to check.
mbed_official	181:a4cbdfbbd2f4	1082	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1083	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	181:a4cbdfbbd2f4	1084	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
mbed_official	181:a4cbdfbbd2f4	1085	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	181:a4cbdfbbd2f4	1086	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	181:a4cbdfbbd2f4	1087	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
mbed_official	181:a4cbdfbbd2f4	1088	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	181:a4cbdfbbd2f4	1089	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	181:a4cbdfbbd2f4	1090	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official	181:a4cbdfbbd2f4	1091	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	181:a4cbdfbbd2f4	1092	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	181:a4cbdfbbd2f4	1093	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	181:a4cbdfbbd2f4	1094	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	181:a4cbdfbbd2f4	1095	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	181:a4cbdfbbd2f4	1096	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	181:a4cbdfbbd2f4	1097	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	181:a4cbdfbbd2f4	1098	*/
mbed_official	181:a4cbdfbbd2f4	1099	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	181:a4cbdfbbd2f4	1100	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
mbed_official	181:a4cbdfbbd2f4	1101	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
mbed_official	181:a4cbdfbbd2f4	1102
mbed_official	181:a4cbdfbbd2f4	1103	/**
mbed_official	181:a4cbdfbbd2f4	1104	* @}
mbed_official	181:a4cbdfbbd2f4	1105	*/
mbed_official	181:a4cbdfbbd2f4	1106
mbed_official	181:a4cbdfbbd2f4	1107	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
mbed_official	181:a4cbdfbbd2f4	1108	/**
mbed_official	181:a4cbdfbbd2f4	1109	* @}
mbed_official	181:a4cbdfbbd2f4	1110	*/
mbed_official	181:a4cbdfbbd2f4	1111
mbed_official	181:a4cbdfbbd2f4	1112	/* Include RCC HAL Extension module */
mbed_official	181:a4cbdfbbd2f4	1113	#include "stm32L0xx_hal_rcc_ex.h"
mbed_official	181:a4cbdfbbd2f4	1114
mbed_official	181:a4cbdfbbd2f4	1115	/* Exported functions --------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1116	/* Initialization and de-initialization methods ******************************/
mbed_official	181:a4cbdfbbd2f4	1117	void HAL_RCC_DeInit(void);
mbed_official	181:a4cbdfbbd2f4	1118	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	181:a4cbdfbbd2f4	1119	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	181:a4cbdfbbd2f4	1120
mbed_official	181:a4cbdfbbd2f4	1121	/* Peripheral Control methods ************************************************/
mbed_official	181:a4cbdfbbd2f4	1122	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	181:a4cbdfbbd2f4	1123	void HAL_RCC_EnableCSS(void);
mbed_official	181:a4cbdfbbd2f4	1124	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	181:a4cbdfbbd2f4	1125	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	181:a4cbdfbbd2f4	1126	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	181:a4cbdfbbd2f4	1127	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	181:a4cbdfbbd2f4	1128	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	181:a4cbdfbbd2f4	1129	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	181:a4cbdfbbd2f4	1130
mbed_official	181:a4cbdfbbd2f4	1131	/* CSS NMI IRQ handler */
mbed_official	181:a4cbdfbbd2f4	1132	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	181:a4cbdfbbd2f4	1133
mbed_official	181:a4cbdfbbd2f4	1134	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	181:a4cbdfbbd2f4	1135	void HAL_RCC_CCSCallback(void);
mbed_official	181:a4cbdfbbd2f4	1136
mbed_official	181:a4cbdfbbd2f4	1137	/**
mbed_official	181:a4cbdfbbd2f4	1138	* @}
mbed_official	181:a4cbdfbbd2f4	1139	*/
mbed_official	181:a4cbdfbbd2f4	1140
mbed_official	181:a4cbdfbbd2f4	1141	/**
mbed_official	181:a4cbdfbbd2f4	1142	* @}
mbed_official	181:a4cbdfbbd2f4	1143	*/
mbed_official	181:a4cbdfbbd2f4	1144
mbed_official	181:a4cbdfbbd2f4	1145	#ifdef __cplusplus
mbed_official	181:a4cbdfbbd2f4	1146	}
mbed_official	181:a4cbdfbbd2f4	1147	#endif
mbed_official	181:a4cbdfbbd2f4	1148
mbed_official	181:a4cbdfbbd2f4	1149	#endif /* __STM32L0xx_HAL_RCC_H */
mbed_official	181:a4cbdfbbd2f4	1150
mbed_official	181:a4cbdfbbd2f4	1151	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc.h@181:a4cbdfbbd2f4, 2014-05-07 (annotated)

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