shao ziyang / mbed-src-kl05

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_spi.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
181:a4cbdfbbd2f4 
test with CLOCK_SETUP = 0

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UserRevisionLine numberNew contents of line
mbed_official 181:a4cbdfbbd2f4 1 /**
mbed_official 181:a4cbdfbbd2f4 2 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 3 * @file stm32l0xx_hal_spi.h
mbed_official 181:a4cbdfbbd2f4 4 * @author MCD Application Team
mbed_official 181:a4cbdfbbd2f4 5 * @version V1.0.0
mbed_official 181:a4cbdfbbd2f4 6 * @date 22-April-2014
mbed_official 181:a4cbdfbbd2f4 7 * @brief Header file of SPI HAL module.
mbed_official 181:a4cbdfbbd2f4 8 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 9 * @attention
mbed_official 181:a4cbdfbbd2f4 10 *
mbed_official 181:a4cbdfbbd2f4 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 181:a4cbdfbbd2f4 12 *
mbed_official 181:a4cbdfbbd2f4 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 181:a4cbdfbbd2f4 14 * are permitted provided that the following conditions are met:
mbed_official 181:a4cbdfbbd2f4 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 16 * this list of conditions and the following disclaimer.
mbed_official 181:a4cbdfbbd2f4 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 181:a4cbdfbbd2f4 19 * and/or other materials provided with the distribution.
mbed_official 181:a4cbdfbbd2f4 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 181:a4cbdfbbd2f4 21 * may be used to endorse or promote products derived from this software
mbed_official 181:a4cbdfbbd2f4 22 * without specific prior written permission.
mbed_official 181:a4cbdfbbd2f4 23 *
mbed_official 181:a4cbdfbbd2f4 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 181:a4cbdfbbd2f4 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 181:a4cbdfbbd2f4 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 181:a4cbdfbbd2f4 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 181:a4cbdfbbd2f4 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 181:a4cbdfbbd2f4 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 181:a4cbdfbbd2f4 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 181:a4cbdfbbd2f4 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 181:a4cbdfbbd2f4 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 181:a4cbdfbbd2f4 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 181:a4cbdfbbd2f4 34 *
mbed_official 181:a4cbdfbbd2f4 35 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 36 */
mbed_official 181:a4cbdfbbd2f4 37
mbed_official 181:a4cbdfbbd2f4 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 39 #ifndef __STM32L0xx_HAL_SPI_H
mbed_official 181:a4cbdfbbd2f4 40 #define __STM32L0xx_HAL_SPI_H
mbed_official 181:a4cbdfbbd2f4 41
mbed_official 181:a4cbdfbbd2f4 42 #ifdef __cplusplus
mbed_official 181:a4cbdfbbd2f4 43 extern "C" {
mbed_official 181:a4cbdfbbd2f4 44 #endif
mbed_official 181:a4cbdfbbd2f4 45
mbed_official 181:a4cbdfbbd2f4 46 /* Includes ------------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 47 #include "stm32l0xx_hal_def.h"
mbed_official 181:a4cbdfbbd2f4 48
mbed_official 181:a4cbdfbbd2f4 49 /** @addtogroup STM32L0xx_HAL_Driver
mbed_official 181:a4cbdfbbd2f4 50 * @{
mbed_official 181:a4cbdfbbd2f4 51 */
mbed_official 181:a4cbdfbbd2f4 52
mbed_official 181:a4cbdfbbd2f4 53 /** @addtogroup SPI
mbed_official 181:a4cbdfbbd2f4 54 * @{
mbed_official 181:a4cbdfbbd2f4 55 */
mbed_official 181:a4cbdfbbd2f4 56
mbed_official 181:a4cbdfbbd2f4 57 /* Exported types ------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 58
mbed_official 181:a4cbdfbbd2f4 59 /**
mbed_official 181:a4cbdfbbd2f4 60 * @brief SPI Configuration Structure definition
mbed_official 181:a4cbdfbbd2f4 61 */
mbed_official 181:a4cbdfbbd2f4 62 typedef struct
mbed_official 181:a4cbdfbbd2f4 63 {
mbed_official 181:a4cbdfbbd2f4 64 uint32_t Mode; /*!< Specifies the SPI operating mode.
mbed_official 181:a4cbdfbbd2f4 65 This parameter can be a value of @ref SPI_mode */
mbed_official 181:a4cbdfbbd2f4 66
mbed_official 181:a4cbdfbbd2f4 67 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
mbed_official 181:a4cbdfbbd2f4 68 This parameter can be a value of @ref SPI_Direction_mode */
mbed_official 181:a4cbdfbbd2f4 69
mbed_official 181:a4cbdfbbd2f4 70 uint32_t DataSize; /*!< Specifies the SPI data size.
mbed_official 181:a4cbdfbbd2f4 71 This parameter can be a value of @ref SPI_data_size */
mbed_official 181:a4cbdfbbd2f4 72
mbed_official 181:a4cbdfbbd2f4 73 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
mbed_official 181:a4cbdfbbd2f4 74 This parameter can be a value of @ref SPI_Clock_Polarity */
mbed_official 181:a4cbdfbbd2f4 75
mbed_official 181:a4cbdfbbd2f4 76 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
mbed_official 181:a4cbdfbbd2f4 77 This parameter can be a value of @ref SPI_Clock_Phase */
mbed_official 181:a4cbdfbbd2f4 78
mbed_official 181:a4cbdfbbd2f4 79 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
mbed_official 181:a4cbdfbbd2f4 80 hardware (NSS pin) or by software using the SSI bit.
mbed_official 181:a4cbdfbbd2f4 81 This parameter can be a value of @ref SPI_Slave_Select_management */
mbed_official 181:a4cbdfbbd2f4 82
mbed_official 181:a4cbdfbbd2f4 83 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
mbed_official 181:a4cbdfbbd2f4 84 used to configure the transmit and receive SCK clock.
mbed_official 181:a4cbdfbbd2f4 85 This parameter can be a value of @ref SPI_BaudRate_Prescaler
mbed_official 181:a4cbdfbbd2f4 86 @note The communication clock is derived from the master
mbed_official 181:a4cbdfbbd2f4 87 clock. The slave clock does not need to be set */
mbed_official 181:a4cbdfbbd2f4 88
mbed_official 181:a4cbdfbbd2f4 89 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
mbed_official 181:a4cbdfbbd2f4 90 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
mbed_official 181:a4cbdfbbd2f4 91
mbed_official 181:a4cbdfbbd2f4 92 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
mbed_official 181:a4cbdfbbd2f4 93 This parameter can be a value of @ref SPI_TI_mode */
mbed_official 181:a4cbdfbbd2f4 94
mbed_official 181:a4cbdfbbd2f4 95 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
mbed_official 181:a4cbdfbbd2f4 96 This parameter can be a value of @ref SPI_CRC_Calculation */
mbed_official 181:a4cbdfbbd2f4 97
mbed_official 181:a4cbdfbbd2f4 98 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
mbed_official 181:a4cbdfbbd2f4 99 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
mbed_official 181:a4cbdfbbd2f4 100
mbed_official 181:a4cbdfbbd2f4 101 }SPI_InitTypeDef;
mbed_official 181:a4cbdfbbd2f4 102
mbed_official 181:a4cbdfbbd2f4 103 /**
mbed_official 181:a4cbdfbbd2f4 104 * @brief HAL SPI State structure definition
mbed_official 181:a4cbdfbbd2f4 105 */
mbed_official 181:a4cbdfbbd2f4 106 typedef enum
mbed_official 181:a4cbdfbbd2f4 107 {
mbed_official 181:a4cbdfbbd2f4 108 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
mbed_official 181:a4cbdfbbd2f4 109 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
mbed_official 181:a4cbdfbbd2f4 110 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
mbed_official 181:a4cbdfbbd2f4 111 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
mbed_official 181:a4cbdfbbd2f4 112 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
mbed_official 181:a4cbdfbbd2f4 113 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
mbed_official 181:a4cbdfbbd2f4 114 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
mbed_official 181:a4cbdfbbd2f4 115
mbed_official 181:a4cbdfbbd2f4 116 }HAL_SPI_StateTypeDef;
mbed_official 181:a4cbdfbbd2f4 117
mbed_official 181:a4cbdfbbd2f4 118 /**
mbed_official 181:a4cbdfbbd2f4 119 * @brief HAL SPI Error Code structure definition
mbed_official 181:a4cbdfbbd2f4 120 */
mbed_official 181:a4cbdfbbd2f4 121 typedef enum
mbed_official 181:a4cbdfbbd2f4 122 {
mbed_official 181:a4cbdfbbd2f4 123 HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
mbed_official 181:a4cbdfbbd2f4 124 HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
mbed_official 181:a4cbdfbbd2f4 125 HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
mbed_official 181:a4cbdfbbd2f4 126 HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
mbed_official 181:a4cbdfbbd2f4 127 HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
mbed_official 181:a4cbdfbbd2f4 128 HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
mbed_official 181:a4cbdfbbd2f4 129 HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
mbed_official 181:a4cbdfbbd2f4 130
mbed_official 181:a4cbdfbbd2f4 131 }HAL_SPI_ErrorTypeDef;
mbed_official 181:a4cbdfbbd2f4 132
mbed_official 181:a4cbdfbbd2f4 133 /**
mbed_official 181:a4cbdfbbd2f4 134 * @brief SPI handle Structure definition
mbed_official 181:a4cbdfbbd2f4 135 */
mbed_official 181:a4cbdfbbd2f4 136 typedef struct __SPI_HandleTypeDef
mbed_official 181:a4cbdfbbd2f4 137 {
mbed_official 181:a4cbdfbbd2f4 138 SPI_TypeDef *Instance; /* SPI registers base address */
mbed_official 181:a4cbdfbbd2f4 139
mbed_official 181:a4cbdfbbd2f4 140 SPI_InitTypeDef Init; /* SPI communication parameters */
mbed_official 181:a4cbdfbbd2f4 141
mbed_official 181:a4cbdfbbd2f4 142 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
mbed_official 181:a4cbdfbbd2f4 143
mbed_official 181:a4cbdfbbd2f4 144 uint16_t TxXferSize; /* SPI Tx transfer size */
mbed_official 181:a4cbdfbbd2f4 145
mbed_official 181:a4cbdfbbd2f4 146 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
mbed_official 181:a4cbdfbbd2f4 147
mbed_official 181:a4cbdfbbd2f4 148 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
mbed_official 181:a4cbdfbbd2f4 149
mbed_official 181:a4cbdfbbd2f4 150 uint16_t RxXferSize; /* SPI Rx transfer size */
mbed_official 181:a4cbdfbbd2f4 151
mbed_official 181:a4cbdfbbd2f4 152 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
mbed_official 181:a4cbdfbbd2f4 153
mbed_official 181:a4cbdfbbd2f4 154 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
mbed_official 181:a4cbdfbbd2f4 155
mbed_official 181:a4cbdfbbd2f4 156 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
mbed_official 181:a4cbdfbbd2f4 157
mbed_official 181:a4cbdfbbd2f4 158 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
mbed_official 181:a4cbdfbbd2f4 159
mbed_official 181:a4cbdfbbd2f4 160 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
mbed_official 181:a4cbdfbbd2f4 161
mbed_official 181:a4cbdfbbd2f4 162 HAL_LockTypeDef Lock; /* SPI locking object */
mbed_official 181:a4cbdfbbd2f4 163
mbed_official 181:a4cbdfbbd2f4 164 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
mbed_official 181:a4cbdfbbd2f4 165
mbed_official 181:a4cbdfbbd2f4 166 __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
mbed_official 181:a4cbdfbbd2f4 167
mbed_official 181:a4cbdfbbd2f4 168 }SPI_HandleTypeDef;
mbed_official 181:a4cbdfbbd2f4 169
mbed_official 181:a4cbdfbbd2f4 170 /* Exported constants --------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 171
mbed_official 181:a4cbdfbbd2f4 172 /** @defgroup SPI_Exported_Constants
mbed_official 181:a4cbdfbbd2f4 173 * @{
mbed_official 181:a4cbdfbbd2f4 174 */
mbed_official 181:a4cbdfbbd2f4 175
mbed_official 181:a4cbdfbbd2f4 176 /** @defgroup SPI_mode
mbed_official 181:a4cbdfbbd2f4 177 * @{
mbed_official 181:a4cbdfbbd2f4 178 */
mbed_official 181:a4cbdfbbd2f4 179 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 180 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
mbed_official 181:a4cbdfbbd2f4 181
mbed_official 181:a4cbdfbbd2f4 182 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
mbed_official 181:a4cbdfbbd2f4 183 ((MODE) == SPI_MODE_MASTER))
mbed_official 181:a4cbdfbbd2f4 184 /**
mbed_official 181:a4cbdfbbd2f4 185 * @}
mbed_official 181:a4cbdfbbd2f4 186 */
mbed_official 181:a4cbdfbbd2f4 187
mbed_official 181:a4cbdfbbd2f4 188 /** @defgroup SPI_Direction_mode
mbed_official 181:a4cbdfbbd2f4 189 * @{
mbed_official 181:a4cbdfbbd2f4 190 */
mbed_official 181:a4cbdfbbd2f4 191 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
mbed_official 181:a4cbdfbbd2f4 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
mbed_official 181:a4cbdfbbd2f4 194
mbed_official 181:a4cbdfbbd2f4 195 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
mbed_official 181:a4cbdfbbd2f4 196 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
mbed_official 181:a4cbdfbbd2f4 197 ((MODE) == SPI_DIRECTION_1LINE))
mbed_official 181:a4cbdfbbd2f4 198
mbed_official 181:a4cbdfbbd2f4 199 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
mbed_official 181:a4cbdfbbd2f4 200 ((MODE) == SPI_DIRECTION_1LINE))
mbed_official 181:a4cbdfbbd2f4 201
mbed_official 181:a4cbdfbbd2f4 202 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
mbed_official 181:a4cbdfbbd2f4 203
mbed_official 181:a4cbdfbbd2f4 204 /**
mbed_official 181:a4cbdfbbd2f4 205 * @}
mbed_official 181:a4cbdfbbd2f4 206 */
mbed_official 181:a4cbdfbbd2f4 207
mbed_official 181:a4cbdfbbd2f4 208 /** @defgroup SPI_data_size
mbed_official 181:a4cbdfbbd2f4 209 * @{
mbed_official 181:a4cbdfbbd2f4 210 */
mbed_official 181:a4cbdfbbd2f4 211 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 212 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
mbed_official 181:a4cbdfbbd2f4 213
mbed_official 181:a4cbdfbbd2f4 214 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
mbed_official 181:a4cbdfbbd2f4 215 ((DATASIZE) == SPI_DATASIZE_8BIT))
mbed_official 181:a4cbdfbbd2f4 216 /**
mbed_official 181:a4cbdfbbd2f4 217 * @}
mbed_official 181:a4cbdfbbd2f4 218 */
mbed_official 181:a4cbdfbbd2f4 219
mbed_official 181:a4cbdfbbd2f4 220 /** @defgroup SPI_Clock_Polarity
mbed_official 181:a4cbdfbbd2f4 221 * @{
mbed_official 181:a4cbdfbbd2f4 222 */
mbed_official 181:a4cbdfbbd2f4 223 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 224 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
mbed_official 181:a4cbdfbbd2f4 225
mbed_official 181:a4cbdfbbd2f4 226 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
mbed_official 181:a4cbdfbbd2f4 227 ((CPOL) == SPI_POLARITY_HIGH))
mbed_official 181:a4cbdfbbd2f4 228 /**
mbed_official 181:a4cbdfbbd2f4 229 * @}
mbed_official 181:a4cbdfbbd2f4 230 */
mbed_official 181:a4cbdfbbd2f4 231
mbed_official 181:a4cbdfbbd2f4 232 /** @defgroup SPI_Clock_Phase
mbed_official 181:a4cbdfbbd2f4 233 * @{
mbed_official 181:a4cbdfbbd2f4 234 */
mbed_official 181:a4cbdfbbd2f4 235 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 236 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
mbed_official 181:a4cbdfbbd2f4 237
mbed_official 181:a4cbdfbbd2f4 238 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
mbed_official 181:a4cbdfbbd2f4 239 ((CPHA) == SPI_PHASE_2EDGE))
mbed_official 181:a4cbdfbbd2f4 240 /**
mbed_official 181:a4cbdfbbd2f4 241 * @}
mbed_official 181:a4cbdfbbd2f4 242 */
mbed_official 181:a4cbdfbbd2f4 243
mbed_official 181:a4cbdfbbd2f4 244 /** @defgroup SPI_Slave_Select_management
mbed_official 181:a4cbdfbbd2f4 245 * @{
mbed_official 181:a4cbdfbbd2f4 246 */
mbed_official 181:a4cbdfbbd2f4 247 #define SPI_NSS_SOFT SPI_CR1_SSM
mbed_official 181:a4cbdfbbd2f4 248 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 249 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
mbed_official 181:a4cbdfbbd2f4 250
mbed_official 181:a4cbdfbbd2f4 251 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
mbed_official 181:a4cbdfbbd2f4 252 ((NSS) == SPI_NSS_HARD_INPUT) || \
mbed_official 181:a4cbdfbbd2f4 253 ((NSS) == SPI_NSS_HARD_OUTPUT))
mbed_official 181:a4cbdfbbd2f4 254 /**
mbed_official 181:a4cbdfbbd2f4 255 * @}
mbed_official 181:a4cbdfbbd2f4 256 */
mbed_official 181:a4cbdfbbd2f4 257
mbed_official 181:a4cbdfbbd2f4 258 /** @defgroup SPI_BaudRate_Prescaler
mbed_official 181:a4cbdfbbd2f4 259 * @{
mbed_official 181:a4cbdfbbd2f4 260 */
mbed_official 181:a4cbdfbbd2f4 261 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 262 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
mbed_official 181:a4cbdfbbd2f4 263 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
mbed_official 181:a4cbdfbbd2f4 264 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
mbed_official 181:a4cbdfbbd2f4 265 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
mbed_official 181:a4cbdfbbd2f4 266 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
mbed_official 181:a4cbdfbbd2f4 267 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
mbed_official 181:a4cbdfbbd2f4 268 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
mbed_official 181:a4cbdfbbd2f4 269
mbed_official 181:a4cbdfbbd2f4 270 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
mbed_official 181:a4cbdfbbd2f4 271 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
mbed_official 181:a4cbdfbbd2f4 272 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
mbed_official 181:a4cbdfbbd2f4 273 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
mbed_official 181:a4cbdfbbd2f4 274 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
mbed_official 181:a4cbdfbbd2f4 275 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
mbed_official 181:a4cbdfbbd2f4 276 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
mbed_official 181:a4cbdfbbd2f4 277 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
mbed_official 181:a4cbdfbbd2f4 278 /**
mbed_official 181:a4cbdfbbd2f4 279 * @}
mbed_official 181:a4cbdfbbd2f4 280 */
mbed_official 181:a4cbdfbbd2f4 281
mbed_official 181:a4cbdfbbd2f4 282 /** @defgroup SPI_MSB_LSB_transmission
mbed_official 181:a4cbdfbbd2f4 283 * @{
mbed_official 181:a4cbdfbbd2f4 284 */
mbed_official 181:a4cbdfbbd2f4 285 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 286 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
mbed_official 181:a4cbdfbbd2f4 287
mbed_official 181:a4cbdfbbd2f4 288 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
mbed_official 181:a4cbdfbbd2f4 289 ((BIT) == SPI_FIRSTBIT_LSB))
mbed_official 181:a4cbdfbbd2f4 290 /**
mbed_official 181:a4cbdfbbd2f4 291 * @}
mbed_official 181:a4cbdfbbd2f4 292 */
mbed_official 181:a4cbdfbbd2f4 293
mbed_official 181:a4cbdfbbd2f4 294 /** @defgroup SPI_TI_mode
mbed_official 181:a4cbdfbbd2f4 295 * @{
mbed_official 181:a4cbdfbbd2f4 296 */
mbed_official 181:a4cbdfbbd2f4 297 #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 298 #define SPI_TIMODE_ENABLED SPI_CR2_FRF
mbed_official 181:a4cbdfbbd2f4 299
mbed_official 181:a4cbdfbbd2f4 300 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
mbed_official 181:a4cbdfbbd2f4 301 ((MODE) == SPI_TIMODE_ENABLED))
mbed_official 181:a4cbdfbbd2f4 302 /**
mbed_official 181:a4cbdfbbd2f4 303 * @}
mbed_official 181:a4cbdfbbd2f4 304 */
mbed_official 181:a4cbdfbbd2f4 305
mbed_official 181:a4cbdfbbd2f4 306 /** @defgroup SPI_CRC_Calculation
mbed_official 181:a4cbdfbbd2f4 307 * @{
mbed_official 181:a4cbdfbbd2f4 308 */
mbed_official 181:a4cbdfbbd2f4 309 #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
mbed_official 181:a4cbdfbbd2f4 310 #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
mbed_official 181:a4cbdfbbd2f4 311
mbed_official 181:a4cbdfbbd2f4 312 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
mbed_official 181:a4cbdfbbd2f4 313 ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
mbed_official 181:a4cbdfbbd2f4 314 /**
mbed_official 181:a4cbdfbbd2f4 315 * @}
mbed_official 181:a4cbdfbbd2f4 316 */
mbed_official 181:a4cbdfbbd2f4 317
mbed_official 181:a4cbdfbbd2f4 318 /** @defgroup SPI_Interrupt_configuration_definition
mbed_official 181:a4cbdfbbd2f4 319 * @{
mbed_official 181:a4cbdfbbd2f4 320 */
mbed_official 181:a4cbdfbbd2f4 321 #define SPI_IT_TXE SPI_CR2_TXEIE
mbed_official 181:a4cbdfbbd2f4 322 #define SPI_IT_RXNE SPI_CR2_RXNEIE
mbed_official 181:a4cbdfbbd2f4 323 #define SPI_IT_ERR SPI_CR2_ERRIE
mbed_official 181:a4cbdfbbd2f4 324 /**
mbed_official 181:a4cbdfbbd2f4 325 * @}
mbed_official 181:a4cbdfbbd2f4 326 */
mbed_official 181:a4cbdfbbd2f4 327
mbed_official 181:a4cbdfbbd2f4 328 /** @defgroup SPI_Flag_definition
mbed_official 181:a4cbdfbbd2f4 329 * @{
mbed_official 181:a4cbdfbbd2f4 330 */
mbed_official 181:a4cbdfbbd2f4 331 #define SPI_FLAG_RXNE SPI_SR_RXNE
mbed_official 181:a4cbdfbbd2f4 332 #define SPI_FLAG_TXE SPI_SR_TXE
mbed_official 181:a4cbdfbbd2f4 333 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
mbed_official 181:a4cbdfbbd2f4 334 #define SPI_FLAG_MODF SPI_SR_MODF
mbed_official 181:a4cbdfbbd2f4 335 #define SPI_FLAG_OVR SPI_SR_OVR
mbed_official 181:a4cbdfbbd2f4 336 #define SPI_FLAG_BSY SPI_SR_BSY
mbed_official 181:a4cbdfbbd2f4 337 #define SPI_FLAG_FRE SPI_SR_FRE
mbed_official 181:a4cbdfbbd2f4 338
mbed_official 181:a4cbdfbbd2f4 339 /**
mbed_official 181:a4cbdfbbd2f4 340 * @}
mbed_official 181:a4cbdfbbd2f4 341 */
mbed_official 181:a4cbdfbbd2f4 342
mbed_official 181:a4cbdfbbd2f4 343 /**
mbed_official 181:a4cbdfbbd2f4 344 * @}
mbed_official 181:a4cbdfbbd2f4 345 */
mbed_official 181:a4cbdfbbd2f4 346
mbed_official 181:a4cbdfbbd2f4 347 /* Exported macro ------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 348
mbed_official 181:a4cbdfbbd2f4 349 /** @brief Reset SPI handle state
mbed_official 181:a4cbdfbbd2f4 350 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 351 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 352 * @retval None
mbed_official 181:a4cbdfbbd2f4 353 */
mbed_official 181:a4cbdfbbd2f4 354 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 355
mbed_official 181:a4cbdfbbd2f4 356 /** @brief Enable or disable the specified SPI interrupts.
mbed_official 181:a4cbdfbbd2f4 357 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 358 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 359 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
mbed_official 181:a4cbdfbbd2f4 360 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 361 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
mbed_official 181:a4cbdfbbd2f4 362 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
mbed_official 181:a4cbdfbbd2f4 363 * @arg SPI_IT_ERR: Error interrupt enable
mbed_official 181:a4cbdfbbd2f4 364 * @retval None
mbed_official 181:a4cbdfbbd2f4 365 */
mbed_official 181:a4cbdfbbd2f4 366 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
mbed_official 181:a4cbdfbbd2f4 367 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
mbed_official 181:a4cbdfbbd2f4 368
mbed_official 181:a4cbdfbbd2f4 369 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
mbed_official 181:a4cbdfbbd2f4 370 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 371 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 372 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
mbed_official 181:a4cbdfbbd2f4 373 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 374 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
mbed_official 181:a4cbdfbbd2f4 375 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
mbed_official 181:a4cbdfbbd2f4 376 * @arg SPI_IT_ERR: Error interrupt enable
mbed_official 181:a4cbdfbbd2f4 377 * @retval The new state of __IT__ (TRUE or FALSE).
mbed_official 181:a4cbdfbbd2f4 378 */
mbed_official 181:a4cbdfbbd2f4 379 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official 181:a4cbdfbbd2f4 380
mbed_official 181:a4cbdfbbd2f4 381 /** @brief Check whether the specified SPI flag is set or not.
mbed_official 181:a4cbdfbbd2f4 382 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 383 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 384 * @param __FLAG__: specifies the flag to check.
mbed_official 181:a4cbdfbbd2f4 385 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 386 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
mbed_official 181:a4cbdfbbd2f4 387 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
mbed_official 181:a4cbdfbbd2f4 388 * @arg SPI_FLAG_CRCERR: CRC error flag
mbed_official 181:a4cbdfbbd2f4 389 * @arg SPI_FLAG_MODF: Mode fault flag
mbed_official 181:a4cbdfbbd2f4 390 * @arg SPI_FLAG_OVR: Overrun flag
mbed_official 181:a4cbdfbbd2f4 391 * @arg SPI_FLAG_BSY: Busy flag
mbed_official 181:a4cbdfbbd2f4 392 * @arg SPI_FLAG_FRE: Frame format error flag
mbed_official 181:a4cbdfbbd2f4 393 * @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official 181:a4cbdfbbd2f4 394 */
mbed_official 181:a4cbdfbbd2f4 395 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
mbed_official 181:a4cbdfbbd2f4 396
mbed_official 181:a4cbdfbbd2f4 397 /** @brief Clear the SPI CRCERR pending flag.
mbed_official 181:a4cbdfbbd2f4 398 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 399 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 400 * @retval None
mbed_official 181:a4cbdfbbd2f4 401 */
mbed_official 181:a4cbdfbbd2f4 402 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= (uint32_t)~((uint32_t)SPI_FLAG_CRCERR))
mbed_official 181:a4cbdfbbd2f4 403
mbed_official 181:a4cbdfbbd2f4 404 /** @brief Clear the SPI MODF pending flag.
mbed_official 181:a4cbdfbbd2f4 405 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 406 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 407 * @retval None
mbed_official 181:a4cbdfbbd2f4 408 */
mbed_official 181:a4cbdfbbd2f4 409 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
mbed_official 181:a4cbdfbbd2f4 410 (__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_SPE);}while(0)
mbed_official 181:a4cbdfbbd2f4 411
mbed_official 181:a4cbdfbbd2f4 412 /** @brief Clear the SPI OVR pending flag.
mbed_official 181:a4cbdfbbd2f4 413 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 414 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 415 * @retval None
mbed_official 181:a4cbdfbbd2f4 416 */
mbed_official 181:a4cbdfbbd2f4 417 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
mbed_official 181:a4cbdfbbd2f4 418 (__HANDLE__)->Instance->SR;}while(0)
mbed_official 181:a4cbdfbbd2f4 419
mbed_official 181:a4cbdfbbd2f4 420 /** @brief Clear the SPI FRE pending flag.
mbed_official 181:a4cbdfbbd2f4 421 * @param __HANDLE__: specifies the SPI handle.
mbed_official 181:a4cbdfbbd2f4 422 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
mbed_official 181:a4cbdfbbd2f4 423 * @retval None
mbed_official 181:a4cbdfbbd2f4 424 */
mbed_official 181:a4cbdfbbd2f4 425 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
mbed_official 181:a4cbdfbbd2f4 426
mbed_official 181:a4cbdfbbd2f4 427 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
mbed_official 181:a4cbdfbbd2f4 428 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_SPE))
mbed_official 181:a4cbdfbbd2f4 429
mbed_official 181:a4cbdfbbd2f4 430 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
mbed_official 181:a4cbdfbbd2f4 431
mbed_official 181:a4cbdfbbd2f4 432 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
mbed_official 181:a4cbdfbbd2f4 433
mbed_official 181:a4cbdfbbd2f4 434 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_BIDIOE))
mbed_official 181:a4cbdfbbd2f4 435
mbed_official 181:a4cbdfbbd2f4 436 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_CRCEN);\
mbed_official 181:a4cbdfbbd2f4 437 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
mbed_official 181:a4cbdfbbd2f4 438
mbed_official 181:a4cbdfbbd2f4 439 /* Exported functions --------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 440
mbed_official 181:a4cbdfbbd2f4 441 /* Initialization/de-initialization functions **********************************/
mbed_official 181:a4cbdfbbd2f4 442 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 443 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 444 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 445 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 446
mbed_official 181:a4cbdfbbd2f4 447 /* I/O operation functions *****************************************************/
mbed_official 181:a4cbdfbbd2f4 448 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
mbed_official 181:a4cbdfbbd2f4 449 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
mbed_official 181:a4cbdfbbd2f4 450 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
mbed_official 181:a4cbdfbbd2f4 451 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
mbed_official 181:a4cbdfbbd2f4 452 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
mbed_official 181:a4cbdfbbd2f4 453 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
mbed_official 181:a4cbdfbbd2f4 454 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
mbed_official 181:a4cbdfbbd2f4 455 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
mbed_official 181:a4cbdfbbd2f4 456 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
mbed_official 181:a4cbdfbbd2f4 457 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 458 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 459 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 460 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 461 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 462
mbed_official 181:a4cbdfbbd2f4 463 /* Peripheral State and Control functions **************************************/
mbed_official 181:a4cbdfbbd2f4 464 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 465 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
mbed_official 181:a4cbdfbbd2f4 466
mbed_official 181:a4cbdfbbd2f4 467 /**
mbed_official 181:a4cbdfbbd2f4 468 * @}
mbed_official 181:a4cbdfbbd2f4 469 */
mbed_official 181:a4cbdfbbd2f4 470
mbed_official 181:a4cbdfbbd2f4 471 /**
mbed_official 181:a4cbdfbbd2f4 472 * @}
mbed_official 181:a4cbdfbbd2f4 473 */
mbed_official 181:a4cbdfbbd2f4 474
mbed_official 181:a4cbdfbbd2f4 475 #ifdef __cplusplus
mbed_official 181:a4cbdfbbd2f4 476 }
mbed_official 181:a4cbdfbbd2f4 477 #endif
mbed_official 181:a4cbdfbbd2f4 478
mbed_official 181:a4cbdfbbd2f4 479 #endif /* __STM32L0xx_HAL_SPI_H */
mbed_official 181:a4cbdfbbd2f4 480
mbed_official 181:a4cbdfbbd2f4 481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/