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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
181:a4cbdfbbd2f4 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 181:a4cbdfbbd2f4 1 /**
mbed_official 181:a4cbdfbbd2f4 2 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 3 * @file stm32l0xx_hal_rcc_ex.c
mbed_official 181:a4cbdfbbd2f4 4 * @author MCD Application Team
mbed_official 181:a4cbdfbbd2f4 5 * @version V1.0.0
mbed_official 181:a4cbdfbbd2f4 6 * @date 22-April-2014
mbed_official 181:a4cbdfbbd2f4 7 * @brief Extended RCC HAL module driver.
mbed_official 181:a4cbdfbbd2f4 8 *
mbed_official 181:a4cbdfbbd2f4 9 * This file provides firmware functions to manage the following
mbed_official 181:a4cbdfbbd2f4 10 * functionalities RCC extension peripheral:
mbed_official 181:a4cbdfbbd2f4 11 * + Extended Peripheral Control functions
mbed_official 181:a4cbdfbbd2f4 12 *
mbed_official 181:a4cbdfbbd2f4 13 @verbatim
mbed_official 181:a4cbdfbbd2f4 14 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 15 ##### RCC specific features #####
mbed_official 181:a4cbdfbbd2f4 16 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 17 For CRS, RCC Extension HAL driver can be used as follows:
mbed_official 181:a4cbdfbbd2f4 18
mbed_official 181:a4cbdfbbd2f4 19 (#) In System clock configuration, HSI48 need to be enabled
mbed_official 181:a4cbdfbbd2f4 20
mbed_official 181:a4cbdfbbd2f4 21 (#] Enable CRS clock in IP MSP init which will use CRS functions
mbed_official 181:a4cbdfbbd2f4 22
mbed_official 181:a4cbdfbbd2f4 23 (#) Call CRS functions like this
mbed_official 181:a4cbdfbbd2f4 24 (##) Prepare synchronization configuration necessary for HSI48 calibration
mbed_official 181:a4cbdfbbd2f4 25 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
mbed_official 181:a4cbdfbbd2f4 26 and also HSI48 oscillator smooth trimming.
mbed_official 181:a4cbdfbbd2f4 27 (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate
mbed_official 181:a4cbdfbbd2f4 28 directly reload value with target and synchronization frequencies values
mbed_official 181:a4cbdfbbd2f4 29 (##) Call function HAL_RCCEx_CRSConfig which
mbed_official 181:a4cbdfbbd2f4 30 (+++) Reset CRS registers to their default values.
mbed_official 181:a4cbdfbbd2f4 31 (+++) Configure CRS registers with synchronization configuration
mbed_official 181:a4cbdfbbd2f4 32 (+++) Enable automatic calibration and frequency error counter feature
mbed_official 181:a4cbdfbbd2f4 33
mbed_official 181:a4cbdfbbd2f4 34 (##) A polling function is provided to wait for complete Synchronization
mbed_official 181:a4cbdfbbd2f4 35 (+++) Call function 'HAL_RCCEx_CRSWaitSynchronization()'
mbed_official 181:a4cbdfbbd2f4 36 (+++) According to CRS status, user can decide to adjust again the calibration or continue
mbed_official 181:a4cbdfbbd2f4 37 application if synchronization is OK
mbed_official 181:a4cbdfbbd2f4 38
mbed_official 181:a4cbdfbbd2f4 39 (#) User can retrieve information related to synchronization in calling function
mbed_official 181:a4cbdfbbd2f4 40 HAL_RCCEx_CRSGetSynchronizationInfo()
mbed_official 181:a4cbdfbbd2f4 41
mbed_official 181:a4cbdfbbd2f4 42 (#) Regarding synchronization status and synchronization information, user can try a new calibration
mbed_official 181:a4cbdfbbd2f4 43 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
mbed_official 181:a4cbdfbbd2f4 44 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
mbed_official 181:a4cbdfbbd2f4 45 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
mbed_official 181:a4cbdfbbd2f4 46 incremented), while when it is detected during the upcounting phase it means that the actual frequency
mbed_official 181:a4cbdfbbd2f4 47 is higher (and that the TRIM value should be decremented).
mbed_official 181:a4cbdfbbd2f4 48
mbed_official 181:a4cbdfbbd2f4 49 (#) To use IT mode, user needs to handle it in calling different macros available to do it
mbed_official 181:a4cbdfbbd2f4 50 (__HAL_RCC_CRS_XXX_IT). Interruptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler)
mbed_official 181:a4cbdfbbd2f4 51 (+++) Call function HAL_RCCEx_CRSConfig()
mbed_official 181:a4cbdfbbd2f4 52 (+++) Enable RCC_IRQn (thnaks to NVIC functions)
mbed_official 181:a4cbdfbbd2f4 53 (+++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT)
mbed_official 181:a4cbdfbbd2f4 54 [+++) Implement CRS status management in RCC_CRS_IRQHandler
mbed_official 181:a4cbdfbbd2f4 55
mbed_official 181:a4cbdfbbd2f4 56 (#) To force a SYNC EVENT, user can use function 'HAL_RCCEx_CRSSoftwareSynchronizationGenerate()'. Function can be
mbed_official 181:a4cbdfbbd2f4 57 called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
mbed_official 181:a4cbdfbbd2f4 58
mbed_official 181:a4cbdfbbd2f4 59 @endverbatim
mbed_official 181:a4cbdfbbd2f4 60 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 61 * @attention
mbed_official 181:a4cbdfbbd2f4 62 *
mbed_official 181:a4cbdfbbd2f4 63 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 181:a4cbdfbbd2f4 64 *
mbed_official 181:a4cbdfbbd2f4 65 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 181:a4cbdfbbd2f4 66 * are permitted provided that the following conditions are met:
mbed_official 181:a4cbdfbbd2f4 67 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 68 * this list of conditions and the following disclaimer.
mbed_official 181:a4cbdfbbd2f4 69 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 70 * this list of conditions and the following disclaimer in the documentation
mbed_official 181:a4cbdfbbd2f4 71 * and/or other materials provided with the distribution.
mbed_official 181:a4cbdfbbd2f4 72 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 181:a4cbdfbbd2f4 73 * may be used to endorse or promote products derived from this software
mbed_official 181:a4cbdfbbd2f4 74 * without specific prior written permission.
mbed_official 181:a4cbdfbbd2f4 75 *
mbed_official 181:a4cbdfbbd2f4 76 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 181:a4cbdfbbd2f4 77 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 181:a4cbdfbbd2f4 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 181:a4cbdfbbd2f4 79 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 181:a4cbdfbbd2f4 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 181:a4cbdfbbd2f4 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 181:a4cbdfbbd2f4 82 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 181:a4cbdfbbd2f4 83 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 181:a4cbdfbbd2f4 84 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 181:a4cbdfbbd2f4 85 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 181:a4cbdfbbd2f4 86 *
mbed_official 181:a4cbdfbbd2f4 87 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 88 */
mbed_official 181:a4cbdfbbd2f4 89
mbed_official 181:a4cbdfbbd2f4 90 /* Includes ------------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 91 #include "stm32l0xx_hal.h"
mbed_official 181:a4cbdfbbd2f4 92
mbed_official 181:a4cbdfbbd2f4 93 /** @addtogroup STM32L0xx_HAL_Driver
mbed_official 181:a4cbdfbbd2f4 94 * @{
mbed_official 181:a4cbdfbbd2f4 95 */
mbed_official 181:a4cbdfbbd2f4 96
mbed_official 181:a4cbdfbbd2f4 97 /** @defgroup RCCEx
mbed_official 181:a4cbdfbbd2f4 98 * @brief RCC Extension HAL module driver
mbed_official 181:a4cbdfbbd2f4 99 * @{
mbed_official 181:a4cbdfbbd2f4 100 */
mbed_official 181:a4cbdfbbd2f4 101
mbed_official 181:a4cbdfbbd2f4 102 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 181:a4cbdfbbd2f4 103
mbed_official 181:a4cbdfbbd2f4 104 /* Private typedef -----------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 105 /* Private define ------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 106 /* Bit position in register */
mbed_official 181:a4cbdfbbd2f4 107 #define CRS_CFGR_FELIM_BITNUMBER 16
mbed_official 181:a4cbdfbbd2f4 108 #define CRS_CR_TRIM_BITNUMBER 8
mbed_official 181:a4cbdfbbd2f4 109 #define CRS_ISR_FECAP_BITNUMBER 16
mbed_official 181:a4cbdfbbd2f4 110
mbed_official 181:a4cbdfbbd2f4 111 /* Private macro -------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 112 /* Private variables ---------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 113 /* Private function prototypes -----------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 114 /* Private functions ---------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 115
mbed_official 181:a4cbdfbbd2f4 116 /** @defgroup RCCEx_Private_Functions
mbed_official 181:a4cbdfbbd2f4 117 * @{
mbed_official 181:a4cbdfbbd2f4 118 */
mbed_official 181:a4cbdfbbd2f4 119
mbed_official 181:a4cbdfbbd2f4 120 /** @defgroup RCCEx_Group1 Extended Peripheral Control functions
mbed_official 181:a4cbdfbbd2f4 121 * @brief Extended Peripheral Control functions
mbed_official 181:a4cbdfbbd2f4 122 *
mbed_official 181:a4cbdfbbd2f4 123 @verbatim
mbed_official 181:a4cbdfbbd2f4 124 ===============================================================================
mbed_official 181:a4cbdfbbd2f4 125 ##### Extended Peripheral Control functions #####
mbed_official 181:a4cbdfbbd2f4 126 ===============================================================================
mbed_official 181:a4cbdfbbd2f4 127 [..]
mbed_official 181:a4cbdfbbd2f4 128 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 181:a4cbdfbbd2f4 129 frequencies.
mbed_official 181:a4cbdfbbd2f4 130
mbed_official 181:a4cbdfbbd2f4 131 @endverbatim
mbed_official 181:a4cbdfbbd2f4 132 * @{
mbed_official 181:a4cbdfbbd2f4 133 */
mbed_official 181:a4cbdfbbd2f4 134
mbed_official 181:a4cbdfbbd2f4 135 /**
mbed_official 181:a4cbdfbbd2f4 136 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official 181:a4cbdfbbd2f4 137 * RCC_PeriphCLKInitTypeDef.
mbed_official 181:a4cbdfbbd2f4 138 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 181:a4cbdfbbd2f4 139 * contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
mbed_official 181:a4cbdfbbd2f4 140 * I2C1, RTC, USB/RNG and LPTIM1 clocks).
mbed_official 181:a4cbdfbbd2f4 141 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 142 */
mbed_official 181:a4cbdfbbd2f4 143 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 181:a4cbdfbbd2f4 144 {
mbed_official 181:a4cbdfbbd2f4 145 uint32_t tickstart = 0;
mbed_official 181:a4cbdfbbd2f4 146 uint32_t tmpreg = 0;
mbed_official 181:a4cbdfbbd2f4 147
mbed_official 181:a4cbdfbbd2f4 148 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 149 assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
mbed_official 181:a4cbdfbbd2f4 150
mbed_official 181:a4cbdfbbd2f4 151 /*------------------------------- USART1 Configuration ------------------------*/
mbed_official 181:a4cbdfbbd2f4 152 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
mbed_official 181:a4cbdfbbd2f4 153 {
mbed_official 181:a4cbdfbbd2f4 154 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 155 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
mbed_official 181:a4cbdfbbd2f4 156
mbed_official 181:a4cbdfbbd2f4 157 /* Configure the USART1 clock source */
mbed_official 181:a4cbdfbbd2f4 158 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
mbed_official 181:a4cbdfbbd2f4 159 }
mbed_official 181:a4cbdfbbd2f4 160
mbed_official 181:a4cbdfbbd2f4 161 /*----------------------------- USART2 Configuration --------------------------*/
mbed_official 181:a4cbdfbbd2f4 162 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
mbed_official 181:a4cbdfbbd2f4 163 {
mbed_official 181:a4cbdfbbd2f4 164 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 165 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
mbed_official 181:a4cbdfbbd2f4 166
mbed_official 181:a4cbdfbbd2f4 167 /* Configure the USART2 clock source */
mbed_official 181:a4cbdfbbd2f4 168 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
mbed_official 181:a4cbdfbbd2f4 169 }
mbed_official 181:a4cbdfbbd2f4 170
mbed_official 181:a4cbdfbbd2f4 171 /*------------------------------ LPUART1 Configuration ------------------------*/
mbed_official 181:a4cbdfbbd2f4 172 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
mbed_official 181:a4cbdfbbd2f4 173 {
mbed_official 181:a4cbdfbbd2f4 174 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 175 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
mbed_official 181:a4cbdfbbd2f4 176
mbed_official 181:a4cbdfbbd2f4 177 /* Configure the LPUAR1 clock source */
mbed_official 181:a4cbdfbbd2f4 178 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
mbed_official 181:a4cbdfbbd2f4 179 }
mbed_official 181:a4cbdfbbd2f4 180
mbed_official 181:a4cbdfbbd2f4 181 /*------------------------------ I2C1 Configuration ------------------------*/
mbed_official 181:a4cbdfbbd2f4 182 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
mbed_official 181:a4cbdfbbd2f4 183 {
mbed_official 181:a4cbdfbbd2f4 184 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 185 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
mbed_official 181:a4cbdfbbd2f4 186
mbed_official 181:a4cbdfbbd2f4 187 /* Configure the I2C1 clock source */
mbed_official 181:a4cbdfbbd2f4 188 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
mbed_official 181:a4cbdfbbd2f4 189 }
mbed_official 181:a4cbdfbbd2f4 190
mbed_official 181:a4cbdfbbd2f4 191
mbed_official 181:a4cbdfbbd2f4 192 /*---------------------------- RTC configuration -------------------------------*/
mbed_official 181:a4cbdfbbd2f4 193 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official 181:a4cbdfbbd2f4 194 {
mbed_official 181:a4cbdfbbd2f4 195 /* Enable Power Clock*/
mbed_official 181:a4cbdfbbd2f4 196 __PWR_CLK_ENABLE();
mbed_official 181:a4cbdfbbd2f4 197
mbed_official 181:a4cbdfbbd2f4 198 /* Enable write access to Backup domain */
mbed_official 181:a4cbdfbbd2f4 199 PWR->CR |= PWR_CR_DBP;
mbed_official 181:a4cbdfbbd2f4 200
mbed_official 181:a4cbdfbbd2f4 201 /* Wait for Backup domain Write protection disable */
mbed_official 181:a4cbdfbbd2f4 202 tickstart = HAL_GetTick();
mbed_official 181:a4cbdfbbd2f4 203
mbed_official 181:a4cbdfbbd2f4 204 while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official 181:a4cbdfbbd2f4 205 {
mbed_official 181:a4cbdfbbd2f4 206 if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
mbed_official 181:a4cbdfbbd2f4 207 {
mbed_official 181:a4cbdfbbd2f4 208 return HAL_TIMEOUT;
mbed_official 181:a4cbdfbbd2f4 209 }
mbed_official 181:a4cbdfbbd2f4 210 }
mbed_official 181:a4cbdfbbd2f4 211
mbed_official 181:a4cbdfbbd2f4 212 /* Reset the Backup domain only if the RTC Clock source selection is modified */
mbed_official 181:a4cbdfbbd2f4 213 if((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
mbed_official 181:a4cbdfbbd2f4 214 {
mbed_official 181:a4cbdfbbd2f4 215 /* Store the content of CSR register before the reset of Backup Domain */
mbed_official 181:a4cbdfbbd2f4 216 tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
mbed_official 181:a4cbdfbbd2f4 217 /* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official 181:a4cbdfbbd2f4 218 __HAL_RCC_BACKUPRESET_FORCE();
mbed_official 181:a4cbdfbbd2f4 219 __HAL_RCC_BACKUPRESET_RELEASE();
mbed_official 181:a4cbdfbbd2f4 220 /* Restore the Content of CSR register */
mbed_official 181:a4cbdfbbd2f4 221 RCC->CSR = tmpreg;
mbed_official 181:a4cbdfbbd2f4 222 }
mbed_official 181:a4cbdfbbd2f4 223
mbed_official 181:a4cbdfbbd2f4 224 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official 181:a4cbdfbbd2f4 225 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
mbed_official 181:a4cbdfbbd2f4 226 {
mbed_official 181:a4cbdfbbd2f4 227 /* Get timeout */
mbed_official 181:a4cbdfbbd2f4 228 tickstart = HAL_GetTick();
mbed_official 181:a4cbdfbbd2f4 229
mbed_official 181:a4cbdfbbd2f4 230 /* Wait till LSE is ready */
mbed_official 181:a4cbdfbbd2f4 231 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official 181:a4cbdfbbd2f4 232 {
mbed_official 181:a4cbdfbbd2f4 233 if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official 181:a4cbdfbbd2f4 234 {
mbed_official 181:a4cbdfbbd2f4 235 return HAL_TIMEOUT;
mbed_official 181:a4cbdfbbd2f4 236 }
mbed_official 181:a4cbdfbbd2f4 237 }
mbed_official 181:a4cbdfbbd2f4 238 }
mbed_official 181:a4cbdfbbd2f4 239 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official 181:a4cbdfbbd2f4 240 }
mbed_official 181:a4cbdfbbd2f4 241 #if !defined(STM32L051xx) && !defined(STM32L061xx)
mbed_official 181:a4cbdfbbd2f4 242 /*---------------------------- USB and RNG configuration --------------------*/
mbed_official 181:a4cbdfbbd2f4 243 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
mbed_official 181:a4cbdfbbd2f4 244 {
mbed_official 181:a4cbdfbbd2f4 245 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
mbed_official 181:a4cbdfbbd2f4 246 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
mbed_official 181:a4cbdfbbd2f4 247 }
mbed_official 181:a4cbdfbbd2f4 248 #endif /* !(STM32L051xx) && !(STM32L061xx) */
mbed_official 181:a4cbdfbbd2f4 249
mbed_official 181:a4cbdfbbd2f4 250 /*---------------------------- LPTIM1 configuration ------------------------*/
mbed_official 181:a4cbdfbbd2f4 251 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
mbed_official 181:a4cbdfbbd2f4 252 {
mbed_official 181:a4cbdfbbd2f4 253 assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
mbed_official 181:a4cbdfbbd2f4 254 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
mbed_official 181:a4cbdfbbd2f4 255 }
mbed_official 181:a4cbdfbbd2f4 256 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 257 }
mbed_official 181:a4cbdfbbd2f4 258
mbed_official 181:a4cbdfbbd2f4 259 /**
mbed_official 181:a4cbdfbbd2f4 260 * @brief Get the RCC_ClkInitStruct according to the internal
mbed_official 181:a4cbdfbbd2f4 261 * RCC configuration registers.
mbed_official 181:a4cbdfbbd2f4 262 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 181:a4cbdfbbd2f4 263 * returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
mbed_official 181:a4cbdfbbd2f4 264 * I2C1, RTC, USB/RNG and LPTIM1 clocks).
mbed_official 181:a4cbdfbbd2f4 265 * @retval None
mbed_official 181:a4cbdfbbd2f4 266 */
mbed_official 181:a4cbdfbbd2f4 267 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 181:a4cbdfbbd2f4 268 {
mbed_official 181:a4cbdfbbd2f4 269 /* Set all possible values for the extended clock type parameter -----------*/
mbed_official 181:a4cbdfbbd2f4 270 /* Common part first */
mbed_official 181:a4cbdfbbd2f4 271 #if !defined(STM32L051xx) && !defined(STM32L061xx)
mbed_official 181:a4cbdfbbd2f4 272 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
mbed_official 181:a4cbdfbbd2f4 273 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
mbed_official 181:a4cbdfbbd2f4 274 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1;
mbed_official 181:a4cbdfbbd2f4 275
mbed_official 181:a4cbdfbbd2f4 276 #else
mbed_official 181:a4cbdfbbd2f4 277 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
mbed_official 181:a4cbdfbbd2f4 278 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
mbed_official 181:a4cbdfbbd2f4 279 RCC_PERIPHCLK_LPTIM1;
mbed_official 181:a4cbdfbbd2f4 280 #endif /* !(STM32L051xx) && !(STM32L061xx) */
mbed_official 181:a4cbdfbbd2f4 281
mbed_official 181:a4cbdfbbd2f4 282 /* Get the USART1 configuration --------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 283 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
mbed_official 181:a4cbdfbbd2f4 284 /* Get the USART2 clock source ---------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 285 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
mbed_official 181:a4cbdfbbd2f4 286 /* Get the LPUART1 clock source ---------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 287 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
mbed_official 181:a4cbdfbbd2f4 288 /* Get the I2C1 clock source -----------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 289 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
mbed_official 181:a4cbdfbbd2f4 290 /* Get the LPTIM1 clock source -----------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 291 PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
mbed_official 181:a4cbdfbbd2f4 292 /* Get the RTC clock source -----------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 293 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
mbed_official 181:a4cbdfbbd2f4 294
mbed_official 181:a4cbdfbbd2f4 295 #if !defined(STM32L051xx) && !defined(STM32L061xx)
mbed_official 181:a4cbdfbbd2f4 296 /* Get the USB/RNG clock source -----------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 297 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
mbed_official 181:a4cbdfbbd2f4 298 #endif /* !(STM32L051xx) && !(STM32L061xx) */
mbed_official 181:a4cbdfbbd2f4 299 }
mbed_official 181:a4cbdfbbd2f4 300
mbed_official 181:a4cbdfbbd2f4 301 /**
mbed_official 181:a4cbdfbbd2f4 302 * @brief Enables the LSE Clock Security System.
mbed_official 181:a4cbdfbbd2f4 303 * @param None
mbed_official 181:a4cbdfbbd2f4 304 * @retval None
mbed_official 181:a4cbdfbbd2f4 305 */
mbed_official 181:a4cbdfbbd2f4 306 void HAL_RCCEx_EnableLSECSS(void)
mbed_official 181:a4cbdfbbd2f4 307 {
mbed_official 181:a4cbdfbbd2f4 308 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
mbed_official 181:a4cbdfbbd2f4 309 }
mbed_official 181:a4cbdfbbd2f4 310
mbed_official 181:a4cbdfbbd2f4 311 /**
mbed_official 181:a4cbdfbbd2f4 312 * @brief Disables the LSE Clock Security System.
mbed_official 181:a4cbdfbbd2f4 313 * @param None
mbed_official 181:a4cbdfbbd2f4 314 * @retval None
mbed_official 181:a4cbdfbbd2f4 315 */
mbed_official 181:a4cbdfbbd2f4 316 void HAL_RCCEx_DisableLSECSS(void)
mbed_official 181:a4cbdfbbd2f4 317 {
mbed_official 181:a4cbdfbbd2f4 318 CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
mbed_official 181:a4cbdfbbd2f4 319 }
mbed_official 181:a4cbdfbbd2f4 320
mbed_official 181:a4cbdfbbd2f4 321 #if !defined(STM32L051xx) && !defined(STM32L061xx)
mbed_official 181:a4cbdfbbd2f4 322
mbed_official 181:a4cbdfbbd2f4 323 /**
mbed_official 181:a4cbdfbbd2f4 324 * @brief Start automatic synchronization using polling mode
mbed_official 181:a4cbdfbbd2f4 325 * @param pInit Pointer on RCC_CRSInitTypeDef structure
mbed_official 181:a4cbdfbbd2f4 326 * @retval None
mbed_official 181:a4cbdfbbd2f4 327 */
mbed_official 181:a4cbdfbbd2f4 328 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
mbed_official 181:a4cbdfbbd2f4 329 {
mbed_official 181:a4cbdfbbd2f4 330 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 331 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
mbed_official 181:a4cbdfbbd2f4 332 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
mbed_official 181:a4cbdfbbd2f4 333 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
mbed_official 181:a4cbdfbbd2f4 334 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
mbed_official 181:a4cbdfbbd2f4 335 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
mbed_official 181:a4cbdfbbd2f4 336 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
mbed_official 181:a4cbdfbbd2f4 337
mbed_official 181:a4cbdfbbd2f4 338
mbed_official 181:a4cbdfbbd2f4 339 /* CONFIGURATION */
mbed_official 181:a4cbdfbbd2f4 340
mbed_official 181:a4cbdfbbd2f4 341 /* Before configuration, reset CRS registers to their default values*/
mbed_official 181:a4cbdfbbd2f4 342 __CRS_FORCE_RESET();
mbed_official 181:a4cbdfbbd2f4 343 __CRS_RELEASE_RESET();
mbed_official 181:a4cbdfbbd2f4 344
mbed_official 181:a4cbdfbbd2f4 345 /* Configure Synchronization input */
mbed_official 181:a4cbdfbbd2f4 346 /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
mbed_official 181:a4cbdfbbd2f4 347 CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL);
mbed_official 181:a4cbdfbbd2f4 348
mbed_official 181:a4cbdfbbd2f4 349 /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */
mbed_official 181:a4cbdfbbd2f4 350 CRS->CFGR |= pInit->Prescaler;
mbed_official 181:a4cbdfbbd2f4 351
mbed_official 181:a4cbdfbbd2f4 352 /* Set the SYNCSRC[1:0] bits according to Source value */
mbed_official 181:a4cbdfbbd2f4 353 CRS->CFGR |= pInit->Source;
mbed_official 181:a4cbdfbbd2f4 354
mbed_official 181:a4cbdfbbd2f4 355 /* Set the SYNCSPOL bits according to Polarity value */
mbed_official 181:a4cbdfbbd2f4 356 CRS->CFGR |= pInit->Polarity;
mbed_official 181:a4cbdfbbd2f4 357
mbed_official 181:a4cbdfbbd2f4 358 /* Configure Frequency Error Measurement */
mbed_official 181:a4cbdfbbd2f4 359 /* Clear RELOAD[15:0] & FELIM[7:0] bits*/
mbed_official 181:a4cbdfbbd2f4 360 CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM);
mbed_official 181:a4cbdfbbd2f4 361
mbed_official 181:a4cbdfbbd2f4 362 /* Set the RELOAD[15:0] bits according to ReloadValue value */
mbed_official 181:a4cbdfbbd2f4 363 CRS->CFGR |= pInit->ReloadValue;
mbed_official 181:a4cbdfbbd2f4 364
mbed_official 181:a4cbdfbbd2f4 365 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
mbed_official 181:a4cbdfbbd2f4 366 CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
mbed_official 181:a4cbdfbbd2f4 367
mbed_official 181:a4cbdfbbd2f4 368 /* Adjust HSI48 oscillator smooth trimming */
mbed_official 181:a4cbdfbbd2f4 369 /* Clear TRIM[5:0] bits */
mbed_official 181:a4cbdfbbd2f4 370 CRS->CR &= ~CRS_CR_TRIM;
mbed_official 181:a4cbdfbbd2f4 371
mbed_official 181:a4cbdfbbd2f4 372 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
mbed_official 181:a4cbdfbbd2f4 373 CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER);
mbed_official 181:a4cbdfbbd2f4 374
mbed_official 181:a4cbdfbbd2f4 375
mbed_official 181:a4cbdfbbd2f4 376 /* START AUTOMATIC SYNCHRONIZATION*/
mbed_official 181:a4cbdfbbd2f4 377
mbed_official 181:a4cbdfbbd2f4 378 /* Enable Automatic trimming */
mbed_official 181:a4cbdfbbd2f4 379 __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
mbed_official 181:a4cbdfbbd2f4 380
mbed_official 181:a4cbdfbbd2f4 381 /* Enable Frequency error counter */
mbed_official 181:a4cbdfbbd2f4 382 __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
mbed_official 181:a4cbdfbbd2f4 383
mbed_official 181:a4cbdfbbd2f4 384 }
mbed_official 181:a4cbdfbbd2f4 385
mbed_official 181:a4cbdfbbd2f4 386 /**
mbed_official 181:a4cbdfbbd2f4 387 * @brief Generate the software synchronization event
mbed_official 181:a4cbdfbbd2f4 388 * @param None
mbed_official 181:a4cbdfbbd2f4 389 * @retval None
mbed_official 181:a4cbdfbbd2f4 390 */
mbed_official 181:a4cbdfbbd2f4 391 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
mbed_official 181:a4cbdfbbd2f4 392 {
mbed_official 181:a4cbdfbbd2f4 393 CRS->CR |= CRS_CR_SWSYNC;
mbed_official 181:a4cbdfbbd2f4 394 }
mbed_official 181:a4cbdfbbd2f4 395
mbed_official 181:a4cbdfbbd2f4 396
mbed_official 181:a4cbdfbbd2f4 397 /**
mbed_official 181:a4cbdfbbd2f4 398 * @brief Function to return synchronization info
mbed_official 181:a4cbdfbbd2f4 399 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
mbed_official 181:a4cbdfbbd2f4 400 * @retval None
mbed_official 181:a4cbdfbbd2f4 401 */
mbed_official 181:a4cbdfbbd2f4 402 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
mbed_official 181:a4cbdfbbd2f4 403 {
mbed_official 181:a4cbdfbbd2f4 404 /* Check the parameter */
mbed_official 181:a4cbdfbbd2f4 405 assert_param(pSynchroInfo != NULL);
mbed_official 181:a4cbdfbbd2f4 406
mbed_official 181:a4cbdfbbd2f4 407 /* Get the reload value */
mbed_official 181:a4cbdfbbd2f4 408 pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
mbed_official 181:a4cbdfbbd2f4 409
mbed_official 181:a4cbdfbbd2f4 410 /* Get HSI48 oscillator smooth trimming */
mbed_official 181:a4cbdfbbd2f4 411 pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
mbed_official 181:a4cbdfbbd2f4 412
mbed_official 181:a4cbdfbbd2f4 413 /* Get Frequency error capture */
mbed_official 181:a4cbdfbbd2f4 414 pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
mbed_official 181:a4cbdfbbd2f4 415
mbed_official 181:a4cbdfbbd2f4 416 /* Get Frequency error direction */
mbed_official 181:a4cbdfbbd2f4 417 pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR);
mbed_official 181:a4cbdfbbd2f4 418
mbed_official 181:a4cbdfbbd2f4 419
mbed_official 181:a4cbdfbbd2f4 420 }
mbed_official 181:a4cbdfbbd2f4 421
mbed_official 181:a4cbdfbbd2f4 422 /**
mbed_official 181:a4cbdfbbd2f4 423 * @brief This function handles CRS Synchronization Timeout.
mbed_official 181:a4cbdfbbd2f4 424 * @param Timeout: Duration of the timeout
mbed_official 181:a4cbdfbbd2f4 425 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
mbed_official 181:a4cbdfbbd2f4 426 * frequency.
mbed_official 181:a4cbdfbbd2f4 427 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
mbed_official 181:a4cbdfbbd2f4 428 * @retval Combination of Synchronization status
mbed_official 181:a4cbdfbbd2f4 429 * This parameter can be a combination of the following values:
mbed_official 181:a4cbdfbbd2f4 430 * @arg RCC_CRS_TIMEOUT
mbed_official 181:a4cbdfbbd2f4 431 * @arg RCC_CRS_SYNCOK
mbed_official 181:a4cbdfbbd2f4 432 * @arg RCC_CRS_SYNCWARM
mbed_official 181:a4cbdfbbd2f4 433 * @arg RCC_CRS_SYNCERR
mbed_official 181:a4cbdfbbd2f4 434 * @arg RCC_CRS_SYNCMISS
mbed_official 181:a4cbdfbbd2f4 435 * @arg RCC_CRS_TRIMOV
mbed_official 181:a4cbdfbbd2f4 436 */
mbed_official 181:a4cbdfbbd2f4 437 RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
mbed_official 181:a4cbdfbbd2f4 438 {
mbed_official 181:a4cbdfbbd2f4 439 RCC_CRSStatusTypeDef crsstatus = RCC_CRS_NONE;
mbed_official 181:a4cbdfbbd2f4 440 uint32_t tickstart = 0;
mbed_official 181:a4cbdfbbd2f4 441
mbed_official 181:a4cbdfbbd2f4 442 /* Get timeout */
mbed_official 181:a4cbdfbbd2f4 443 tickstart = HAL_GetTick();
mbed_official 181:a4cbdfbbd2f4 444
mbed_official 181:a4cbdfbbd2f4 445 /* Check that if one of CRS flags have been set */
mbed_official 181:a4cbdfbbd2f4 446 while(RCC_CRS_NONE == crsstatus)
mbed_official 181:a4cbdfbbd2f4 447 {
mbed_official 181:a4cbdfbbd2f4 448 if(Timeout != HAL_MAX_DELAY)
mbed_official 181:a4cbdfbbd2f4 449 {
mbed_official 181:a4cbdfbbd2f4 450 if((HAL_GetTick() - tickstart ) > Timeout)
mbed_official 181:a4cbdfbbd2f4 451 {
mbed_official 181:a4cbdfbbd2f4 452 crsstatus = RCC_CRS_TIMEOUT;
mbed_official 181:a4cbdfbbd2f4 453 }
mbed_official 181:a4cbdfbbd2f4 454 }
mbed_official 181:a4cbdfbbd2f4 455 /* Check CRS SYNCOK flag */
mbed_official 181:a4cbdfbbd2f4 456 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
mbed_official 181:a4cbdfbbd2f4 457 {
mbed_official 181:a4cbdfbbd2f4 458 /* CRS SYNC event OK */
mbed_official 181:a4cbdfbbd2f4 459 crsstatus |= RCC_CRS_SYNCOK;
mbed_official 181:a4cbdfbbd2f4 460
mbed_official 181:a4cbdfbbd2f4 461 /* Clear CRS SYNC event OK bit */
mbed_official 181:a4cbdfbbd2f4 462 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
mbed_official 181:a4cbdfbbd2f4 463 }
mbed_official 181:a4cbdfbbd2f4 464
mbed_official 181:a4cbdfbbd2f4 465 /* Check CRS SYNCWARN flag */
mbed_official 181:a4cbdfbbd2f4 466 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
mbed_official 181:a4cbdfbbd2f4 467 {
mbed_official 181:a4cbdfbbd2f4 468 /* CRS SYNC warning */
mbed_official 181:a4cbdfbbd2f4 469 crsstatus |= RCC_CRS_SYNCWARM;
mbed_official 181:a4cbdfbbd2f4 470
mbed_official 181:a4cbdfbbd2f4 471 /* Clear CRS SYNCWARN bit */
mbed_official 181:a4cbdfbbd2f4 472 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
mbed_official 181:a4cbdfbbd2f4 473 }
mbed_official 181:a4cbdfbbd2f4 474
mbed_official 181:a4cbdfbbd2f4 475 /* Check CRS TRIM overflow flag */
mbed_official 181:a4cbdfbbd2f4 476 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
mbed_official 181:a4cbdfbbd2f4 477 {
mbed_official 181:a4cbdfbbd2f4 478 /* CRS SYNC Error */
mbed_official 181:a4cbdfbbd2f4 479 crsstatus |= RCC_CRS_TRIMOV;
mbed_official 181:a4cbdfbbd2f4 480
mbed_official 181:a4cbdfbbd2f4 481 /* Clear CRS Error bit */
mbed_official 181:a4cbdfbbd2f4 482 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
mbed_official 181:a4cbdfbbd2f4 483 }
mbed_official 181:a4cbdfbbd2f4 484
mbed_official 181:a4cbdfbbd2f4 485 /* Check CRS Error flag */
mbed_official 181:a4cbdfbbd2f4 486 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
mbed_official 181:a4cbdfbbd2f4 487 {
mbed_official 181:a4cbdfbbd2f4 488 /* CRS SYNC Error */
mbed_official 181:a4cbdfbbd2f4 489 crsstatus |= RCC_CRS_SYNCERR;
mbed_official 181:a4cbdfbbd2f4 490
mbed_official 181:a4cbdfbbd2f4 491 /* Clear CRS Error bit */
mbed_official 181:a4cbdfbbd2f4 492 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
mbed_official 181:a4cbdfbbd2f4 493 }
mbed_official 181:a4cbdfbbd2f4 494
mbed_official 181:a4cbdfbbd2f4 495 /* Check CRS SYNC Missed flag */
mbed_official 181:a4cbdfbbd2f4 496 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
mbed_official 181:a4cbdfbbd2f4 497 {
mbed_official 181:a4cbdfbbd2f4 498 /* CRS SYNC Missed */
mbed_official 181:a4cbdfbbd2f4 499 crsstatus |= RCC_CRS_SYNCMISS;
mbed_official 181:a4cbdfbbd2f4 500
mbed_official 181:a4cbdfbbd2f4 501 /* Clear CRS SYNC Missed bit */
mbed_official 181:a4cbdfbbd2f4 502 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
mbed_official 181:a4cbdfbbd2f4 503 }
mbed_official 181:a4cbdfbbd2f4 504
mbed_official 181:a4cbdfbbd2f4 505 /* Check CRS Expected SYNC flag */
mbed_official 181:a4cbdfbbd2f4 506 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
mbed_official 181:a4cbdfbbd2f4 507 {
mbed_official 181:a4cbdfbbd2f4 508 /* frequency error counter reached a zero value */
mbed_official 181:a4cbdfbbd2f4 509 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
mbed_official 181:a4cbdfbbd2f4 510 }
mbed_official 181:a4cbdfbbd2f4 511 }
mbed_official 181:a4cbdfbbd2f4 512
mbed_official 181:a4cbdfbbd2f4 513 return crsstatus;
mbed_official 181:a4cbdfbbd2f4 514 }
mbed_official 181:a4cbdfbbd2f4 515
mbed_official 181:a4cbdfbbd2f4 516 #endif /* !(STM32L051xx) && !(STM32L061xx) */
mbed_official 181:a4cbdfbbd2f4 517
mbed_official 181:a4cbdfbbd2f4 518 /**
mbed_official 181:a4cbdfbbd2f4 519 * @}
mbed_official 181:a4cbdfbbd2f4 520 */
mbed_official 181:a4cbdfbbd2f4 521
mbed_official 181:a4cbdfbbd2f4 522 /**
mbed_official 181:a4cbdfbbd2f4 523 * @}
mbed_official 181:a4cbdfbbd2f4 524 */
mbed_official 181:a4cbdfbbd2f4 525
mbed_official 181:a4cbdfbbd2f4 526 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 181:a4cbdfbbd2f4 527 /**
mbed_official 181:a4cbdfbbd2f4 528 * @}
mbed_official 181:a4cbdfbbd2f4 529 */
mbed_official 181:a4cbdfbbd2f4 530
mbed_official 181:a4cbdfbbd2f4 531 /**
mbed_official 181:a4cbdfbbd2f4 532 * @}
mbed_official 181:a4cbdfbbd2f4 533 */
mbed_official 181:a4cbdfbbd2f4 534
mbed_official 181:a4cbdfbbd2f4 535 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/