shao ziyang
mbed library sources
Dependents: frdm_kl05z_gpio_test
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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc_ex.c@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 235:685d5f11838f
test with CLOCK_SETUP = 0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 235:685d5f11838f | 1 | /** |
| mbed_official | 235:685d5f11838f | 2 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 3 | * @file stm32f4xx_hal_rcc_ex.c |
| mbed_official | 235:685d5f11838f | 4 | * @author MCD Application Team |
| mbed_official | 235:685d5f11838f | 5 | * @version V1.1.0 |
| mbed_official | 235:685d5f11838f | 6 | * @date 19-June-2014 |
| mbed_official | 235:685d5f11838f | 7 | * @brief Extension RCC HAL module driver. |
| mbed_official | 235:685d5f11838f | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 235:685d5f11838f | 9 | * functionalities RCC extension peripheral: |
| mbed_official | 235:685d5f11838f | 10 | * + Extended Peripheral Control functions |
| mbed_official | 235:685d5f11838f | 11 | * |
| mbed_official | 235:685d5f11838f | 12 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 13 | * @attention |
| mbed_official | 235:685d5f11838f | 14 | * |
| mbed_official | 235:685d5f11838f | 15 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 235:685d5f11838f | 16 | * |
| mbed_official | 235:685d5f11838f | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 235:685d5f11838f | 18 | * are permitted provided that the following conditions are met: |
| mbed_official | 235:685d5f11838f | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 235:685d5f11838f | 20 | * this list of conditions and the following disclaimer. |
| mbed_official | 235:685d5f11838f | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 235:685d5f11838f | 22 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 235:685d5f11838f | 23 | * and/or other materials provided with the distribution. |
| mbed_official | 235:685d5f11838f | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 235:685d5f11838f | 25 | * may be used to endorse or promote products derived from this software |
| mbed_official | 235:685d5f11838f | 26 | * without specific prior written permission. |
| mbed_official | 235:685d5f11838f | 27 | * |
| mbed_official | 235:685d5f11838f | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 235:685d5f11838f | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 235:685d5f11838f | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 235:685d5f11838f | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 235:685d5f11838f | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 235:685d5f11838f | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 235:685d5f11838f | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 235:685d5f11838f | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 235:685d5f11838f | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 235:685d5f11838f | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 235:685d5f11838f | 38 | * |
| mbed_official | 235:685d5f11838f | 39 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 40 | */ |
| mbed_official | 235:685d5f11838f | 41 | |
| mbed_official | 235:685d5f11838f | 42 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 43 | #include "stm32f4xx_hal.h" |
| mbed_official | 235:685d5f11838f | 44 | |
| mbed_official | 235:685d5f11838f | 45 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 235:685d5f11838f | 46 | * @{ |
| mbed_official | 235:685d5f11838f | 47 | */ |
| mbed_official | 235:685d5f11838f | 48 | |
| mbed_official | 235:685d5f11838f | 49 | /** @defgroup RCC |
| mbed_official | 235:685d5f11838f | 50 | * @brief RCC HAL module driver |
| mbed_official | 235:685d5f11838f | 51 | * @{ |
| mbed_official | 235:685d5f11838f | 52 | */ |
| mbed_official | 235:685d5f11838f | 53 | |
| mbed_official | 235:685d5f11838f | 54 | #ifdef HAL_RCC_MODULE_ENABLED |
| mbed_official | 235:685d5f11838f | 55 | |
| mbed_official | 235:685d5f11838f | 56 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 57 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 58 | #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
| mbed_official | 235:685d5f11838f | 59 | #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
| mbed_official | 235:685d5f11838f | 60 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 61 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 62 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 63 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 64 | |
| mbed_official | 235:685d5f11838f | 65 | /** @defgroup RCCEx_Private_Functions |
| mbed_official | 235:685d5f11838f | 66 | * @{ |
| mbed_official | 235:685d5f11838f | 67 | */ |
| mbed_official | 235:685d5f11838f | 68 | |
| mbed_official | 235:685d5f11838f | 69 | /** @defgroup RCCEx_Group1 Extended Peripheral Control functions |
| mbed_official | 235:685d5f11838f | 70 | * @brief Extended Peripheral Control functions |
| mbed_official | 235:685d5f11838f | 71 | * |
| mbed_official | 235:685d5f11838f | 72 | @verbatim |
| mbed_official | 235:685d5f11838f | 73 | =============================================================================== |
| mbed_official | 235:685d5f11838f | 74 | ##### Extended Peripheral Control functions ##### |
| mbed_official | 235:685d5f11838f | 75 | =============================================================================== |
| mbed_official | 235:685d5f11838f | 76 | [..] |
| mbed_official | 235:685d5f11838f | 77 | This subsection provides a set of functions allowing to control the RCC Clocks |
| mbed_official | 235:685d5f11838f | 78 | frequencies. |
| mbed_official | 235:685d5f11838f | 79 | [..] |
| mbed_official | 235:685d5f11838f | 80 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
| mbed_official | 235:685d5f11838f | 81 | select the RTC clock source; in this case the Backup domain will be reset in |
| mbed_official | 235:685d5f11838f | 82 | order to modify the RTC Clock source, as consequence RTC registers (including |
| mbed_official | 235:685d5f11838f | 83 | the backup registers) and RCC_BDCR register are set to their reset values. |
| mbed_official | 235:685d5f11838f | 84 | |
| mbed_official | 235:685d5f11838f | 85 | @endverbatim |
| mbed_official | 235:685d5f11838f | 86 | * @{ |
| mbed_official | 235:685d5f11838f | 87 | */ |
| mbed_official | 235:685d5f11838f | 88 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 89 | /** |
| mbed_official | 235:685d5f11838f | 90 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
| mbed_official | 235:685d5f11838f | 91 | * parameters in the RCC_PeriphCLKInitTypeDef. |
| mbed_official | 235:685d5f11838f | 92 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| mbed_official | 235:685d5f11838f | 93 | * contains the configuration information for the Extended Peripherals |
| mbed_official | 235:685d5f11838f | 94 | * clocks(I2S, SAI, LTDC RTC and TIM). |
| mbed_official | 235:685d5f11838f | 95 | * |
| mbed_official | 235:685d5f11838f | 96 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
| mbed_official | 235:685d5f11838f | 97 | * the RTC clock source; in this case the Backup domain will be reset in |
| mbed_official | 235:685d5f11838f | 98 | * order to modify the RTC Clock source, as consequence RTC registers (including |
| mbed_official | 235:685d5f11838f | 99 | * the backup registers) and RCC_BDCR register are set to their reset values. |
| mbed_official | 235:685d5f11838f | 100 | * |
| mbed_official | 235:685d5f11838f | 101 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 102 | */ |
| mbed_official | 235:685d5f11838f | 103 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| mbed_official | 235:685d5f11838f | 104 | { |
| mbed_official | 235:685d5f11838f | 105 | uint32_t tickstart = 0; |
| mbed_official | 235:685d5f11838f | 106 | uint32_t tmpreg = 0; |
| mbed_official | 235:685d5f11838f | 107 | |
| mbed_official | 235:685d5f11838f | 108 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 109 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
| mbed_official | 235:685d5f11838f | 110 | |
| mbed_official | 235:685d5f11838f | 111 | /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/ |
| mbed_official | 235:685d5f11838f | 112 | |
| mbed_official | 235:685d5f11838f | 113 | /*----------------------- Common configuration SAI/I2S ---------------------------*/ |
| mbed_official | 235:685d5f11838f | 114 | /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division |
| mbed_official | 235:685d5f11838f | 115 | factor is common parameters for both peripherals */ |
| mbed_official | 235:685d5f11838f | 116 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || |
| mbed_official | 235:685d5f11838f | 117 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S)) |
| mbed_official | 235:685d5f11838f | 118 | { |
| mbed_official | 235:685d5f11838f | 119 | /* check for Parameters */ |
| mbed_official | 235:685d5f11838f | 120 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
| mbed_official | 235:685d5f11838f | 121 | |
| mbed_official | 235:685d5f11838f | 122 | /* Disable the PLLI2S */ |
| mbed_official | 235:685d5f11838f | 123 | __HAL_RCC_PLLI2S_DISABLE(); |
| mbed_official | 235:685d5f11838f | 124 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 125 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 126 | /* Wait till PLLI2S is disabled */ |
| mbed_official | 235:685d5f11838f | 127 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
| mbed_official | 235:685d5f11838f | 128 | { |
| mbed_official | 235:685d5f11838f | 129 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 130 | { |
| mbed_official | 235:685d5f11838f | 131 | /* return in case of Timeout detected */ |
| mbed_official | 235:685d5f11838f | 132 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 133 | } |
| mbed_official | 235:685d5f11838f | 134 | } |
| mbed_official | 235:685d5f11838f | 135 | |
| mbed_official | 235:685d5f11838f | 136 | /*---------------------------- I2S configuration -------------------------------*/ |
| mbed_official | 235:685d5f11838f | 137 | /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added |
| mbed_official | 235:685d5f11838f | 138 | only for I2S configuration */ |
| mbed_official | 235:685d5f11838f | 139 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) |
| mbed_official | 235:685d5f11838f | 140 | { |
| mbed_official | 235:685d5f11838f | 141 | /* check for Parameters */ |
| mbed_official | 235:685d5f11838f | 142 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
| mbed_official | 235:685d5f11838f | 143 | /* Configure the PLLI2S division factors */ |
| mbed_official | 235:685d5f11838f | 144 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */ |
| mbed_official | 235:685d5f11838f | 145 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
| mbed_official | 235:685d5f11838f | 146 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); |
| mbed_official | 235:685d5f11838f | 147 | } |
| mbed_official | 235:685d5f11838f | 148 | |
| mbed_official | 235:685d5f11838f | 149 | /*---------------------------- SAI configuration -------------------------------*/ |
| mbed_official | 235:685d5f11838f | 150 | /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must |
| mbed_official | 235:685d5f11838f | 151 | be added only for SAI configuration */ |
| mbed_official | 235:685d5f11838f | 152 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) |
| mbed_official | 235:685d5f11838f | 153 | { |
| mbed_official | 235:685d5f11838f | 154 | /* Check the PLLI2S division factors */ |
| mbed_official | 235:685d5f11838f | 155 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); |
| mbed_official | 235:685d5f11838f | 156 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); |
| mbed_official | 235:685d5f11838f | 157 | |
| mbed_official | 235:685d5f11838f | 158 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ |
| mbed_official | 235:685d5f11838f | 159 | tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
| mbed_official | 235:685d5f11838f | 160 | /* Configure the PLLI2S division factors */ |
| mbed_official | 235:685d5f11838f | 161 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 235:685d5f11838f | 162 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| mbed_official | 235:685d5f11838f | 163 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
| mbed_official | 235:685d5f11838f | 164 | __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg); |
| mbed_official | 235:685d5f11838f | 165 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
| mbed_official | 235:685d5f11838f | 166 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); |
| mbed_official | 235:685d5f11838f | 167 | } |
| mbed_official | 235:685d5f11838f | 168 | |
| mbed_official | 235:685d5f11838f | 169 | /* Enable the PLLI2S */ |
| mbed_official | 235:685d5f11838f | 170 | __HAL_RCC_PLLI2S_ENABLE(); |
| mbed_official | 235:685d5f11838f | 171 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 172 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 173 | /* Wait till PLLI2S is ready */ |
| mbed_official | 235:685d5f11838f | 174 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
| mbed_official | 235:685d5f11838f | 175 | { |
| mbed_official | 235:685d5f11838f | 176 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 177 | { |
| mbed_official | 235:685d5f11838f | 178 | /* return in case of Timeout detected */ |
| mbed_official | 235:685d5f11838f | 179 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 180 | } |
| mbed_official | 235:685d5f11838f | 181 | } |
| mbed_official | 235:685d5f11838f | 182 | } |
| mbed_official | 235:685d5f11838f | 183 | |
| mbed_official | 235:685d5f11838f | 184 | /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ |
| mbed_official | 235:685d5f11838f | 185 | |
| mbed_official | 235:685d5f11838f | 186 | /*----------------------- Common configuration SAI/LTDC --------------------*/ |
| mbed_official | 235:685d5f11838f | 187 | /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division |
| mbed_official | 235:685d5f11838f | 188 | factor is common parameters for both peripherals */ |
| mbed_official | 235:685d5f11838f | 189 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || |
| mbed_official | 235:685d5f11838f | 190 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) |
| mbed_official | 235:685d5f11838f | 191 | { |
| mbed_official | 235:685d5f11838f | 192 | /* Check the PLLSAI division factors */ |
| mbed_official | 235:685d5f11838f | 193 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); |
| mbed_official | 235:685d5f11838f | 194 | |
| mbed_official | 235:685d5f11838f | 195 | /* Disable PLLSAI Clock */ |
| mbed_official | 235:685d5f11838f | 196 | __HAL_RCC_PLLSAI_DISABLE(); |
| mbed_official | 235:685d5f11838f | 197 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 198 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 199 | /* Wait till PLLSAI is disabled */ |
| mbed_official | 235:685d5f11838f | 200 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) |
| mbed_official | 235:685d5f11838f | 201 | { |
| mbed_official | 235:685d5f11838f | 202 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 203 | { |
| mbed_official | 235:685d5f11838f | 204 | /* return in case of Timeout detected */ |
| mbed_official | 235:685d5f11838f | 205 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 206 | } |
| mbed_official | 235:685d5f11838f | 207 | } |
| mbed_official | 235:685d5f11838f | 208 | |
| mbed_official | 235:685d5f11838f | 209 | /*---------------------------- SAI configuration -------------------------*/ |
| mbed_official | 235:685d5f11838f | 210 | /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must |
| mbed_official | 235:685d5f11838f | 211 | be added only for SAI configuration */ |
| mbed_official | 235:685d5f11838f | 212 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) |
| mbed_official | 235:685d5f11838f | 213 | { |
| mbed_official | 235:685d5f11838f | 214 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); |
| mbed_official | 235:685d5f11838f | 215 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); |
| mbed_official | 235:685d5f11838f | 216 | |
| mbed_official | 235:685d5f11838f | 217 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ |
| mbed_official | 235:685d5f11838f | 218 | tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
| mbed_official | 235:685d5f11838f | 219 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 235:685d5f11838f | 220 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
| mbed_official | 235:685d5f11838f | 221 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
| mbed_official | 235:685d5f11838f | 222 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg); |
| mbed_official | 235:685d5f11838f | 223 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
| mbed_official | 235:685d5f11838f | 224 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); |
| mbed_official | 235:685d5f11838f | 225 | } |
| mbed_official | 235:685d5f11838f | 226 | |
| mbed_official | 235:685d5f11838f | 227 | /*---------------------------- LTDC configuration ------------------------*/ |
| mbed_official | 235:685d5f11838f | 228 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) |
| mbed_official | 235:685d5f11838f | 229 | { |
| mbed_official | 235:685d5f11838f | 230 | assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); |
| mbed_official | 235:685d5f11838f | 231 | assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); |
| mbed_official | 235:685d5f11838f | 232 | |
| mbed_official | 235:685d5f11838f | 233 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ |
| mbed_official | 235:685d5f11838f | 234 | tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
| mbed_official | 235:685d5f11838f | 235 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 235:685d5f11838f | 236 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
| mbed_official | 235:685d5f11838f | 237 | /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ |
| mbed_official | 235:685d5f11838f | 238 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR); |
| mbed_official | 235:685d5f11838f | 239 | /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ |
| mbed_official | 235:685d5f11838f | 240 | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); |
| mbed_official | 235:685d5f11838f | 241 | } |
| mbed_official | 235:685d5f11838f | 242 | /* Enable PLLSAI Clock */ |
| mbed_official | 235:685d5f11838f | 243 | __HAL_RCC_PLLSAI_ENABLE(); |
| mbed_official | 235:685d5f11838f | 244 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 245 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 246 | /* Wait till PLLSAI is ready */ |
| mbed_official | 235:685d5f11838f | 247 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) |
| mbed_official | 235:685d5f11838f | 248 | { |
| mbed_official | 235:685d5f11838f | 249 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 250 | { |
| mbed_official | 235:685d5f11838f | 251 | /* return in case of Timeout detected */ |
| mbed_official | 235:685d5f11838f | 252 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 253 | } |
| mbed_official | 235:685d5f11838f | 254 | } |
| mbed_official | 235:685d5f11838f | 255 | } |
| mbed_official | 235:685d5f11838f | 256 | |
| mbed_official | 235:685d5f11838f | 257 | |
| mbed_official | 235:685d5f11838f | 258 | /*---------------------------- RTC configuration ---------------------------*/ |
| mbed_official | 235:685d5f11838f | 259 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
| mbed_official | 235:685d5f11838f | 260 | { |
| mbed_official | 235:685d5f11838f | 261 | /* Enable Power Clock*/ |
| mbed_official | 235:685d5f11838f | 262 | __PWR_CLK_ENABLE(); |
| mbed_official | 235:685d5f11838f | 263 | |
| mbed_official | 235:685d5f11838f | 264 | /* Enable write access to Backup domain */ |
| mbed_official | 235:685d5f11838f | 265 | PWR->CR |= PWR_CR_DBP; |
| mbed_official | 235:685d5f11838f | 266 | |
| mbed_official | 235:685d5f11838f | 267 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 268 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 269 | |
| mbed_official | 235:685d5f11838f | 270 | while((PWR->CR & PWR_CR_DBP) == RESET) |
| mbed_official | 235:685d5f11838f | 271 | { |
| mbed_official | 235:685d5f11838f | 272 | if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 273 | { |
| mbed_official | 235:685d5f11838f | 274 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 275 | } |
| mbed_official | 235:685d5f11838f | 276 | } |
| mbed_official | 235:685d5f11838f | 277 | |
| mbed_official | 235:685d5f11838f | 278 | /* Reset the Backup domain only if the RTC Clock source selction is modified */ |
| mbed_official | 235:685d5f11838f | 279 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
| mbed_official | 235:685d5f11838f | 280 | { |
| mbed_official | 235:685d5f11838f | 281 | /* Store the content of BDCR register before the reset of Backup Domain */ |
| mbed_official | 235:685d5f11838f | 282 | tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
| mbed_official | 235:685d5f11838f | 283 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
| mbed_official | 235:685d5f11838f | 284 | __HAL_RCC_BACKUPRESET_FORCE(); |
| mbed_official | 235:685d5f11838f | 285 | __HAL_RCC_BACKUPRESET_RELEASE(); |
| mbed_official | 235:685d5f11838f | 286 | /* Restore the Content of BDCR register */ |
| mbed_official | 235:685d5f11838f | 287 | RCC->BDCR = tmpreg; |
| mbed_official | 235:685d5f11838f | 288 | } |
| mbed_official | 235:685d5f11838f | 289 | |
| mbed_official | 235:685d5f11838f | 290 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
| mbed_official | 235:685d5f11838f | 291 | if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) |
| mbed_official | 235:685d5f11838f | 292 | { |
| mbed_official | 235:685d5f11838f | 293 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 294 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 295 | |
| mbed_official | 235:685d5f11838f | 296 | /* Wait till LSE is ready */ |
| mbed_official | 235:685d5f11838f | 297 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
| mbed_official | 235:685d5f11838f | 298 | { |
| mbed_official | 235:685d5f11838f | 299 | if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 300 | { |
| mbed_official | 235:685d5f11838f | 301 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 302 | } |
| mbed_official | 235:685d5f11838f | 303 | } |
| mbed_official | 235:685d5f11838f | 304 | } |
| mbed_official | 235:685d5f11838f | 305 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
| mbed_official | 235:685d5f11838f | 306 | } |
| mbed_official | 235:685d5f11838f | 307 | |
| mbed_official | 235:685d5f11838f | 308 | /*---------------------------- TIM configuration ---------------------------*/ |
| mbed_official | 235:685d5f11838f | 309 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) |
| mbed_official | 235:685d5f11838f | 310 | { |
| mbed_official | 235:685d5f11838f | 311 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); |
| mbed_official | 235:685d5f11838f | 312 | } |
| mbed_official | 235:685d5f11838f | 313 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 314 | } |
| mbed_official | 235:685d5f11838f | 315 | |
| mbed_official | 235:685d5f11838f | 316 | /** |
| mbed_official | 235:685d5f11838f | 317 | * @brief Configures the RCC_OscInitStruct according to the internal |
| mbed_official | 235:685d5f11838f | 318 | * RCC configuration registers. |
| mbed_official | 235:685d5f11838f | 319 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| mbed_official | 235:685d5f11838f | 320 | * will be configured. |
| mbed_official | 235:685d5f11838f | 321 | * @retval None |
| mbed_official | 235:685d5f11838f | 322 | */ |
| mbed_official | 235:685d5f11838f | 323 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| mbed_official | 235:685d5f11838f | 324 | { |
| mbed_official | 235:685d5f11838f | 325 | uint32_t tempreg; |
| mbed_official | 235:685d5f11838f | 326 | |
| mbed_official | 235:685d5f11838f | 327 | /* Set all possible values for the extended clock type parameter------------*/ |
| mbed_official | 235:685d5f11838f | 328 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; |
| mbed_official | 235:685d5f11838f | 329 | |
| mbed_official | 235:685d5f11838f | 330 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 331 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); |
| mbed_official | 235:685d5f11838f | 332 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
| mbed_official | 235:685d5f11838f | 333 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
| mbed_official | 235:685d5f11838f | 334 | /* Get the PLLSAI Clock configuration -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 335 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); |
| mbed_official | 235:685d5f11838f | 336 | PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
| mbed_official | 235:685d5f11838f | 337 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
| mbed_official | 235:685d5f11838f | 338 | /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 339 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); |
| mbed_official | 235:685d5f11838f | 340 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); |
| mbed_official | 235:685d5f11838f | 341 | PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); |
| mbed_official | 235:685d5f11838f | 342 | /* Get the RTC Clock configuration -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 343 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); |
| mbed_official | 235:685d5f11838f | 344 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); |
| mbed_official | 235:685d5f11838f | 345 | |
| mbed_official | 235:685d5f11838f | 346 | if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) |
| mbed_official | 235:685d5f11838f | 347 | { |
| mbed_official | 235:685d5f11838f | 348 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; |
| mbed_official | 235:685d5f11838f | 349 | } |
| mbed_official | 235:685d5f11838f | 350 | else |
| mbed_official | 235:685d5f11838f | 351 | { |
| mbed_official | 235:685d5f11838f | 352 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; |
| mbed_official | 235:685d5f11838f | 353 | } |
| mbed_official | 235:685d5f11838f | 354 | } |
| mbed_official | 235:685d5f11838f | 355 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 356 | |
| mbed_official | 235:685d5f11838f | 357 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ |
| mbed_official | 235:685d5f11838f | 358 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 359 | /** |
| mbed_official | 235:685d5f11838f | 360 | * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the |
| mbed_official | 235:685d5f11838f | 361 | * RCC_PeriphCLKInitTypeDef. |
| mbed_official | 235:685d5f11838f | 362 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| mbed_official | 235:685d5f11838f | 363 | * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). |
| mbed_official | 235:685d5f11838f | 364 | * |
| mbed_official | 235:685d5f11838f | 365 | * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case |
| mbed_official | 235:685d5f11838f | 366 | * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup |
| mbed_official | 235:685d5f11838f | 367 | * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset |
| mbed_official | 235:685d5f11838f | 368 | * |
| mbed_official | 235:685d5f11838f | 369 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 370 | */ |
| mbed_official | 235:685d5f11838f | 371 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| mbed_official | 235:685d5f11838f | 372 | { |
| mbed_official | 235:685d5f11838f | 373 | uint32_t tickstart = 0; |
| mbed_official | 235:685d5f11838f | 374 | uint32_t tmpreg = 0; |
| mbed_official | 235:685d5f11838f | 375 | |
| mbed_official | 235:685d5f11838f | 376 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 377 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
| mbed_official | 235:685d5f11838f | 378 | |
| mbed_official | 235:685d5f11838f | 379 | /*---------------------------- I2S configuration ---------------------------*/ |
| mbed_official | 235:685d5f11838f | 380 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) |
| mbed_official | 235:685d5f11838f | 381 | { |
| mbed_official | 235:685d5f11838f | 382 | /* check for Parameters */ |
| mbed_official | 235:685d5f11838f | 383 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
| mbed_official | 235:685d5f11838f | 384 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
| mbed_official | 235:685d5f11838f | 385 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 386 | assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); |
| mbed_official | 235:685d5f11838f | 387 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 388 | /* Disable the PLLI2S */ |
| mbed_official | 235:685d5f11838f | 389 | __HAL_RCC_PLLI2S_DISABLE(); |
| mbed_official | 235:685d5f11838f | 390 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 391 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 392 | /* Wait till PLLI2S is disabled */ |
| mbed_official | 235:685d5f11838f | 393 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
| mbed_official | 235:685d5f11838f | 394 | { |
| mbed_official | 235:685d5f11838f | 395 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 396 | { |
| mbed_official | 235:685d5f11838f | 397 | /* return in case of Timeout detected */ |
| mbed_official | 235:685d5f11838f | 398 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 399 | } |
| mbed_official | 235:685d5f11838f | 400 | } |
| mbed_official | 235:685d5f11838f | 401 | |
| mbed_official | 235:685d5f11838f | 402 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 403 | /* Configure the PLLI2S division factors */ |
| mbed_official | 235:685d5f11838f | 404 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */ |
| mbed_official | 235:685d5f11838f | 405 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
| mbed_official | 235:685d5f11838f | 406 | __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); |
| mbed_official | 235:685d5f11838f | 407 | #else |
| mbed_official | 235:685d5f11838f | 408 | /* Configure the PLLI2S division factors */ |
| mbed_official | 235:685d5f11838f | 409 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */ |
| mbed_official | 235:685d5f11838f | 410 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
| mbed_official | 235:685d5f11838f | 411 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); |
| mbed_official | 235:685d5f11838f | 412 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 413 | |
| mbed_official | 235:685d5f11838f | 414 | /* Enable the PLLI2S */ |
| mbed_official | 235:685d5f11838f | 415 | __HAL_RCC_PLLI2S_ENABLE(); |
| mbed_official | 235:685d5f11838f | 416 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 417 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 418 | /* Wait till PLLI2S is ready */ |
| mbed_official | 235:685d5f11838f | 419 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
| mbed_official | 235:685d5f11838f | 420 | { |
| mbed_official | 235:685d5f11838f | 421 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 422 | { |
| mbed_official | 235:685d5f11838f | 423 | /* return in case of Timeout detected */ |
| mbed_official | 235:685d5f11838f | 424 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 425 | } |
| mbed_official | 235:685d5f11838f | 426 | } |
| mbed_official | 235:685d5f11838f | 427 | } |
| mbed_official | 235:685d5f11838f | 428 | |
| mbed_official | 235:685d5f11838f | 429 | /*---------------------------- RTC configuration ---------------------------*/ |
| mbed_official | 235:685d5f11838f | 430 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
| mbed_official | 235:685d5f11838f | 431 | { |
| mbed_official | 235:685d5f11838f | 432 | /* Enable Power Clock*/ |
| mbed_official | 235:685d5f11838f | 433 | __PWR_CLK_ENABLE(); |
| mbed_official | 235:685d5f11838f | 434 | |
| mbed_official | 235:685d5f11838f | 435 | /* Enable write access to Backup domain */ |
| mbed_official | 235:685d5f11838f | 436 | PWR->CR |= PWR_CR_DBP; |
| mbed_official | 235:685d5f11838f | 437 | |
| mbed_official | 235:685d5f11838f | 438 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 439 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 440 | |
| mbed_official | 235:685d5f11838f | 441 | while((PWR->CR & PWR_CR_DBP) == RESET) |
| mbed_official | 235:685d5f11838f | 442 | { |
| mbed_official | 235:685d5f11838f | 443 | if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 444 | { |
| mbed_official | 235:685d5f11838f | 445 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 446 | } |
| mbed_official | 235:685d5f11838f | 447 | } |
| mbed_official | 235:685d5f11838f | 448 | |
| mbed_official | 235:685d5f11838f | 449 | /* Reset the Backup domain only if the RTC Clock source selction is modified */ |
| mbed_official | 235:685d5f11838f | 450 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
| mbed_official | 235:685d5f11838f | 451 | { |
| mbed_official | 235:685d5f11838f | 452 | /* Store the content of BDCR register before the reset of Backup Domain */ |
| mbed_official | 235:685d5f11838f | 453 | tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
| mbed_official | 235:685d5f11838f | 454 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
| mbed_official | 235:685d5f11838f | 455 | __HAL_RCC_BACKUPRESET_FORCE(); |
| mbed_official | 235:685d5f11838f | 456 | __HAL_RCC_BACKUPRESET_RELEASE(); |
| mbed_official | 235:685d5f11838f | 457 | /* Restore the Content of BDCR register */ |
| mbed_official | 235:685d5f11838f | 458 | RCC->BDCR = tmpreg; |
| mbed_official | 235:685d5f11838f | 459 | } |
| mbed_official | 235:685d5f11838f | 460 | |
| mbed_official | 235:685d5f11838f | 461 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
| mbed_official | 235:685d5f11838f | 462 | if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) |
| mbed_official | 235:685d5f11838f | 463 | { |
| mbed_official | 235:685d5f11838f | 464 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 465 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 466 | |
| mbed_official | 235:685d5f11838f | 467 | /* Wait till LSE is ready */ |
| mbed_official | 235:685d5f11838f | 468 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
| mbed_official | 235:685d5f11838f | 469 | { |
| mbed_official | 235:685d5f11838f | 470 | if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) |
| mbed_official | 235:685d5f11838f | 471 | { |
| mbed_official | 235:685d5f11838f | 472 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 473 | } |
| mbed_official | 235:685d5f11838f | 474 | } |
| mbed_official | 235:685d5f11838f | 475 | } |
| mbed_official | 235:685d5f11838f | 476 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
| mbed_official | 235:685d5f11838f | 477 | } |
| mbed_official | 235:685d5f11838f | 478 | |
| mbed_official | 235:685d5f11838f | 479 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 480 | } |
| mbed_official | 235:685d5f11838f | 481 | |
| mbed_official | 235:685d5f11838f | 482 | /** |
| mbed_official | 235:685d5f11838f | 483 | * @brief Configures the RCC_OscInitStruct according to the internal |
| mbed_official | 235:685d5f11838f | 484 | * RCC configuration registers. |
| mbed_official | 235:685d5f11838f | 485 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| mbed_official | 235:685d5f11838f | 486 | * will be configured. |
| mbed_official | 235:685d5f11838f | 487 | * @retval None |
| mbed_official | 235:685d5f11838f | 488 | */ |
| mbed_official | 235:685d5f11838f | 489 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| mbed_official | 235:685d5f11838f | 490 | { |
| mbed_official | 235:685d5f11838f | 491 | uint32_t tempreg; |
| mbed_official | 235:685d5f11838f | 492 | |
| mbed_official | 235:685d5f11838f | 493 | /* Set all possible values for the extended clock type parameter------------*/ |
| mbed_official | 235:685d5f11838f | 494 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; |
| mbed_official | 235:685d5f11838f | 495 | |
| mbed_official | 235:685d5f11838f | 496 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 497 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); |
| mbed_official | 235:685d5f11838f | 498 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
| mbed_official | 235:685d5f11838f | 499 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 500 | PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); |
| mbed_official | 235:685d5f11838f | 501 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 502 | /* Get the RTC Clock configuration -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 503 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); |
| mbed_official | 235:685d5f11838f | 504 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); |
| mbed_official | 235:685d5f11838f | 505 | |
| mbed_official | 235:685d5f11838f | 506 | } |
| mbed_official | 235:685d5f11838f | 507 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 508 | |
| mbed_official | 235:685d5f11838f | 509 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 510 | /** |
| mbed_official | 235:685d5f11838f | 511 | * @brief Select LSE mode |
| mbed_official | 235:685d5f11838f | 512 | * |
| mbed_official | 235:685d5f11838f | 513 | * @note This mode is only available for STM32F411xx devices. |
| mbed_official | 235:685d5f11838f | 514 | * |
| mbed_official | 235:685d5f11838f | 515 | * @param Mode: specifies the LSE mode. |
| mbed_official | 235:685d5f11838f | 516 | * This parameter can be one of the following values: |
| mbed_official | 235:685d5f11838f | 517 | * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection |
| mbed_official | 235:685d5f11838f | 518 | * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection |
| mbed_official | 235:685d5f11838f | 519 | * @retval None |
| mbed_official | 235:685d5f11838f | 520 | */ |
| mbed_official | 235:685d5f11838f | 521 | void HAL_RCCEx_SelectLSEMode(uint8_t Mode) |
| mbed_official | 235:685d5f11838f | 522 | { |
| mbed_official | 235:685d5f11838f | 523 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 524 | assert_param(IS_RCC_LSE_MODE(Mode)); |
| mbed_official | 235:685d5f11838f | 525 | if(Mode == RCC_LSE_HIGHDRIVE_MODE) |
| mbed_official | 235:685d5f11838f | 526 | { |
| mbed_official | 235:685d5f11838f | 527 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); |
| mbed_official | 235:685d5f11838f | 528 | } |
| mbed_official | 235:685d5f11838f | 529 | else |
| mbed_official | 235:685d5f11838f | 530 | { |
| mbed_official | 235:685d5f11838f | 531 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); |
| mbed_official | 235:685d5f11838f | 532 | } |
| mbed_official | 235:685d5f11838f | 533 | } |
| mbed_official | 235:685d5f11838f | 534 | |
| mbed_official | 235:685d5f11838f | 535 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 536 | |
| mbed_official | 235:685d5f11838f | 537 | /** |
| mbed_official | 235:685d5f11838f | 538 | * @} |
| mbed_official | 235:685d5f11838f | 539 | */ |
| mbed_official | 235:685d5f11838f | 540 | |
| mbed_official | 235:685d5f11838f | 541 | /** |
| mbed_official | 235:685d5f11838f | 542 | * @} |
| mbed_official | 235:685d5f11838f | 543 | */ |
| mbed_official | 235:685d5f11838f | 544 | |
| mbed_official | 235:685d5f11838f | 545 | #endif /* HAL_RCC_MODULE_ENABLED */ |
| mbed_official | 235:685d5f11838f | 546 | /** |
| mbed_official | 235:685d5f11838f | 547 | * @} |
| mbed_official | 235:685d5f11838f | 548 | */ |
| mbed_official | 235:685d5f11838f | 549 | |
| mbed_official | 235:685d5f11838f | 550 | /** |
| mbed_official | 235:685d5f11838f | 551 | * @} |
| mbed_official | 235:685d5f11838f | 552 | */ |
| mbed_official | 235:685d5f11838f | 553 | |
| mbed_official | 235:685d5f11838f | 554 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |