shao ziyang / mbed-src-kl05

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_eth.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
235:685d5f11838f 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 235:685d5f11838f 1 /**
mbed_official 235:685d5f11838f 2 ******************************************************************************
mbed_official 235:685d5f11838f 3 * @file stm32f4xx_hal_eth.h
mbed_official 235:685d5f11838f 4 * @author MCD Application Team
mbed_official 235:685d5f11838f 5 * @version V1.1.0
mbed_official 235:685d5f11838f 6 * @date 19-June-2014
mbed_official 235:685d5f11838f 7 * @brief Header file of ETH HAL module.
mbed_official 235:685d5f11838f 8 ******************************************************************************
mbed_official 235:685d5f11838f 9 * @attention
mbed_official 235:685d5f11838f 10 *
mbed_official 235:685d5f11838f 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 235:685d5f11838f 12 *
mbed_official 235:685d5f11838f 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 235:685d5f11838f 14 * are permitted provided that the following conditions are met:
mbed_official 235:685d5f11838f 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 235:685d5f11838f 16 * this list of conditions and the following disclaimer.
mbed_official 235:685d5f11838f 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 235:685d5f11838f 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 235:685d5f11838f 19 * and/or other materials provided with the distribution.
mbed_official 235:685d5f11838f 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 235:685d5f11838f 21 * may be used to endorse or promote products derived from this software
mbed_official 235:685d5f11838f 22 * without specific prior written permission.
mbed_official 235:685d5f11838f 23 *
mbed_official 235:685d5f11838f 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 235:685d5f11838f 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 235:685d5f11838f 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 235:685d5f11838f 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 235:685d5f11838f 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 235:685d5f11838f 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 235:685d5f11838f 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 235:685d5f11838f 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 235:685d5f11838f 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 235:685d5f11838f 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 235:685d5f11838f 34 *
mbed_official 235:685d5f11838f 35 ******************************************************************************
mbed_official 235:685d5f11838f 36 */
mbed_official 235:685d5f11838f 37
mbed_official 235:685d5f11838f 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 235:685d5f11838f 39 #ifndef __STM32F4xx_HAL_ETH_H
mbed_official 235:685d5f11838f 40 #define __STM32F4xx_HAL_ETH_H
mbed_official 235:685d5f11838f 41
mbed_official 235:685d5f11838f 42 #ifdef __cplusplus
mbed_official 235:685d5f11838f 43 extern "C" {
mbed_official 235:685d5f11838f 44 #endif
mbed_official 235:685d5f11838f 45
mbed_official 235:685d5f11838f 46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 235:685d5f11838f 47 /* Includes ------------------------------------------------------------------*/
mbed_official 235:685d5f11838f 48 #include "stm32f4xx_hal_def.h"
mbed_official 235:685d5f11838f 49
mbed_official 235:685d5f11838f 50 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 235:685d5f11838f 51 * @{
mbed_official 235:685d5f11838f 52 */
mbed_official 235:685d5f11838f 53
mbed_official 235:685d5f11838f 54 /** @addtogroup ETH
mbed_official 235:685d5f11838f 55 * @{
mbed_official 235:685d5f11838f 56 */
mbed_official 235:685d5f11838f 57
mbed_official 235:685d5f11838f 58 /* Exported types ------------------------------------------------------------*/
mbed_official 235:685d5f11838f 59
mbed_official 235:685d5f11838f 60 /**
mbed_official 235:685d5f11838f 61 * @brief HAL State structures definition
mbed_official 235:685d5f11838f 62 */
mbed_official 235:685d5f11838f 63 typedef enum
mbed_official 235:685d5f11838f 64 {
mbed_official 235:685d5f11838f 65 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
mbed_official 235:685d5f11838f 66 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
mbed_official 235:685d5f11838f 67 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
mbed_official 235:685d5f11838f 68 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
mbed_official 235:685d5f11838f 69 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
mbed_official 235:685d5f11838f 70 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
mbed_official 235:685d5f11838f 71 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
mbed_official 235:685d5f11838f 72 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
mbed_official 235:685d5f11838f 73 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
mbed_official 235:685d5f11838f 74 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
mbed_official 235:685d5f11838f 75 }HAL_ETH_StateTypeDef;
mbed_official 235:685d5f11838f 76
mbed_official 235:685d5f11838f 77 /**
mbed_official 235:685d5f11838f 78 * @brief ETH Init Structure definition
mbed_official 235:685d5f11838f 79 */
mbed_official 235:685d5f11838f 80
mbed_official 235:685d5f11838f 81 typedef struct
mbed_official 235:685d5f11838f 82 {
mbed_official 235:685d5f11838f 83 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
mbed_official 235:685d5f11838f 84 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
mbed_official 235:685d5f11838f 85 and the mode (half/full-duplex).
mbed_official 235:685d5f11838f 86 This parameter can be a value of @ref ETH_AutoNegotiation */
mbed_official 235:685d5f11838f 87
mbed_official 235:685d5f11838f 88 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
mbed_official 235:685d5f11838f 89 This parameter can be a value of @ref ETH_Speed */
mbed_official 235:685d5f11838f 90
mbed_official 235:685d5f11838f 91 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
mbed_official 235:685d5f11838f 92 This parameter can be a value of @ref ETH_Duplex_Mode */
mbed_official 235:685d5f11838f 93
mbed_official 235:685d5f11838f 94 uint16_t PhyAddress; /*!< Ethernet PHY address.
mbed_official 235:685d5f11838f 95 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official 235:685d5f11838f 96
mbed_official 235:685d5f11838f 97 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
mbed_official 235:685d5f11838f 98
mbed_official 235:685d5f11838f 99 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
mbed_official 235:685d5f11838f 100 This parameter can be a value of @ref ETH_Rx_Mode */
mbed_official 235:685d5f11838f 101
mbed_official 235:685d5f11838f 102 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
mbed_official 235:685d5f11838f 103 This parameter can be a value of @ref ETH_Checksum_Mode */
mbed_official 235:685d5f11838f 104
mbed_official 235:685d5f11838f 105 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
mbed_official 235:685d5f11838f 106 This parameter can be a value of @ref ETH_Media_Interface */
mbed_official 235:685d5f11838f 107
mbed_official 235:685d5f11838f 108 } ETH_InitTypeDef;
mbed_official 235:685d5f11838f 109
mbed_official 235:685d5f11838f 110
mbed_official 235:685d5f11838f 111 /**
mbed_official 235:685d5f11838f 112 * @brief ETH MAC Configuration Structure definition
mbed_official 235:685d5f11838f 113 */
mbed_official 235:685d5f11838f 114
mbed_official 235:685d5f11838f 115 typedef struct
mbed_official 235:685d5f11838f 116 {
mbed_official 235:685d5f11838f 117 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
mbed_official 235:685d5f11838f 118 When enabled, the MAC allows no more then 2048 bytes to be received.
mbed_official 235:685d5f11838f 119 When disabled, the MAC can receive up to 16384 bytes.
mbed_official 235:685d5f11838f 120 This parameter can be a value of @ref ETH_watchdog */
mbed_official 235:685d5f11838f 121
mbed_official 235:685d5f11838f 122 uint32_t Jabber; /*!< Selects or not Jabber timer
mbed_official 235:685d5f11838f 123 When enabled, the MAC allows no more then 2048 bytes to be sent.
mbed_official 235:685d5f11838f 124 When disabled, the MAC can send up to 16384 bytes.
mbed_official 235:685d5f11838f 125 This parameter can be a value of @ref ETH_Jabber */
mbed_official 235:685d5f11838f 126
mbed_official 235:685d5f11838f 127 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
mbed_official 235:685d5f11838f 128 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
mbed_official 235:685d5f11838f 129
mbed_official 235:685d5f11838f 130 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
mbed_official 235:685d5f11838f 131 This parameter can be a value of @ref ETH_Carrier_Sense */
mbed_official 235:685d5f11838f 132
mbed_official 235:685d5f11838f 133 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
mbed_official 235:685d5f11838f 134 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
mbed_official 235:685d5f11838f 135 in Half-Duplex mode.
mbed_official 235:685d5f11838f 136 This parameter can be a value of @ref ETH_Receive_Own */
mbed_official 235:685d5f11838f 137
mbed_official 235:685d5f11838f 138 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
mbed_official 235:685d5f11838f 139 This parameter can be a value of @ref ETH_Loop_Back_Mode */
mbed_official 235:685d5f11838f 140
mbed_official 235:685d5f11838f 141 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
mbed_official 235:685d5f11838f 142 This parameter can be a value of @ref ETH_Checksum_Offload */
mbed_official 235:685d5f11838f 143
mbed_official 235:685d5f11838f 144 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
mbed_official 235:685d5f11838f 145 when a collision occurs (Half-Duplex mode).
mbed_official 235:685d5f11838f 146 This parameter can be a value of @ref ETH_Retry_Transmission */
mbed_official 235:685d5f11838f 147
mbed_official 235:685d5f11838f 148 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
mbed_official 235:685d5f11838f 149 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
mbed_official 235:685d5f11838f 150
mbed_official 235:685d5f11838f 151 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
mbed_official 235:685d5f11838f 152 This parameter can be a value of @ref ETH_Back_Off_Limit */
mbed_official 235:685d5f11838f 153
mbed_official 235:685d5f11838f 154 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
mbed_official 235:685d5f11838f 155 This parameter can be a value of @ref ETH_Deferral_Check */
mbed_official 235:685d5f11838f 156
mbed_official 235:685d5f11838f 157 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
mbed_official 235:685d5f11838f 158 This parameter can be a value of @ref ETH_Receive_All */
mbed_official 235:685d5f11838f 159
mbed_official 235:685d5f11838f 160 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
mbed_official 235:685d5f11838f 161 This parameter can be a value of @ref ETH_Source_Addr_Filter */
mbed_official 235:685d5f11838f 162
mbed_official 235:685d5f11838f 163 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
mbed_official 235:685d5f11838f 164 This parameter can be a value of @ref ETH_Pass_Control_Frames */
mbed_official 235:685d5f11838f 165
mbed_official 235:685d5f11838f 166 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
mbed_official 235:685d5f11838f 167 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
mbed_official 235:685d5f11838f 168
mbed_official 235:685d5f11838f 169 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
mbed_official 235:685d5f11838f 170 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
mbed_official 235:685d5f11838f 171
mbed_official 235:685d5f11838f 172 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
mbed_official 235:685d5f11838f 173 This parameter can be a value of @ref ETH_Promiscuous_Mode */
mbed_official 235:685d5f11838f 174
mbed_official 235:685d5f11838f 175 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official 235:685d5f11838f 176 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
mbed_official 235:685d5f11838f 177
mbed_official 235:685d5f11838f 178 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official 235:685d5f11838f 179 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
mbed_official 235:685d5f11838f 180
mbed_official 235:685d5f11838f 181 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
mbed_official 235:685d5f11838f 182 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official 235:685d5f11838f 183
mbed_official 235:685d5f11838f 184 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
mbed_official 235:685d5f11838f 185 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official 235:685d5f11838f 186
mbed_official 235:685d5f11838f 187 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
mbed_official 235:685d5f11838f 188 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
mbed_official 235:685d5f11838f 189
mbed_official 235:685d5f11838f 190 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
mbed_official 235:685d5f11838f 191 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
mbed_official 235:685d5f11838f 192
mbed_official 235:685d5f11838f 193 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
mbed_official 235:685d5f11838f 194 automatic retransmission of PAUSE Frame.
mbed_official 235:685d5f11838f 195 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
mbed_official 235:685d5f11838f 196
mbed_official 235:685d5f11838f 197 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
mbed_official 235:685d5f11838f 198 unicast address and unique multicast address).
mbed_official 235:685d5f11838f 199 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
mbed_official 235:685d5f11838f 200
mbed_official 235:685d5f11838f 201 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
mbed_official 235:685d5f11838f 202 disable its transmitter for a specified time (Pause Time)
mbed_official 235:685d5f11838f 203 This parameter can be a value of @ref ETH_Receive_Flow_Control */
mbed_official 235:685d5f11838f 204
mbed_official 235:685d5f11838f 205 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
mbed_official 235:685d5f11838f 206 or the MAC back-pressure operation (Half-Duplex mode)
mbed_official 235:685d5f11838f 207 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
mbed_official 235:685d5f11838f 208
mbed_official 235:685d5f11838f 209 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
mbed_official 235:685d5f11838f 210 comparison and filtering.
mbed_official 235:685d5f11838f 211 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
mbed_official 235:685d5f11838f 212
mbed_official 235:685d5f11838f 213 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
mbed_official 235:685d5f11838f 214
mbed_official 235:685d5f11838f 215 } ETH_MACInitTypeDef;
mbed_official 235:685d5f11838f 216
mbed_official 235:685d5f11838f 217
mbed_official 235:685d5f11838f 218 /**
mbed_official 235:685d5f11838f 219 * @brief ETH DMA Configuration Structure definition
mbed_official 235:685d5f11838f 220 */
mbed_official 235:685d5f11838f 221
mbed_official 235:685d5f11838f 222 typedef struct
mbed_official 235:685d5f11838f 223 {
mbed_official 235:685d5f11838f 224 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
mbed_official 235:685d5f11838f 225 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
mbed_official 235:685d5f11838f 226
mbed_official 235:685d5f11838f 227 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
mbed_official 235:685d5f11838f 228 This parameter can be a value of @ref ETH_Receive_Store_Forward */
mbed_official 235:685d5f11838f 229
mbed_official 235:685d5f11838f 230 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
mbed_official 235:685d5f11838f 231 This parameter can be a value of @ref ETH_Flush_Received_Frame */
mbed_official 235:685d5f11838f 232
mbed_official 235:685d5f11838f 233 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
mbed_official 235:685d5f11838f 234 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
mbed_official 235:685d5f11838f 235
mbed_official 235:685d5f11838f 236 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
mbed_official 235:685d5f11838f 237 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
mbed_official 235:685d5f11838f 238
mbed_official 235:685d5f11838f 239 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
mbed_official 235:685d5f11838f 240 This parameter can be a value of @ref ETH_Forward_Error_Frames */
mbed_official 235:685d5f11838f 241
mbed_official 235:685d5f11838f 242 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
mbed_official 235:685d5f11838f 243 and length less than 64 bytes) including pad-bytes and CRC)
mbed_official 235:685d5f11838f 244 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
mbed_official 235:685d5f11838f 245
mbed_official 235:685d5f11838f 246 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
mbed_official 235:685d5f11838f 247 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
mbed_official 235:685d5f11838f 248
mbed_official 235:685d5f11838f 249 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
mbed_official 235:685d5f11838f 250 frame of Transmit data even before obtaining the status for the first frame.
mbed_official 235:685d5f11838f 251 This parameter can be a value of @ref ETH_Second_Frame_Operate */
mbed_official 235:685d5f11838f 252
mbed_official 235:685d5f11838f 253 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
mbed_official 235:685d5f11838f 254 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
mbed_official 235:685d5f11838f 255
mbed_official 235:685d5f11838f 256 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
mbed_official 235:685d5f11838f 257 This parameter can be a value of @ref ETH_Fixed_Burst */
mbed_official 235:685d5f11838f 258
mbed_official 235:685d5f11838f 259 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
mbed_official 235:685d5f11838f 260 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
mbed_official 235:685d5f11838f 261
mbed_official 235:685d5f11838f 262 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
mbed_official 235:685d5f11838f 263 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
mbed_official 235:685d5f11838f 264
mbed_official 235:685d5f11838f 265 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
mbed_official 235:685d5f11838f 266 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
mbed_official 235:685d5f11838f 267
mbed_official 235:685d5f11838f 268 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
mbed_official 235:685d5f11838f 269 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official 235:685d5f11838f 270
mbed_official 235:685d5f11838f 271 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
mbed_official 235:685d5f11838f 272 This parameter can be a value of @ref ETH_DMA_Arbitration */
mbed_official 235:685d5f11838f 273 } ETH_DMAInitTypeDef;
mbed_official 235:685d5f11838f 274
mbed_official 235:685d5f11838f 275
mbed_official 235:685d5f11838f 276 /**
mbed_official 235:685d5f11838f 277 * @brief ETH DMA Descriptors data structure definition
mbed_official 235:685d5f11838f 278 */
mbed_official 235:685d5f11838f 279
mbed_official 235:685d5f11838f 280 typedef struct
mbed_official 235:685d5f11838f 281 {
mbed_official 235:685d5f11838f 282 __IO uint32_t Status; /*!< Status */
mbed_official 235:685d5f11838f 283
mbed_official 235:685d5f11838f 284 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
mbed_official 235:685d5f11838f 285
mbed_official 235:685d5f11838f 286 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
mbed_official 235:685d5f11838f 287
mbed_official 235:685d5f11838f 288 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
mbed_official 235:685d5f11838f 289
mbed_official 235:685d5f11838f 290 /*!< Enhanced ETHERNET DMA PTP Descriptors */
mbed_official 235:685d5f11838f 291 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
mbed_official 235:685d5f11838f 292
mbed_official 235:685d5f11838f 293 uint32_t Reserved1; /*!< Reserved */
mbed_official 235:685d5f11838f 294
mbed_official 235:685d5f11838f 295 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
mbed_official 235:685d5f11838f 296
mbed_official 235:685d5f11838f 297 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
mbed_official 235:685d5f11838f 298
mbed_official 235:685d5f11838f 299 } ETH_DMADescTypeDef;
mbed_official 235:685d5f11838f 300
mbed_official 235:685d5f11838f 301
mbed_official 235:685d5f11838f 302 /**
mbed_official 235:685d5f11838f 303 * @brief Received Frame Informations structure definition
mbed_official 235:685d5f11838f 304 */
mbed_official 235:685d5f11838f 305 typedef struct
mbed_official 235:685d5f11838f 306 {
mbed_official 235:685d5f11838f 307 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
mbed_official 235:685d5f11838f 308
mbed_official 235:685d5f11838f 309 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
mbed_official 235:685d5f11838f 310
mbed_official 235:685d5f11838f 311 uint32_t SegCount; /*!< Segment count */
mbed_official 235:685d5f11838f 312
mbed_official 235:685d5f11838f 313 uint32_t length; /*!< Frame length */
mbed_official 235:685d5f11838f 314
mbed_official 235:685d5f11838f 315 uint32_t buffer; /*!< Frame buffer */
mbed_official 235:685d5f11838f 316
mbed_official 235:685d5f11838f 317 } ETH_DMARxFrameInfos;
mbed_official 235:685d5f11838f 318
mbed_official 235:685d5f11838f 319
mbed_official 235:685d5f11838f 320 /**
mbed_official 235:685d5f11838f 321 * @brief ETH Handle Structure definition
mbed_official 235:685d5f11838f 322 */
mbed_official 235:685d5f11838f 323
mbed_official 235:685d5f11838f 324 typedef struct
mbed_official 235:685d5f11838f 325 {
mbed_official 235:685d5f11838f 326 ETH_TypeDef *Instance; /*!< Register base address */
mbed_official 235:685d5f11838f 327
mbed_official 235:685d5f11838f 328 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
mbed_official 235:685d5f11838f 329
mbed_official 235:685d5f11838f 330 uint32_t LinkStatus; /*!< Ethernet link status */
mbed_official 235:685d5f11838f 331
mbed_official 235:685d5f11838f 332 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
mbed_official 235:685d5f11838f 333
mbed_official 235:685d5f11838f 334 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
mbed_official 235:685d5f11838f 335
mbed_official 235:685d5f11838f 336 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
mbed_official 235:685d5f11838f 337
mbed_official 235:685d5f11838f 338 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
mbed_official 235:685d5f11838f 339
mbed_official 235:685d5f11838f 340 HAL_LockTypeDef Lock; /*!< ETH Lock */
mbed_official 235:685d5f11838f 341
mbed_official 235:685d5f11838f 342 } ETH_HandleTypeDef;
mbed_official 235:685d5f11838f 343
mbed_official 235:685d5f11838f 344 /* Exported constants --------------------------------------------------------*/
mbed_official 235:685d5f11838f 345
mbed_official 235:685d5f11838f 346 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
mbed_official 235:685d5f11838f 347
mbed_official 235:685d5f11838f 348 /* Delay to wait when writing to some Ethernet registers */
mbed_official 235:685d5f11838f 349 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
mbed_official 235:685d5f11838f 350
mbed_official 235:685d5f11838f 351
mbed_official 235:685d5f11838f 352 /* ETHERNET Errors */
mbed_official 235:685d5f11838f 353 #define ETH_SUCCESS ((uint32_t)0)
mbed_official 235:685d5f11838f 354 #define ETH_ERROR ((uint32_t)1)
mbed_official 235:685d5f11838f 355
mbed_official 235:685d5f11838f 356 /** @defgroup ETH_Buffers_setting
mbed_official 235:685d5f11838f 357 * @{
mbed_official 235:685d5f11838f 358 */
mbed_official 235:685d5f11838f 359 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
mbed_official 235:685d5f11838f 360 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
mbed_official 235:685d5f11838f 361 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
mbed_official 235:685d5f11838f 362 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
mbed_official 235:685d5f11838f 363 #define VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
mbed_official 235:685d5f11838f 364 #define MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
mbed_official 235:685d5f11838f 365 #define MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
mbed_official 235:685d5f11838f 366 #define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
mbed_official 235:685d5f11838f 367
mbed_official 235:685d5f11838f 368 /* Ethernet driver receive buffers are organized in a chained linked-list, when
mbed_official 235:685d5f11838f 369 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
mbed_official 235:685d5f11838f 370 to the driver receive buffers memory.
mbed_official 235:685d5f11838f 371
mbed_official 235:685d5f11838f 372 Depending on the size of the received ethernet packet and the size of
mbed_official 235:685d5f11838f 373 each ethernet driver receive buffer, the received packet can take one or more
mbed_official 235:685d5f11838f 374 ethernet driver receive buffer.
mbed_official 235:685d5f11838f 375
mbed_official 235:685d5f11838f 376 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
mbed_official 235:685d5f11838f 377 and the total count of the driver receive buffers ETH_RXBUFNB.
mbed_official 235:685d5f11838f 378
mbed_official 235:685d5f11838f 379 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
mbed_official 235:685d5f11838f 380 example, they can be reconfigured in the application layer to fit the application
mbed_official 235:685d5f11838f 381 needs */
mbed_official 235:685d5f11838f 382
mbed_official 235:685d5f11838f 383 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
mbed_official 235:685d5f11838f 384 packet */
mbed_official 235:685d5f11838f 385 #ifndef ETH_RX_BUF_SIZE
mbed_official 235:685d5f11838f 386 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official 235:685d5f11838f 387 #endif
mbed_official 235:685d5f11838f 388
mbed_official 235:685d5f11838f 389 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
mbed_official 235:685d5f11838f 390 #ifndef ETH_RXBUFNB
mbed_official 235:685d5f11838f 391 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
mbed_official 235:685d5f11838f 392 #endif
mbed_official 235:685d5f11838f 393
mbed_official 235:685d5f11838f 394
mbed_official 235:685d5f11838f 395 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
mbed_official 235:685d5f11838f 396 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
mbed_official 235:685d5f11838f 397 driver transmit buffers memory to the TxFIFO.
mbed_official 235:685d5f11838f 398
mbed_official 235:685d5f11838f 399 Depending on the size of the Ethernet packet to be transmitted and the size of
mbed_official 235:685d5f11838f 400 each ethernet driver transmit buffer, the packet to be transmitted can take
mbed_official 235:685d5f11838f 401 one or more ethernet driver transmit buffer.
mbed_official 235:685d5f11838f 402
mbed_official 235:685d5f11838f 403 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
mbed_official 235:685d5f11838f 404 and the total count of the driver transmit buffers ETH_TXBUFNB.
mbed_official 235:685d5f11838f 405
mbed_official 235:685d5f11838f 406 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
mbed_official 235:685d5f11838f 407 example, they can be reconfigured in the application layer to fit the application
mbed_official 235:685d5f11838f 408 needs */
mbed_official 235:685d5f11838f 409
mbed_official 235:685d5f11838f 410 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
mbed_official 235:685d5f11838f 411 packet */
mbed_official 235:685d5f11838f 412 #ifndef ETH_TX_BUF_SIZE
mbed_official 235:685d5f11838f 413 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official 235:685d5f11838f 414 #endif
mbed_official 235:685d5f11838f 415
mbed_official 235:685d5f11838f 416 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
mbed_official 235:685d5f11838f 417 #ifndef ETH_TXBUFNB
mbed_official 235:685d5f11838f 418 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
mbed_official 235:685d5f11838f 419 #endif
mbed_official 235:685d5f11838f 420
mbed_official 235:685d5f11838f 421
mbed_official 235:685d5f11838f 422 /*
mbed_official 235:685d5f11838f 423 DMA Tx Desciptor
mbed_official 235:685d5f11838f 424 -----------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 425 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
mbed_official 235:685d5f11838f 426 -----------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 427 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
mbed_official 235:685d5f11838f 428 -----------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 429 TDES2 | Buffer1 Address [31:0] |
mbed_official 235:685d5f11838f 430 -----------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 431 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
mbed_official 235:685d5f11838f 432 -----------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 433 */
mbed_official 235:685d5f11838f 434
mbed_official 235:685d5f11838f 435 /**
mbed_official 235:685d5f11838f 436 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
mbed_official 235:685d5f11838f 437 */
mbed_official 235:685d5f11838f 438 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
mbed_official 235:685d5f11838f 439 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
mbed_official 235:685d5f11838f 440 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
mbed_official 235:685d5f11838f 441 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
mbed_official 235:685d5f11838f 442 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
mbed_official 235:685d5f11838f 443 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
mbed_official 235:685d5f11838f 444 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
mbed_official 235:685d5f11838f 445 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
mbed_official 235:685d5f11838f 446 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
mbed_official 235:685d5f11838f 447 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
mbed_official 235:685d5f11838f 448 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
mbed_official 235:685d5f11838f 449 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
mbed_official 235:685d5f11838f 450 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
mbed_official 235:685d5f11838f 451 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
mbed_official 235:685d5f11838f 452 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
mbed_official 235:685d5f11838f 453 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
mbed_official 235:685d5f11838f 454 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
mbed_official 235:685d5f11838f 455 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
mbed_official 235:685d5f11838f 456 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
mbed_official 235:685d5f11838f 457 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
mbed_official 235:685d5f11838f 458 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
mbed_official 235:685d5f11838f 459 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
mbed_official 235:685d5f11838f 460 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
mbed_official 235:685d5f11838f 461 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
mbed_official 235:685d5f11838f 462 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
mbed_official 235:685d5f11838f 463 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
mbed_official 235:685d5f11838f 464 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
mbed_official 235:685d5f11838f 465 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
mbed_official 235:685d5f11838f 466 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
mbed_official 235:685d5f11838f 467
mbed_official 235:685d5f11838f 468 /**
mbed_official 235:685d5f11838f 469 * @brief Bit definition of TDES1 register
mbed_official 235:685d5f11838f 470 */
mbed_official 235:685d5f11838f 471 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
mbed_official 235:685d5f11838f 472 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
mbed_official 235:685d5f11838f 473
mbed_official 235:685d5f11838f 474 /**
mbed_official 235:685d5f11838f 475 * @brief Bit definition of TDES2 register
mbed_official 235:685d5f11838f 476 */
mbed_official 235:685d5f11838f 477 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
mbed_official 235:685d5f11838f 478
mbed_official 235:685d5f11838f 479 /**
mbed_official 235:685d5f11838f 480 * @brief Bit definition of TDES3 register
mbed_official 235:685d5f11838f 481 */
mbed_official 235:685d5f11838f 482 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
mbed_official 235:685d5f11838f 483
mbed_official 235:685d5f11838f 484 /*---------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 485 TDES6 | Transmit Time Stamp Low [31:0] |
mbed_official 235:685d5f11838f 486 -----------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 487 TDES7 | Transmit Time Stamp High [31:0] |
mbed_official 235:685d5f11838f 488 ----------------------------------------------------------------------------------------------*/
mbed_official 235:685d5f11838f 489
mbed_official 235:685d5f11838f 490 /* Bit definition of TDES6 register */
mbed_official 235:685d5f11838f 491 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
mbed_official 235:685d5f11838f 492
mbed_official 235:685d5f11838f 493 /* Bit definition of TDES7 register */
mbed_official 235:685d5f11838f 494 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
mbed_official 235:685d5f11838f 495
mbed_official 235:685d5f11838f 496 /**
mbed_official 235:685d5f11838f 497 * @}
mbed_official 235:685d5f11838f 498 */
mbed_official 235:685d5f11838f 499
mbed_official 235:685d5f11838f 500
mbed_official 235:685d5f11838f 501 /** @defgroup ETH_DMA_Rx_descriptor
mbed_official 235:685d5f11838f 502 * @{
mbed_official 235:685d5f11838f 503 */
mbed_official 235:685d5f11838f 504
mbed_official 235:685d5f11838f 505 /*
mbed_official 235:685d5f11838f 506 DMA Rx Descriptor
mbed_official 235:685d5f11838f 507 --------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 508 RDES0 | OWN(31) | Status [30:0] |
mbed_official 235:685d5f11838f 509 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 510 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
mbed_official 235:685d5f11838f 511 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 512 RDES2 | Buffer1 Address [31:0] |
mbed_official 235:685d5f11838f 513 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 514 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
mbed_official 235:685d5f11838f 515 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 516 */
mbed_official 235:685d5f11838f 517
mbed_official 235:685d5f11838f 518 /**
mbed_official 235:685d5f11838f 519 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
mbed_official 235:685d5f11838f 520 */
mbed_official 235:685d5f11838f 521 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
mbed_official 235:685d5f11838f 522 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
mbed_official 235:685d5f11838f 523 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
mbed_official 235:685d5f11838f 524 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
mbed_official 235:685d5f11838f 525 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
mbed_official 235:685d5f11838f 526 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
mbed_official 235:685d5f11838f 527 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
mbed_official 235:685d5f11838f 528 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
mbed_official 235:685d5f11838f 529 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
mbed_official 235:685d5f11838f 530 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
mbed_official 235:685d5f11838f 531 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
mbed_official 235:685d5f11838f 532 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
mbed_official 235:685d5f11838f 533 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
mbed_official 235:685d5f11838f 534 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
mbed_official 235:685d5f11838f 535 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
mbed_official 235:685d5f11838f 536 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
mbed_official 235:685d5f11838f 537 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
mbed_official 235:685d5f11838f 538 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
mbed_official 235:685d5f11838f 539 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
mbed_official 235:685d5f11838f 540
mbed_official 235:685d5f11838f 541 /**
mbed_official 235:685d5f11838f 542 * @brief Bit definition of RDES1 register
mbed_official 235:685d5f11838f 543 */
mbed_official 235:685d5f11838f 544 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
mbed_official 235:685d5f11838f 545 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
mbed_official 235:685d5f11838f 546 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
mbed_official 235:685d5f11838f 547 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
mbed_official 235:685d5f11838f 548 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
mbed_official 235:685d5f11838f 549
mbed_official 235:685d5f11838f 550 /**
mbed_official 235:685d5f11838f 551 * @brief Bit definition of RDES2 register
mbed_official 235:685d5f11838f 552 */
mbed_official 235:685d5f11838f 553 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
mbed_official 235:685d5f11838f 554
mbed_official 235:685d5f11838f 555 /**
mbed_official 235:685d5f11838f 556 * @brief Bit definition of RDES3 register
mbed_official 235:685d5f11838f 557 */
mbed_official 235:685d5f11838f 558 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
mbed_official 235:685d5f11838f 559
mbed_official 235:685d5f11838f 560 /*---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 561 RDES4 | Reserved[31:15] | Extended Status [14:0] |
mbed_official 235:685d5f11838f 562 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 563 RDES5 | Reserved[31:0] |
mbed_official 235:685d5f11838f 564 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 565 RDES6 | Receive Time Stamp Low [31:0] |
mbed_official 235:685d5f11838f 566 ---------------------------------------------------------------------------------------------------------------------
mbed_official 235:685d5f11838f 567 RDES7 | Receive Time Stamp High [31:0] |
mbed_official 235:685d5f11838f 568 --------------------------------------------------------------------------------------------------------------------*/
mbed_official 235:685d5f11838f 569
mbed_official 235:685d5f11838f 570 /* Bit definition of RDES4 register */
mbed_official 235:685d5f11838f 571 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
mbed_official 235:685d5f11838f 572 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
mbed_official 235:685d5f11838f 573 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
mbed_official 235:685d5f11838f 574 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
mbed_official 235:685d5f11838f 575 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
mbed_official 235:685d5f11838f 576 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
mbed_official 235:685d5f11838f 577 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
mbed_official 235:685d5f11838f 578 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
mbed_official 235:685d5f11838f 579 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
mbed_official 235:685d5f11838f 580 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
mbed_official 235:685d5f11838f 581 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
mbed_official 235:685d5f11838f 582 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
mbed_official 235:685d5f11838f 583 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
mbed_official 235:685d5f11838f 584 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
mbed_official 235:685d5f11838f 585 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
mbed_official 235:685d5f11838f 586 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
mbed_official 235:685d5f11838f 587 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
mbed_official 235:685d5f11838f 588 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
mbed_official 235:685d5f11838f 589 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
mbed_official 235:685d5f11838f 590
mbed_official 235:685d5f11838f 591 /* Bit definition of RDES6 register */
mbed_official 235:685d5f11838f 592 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
mbed_official 235:685d5f11838f 593
mbed_official 235:685d5f11838f 594 /* Bit definition of RDES7 register */
mbed_official 235:685d5f11838f 595 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
mbed_official 235:685d5f11838f 596
mbed_official 235:685d5f11838f 597
mbed_official 235:685d5f11838f 598 /** @defgroup ETH_AutoNegotiation
mbed_official 235:685d5f11838f 599 * @{
mbed_official 235:685d5f11838f 600 */
mbed_official 235:685d5f11838f 601 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
mbed_official 235:685d5f11838f 602 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 603 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
mbed_official 235:685d5f11838f 604 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
mbed_official 235:685d5f11838f 605 /**
mbed_official 235:685d5f11838f 606 * @}
mbed_official 235:685d5f11838f 607 */
mbed_official 235:685d5f11838f 608 /** @defgroup ETH_Speed
mbed_official 235:685d5f11838f 609 * @{
mbed_official 235:685d5f11838f 610 */
mbed_official 235:685d5f11838f 611 #define ETH_SPEED_10M ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 612 #define ETH_SPEED_100M ((uint32_t)0x00004000)
mbed_official 235:685d5f11838f 613 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
mbed_official 235:685d5f11838f 614 ((SPEED) == ETH_SPEED_100M))
mbed_official 235:685d5f11838f 615 /**
mbed_official 235:685d5f11838f 616 * @}
mbed_official 235:685d5f11838f 617 */
mbed_official 235:685d5f11838f 618 /** @defgroup ETH_Duplex_Mode
mbed_official 235:685d5f11838f 619 * @{
mbed_official 235:685d5f11838f 620 */
mbed_official 235:685d5f11838f 621 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
mbed_official 235:685d5f11838f 622 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 623 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
mbed_official 235:685d5f11838f 624 ((MODE) == ETH_MODE_HALFDUPLEX))
mbed_official 235:685d5f11838f 625 /**
mbed_official 235:685d5f11838f 626 * @}
mbed_official 235:685d5f11838f 627 */
mbed_official 235:685d5f11838f 628 /** @defgroup ETH_Rx_Mode
mbed_official 235:685d5f11838f 629 * @{
mbed_official 235:685d5f11838f 630 */
mbed_official 235:685d5f11838f 631 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 632 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
mbed_official 235:685d5f11838f 633 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 235:685d5f11838f 634 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 235:685d5f11838f 635 /**
mbed_official 235:685d5f11838f 636 * @}
mbed_official 235:685d5f11838f 637 */
mbed_official 235:685d5f11838f 638
mbed_official 235:685d5f11838f 639 /** @defgroup ETH_Checksum_Mode
mbed_official 235:685d5f11838f 640 * @{
mbed_official 235:685d5f11838f 641 */
mbed_official 235:685d5f11838f 642 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 643 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
mbed_official 235:685d5f11838f 644 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
mbed_official 235:685d5f11838f 645 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
mbed_official 235:685d5f11838f 646 /**
mbed_official 235:685d5f11838f 647 * @}
mbed_official 235:685d5f11838f 648 */
mbed_official 235:685d5f11838f 649
mbed_official 235:685d5f11838f 650 /** @defgroup ETH_Media_Interface
mbed_official 235:685d5f11838f 651 * @{
mbed_official 235:685d5f11838f 652 */
mbed_official 235:685d5f11838f 653 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 654 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
mbed_official 235:685d5f11838f 655 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
mbed_official 235:685d5f11838f 656 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
mbed_official 235:685d5f11838f 657
mbed_official 235:685d5f11838f 658 /**
mbed_official 235:685d5f11838f 659 * @}
mbed_official 235:685d5f11838f 660 */
mbed_official 235:685d5f11838f 661
mbed_official 235:685d5f11838f 662 /** @defgroup ETH_watchdog
mbed_official 235:685d5f11838f 663 * @{
mbed_official 235:685d5f11838f 664 */
mbed_official 235:685d5f11838f 665 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 666 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
mbed_official 235:685d5f11838f 667 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
mbed_official 235:685d5f11838f 668 ((CMD) == ETH_WATCHDOG_DISABLE))
mbed_official 235:685d5f11838f 669
mbed_official 235:685d5f11838f 670 /**
mbed_official 235:685d5f11838f 671 * @}
mbed_official 235:685d5f11838f 672 */
mbed_official 235:685d5f11838f 673
mbed_official 235:685d5f11838f 674 /** @defgroup ETH_Jabber
mbed_official 235:685d5f11838f 675 * @{
mbed_official 235:685d5f11838f 676 */
mbed_official 235:685d5f11838f 677 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 678 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
mbed_official 235:685d5f11838f 679 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
mbed_official 235:685d5f11838f 680 ((CMD) == ETH_JABBER_DISABLE))
mbed_official 235:685d5f11838f 681
mbed_official 235:685d5f11838f 682 /**
mbed_official 235:685d5f11838f 683 * @}
mbed_official 235:685d5f11838f 684 */
mbed_official 235:685d5f11838f 685
mbed_official 235:685d5f11838f 686 /** @defgroup ETH_Inter_Frame_Gap
mbed_official 235:685d5f11838f 687 * @{
mbed_official 235:685d5f11838f 688 */
mbed_official 235:685d5f11838f 689 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
mbed_official 235:685d5f11838f 690 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
mbed_official 235:685d5f11838f 691 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
mbed_official 235:685d5f11838f 692 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
mbed_official 235:685d5f11838f 693 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
mbed_official 235:685d5f11838f 694 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
mbed_official 235:685d5f11838f 695 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
mbed_official 235:685d5f11838f 696 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
mbed_official 235:685d5f11838f 697 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
mbed_official 235:685d5f11838f 698 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
mbed_official 235:685d5f11838f 699 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
mbed_official 235:685d5f11838f 700 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
mbed_official 235:685d5f11838f 701 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
mbed_official 235:685d5f11838f 702 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
mbed_official 235:685d5f11838f 703 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
mbed_official 235:685d5f11838f 704 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
mbed_official 235:685d5f11838f 705
mbed_official 235:685d5f11838f 706 /**
mbed_official 235:685d5f11838f 707 * @}
mbed_official 235:685d5f11838f 708 */
mbed_official 235:685d5f11838f 709
mbed_official 235:685d5f11838f 710 /** @defgroup ETH_Carrier_Sense
mbed_official 235:685d5f11838f 711 * @{
mbed_official 235:685d5f11838f 712 */
mbed_official 235:685d5f11838f 713 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 714 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
mbed_official 235:685d5f11838f 715 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
mbed_official 235:685d5f11838f 716 ((CMD) == ETH_CARRIERSENCE_DISABLE))
mbed_official 235:685d5f11838f 717
mbed_official 235:685d5f11838f 718 /**
mbed_official 235:685d5f11838f 719 * @}
mbed_official 235:685d5f11838f 720 */
mbed_official 235:685d5f11838f 721
mbed_official 235:685d5f11838f 722 /** @defgroup ETH_Receive_Own
mbed_official 235:685d5f11838f 723 * @{
mbed_official 235:685d5f11838f 724 */
mbed_official 235:685d5f11838f 725 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 726 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
mbed_official 235:685d5f11838f 727 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
mbed_official 235:685d5f11838f 728 ((CMD) == ETH_RECEIVEOWN_DISABLE))
mbed_official 235:685d5f11838f 729
mbed_official 235:685d5f11838f 730 /**
mbed_official 235:685d5f11838f 731 * @}
mbed_official 235:685d5f11838f 732 */
mbed_official 235:685d5f11838f 733
mbed_official 235:685d5f11838f 734 /** @defgroup ETH_Loop_Back_Mode
mbed_official 235:685d5f11838f 735 * @{
mbed_official 235:685d5f11838f 736 */
mbed_official 235:685d5f11838f 737 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
mbed_official 235:685d5f11838f 738 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 739 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
mbed_official 235:685d5f11838f 740 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
mbed_official 235:685d5f11838f 741
mbed_official 235:685d5f11838f 742 /**
mbed_official 235:685d5f11838f 743 * @}
mbed_official 235:685d5f11838f 744 */
mbed_official 235:685d5f11838f 745
mbed_official 235:685d5f11838f 746 /** @defgroup ETH_Checksum_Offload
mbed_official 235:685d5f11838f 747 * @{
mbed_official 235:685d5f11838f 748 */
mbed_official 235:685d5f11838f 749 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
mbed_official 235:685d5f11838f 750 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 751 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
mbed_official 235:685d5f11838f 752 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
mbed_official 235:685d5f11838f 753
mbed_official 235:685d5f11838f 754 /**
mbed_official 235:685d5f11838f 755 * @}
mbed_official 235:685d5f11838f 756 */
mbed_official 235:685d5f11838f 757
mbed_official 235:685d5f11838f 758 /** @defgroup ETH_Retry_Transmission
mbed_official 235:685d5f11838f 759 * @{
mbed_official 235:685d5f11838f 760 */
mbed_official 235:685d5f11838f 761 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 762 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
mbed_official 235:685d5f11838f 763 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
mbed_official 235:685d5f11838f 764 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
mbed_official 235:685d5f11838f 765
mbed_official 235:685d5f11838f 766 /**
mbed_official 235:685d5f11838f 767 * @}
mbed_official 235:685d5f11838f 768 */
mbed_official 235:685d5f11838f 769
mbed_official 235:685d5f11838f 770 /** @defgroup ETH_Automatic_Pad_CRC_Strip
mbed_official 235:685d5f11838f 771 * @{
mbed_official 235:685d5f11838f 772 */
mbed_official 235:685d5f11838f 773 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
mbed_official 235:685d5f11838f 774 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 775 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
mbed_official 235:685d5f11838f 776 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
mbed_official 235:685d5f11838f 777
mbed_official 235:685d5f11838f 778 /**
mbed_official 235:685d5f11838f 779 * @}
mbed_official 235:685d5f11838f 780 */
mbed_official 235:685d5f11838f 781
mbed_official 235:685d5f11838f 782 /** @defgroup ETH_Back_Off_Limit
mbed_official 235:685d5f11838f 783 * @{
mbed_official 235:685d5f11838f 784 */
mbed_official 235:685d5f11838f 785 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 786 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
mbed_official 235:685d5f11838f 787 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
mbed_official 235:685d5f11838f 788 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
mbed_official 235:685d5f11838f 789 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
mbed_official 235:685d5f11838f 790 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
mbed_official 235:685d5f11838f 791 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
mbed_official 235:685d5f11838f 792 ((LIMIT) == ETH_BACKOFFLIMIT_1))
mbed_official 235:685d5f11838f 793
mbed_official 235:685d5f11838f 794 /**
mbed_official 235:685d5f11838f 795 * @}
mbed_official 235:685d5f11838f 796 */
mbed_official 235:685d5f11838f 797
mbed_official 235:685d5f11838f 798 /** @defgroup ETH_Deferral_Check
mbed_official 235:685d5f11838f 799 * @{
mbed_official 235:685d5f11838f 800 */
mbed_official 235:685d5f11838f 801 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
mbed_official 235:685d5f11838f 802 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 803 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
mbed_official 235:685d5f11838f 804 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
mbed_official 235:685d5f11838f 805
mbed_official 235:685d5f11838f 806 /**
mbed_official 235:685d5f11838f 807 * @}
mbed_official 235:685d5f11838f 808 */
mbed_official 235:685d5f11838f 809
mbed_official 235:685d5f11838f 810 /** @defgroup ETH_Receive_All
mbed_official 235:685d5f11838f 811 * @{
mbed_official 235:685d5f11838f 812 */
mbed_official 235:685d5f11838f 813 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
mbed_official 235:685d5f11838f 814 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 815 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
mbed_official 235:685d5f11838f 816 ((CMD) == ETH_RECEIVEAll_DISABLE))
mbed_official 235:685d5f11838f 817
mbed_official 235:685d5f11838f 818 /**
mbed_official 235:685d5f11838f 819 * @}
mbed_official 235:685d5f11838f 820 */
mbed_official 235:685d5f11838f 821
mbed_official 235:685d5f11838f 822 /** @defgroup ETH_Source_Addr_Filter
mbed_official 235:685d5f11838f 823 * @{
mbed_official 235:685d5f11838f 824 */
mbed_official 235:685d5f11838f 825 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
mbed_official 235:685d5f11838f 826 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
mbed_official 235:685d5f11838f 827 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 828 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
mbed_official 235:685d5f11838f 829 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
mbed_official 235:685d5f11838f 830 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
mbed_official 235:685d5f11838f 831
mbed_official 235:685d5f11838f 832 /**
mbed_official 235:685d5f11838f 833 * @}
mbed_official 235:685d5f11838f 834 */
mbed_official 235:685d5f11838f 835
mbed_official 235:685d5f11838f 836 /** @defgroup ETH_Pass_Control_Frames
mbed_official 235:685d5f11838f 837 * @{
mbed_official 235:685d5f11838f 838 */
mbed_official 235:685d5f11838f 839 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
mbed_official 235:685d5f11838f 840 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
mbed_official 235:685d5f11838f 841 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
mbed_official 235:685d5f11838f 842 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
mbed_official 235:685d5f11838f 843 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
mbed_official 235:685d5f11838f 844 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
mbed_official 235:685d5f11838f 845
mbed_official 235:685d5f11838f 846 /**
mbed_official 235:685d5f11838f 847 * @}
mbed_official 235:685d5f11838f 848 */
mbed_official 235:685d5f11838f 849
mbed_official 235:685d5f11838f 850 /** @defgroup ETH_Broadcast_Frames_Reception
mbed_official 235:685d5f11838f 851 * @{
mbed_official 235:685d5f11838f 852 */
mbed_official 235:685d5f11838f 853 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 854 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
mbed_official 235:685d5f11838f 855 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
mbed_official 235:685d5f11838f 856 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
mbed_official 235:685d5f11838f 857
mbed_official 235:685d5f11838f 858 /**
mbed_official 235:685d5f11838f 859 * @}
mbed_official 235:685d5f11838f 860 */
mbed_official 235:685d5f11838f 861
mbed_official 235:685d5f11838f 862 /** @defgroup ETH_Destination_Addr_Filter
mbed_official 235:685d5f11838f 863 * @{
mbed_official 235:685d5f11838f 864 */
mbed_official 235:685d5f11838f 865 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 866 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
mbed_official 235:685d5f11838f 867 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
mbed_official 235:685d5f11838f 868 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
mbed_official 235:685d5f11838f 869
mbed_official 235:685d5f11838f 870 /**
mbed_official 235:685d5f11838f 871 * @}
mbed_official 235:685d5f11838f 872 */
mbed_official 235:685d5f11838f 873
mbed_official 235:685d5f11838f 874 /** @defgroup ETH_Promiscuous_Mode
mbed_official 235:685d5f11838f 875 * @{
mbed_official 235:685d5f11838f 876 */
mbed_official 235:685d5f11838f 877 #define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
mbed_official 235:685d5f11838f 878 #define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 879 #define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
mbed_official 235:685d5f11838f 880 ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
mbed_official 235:685d5f11838f 881
mbed_official 235:685d5f11838f 882 /**
mbed_official 235:685d5f11838f 883 * @}
mbed_official 235:685d5f11838f 884 */
mbed_official 235:685d5f11838f 885
mbed_official 235:685d5f11838f 886 /** @defgroup ETH_Multicast_Frames_Filter
mbed_official 235:685d5f11838f 887 * @{
mbed_official 235:685d5f11838f 888 */
mbed_official 235:685d5f11838f 889 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
mbed_official 235:685d5f11838f 890 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
mbed_official 235:685d5f11838f 891 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 892 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
mbed_official 235:685d5f11838f 893 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
mbed_official 235:685d5f11838f 894 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
mbed_official 235:685d5f11838f 895 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
mbed_official 235:685d5f11838f 896 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
mbed_official 235:685d5f11838f 897 /**
mbed_official 235:685d5f11838f 898 * @}
mbed_official 235:685d5f11838f 899 */
mbed_official 235:685d5f11838f 900
mbed_official 235:685d5f11838f 901 /** @defgroup ETH_Unicast_Frames_Filter
mbed_official 235:685d5f11838f 902 * @{
mbed_official 235:685d5f11838f 903 */
mbed_official 235:685d5f11838f 904 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
mbed_official 235:685d5f11838f 905 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
mbed_official 235:685d5f11838f 906 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 907 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
mbed_official 235:685d5f11838f 908 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
mbed_official 235:685d5f11838f 909 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
mbed_official 235:685d5f11838f 910 /**
mbed_official 235:685d5f11838f 911 * @}
mbed_official 235:685d5f11838f 912 */
mbed_official 235:685d5f11838f 913
mbed_official 235:685d5f11838f 914 /** @defgroup ETH_Pause_Time
mbed_official 235:685d5f11838f 915 * @{
mbed_official 235:685d5f11838f 916 */
mbed_official 235:685d5f11838f 917 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
mbed_official 235:685d5f11838f 918
mbed_official 235:685d5f11838f 919 /**
mbed_official 235:685d5f11838f 920 * @}
mbed_official 235:685d5f11838f 921 */
mbed_official 235:685d5f11838f 922
mbed_official 235:685d5f11838f 923 /** @defgroup ETH_Zero_Quanta_Pause
mbed_official 235:685d5f11838f 924 * @{
mbed_official 235:685d5f11838f 925 */
mbed_official 235:685d5f11838f 926 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 927 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
mbed_official 235:685d5f11838f 928 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
mbed_official 235:685d5f11838f 929 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
mbed_official 235:685d5f11838f 930 /**
mbed_official 235:685d5f11838f 931 * @}
mbed_official 235:685d5f11838f 932 */
mbed_official 235:685d5f11838f 933
mbed_official 235:685d5f11838f 934 /** @defgroup ETH_Pause_Low_Threshold
mbed_official 235:685d5f11838f 935 * @{
mbed_official 235:685d5f11838f 936 */
mbed_official 235:685d5f11838f 937 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
mbed_official 235:685d5f11838f 938 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
mbed_official 235:685d5f11838f 939 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
mbed_official 235:685d5f11838f 940 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
mbed_official 235:685d5f11838f 941 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
mbed_official 235:685d5f11838f 942 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
mbed_official 235:685d5f11838f 943 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
mbed_official 235:685d5f11838f 944 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
mbed_official 235:685d5f11838f 945 /**
mbed_official 235:685d5f11838f 946 * @}
mbed_official 235:685d5f11838f 947 */
mbed_official 235:685d5f11838f 948
mbed_official 235:685d5f11838f 949 /** @defgroup ETH_Unicast_Pause_Frame_Detect
mbed_official 235:685d5f11838f 950 * @{
mbed_official 235:685d5f11838f 951 */
mbed_official 235:685d5f11838f 952 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
mbed_official 235:685d5f11838f 953 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 954 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
mbed_official 235:685d5f11838f 955 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
mbed_official 235:685d5f11838f 956 /**
mbed_official 235:685d5f11838f 957 * @}
mbed_official 235:685d5f11838f 958 */
mbed_official 235:685d5f11838f 959
mbed_official 235:685d5f11838f 960 /** @defgroup ETH_Receive_Flow_Control
mbed_official 235:685d5f11838f 961 * @{
mbed_official 235:685d5f11838f 962 */
mbed_official 235:685d5f11838f 963 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
mbed_official 235:685d5f11838f 964 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 965 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
mbed_official 235:685d5f11838f 966 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
mbed_official 235:685d5f11838f 967 /**
mbed_official 235:685d5f11838f 968 * @}
mbed_official 235:685d5f11838f 969 */
mbed_official 235:685d5f11838f 970
mbed_official 235:685d5f11838f 971 /** @defgroup ETH_Transmit_Flow_Control
mbed_official 235:685d5f11838f 972 * @{
mbed_official 235:685d5f11838f 973 */
mbed_official 235:685d5f11838f 974 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
mbed_official 235:685d5f11838f 975 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 976 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
mbed_official 235:685d5f11838f 977 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
mbed_official 235:685d5f11838f 978 /**
mbed_official 235:685d5f11838f 979 * @}
mbed_official 235:685d5f11838f 980 */
mbed_official 235:685d5f11838f 981
mbed_official 235:685d5f11838f 982 /** @defgroup ETH_VLAN_Tag_Comparison
mbed_official 235:685d5f11838f 983 * @{
mbed_official 235:685d5f11838f 984 */
mbed_official 235:685d5f11838f 985 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
mbed_official 235:685d5f11838f 986 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 987 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
mbed_official 235:685d5f11838f 988 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
mbed_official 235:685d5f11838f 989 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
mbed_official 235:685d5f11838f 990
mbed_official 235:685d5f11838f 991 /**
mbed_official 235:685d5f11838f 992 * @}
mbed_official 235:685d5f11838f 993 */
mbed_official 235:685d5f11838f 994
mbed_official 235:685d5f11838f 995 /** @defgroup ETH_MAC_addresses
mbed_official 235:685d5f11838f 996 * @{
mbed_official 235:685d5f11838f 997 */
mbed_official 235:685d5f11838f 998 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 999 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
mbed_official 235:685d5f11838f 1000 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
mbed_official 235:685d5f11838f 1001 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
mbed_official 235:685d5f11838f 1002 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
mbed_official 235:685d5f11838f 1003 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
mbed_official 235:685d5f11838f 1004 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
mbed_official 235:685d5f11838f 1005 ((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official 235:685d5f11838f 1006 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
mbed_official 235:685d5f11838f 1007 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
mbed_official 235:685d5f11838f 1008 ((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official 235:685d5f11838f 1009 /**
mbed_official 235:685d5f11838f 1010 * @}
mbed_official 235:685d5f11838f 1011 */
mbed_official 235:685d5f11838f 1012
mbed_official 235:685d5f11838f 1013 /** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
mbed_official 235:685d5f11838f 1014 * @{
mbed_official 235:685d5f11838f 1015 */
mbed_official 235:685d5f11838f 1016 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1017 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
mbed_official 235:685d5f11838f 1018 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
mbed_official 235:685d5f11838f 1019 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
mbed_official 235:685d5f11838f 1020 /**
mbed_official 235:685d5f11838f 1021 * @}
mbed_official 235:685d5f11838f 1022 */
mbed_official 235:685d5f11838f 1023
mbed_official 235:685d5f11838f 1024 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes
mbed_official 235:685d5f11838f 1025 * @{
mbed_official 235:685d5f11838f 1026 */
mbed_official 235:685d5f11838f 1027 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
mbed_official 235:685d5f11838f 1028 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
mbed_official 235:685d5f11838f 1029 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
mbed_official 235:685d5f11838f 1030 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
mbed_official 235:685d5f11838f 1031 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
mbed_official 235:685d5f11838f 1032 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
mbed_official 235:685d5f11838f 1033 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
mbed_official 235:685d5f11838f 1034 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
mbed_official 235:685d5f11838f 1035 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
mbed_official 235:685d5f11838f 1036 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
mbed_official 235:685d5f11838f 1037 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
mbed_official 235:685d5f11838f 1038 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
mbed_official 235:685d5f11838f 1039
mbed_official 235:685d5f11838f 1040 /**
mbed_official 235:685d5f11838f 1041 * @}
mbed_official 235:685d5f11838f 1042 */
mbed_official 235:685d5f11838f 1043
mbed_official 235:685d5f11838f 1044 /** @defgroup ETH_MAC_Debug_flags
mbed_official 235:685d5f11838f 1045 * @{
mbed_official 235:685d5f11838f 1046 */
mbed_official 235:685d5f11838f 1047 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
mbed_official 235:685d5f11838f 1048
mbed_official 235:685d5f11838f 1049 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
mbed_official 235:685d5f11838f 1050
mbed_official 235:685d5f11838f 1051 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
mbed_official 235:685d5f11838f 1052
mbed_official 235:685d5f11838f 1053 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
mbed_official 235:685d5f11838f 1054 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
mbed_official 235:685d5f11838f 1055 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
mbed_official 235:685d5f11838f 1056 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
mbed_official 235:685d5f11838f 1057
mbed_official 235:685d5f11838f 1058 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
mbed_official 235:685d5f11838f 1059
mbed_official 235:685d5f11838f 1060 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
mbed_official 235:685d5f11838f 1061 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
mbed_official 235:685d5f11838f 1062 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
mbed_official 235:685d5f11838f 1063 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
mbed_official 235:685d5f11838f 1064
mbed_official 235:685d5f11838f 1065 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
mbed_official 235:685d5f11838f 1066
mbed_official 235:685d5f11838f 1067 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
mbed_official 235:685d5f11838f 1068 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
mbed_official 235:685d5f11838f 1069 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
mbed_official 235:685d5f11838f 1070 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
mbed_official 235:685d5f11838f 1071
mbed_official 235:685d5f11838f 1072 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
mbed_official 235:685d5f11838f 1073 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
mbed_official 235:685d5f11838f 1074 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
mbed_official 235:685d5f11838f 1075 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
mbed_official 235:685d5f11838f 1076
mbed_official 235:685d5f11838f 1077 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
mbed_official 235:685d5f11838f 1078
mbed_official 235:685d5f11838f 1079 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
mbed_official 235:685d5f11838f 1080 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
mbed_official 235:685d5f11838f 1081 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
mbed_official 235:685d5f11838f 1082 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
mbed_official 235:685d5f11838f 1083
mbed_official 235:685d5f11838f 1084 #define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
mbed_official 235:685d5f11838f 1085
mbed_official 235:685d5f11838f 1086 /**
mbed_official 235:685d5f11838f 1087 * @}
mbed_official 235:685d5f11838f 1088 */
mbed_official 235:685d5f11838f 1089
mbed_official 235:685d5f11838f 1090 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
mbed_official 235:685d5f11838f 1091 * @{
mbed_official 235:685d5f11838f 1092 */
mbed_official 235:685d5f11838f 1093 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1094 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
mbed_official 235:685d5f11838f 1095 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
mbed_official 235:685d5f11838f 1096 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
mbed_official 235:685d5f11838f 1097 /**
mbed_official 235:685d5f11838f 1098 * @}
mbed_official 235:685d5f11838f 1099 */
mbed_official 235:685d5f11838f 1100
mbed_official 235:685d5f11838f 1101 /** @defgroup ETH_Receive_Store_Forward
mbed_official 235:685d5f11838f 1102 * @{
mbed_official 235:685d5f11838f 1103 */
mbed_official 235:685d5f11838f 1104 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
mbed_official 235:685d5f11838f 1105 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1106 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
mbed_official 235:685d5f11838f 1107 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
mbed_official 235:685d5f11838f 1108 /**
mbed_official 235:685d5f11838f 1109 * @}
mbed_official 235:685d5f11838f 1110 */
mbed_official 235:685d5f11838f 1111
mbed_official 235:685d5f11838f 1112 /** @defgroup ETH_Flush_Received_Frame
mbed_official 235:685d5f11838f 1113 * @{
mbed_official 235:685d5f11838f 1114 */
mbed_official 235:685d5f11838f 1115 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1116 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
mbed_official 235:685d5f11838f 1117 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
mbed_official 235:685d5f11838f 1118 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
mbed_official 235:685d5f11838f 1119 /**
mbed_official 235:685d5f11838f 1120 * @}
mbed_official 235:685d5f11838f 1121 */
mbed_official 235:685d5f11838f 1122
mbed_official 235:685d5f11838f 1123 /** @defgroup ETH_Transmit_Store_Forward
mbed_official 235:685d5f11838f 1124 * @{
mbed_official 235:685d5f11838f 1125 */
mbed_official 235:685d5f11838f 1126 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
mbed_official 235:685d5f11838f 1127 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1128 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
mbed_official 235:685d5f11838f 1129 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
mbed_official 235:685d5f11838f 1130 /**
mbed_official 235:685d5f11838f 1131 * @}
mbed_official 235:685d5f11838f 1132 */
mbed_official 235:685d5f11838f 1133
mbed_official 235:685d5f11838f 1134 /** @defgroup ETH_Transmit_Threshold_Control
mbed_official 235:685d5f11838f 1135 * @{
mbed_official 235:685d5f11838f 1136 */
mbed_official 235:685d5f11838f 1137 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
mbed_official 235:685d5f11838f 1138 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
mbed_official 235:685d5f11838f 1139 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
mbed_official 235:685d5f11838f 1140 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
mbed_official 235:685d5f11838f 1141 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
mbed_official 235:685d5f11838f 1142 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
mbed_official 235:685d5f11838f 1143 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
mbed_official 235:685d5f11838f 1144 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
mbed_official 235:685d5f11838f 1145 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
mbed_official 235:685d5f11838f 1146 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
mbed_official 235:685d5f11838f 1147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
mbed_official 235:685d5f11838f 1148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
mbed_official 235:685d5f11838f 1149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
mbed_official 235:685d5f11838f 1150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
mbed_official 235:685d5f11838f 1151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
mbed_official 235:685d5f11838f 1152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
mbed_official 235:685d5f11838f 1153 /**
mbed_official 235:685d5f11838f 1154 * @}
mbed_official 235:685d5f11838f 1155 */
mbed_official 235:685d5f11838f 1156
mbed_official 235:685d5f11838f 1157 /** @defgroup ETH_Forward_Error_Frames
mbed_official 235:685d5f11838f 1158 * @{
mbed_official 235:685d5f11838f 1159 */
mbed_official 235:685d5f11838f 1160 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
mbed_official 235:685d5f11838f 1161 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1162 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
mbed_official 235:685d5f11838f 1163 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
mbed_official 235:685d5f11838f 1164 /**
mbed_official 235:685d5f11838f 1165 * @}
mbed_official 235:685d5f11838f 1166 */
mbed_official 235:685d5f11838f 1167
mbed_official 235:685d5f11838f 1168 /** @defgroup ETH_Forward_Undersized_Good_Frames
mbed_official 235:685d5f11838f 1169 * @{
mbed_official 235:685d5f11838f 1170 */
mbed_official 235:685d5f11838f 1171 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
mbed_official 235:685d5f11838f 1172 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
mbed_official 235:685d5f11838f 1174 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
mbed_official 235:685d5f11838f 1175
mbed_official 235:685d5f11838f 1176 /**
mbed_official 235:685d5f11838f 1177 * @}
mbed_official 235:685d5f11838f 1178 */
mbed_official 235:685d5f11838f 1179
mbed_official 235:685d5f11838f 1180 /** @defgroup ETH_Receive_Threshold_Control
mbed_official 235:685d5f11838f 1181 * @{
mbed_official 235:685d5f11838f 1182 */
mbed_official 235:685d5f11838f 1183 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
mbed_official 235:685d5f11838f 1184 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
mbed_official 235:685d5f11838f 1185 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
mbed_official 235:685d5f11838f 1186 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
mbed_official 235:685d5f11838f 1187 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
mbed_official 235:685d5f11838f 1188 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
mbed_official 235:685d5f11838f 1189 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
mbed_official 235:685d5f11838f 1190 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
mbed_official 235:685d5f11838f 1191 /**
mbed_official 235:685d5f11838f 1192 * @}
mbed_official 235:685d5f11838f 1193 */
mbed_official 235:685d5f11838f 1194
mbed_official 235:685d5f11838f 1195 /** @defgroup ETH_Second_Frame_Operate
mbed_official 235:685d5f11838f 1196 * @{
mbed_official 235:685d5f11838f 1197 */
mbed_official 235:685d5f11838f 1198 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
mbed_official 235:685d5f11838f 1199 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1200 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
mbed_official 235:685d5f11838f 1201 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
mbed_official 235:685d5f11838f 1202
mbed_official 235:685d5f11838f 1203 /**
mbed_official 235:685d5f11838f 1204 * @}
mbed_official 235:685d5f11838f 1205 */
mbed_official 235:685d5f11838f 1206
mbed_official 235:685d5f11838f 1207 /** @defgroup ETH_Address_Aligned_Beats
mbed_official 235:685d5f11838f 1208 * @{
mbed_official 235:685d5f11838f 1209 */
mbed_official 235:685d5f11838f 1210 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
mbed_official 235:685d5f11838f 1211 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1212 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
mbed_official 235:685d5f11838f 1213 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
mbed_official 235:685d5f11838f 1214
mbed_official 235:685d5f11838f 1215 /**
mbed_official 235:685d5f11838f 1216 * @}
mbed_official 235:685d5f11838f 1217 */
mbed_official 235:685d5f11838f 1218
mbed_official 235:685d5f11838f 1219 /** @defgroup ETH_Fixed_Burst
mbed_official 235:685d5f11838f 1220 * @{
mbed_official 235:685d5f11838f 1221 */
mbed_official 235:685d5f11838f 1222 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
mbed_official 235:685d5f11838f 1223 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1224 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
mbed_official 235:685d5f11838f 1225 ((CMD) == ETH_FIXEDBURST_DISABLE))
mbed_official 235:685d5f11838f 1226
mbed_official 235:685d5f11838f 1227 /**
mbed_official 235:685d5f11838f 1228 * @}
mbed_official 235:685d5f11838f 1229 */
mbed_official 235:685d5f11838f 1230
mbed_official 235:685d5f11838f 1231 /** @defgroup ETH_Rx_DMA_Burst_Length
mbed_official 235:685d5f11838f 1232 * @{
mbed_official 235:685d5f11838f 1233 */
mbed_official 235:685d5f11838f 1234 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
mbed_official 235:685d5f11838f 1235 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
mbed_official 235:685d5f11838f 1236 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 235:685d5f11838f 1237 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 235:685d5f11838f 1238 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 235:685d5f11838f 1239 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 235:685d5f11838f 1240 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 235:685d5f11838f 1241 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 235:685d5f11838f 1242 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 235:685d5f11838f 1243 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 235:685d5f11838f 1244 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
mbed_official 235:685d5f11838f 1245 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
mbed_official 235:685d5f11838f 1246
mbed_official 235:685d5f11838f 1247 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
mbed_official 235:685d5f11838f 1248 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
mbed_official 235:685d5f11838f 1249 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
mbed_official 235:685d5f11838f 1250 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
mbed_official 235:685d5f11838f 1251 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
mbed_official 235:685d5f11838f 1252 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
mbed_official 235:685d5f11838f 1253 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
mbed_official 235:685d5f11838f 1254 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
mbed_official 235:685d5f11838f 1255 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
mbed_official 235:685d5f11838f 1256 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
mbed_official 235:685d5f11838f 1257 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
mbed_official 235:685d5f11838f 1258 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official 235:685d5f11838f 1259
mbed_official 235:685d5f11838f 1260 /**
mbed_official 235:685d5f11838f 1261 * @}
mbed_official 235:685d5f11838f 1262 */
mbed_official 235:685d5f11838f 1263
mbed_official 235:685d5f11838f 1264 /** @defgroup ETH_Tx_DMA_Burst_Length
mbed_official 235:685d5f11838f 1265 * @{
mbed_official 235:685d5f11838f 1266 */
mbed_official 235:685d5f11838f 1267 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
mbed_official 235:685d5f11838f 1268 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
mbed_official 235:685d5f11838f 1269 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 235:685d5f11838f 1270 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 235:685d5f11838f 1271 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 235:685d5f11838f 1272 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 235:685d5f11838f 1273 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 235:685d5f11838f 1274 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 235:685d5f11838f 1275 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 235:685d5f11838f 1276 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 235:685d5f11838f 1277 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
mbed_official 235:685d5f11838f 1278 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
mbed_official 235:685d5f11838f 1279
mbed_official 235:685d5f11838f 1280 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
mbed_official 235:685d5f11838f 1281 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
mbed_official 235:685d5f11838f 1282 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
mbed_official 235:685d5f11838f 1283 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
mbed_official 235:685d5f11838f 1284 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
mbed_official 235:685d5f11838f 1285 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
mbed_official 235:685d5f11838f 1286 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
mbed_official 235:685d5f11838f 1287 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
mbed_official 235:685d5f11838f 1288 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
mbed_official 235:685d5f11838f 1289 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
mbed_official 235:685d5f11838f 1290 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
mbed_official 235:685d5f11838f 1291 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official 235:685d5f11838f 1292
mbed_official 235:685d5f11838f 1293 /** @defgroup ETH_DMA_Enhanced_descriptor_format
mbed_official 235:685d5f11838f 1294 * @{
mbed_official 235:685d5f11838f 1295 */
mbed_official 235:685d5f11838f 1296 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
mbed_official 235:685d5f11838f 1297 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1298
mbed_official 235:685d5f11838f 1299 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
mbed_official 235:685d5f11838f 1300 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
mbed_official 235:685d5f11838f 1301
mbed_official 235:685d5f11838f 1302 /**
mbed_official 235:685d5f11838f 1303 * @}
mbed_official 235:685d5f11838f 1304 */
mbed_official 235:685d5f11838f 1305
mbed_official 235:685d5f11838f 1306 /**
mbed_official 235:685d5f11838f 1307 * @brief ETH DMA Descriptor SkipLength
mbed_official 235:685d5f11838f 1308 */
mbed_official 235:685d5f11838f 1309 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
mbed_official 235:685d5f11838f 1310
mbed_official 235:685d5f11838f 1311
mbed_official 235:685d5f11838f 1312 /** @defgroup ETH_DMA_Arbitration
mbed_official 235:685d5f11838f 1313 * @{
mbed_official 235:685d5f11838f 1314 */
mbed_official 235:685d5f11838f 1315 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
mbed_official 235:685d5f11838f 1316 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
mbed_official 235:685d5f11838f 1317 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
mbed_official 235:685d5f11838f 1318 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
mbed_official 235:685d5f11838f 1319 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
mbed_official 235:685d5f11838f 1320 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
mbed_official 235:685d5f11838f 1321 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
mbed_official 235:685d5f11838f 1322 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
mbed_official 235:685d5f11838f 1323 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
mbed_official 235:685d5f11838f 1324 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
mbed_official 235:685d5f11838f 1325 /**
mbed_official 235:685d5f11838f 1326 * @}
mbed_official 235:685d5f11838f 1327 */
mbed_official 235:685d5f11838f 1328
mbed_official 235:685d5f11838f 1329 /** @defgroup ETH_DMA_Tx_descriptor_flags
mbed_official 235:685d5f11838f 1330 * @{
mbed_official 235:685d5f11838f 1331 */
mbed_official 235:685d5f11838f 1332 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
mbed_official 235:685d5f11838f 1333 ((FLAG) == ETH_DMATXDESC_IC) || \
mbed_official 235:685d5f11838f 1334 ((FLAG) == ETH_DMATXDESC_LS) || \
mbed_official 235:685d5f11838f 1335 ((FLAG) == ETH_DMATXDESC_FS) || \
mbed_official 235:685d5f11838f 1336 ((FLAG) == ETH_DMATXDESC_DC) || \
mbed_official 235:685d5f11838f 1337 ((FLAG) == ETH_DMATXDESC_DP) || \
mbed_official 235:685d5f11838f 1338 ((FLAG) == ETH_DMATXDESC_TTSE) || \
mbed_official 235:685d5f11838f 1339 ((FLAG) == ETH_DMATXDESC_TER) || \
mbed_official 235:685d5f11838f 1340 ((FLAG) == ETH_DMATXDESC_TCH) || \
mbed_official 235:685d5f11838f 1341 ((FLAG) == ETH_DMATXDESC_TTSS) || \
mbed_official 235:685d5f11838f 1342 ((FLAG) == ETH_DMATXDESC_IHE) || \
mbed_official 235:685d5f11838f 1343 ((FLAG) == ETH_DMATXDESC_ES) || \
mbed_official 235:685d5f11838f 1344 ((FLAG) == ETH_DMATXDESC_JT) || \
mbed_official 235:685d5f11838f 1345 ((FLAG) == ETH_DMATXDESC_FF) || \
mbed_official 235:685d5f11838f 1346 ((FLAG) == ETH_DMATXDESC_PCE) || \
mbed_official 235:685d5f11838f 1347 ((FLAG) == ETH_DMATXDESC_LCA) || \
mbed_official 235:685d5f11838f 1348 ((FLAG) == ETH_DMATXDESC_NC) || \
mbed_official 235:685d5f11838f 1349 ((FLAG) == ETH_DMATXDESC_LCO) || \
mbed_official 235:685d5f11838f 1350 ((FLAG) == ETH_DMATXDESC_EC) || \
mbed_official 235:685d5f11838f 1351 ((FLAG) == ETH_DMATXDESC_VF) || \
mbed_official 235:685d5f11838f 1352 ((FLAG) == ETH_DMATXDESC_CC) || \
mbed_official 235:685d5f11838f 1353 ((FLAG) == ETH_DMATXDESC_ED) || \
mbed_official 235:685d5f11838f 1354 ((FLAG) == ETH_DMATXDESC_UF) || \
mbed_official 235:685d5f11838f 1355 ((FLAG) == ETH_DMATXDESC_DB))
mbed_official 235:685d5f11838f 1356
mbed_official 235:685d5f11838f 1357 /**
mbed_official 235:685d5f11838f 1358 * @}
mbed_official 235:685d5f11838f 1359 */
mbed_official 235:685d5f11838f 1360
mbed_official 235:685d5f11838f 1361 /** @defgroup ETH_DMA_Tx_descriptor_segment
mbed_official 235:685d5f11838f 1362 * @{
mbed_official 235:685d5f11838f 1363 */
mbed_official 235:685d5f11838f 1364 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
mbed_official 235:685d5f11838f 1365 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
mbed_official 235:685d5f11838f 1366 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
mbed_official 235:685d5f11838f 1367 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
mbed_official 235:685d5f11838f 1368
mbed_official 235:685d5f11838f 1369 /**
mbed_official 235:685d5f11838f 1370 * @}
mbed_official 235:685d5f11838f 1371 */
mbed_official 235:685d5f11838f 1372
mbed_official 235:685d5f11838f 1373 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
mbed_official 235:685d5f11838f 1374 * @{
mbed_official 235:685d5f11838f 1375 */
mbed_official 235:685d5f11838f 1376 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
mbed_official 235:685d5f11838f 1377 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
mbed_official 235:685d5f11838f 1378 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
mbed_official 235:685d5f11838f 1379 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
mbed_official 235:685d5f11838f 1380 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
mbed_official 235:685d5f11838f 1381 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
mbed_official 235:685d5f11838f 1382 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
mbed_official 235:685d5f11838f 1383 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
mbed_official 235:685d5f11838f 1384 /**
mbed_official 235:685d5f11838f 1385 * @brief ETH DMA Tx Desciptor buffer size
mbed_official 235:685d5f11838f 1386 */
mbed_official 235:685d5f11838f 1387 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
mbed_official 235:685d5f11838f 1388
mbed_official 235:685d5f11838f 1389 /**
mbed_official 235:685d5f11838f 1390 * @}
mbed_official 235:685d5f11838f 1391 */
mbed_official 235:685d5f11838f 1392
mbed_official 235:685d5f11838f 1393 /** @defgroup ETH_DMA_Rx_descriptor_flags
mbed_official 235:685d5f11838f 1394 * @{
mbed_official 235:685d5f11838f 1395 */
mbed_official 235:685d5f11838f 1396 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
mbed_official 235:685d5f11838f 1397 ((FLAG) == ETH_DMARXDESC_AFM) || \
mbed_official 235:685d5f11838f 1398 ((FLAG) == ETH_DMARXDESC_ES) || \
mbed_official 235:685d5f11838f 1399 ((FLAG) == ETH_DMARXDESC_DE) || \
mbed_official 235:685d5f11838f 1400 ((FLAG) == ETH_DMARXDESC_SAF) || \
mbed_official 235:685d5f11838f 1401 ((FLAG) == ETH_DMARXDESC_LE) || \
mbed_official 235:685d5f11838f 1402 ((FLAG) == ETH_DMARXDESC_OE) || \
mbed_official 235:685d5f11838f 1403 ((FLAG) == ETH_DMARXDESC_VLAN) || \
mbed_official 235:685d5f11838f 1404 ((FLAG) == ETH_DMARXDESC_FS) || \
mbed_official 235:685d5f11838f 1405 ((FLAG) == ETH_DMARXDESC_LS) || \
mbed_official 235:685d5f11838f 1406 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
mbed_official 235:685d5f11838f 1407 ((FLAG) == ETH_DMARXDESC_LC) || \
mbed_official 235:685d5f11838f 1408 ((FLAG) == ETH_DMARXDESC_FT) || \
mbed_official 235:685d5f11838f 1409 ((FLAG) == ETH_DMARXDESC_RWT) || \
mbed_official 235:685d5f11838f 1410 ((FLAG) == ETH_DMARXDESC_RE) || \
mbed_official 235:685d5f11838f 1411 ((FLAG) == ETH_DMARXDESC_DBE) || \
mbed_official 235:685d5f11838f 1412 ((FLAG) == ETH_DMARXDESC_CE) || \
mbed_official 235:685d5f11838f 1413 ((FLAG) == ETH_DMARXDESC_MAMPCE))
mbed_official 235:685d5f11838f 1414
mbed_official 235:685d5f11838f 1415 /* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
mbed_official 235:685d5f11838f 1416 #define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
mbed_official 235:685d5f11838f 1417 ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
mbed_official 235:685d5f11838f 1418 ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
mbed_official 235:685d5f11838f 1419 ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
mbed_official 235:685d5f11838f 1420 ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
mbed_official 235:685d5f11838f 1421 ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
mbed_official 235:685d5f11838f 1422 ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
mbed_official 235:685d5f11838f 1423 ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
mbed_official 235:685d5f11838f 1424 ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
mbed_official 235:685d5f11838f 1425
mbed_official 235:685d5f11838f 1426 /**
mbed_official 235:685d5f11838f 1427 * @}
mbed_official 235:685d5f11838f 1428 */
mbed_official 235:685d5f11838f 1429
mbed_official 235:685d5f11838f 1430 /** @defgroup ETH_DMA_Rx_descriptor_buffers_
mbed_official 235:685d5f11838f 1431 * @{
mbed_official 235:685d5f11838f 1432 */
mbed_official 235:685d5f11838f 1433 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
mbed_official 235:685d5f11838f 1434 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
mbed_official 235:685d5f11838f 1435 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
mbed_official 235:685d5f11838f 1436 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
mbed_official 235:685d5f11838f 1437
mbed_official 235:685d5f11838f 1438
mbed_official 235:685d5f11838f 1439 /* ETHERNET DMA Tx descriptors Collision Count Shift */
mbed_official 235:685d5f11838f 1440 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
mbed_official 235:685d5f11838f 1441
mbed_official 235:685d5f11838f 1442 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
mbed_official 235:685d5f11838f 1443 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official 235:685d5f11838f 1444
mbed_official 235:685d5f11838f 1445 /* ETHERNET DMA Rx descriptors Frame Length Shift */
mbed_official 235:685d5f11838f 1446 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
mbed_official 235:685d5f11838f 1447
mbed_official 235:685d5f11838f 1448 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
mbed_official 235:685d5f11838f 1449 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official 235:685d5f11838f 1450
mbed_official 235:685d5f11838f 1451 /* ETHERNET DMA Rx descriptors Frame length Shift */
mbed_official 235:685d5f11838f 1452 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
mbed_official 235:685d5f11838f 1453
mbed_official 235:685d5f11838f 1454 /**
mbed_official 235:685d5f11838f 1455 * @}
mbed_official 235:685d5f11838f 1456 */
mbed_official 235:685d5f11838f 1457
mbed_official 235:685d5f11838f 1458 /** @defgroup ETH_PMT_Flags
mbed_official 235:685d5f11838f 1459 * @{
mbed_official 235:685d5f11838f 1460 */
mbed_official 235:685d5f11838f 1461 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
mbed_official 235:685d5f11838f 1462 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
mbed_official 235:685d5f11838f 1463 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
mbed_official 235:685d5f11838f 1464 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
mbed_official 235:685d5f11838f 1465 ((FLAG) == ETH_PMT_FLAG_MPR))
mbed_official 235:685d5f11838f 1466 /**
mbed_official 235:685d5f11838f 1467 * @}
mbed_official 235:685d5f11838f 1468 */
mbed_official 235:685d5f11838f 1469
mbed_official 235:685d5f11838f 1470 /** @defgroup ETH_MMC_Tx_Interrupts
mbed_official 235:685d5f11838f 1471 * @{
mbed_official 235:685d5f11838f 1472 */
mbed_official 235:685d5f11838f 1473 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
mbed_official 235:685d5f11838f 1474 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
mbed_official 235:685d5f11838f 1475 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
mbed_official 235:685d5f11838f 1476
mbed_official 235:685d5f11838f 1477 /**
mbed_official 235:685d5f11838f 1478 * @}
mbed_official 235:685d5f11838f 1479 */
mbed_official 235:685d5f11838f 1480
mbed_official 235:685d5f11838f 1481 /** @defgroup ETH_MMC_Rx_Interrupts
mbed_official 235:685d5f11838f 1482 * @{
mbed_official 235:685d5f11838f 1483 */
mbed_official 235:685d5f11838f 1484 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
mbed_official 235:685d5f11838f 1485 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
mbed_official 235:685d5f11838f 1486 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
mbed_official 235:685d5f11838f 1487 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
mbed_official 235:685d5f11838f 1488 ((IT) != 0x00))
mbed_official 235:685d5f11838f 1489 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
mbed_official 235:685d5f11838f 1490 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
mbed_official 235:685d5f11838f 1491 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
mbed_official 235:685d5f11838f 1492 /**
mbed_official 235:685d5f11838f 1493 * @}
mbed_official 235:685d5f11838f 1494 */
mbed_official 235:685d5f11838f 1495
mbed_official 235:685d5f11838f 1496 /** @defgroup ETH_MMC_Registers
mbed_official 235:685d5f11838f 1497 * @{
mbed_official 235:685d5f11838f 1498 */
mbed_official 235:685d5f11838f 1499 #define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
mbed_official 235:685d5f11838f 1500 #define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
mbed_official 235:685d5f11838f 1501 #define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
mbed_official 235:685d5f11838f 1502 #define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
mbed_official 235:685d5f11838f 1503 #define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
mbed_official 235:685d5f11838f 1504 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
mbed_official 235:685d5f11838f 1505 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
mbed_official 235:685d5f11838f 1506 #define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
mbed_official 235:685d5f11838f 1507 #define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
mbed_official 235:685d5f11838f 1508 #define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
mbed_official 235:685d5f11838f 1509 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
mbed_official 235:685d5f11838f 1510
mbed_official 235:685d5f11838f 1511 /**
mbed_official 235:685d5f11838f 1512 * @brief ETH MMC registers
mbed_official 235:685d5f11838f 1513 */
mbed_official 235:685d5f11838f 1514 #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
mbed_official 235:685d5f11838f 1515 ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
mbed_official 235:685d5f11838f 1516 ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
mbed_official 235:685d5f11838f 1517 ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
mbed_official 235:685d5f11838f 1518 ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
mbed_official 235:685d5f11838f 1519 ((REG) == ETH_MMCRGUFCR))
mbed_official 235:685d5f11838f 1520 /**
mbed_official 235:685d5f11838f 1521 * @}
mbed_official 235:685d5f11838f 1522 */
mbed_official 235:685d5f11838f 1523
mbed_official 235:685d5f11838f 1524 /** @defgroup ETH_MAC_Flags
mbed_official 235:685d5f11838f 1525 * @{
mbed_official 235:685d5f11838f 1526 */
mbed_official 235:685d5f11838f 1527 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
mbed_official 235:685d5f11838f 1528 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
mbed_official 235:685d5f11838f 1529 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
mbed_official 235:685d5f11838f 1530 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
mbed_official 235:685d5f11838f 1531 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
mbed_official 235:685d5f11838f 1532 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
mbed_official 235:685d5f11838f 1533 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
mbed_official 235:685d5f11838f 1534 ((FLAG) == ETH_MAC_FLAG_PMT))
mbed_official 235:685d5f11838f 1535 /**
mbed_official 235:685d5f11838f 1536 * @}
mbed_official 235:685d5f11838f 1537 */
mbed_official 235:685d5f11838f 1538
mbed_official 235:685d5f11838f 1539 /** @defgroup ETH_DMA_Flags
mbed_official 235:685d5f11838f 1540 * @{
mbed_official 235:685d5f11838f 1541 */
mbed_official 235:685d5f11838f 1542 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
mbed_official 235:685d5f11838f 1543 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
mbed_official 235:685d5f11838f 1544 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
mbed_official 235:685d5f11838f 1545 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
mbed_official 235:685d5f11838f 1546 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
mbed_official 235:685d5f11838f 1547 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
mbed_official 235:685d5f11838f 1548 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
mbed_official 235:685d5f11838f 1549 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
mbed_official 235:685d5f11838f 1550 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
mbed_official 235:685d5f11838f 1551 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
mbed_official 235:685d5f11838f 1552 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
mbed_official 235:685d5f11838f 1553 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
mbed_official 235:685d5f11838f 1554 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
mbed_official 235:685d5f11838f 1555 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
mbed_official 235:685d5f11838f 1556 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
mbed_official 235:685d5f11838f 1557 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
mbed_official 235:685d5f11838f 1558 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
mbed_official 235:685d5f11838f 1559 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
mbed_official 235:685d5f11838f 1560 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
mbed_official 235:685d5f11838f 1561 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
mbed_official 235:685d5f11838f 1562 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
mbed_official 235:685d5f11838f 1563
mbed_official 235:685d5f11838f 1564 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
mbed_official 235:685d5f11838f 1565 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
mbed_official 235:685d5f11838f 1566 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
mbed_official 235:685d5f11838f 1567 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
mbed_official 235:685d5f11838f 1568 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
mbed_official 235:685d5f11838f 1569 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
mbed_official 235:685d5f11838f 1570 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
mbed_official 235:685d5f11838f 1571 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
mbed_official 235:685d5f11838f 1572 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
mbed_official 235:685d5f11838f 1573 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
mbed_official 235:685d5f11838f 1574 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
mbed_official 235:685d5f11838f 1575 ((FLAG) == ETH_DMA_FLAG_T))
mbed_official 235:685d5f11838f 1576 /**
mbed_official 235:685d5f11838f 1577 * @}
mbed_official 235:685d5f11838f 1578 */
mbed_official 235:685d5f11838f 1579
mbed_official 235:685d5f11838f 1580 /** @defgroup ETH_MAC_Interrupts
mbed_official 235:685d5f11838f 1581 * @{
mbed_official 235:685d5f11838f 1582 */
mbed_official 235:685d5f11838f 1583 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
mbed_official 235:685d5f11838f 1584 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
mbed_official 235:685d5f11838f 1585 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
mbed_official 235:685d5f11838f 1586 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
mbed_official 235:685d5f11838f 1587 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
mbed_official 235:685d5f11838f 1588 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
mbed_official 235:685d5f11838f 1589 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
mbed_official 235:685d5f11838f 1590 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
mbed_official 235:685d5f11838f 1591 ((IT) == ETH_MAC_IT_PMT))
mbed_official 235:685d5f11838f 1592 /**
mbed_official 235:685d5f11838f 1593 * @}
mbed_official 235:685d5f11838f 1594 */
mbed_official 235:685d5f11838f 1595
mbed_official 235:685d5f11838f 1596 /** @defgroup ETH_DMA_Interrupts
mbed_official 235:685d5f11838f 1597 * @{
mbed_official 235:685d5f11838f 1598 */
mbed_official 235:685d5f11838f 1599 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
mbed_official 235:685d5f11838f 1600 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
mbed_official 235:685d5f11838f 1601 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
mbed_official 235:685d5f11838f 1602 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
mbed_official 235:685d5f11838f 1603 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
mbed_official 235:685d5f11838f 1604 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
mbed_official 235:685d5f11838f 1605 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
mbed_official 235:685d5f11838f 1606 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
mbed_official 235:685d5f11838f 1607 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
mbed_official 235:685d5f11838f 1608 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
mbed_official 235:685d5f11838f 1609 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
mbed_official 235:685d5f11838f 1610 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
mbed_official 235:685d5f11838f 1611 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
mbed_official 235:685d5f11838f 1612 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
mbed_official 235:685d5f11838f 1613 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
mbed_official 235:685d5f11838f 1614 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
mbed_official 235:685d5f11838f 1615 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
mbed_official 235:685d5f11838f 1616 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
mbed_official 235:685d5f11838f 1617
mbed_official 235:685d5f11838f 1618 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
mbed_official 235:685d5f11838f 1619 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
mbed_official 235:685d5f11838f 1620 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
mbed_official 235:685d5f11838f 1621 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
mbed_official 235:685d5f11838f 1622 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
mbed_official 235:685d5f11838f 1623 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
mbed_official 235:685d5f11838f 1624 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
mbed_official 235:685d5f11838f 1625 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
mbed_official 235:685d5f11838f 1626 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
mbed_official 235:685d5f11838f 1627 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
mbed_official 235:685d5f11838f 1628
mbed_official 235:685d5f11838f 1629 /**
mbed_official 235:685d5f11838f 1630 * @}
mbed_official 235:685d5f11838f 1631 */
mbed_official 235:685d5f11838f 1632
mbed_official 235:685d5f11838f 1633 /** @defgroup ETH_DMA_transmit_process_state_
mbed_official 235:685d5f11838f 1634 * @{
mbed_official 235:685d5f11838f 1635 */
mbed_official 235:685d5f11838f 1636 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
mbed_official 235:685d5f11838f 1637 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
mbed_official 235:685d5f11838f 1638 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
mbed_official 235:685d5f11838f 1639 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
mbed_official 235:685d5f11838f 1640 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
mbed_official 235:685d5f11838f 1641 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
mbed_official 235:685d5f11838f 1642
mbed_official 235:685d5f11838f 1643 /**
mbed_official 235:685d5f11838f 1644 * @}
mbed_official 235:685d5f11838f 1645 */
mbed_official 235:685d5f11838f 1646
mbed_official 235:685d5f11838f 1647
mbed_official 235:685d5f11838f 1648 /** @defgroup ETH_DMA_receive_process_state_
mbed_official 235:685d5f11838f 1649 * @{
mbed_official 235:685d5f11838f 1650 */
mbed_official 235:685d5f11838f 1651 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
mbed_official 235:685d5f11838f 1652 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
mbed_official 235:685d5f11838f 1653 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
mbed_official 235:685d5f11838f 1654 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
mbed_official 235:685d5f11838f 1655 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
mbed_official 235:685d5f11838f 1656 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
mbed_official 235:685d5f11838f 1657
mbed_official 235:685d5f11838f 1658 /**
mbed_official 235:685d5f11838f 1659 * @}
mbed_official 235:685d5f11838f 1660 */
mbed_official 235:685d5f11838f 1661
mbed_official 235:685d5f11838f 1662 /** @defgroup ETH_DMA_overflow_
mbed_official 235:685d5f11838f 1663 * @{
mbed_official 235:685d5f11838f 1664 */
mbed_official 235:685d5f11838f 1665 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
mbed_official 235:685d5f11838f 1666 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
mbed_official 235:685d5f11838f 1667 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
mbed_official 235:685d5f11838f 1668 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
mbed_official 235:685d5f11838f 1669 /**
mbed_official 235:685d5f11838f 1670 * @}
mbed_official 235:685d5f11838f 1671 */
mbed_official 235:685d5f11838f 1672
mbed_official 235:685d5f11838f 1673 /* ETHERNET MAC address offsets */
mbed_official 235:685d5f11838f 1674 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
mbed_official 235:685d5f11838f 1675 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
mbed_official 235:685d5f11838f 1676
mbed_official 235:685d5f11838f 1677 /* ETHERNET MACMIIAR register Mask */
mbed_official 235:685d5f11838f 1678 #define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
mbed_official 235:685d5f11838f 1679
mbed_official 235:685d5f11838f 1680 /* ETHERNET MACCR register Mask */
mbed_official 235:685d5f11838f 1681 #define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
mbed_official 235:685d5f11838f 1682
mbed_official 235:685d5f11838f 1683 /* ETHERNET MACFCR register Mask */
mbed_official 235:685d5f11838f 1684 #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
mbed_official 235:685d5f11838f 1685
mbed_official 235:685d5f11838f 1686
mbed_official 235:685d5f11838f 1687 /* ETHERNET DMAOMR register Mask */
mbed_official 235:685d5f11838f 1688 #define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
mbed_official 235:685d5f11838f 1689
mbed_official 235:685d5f11838f 1690
mbed_official 235:685d5f11838f 1691 /* ETHERNET Remote Wake-up frame register length */
mbed_official 235:685d5f11838f 1692 #define ETH_WAKEUP_REGISTER_LENGTH 8
mbed_official 235:685d5f11838f 1693
mbed_official 235:685d5f11838f 1694 /* ETHERNET Missed frames counter Shift */
mbed_official 235:685d5f11838f 1695 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
mbed_official 235:685d5f11838f 1696
mbed_official 235:685d5f11838f 1697 /**
mbed_official 235:685d5f11838f 1698 * @}
mbed_official 235:685d5f11838f 1699 */
mbed_official 235:685d5f11838f 1700
mbed_official 235:685d5f11838f 1701 /* Exported macro ------------------------------------------------------------*/
mbed_official 235:685d5f11838f 1702
mbed_official 235:685d5f11838f 1703 /** @brief Reset ETH handle state
mbed_official 235:685d5f11838f 1704 * @param __HANDLE__: specifies the ETH handle.
mbed_official 235:685d5f11838f 1705 * @retval None
mbed_official 235:685d5f11838f 1706 */
mbed_official 235:685d5f11838f 1707 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
mbed_official 235:685d5f11838f 1708
mbed_official 235:685d5f11838f 1709 /**
mbed_official 235:685d5f11838f 1710 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
mbed_official 235:685d5f11838f 1711 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1712 * @param __FLAG__: specifies the flag to check.
mbed_official 235:685d5f11838f 1713 * @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official 235:685d5f11838f 1714 */
mbed_official 235:685d5f11838f 1715 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official 235:685d5f11838f 1716
mbed_official 235:685d5f11838f 1717 /**
mbed_official 235:685d5f11838f 1718 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
mbed_official 235:685d5f11838f 1719 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1720 * @param __FLAG__: specifies the flag to check.
mbed_official 235:685d5f11838f 1721 * @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official 235:685d5f11838f 1722 */
mbed_official 235:685d5f11838f 1723 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official 235:685d5f11838f 1724
mbed_official 235:685d5f11838f 1725 /**
mbed_official 235:685d5f11838f 1726 * @brief Enables the specified DMA Rx Desc receive interrupt.
mbed_official 235:685d5f11838f 1727 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1728 * @retval None
mbed_official 235:685d5f11838f 1729 */
mbed_official 235:685d5f11838f 1730 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
mbed_official 235:685d5f11838f 1731
mbed_official 235:685d5f11838f 1732 /**
mbed_official 235:685d5f11838f 1733 * @brief Disables the specified DMA Rx Desc receive interrupt.
mbed_official 235:685d5f11838f 1734 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1735 * @retval None
mbed_official 235:685d5f11838f 1736 */
mbed_official 235:685d5f11838f 1737 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
mbed_official 235:685d5f11838f 1738
mbed_official 235:685d5f11838f 1739 /**
mbed_official 235:685d5f11838f 1740 * @brief Set the specified DMA Rx Desc Own bit.
mbed_official 235:685d5f11838f 1741 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1742 * @retval None
mbed_official 235:685d5f11838f 1743 */
mbed_official 235:685d5f11838f 1744 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
mbed_official 235:685d5f11838f 1745
mbed_official 235:685d5f11838f 1746 /**
mbed_official 235:685d5f11838f 1747 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
mbed_official 235:685d5f11838f 1748 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1749 * @retval The Transmit descriptor collision counter value.
mbed_official 235:685d5f11838f 1750 */
mbed_official 235:685d5f11838f 1751 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
mbed_official 235:685d5f11838f 1752
mbed_official 235:685d5f11838f 1753 /**
mbed_official 235:685d5f11838f 1754 * @brief Set the specified DMA Tx Desc Own bit.
mbed_official 235:685d5f11838f 1755 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1756 * @retval None
mbed_official 235:685d5f11838f 1757 */
mbed_official 235:685d5f11838f 1758 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
mbed_official 235:685d5f11838f 1759
mbed_official 235:685d5f11838f 1760 /**
mbed_official 235:685d5f11838f 1761 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
mbed_official 235:685d5f11838f 1762 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1763 * @retval None
mbed_official 235:685d5f11838f 1764 */
mbed_official 235:685d5f11838f 1765 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
mbed_official 235:685d5f11838f 1766
mbed_official 235:685d5f11838f 1767 /**
mbed_official 235:685d5f11838f 1768 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
mbed_official 235:685d5f11838f 1769 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1770 * @retval None
mbed_official 235:685d5f11838f 1771 */
mbed_official 235:685d5f11838f 1772 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
mbed_official 235:685d5f11838f 1773
mbed_official 235:685d5f11838f 1774 /**
mbed_official 235:685d5f11838f 1775 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
mbed_official 235:685d5f11838f 1776 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1777 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
mbed_official 235:685d5f11838f 1778 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1779 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
mbed_official 235:685d5f11838f 1780 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
mbed_official 235:685d5f11838f 1781 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
mbed_official 235:685d5f11838f 1782 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
mbed_official 235:685d5f11838f 1783 * @retval None
mbed_official 235:685d5f11838f 1784 */
mbed_official 235:685d5f11838f 1785 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
mbed_official 235:685d5f11838f 1786
mbed_official 235:685d5f11838f 1787 /**
mbed_official 235:685d5f11838f 1788 * @brief Enables the DMA Tx Desc CRC.
mbed_official 235:685d5f11838f 1789 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1790 * @retval None
mbed_official 235:685d5f11838f 1791 */
mbed_official 235:685d5f11838f 1792 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
mbed_official 235:685d5f11838f 1793
mbed_official 235:685d5f11838f 1794 /**
mbed_official 235:685d5f11838f 1795 * @brief Disables the DMA Tx Desc CRC.
mbed_official 235:685d5f11838f 1796 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1797 * @retval None
mbed_official 235:685d5f11838f 1798 */
mbed_official 235:685d5f11838f 1799 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
mbed_official 235:685d5f11838f 1800
mbed_official 235:685d5f11838f 1801 /**
mbed_official 235:685d5f11838f 1802 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official 235:685d5f11838f 1803 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1804 * @retval None
mbed_official 235:685d5f11838f 1805 */
mbed_official 235:685d5f11838f 1806 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
mbed_official 235:685d5f11838f 1807
mbed_official 235:685d5f11838f 1808 /**
mbed_official 235:685d5f11838f 1809 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official 235:685d5f11838f 1810 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1811 * @retval None
mbed_official 235:685d5f11838f 1812 */
mbed_official 235:685d5f11838f 1813 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
mbed_official 235:685d5f11838f 1814
mbed_official 235:685d5f11838f 1815 /**
mbed_official 235:685d5f11838f 1816 * @brief Enables the specified ETHERNET MAC interrupts.
mbed_official 235:685d5f11838f 1817 * @param __HANDLE__ : ETH Handle
mbed_official 235:685d5f11838f 1818 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official 235:685d5f11838f 1819 * enabled or disabled.
mbed_official 235:685d5f11838f 1820 * This parameter can be any combination of the following values:
mbed_official 235:685d5f11838f 1821 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official 235:685d5f11838f 1822 * @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official 235:685d5f11838f 1823 * @retval None
mbed_official 235:685d5f11838f 1824 */
mbed_official 235:685d5f11838f 1825 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
mbed_official 235:685d5f11838f 1826
mbed_official 235:685d5f11838f 1827 /**
mbed_official 235:685d5f11838f 1828 * @brief Disables the specified ETHERNET MAC interrupts.
mbed_official 235:685d5f11838f 1829 * @param __HANDLE__ : ETH Handle
mbed_official 235:685d5f11838f 1830 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official 235:685d5f11838f 1831 * enabled or disabled.
mbed_official 235:685d5f11838f 1832 * This parameter can be any combination of the following values:
mbed_official 235:685d5f11838f 1833 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official 235:685d5f11838f 1834 * @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official 235:685d5f11838f 1835 * @retval None
mbed_official 235:685d5f11838f 1836 */
mbed_official 235:685d5f11838f 1837 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
mbed_official 235:685d5f11838f 1838
mbed_official 235:685d5f11838f 1839 /**
mbed_official 235:685d5f11838f 1840 * @brief Initiate a Pause Control Frame (Full-duplex only).
mbed_official 235:685d5f11838f 1841 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1842 * @retval None
mbed_official 235:685d5f11838f 1843 */
mbed_official 235:685d5f11838f 1844 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
mbed_official 235:685d5f11838f 1845
mbed_official 235:685d5f11838f 1846 /**
mbed_official 235:685d5f11838f 1847 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
mbed_official 235:685d5f11838f 1848 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1849 * @retval The new state of flow control busy status bit (SET or RESET).
mbed_official 235:685d5f11838f 1850 */
mbed_official 235:685d5f11838f 1851 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
mbed_official 235:685d5f11838f 1852
mbed_official 235:685d5f11838f 1853 /**
mbed_official 235:685d5f11838f 1854 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
mbed_official 235:685d5f11838f 1855 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1856 * @retval None
mbed_official 235:685d5f11838f 1857 */
mbed_official 235:685d5f11838f 1858 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
mbed_official 235:685d5f11838f 1859
mbed_official 235:685d5f11838f 1860 /**
mbed_official 235:685d5f11838f 1861 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
mbed_official 235:685d5f11838f 1862 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1863 * @retval None
mbed_official 235:685d5f11838f 1864 */
mbed_official 235:685d5f11838f 1865 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
mbed_official 235:685d5f11838f 1866
mbed_official 235:685d5f11838f 1867 /**
mbed_official 235:685d5f11838f 1868 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
mbed_official 235:685d5f11838f 1869 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1870 * @param __FLAG__: specifies the flag to check.
mbed_official 235:685d5f11838f 1871 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1872 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
mbed_official 235:685d5f11838f 1873 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
mbed_official 235:685d5f11838f 1874 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
mbed_official 235:685d5f11838f 1875 * @arg ETH_MAC_FLAG_MMC : MMC flag
mbed_official 235:685d5f11838f 1876 * @arg ETH_MAC_FLAG_PMT : PMT flag
mbed_official 235:685d5f11838f 1877 * @retval The state of ETHERNET MAC flag.
mbed_official 235:685d5f11838f 1878 */
mbed_official 235:685d5f11838f 1879 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
mbed_official 235:685d5f11838f 1880
mbed_official 235:685d5f11838f 1881 /**
mbed_official 235:685d5f11838f 1882 * @brief Enables the specified ETHERNET DMA interrupts.
mbed_official 235:685d5f11838f 1883 * @param __HANDLE__ : ETH Handle
mbed_official 235:685d5f11838f 1884 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official 235:685d5f11838f 1885 * enabled @defgroup ETH_DMA_Interrupts
mbed_official 235:685d5f11838f 1886 * @retval None
mbed_official 235:685d5f11838f 1887 */
mbed_official 235:685d5f11838f 1888 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
mbed_official 235:685d5f11838f 1889
mbed_official 235:685d5f11838f 1890 /**
mbed_official 235:685d5f11838f 1891 * @brief Disables the specified ETHERNET DMA interrupts.
mbed_official 235:685d5f11838f 1892 * @param __HANDLE__ : ETH Handle
mbed_official 235:685d5f11838f 1893 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official 235:685d5f11838f 1894 * disabled. @defgroup ETH_DMA_Interrupts
mbed_official 235:685d5f11838f 1895 * @retval None
mbed_official 235:685d5f11838f 1896 */
mbed_official 235:685d5f11838f 1897 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
mbed_official 235:685d5f11838f 1898
mbed_official 235:685d5f11838f 1899 /**
mbed_official 235:685d5f11838f 1900 * @brief Clears the ETHERNET DMA IT pending bit.
mbed_official 235:685d5f11838f 1901 * @param __HANDLE__ : ETH Handle
mbed_official 235:685d5f11838f 1902 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
mbed_official 235:685d5f11838f 1903 * @retval None
mbed_official 235:685d5f11838f 1904 */
mbed_official 235:685d5f11838f 1905 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
mbed_official 235:685d5f11838f 1906
mbed_official 235:685d5f11838f 1907 /**
mbed_official 235:685d5f11838f 1908 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official 235:685d5f11838f 1909 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1910 * @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags
mbed_official 235:685d5f11838f 1911 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official 235:685d5f11838f 1912 */
mbed_official 235:685d5f11838f 1913 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
mbed_official 235:685d5f11838f 1914
mbed_official 235:685d5f11838f 1915 /**
mbed_official 235:685d5f11838f 1916 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official 235:685d5f11838f 1917 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1918 * @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags
mbed_official 235:685d5f11838f 1919 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official 235:685d5f11838f 1920 */
mbed_official 235:685d5f11838f 1921 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
mbed_official 235:685d5f11838f 1922
mbed_official 235:685d5f11838f 1923 /**
mbed_official 235:685d5f11838f 1924 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
mbed_official 235:685d5f11838f 1925 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1926 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
mbed_official 235:685d5f11838f 1927 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1928 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
mbed_official 235:685d5f11838f 1929 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
mbed_official 235:685d5f11838f 1930 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
mbed_official 235:685d5f11838f 1931 */
mbed_official 235:685d5f11838f 1932 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
mbed_official 235:685d5f11838f 1933
mbed_official 235:685d5f11838f 1934 /**
mbed_official 235:685d5f11838f 1935 * @brief Set the DMA Receive status watchdog timer register value
mbed_official 235:685d5f11838f 1936 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1937 * @param __VALUE__: DMA Receive status watchdog timer register value
mbed_official 235:685d5f11838f 1938 * @retval None
mbed_official 235:685d5f11838f 1939 */
mbed_official 235:685d5f11838f 1940 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
mbed_official 235:685d5f11838f 1941
mbed_official 235:685d5f11838f 1942 /**
mbed_official 235:685d5f11838f 1943 * @brief Enables any unicast packet filtered by the MAC address
mbed_official 235:685d5f11838f 1944 * recognition to be a wake-up frame.
mbed_official 235:685d5f11838f 1945 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 1946 * @retval None
mbed_official 235:685d5f11838f 1947 */
mbed_official 235:685d5f11838f 1948 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
mbed_official 235:685d5f11838f 1949
mbed_official 235:685d5f11838f 1950 /**
mbed_official 235:685d5f11838f 1951 * @brief Disables any unicast packet filtered by the MAC address
mbed_official 235:685d5f11838f 1952 * recognition to be a wake-up frame.
mbed_official 235:685d5f11838f 1953 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 1954 * @retval None
mbed_official 235:685d5f11838f 1955 */
mbed_official 235:685d5f11838f 1956 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
mbed_official 235:685d5f11838f 1957
mbed_official 235:685d5f11838f 1958 /**
mbed_official 235:685d5f11838f 1959 * @brief Enables the MAC Wake-Up Frame Detection.
mbed_official 235:685d5f11838f 1960 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 1961 * @retval None
mbed_official 235:685d5f11838f 1962 */
mbed_official 235:685d5f11838f 1963 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
mbed_official 235:685d5f11838f 1964
mbed_official 235:685d5f11838f 1965 /**
mbed_official 235:685d5f11838f 1966 * @brief Disables the MAC Wake-Up Frame Detection.
mbed_official 235:685d5f11838f 1967 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 1968 * @retval None
mbed_official 235:685d5f11838f 1969 */
mbed_official 235:685d5f11838f 1970 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official 235:685d5f11838f 1971
mbed_official 235:685d5f11838f 1972 /**
mbed_official 235:685d5f11838f 1973 * @brief Enables the MAC Magic Packet Detection.
mbed_official 235:685d5f11838f 1974 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 1975 * @retval None
mbed_official 235:685d5f11838f 1976 */
mbed_official 235:685d5f11838f 1977 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
mbed_official 235:685d5f11838f 1978
mbed_official 235:685d5f11838f 1979 /**
mbed_official 235:685d5f11838f 1980 * @brief Disables the MAC Magic Packet Detection.
mbed_official 235:685d5f11838f 1981 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 1982 * @retval None
mbed_official 235:685d5f11838f 1983 */
mbed_official 235:685d5f11838f 1984 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official 235:685d5f11838f 1985
mbed_official 235:685d5f11838f 1986 /**
mbed_official 235:685d5f11838f 1987 * @brief Enables the MAC Power Down.
mbed_official 235:685d5f11838f 1988 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1989 * @retval None
mbed_official 235:685d5f11838f 1990 */
mbed_official 235:685d5f11838f 1991 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
mbed_official 235:685d5f11838f 1992
mbed_official 235:685d5f11838f 1993 /**
mbed_official 235:685d5f11838f 1994 * @brief Disables the MAC Power Down.
mbed_official 235:685d5f11838f 1995 * @param __HANDLE__: ETH Handle
mbed_official 235:685d5f11838f 1996 * @retval None
mbed_official 235:685d5f11838f 1997 */
mbed_official 235:685d5f11838f 1998 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
mbed_official 235:685d5f11838f 1999
mbed_official 235:685d5f11838f 2000 /**
mbed_official 235:685d5f11838f 2001 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
mbed_official 235:685d5f11838f 2002 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2003 * @param __FLAG__: specifies the flag to check.
mbed_official 235:685d5f11838f 2004 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 2005 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
mbed_official 235:685d5f11838f 2006 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
mbed_official 235:685d5f11838f 2007 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
mbed_official 235:685d5f11838f 2008 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
mbed_official 235:685d5f11838f 2009 */
mbed_official 235:685d5f11838f 2010 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
mbed_official 235:685d5f11838f 2011
mbed_official 235:685d5f11838f 2012 /**
mbed_official 235:685d5f11838f 2013 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
mbed_official 235:685d5f11838f 2014 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2015 * @retval None
mbed_official 235:685d5f11838f 2016 */
mbed_official 235:685d5f11838f 2017 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
mbed_official 235:685d5f11838f 2018
mbed_official 235:685d5f11838f 2019 /**
mbed_official 235:685d5f11838f 2020 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
mbed_official 235:685d5f11838f 2021 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2022 * @retval None
mbed_official 235:685d5f11838f 2023 */
mbed_official 235:685d5f11838f 2024 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
mbed_official 235:685d5f11838f 2025 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
mbed_official 235:685d5f11838f 2026
mbed_official 235:685d5f11838f 2027 /**
mbed_official 235:685d5f11838f 2028 * @brief Enables the MMC Counter Freeze.
mbed_official 235:685d5f11838f 2029 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2030 * @retval None
mbed_official 235:685d5f11838f 2031 */
mbed_official 235:685d5f11838f 2032 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
mbed_official 235:685d5f11838f 2033
mbed_official 235:685d5f11838f 2034 /**
mbed_official 235:685d5f11838f 2035 * @brief Disables the MMC Counter Freeze.
mbed_official 235:685d5f11838f 2036 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2037 * @retval None
mbed_official 235:685d5f11838f 2038 */
mbed_official 235:685d5f11838f 2039 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
mbed_official 235:685d5f11838f 2040
mbed_official 235:685d5f11838f 2041 /**
mbed_official 235:685d5f11838f 2042 * @brief Enables the MMC Reset On Read.
mbed_official 235:685d5f11838f 2043 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2044 * @retval None
mbed_official 235:685d5f11838f 2045 */
mbed_official 235:685d5f11838f 2046 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
mbed_official 235:685d5f11838f 2047
mbed_official 235:685d5f11838f 2048 /**
mbed_official 235:685d5f11838f 2049 * @brief Disables the MMC Reset On Read.
mbed_official 235:685d5f11838f 2050 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2051 * @retval None
mbed_official 235:685d5f11838f 2052 */
mbed_official 235:685d5f11838f 2053 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
mbed_official 235:685d5f11838f 2054
mbed_official 235:685d5f11838f 2055 /**
mbed_official 235:685d5f11838f 2056 * @brief Enables the MMC Counter Stop Rollover.
mbed_official 235:685d5f11838f 2057 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2058 * @retval None
mbed_official 235:685d5f11838f 2059 */
mbed_official 235:685d5f11838f 2060 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
mbed_official 235:685d5f11838f 2061
mbed_official 235:685d5f11838f 2062 /**
mbed_official 235:685d5f11838f 2063 * @brief Disables the MMC Counter Stop Rollover.
mbed_official 235:685d5f11838f 2064 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2065 * @retval None
mbed_official 235:685d5f11838f 2066 */
mbed_official 235:685d5f11838f 2067 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
mbed_official 235:685d5f11838f 2068
mbed_official 235:685d5f11838f 2069 /**
mbed_official 235:685d5f11838f 2070 * @brief Resets the MMC Counters.
mbed_official 235:685d5f11838f 2071 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2072 * @retval None
mbed_official 235:685d5f11838f 2073 */
mbed_official 235:685d5f11838f 2074 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
mbed_official 235:685d5f11838f 2075
mbed_official 235:685d5f11838f 2076 /**
mbed_official 235:685d5f11838f 2077 * @brief Enables the specified ETHERNET MMC Rx interrupts.
mbed_official 235:685d5f11838f 2078 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2079 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 235:685d5f11838f 2080 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 2081 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official 235:685d5f11838f 2082 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official 235:685d5f11838f 2083 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official 235:685d5f11838f 2084 * @retval None
mbed_official 235:685d5f11838f 2085 */
mbed_official 235:685d5f11838f 2086 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official 235:685d5f11838f 2087 /**
mbed_official 235:685d5f11838f 2088 * @brief Disables the specified ETHERNET MMC Rx interrupts.
mbed_official 235:685d5f11838f 2089 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2090 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 235:685d5f11838f 2091 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 2092 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official 235:685d5f11838f 2093 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official 235:685d5f11838f 2094 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official 235:685d5f11838f 2095 * @retval None
mbed_official 235:685d5f11838f 2096 */
mbed_official 235:685d5f11838f 2097 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official 235:685d5f11838f 2098 /**
mbed_official 235:685d5f11838f 2099 * @brief Enables the specified ETHERNET MMC Tx interrupts.
mbed_official 235:685d5f11838f 2100 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2101 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 235:685d5f11838f 2102 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 2103 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official 235:685d5f11838f 2104 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official 235:685d5f11838f 2105 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official 235:685d5f11838f 2106 * @retval None
mbed_official 235:685d5f11838f 2107 */
mbed_official 235:685d5f11838f 2108 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
mbed_official 235:685d5f11838f 2109
mbed_official 235:685d5f11838f 2110 /**
mbed_official 235:685d5f11838f 2111 * @brief Disables the specified ETHERNET MMC Tx interrupts.
mbed_official 235:685d5f11838f 2112 * @param __HANDLE__: ETH Handle.
mbed_official 235:685d5f11838f 2113 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 235:685d5f11838f 2114 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 2115 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official 235:685d5f11838f 2116 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official 235:685d5f11838f 2117 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official 235:685d5f11838f 2118 * @retval None
mbed_official 235:685d5f11838f 2119 */
mbed_official 235:685d5f11838f 2120 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
mbed_official 235:685d5f11838f 2121
mbed_official 235:685d5f11838f 2122 /** @defgroup ETH_EXTI_LINE_WAKEUP
mbed_official 235:685d5f11838f 2123 * @{
mbed_official 235:685d5f11838f 2124 */
mbed_official 235:685d5f11838f 2125 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
mbed_official 235:685d5f11838f 2126
mbed_official 235:685d5f11838f 2127 /**
mbed_official 235:685d5f11838f 2128 * @}
mbed_official 235:685d5f11838f 2129 */
mbed_official 235:685d5f11838f 2130
mbed_official 235:685d5f11838f 2131 /**
mbed_official 235:685d5f11838f 2132 * @brief Enables the ETH External interrupt line.
mbed_official 235:685d5f11838f 2133 * @param None
mbed_official 235:685d5f11838f 2134 * @retval None
mbed_official 235:685d5f11838f 2135 */
mbed_official 235:685d5f11838f 2136 #define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 235:685d5f11838f 2137
mbed_official 235:685d5f11838f 2138 /**
mbed_official 235:685d5f11838f 2139 * @brief Disables the ETH External interrupt line.
mbed_official 235:685d5f11838f 2140 * @param None
mbed_official 235:685d5f11838f 2141 * @retval None
mbed_official 235:685d5f11838f 2142 */
mbed_official 235:685d5f11838f 2143 #define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 235:685d5f11838f 2144
mbed_official 235:685d5f11838f 2145 /**
mbed_official 235:685d5f11838f 2146 * @brief Get flag of the ETH External interrupt line.
mbed_official 235:685d5f11838f 2147 * @param None
mbed_official 235:685d5f11838f 2148 * @retval None
mbed_official 235:685d5f11838f 2149 */
mbed_official 235:685d5f11838f 2150 #define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
mbed_official 235:685d5f11838f 2151
mbed_official 235:685d5f11838f 2152 /**
mbed_official 235:685d5f11838f 2153 * @brief Clear flag of the ETH External interrupt line.
mbed_official 235:685d5f11838f 2154 * @param None
mbed_official 235:685d5f11838f 2155 * @retval None
mbed_official 235:685d5f11838f 2156 */
mbed_official 235:685d5f11838f 2157 #define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
mbed_official 235:685d5f11838f 2158
mbed_official 235:685d5f11838f 2159 /**
mbed_official 235:685d5f11838f 2160 * @brief Sets rising edge trigger to the ETH External interrupt line.
mbed_official 235:685d5f11838f 2161 * @param None
mbed_official 235:685d5f11838f 2162 * @retval None
mbed_official 235:685d5f11838f 2163 */
mbed_official 235:685d5f11838f 2164 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
mbed_official 235:685d5f11838f 2165 EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
mbed_official 235:685d5f11838f 2166
mbed_official 235:685d5f11838f 2167 /**
mbed_official 235:685d5f11838f 2168 * @brief Sets falling edge trigger to the ETH External interrupt line.
mbed_official 235:685d5f11838f 2169 * @param None
mbed_official 235:685d5f11838f 2170 * @retval None
mbed_official 235:685d5f11838f 2171 */
mbed_official 235:685d5f11838f 2172 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP);\
mbed_official 235:685d5f11838f 2173 EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 235:685d5f11838f 2174
mbed_official 235:685d5f11838f 2175 /**
mbed_official 235:685d5f11838f 2176 * @brief Sets rising/falling edge trigger to the ETH External interrupt line.
mbed_official 235:685d5f11838f 2177 * @param None
mbed_official 235:685d5f11838f 2178 * @retval None
mbed_official 235:685d5f11838f 2179 */
mbed_official 235:685d5f11838f 2180 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
mbed_official 235:685d5f11838f 2181 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
mbed_official 235:685d5f11838f 2182 EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
mbed_official 235:685d5f11838f 2183 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
mbed_official 235:685d5f11838f 2184
mbed_official 235:685d5f11838f 2185 /* Exported functions --------------------------------------------------------*/
mbed_official 235:685d5f11838f 2186
mbed_official 235:685d5f11838f 2187 /* Initialization and de-initialization functions ****************************/
mbed_official 235:685d5f11838f 2188 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2189 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2190 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2191 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2192 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
mbed_official 235:685d5f11838f 2193 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
mbed_official 235:685d5f11838f 2194
mbed_official 235:685d5f11838f 2195 /* IO operation functions ****************************************************/
mbed_official 235:685d5f11838f 2196 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
mbed_official 235:685d5f11838f 2197 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2198
mbed_official 235:685d5f11838f 2199 /* Non-Blocking mode: Interrupt */
mbed_official 235:685d5f11838f 2200 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2201 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2202
mbed_official 235:685d5f11838f 2203 /* Callback in non blocking modes (Interrupt) */
mbed_official 235:685d5f11838f 2204 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2205 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2206 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2207
mbed_official 235:685d5f11838f 2208 /* Cmmunication with PHY functions*/
mbed_official 235:685d5f11838f 2209 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
mbed_official 235:685d5f11838f 2210 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
mbed_official 235:685d5f11838f 2211
mbed_official 235:685d5f11838f 2212 /* Peripheral Control functions **********************************************/
mbed_official 235:685d5f11838f 2213 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2214 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2215
mbed_official 235:685d5f11838f 2216 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
mbed_official 235:685d5f11838f 2217 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
mbed_official 235:685d5f11838f 2218
mbed_official 235:685d5f11838f 2219 /* Peripheral State functions ************************************************/
mbed_official 235:685d5f11838f 2220 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 2221
mbed_official 235:685d5f11838f 2222 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 235:685d5f11838f 2223 /**
mbed_official 235:685d5f11838f 2224 * @}
mbed_official 235:685d5f11838f 2225 */
mbed_official 235:685d5f11838f 2226
mbed_official 235:685d5f11838f 2227 /**
mbed_official 235:685d5f11838f 2228 * @}
mbed_official 235:685d5f11838f 2229 */
mbed_official 235:685d5f11838f 2230
mbed_official 235:685d5f11838f 2231 #ifdef __cplusplus
mbed_official 235:685d5f11838f 2232 }
mbed_official 235:685d5f11838f 2233 #endif
mbed_official 235:685d5f11838f 2234
mbed_official 235:685d5f11838f 2235 #endif /* __STM32F4xx_HAL_ETH_H */
mbed_official 235:685d5f11838f 2236
mbed_official 235:685d5f11838f 2237
mbed_official 235:685d5f11838f 2238
mbed_official 235:685d5f11838f 2239 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/