shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f072xb.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
218:44081b78fdc2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 205:c41fc65bcfb4 1 /**
mbed_official 205:c41fc65bcfb4 2 ******************************************************************************
mbed_official 205:c41fc65bcfb4 3 * @file stm32f072xb.h
mbed_official 205:c41fc65bcfb4 4 * @author MCD Application Team
mbed_official 205:c41fc65bcfb4 5 * @version V2.0.0
mbed_official 218:44081b78fdc2 6 * @date 28-May-2014
mbed_official 205:c41fc65bcfb4 7 * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
mbed_official 205:c41fc65bcfb4 8 *
mbed_official 205:c41fc65bcfb4 9 * This file contains:
mbed_official 205:c41fc65bcfb4 10 * - Data structures and the address mapping for all peripherals
mbed_official 205:c41fc65bcfb4 11 * - Peripheral's registers declarations and bits definition
mbed_official 205:c41fc65bcfb4 12 * - Macros to access peripheral’s registers hardware
mbed_official 205:c41fc65bcfb4 13 *
mbed_official 205:c41fc65bcfb4 14 ******************************************************************************
mbed_official 205:c41fc65bcfb4 15 * @attention
mbed_official 205:c41fc65bcfb4 16 *
mbed_official 205:c41fc65bcfb4 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 205:c41fc65bcfb4 18 *
mbed_official 205:c41fc65bcfb4 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 205:c41fc65bcfb4 20 * are permitted provided that the following conditions are met:
mbed_official 205:c41fc65bcfb4 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 205:c41fc65bcfb4 22 * this list of conditions and the following disclaimer.
mbed_official 205:c41fc65bcfb4 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 205:c41fc65bcfb4 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 205:c41fc65bcfb4 25 * and/or other materials provided with the distribution.
mbed_official 205:c41fc65bcfb4 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 205:c41fc65bcfb4 27 * may be used to endorse or promote products derived from this software
mbed_official 205:c41fc65bcfb4 28 * without specific prior written permission.
mbed_official 205:c41fc65bcfb4 29 *
mbed_official 205:c41fc65bcfb4 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 205:c41fc65bcfb4 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 205:c41fc65bcfb4 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 205:c41fc65bcfb4 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 205:c41fc65bcfb4 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 205:c41fc65bcfb4 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 205:c41fc65bcfb4 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 205:c41fc65bcfb4 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 205:c41fc65bcfb4 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 205:c41fc65bcfb4 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 205:c41fc65bcfb4 40 *
mbed_official 205:c41fc65bcfb4 41 ******************************************************************************
mbed_official 205:c41fc65bcfb4 42 */
mbed_official 205:c41fc65bcfb4 43
mbed_official 205:c41fc65bcfb4 44 /** @addtogroup CMSIS_Device
mbed_official 205:c41fc65bcfb4 45 * @{
mbed_official 205:c41fc65bcfb4 46 */
mbed_official 205:c41fc65bcfb4 47
mbed_official 205:c41fc65bcfb4 48 /** @addtogroup stm32f072xb
mbed_official 205:c41fc65bcfb4 49 * @{
mbed_official 205:c41fc65bcfb4 50 */
mbed_official 205:c41fc65bcfb4 51
mbed_official 205:c41fc65bcfb4 52 #ifndef __STM32F072xB_H
mbed_official 205:c41fc65bcfb4 53 #define __STM32F072xB_H
mbed_official 205:c41fc65bcfb4 54
mbed_official 205:c41fc65bcfb4 55 #ifdef __cplusplus
mbed_official 205:c41fc65bcfb4 56 extern "C" {
mbed_official 205:c41fc65bcfb4 57 #endif /* __cplusplus */
mbed_official 205:c41fc65bcfb4 58
mbed_official 205:c41fc65bcfb4 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 205:c41fc65bcfb4 60 * @{
mbed_official 205:c41fc65bcfb4 61 */
mbed_official 205:c41fc65bcfb4 62
mbed_official 205:c41fc65bcfb4 63 /**
mbed_official 205:c41fc65bcfb4 64 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official 205:c41fc65bcfb4 65 */
mbed_official 205:c41fc65bcfb4 66 #define __CM0_REV 0 /*!< Core Revision r0p0 */
mbed_official 205:c41fc65bcfb4 67 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
mbed_official 205:c41fc65bcfb4 68 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
mbed_official 205:c41fc65bcfb4 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 205:c41fc65bcfb4 70
mbed_official 205:c41fc65bcfb4 71 /**
mbed_official 205:c41fc65bcfb4 72 * @}
mbed_official 205:c41fc65bcfb4 73 */
mbed_official 205:c41fc65bcfb4 74
mbed_official 205:c41fc65bcfb4 75 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 205:c41fc65bcfb4 76 * @{
mbed_official 205:c41fc65bcfb4 77 */
mbed_official 205:c41fc65bcfb4 78
mbed_official 205:c41fc65bcfb4 79 /**
mbed_official 205:c41fc65bcfb4 80 * @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
mbed_official 205:c41fc65bcfb4 81 */
mbed_official 205:c41fc65bcfb4 82 typedef enum
mbed_official 205:c41fc65bcfb4 83 {
mbed_official 205:c41fc65bcfb4 84 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
mbed_official 205:c41fc65bcfb4 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 205:c41fc65bcfb4 86 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 205:c41fc65bcfb4 87 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 205:c41fc65bcfb4 88 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 205:c41fc65bcfb4 89 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 205:c41fc65bcfb4 90
mbed_official 205:c41fc65bcfb4 91 /****** STM32F072x8/STM32F072xB specific Interrupt Numbers **************************************************/
mbed_official 205:c41fc65bcfb4 92 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 205:c41fc65bcfb4 93 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
mbed_official 205:c41fc65bcfb4 94 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
mbed_official 205:c41fc65bcfb4 95 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
mbed_official 205:c41fc65bcfb4 96 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
mbed_official 205:c41fc65bcfb4 97 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 205:c41fc65bcfb4 98 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 205:c41fc65bcfb4 99 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 205:c41fc65bcfb4 100 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
mbed_official 205:c41fc65bcfb4 101 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 205:c41fc65bcfb4 102 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 205:c41fc65bcfb4 103 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupts */
mbed_official 205:c41fc65bcfb4 104 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
mbed_official 205:c41fc65bcfb4 105 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 205:c41fc65bcfb4 106 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 205:c41fc65bcfb4 107 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
mbed_official 205:c41fc65bcfb4 108 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
mbed_official 205:c41fc65bcfb4 109 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
mbed_official 205:c41fc65bcfb4 110 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
mbed_official 205:c41fc65bcfb4 111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
mbed_official 205:c41fc65bcfb4 112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
mbed_official 205:c41fc65bcfb4 113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
mbed_official 205:c41fc65bcfb4 114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
mbed_official 205:c41fc65bcfb4 115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 205:c41fc65bcfb4 116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
mbed_official 205:c41fc65bcfb4 117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
mbed_official 205:c41fc65bcfb4 118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
mbed_official 205:c41fc65bcfb4 119 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 205:c41fc65bcfb4 120 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
mbed_official 205:c41fc65bcfb4 121 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
mbed_official 205:c41fc65bcfb4 122 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
mbed_official 205:c41fc65bcfb4 123 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
mbed_official 205:c41fc65bcfb4 124 } IRQn_Type;
mbed_official 205:c41fc65bcfb4 125
mbed_official 205:c41fc65bcfb4 126 /**
mbed_official 205:c41fc65bcfb4 127 * @}
mbed_official 205:c41fc65bcfb4 128 */
mbed_official 205:c41fc65bcfb4 129
mbed_official 205:c41fc65bcfb4 130 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official 205:c41fc65bcfb4 131 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official 205:c41fc65bcfb4 132 #include <stdint.h>
mbed_official 205:c41fc65bcfb4 133
mbed_official 205:c41fc65bcfb4 134 /** @addtogroup Peripheral_registers_structures
mbed_official 205:c41fc65bcfb4 135 * @{
mbed_official 205:c41fc65bcfb4 136 */
mbed_official 205:c41fc65bcfb4 137
mbed_official 205:c41fc65bcfb4 138 /**
mbed_official 205:c41fc65bcfb4 139 * @brief Analog to Digital Converter
mbed_official 205:c41fc65bcfb4 140 */
mbed_official 205:c41fc65bcfb4 141
mbed_official 205:c41fc65bcfb4 142 typedef struct
mbed_official 205:c41fc65bcfb4 143 {
mbed_official 205:c41fc65bcfb4 144 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
mbed_official 205:c41fc65bcfb4 145 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
mbed_official 205:c41fc65bcfb4 146 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
mbed_official 205:c41fc65bcfb4 147 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
mbed_official 205:c41fc65bcfb4 148 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
mbed_official 205:c41fc65bcfb4 149 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
mbed_official 205:c41fc65bcfb4 150 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 205:c41fc65bcfb4 151 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 205:c41fc65bcfb4 152 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
mbed_official 205:c41fc65bcfb4 153 uint32_t RESERVED3; /*!< Reserved, 0x24 */
mbed_official 205:c41fc65bcfb4 154 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
mbed_official 205:c41fc65bcfb4 155 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
mbed_official 205:c41fc65bcfb4 156 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
mbed_official 205:c41fc65bcfb4 157 }ADC_TypeDef;
mbed_official 205:c41fc65bcfb4 158
mbed_official 205:c41fc65bcfb4 159 typedef struct
mbed_official 205:c41fc65bcfb4 160 {
mbed_official 205:c41fc65bcfb4 161 __IO uint32_t CCR;
mbed_official 205:c41fc65bcfb4 162 }ADC_Common_TypeDef;
mbed_official 205:c41fc65bcfb4 163
mbed_official 205:c41fc65bcfb4 164 /**
mbed_official 205:c41fc65bcfb4 165 * @brief Controller Area Network TxMailBox
mbed_official 205:c41fc65bcfb4 166 */
mbed_official 205:c41fc65bcfb4 167 typedef struct
mbed_official 205:c41fc65bcfb4 168 {
mbed_official 205:c41fc65bcfb4 169 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 205:c41fc65bcfb4 170 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 205:c41fc65bcfb4 171 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 205:c41fc65bcfb4 172 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 205:c41fc65bcfb4 173 }CAN_TxMailBox_TypeDef;
mbed_official 205:c41fc65bcfb4 174
mbed_official 205:c41fc65bcfb4 175 /**
mbed_official 205:c41fc65bcfb4 176 * @brief Controller Area Network FIFOMailBox
mbed_official 205:c41fc65bcfb4 177 */
mbed_official 205:c41fc65bcfb4 178 typedef struct
mbed_official 205:c41fc65bcfb4 179 {
mbed_official 205:c41fc65bcfb4 180 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 205:c41fc65bcfb4 181 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 205:c41fc65bcfb4 182 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 205:c41fc65bcfb4 183 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 205:c41fc65bcfb4 184 }CAN_FIFOMailBox_TypeDef;
mbed_official 205:c41fc65bcfb4 185
mbed_official 205:c41fc65bcfb4 186 /**
mbed_official 205:c41fc65bcfb4 187 * @brief Controller Area Network FilterRegister
mbed_official 205:c41fc65bcfb4 188 */
mbed_official 205:c41fc65bcfb4 189 typedef struct
mbed_official 205:c41fc65bcfb4 190 {
mbed_official 205:c41fc65bcfb4 191 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 205:c41fc65bcfb4 192 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 205:c41fc65bcfb4 193 }CAN_FilterRegister_TypeDef;
mbed_official 205:c41fc65bcfb4 194
mbed_official 205:c41fc65bcfb4 195 /**
mbed_official 205:c41fc65bcfb4 196 * @brief Controller Area Network
mbed_official 205:c41fc65bcfb4 197 */
mbed_official 205:c41fc65bcfb4 198 typedef struct
mbed_official 205:c41fc65bcfb4 199 {
mbed_official 205:c41fc65bcfb4 200 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 201 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 202 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 203 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 204 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 205 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 206 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 207 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 208 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 205:c41fc65bcfb4 209 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 205:c41fc65bcfb4 210 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 205:c41fc65bcfb4 211 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 205:c41fc65bcfb4 212 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 205:c41fc65bcfb4 213 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 205:c41fc65bcfb4 214 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 205:c41fc65bcfb4 215 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 205:c41fc65bcfb4 216 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 205:c41fc65bcfb4 217 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 205:c41fc65bcfb4 218 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 205:c41fc65bcfb4 219 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 205:c41fc65bcfb4 220 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 205:c41fc65bcfb4 221 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 205:c41fc65bcfb4 222 }CAN_TypeDef;
mbed_official 205:c41fc65bcfb4 223
mbed_official 205:c41fc65bcfb4 224 /**
mbed_official 205:c41fc65bcfb4 225 * @brief HDMI-CEC
mbed_official 205:c41fc65bcfb4 226 */
mbed_official 205:c41fc65bcfb4 227
mbed_official 205:c41fc65bcfb4 228 typedef struct
mbed_official 205:c41fc65bcfb4 229 {
mbed_official 205:c41fc65bcfb4 230 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 205:c41fc65bcfb4 231 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 205:c41fc65bcfb4 232 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 205:c41fc65bcfb4 233 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 205:c41fc65bcfb4 234 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 205:c41fc65bcfb4 235 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 205:c41fc65bcfb4 236 }CEC_TypeDef;
mbed_official 205:c41fc65bcfb4 237
mbed_official 205:c41fc65bcfb4 238 /**
mbed_official 205:c41fc65bcfb4 239 * @brief Comparator
mbed_official 205:c41fc65bcfb4 240 */
mbed_official 205:c41fc65bcfb4 241
mbed_official 205:c41fc65bcfb4 242 typedef struct
mbed_official 205:c41fc65bcfb4 243 {
mbed_official 205:c41fc65bcfb4 244 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 245 }COMP_TypeDef;
mbed_official 205:c41fc65bcfb4 246
mbed_official 205:c41fc65bcfb4 247 /**
mbed_official 205:c41fc65bcfb4 248 * @brief CRC calculation unit
mbed_official 205:c41fc65bcfb4 249 */
mbed_official 205:c41fc65bcfb4 250
mbed_official 205:c41fc65bcfb4 251 typedef struct
mbed_official 205:c41fc65bcfb4 252 {
mbed_official 205:c41fc65bcfb4 253 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 254 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 255 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 205:c41fc65bcfb4 256 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 205:c41fc65bcfb4 257 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 258 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 205:c41fc65bcfb4 259 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 260 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 261 }CRC_TypeDef;
mbed_official 205:c41fc65bcfb4 262
mbed_official 205:c41fc65bcfb4 263 /**
mbed_official 205:c41fc65bcfb4 264 * @brief Clock Recovery System
mbed_official 205:c41fc65bcfb4 265 */
mbed_official 205:c41fc65bcfb4 266 typedef struct
mbed_official 205:c41fc65bcfb4 267 {
mbed_official 205:c41fc65bcfb4 268 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 269 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 270 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 271 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 272 }CRS_TypeDef;
mbed_official 205:c41fc65bcfb4 273
mbed_official 205:c41fc65bcfb4 274 /**
mbed_official 205:c41fc65bcfb4 275 * @brief Digital to Analog Converter
mbed_official 205:c41fc65bcfb4 276 */
mbed_official 205:c41fc65bcfb4 277
mbed_official 205:c41fc65bcfb4 278 typedef struct
mbed_official 205:c41fc65bcfb4 279 {
mbed_official 205:c41fc65bcfb4 280 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 281 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 282 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 283 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 284 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 285 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 286 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 287 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 288 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 289 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 290 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 291 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 205:c41fc65bcfb4 292 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 205:c41fc65bcfb4 293 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 205:c41fc65bcfb4 294 }DAC_TypeDef;
mbed_official 205:c41fc65bcfb4 295
mbed_official 205:c41fc65bcfb4 296 /**
mbed_official 205:c41fc65bcfb4 297 * @brief Debug MCU
mbed_official 205:c41fc65bcfb4 298 */
mbed_official 205:c41fc65bcfb4 299
mbed_official 205:c41fc65bcfb4 300 typedef struct
mbed_official 205:c41fc65bcfb4 301 {
mbed_official 205:c41fc65bcfb4 302 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 303 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 304 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 305 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 306 }DBGMCU_TypeDef;
mbed_official 205:c41fc65bcfb4 307
mbed_official 205:c41fc65bcfb4 308 /**
mbed_official 205:c41fc65bcfb4 309 * @brief DMA Controller
mbed_official 205:c41fc65bcfb4 310 */
mbed_official 205:c41fc65bcfb4 311
mbed_official 205:c41fc65bcfb4 312 typedef struct
mbed_official 205:c41fc65bcfb4 313 {
mbed_official 205:c41fc65bcfb4 314 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 205:c41fc65bcfb4 315 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 205:c41fc65bcfb4 316 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 205:c41fc65bcfb4 317 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 205:c41fc65bcfb4 318 }DMA_Channel_TypeDef;
mbed_official 205:c41fc65bcfb4 319
mbed_official 205:c41fc65bcfb4 320 typedef struct
mbed_official 205:c41fc65bcfb4 321 {
mbed_official 205:c41fc65bcfb4 322 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 323 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 324 }DMA_TypeDef;
mbed_official 205:c41fc65bcfb4 325
mbed_official 205:c41fc65bcfb4 326 /**
mbed_official 205:c41fc65bcfb4 327 * @brief External Interrupt/Event Controller
mbed_official 205:c41fc65bcfb4 328 */
mbed_official 205:c41fc65bcfb4 329
mbed_official 205:c41fc65bcfb4 330 typedef struct
mbed_official 205:c41fc65bcfb4 331 {
mbed_official 205:c41fc65bcfb4 332 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 333 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 334 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 335 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 336 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 337 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 338 }EXTI_TypeDef;
mbed_official 205:c41fc65bcfb4 339
mbed_official 205:c41fc65bcfb4 340 /**
mbed_official 205:c41fc65bcfb4 341 * @brief FLASH Registers
mbed_official 205:c41fc65bcfb4 342 */
mbed_official 205:c41fc65bcfb4 343 typedef struct
mbed_official 205:c41fc65bcfb4 344 {
mbed_official 205:c41fc65bcfb4 345 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 346 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 347 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 348 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 349 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 350 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 351 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 205:c41fc65bcfb4 352 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 353 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 354 }FLASH_TypeDef;
mbed_official 205:c41fc65bcfb4 355
mbed_official 205:c41fc65bcfb4 356
mbed_official 205:c41fc65bcfb4 357 /**
mbed_official 205:c41fc65bcfb4 358 * @brief Option Bytes Registers
mbed_official 205:c41fc65bcfb4 359 */
mbed_official 205:c41fc65bcfb4 360 typedef struct
mbed_official 205:c41fc65bcfb4 361 {
mbed_official 205:c41fc65bcfb4 362 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 363 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
mbed_official 205:c41fc65bcfb4 364 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 365 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
mbed_official 205:c41fc65bcfb4 366 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 367 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
mbed_official 205:c41fc65bcfb4 368 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 369 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
mbed_official 205:c41fc65bcfb4 370 }OB_TypeDef;
mbed_official 205:c41fc65bcfb4 371
mbed_official 205:c41fc65bcfb4 372 /**
mbed_official 205:c41fc65bcfb4 373 * @brief General Purpose I/O
mbed_official 205:c41fc65bcfb4 374 */
mbed_official 205:c41fc65bcfb4 375
mbed_official 205:c41fc65bcfb4 376 typedef struct
mbed_official 205:c41fc65bcfb4 377 {
mbed_official 205:c41fc65bcfb4 378 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 379 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 380 uint16_t RESERVED0; /*!< Reserved, 0x06 */
mbed_official 205:c41fc65bcfb4 381 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 382 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 383 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 384 uint16_t RESERVED1; /*!< Reserved, 0x12 */
mbed_official 205:c41fc65bcfb4 385 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 386 uint16_t RESERVED2; /*!< Reserved, 0x16 */
mbed_official 205:c41fc65bcfb4 387 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 388 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
mbed_official 205:c41fc65bcfb4 389 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 390 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
mbed_official 205:c41fc65bcfb4 391 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 392 uint16_t RESERVED3; /*!< Reserved, 0x2A */
mbed_official 205:c41fc65bcfb4 393 }GPIO_TypeDef;
mbed_official 205:c41fc65bcfb4 394
mbed_official 205:c41fc65bcfb4 395 /**
mbed_official 205:c41fc65bcfb4 396 * @brief SysTem Configuration
mbed_official 205:c41fc65bcfb4 397 */
mbed_official 205:c41fc65bcfb4 398
mbed_official 205:c41fc65bcfb4 399 typedef struct
mbed_official 205:c41fc65bcfb4 400 {
mbed_official 205:c41fc65bcfb4 401 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 402 uint32_t RESERVED; /*!< Reserved, 0x04 */
mbed_official 205:c41fc65bcfb4 403 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
mbed_official 205:c41fc65bcfb4 404 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 405 }SYSCFG_TypeDef;
mbed_official 205:c41fc65bcfb4 406
mbed_official 205:c41fc65bcfb4 407 /**
mbed_official 205:c41fc65bcfb4 408 * @brief Inter-integrated Circuit Interface
mbed_official 205:c41fc65bcfb4 409 */
mbed_official 205:c41fc65bcfb4 410
mbed_official 205:c41fc65bcfb4 411 typedef struct
mbed_official 205:c41fc65bcfb4 412 {
mbed_official 205:c41fc65bcfb4 413 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 414 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 415 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 416 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 417 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 418 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 419 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 420 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 421 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 422 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 423 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 424 }I2C_TypeDef;
mbed_official 205:c41fc65bcfb4 425
mbed_official 205:c41fc65bcfb4 426 /**
mbed_official 205:c41fc65bcfb4 427 * @brief Independent WATCHDOG
mbed_official 205:c41fc65bcfb4 428 */
mbed_official 205:c41fc65bcfb4 429
mbed_official 205:c41fc65bcfb4 430 typedef struct
mbed_official 205:c41fc65bcfb4 431 {
mbed_official 205:c41fc65bcfb4 432 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 433 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 434 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 435 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 436 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 437 }IWDG_TypeDef;
mbed_official 205:c41fc65bcfb4 438
mbed_official 205:c41fc65bcfb4 439 /**
mbed_official 205:c41fc65bcfb4 440 * @brief Power Control
mbed_official 205:c41fc65bcfb4 441 */
mbed_official 205:c41fc65bcfb4 442
mbed_official 205:c41fc65bcfb4 443 typedef struct
mbed_official 205:c41fc65bcfb4 444 {
mbed_official 205:c41fc65bcfb4 445 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 446 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 447 }PWR_TypeDef;
mbed_official 205:c41fc65bcfb4 448
mbed_official 205:c41fc65bcfb4 449 /**
mbed_official 205:c41fc65bcfb4 450 * @brief Reset and Clock Control
mbed_official 205:c41fc65bcfb4 451 */
mbed_official 205:c41fc65bcfb4 452 typedef struct
mbed_official 205:c41fc65bcfb4 453 {
mbed_official 205:c41fc65bcfb4 454 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 455 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 456 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 457 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 458 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 459 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 460 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 461 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 462 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 463 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 464 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 465 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 205:c41fc65bcfb4 466 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 205:c41fc65bcfb4 467 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
mbed_official 205:c41fc65bcfb4 468 }RCC_TypeDef;
mbed_official 205:c41fc65bcfb4 469
mbed_official 205:c41fc65bcfb4 470 /**
mbed_official 205:c41fc65bcfb4 471 * @brief Real-Time Clock
mbed_official 205:c41fc65bcfb4 472 */
mbed_official 205:c41fc65bcfb4 473
mbed_official 205:c41fc65bcfb4 474 typedef struct
mbed_official 205:c41fc65bcfb4 475 {
mbed_official 205:c41fc65bcfb4 476 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 477 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 478 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 479 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 480 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 481 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 482 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 483 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 484 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 485 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 486 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 487 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 205:c41fc65bcfb4 488 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 205:c41fc65bcfb4 489 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 205:c41fc65bcfb4 490 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 205:c41fc65bcfb4 491 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 205:c41fc65bcfb4 492 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 205:c41fc65bcfb4 493 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 205:c41fc65bcfb4 494 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
mbed_official 205:c41fc65bcfb4 495 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
mbed_official 205:c41fc65bcfb4 496 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 205:c41fc65bcfb4 497 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 205:c41fc65bcfb4 498 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 205:c41fc65bcfb4 499 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 205:c41fc65bcfb4 500 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 205:c41fc65bcfb4 501 }RTC_TypeDef;
mbed_official 205:c41fc65bcfb4 502
mbed_official 205:c41fc65bcfb4 503 /**
mbed_official 205:c41fc65bcfb4 504 * @brief Serial Peripheral Interface
mbed_official 205:c41fc65bcfb4 505 */
mbed_official 205:c41fc65bcfb4 506
mbed_official 205:c41fc65bcfb4 507 typedef struct
mbed_official 205:c41fc65bcfb4 508 {
mbed_official 205:c41fc65bcfb4 509 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 510 uint16_t RESERVED0; /*!< Reserved, 0x02 */
mbed_official 205:c41fc65bcfb4 511 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 512 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 205:c41fc65bcfb4 513 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 514 uint16_t RESERVED2; /*!< Reserved, 0x0A */
mbed_official 205:c41fc65bcfb4 515 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 516 uint16_t RESERVED3; /*!< Reserved, 0x0E */
mbed_official 205:c41fc65bcfb4 517 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 518 uint16_t RESERVED4; /*!< Reserved, 0x12 */
mbed_official 205:c41fc65bcfb4 519 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 520 uint16_t RESERVED5; /*!< Reserved, 0x16 */
mbed_official 205:c41fc65bcfb4 521 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 522 uint16_t RESERVED6; /*!< Reserved, 0x1A */
mbed_official 205:c41fc65bcfb4 523 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 524 uint16_t RESERVED7; /*!< Reserved, 0x1E */
mbed_official 205:c41fc65bcfb4 525 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 526 uint16_t RESERVED8; /*!< Reserved, 0x22 */
mbed_official 205:c41fc65bcfb4 527 }SPI_TypeDef;
mbed_official 205:c41fc65bcfb4 528
mbed_official 205:c41fc65bcfb4 529 /**
mbed_official 205:c41fc65bcfb4 530 * @brief TIM
mbed_official 205:c41fc65bcfb4 531 */
mbed_official 205:c41fc65bcfb4 532 typedef struct
mbed_official 205:c41fc65bcfb4 533 {
mbed_official 205:c41fc65bcfb4 534 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 535 uint16_t RESERVED0; /*!< Reserved, 0x02 */
mbed_official 205:c41fc65bcfb4 536 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 537 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 205:c41fc65bcfb4 538 __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 539 uint16_t RESERVED2; /*!< Reserved, 0x0A */
mbed_official 205:c41fc65bcfb4 540 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 541 uint16_t RESERVED3; /*!< Reserved, 0x0E */
mbed_official 205:c41fc65bcfb4 542 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 543 uint16_t RESERVED4; /*!< Reserved, 0x12 */
mbed_official 205:c41fc65bcfb4 544 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 545 uint16_t RESERVED5; /*!< Reserved, 0x16 */
mbed_official 205:c41fc65bcfb4 546 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 547 uint16_t RESERVED6; /*!< Reserved, 0x1A */
mbed_official 205:c41fc65bcfb4 548 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 549 uint16_t RESERVED7; /*!< Reserved, 0x1E */
mbed_official 205:c41fc65bcfb4 550 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 551 uint16_t RESERVED8; /*!< Reserved, 0x22 */
mbed_official 205:c41fc65bcfb4 552 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 553 __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 554 uint16_t RESERVED10; /*!< Reserved, 0x2A */
mbed_official 205:c41fc65bcfb4 555 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 205:c41fc65bcfb4 556 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 205:c41fc65bcfb4 557 uint16_t RESERVED12; /*!< Reserved, 0x32 */
mbed_official 205:c41fc65bcfb4 558 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 205:c41fc65bcfb4 559 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 205:c41fc65bcfb4 560 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 205:c41fc65bcfb4 561 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 205:c41fc65bcfb4 562 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 205:c41fc65bcfb4 563 uint16_t RESERVED17; /*!< Reserved, 0x26 */
mbed_official 205:c41fc65bcfb4 564 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 205:c41fc65bcfb4 565 uint16_t RESERVED18; /*!< Reserved, 0x4A */
mbed_official 205:c41fc65bcfb4 566 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 205:c41fc65bcfb4 567 uint16_t RESERVED19; /*!< Reserved, 0x4E */
mbed_official 205:c41fc65bcfb4 568 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 205:c41fc65bcfb4 569 uint16_t RESERVED20; /*!< Reserved, 0x52 */
mbed_official 205:c41fc65bcfb4 570 }TIM_TypeDef;
mbed_official 205:c41fc65bcfb4 571
mbed_official 205:c41fc65bcfb4 572 /**
mbed_official 205:c41fc65bcfb4 573 * @brief Touch Sensing Controller (TSC)
mbed_official 205:c41fc65bcfb4 574 */
mbed_official 205:c41fc65bcfb4 575 typedef struct
mbed_official 205:c41fc65bcfb4 576 {
mbed_official 205:c41fc65bcfb4 577 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 578 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 579 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 580 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 581 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 582 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 583 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 584 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 585 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 586 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 587 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 588 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 205:c41fc65bcfb4 589 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 205:c41fc65bcfb4 590 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 205:c41fc65bcfb4 591 }TSC_TypeDef;
mbed_official 205:c41fc65bcfb4 592
mbed_official 205:c41fc65bcfb4 593 /**
mbed_official 205:c41fc65bcfb4 594 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 205:c41fc65bcfb4 595 */
mbed_official 205:c41fc65bcfb4 596
mbed_official 205:c41fc65bcfb4 597 typedef struct
mbed_official 205:c41fc65bcfb4 598 {
mbed_official 205:c41fc65bcfb4 599 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 600 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 601 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 602 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 603 uint16_t RESERVED1; /*!< Reserved, 0x0E */
mbed_official 205:c41fc65bcfb4 604 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 605 uint16_t RESERVED2; /*!< Reserved, 0x12 */
mbed_official 205:c41fc65bcfb4 606 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 607 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 608 uint16_t RESERVED3; /*!< Reserved, 0x1A */
mbed_official 205:c41fc65bcfb4 609 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 610 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 205:c41fc65bcfb4 611 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 205:c41fc65bcfb4 612 uint16_t RESERVED4; /*!< Reserved, 0x26 */
mbed_official 205:c41fc65bcfb4 613 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 205:c41fc65bcfb4 614 uint16_t RESERVED5; /*!< Reserved, 0x2A */
mbed_official 205:c41fc65bcfb4 615 }USART_TypeDef;
mbed_official 205:c41fc65bcfb4 616
mbed_official 205:c41fc65bcfb4 617 /**
mbed_official 205:c41fc65bcfb4 618 * @brief Universal Serial Bus Full Speed Device
mbed_official 205:c41fc65bcfb4 619 */
mbed_official 205:c41fc65bcfb4 620
mbed_official 205:c41fc65bcfb4 621 typedef struct
mbed_official 205:c41fc65bcfb4 622 {
mbed_official 205:c41fc65bcfb4 623 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 624 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 625 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 626 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 627 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 628 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 629 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 205:c41fc65bcfb4 630 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 631 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 205:c41fc65bcfb4 632 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 633 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 205:c41fc65bcfb4 634 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 635 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 205:c41fc65bcfb4 636 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 637 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 205:c41fc65bcfb4 638 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 639 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 205:c41fc65bcfb4 640 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 641 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 205:c41fc65bcfb4 642 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 643 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 205:c41fc65bcfb4 644 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 645 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 205:c41fc65bcfb4 646 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 647 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 205:c41fc65bcfb4 648 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 649 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
mbed_official 205:c41fc65bcfb4 650 __IO uint16_t RESERVEDD; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 651 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
mbed_official 205:c41fc65bcfb4 652 __IO uint16_t RESERVEDE; /*!< Reserved */
mbed_official 205:c41fc65bcfb4 653 }USB_TypeDef;
mbed_official 205:c41fc65bcfb4 654
mbed_official 205:c41fc65bcfb4 655 /**
mbed_official 205:c41fc65bcfb4 656 * @brief Window WATCHDOG
mbed_official 205:c41fc65bcfb4 657 */
mbed_official 205:c41fc65bcfb4 658 typedef struct
mbed_official 205:c41fc65bcfb4 659 {
mbed_official 205:c41fc65bcfb4 660 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 205:c41fc65bcfb4 661 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 205:c41fc65bcfb4 662 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 205:c41fc65bcfb4 663 }WWDG_TypeDef;
mbed_official 205:c41fc65bcfb4 664
mbed_official 205:c41fc65bcfb4 665 /**
mbed_official 205:c41fc65bcfb4 666 * @}
mbed_official 205:c41fc65bcfb4 667 */
mbed_official 205:c41fc65bcfb4 668
mbed_official 205:c41fc65bcfb4 669 /** @addtogroup Peripheral_memory_map
mbed_official 205:c41fc65bcfb4 670 * @{
mbed_official 205:c41fc65bcfb4 671 */
mbed_official 205:c41fc65bcfb4 672
mbed_official 205:c41fc65bcfb4 673 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 205:c41fc65bcfb4 674 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 205:c41fc65bcfb4 675 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 205:c41fc65bcfb4 676
mbed_official 205:c41fc65bcfb4 677 /*!< Peripheral memory map */
mbed_official 205:c41fc65bcfb4 678 #define APBPERIPH_BASE PERIPH_BASE
mbed_official 205:c41fc65bcfb4 679 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 205:c41fc65bcfb4 680 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 205:c41fc65bcfb4 681
mbed_official 205:c41fc65bcfb4 682 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official 205:c41fc65bcfb4 683 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official 205:c41fc65bcfb4 684 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
mbed_official 205:c41fc65bcfb4 685 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
mbed_official 205:c41fc65bcfb4 686 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official 205:c41fc65bcfb4 687 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official 205:c41fc65bcfb4 688 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official 205:c41fc65bcfb4 689 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official 205:c41fc65bcfb4 690 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official 205:c41fc65bcfb4 691 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official 205:c41fc65bcfb4 692 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
mbed_official 205:c41fc65bcfb4 693 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
mbed_official 205:c41fc65bcfb4 694 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official 205:c41fc65bcfb4 695 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
mbed_official 205:c41fc65bcfb4 696 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
mbed_official 205:c41fc65bcfb4 697 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
mbed_official 205:c41fc65bcfb4 698 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
mbed_official 205:c41fc65bcfb4 699 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
mbed_official 205:c41fc65bcfb4 700 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official 205:c41fc65bcfb4 701 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
mbed_official 205:c41fc65bcfb4 702 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
mbed_official 205:c41fc65bcfb4 703
mbed_official 205:c41fc65bcfb4 704 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official 205:c41fc65bcfb4 705 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official 205:c41fc65bcfb4 706 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official 205:c41fc65bcfb4 707 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official 205:c41fc65bcfb4 708 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official 205:c41fc65bcfb4 709 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official 205:c41fc65bcfb4 710 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official 205:c41fc65bcfb4 711 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official 205:c41fc65bcfb4 712 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
mbed_official 205:c41fc65bcfb4 713 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official 205:c41fc65bcfb4 714 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official 205:c41fc65bcfb4 715 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official 205:c41fc65bcfb4 716
mbed_official 205:c41fc65bcfb4 717 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 205:c41fc65bcfb4 718 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 205:c41fc65bcfb4 719 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 205:c41fc65bcfb4 720 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 205:c41fc65bcfb4 721 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 205:c41fc65bcfb4 722 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 205:c41fc65bcfb4 723 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official 205:c41fc65bcfb4 724 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official 205:c41fc65bcfb4 725
mbed_official 205:c41fc65bcfb4 726 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 205:c41fc65bcfb4 727 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
mbed_official 205:c41fc65bcfb4 728 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
mbed_official 205:c41fc65bcfb4 729 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 205:c41fc65bcfb4 730 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
mbed_official 205:c41fc65bcfb4 731
mbed_official 205:c41fc65bcfb4 732 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 205:c41fc65bcfb4 733 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 205:c41fc65bcfb4 734 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 205:c41fc65bcfb4 735 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 205:c41fc65bcfb4 736 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
mbed_official 205:c41fc65bcfb4 737 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 205:c41fc65bcfb4 738
mbed_official 205:c41fc65bcfb4 739 /**
mbed_official 205:c41fc65bcfb4 740 * @}
mbed_official 205:c41fc65bcfb4 741 */
mbed_official 205:c41fc65bcfb4 742
mbed_official 205:c41fc65bcfb4 743 /** @addtogroup Peripheral_declaration
mbed_official 205:c41fc65bcfb4 744 * @{
mbed_official 205:c41fc65bcfb4 745 */
mbed_official 205:c41fc65bcfb4 746
mbed_official 205:c41fc65bcfb4 747 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 205:c41fc65bcfb4 748 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 205:c41fc65bcfb4 749 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 205:c41fc65bcfb4 750 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 205:c41fc65bcfb4 751 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 205:c41fc65bcfb4 752 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 205:c41fc65bcfb4 753 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 205:c41fc65bcfb4 754 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 205:c41fc65bcfb4 755 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 205:c41fc65bcfb4 756 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 205:c41fc65bcfb4 757 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 205:c41fc65bcfb4 758 #define USART4 ((USART_TypeDef *) USART4_BASE)
mbed_official 205:c41fc65bcfb4 759 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 205:c41fc65bcfb4 760 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 205:c41fc65bcfb4 761 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 205:c41fc65bcfb4 762 #define CRS ((CRS_TypeDef *) CRS_BASE)
mbed_official 205:c41fc65bcfb4 763 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 205:c41fc65bcfb4 764 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 205:c41fc65bcfb4 765 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 205:c41fc65bcfb4 766 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 205:c41fc65bcfb4 767 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 205:c41fc65bcfb4 768 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
mbed_official 205:c41fc65bcfb4 769 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000004))
mbed_official 205:c41fc65bcfb4 770 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 205:c41fc65bcfb4 771 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 205:c41fc65bcfb4 772 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 205:c41fc65bcfb4 773 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 205:c41fc65bcfb4 774 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 205:c41fc65bcfb4 775 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 205:c41fc65bcfb4 776 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 205:c41fc65bcfb4 777 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 205:c41fc65bcfb4 778 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 205:c41fc65bcfb4 779 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 205:c41fc65bcfb4 780 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 205:c41fc65bcfb4 781 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 205:c41fc65bcfb4 782 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 205:c41fc65bcfb4 783 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 205:c41fc65bcfb4 784 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 205:c41fc65bcfb4 785 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 205:c41fc65bcfb4 786 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 205:c41fc65bcfb4 787 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 205:c41fc65bcfb4 788 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 205:c41fc65bcfb4 789 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 205:c41fc65bcfb4 790 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 205:c41fc65bcfb4 791 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 205:c41fc65bcfb4 792 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 205:c41fc65bcfb4 793 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 205:c41fc65bcfb4 794 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 205:c41fc65bcfb4 795 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 205:c41fc65bcfb4 796 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 205:c41fc65bcfb4 797 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 205:c41fc65bcfb4 798 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 205:c41fc65bcfb4 799 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 205:c41fc65bcfb4 800 /**
mbed_official 205:c41fc65bcfb4 801 * @}
mbed_official 205:c41fc65bcfb4 802 */
mbed_official 205:c41fc65bcfb4 803
mbed_official 205:c41fc65bcfb4 804 /** @addtogroup Exported_constants
mbed_official 205:c41fc65bcfb4 805 * @{
mbed_official 205:c41fc65bcfb4 806 */
mbed_official 205:c41fc65bcfb4 807
mbed_official 205:c41fc65bcfb4 808 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 205:c41fc65bcfb4 809 * @{
mbed_official 205:c41fc65bcfb4 810 */
mbed_official 205:c41fc65bcfb4 811
mbed_official 205:c41fc65bcfb4 812 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 813 /* Peripheral Registers Bits Definition */
mbed_official 205:c41fc65bcfb4 814 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 815 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 816 /* */
mbed_official 205:c41fc65bcfb4 817 /* Analog to Digital Converter (ADC) */
mbed_official 205:c41fc65bcfb4 818 /* */
mbed_official 205:c41fc65bcfb4 819 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 820 /******************** Bits definition for ADC_ISR register ******************/
mbed_official 205:c41fc65bcfb4 821 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
mbed_official 205:c41fc65bcfb4 822 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
mbed_official 205:c41fc65bcfb4 823 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
mbed_official 205:c41fc65bcfb4 824 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
mbed_official 205:c41fc65bcfb4 825 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
mbed_official 205:c41fc65bcfb4 826 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
mbed_official 205:c41fc65bcfb4 827
mbed_official 205:c41fc65bcfb4 828 /* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 829 #define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official 205:c41fc65bcfb4 830
mbed_official 205:c41fc65bcfb4 831 /******************** Bits definition for ADC_IER register ******************/
mbed_official 205:c41fc65bcfb4 832 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
mbed_official 205:c41fc65bcfb4 833 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
mbed_official 205:c41fc65bcfb4 834 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
mbed_official 205:c41fc65bcfb4 835 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
mbed_official 205:c41fc65bcfb4 836 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
mbed_official 205:c41fc65bcfb4 837 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
mbed_official 205:c41fc65bcfb4 838
mbed_official 205:c41fc65bcfb4 839 /* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 840 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official 205:c41fc65bcfb4 841
mbed_official 205:c41fc65bcfb4 842 /******************** Bits definition for ADC_CR register *******************/
mbed_official 205:c41fc65bcfb4 843 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
mbed_official 205:c41fc65bcfb4 844 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
mbed_official 205:c41fc65bcfb4 845 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
mbed_official 205:c41fc65bcfb4 846 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
mbed_official 205:c41fc65bcfb4 847 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
mbed_official 205:c41fc65bcfb4 848
mbed_official 205:c41fc65bcfb4 849 /******************* Bits definition for ADC_CFGR1 register *****************/
mbed_official 205:c41fc65bcfb4 850 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 205:c41fc65bcfb4 851 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 852 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 853 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 854 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 855 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 205:c41fc65bcfb4 856 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 205:c41fc65bcfb4 857 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
mbed_official 205:c41fc65bcfb4 858 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
mbed_official 205:c41fc65bcfb4 859 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
mbed_official 205:c41fc65bcfb4 860 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
mbed_official 205:c41fc65bcfb4 861 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
mbed_official 205:c41fc65bcfb4 862 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
mbed_official 205:c41fc65bcfb4 863 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 205:c41fc65bcfb4 864 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 865 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 866 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 205:c41fc65bcfb4 867 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 868 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 869 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 870 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
mbed_official 205:c41fc65bcfb4 871 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
mbed_official 205:c41fc65bcfb4 872 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 873 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 874 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
mbed_official 205:c41fc65bcfb4 875 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
mbed_official 205:c41fc65bcfb4 876 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
mbed_official 205:c41fc65bcfb4 877
mbed_official 205:c41fc65bcfb4 878 /* Old WAIT bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 879 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official 205:c41fc65bcfb4 880
mbed_official 205:c41fc65bcfb4 881 /******************* Bits definition for ADC_CFGR2 register *****************/
mbed_official 205:c41fc65bcfb4 882 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
mbed_official 205:c41fc65bcfb4 883 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
mbed_official 205:c41fc65bcfb4 884 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
mbed_official 205:c41fc65bcfb4 885
mbed_official 205:c41fc65bcfb4 886 /* Old bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 887 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
mbed_official 205:c41fc65bcfb4 888 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
mbed_official 205:c41fc65bcfb4 889
mbed_official 205:c41fc65bcfb4 890 /****************** Bit definition for ADC_SMPR register ********************/
mbed_official 205:c41fc65bcfb4 891 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 205:c41fc65bcfb4 892 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 893 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 894 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 895
mbed_official 205:c41fc65bcfb4 896 /* Old bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 897 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 205:c41fc65bcfb4 898 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 899 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 900 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 901
mbed_official 205:c41fc65bcfb4 902 /******************* Bit definition for ADC_TR register ********************/
mbed_official 205:c41fc65bcfb4 903 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
mbed_official 205:c41fc65bcfb4 904 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 205:c41fc65bcfb4 905
mbed_official 205:c41fc65bcfb4 906 /* Old bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 907 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
mbed_official 205:c41fc65bcfb4 908 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
mbed_official 205:c41fc65bcfb4 909
mbed_official 205:c41fc65bcfb4 910 /****************** Bit definition for ADC_CHSELR register ******************/
mbed_official 205:c41fc65bcfb4 911 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
mbed_official 205:c41fc65bcfb4 912 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
mbed_official 205:c41fc65bcfb4 913 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
mbed_official 205:c41fc65bcfb4 914 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
mbed_official 205:c41fc65bcfb4 915 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
mbed_official 205:c41fc65bcfb4 916 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
mbed_official 205:c41fc65bcfb4 917 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
mbed_official 205:c41fc65bcfb4 918 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
mbed_official 205:c41fc65bcfb4 919 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
mbed_official 205:c41fc65bcfb4 920 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
mbed_official 205:c41fc65bcfb4 921 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
mbed_official 205:c41fc65bcfb4 922 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
mbed_official 205:c41fc65bcfb4 923 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
mbed_official 205:c41fc65bcfb4 924 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
mbed_official 205:c41fc65bcfb4 925 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
mbed_official 205:c41fc65bcfb4 926 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
mbed_official 205:c41fc65bcfb4 927 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
mbed_official 205:c41fc65bcfb4 928 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
mbed_official 205:c41fc65bcfb4 929 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
mbed_official 205:c41fc65bcfb4 930
mbed_official 205:c41fc65bcfb4 931 /******************** Bit definition for ADC_DR register ********************/
mbed_official 205:c41fc65bcfb4 932 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 205:c41fc65bcfb4 933
mbed_official 205:c41fc65bcfb4 934 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 205:c41fc65bcfb4 935 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
mbed_official 205:c41fc65bcfb4 936 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
mbed_official 205:c41fc65bcfb4 937 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
mbed_official 205:c41fc65bcfb4 938
mbed_official 205:c41fc65bcfb4 939 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 940 /* */
mbed_official 205:c41fc65bcfb4 941 /* Controller Area Network (CAN ) */
mbed_official 205:c41fc65bcfb4 942 /* */
mbed_official 205:c41fc65bcfb4 943 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 944 /*!<CAN control and status registers */
mbed_official 205:c41fc65bcfb4 945 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 205:c41fc65bcfb4 946 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
mbed_official 205:c41fc65bcfb4 947 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
mbed_official 205:c41fc65bcfb4 948 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
mbed_official 205:c41fc65bcfb4 949 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
mbed_official 205:c41fc65bcfb4 950 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
mbed_official 205:c41fc65bcfb4 951 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
mbed_official 205:c41fc65bcfb4 952 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
mbed_official 205:c41fc65bcfb4 953 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
mbed_official 205:c41fc65bcfb4 954 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
mbed_official 205:c41fc65bcfb4 955
mbed_official 205:c41fc65bcfb4 956 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 205:c41fc65bcfb4 957 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 205:c41fc65bcfb4 958 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 205:c41fc65bcfb4 959 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
mbed_official 205:c41fc65bcfb4 960 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 205:c41fc65bcfb4 961 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 205:c41fc65bcfb4 962 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
mbed_official 205:c41fc65bcfb4 963 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
mbed_official 205:c41fc65bcfb4 964 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
mbed_official 205:c41fc65bcfb4 965 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
mbed_official 205:c41fc65bcfb4 966
mbed_official 205:c41fc65bcfb4 967 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 205:c41fc65bcfb4 968 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 205:c41fc65bcfb4 969 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 205:c41fc65bcfb4 970 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 205:c41fc65bcfb4 971 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 205:c41fc65bcfb4 972 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 205:c41fc65bcfb4 973 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 205:c41fc65bcfb4 974 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 205:c41fc65bcfb4 975 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 205:c41fc65bcfb4 976 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 205:c41fc65bcfb4 977 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 205:c41fc65bcfb4 978 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 205:c41fc65bcfb4 979 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 205:c41fc65bcfb4 980 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 205:c41fc65bcfb4 981 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 205:c41fc65bcfb4 982 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 205:c41fc65bcfb4 983 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 205:c41fc65bcfb4 984
mbed_official 205:c41fc65bcfb4 985 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 205:c41fc65bcfb4 986 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 205:c41fc65bcfb4 987 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 205:c41fc65bcfb4 988 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 205:c41fc65bcfb4 989
mbed_official 205:c41fc65bcfb4 990 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 205:c41fc65bcfb4 991 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 205:c41fc65bcfb4 992 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 205:c41fc65bcfb4 993 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 205:c41fc65bcfb4 994
mbed_official 205:c41fc65bcfb4 995 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 205:c41fc65bcfb4 996 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 205:c41fc65bcfb4 997 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
mbed_official 205:c41fc65bcfb4 998 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 205:c41fc65bcfb4 999 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 205:c41fc65bcfb4 1000
mbed_official 205:c41fc65bcfb4 1001 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 205:c41fc65bcfb4 1002 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 205:c41fc65bcfb4 1003 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
mbed_official 205:c41fc65bcfb4 1004 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 205:c41fc65bcfb4 1005 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 205:c41fc65bcfb4 1006
mbed_official 205:c41fc65bcfb4 1007 /******************** Bit definition for CAN_IER register *******************/
mbed_official 205:c41fc65bcfb4 1008 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1009 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1010 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1011 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1012 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1013 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1014 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1015 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1016 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1017 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1018 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1019 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1020 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1021 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 205:c41fc65bcfb4 1022
mbed_official 205:c41fc65bcfb4 1023 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 205:c41fc65bcfb4 1024 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 205:c41fc65bcfb4 1025 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 205:c41fc65bcfb4 1026 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 205:c41fc65bcfb4 1027
mbed_official 205:c41fc65bcfb4 1028 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 205:c41fc65bcfb4 1029 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 1030 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 1031 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 1032
mbed_official 205:c41fc65bcfb4 1033 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 205:c41fc65bcfb4 1034 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 205:c41fc65bcfb4 1035
mbed_official 205:c41fc65bcfb4 1036 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 205:c41fc65bcfb4 1037 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 205:c41fc65bcfb4 1038 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 205:c41fc65bcfb4 1039 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
mbed_official 205:c41fc65bcfb4 1040 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
mbed_official 205:c41fc65bcfb4 1041 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
mbed_official 205:c41fc65bcfb4 1042 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
mbed_official 205:c41fc65bcfb4 1043 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 205:c41fc65bcfb4 1044 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
mbed_official 205:c41fc65bcfb4 1045 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
mbed_official 205:c41fc65bcfb4 1046 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
mbed_official 205:c41fc65bcfb4 1047 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 205:c41fc65bcfb4 1048 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
mbed_official 205:c41fc65bcfb4 1049 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
mbed_official 205:c41fc65bcfb4 1050 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 205:c41fc65bcfb4 1051 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 205:c41fc65bcfb4 1052
mbed_official 205:c41fc65bcfb4 1053 /*!<Mailbox registers */
mbed_official 205:c41fc65bcfb4 1054 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 205:c41fc65bcfb4 1055 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 205:c41fc65bcfb4 1056 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 205:c41fc65bcfb4 1057 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 205:c41fc65bcfb4 1058 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 205:c41fc65bcfb4 1059 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 205:c41fc65bcfb4 1060
mbed_official 205:c41fc65bcfb4 1061 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 205:c41fc65bcfb4 1062 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 205:c41fc65bcfb4 1063 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 205:c41fc65bcfb4 1064 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 205:c41fc65bcfb4 1065
mbed_official 205:c41fc65bcfb4 1066 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 205:c41fc65bcfb4 1067 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 205:c41fc65bcfb4 1068 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 205:c41fc65bcfb4 1069 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 205:c41fc65bcfb4 1070 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 205:c41fc65bcfb4 1071
mbed_official 205:c41fc65bcfb4 1072 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 205:c41fc65bcfb4 1073 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 205:c41fc65bcfb4 1074 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 205:c41fc65bcfb4 1075 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 205:c41fc65bcfb4 1076 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 205:c41fc65bcfb4 1077
mbed_official 205:c41fc65bcfb4 1078 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 205:c41fc65bcfb4 1079 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 205:c41fc65bcfb4 1080 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 205:c41fc65bcfb4 1081 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 205:c41fc65bcfb4 1082 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 205:c41fc65bcfb4 1083 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 205:c41fc65bcfb4 1084
mbed_official 205:c41fc65bcfb4 1085 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 205:c41fc65bcfb4 1086 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 205:c41fc65bcfb4 1087 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 205:c41fc65bcfb4 1088 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 205:c41fc65bcfb4 1089
mbed_official 205:c41fc65bcfb4 1090 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 205:c41fc65bcfb4 1091 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 205:c41fc65bcfb4 1092 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 205:c41fc65bcfb4 1093 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 205:c41fc65bcfb4 1094 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 205:c41fc65bcfb4 1095
mbed_official 205:c41fc65bcfb4 1096 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 205:c41fc65bcfb4 1097 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 205:c41fc65bcfb4 1098 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 205:c41fc65bcfb4 1099 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 205:c41fc65bcfb4 1100 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 205:c41fc65bcfb4 1101
mbed_official 205:c41fc65bcfb4 1102 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 205:c41fc65bcfb4 1103 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 205:c41fc65bcfb4 1104 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 205:c41fc65bcfb4 1105 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 205:c41fc65bcfb4 1106 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 205:c41fc65bcfb4 1107 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 205:c41fc65bcfb4 1108
mbed_official 205:c41fc65bcfb4 1109 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 205:c41fc65bcfb4 1110 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 205:c41fc65bcfb4 1111 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 205:c41fc65bcfb4 1112 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 205:c41fc65bcfb4 1113
mbed_official 205:c41fc65bcfb4 1114 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 205:c41fc65bcfb4 1115 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 205:c41fc65bcfb4 1116 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 205:c41fc65bcfb4 1117 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 205:c41fc65bcfb4 1118 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 205:c41fc65bcfb4 1119
mbed_official 205:c41fc65bcfb4 1120 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 205:c41fc65bcfb4 1121 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 205:c41fc65bcfb4 1122 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 205:c41fc65bcfb4 1123 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 205:c41fc65bcfb4 1124 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 205:c41fc65bcfb4 1125
mbed_official 205:c41fc65bcfb4 1126 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 205:c41fc65bcfb4 1127 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 205:c41fc65bcfb4 1128 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 205:c41fc65bcfb4 1129 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 205:c41fc65bcfb4 1130 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 205:c41fc65bcfb4 1131
mbed_official 205:c41fc65bcfb4 1132 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 205:c41fc65bcfb4 1133 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 205:c41fc65bcfb4 1134 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 205:c41fc65bcfb4 1135 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 205:c41fc65bcfb4 1136
mbed_official 205:c41fc65bcfb4 1137 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 205:c41fc65bcfb4 1138 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 205:c41fc65bcfb4 1139 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 205:c41fc65bcfb4 1140 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 205:c41fc65bcfb4 1141 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 205:c41fc65bcfb4 1142
mbed_official 205:c41fc65bcfb4 1143 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 205:c41fc65bcfb4 1144 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 205:c41fc65bcfb4 1145 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 205:c41fc65bcfb4 1146 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 205:c41fc65bcfb4 1147 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 205:c41fc65bcfb4 1148
mbed_official 205:c41fc65bcfb4 1149 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 205:c41fc65bcfb4 1150 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 205:c41fc65bcfb4 1151 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 205:c41fc65bcfb4 1152 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 205:c41fc65bcfb4 1153 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 205:c41fc65bcfb4 1154
mbed_official 205:c41fc65bcfb4 1155 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 205:c41fc65bcfb4 1156 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 205:c41fc65bcfb4 1157 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 205:c41fc65bcfb4 1158 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 205:c41fc65bcfb4 1159
mbed_official 205:c41fc65bcfb4 1160 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 205:c41fc65bcfb4 1161 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 205:c41fc65bcfb4 1162 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 205:c41fc65bcfb4 1163 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 205:c41fc65bcfb4 1164 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 205:c41fc65bcfb4 1165
mbed_official 205:c41fc65bcfb4 1166 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 205:c41fc65bcfb4 1167 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 205:c41fc65bcfb4 1168 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 205:c41fc65bcfb4 1169 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 205:c41fc65bcfb4 1170 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 205:c41fc65bcfb4 1171
mbed_official 205:c41fc65bcfb4 1172 /*!<CAN filter registers */
mbed_official 205:c41fc65bcfb4 1173 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 205:c41fc65bcfb4 1174 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
mbed_official 205:c41fc65bcfb4 1175
mbed_official 205:c41fc65bcfb4 1176 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 205:c41fc65bcfb4 1177 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
mbed_official 205:c41fc65bcfb4 1178 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
mbed_official 205:c41fc65bcfb4 1179 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
mbed_official 205:c41fc65bcfb4 1180 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
mbed_official 205:c41fc65bcfb4 1181 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
mbed_official 205:c41fc65bcfb4 1182 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
mbed_official 205:c41fc65bcfb4 1183 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
mbed_official 205:c41fc65bcfb4 1184 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
mbed_official 205:c41fc65bcfb4 1185 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
mbed_official 205:c41fc65bcfb4 1186 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
mbed_official 205:c41fc65bcfb4 1187 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
mbed_official 205:c41fc65bcfb4 1188 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
mbed_official 205:c41fc65bcfb4 1189 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
mbed_official 205:c41fc65bcfb4 1190 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
mbed_official 205:c41fc65bcfb4 1191 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
mbed_official 205:c41fc65bcfb4 1192
mbed_official 205:c41fc65bcfb4 1193 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 205:c41fc65bcfb4 1194 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
mbed_official 205:c41fc65bcfb4 1195 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
mbed_official 205:c41fc65bcfb4 1196 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
mbed_official 205:c41fc65bcfb4 1197 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
mbed_official 205:c41fc65bcfb4 1198 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
mbed_official 205:c41fc65bcfb4 1199 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
mbed_official 205:c41fc65bcfb4 1200 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
mbed_official 205:c41fc65bcfb4 1201 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
mbed_official 205:c41fc65bcfb4 1202 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
mbed_official 205:c41fc65bcfb4 1203 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
mbed_official 205:c41fc65bcfb4 1204 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
mbed_official 205:c41fc65bcfb4 1205 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
mbed_official 205:c41fc65bcfb4 1206 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
mbed_official 205:c41fc65bcfb4 1207 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
mbed_official 205:c41fc65bcfb4 1208 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
mbed_official 205:c41fc65bcfb4 1209
mbed_official 205:c41fc65bcfb4 1210 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 205:c41fc65bcfb4 1211 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
mbed_official 205:c41fc65bcfb4 1212 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 205:c41fc65bcfb4 1213 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 205:c41fc65bcfb4 1214 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 205:c41fc65bcfb4 1215 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 205:c41fc65bcfb4 1216 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 205:c41fc65bcfb4 1217 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 205:c41fc65bcfb4 1218 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 205:c41fc65bcfb4 1219 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 205:c41fc65bcfb4 1220 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 205:c41fc65bcfb4 1221 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 205:c41fc65bcfb4 1222 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 205:c41fc65bcfb4 1223 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 205:c41fc65bcfb4 1224 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 205:c41fc65bcfb4 1225 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 205:c41fc65bcfb4 1226
mbed_official 205:c41fc65bcfb4 1227 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 205:c41fc65bcfb4 1228 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
mbed_official 205:c41fc65bcfb4 1229 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
mbed_official 205:c41fc65bcfb4 1230 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
mbed_official 205:c41fc65bcfb4 1231 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
mbed_official 205:c41fc65bcfb4 1232 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
mbed_official 205:c41fc65bcfb4 1233 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
mbed_official 205:c41fc65bcfb4 1234 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
mbed_official 205:c41fc65bcfb4 1235 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
mbed_official 205:c41fc65bcfb4 1236 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
mbed_official 205:c41fc65bcfb4 1237 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
mbed_official 205:c41fc65bcfb4 1238 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
mbed_official 205:c41fc65bcfb4 1239 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
mbed_official 205:c41fc65bcfb4 1240 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
mbed_official 205:c41fc65bcfb4 1241 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
mbed_official 205:c41fc65bcfb4 1242 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
mbed_official 205:c41fc65bcfb4 1243
mbed_official 205:c41fc65bcfb4 1244 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 205:c41fc65bcfb4 1245 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1246 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1247 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1248 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1249 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1250 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1251 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1252 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1253 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1254 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1255 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1256 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1257 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1258 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1259 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1260 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1261 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1262 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1263 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1264 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1265 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1266 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1267 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1268 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1269 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1270 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1271 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1272 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1273 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1274 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1275 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1276 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1277
mbed_official 205:c41fc65bcfb4 1278 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 205:c41fc65bcfb4 1279 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1280 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1281 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1282 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1283 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1284 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1285 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1286 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1287 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1288 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1289 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1290 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1291 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1292 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1293 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1294 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1295 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1296 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1297 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1298 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1299 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1300 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1301 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1302 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1303 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1304 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1305 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1306 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1307 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1308 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1309 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1310 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1311
mbed_official 205:c41fc65bcfb4 1312 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 205:c41fc65bcfb4 1313 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1314 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1315 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1316 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1317 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1318 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1319 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1320 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1321 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1322 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1323 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1324 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1325 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1326 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1327 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1328 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1329 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1330 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1331 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1332 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1333 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1334 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1335 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1336 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1337 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1338 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1339 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1340 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1341 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1342 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1343 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1344 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1345
mbed_official 205:c41fc65bcfb4 1346 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 205:c41fc65bcfb4 1347 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1348 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1349 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1350 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1351 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1352 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1353 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1354 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1355 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1356 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1357 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1358 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1359 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1360 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1361 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1362 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1363 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1364 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1365 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1366 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1367 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1368 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1369 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1370 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1371 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1372 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1373 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1374 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1375 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1376 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1377 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1378 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1379
mbed_official 205:c41fc65bcfb4 1380 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 205:c41fc65bcfb4 1381 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1382 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1383 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1384 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1385 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1386 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1387 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1388 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1389 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1390 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1391 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1392 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1393 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1394 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1395 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1396 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1397 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1398 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1399 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1400 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1401 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1402 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1403 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1404 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1405 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1406 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1407 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1408 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1409 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1410 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1411 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1412 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1413
mbed_official 205:c41fc65bcfb4 1414 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 205:c41fc65bcfb4 1415 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1416 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1417 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1418 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1419 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1420 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1421 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1422 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1423 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1424 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1425 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1426 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1427 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1428 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1429 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1430 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1431 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1432 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1433 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1434 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1435 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1436 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1437 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1438 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1439 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1440 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1441 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1442 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1443 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1444 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1445 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1446 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1447
mbed_official 205:c41fc65bcfb4 1448 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 205:c41fc65bcfb4 1449 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1450 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1451 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1452 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1453 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1454 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1455 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1456 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1457 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1458 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1459 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1460 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1461 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1462 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1463 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1464 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1465 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1466 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1467 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1468 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1469 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1470 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1471 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1472 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1473 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1474 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1475 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1476 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1477 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1478 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1479 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1480 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1481
mbed_official 205:c41fc65bcfb4 1482 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 205:c41fc65bcfb4 1483 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1484 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1485 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1486 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1487 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1488 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1489 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1490 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1491 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1492 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1493 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1494 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1495 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1496 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1497 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1498 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1499 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1500 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1501 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1502 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1503 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1504 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1505 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1506 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1507 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1508 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1509 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1510 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1511 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1512 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1513 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1514 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1515
mbed_official 205:c41fc65bcfb4 1516 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 205:c41fc65bcfb4 1517 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1518 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1519 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1520 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1521 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1522 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1523 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1524 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1525 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1526 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1527 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1528 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1529 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1530 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1531 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1532 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1533 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1534 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1535 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1536 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1537 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1538 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1539 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1540 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1541 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1542 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1543 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1544 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1545 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1546 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1547 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1548 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1549
mbed_official 205:c41fc65bcfb4 1550 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 205:c41fc65bcfb4 1551 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1552 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1553 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1554 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1555 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1556 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1557 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1558 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1559 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1560 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1561 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1562 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1563 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1564 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1565 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1566 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1567 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1568 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1569 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1570 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1571 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1572 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1573 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1574 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1575 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1576 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1577 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1578 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1579 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1580 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1581 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1582 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1583
mbed_official 205:c41fc65bcfb4 1584 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 205:c41fc65bcfb4 1585 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1586 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1587 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1588 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1589 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1590 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1591 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1592 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1593 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1594 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1595 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1596 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1597 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1598 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1599 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1600 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1601 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1602 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1603 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1604 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1605 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1606 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1607 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1608 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1609 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1610 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1611 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1612 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1613 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1614 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1615 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1616 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1617
mbed_official 205:c41fc65bcfb4 1618 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 205:c41fc65bcfb4 1619 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1620 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1621 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1622 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1623 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1624 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1625 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1626 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1627 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1628 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1629 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1630 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1631 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1632 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1633 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1634 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1635 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1636 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1637 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1638 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1639 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1640 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1641 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1642 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1643 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1644 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1645 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1646 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1647 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1648 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1649 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1650 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1651
mbed_official 205:c41fc65bcfb4 1652 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 205:c41fc65bcfb4 1653 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1654 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1655 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1656 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1657 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1658 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1659 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1660 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1661 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1662 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1663 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1664 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1665 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1666 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1667 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1668 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1669 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1670 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1671 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1672 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1673 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1674 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1675 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1676 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1677 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1678 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1679 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1680 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1681 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1682 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1683 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1684 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1685
mbed_official 205:c41fc65bcfb4 1686 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 205:c41fc65bcfb4 1687 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1688 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1689 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1690 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1691 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1692 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1693 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1694 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1695 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1696 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1697 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1698 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1699 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1700 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1701 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1702 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1703 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1704 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1705 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1706 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1707 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1708 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1709 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1710 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1711 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1712 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1713 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1714 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1715 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1716 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1717 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1718 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1719
mbed_official 205:c41fc65bcfb4 1720 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 205:c41fc65bcfb4 1721 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1722 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1723 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1724 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1725 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1726 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1727 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1728 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1729 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1730 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1731 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1732 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1733 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1734 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1735 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1736 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1737 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1738 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1739 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1740 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1741 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1742 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1743 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1744 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1745 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1746 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1747 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1748 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1749 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1750 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1751 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1752 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1753
mbed_official 205:c41fc65bcfb4 1754 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 205:c41fc65bcfb4 1755 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1756 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1757 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1758 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1759 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1760 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1761 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1762 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1763 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1764 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1765 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1766 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1767 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1768 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1769 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1770 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1771 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1772 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1773 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1774 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1775 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1776 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1777 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1778 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1779 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1780 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1781 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1782 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1783 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1784 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1785 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1786 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1787
mbed_official 205:c41fc65bcfb4 1788 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 205:c41fc65bcfb4 1789 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1790 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1791 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1792 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1793 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1794 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1795 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1796 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1797 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1798 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1799 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1800 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1801 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1802 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1803 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1804 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1805 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1806 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1807 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1808 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1809 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1810 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1811 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1812 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1813 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1814 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1815 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1816 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1817 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1818 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1819 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1820 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1821
mbed_official 205:c41fc65bcfb4 1822 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 205:c41fc65bcfb4 1823 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1824 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1825 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1826 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1827 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1828 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1829 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1830 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1831 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1832 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1833 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1834 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1835 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1836 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1837 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1838 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1839 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1840 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1841 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1842 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1843 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1844 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1845 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1846 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1847 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1848 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1849 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1850 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1851 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1852 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1853 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1854 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1855
mbed_official 205:c41fc65bcfb4 1856 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 205:c41fc65bcfb4 1857 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1858 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1859 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1860 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1861 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1862 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1863 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1864 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1865 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1866 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1867 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1868 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1869 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1870 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1871 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1872 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1873 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1874 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1875 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1876 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1877 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1878 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1879 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1880 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1881 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1882 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1883 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1884 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1885 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1886 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1887 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1888 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1889
mbed_official 205:c41fc65bcfb4 1890 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 205:c41fc65bcfb4 1891 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1892 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1893 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1894 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1895 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1896 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1897 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1898 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1899 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1900 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1901 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1902 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1903 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1904 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1905 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1906 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1907 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1908 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1909 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1910 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1911 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1912 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1913 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1914 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1915 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1916 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1917 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1918 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1919 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1920 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1921 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1922 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1923
mbed_official 205:c41fc65bcfb4 1924 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 205:c41fc65bcfb4 1925 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1926 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1927 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1928 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1929 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1930 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1931 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1932 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1933 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1934 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1935 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1936 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1937 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1938 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1939 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1940 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1941 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1942 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1943 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1944 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1945 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1946 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1947 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1948 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1949 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1950 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1951 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1952 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1953 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1954 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1955 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1956 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1957
mbed_official 205:c41fc65bcfb4 1958 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 205:c41fc65bcfb4 1959 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1960 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1961 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1962 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1963 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1964 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1965 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 1966 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 1967 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 1968 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 1969 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 1970 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 1971 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 1972 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 1973 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 1974 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 1975 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 1976 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 1977 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 1978 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 1979 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 1980 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 1981 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 1982 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 1983 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 1984 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 1985 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 1986 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 1987 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 1988 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 1989 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 1990 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 1991
mbed_official 205:c41fc65bcfb4 1992 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 205:c41fc65bcfb4 1993 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 1994 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 1995 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 1996 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 1997 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 1998 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 1999 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 2000 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 2001 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 2002 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 2003 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 2004 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 2005 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 2006 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 2007 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 2008 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 2009 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 2010 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 2011 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 2012 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 2013 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 2014 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 2015 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 2016 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 2017 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 2018 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 2019 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 2020 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 2021 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 2022 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 2023 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 2024 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 2025
mbed_official 205:c41fc65bcfb4 2026 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 205:c41fc65bcfb4 2027 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 2028 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 2029 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 2030 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 2031 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 2032 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 2033 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 2034 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 2035 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 2036 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 2037 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 2038 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 2039 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 2040 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 2041 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 2042 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 2043 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 2044 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 2045 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 2046 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 2047 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 2048 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 2049 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 2050 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 2051 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 2052 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 2053 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 2054 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 2055 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 2056 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 2057 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 2058 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 2059
mbed_official 205:c41fc65bcfb4 2060 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 205:c41fc65bcfb4 2061 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 2062 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 2063 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 2064 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 2065 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 2066 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 2067 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 2068 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 2069 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 2070 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 2071 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 2072 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 2073 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 2074 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 2075 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 2076 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 2077 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 2078 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 2079 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 2080 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 2081 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 2082 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 2083 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 2084 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 2085 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 2086 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 2087 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 2088 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 2089 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 2090 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 2091 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 2092 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 2093
mbed_official 205:c41fc65bcfb4 2094 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 205:c41fc65bcfb4 2095 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 2096 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 2097 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 2098 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 2099 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 2100 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 2101 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 2102 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 2103 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 2104 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 2105 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 2106 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 2107 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 2108 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 2109 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 2110 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 2111 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 2112 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 2113 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 2114 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 2115 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 2116 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 2117 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 2118 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 2119 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 2120 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 2121 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 2122 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 2123 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 2124 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 2125 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 2126 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 2127
mbed_official 205:c41fc65bcfb4 2128 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 205:c41fc65bcfb4 2129 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 2130 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 2131 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 2132 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 2133 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 2134 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 2135 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 2136 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 2137 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 2138 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 2139 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 2140 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 2141 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 2142 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 2143 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 2144 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 2145 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 2146 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 2147 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 2148 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 2149 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 2150 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 2151 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 2152 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 2153 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 2154 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 2155 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 2156 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 2157 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 2158 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 2159 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 2160 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 2161
mbed_official 205:c41fc65bcfb4 2162 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 205:c41fc65bcfb4 2163 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 205:c41fc65bcfb4 2164 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 205:c41fc65bcfb4 2165 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 205:c41fc65bcfb4 2166 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 205:c41fc65bcfb4 2167 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 205:c41fc65bcfb4 2168 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 205:c41fc65bcfb4 2169 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 205:c41fc65bcfb4 2170 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 205:c41fc65bcfb4 2171 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 205:c41fc65bcfb4 2172 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 205:c41fc65bcfb4 2173 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 205:c41fc65bcfb4 2174 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 205:c41fc65bcfb4 2175 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 205:c41fc65bcfb4 2176 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 205:c41fc65bcfb4 2177 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 205:c41fc65bcfb4 2178 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 205:c41fc65bcfb4 2179 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 205:c41fc65bcfb4 2180 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 205:c41fc65bcfb4 2181 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 205:c41fc65bcfb4 2182 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 205:c41fc65bcfb4 2183 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 205:c41fc65bcfb4 2184 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 205:c41fc65bcfb4 2185 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 205:c41fc65bcfb4 2186 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 205:c41fc65bcfb4 2187 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 205:c41fc65bcfb4 2188 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 205:c41fc65bcfb4 2189 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 205:c41fc65bcfb4 2190 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 205:c41fc65bcfb4 2191 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 205:c41fc65bcfb4 2192 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 205:c41fc65bcfb4 2193 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 205:c41fc65bcfb4 2194 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 205:c41fc65bcfb4 2195
mbed_official 205:c41fc65bcfb4 2196 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2197 /* */
mbed_official 205:c41fc65bcfb4 2198 /* HDMI-CEC (CEC) */
mbed_official 205:c41fc65bcfb4 2199 /* */
mbed_official 205:c41fc65bcfb4 2200 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2201
mbed_official 205:c41fc65bcfb4 2202 /******************* Bit definition for CEC_CR register *********************/
mbed_official 205:c41fc65bcfb4 2203 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
mbed_official 205:c41fc65bcfb4 2204 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
mbed_official 205:c41fc65bcfb4 2205 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
mbed_official 205:c41fc65bcfb4 2206
mbed_official 205:c41fc65bcfb4 2207 /******************* Bit definition for CEC_CFGR register *******************/
mbed_official 205:c41fc65bcfb4 2208 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
mbed_official 205:c41fc65bcfb4 2209 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
mbed_official 205:c41fc65bcfb4 2210 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
mbed_official 205:c41fc65bcfb4 2211 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
mbed_official 205:c41fc65bcfb4 2212 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
mbed_official 205:c41fc65bcfb4 2213 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
mbed_official 205:c41fc65bcfb4 2214 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
mbed_official 205:c41fc65bcfb4 2215 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
mbed_official 205:c41fc65bcfb4 2216 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
mbed_official 205:c41fc65bcfb4 2217
mbed_official 205:c41fc65bcfb4 2218 /******************* Bit definition for CEC_TXDR register *******************/
mbed_official 205:c41fc65bcfb4 2219 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
mbed_official 205:c41fc65bcfb4 2220
mbed_official 205:c41fc65bcfb4 2221 /******************* Bit definition for CEC_RXDR register *******************/
mbed_official 205:c41fc65bcfb4 2222 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
mbed_official 205:c41fc65bcfb4 2223
mbed_official 205:c41fc65bcfb4 2224 /******************* Bit definition for CEC_ISR register ********************/
mbed_official 205:c41fc65bcfb4 2225 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
mbed_official 205:c41fc65bcfb4 2226 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
mbed_official 205:c41fc65bcfb4 2227 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
mbed_official 205:c41fc65bcfb4 2228 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
mbed_official 205:c41fc65bcfb4 2229 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
mbed_official 205:c41fc65bcfb4 2230 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
mbed_official 205:c41fc65bcfb4 2231 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
mbed_official 205:c41fc65bcfb4 2232 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
mbed_official 205:c41fc65bcfb4 2233 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
mbed_official 205:c41fc65bcfb4 2234 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
mbed_official 205:c41fc65bcfb4 2235 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
mbed_official 205:c41fc65bcfb4 2236 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
mbed_official 205:c41fc65bcfb4 2237 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
mbed_official 205:c41fc65bcfb4 2238
mbed_official 205:c41fc65bcfb4 2239 /******************* Bit definition for CEC_IER register ********************/
mbed_official 205:c41fc65bcfb4 2240 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
mbed_official 205:c41fc65bcfb4 2241 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
mbed_official 205:c41fc65bcfb4 2242 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
mbed_official 205:c41fc65bcfb4 2243 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
mbed_official 205:c41fc65bcfb4 2244 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
mbed_official 205:c41fc65bcfb4 2245 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
mbed_official 205:c41fc65bcfb4 2246 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
mbed_official 205:c41fc65bcfb4 2247 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
mbed_official 205:c41fc65bcfb4 2248 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
mbed_official 205:c41fc65bcfb4 2249 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
mbed_official 205:c41fc65bcfb4 2250 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
mbed_official 205:c41fc65bcfb4 2251 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
mbed_official 205:c41fc65bcfb4 2252 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 205:c41fc65bcfb4 2253
mbed_official 205:c41fc65bcfb4 2254
mbed_official 205:c41fc65bcfb4 2255 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2256 /* */
mbed_official 205:c41fc65bcfb4 2257 /* Analog Comparators (COMP) */
mbed_official 205:c41fc65bcfb4 2258 /* */
mbed_official 205:c41fc65bcfb4 2259 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2260 /*********************** Bit definition for COMP_CSR register ***************/
mbed_official 205:c41fc65bcfb4 2261 /* COMP1 bits definition */
mbed_official 205:c41fc65bcfb4 2262 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 205:c41fc65bcfb4 2263 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
mbed_official 205:c41fc65bcfb4 2264 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
mbed_official 205:c41fc65bcfb4 2265 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
mbed_official 205:c41fc65bcfb4 2266 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
mbed_official 205:c41fc65bcfb4 2267 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 205:c41fc65bcfb4 2268 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 205:c41fc65bcfb4 2269 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 205:c41fc65bcfb4 2270 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 205:c41fc65bcfb4 2271 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
mbed_official 205:c41fc65bcfb4 2272 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
mbed_official 205:c41fc65bcfb4 2273 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
mbed_official 205:c41fc65bcfb4 2274 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
mbed_official 205:c41fc65bcfb4 2275 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
mbed_official 205:c41fc65bcfb4 2276 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
mbed_official 205:c41fc65bcfb4 2277 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
mbed_official 205:c41fc65bcfb4 2278 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
mbed_official 205:c41fc65bcfb4 2279 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
mbed_official 205:c41fc65bcfb4 2280 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
mbed_official 205:c41fc65bcfb4 2281 /* COMP2 bits definition */
mbed_official 205:c41fc65bcfb4 2282 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
mbed_official 205:c41fc65bcfb4 2283 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
mbed_official 205:c41fc65bcfb4 2284 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
mbed_official 205:c41fc65bcfb4 2285 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
mbed_official 205:c41fc65bcfb4 2286 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
mbed_official 205:c41fc65bcfb4 2287 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
mbed_official 205:c41fc65bcfb4 2288 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
mbed_official 205:c41fc65bcfb4 2289 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
mbed_official 205:c41fc65bcfb4 2290 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
mbed_official 205:c41fc65bcfb4 2291 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
mbed_official 205:c41fc65bcfb4 2292 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
mbed_official 205:c41fc65bcfb4 2293 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
mbed_official 205:c41fc65bcfb4 2294 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
mbed_official 205:c41fc65bcfb4 2295 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
mbed_official 205:c41fc65bcfb4 2296 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
mbed_official 205:c41fc65bcfb4 2297 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
mbed_official 205:c41fc65bcfb4 2298 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
mbed_official 205:c41fc65bcfb4 2299 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 205:c41fc65bcfb4 2300 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 205:c41fc65bcfb4 2301 /* COMPx bits definition */
mbed_official 205:c41fc65bcfb4 2302 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
mbed_official 205:c41fc65bcfb4 2303 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
mbed_official 205:c41fc65bcfb4 2304 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
mbed_official 205:c41fc65bcfb4 2305 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
mbed_official 205:c41fc65bcfb4 2306 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
mbed_official 205:c41fc65bcfb4 2307 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
mbed_official 205:c41fc65bcfb4 2308 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
mbed_official 205:c41fc65bcfb4 2309 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
mbed_official 205:c41fc65bcfb4 2310 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
mbed_official 205:c41fc65bcfb4 2311 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
mbed_official 205:c41fc65bcfb4 2312 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
mbed_official 205:c41fc65bcfb4 2313 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
mbed_official 205:c41fc65bcfb4 2314 #define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
mbed_official 205:c41fc65bcfb4 2315 #define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
mbed_official 205:c41fc65bcfb4 2316 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
mbed_official 205:c41fc65bcfb4 2317 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
mbed_official 205:c41fc65bcfb4 2318 #define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
mbed_official 205:c41fc65bcfb4 2319 #define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
mbed_official 205:c41fc65bcfb4 2320
mbed_official 205:c41fc65bcfb4 2321 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2322 /* */
mbed_official 205:c41fc65bcfb4 2323 /* CRC calculation unit (CRC) */
mbed_official 205:c41fc65bcfb4 2324 /* */
mbed_official 205:c41fc65bcfb4 2325 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2326 /******************* Bit definition for CRC_DR register *********************/
mbed_official 205:c41fc65bcfb4 2327 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 205:c41fc65bcfb4 2328
mbed_official 205:c41fc65bcfb4 2329 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 205:c41fc65bcfb4 2330 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 205:c41fc65bcfb4 2331
mbed_official 205:c41fc65bcfb4 2332 /******************** Bit definition for CRC_CR register ********************/
mbed_official 205:c41fc65bcfb4 2333 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 205:c41fc65bcfb4 2334 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 205:c41fc65bcfb4 2335 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 205:c41fc65bcfb4 2336 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 205:c41fc65bcfb4 2337 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 205:c41fc65bcfb4 2338 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
mbed_official 205:c41fc65bcfb4 2339 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
mbed_official 205:c41fc65bcfb4 2340 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 205:c41fc65bcfb4 2341
mbed_official 205:c41fc65bcfb4 2342 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 205:c41fc65bcfb4 2343 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 205:c41fc65bcfb4 2344
mbed_official 205:c41fc65bcfb4 2345 /******************* Bit definition for CRC_POL register ********************/
mbed_official 205:c41fc65bcfb4 2346 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 205:c41fc65bcfb4 2347
mbed_official 205:c41fc65bcfb4 2348 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2349 /* */
mbed_official 205:c41fc65bcfb4 2350 /* CRS Clock Recovery System */
mbed_official 205:c41fc65bcfb4 2351 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2352
mbed_official 205:c41fc65bcfb4 2353 /******************* Bit definition for CRS_CR register *********************/
mbed_official 205:c41fc65bcfb4 2354 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
mbed_official 205:c41fc65bcfb4 2355 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
mbed_official 205:c41fc65bcfb4 2356 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
mbed_official 205:c41fc65bcfb4 2357 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
mbed_official 205:c41fc65bcfb4 2358 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
mbed_official 205:c41fc65bcfb4 2359 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
mbed_official 205:c41fc65bcfb4 2360 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
mbed_official 205:c41fc65bcfb4 2361 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
mbed_official 205:c41fc65bcfb4 2362
mbed_official 205:c41fc65bcfb4 2363 /******************* Bit definition for CRS_CFGR register *********************/
mbed_official 205:c41fc65bcfb4 2364 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
mbed_official 205:c41fc65bcfb4 2365 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
mbed_official 205:c41fc65bcfb4 2366
mbed_official 205:c41fc65bcfb4 2367 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
mbed_official 205:c41fc65bcfb4 2368 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
mbed_official 205:c41fc65bcfb4 2369 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
mbed_official 205:c41fc65bcfb4 2370 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
mbed_official 205:c41fc65bcfb4 2371
mbed_official 205:c41fc65bcfb4 2372 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
mbed_official 205:c41fc65bcfb4 2373 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
mbed_official 205:c41fc65bcfb4 2374 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
mbed_official 205:c41fc65bcfb4 2375
mbed_official 205:c41fc65bcfb4 2376 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
mbed_official 205:c41fc65bcfb4 2377
mbed_official 205:c41fc65bcfb4 2378 /******************* Bit definition for CRS_ISR register *********************/
mbed_official 205:c41fc65bcfb4 2379 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
mbed_official 205:c41fc65bcfb4 2380 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
mbed_official 205:c41fc65bcfb4 2381 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
mbed_official 205:c41fc65bcfb4 2382 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
mbed_official 205:c41fc65bcfb4 2383 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
mbed_official 205:c41fc65bcfb4 2384 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
mbed_official 205:c41fc65bcfb4 2385 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
mbed_official 205:c41fc65bcfb4 2386 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
mbed_official 205:c41fc65bcfb4 2387 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
mbed_official 205:c41fc65bcfb4 2388
mbed_official 205:c41fc65bcfb4 2389 /******************* Bit definition for CRS_ICR register *********************/
mbed_official 205:c41fc65bcfb4 2390 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
mbed_official 205:c41fc65bcfb4 2391 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
mbed_official 205:c41fc65bcfb4 2392 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
mbed_official 205:c41fc65bcfb4 2393 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
mbed_official 205:c41fc65bcfb4 2394
mbed_official 205:c41fc65bcfb4 2395 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2396 /* */
mbed_official 205:c41fc65bcfb4 2397 /* Digital to Analog Converter (DAC) */
mbed_official 205:c41fc65bcfb4 2398 /* */
mbed_official 205:c41fc65bcfb4 2399 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2400 /******************** Bit definition for DAC_CR register ********************/
mbed_official 205:c41fc65bcfb4 2401 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 205:c41fc65bcfb4 2402 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 205:c41fc65bcfb4 2403 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 205:c41fc65bcfb4 2404
mbed_official 205:c41fc65bcfb4 2405 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 205:c41fc65bcfb4 2406 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2407 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2408 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 2409
mbed_official 205:c41fc65bcfb4 2410 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 205:c41fc65bcfb4 2411 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2412 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2413
mbed_official 205:c41fc65bcfb4 2414 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 205:c41fc65bcfb4 2415 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2416 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2417 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 2418 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 2419
mbed_official 205:c41fc65bcfb4 2420 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 205:c41fc65bcfb4 2421 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
mbed_official 205:c41fc65bcfb4 2422
mbed_official 205:c41fc65bcfb4 2423 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 205:c41fc65bcfb4 2424 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 205:c41fc65bcfb4 2425 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 205:c41fc65bcfb4 2426
mbed_official 205:c41fc65bcfb4 2427 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 205:c41fc65bcfb4 2428 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2429 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2430 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 2431
mbed_official 205:c41fc65bcfb4 2432 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 205:c41fc65bcfb4 2433 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2434 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2435
mbed_official 205:c41fc65bcfb4 2436 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 205:c41fc65bcfb4 2437 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2438 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2439 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 2440 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 2441
mbed_official 205:c41fc65bcfb4 2442 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 205:c41fc65bcfb4 2443 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
mbed_official 205:c41fc65bcfb4 2444
mbed_official 205:c41fc65bcfb4 2445 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 205:c41fc65bcfb4 2446 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
mbed_official 205:c41fc65bcfb4 2447 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
mbed_official 205:c41fc65bcfb4 2448
mbed_official 205:c41fc65bcfb4 2449 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 205:c41fc65bcfb4 2450 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2451
mbed_official 205:c41fc65bcfb4 2452 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 205:c41fc65bcfb4 2453 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 205:c41fc65bcfb4 2454
mbed_official 205:c41fc65bcfb4 2455 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 205:c41fc65bcfb4 2456 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2457
mbed_official 205:c41fc65bcfb4 2458 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 205:c41fc65bcfb4 2459 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2460
mbed_official 205:c41fc65bcfb4 2461 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 205:c41fc65bcfb4 2462 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 205:c41fc65bcfb4 2463
mbed_official 205:c41fc65bcfb4 2464 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 205:c41fc65bcfb4 2465 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2466
mbed_official 205:c41fc65bcfb4 2467 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 205:c41fc65bcfb4 2468 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2469 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2470
mbed_official 205:c41fc65bcfb4 2471 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 205:c41fc65bcfb4 2472 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 205:c41fc65bcfb4 2473 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 205:c41fc65bcfb4 2474
mbed_official 205:c41fc65bcfb4 2475 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 205:c41fc65bcfb4 2476 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2477 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 205:c41fc65bcfb4 2478
mbed_official 205:c41fc65bcfb4 2479 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 205:c41fc65bcfb4 2480 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
mbed_official 205:c41fc65bcfb4 2481
mbed_official 205:c41fc65bcfb4 2482 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 205:c41fc65bcfb4 2483 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
mbed_official 205:c41fc65bcfb4 2484
mbed_official 205:c41fc65bcfb4 2485 /******************** Bit definition for DAC_SR register ********************/
mbed_official 205:c41fc65bcfb4 2486 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 205:c41fc65bcfb4 2487 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 205:c41fc65bcfb4 2488
mbed_official 205:c41fc65bcfb4 2489 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2490 /* */
mbed_official 205:c41fc65bcfb4 2491 /* Debug MCU (DBGMCU) */
mbed_official 205:c41fc65bcfb4 2492 /* */
mbed_official 205:c41fc65bcfb4 2493 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2494
mbed_official 205:c41fc65bcfb4 2495 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 205:c41fc65bcfb4 2496 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 205:c41fc65bcfb4 2497
mbed_official 205:c41fc65bcfb4 2498 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 205:c41fc65bcfb4 2499 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2500 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2501 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 2502 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 2503 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 205:c41fc65bcfb4 2504 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 205:c41fc65bcfb4 2505 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 205:c41fc65bcfb4 2506 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 205:c41fc65bcfb4 2507 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 205:c41fc65bcfb4 2508 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 205:c41fc65bcfb4 2509 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 205:c41fc65bcfb4 2510 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 205:c41fc65bcfb4 2511 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 205:c41fc65bcfb4 2512 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 205:c41fc65bcfb4 2513 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 205:c41fc65bcfb4 2514 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 205:c41fc65bcfb4 2515
mbed_official 205:c41fc65bcfb4 2516 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 205:c41fc65bcfb4 2517 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 205:c41fc65bcfb4 2518 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 205:c41fc65bcfb4 2519
mbed_official 205:c41fc65bcfb4 2520 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 205:c41fc65bcfb4 2521 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2522 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2523 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2524 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2525 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2526 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
mbed_official 205:c41fc65bcfb4 2527 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 205:c41fc65bcfb4 2528 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 205:c41fc65bcfb4 2529 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
mbed_official 205:c41fc65bcfb4 2530 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
mbed_official 205:c41fc65bcfb4 2531
mbed_official 205:c41fc65bcfb4 2532 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 205:c41fc65bcfb4 2533 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2534 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2535 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2536 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
mbed_official 205:c41fc65bcfb4 2537
mbed_official 205:c41fc65bcfb4 2538 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2539 /* */
mbed_official 205:c41fc65bcfb4 2540 /* DMA Controller (DMA) */
mbed_official 205:c41fc65bcfb4 2541 /* */
mbed_official 205:c41fc65bcfb4 2542 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2543 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 205:c41fc65bcfb4 2544 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2545 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2546 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2547 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2548 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2549 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2550 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2551 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2552 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2553 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2554 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2555 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2556 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2557 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2558 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2559 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2560 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2561 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2562 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2563 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2564 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2565 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2566 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2567 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2568 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 205:c41fc65bcfb4 2569 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 205:c41fc65bcfb4 2570 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 205:c41fc65bcfb4 2571 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 205:c41fc65bcfb4 2572
mbed_official 205:c41fc65bcfb4 2573 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 205:c41fc65bcfb4 2574 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2575 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2576 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2577 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2578 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2579 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2580 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2581 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2582 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2583 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2584 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2585 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2586 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2587 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2588 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2589 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2590 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2591 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2592 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2593 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2594 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2595 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2596 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2597 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2598 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 205:c41fc65bcfb4 2599 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 205:c41fc65bcfb4 2600 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 205:c41fc65bcfb4 2601 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 205:c41fc65bcfb4 2602
mbed_official 205:c41fc65bcfb4 2603 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 205:c41fc65bcfb4 2604 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 205:c41fc65bcfb4 2605 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 205:c41fc65bcfb4 2606 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 205:c41fc65bcfb4 2607 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 205:c41fc65bcfb4 2608 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 205:c41fc65bcfb4 2609 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 205:c41fc65bcfb4 2610 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 205:c41fc65bcfb4 2611 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 205:c41fc65bcfb4 2612
mbed_official 205:c41fc65bcfb4 2613 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 205:c41fc65bcfb4 2614 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2615 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2616
mbed_official 205:c41fc65bcfb4 2617 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 205:c41fc65bcfb4 2618 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2619 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2620
mbed_official 205:c41fc65bcfb4 2621 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 205:c41fc65bcfb4 2622 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 2623 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 2624
mbed_official 205:c41fc65bcfb4 2625 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 205:c41fc65bcfb4 2626
mbed_official 205:c41fc65bcfb4 2627 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 205:c41fc65bcfb4 2628 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 205:c41fc65bcfb4 2629
mbed_official 205:c41fc65bcfb4 2630 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 205:c41fc65bcfb4 2631 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 205:c41fc65bcfb4 2632
mbed_official 205:c41fc65bcfb4 2633 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 205:c41fc65bcfb4 2634 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 205:c41fc65bcfb4 2635
mbed_official 205:c41fc65bcfb4 2636 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2637 /* */
mbed_official 205:c41fc65bcfb4 2638 /* External Interrupt/Event Controller (EXTI) */
mbed_official 205:c41fc65bcfb4 2639 /* */
mbed_official 205:c41fc65bcfb4 2640 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2641 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 205:c41fc65bcfb4 2642 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 205:c41fc65bcfb4 2643 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 205:c41fc65bcfb4 2644 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 205:c41fc65bcfb4 2645 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 205:c41fc65bcfb4 2646 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 205:c41fc65bcfb4 2647 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 205:c41fc65bcfb4 2648 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 205:c41fc65bcfb4 2649 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 205:c41fc65bcfb4 2650 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 205:c41fc65bcfb4 2651 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 205:c41fc65bcfb4 2652 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 205:c41fc65bcfb4 2653 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 205:c41fc65bcfb4 2654 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 205:c41fc65bcfb4 2655 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 205:c41fc65bcfb4 2656 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 205:c41fc65bcfb4 2657 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 205:c41fc65bcfb4 2658 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 205:c41fc65bcfb4 2659 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 205:c41fc65bcfb4 2660 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 205:c41fc65bcfb4 2661 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 205:c41fc65bcfb4 2662 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 205:c41fc65bcfb4 2663 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 205:c41fc65bcfb4 2664 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 205:c41fc65bcfb4 2665 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 205:c41fc65bcfb4 2666
mbed_official 205:c41fc65bcfb4 2667 /****************** Bit definition for EXTI_EMR register ********************/
mbed_official 205:c41fc65bcfb4 2668 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 205:c41fc65bcfb4 2669 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 205:c41fc65bcfb4 2670 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 205:c41fc65bcfb4 2671 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 205:c41fc65bcfb4 2672 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 205:c41fc65bcfb4 2673 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 205:c41fc65bcfb4 2674 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 205:c41fc65bcfb4 2675 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 205:c41fc65bcfb4 2676 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 205:c41fc65bcfb4 2677 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 205:c41fc65bcfb4 2678 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 205:c41fc65bcfb4 2679 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 205:c41fc65bcfb4 2680 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 205:c41fc65bcfb4 2681 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 205:c41fc65bcfb4 2682 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 205:c41fc65bcfb4 2683 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 205:c41fc65bcfb4 2684 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 205:c41fc65bcfb4 2685 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 205:c41fc65bcfb4 2686 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 205:c41fc65bcfb4 2687 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 205:c41fc65bcfb4 2688 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 205:c41fc65bcfb4 2689 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 205:c41fc65bcfb4 2690 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 205:c41fc65bcfb4 2691 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 205:c41fc65bcfb4 2692
mbed_official 205:c41fc65bcfb4 2693 /******************* Bit definition for EXTI_RTSR register ******************/
mbed_official 205:c41fc65bcfb4 2694 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 205:c41fc65bcfb4 2695 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 205:c41fc65bcfb4 2696 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 205:c41fc65bcfb4 2697 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 205:c41fc65bcfb4 2698 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 205:c41fc65bcfb4 2699 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 205:c41fc65bcfb4 2700 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 205:c41fc65bcfb4 2701 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 205:c41fc65bcfb4 2702 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 205:c41fc65bcfb4 2703 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 205:c41fc65bcfb4 2704 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 205:c41fc65bcfb4 2705 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 205:c41fc65bcfb4 2706 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 205:c41fc65bcfb4 2707 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 205:c41fc65bcfb4 2708 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 205:c41fc65bcfb4 2709 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 205:c41fc65bcfb4 2710 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 205:c41fc65bcfb4 2711 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 205:c41fc65bcfb4 2712 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 205:c41fc65bcfb4 2713
mbed_official 205:c41fc65bcfb4 2714 /******************* Bit definition for EXTI_FTSR register *******************/
mbed_official 205:c41fc65bcfb4 2715 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 205:c41fc65bcfb4 2716 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 205:c41fc65bcfb4 2717 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 205:c41fc65bcfb4 2718 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 205:c41fc65bcfb4 2719 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 205:c41fc65bcfb4 2720 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 205:c41fc65bcfb4 2721 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 205:c41fc65bcfb4 2722 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 205:c41fc65bcfb4 2723 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 205:c41fc65bcfb4 2724 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 205:c41fc65bcfb4 2725 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 205:c41fc65bcfb4 2726 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 205:c41fc65bcfb4 2727 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 205:c41fc65bcfb4 2728 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 205:c41fc65bcfb4 2729 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 205:c41fc65bcfb4 2730 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 205:c41fc65bcfb4 2731 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 205:c41fc65bcfb4 2732 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 205:c41fc65bcfb4 2733 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 205:c41fc65bcfb4 2734
mbed_official 205:c41fc65bcfb4 2735 /******************* Bit definition for EXTI_SWIER register *******************/
mbed_official 205:c41fc65bcfb4 2736 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 205:c41fc65bcfb4 2737 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 205:c41fc65bcfb4 2738 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 205:c41fc65bcfb4 2739 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 205:c41fc65bcfb4 2740 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 205:c41fc65bcfb4 2741 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 205:c41fc65bcfb4 2742 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 205:c41fc65bcfb4 2743 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 205:c41fc65bcfb4 2744 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 205:c41fc65bcfb4 2745 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 205:c41fc65bcfb4 2746 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 205:c41fc65bcfb4 2747 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 205:c41fc65bcfb4 2748 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 205:c41fc65bcfb4 2749 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 205:c41fc65bcfb4 2750 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 205:c41fc65bcfb4 2751 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 205:c41fc65bcfb4 2752 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 205:c41fc65bcfb4 2753 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 205:c41fc65bcfb4 2754 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 205:c41fc65bcfb4 2755
mbed_official 205:c41fc65bcfb4 2756 /****************** Bit definition for EXTI_PR register *********************/
mbed_official 205:c41fc65bcfb4 2757 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 205:c41fc65bcfb4 2758 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 205:c41fc65bcfb4 2759 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 205:c41fc65bcfb4 2760 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 205:c41fc65bcfb4 2761 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 205:c41fc65bcfb4 2762 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 205:c41fc65bcfb4 2763 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 205:c41fc65bcfb4 2764 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 205:c41fc65bcfb4 2765 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 205:c41fc65bcfb4 2766 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 205:c41fc65bcfb4 2767 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 205:c41fc65bcfb4 2768 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 205:c41fc65bcfb4 2769 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 205:c41fc65bcfb4 2770 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 205:c41fc65bcfb4 2771 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 205:c41fc65bcfb4 2772 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 205:c41fc65bcfb4 2773 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 205:c41fc65bcfb4 2774 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 205:c41fc65bcfb4 2775 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 205:c41fc65bcfb4 2776
mbed_official 205:c41fc65bcfb4 2777 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2778 /* */
mbed_official 205:c41fc65bcfb4 2779 /* FLASH and Option Bytes Registers */
mbed_official 205:c41fc65bcfb4 2780 /* */
mbed_official 205:c41fc65bcfb4 2781 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2782
mbed_official 205:c41fc65bcfb4 2783 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 205:c41fc65bcfb4 2784 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
mbed_official 205:c41fc65bcfb4 2785
mbed_official 205:c41fc65bcfb4 2786 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 205:c41fc65bcfb4 2787 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 205:c41fc65bcfb4 2788
mbed_official 205:c41fc65bcfb4 2789 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 205:c41fc65bcfb4 2790 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 205:c41fc65bcfb4 2791
mbed_official 205:c41fc65bcfb4 2792 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 205:c41fc65bcfb4 2793 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 205:c41fc65bcfb4 2794
mbed_official 205:c41fc65bcfb4 2795 /****************** FLASH Keys **********************************************/
mbed_official 205:c41fc65bcfb4 2796 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
mbed_official 205:c41fc65bcfb4 2797 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official 205:c41fc65bcfb4 2798 to unlock the write access to the FPEC. */
mbed_official 205:c41fc65bcfb4 2799
mbed_official 205:c41fc65bcfb4 2800 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
mbed_official 205:c41fc65bcfb4 2801 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official 205:c41fc65bcfb4 2802 unlock the write access to the option byte block */
mbed_official 205:c41fc65bcfb4 2803
mbed_official 205:c41fc65bcfb4 2804 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 205:c41fc65bcfb4 2805 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 205:c41fc65bcfb4 2806 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 205:c41fc65bcfb4 2807 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 205:c41fc65bcfb4 2808 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 205:c41fc65bcfb4 2809 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
mbed_official 205:c41fc65bcfb4 2810
mbed_official 205:c41fc65bcfb4 2811 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 205:c41fc65bcfb4 2812 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 205:c41fc65bcfb4 2813 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 205:c41fc65bcfb4 2814 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 205:c41fc65bcfb4 2815 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 205:c41fc65bcfb4 2816 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 205:c41fc65bcfb4 2817 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 205:c41fc65bcfb4 2818 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 205:c41fc65bcfb4 2819 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 205:c41fc65bcfb4 2820 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 205:c41fc65bcfb4 2821 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 205:c41fc65bcfb4 2822 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
mbed_official 205:c41fc65bcfb4 2823
mbed_official 205:c41fc65bcfb4 2824 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 205:c41fc65bcfb4 2825 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 205:c41fc65bcfb4 2826
mbed_official 205:c41fc65bcfb4 2827 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 205:c41fc65bcfb4 2828 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 205:c41fc65bcfb4 2829 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 205:c41fc65bcfb4 2830 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
mbed_official 205:c41fc65bcfb4 2831
mbed_official 205:c41fc65bcfb4 2832 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
mbed_official 205:c41fc65bcfb4 2833 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 205:c41fc65bcfb4 2834 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 205:c41fc65bcfb4 2835 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 205:c41fc65bcfb4 2836 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 205:c41fc65bcfb4 2837 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
mbed_official 205:c41fc65bcfb4 2838
mbed_official 205:c41fc65bcfb4 2839 /* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 2840 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official 205:c41fc65bcfb4 2841
mbed_official 205:c41fc65bcfb4 2842 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 2843 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official 205:c41fc65bcfb4 2844
mbed_official 205:c41fc65bcfb4 2845 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 205:c41fc65bcfb4 2846 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
mbed_official 205:c41fc65bcfb4 2847
mbed_official 205:c41fc65bcfb4 2848 /*----------------------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 2849
mbed_official 205:c41fc65bcfb4 2850 /****************** Bit definition for OB_RDP register **********************/
mbed_official 205:c41fc65bcfb4 2851 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 205:c41fc65bcfb4 2852 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 205:c41fc65bcfb4 2853
mbed_official 205:c41fc65bcfb4 2854 /****************** Bit definition for OB_USER register *********************/
mbed_official 205:c41fc65bcfb4 2855 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 205:c41fc65bcfb4 2856 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 205:c41fc65bcfb4 2857
mbed_official 205:c41fc65bcfb4 2858 /****************** Bit definition for OB_WRP0 register *********************/
mbed_official 205:c41fc65bcfb4 2859 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 205:c41fc65bcfb4 2860 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 205:c41fc65bcfb4 2861
mbed_official 205:c41fc65bcfb4 2862 /****************** Bit definition for OB_WRP1 register *********************/
mbed_official 205:c41fc65bcfb4 2863 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 205:c41fc65bcfb4 2864 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 205:c41fc65bcfb4 2865
mbed_official 205:c41fc65bcfb4 2866 /****************** Bit definition for OB_WRP2 register *********************/
mbed_official 205:c41fc65bcfb4 2867 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 205:c41fc65bcfb4 2868 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 205:c41fc65bcfb4 2869
mbed_official 205:c41fc65bcfb4 2870 /****************** Bit definition for OB_WRP3 register *********************/
mbed_official 205:c41fc65bcfb4 2871 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 205:c41fc65bcfb4 2872 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 205:c41fc65bcfb4 2873
mbed_official 205:c41fc65bcfb4 2874 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2875 /* */
mbed_official 205:c41fc65bcfb4 2876 /* General Purpose IOs (GPIO) */
mbed_official 205:c41fc65bcfb4 2877 /* */
mbed_official 205:c41fc65bcfb4 2878 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 2879 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 205:c41fc65bcfb4 2880 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 205:c41fc65bcfb4 2881 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 2882 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 2883 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 205:c41fc65bcfb4 2884 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 2885 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 2886 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 205:c41fc65bcfb4 2887 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 2888 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 2889 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 205:c41fc65bcfb4 2890 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 2891 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 2892 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 205:c41fc65bcfb4 2893 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 2894 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 2895 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 205:c41fc65bcfb4 2896 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 2897 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 2898 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 205:c41fc65bcfb4 2899 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 2900 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 2901 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 205:c41fc65bcfb4 2902 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 2903 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 2904 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 205:c41fc65bcfb4 2905 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 2906 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 2907 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 205:c41fc65bcfb4 2908 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 2909 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 2910 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 205:c41fc65bcfb4 2911 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 2912 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 2913 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 205:c41fc65bcfb4 2914 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 2915 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 2916 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 205:c41fc65bcfb4 2917 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 2918 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 2919 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 205:c41fc65bcfb4 2920 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 2921 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 2922 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 205:c41fc65bcfb4 2923 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 205:c41fc65bcfb4 2924 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 205:c41fc65bcfb4 2925 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 205:c41fc65bcfb4 2926 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 205:c41fc65bcfb4 2927 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 205:c41fc65bcfb4 2928
mbed_official 205:c41fc65bcfb4 2929 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 205:c41fc65bcfb4 2930 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 2931 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 2932 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 2933 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 2934 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 2935 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 2936 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 2937 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 2938 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 2939 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 2940 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 2941 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 2942 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 2943 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 2944 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 2945 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 2946
mbed_official 205:c41fc65bcfb4 2947 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 205:c41fc65bcfb4 2948 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 205:c41fc65bcfb4 2949 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 2950 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 2951 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 205:c41fc65bcfb4 2952 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 2953 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 2954 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 205:c41fc65bcfb4 2955 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 2956 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 2957 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 205:c41fc65bcfb4 2958 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 2959 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 2960 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 205:c41fc65bcfb4 2961 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 2962 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 2963 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 205:c41fc65bcfb4 2964 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 2965 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 2966 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 205:c41fc65bcfb4 2967 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 2968 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 2969 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 205:c41fc65bcfb4 2970 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 2971 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 2972 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 205:c41fc65bcfb4 2973 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 2974 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 2975 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 205:c41fc65bcfb4 2976 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 2977 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 2978 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 205:c41fc65bcfb4 2979 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 2980 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 2981 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 205:c41fc65bcfb4 2982 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 2983 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 2984 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 205:c41fc65bcfb4 2985 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 2986 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 2987 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 205:c41fc65bcfb4 2988 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 2989 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 2990 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 205:c41fc65bcfb4 2991 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 205:c41fc65bcfb4 2992 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 205:c41fc65bcfb4 2993 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 205:c41fc65bcfb4 2994 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 205:c41fc65bcfb4 2995 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 205:c41fc65bcfb4 2996
mbed_official 205:c41fc65bcfb4 2997 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 2998 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official 205:c41fc65bcfb4 2999 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official 205:c41fc65bcfb4 3000 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official 205:c41fc65bcfb4 3001 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official 205:c41fc65bcfb4 3002 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official 205:c41fc65bcfb4 3003 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official 205:c41fc65bcfb4 3004 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official 205:c41fc65bcfb4 3005 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official 205:c41fc65bcfb4 3006 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official 205:c41fc65bcfb4 3007 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official 205:c41fc65bcfb4 3008 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official 205:c41fc65bcfb4 3009 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official 205:c41fc65bcfb4 3010 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official 205:c41fc65bcfb4 3011 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official 205:c41fc65bcfb4 3012 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official 205:c41fc65bcfb4 3013 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official 205:c41fc65bcfb4 3014 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official 205:c41fc65bcfb4 3015 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official 205:c41fc65bcfb4 3016 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official 205:c41fc65bcfb4 3017 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official 205:c41fc65bcfb4 3018 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official 205:c41fc65bcfb4 3019 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official 205:c41fc65bcfb4 3020 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official 205:c41fc65bcfb4 3021 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official 205:c41fc65bcfb4 3022 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official 205:c41fc65bcfb4 3023 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official 205:c41fc65bcfb4 3024 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official 205:c41fc65bcfb4 3025 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official 205:c41fc65bcfb4 3026 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official 205:c41fc65bcfb4 3027 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official 205:c41fc65bcfb4 3028 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official 205:c41fc65bcfb4 3029 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official 205:c41fc65bcfb4 3030 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official 205:c41fc65bcfb4 3031 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official 205:c41fc65bcfb4 3032 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official 205:c41fc65bcfb4 3033 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official 205:c41fc65bcfb4 3034 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official 205:c41fc65bcfb4 3035 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official 205:c41fc65bcfb4 3036 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official 205:c41fc65bcfb4 3037 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official 205:c41fc65bcfb4 3038 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official 205:c41fc65bcfb4 3039 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official 205:c41fc65bcfb4 3040 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official 205:c41fc65bcfb4 3041 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official 205:c41fc65bcfb4 3042 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official 205:c41fc65bcfb4 3043 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official 205:c41fc65bcfb4 3044 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official 205:c41fc65bcfb4 3045 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official 205:c41fc65bcfb4 3046
mbed_official 205:c41fc65bcfb4 3047 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 205:c41fc65bcfb4 3048 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 205:c41fc65bcfb4 3049 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3050 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3051 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 205:c41fc65bcfb4 3052 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3053 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3054 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 205:c41fc65bcfb4 3055 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3056 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3057 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 205:c41fc65bcfb4 3058 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3059 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3060 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 205:c41fc65bcfb4 3061 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3062 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3063 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 205:c41fc65bcfb4 3064 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3065 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3066 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 205:c41fc65bcfb4 3067 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3068 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3069 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 205:c41fc65bcfb4 3070 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3071 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3072 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 205:c41fc65bcfb4 3073 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3074 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3075 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 205:c41fc65bcfb4 3076 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3077 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3078 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 205:c41fc65bcfb4 3079 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3080 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3081 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 205:c41fc65bcfb4 3082 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3083 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 3084 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 205:c41fc65bcfb4 3085 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 3086 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 3087 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 205:c41fc65bcfb4 3088 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 3089 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 3090 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 205:c41fc65bcfb4 3091 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 205:c41fc65bcfb4 3092 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 205:c41fc65bcfb4 3093 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 205:c41fc65bcfb4 3094 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 205:c41fc65bcfb4 3095 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 205:c41fc65bcfb4 3096
mbed_official 205:c41fc65bcfb4 3097 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 205:c41fc65bcfb4 3098 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3099 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3100 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3101 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3102 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3103 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3104 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3105 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3106 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3107 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3108 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3109 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3110 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3111 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3112 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3113 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3114
mbed_official 205:c41fc65bcfb4 3115 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 205:c41fc65bcfb4 3116 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3117 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3118 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3119 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3120 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3121 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3122 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3123 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3124 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3125 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3126 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3127 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3128 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3129 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3130 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3131 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3132
mbed_official 205:c41fc65bcfb4 3133 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 205:c41fc65bcfb4 3134 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3135 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3136 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3137 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3138 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3139 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3140 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3141 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3142 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3143 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3144 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3145 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3146 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3147 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3148 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3149 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3150 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3151 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3152 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3153 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3154 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3155 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3156 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3157 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 3158 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 3159 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 3160 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 3161 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 3162 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 205:c41fc65bcfb4 3163 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 205:c41fc65bcfb4 3164 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 205:c41fc65bcfb4 3165 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 205:c41fc65bcfb4 3166
mbed_official 205:c41fc65bcfb4 3167 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 205:c41fc65bcfb4 3168 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3169 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3170 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3171 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3172 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3173 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3174 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3175 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3176 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3177 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3178 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3179 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3180 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3181 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3182 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3183 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3184 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3185
mbed_official 205:c41fc65bcfb4 3186 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 205:c41fc65bcfb4 3187 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3188 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 205:c41fc65bcfb4 3189 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3190 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 205:c41fc65bcfb4 3191 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 205:c41fc65bcfb4 3192 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 205:c41fc65bcfb4 3193 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 205:c41fc65bcfb4 3194 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 205:c41fc65bcfb4 3195
mbed_official 205:c41fc65bcfb4 3196 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 205:c41fc65bcfb4 3197 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3198 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 205:c41fc65bcfb4 3199 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3200 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 205:c41fc65bcfb4 3201 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 205:c41fc65bcfb4 3202 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 205:c41fc65bcfb4 3203 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 205:c41fc65bcfb4 3204 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 205:c41fc65bcfb4 3205
mbed_official 205:c41fc65bcfb4 3206 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 205:c41fc65bcfb4 3207 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3208 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3209 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3210 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3211 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3212 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3213 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3214 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3215 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3216 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3217 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3218 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3219 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3220 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3221 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3222 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3223
mbed_official 205:c41fc65bcfb4 3224 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 3225 /* */
mbed_official 205:c41fc65bcfb4 3226 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 205:c41fc65bcfb4 3227 /* */
mbed_official 205:c41fc65bcfb4 3228 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 3229
mbed_official 205:c41fc65bcfb4 3230 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 205:c41fc65bcfb4 3231 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 205:c41fc65bcfb4 3232 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 205:c41fc65bcfb4 3233 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 205:c41fc65bcfb4 3234 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 205:c41fc65bcfb4 3235 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 205:c41fc65bcfb4 3236 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 205:c41fc65bcfb4 3237 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 205:c41fc65bcfb4 3238 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 205:c41fc65bcfb4 3239 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 205:c41fc65bcfb4 3240 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 205:c41fc65bcfb4 3241 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 205:c41fc65bcfb4 3242 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 205:c41fc65bcfb4 3243 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 205:c41fc65bcfb4 3244 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 205:c41fc65bcfb4 3245 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 205:c41fc65bcfb4 3246 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 205:c41fc65bcfb4 3247 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 205:c41fc65bcfb4 3248 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 205:c41fc65bcfb4 3249 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 205:c41fc65bcfb4 3250 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 205:c41fc65bcfb4 3251 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 205:c41fc65bcfb4 3252
mbed_official 205:c41fc65bcfb4 3253 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 205:c41fc65bcfb4 3254 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 205:c41fc65bcfb4 3255 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 205:c41fc65bcfb4 3256 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 205:c41fc65bcfb4 3257 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 205:c41fc65bcfb4 3258 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 205:c41fc65bcfb4 3259 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 205:c41fc65bcfb4 3260 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 205:c41fc65bcfb4 3261 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 205:c41fc65bcfb4 3262 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 205:c41fc65bcfb4 3263 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 205:c41fc65bcfb4 3264 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 205:c41fc65bcfb4 3265
mbed_official 205:c41fc65bcfb4 3266 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 205:c41fc65bcfb4 3267 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 205:c41fc65bcfb4 3268 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 205:c41fc65bcfb4 3269 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 205:c41fc65bcfb4 3270
mbed_official 205:c41fc65bcfb4 3271 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 205:c41fc65bcfb4 3272 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 205:c41fc65bcfb4 3273 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 205:c41fc65bcfb4 3274 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 205:c41fc65bcfb4 3275
mbed_official 205:c41fc65bcfb4 3276 /******************* Bit definition for I2C_TIMINGR register ****************/
mbed_official 205:c41fc65bcfb4 3277 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 205:c41fc65bcfb4 3278 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 205:c41fc65bcfb4 3279 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 205:c41fc65bcfb4 3280 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 205:c41fc65bcfb4 3281 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 205:c41fc65bcfb4 3282
mbed_official 205:c41fc65bcfb4 3283 /******************* Bit definition for I2C_TIMEOUTR register ****************/
mbed_official 205:c41fc65bcfb4 3284 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 205:c41fc65bcfb4 3285 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 205:c41fc65bcfb4 3286 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 205:c41fc65bcfb4 3287 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 205:c41fc65bcfb4 3288 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 205:c41fc65bcfb4 3289
mbed_official 205:c41fc65bcfb4 3290 /****************** Bit definition for I2C_ISR register ********************/
mbed_official 205:c41fc65bcfb4 3291 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 205:c41fc65bcfb4 3292 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 205:c41fc65bcfb4 3293 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 205:c41fc65bcfb4 3294 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 205:c41fc65bcfb4 3295 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 205:c41fc65bcfb4 3296 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 205:c41fc65bcfb4 3297 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 205:c41fc65bcfb4 3298 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 205:c41fc65bcfb4 3299 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 205:c41fc65bcfb4 3300 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 205:c41fc65bcfb4 3301 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 205:c41fc65bcfb4 3302 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 205:c41fc65bcfb4 3303 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 205:c41fc65bcfb4 3304 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 205:c41fc65bcfb4 3305 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 205:c41fc65bcfb4 3306 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 205:c41fc65bcfb4 3307 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 205:c41fc65bcfb4 3308
mbed_official 205:c41fc65bcfb4 3309 /****************** Bit definition for I2C_ICR register ********************/
mbed_official 205:c41fc65bcfb4 3310 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 205:c41fc65bcfb4 3311 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 205:c41fc65bcfb4 3312 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 205:c41fc65bcfb4 3313 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 205:c41fc65bcfb4 3314 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 205:c41fc65bcfb4 3315 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 205:c41fc65bcfb4 3316 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 205:c41fc65bcfb4 3317 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 205:c41fc65bcfb4 3318 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 205:c41fc65bcfb4 3319
mbed_official 205:c41fc65bcfb4 3320 /****************** Bit definition for I2C_PECR register *******************/
mbed_official 205:c41fc65bcfb4 3321 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 205:c41fc65bcfb4 3322
mbed_official 205:c41fc65bcfb4 3323 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 205:c41fc65bcfb4 3324 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 205:c41fc65bcfb4 3325
mbed_official 205:c41fc65bcfb4 3326 /****************** Bit definition for I2C_TXDR register *******************/
mbed_official 205:c41fc65bcfb4 3327 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 205:c41fc65bcfb4 3328
mbed_official 205:c41fc65bcfb4 3329 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3330 /* */
mbed_official 205:c41fc65bcfb4 3331 /* Independent WATCHDOG (IWDG) */
mbed_official 205:c41fc65bcfb4 3332 /* */
mbed_official 205:c41fc65bcfb4 3333 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3334 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 205:c41fc65bcfb4 3335 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
mbed_official 205:c41fc65bcfb4 3336
mbed_official 205:c41fc65bcfb4 3337 /******************* Bit definition for IWDG_PR register *******************/
mbed_official 205:c41fc65bcfb4 3338 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
mbed_official 205:c41fc65bcfb4 3339 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3340 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3341 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3342
mbed_official 205:c41fc65bcfb4 3343 /******************* Bit definition for IWDG_RLR register ******************/
mbed_official 205:c41fc65bcfb4 3344 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
mbed_official 205:c41fc65bcfb4 3345
mbed_official 205:c41fc65bcfb4 3346 /******************* Bit definition for IWDG_SR register *******************/
mbed_official 205:c41fc65bcfb4 3347 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 205:c41fc65bcfb4 3348 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 205:c41fc65bcfb4 3349 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
mbed_official 205:c41fc65bcfb4 3350
mbed_official 205:c41fc65bcfb4 3351 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 205:c41fc65bcfb4 3352 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 205:c41fc65bcfb4 3353
mbed_official 205:c41fc65bcfb4 3354 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3355 /* */
mbed_official 205:c41fc65bcfb4 3356 /* Power Control (PWR) */
mbed_official 205:c41fc65bcfb4 3357 /* */
mbed_official 205:c41fc65bcfb4 3358 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3359
mbed_official 205:c41fc65bcfb4 3360 /******************** Bit definition for PWR_CR register *******************/
mbed_official 205:c41fc65bcfb4 3361 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 205:c41fc65bcfb4 3362 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 205:c41fc65bcfb4 3363 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 205:c41fc65bcfb4 3364 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 205:c41fc65bcfb4 3365 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 205:c41fc65bcfb4 3366
mbed_official 205:c41fc65bcfb4 3367 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 205:c41fc65bcfb4 3368 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3369 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3370 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3371
mbed_official 205:c41fc65bcfb4 3372 /*!< PVD level configuration */
mbed_official 205:c41fc65bcfb4 3373 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 205:c41fc65bcfb4 3374 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 205:c41fc65bcfb4 3375 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 205:c41fc65bcfb4 3376 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 205:c41fc65bcfb4 3377 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 205:c41fc65bcfb4 3378 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 205:c41fc65bcfb4 3379 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 205:c41fc65bcfb4 3380 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 205:c41fc65bcfb4 3381
mbed_official 205:c41fc65bcfb4 3382 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 205:c41fc65bcfb4 3383
mbed_official 205:c41fc65bcfb4 3384 /******************* Bit definition for PWR_CSR register *******************/
mbed_official 205:c41fc65bcfb4 3385 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 205:c41fc65bcfb4 3386 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 205:c41fc65bcfb4 3387 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 205:c41fc65bcfb4 3388 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 205:c41fc65bcfb4 3389
mbed_official 205:c41fc65bcfb4 3390 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 205:c41fc65bcfb4 3391 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 205:c41fc65bcfb4 3392 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 205:c41fc65bcfb4 3393 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
mbed_official 205:c41fc65bcfb4 3394 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
mbed_official 205:c41fc65bcfb4 3395 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
mbed_official 205:c41fc65bcfb4 3396 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
mbed_official 205:c41fc65bcfb4 3397 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
mbed_official 205:c41fc65bcfb4 3398
mbed_official 205:c41fc65bcfb4 3399 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3400 /* */
mbed_official 205:c41fc65bcfb4 3401 /* Reset and Clock Control */
mbed_official 205:c41fc65bcfb4 3402 /* */
mbed_official 205:c41fc65bcfb4 3403 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3404
mbed_official 205:c41fc65bcfb4 3405 /******************** Bit definition for RCC_CR register *******************/
mbed_official 205:c41fc65bcfb4 3406 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 205:c41fc65bcfb4 3407 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 205:c41fc65bcfb4 3408
mbed_official 205:c41fc65bcfb4 3409 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
mbed_official 205:c41fc65bcfb4 3410 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 3411 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 3412 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 3413 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 3414 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 3415
mbed_official 205:c41fc65bcfb4 3416 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
mbed_official 205:c41fc65bcfb4 3417 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 3418 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 3419 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 3420 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 3421 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 3422 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 205:c41fc65bcfb4 3423 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 205:c41fc65bcfb4 3424 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 205:c41fc65bcfb4 3425
mbed_official 205:c41fc65bcfb4 3426 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 205:c41fc65bcfb4 3427 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 205:c41fc65bcfb4 3428 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 205:c41fc65bcfb4 3429 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
mbed_official 205:c41fc65bcfb4 3430 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 205:c41fc65bcfb4 3431 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 205:c41fc65bcfb4 3432
mbed_official 205:c41fc65bcfb4 3433 /******************** Bit definition for RCC_CFGR register *****************/
mbed_official 205:c41fc65bcfb4 3434 /*!< SW configuration */
mbed_official 205:c41fc65bcfb4 3435 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 205:c41fc65bcfb4 3436 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3437 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3438
mbed_official 205:c41fc65bcfb4 3439 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 205:c41fc65bcfb4 3440 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 205:c41fc65bcfb4 3441 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 205:c41fc65bcfb4 3442 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
mbed_official 205:c41fc65bcfb4 3443
mbed_official 205:c41fc65bcfb4 3444 /*!< SWS configuration */
mbed_official 205:c41fc65bcfb4 3445 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 205:c41fc65bcfb4 3446 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3447 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3448
mbed_official 205:c41fc65bcfb4 3449 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 205:c41fc65bcfb4 3450 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 205:c41fc65bcfb4 3451 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 205:c41fc65bcfb4 3452 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
mbed_official 205:c41fc65bcfb4 3453
mbed_official 205:c41fc65bcfb4 3454 /*!< HPRE configuration */
mbed_official 205:c41fc65bcfb4 3455 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 205:c41fc65bcfb4 3456 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3457 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3458 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3459 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 3460
mbed_official 205:c41fc65bcfb4 3461 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 205:c41fc65bcfb4 3462 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 205:c41fc65bcfb4 3463 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 205:c41fc65bcfb4 3464 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 205:c41fc65bcfb4 3465 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 205:c41fc65bcfb4 3466 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 205:c41fc65bcfb4 3467 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 205:c41fc65bcfb4 3468 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 205:c41fc65bcfb4 3469 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 205:c41fc65bcfb4 3470
mbed_official 205:c41fc65bcfb4 3471 /*!< PPRE configuration */
mbed_official 205:c41fc65bcfb4 3472 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
mbed_official 205:c41fc65bcfb4 3473 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3474 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3475 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3476
mbed_official 205:c41fc65bcfb4 3477 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 205:c41fc65bcfb4 3478 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 205:c41fc65bcfb4 3479 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 205:c41fc65bcfb4 3480 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 205:c41fc65bcfb4 3481 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 205:c41fc65bcfb4 3482
mbed_official 205:c41fc65bcfb4 3483 /*!< ADCPPRE configuration */
mbed_official 205:c41fc65bcfb4 3484 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
mbed_official 205:c41fc65bcfb4 3485
mbed_official 205:c41fc65bcfb4 3486 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
mbed_official 205:c41fc65bcfb4 3487 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
mbed_official 205:c41fc65bcfb4 3488
mbed_official 205:c41fc65bcfb4 3489 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
mbed_official 205:c41fc65bcfb4 3490 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 205:c41fc65bcfb4 3491 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
mbed_official 205:c41fc65bcfb4 3492 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 205:c41fc65bcfb4 3493 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
mbed_official 205:c41fc65bcfb4 3494
mbed_official 205:c41fc65bcfb4 3495 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 205:c41fc65bcfb4 3496 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 205:c41fc65bcfb4 3497 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 205:c41fc65bcfb4 3498
mbed_official 205:c41fc65bcfb4 3499 /*!< PLLMUL configuration */
mbed_official 205:c41fc65bcfb4 3500 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 205:c41fc65bcfb4 3501 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3502 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3503 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3504 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 3505
mbed_official 205:c41fc65bcfb4 3506 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 205:c41fc65bcfb4 3507 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 205:c41fc65bcfb4 3508 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 205:c41fc65bcfb4 3509 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 205:c41fc65bcfb4 3510 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 205:c41fc65bcfb4 3511 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 205:c41fc65bcfb4 3512 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 205:c41fc65bcfb4 3513 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 205:c41fc65bcfb4 3514 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 205:c41fc65bcfb4 3515 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 205:c41fc65bcfb4 3516 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 205:c41fc65bcfb4 3517 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 205:c41fc65bcfb4 3518 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 205:c41fc65bcfb4 3519 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 205:c41fc65bcfb4 3520 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 205:c41fc65bcfb4 3521
mbed_official 205:c41fc65bcfb4 3522 /*!< USB configuration */
mbed_official 205:c41fc65bcfb4 3523 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
mbed_official 205:c41fc65bcfb4 3524
mbed_official 205:c41fc65bcfb4 3525 /*!< MCO configuration */
mbed_official 205:c41fc65bcfb4 3526 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
mbed_official 205:c41fc65bcfb4 3527 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3528 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3529 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3530 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 3531
mbed_official 205:c41fc65bcfb4 3532 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 205:c41fc65bcfb4 3533 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3534 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3535 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3536 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3537 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3538 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3539 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 205:c41fc65bcfb4 3540 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
mbed_official 205:c41fc65bcfb4 3541
mbed_official 205:c41fc65bcfb4 3542 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
mbed_official 205:c41fc65bcfb4 3543 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
mbed_official 205:c41fc65bcfb4 3544 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
mbed_official 205:c41fc65bcfb4 3545 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
mbed_official 205:c41fc65bcfb4 3546 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
mbed_official 205:c41fc65bcfb4 3547 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
mbed_official 205:c41fc65bcfb4 3548 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
mbed_official 205:c41fc65bcfb4 3549 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
mbed_official 205:c41fc65bcfb4 3550 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
mbed_official 205:c41fc65bcfb4 3551
mbed_official 205:c41fc65bcfb4 3552 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 205:c41fc65bcfb4 3553
mbed_official 205:c41fc65bcfb4 3554 /*!<****************** Bit definition for RCC_CIR register *****************/
mbed_official 205:c41fc65bcfb4 3555 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3556 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3557 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3558 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3559 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3560 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3561 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
mbed_official 205:c41fc65bcfb4 3562 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 205:c41fc65bcfb4 3563 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3564 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3565 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3566 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3567 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3568 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3569 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
mbed_official 205:c41fc65bcfb4 3570 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3571 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3572 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3573 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3574 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3575 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3576 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3577 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 205:c41fc65bcfb4 3578
mbed_official 205:c41fc65bcfb4 3579 /***************** Bit definition for RCC_APB2RSTR register ****************/
mbed_official 205:c41fc65bcfb4 3580 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
mbed_official 205:c41fc65bcfb4 3581 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
mbed_official 205:c41fc65bcfb4 3582 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
mbed_official 205:c41fc65bcfb4 3583 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
mbed_official 205:c41fc65bcfb4 3584 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
mbed_official 205:c41fc65bcfb4 3585 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
mbed_official 205:c41fc65bcfb4 3586 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
mbed_official 205:c41fc65bcfb4 3587 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
mbed_official 205:c41fc65bcfb4 3588 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
mbed_official 205:c41fc65bcfb4 3589
mbed_official 205:c41fc65bcfb4 3590 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 3591 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official 205:c41fc65bcfb4 3592
mbed_official 205:c41fc65bcfb4 3593 /***************** Bit definition for RCC_APB1RSTR register ****************/
mbed_official 205:c41fc65bcfb4 3594 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
mbed_official 205:c41fc65bcfb4 3595 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
mbed_official 205:c41fc65bcfb4 3596 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
mbed_official 205:c41fc65bcfb4 3597 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
mbed_official 205:c41fc65bcfb4 3598 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
mbed_official 205:c41fc65bcfb4 3599 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
mbed_official 205:c41fc65bcfb4 3600 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
mbed_official 205:c41fc65bcfb4 3601 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
mbed_official 205:c41fc65bcfb4 3602 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
mbed_official 205:c41fc65bcfb4 3603 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
mbed_official 205:c41fc65bcfb4 3604 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
mbed_official 205:c41fc65bcfb4 3605 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
mbed_official 205:c41fc65bcfb4 3606 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
mbed_official 205:c41fc65bcfb4 3607 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
mbed_official 205:c41fc65bcfb4 3608 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
mbed_official 205:c41fc65bcfb4 3609 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
mbed_official 205:c41fc65bcfb4 3610 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
mbed_official 205:c41fc65bcfb4 3611 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
mbed_official 205:c41fc65bcfb4 3612
mbed_official 205:c41fc65bcfb4 3613 /****************** Bit definition for RCC_AHBENR register *****************/
mbed_official 205:c41fc65bcfb4 3614 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 205:c41fc65bcfb4 3615 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 205:c41fc65bcfb4 3616 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 205:c41fc65bcfb4 3617 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 205:c41fc65bcfb4 3618 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 205:c41fc65bcfb4 3619 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 205:c41fc65bcfb4 3620 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 205:c41fc65bcfb4 3621 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 205:c41fc65bcfb4 3622 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 205:c41fc65bcfb4 3623 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 205:c41fc65bcfb4 3624 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
mbed_official 205:c41fc65bcfb4 3625
mbed_official 205:c41fc65bcfb4 3626 /* Old Bit definition maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 3627 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
mbed_official 205:c41fc65bcfb4 3628 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
mbed_official 205:c41fc65bcfb4 3629
mbed_official 205:c41fc65bcfb4 3630 /***************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 205:c41fc65bcfb4 3631 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
mbed_official 205:c41fc65bcfb4 3632 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 205:c41fc65bcfb4 3633 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 205:c41fc65bcfb4 3634 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 205:c41fc65bcfb4 3635 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 205:c41fc65bcfb4 3636 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 205:c41fc65bcfb4 3637 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 205:c41fc65bcfb4 3638 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 205:c41fc65bcfb4 3639 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
mbed_official 205:c41fc65bcfb4 3640
mbed_official 205:c41fc65bcfb4 3641 /* Old Bit definition maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 3642 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
mbed_official 205:c41fc65bcfb4 3643 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 205:c41fc65bcfb4 3644
mbed_official 205:c41fc65bcfb4 3645 /***************** Bit definition for RCC_APB1ENR register *****************/
mbed_official 205:c41fc65bcfb4 3646 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 205:c41fc65bcfb4 3647 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 205:c41fc65bcfb4 3648 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 205:c41fc65bcfb4 3649 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 205:c41fc65bcfb4 3650 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
mbed_official 205:c41fc65bcfb4 3651 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 205:c41fc65bcfb4 3652 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 205:c41fc65bcfb4 3653 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
mbed_official 205:c41fc65bcfb4 3654 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
mbed_official 205:c41fc65bcfb4 3655 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
mbed_official 205:c41fc65bcfb4 3656 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
mbed_official 205:c41fc65bcfb4 3657 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
mbed_official 205:c41fc65bcfb4 3658 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 205:c41fc65bcfb4 3659 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 205:c41fc65bcfb4 3660 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
mbed_official 205:c41fc65bcfb4 3661 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 205:c41fc65bcfb4 3662 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
mbed_official 205:c41fc65bcfb4 3663 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
mbed_official 205:c41fc65bcfb4 3664
mbed_official 205:c41fc65bcfb4 3665 /******************* Bit definition for RCC_BDCR register ******************/
mbed_official 205:c41fc65bcfb4 3666 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 205:c41fc65bcfb4 3667 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 205:c41fc65bcfb4 3668 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 205:c41fc65bcfb4 3669
mbed_official 205:c41fc65bcfb4 3670 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 205:c41fc65bcfb4 3671 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3672 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3673
mbed_official 205:c41fc65bcfb4 3674 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 205:c41fc65bcfb4 3675 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3676 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3677
mbed_official 205:c41fc65bcfb4 3678 /*!< RTC configuration */
mbed_official 205:c41fc65bcfb4 3679 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 205:c41fc65bcfb4 3680 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 205:c41fc65bcfb4 3681 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 205:c41fc65bcfb4 3682 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
mbed_official 205:c41fc65bcfb4 3683
mbed_official 205:c41fc65bcfb4 3684 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 205:c41fc65bcfb4 3685 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 205:c41fc65bcfb4 3686
mbed_official 205:c41fc65bcfb4 3687 /******************* Bit definition for RCC_CSR register *******************/
mbed_official 205:c41fc65bcfb4 3688 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 205:c41fc65bcfb4 3689 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 205:c41fc65bcfb4 3690 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
mbed_official 205:c41fc65bcfb4 3691 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 205:c41fc65bcfb4 3692 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 205:c41fc65bcfb4 3693 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 205:c41fc65bcfb4 3694 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 205:c41fc65bcfb4 3695 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 205:c41fc65bcfb4 3696 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 205:c41fc65bcfb4 3697 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 205:c41fc65bcfb4 3698 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 205:c41fc65bcfb4 3699
mbed_official 205:c41fc65bcfb4 3700 /* Old Bit definition maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 3701 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 205:c41fc65bcfb4 3702
mbed_official 205:c41fc65bcfb4 3703 /******************* Bit definition for RCC_AHBRSTR register ***************/
mbed_official 205:c41fc65bcfb4 3704 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
mbed_official 205:c41fc65bcfb4 3705 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
mbed_official 205:c41fc65bcfb4 3706 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
mbed_official 205:c41fc65bcfb4 3707 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
mbed_official 205:c41fc65bcfb4 3708 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
mbed_official 205:c41fc65bcfb4 3709 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
mbed_official 205:c41fc65bcfb4 3710 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
mbed_official 205:c41fc65bcfb4 3711
mbed_official 205:c41fc65bcfb4 3712 /* Old Bit definition maintained for legacy purpose */
mbed_official 205:c41fc65bcfb4 3713 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
mbed_official 205:c41fc65bcfb4 3714
mbed_official 205:c41fc65bcfb4 3715 /******************* Bit definition for RCC_CFGR2 register *****************/
mbed_official 205:c41fc65bcfb4 3716 /*!< PREDIV configuration */
mbed_official 205:c41fc65bcfb4 3717 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 205:c41fc65bcfb4 3718 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3719 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3720 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 3721 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 3722
mbed_official 205:c41fc65bcfb4 3723 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 205:c41fc65bcfb4 3724 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 205:c41fc65bcfb4 3725 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 205:c41fc65bcfb4 3726 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 205:c41fc65bcfb4 3727 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 205:c41fc65bcfb4 3728 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 205:c41fc65bcfb4 3729 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 205:c41fc65bcfb4 3730 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 205:c41fc65bcfb4 3731 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 205:c41fc65bcfb4 3732 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 205:c41fc65bcfb4 3733 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 205:c41fc65bcfb4 3734 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 205:c41fc65bcfb4 3735 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 205:c41fc65bcfb4 3736 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 205:c41fc65bcfb4 3737 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 205:c41fc65bcfb4 3738 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 205:c41fc65bcfb4 3739
mbed_official 205:c41fc65bcfb4 3740 /******************* Bit definition for RCC_CFGR3 register *****************/
mbed_official 205:c41fc65bcfb4 3741 /*!< USART1 Clock source selection */
mbed_official 205:c41fc65bcfb4 3742 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 205:c41fc65bcfb4 3743 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3744 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3745
mbed_official 205:c41fc65bcfb4 3746 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
mbed_official 205:c41fc65bcfb4 3747 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 205:c41fc65bcfb4 3748 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 205:c41fc65bcfb4 3749 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 205:c41fc65bcfb4 3750
mbed_official 205:c41fc65bcfb4 3751 /*!< I2C1 Clock source selection */
mbed_official 205:c41fc65bcfb4 3752 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 205:c41fc65bcfb4 3753
mbed_official 205:c41fc65bcfb4 3754 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 205:c41fc65bcfb4 3755 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 205:c41fc65bcfb4 3756
mbed_official 205:c41fc65bcfb4 3757 /*!< CEC Clock source selection */
mbed_official 205:c41fc65bcfb4 3758 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
mbed_official 205:c41fc65bcfb4 3759
mbed_official 205:c41fc65bcfb4 3760 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
mbed_official 205:c41fc65bcfb4 3761 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
mbed_official 205:c41fc65bcfb4 3762
mbed_official 205:c41fc65bcfb4 3763 /*!< USB Clock source selection */
mbed_official 205:c41fc65bcfb4 3764 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
mbed_official 205:c41fc65bcfb4 3765
mbed_official 205:c41fc65bcfb4 3766 #define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
mbed_official 205:c41fc65bcfb4 3767 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
mbed_official 205:c41fc65bcfb4 3768
mbed_official 205:c41fc65bcfb4 3769 /*!< USART2 Clock source selection */
mbed_official 205:c41fc65bcfb4 3770 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 205:c41fc65bcfb4 3771 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 3772 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 3773
mbed_official 205:c41fc65bcfb4 3774 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
mbed_official 205:c41fc65bcfb4 3775 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
mbed_official 205:c41fc65bcfb4 3776 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
mbed_official 205:c41fc65bcfb4 3777 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
mbed_official 205:c41fc65bcfb4 3778
mbed_official 205:c41fc65bcfb4 3779 /******************* Bit definition for RCC_CR2 register *******************/
mbed_official 205:c41fc65bcfb4 3780 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
mbed_official 205:c41fc65bcfb4 3781 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
mbed_official 205:c41fc65bcfb4 3782 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
mbed_official 205:c41fc65bcfb4 3783 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
mbed_official 205:c41fc65bcfb4 3784 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
mbed_official 205:c41fc65bcfb4 3785 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
mbed_official 205:c41fc65bcfb4 3786 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
mbed_official 205:c41fc65bcfb4 3787 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
mbed_official 205:c41fc65bcfb4 3788
mbed_official 205:c41fc65bcfb4 3789 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3790 /* */
mbed_official 205:c41fc65bcfb4 3791 /* Real-Time Clock (RTC) */
mbed_official 205:c41fc65bcfb4 3792 /* */
mbed_official 205:c41fc65bcfb4 3793 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 3794 /******************** Bits definition for RTC_TR register ******************/
mbed_official 205:c41fc65bcfb4 3795 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3796 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 205:c41fc65bcfb4 3797 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3798 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3799 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 205:c41fc65bcfb4 3800 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3801 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3802 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3803 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3804 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 205:c41fc65bcfb4 3805 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3806 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3807 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3808 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3809 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3810 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3811 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3812 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3813 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 205:c41fc65bcfb4 3814 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3815 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3816 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3817 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3818 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3819 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3820 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3821 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3822
mbed_official 205:c41fc65bcfb4 3823 /******************** Bits definition for RTC_DR register ******************/
mbed_official 205:c41fc65bcfb4 3824 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 205:c41fc65bcfb4 3825 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3826 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3827 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3828 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 3829 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 205:c41fc65bcfb4 3830 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3831 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3832 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3833 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3834 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 205:c41fc65bcfb4 3835 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3836 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3837 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3838 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3839 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3840 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3841 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3842 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3843 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3844 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 205:c41fc65bcfb4 3845 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3846 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3847 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3848 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3849 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3850 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3851 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3852
mbed_official 205:c41fc65bcfb4 3853 /******************** Bits definition for RTC_CR register ******************/
mbed_official 205:c41fc65bcfb4 3854 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 3855 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 205:c41fc65bcfb4 3856 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3857 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3858 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3859 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3860 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3861 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3862 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3863 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3864 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3865 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3866 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3867 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3868 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3869 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3870 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3871 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3872 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 205:c41fc65bcfb4 3873 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3874 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3875 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3876
mbed_official 205:c41fc65bcfb4 3877 /******************** Bits definition for RTC_ISR register *****************/
mbed_official 205:c41fc65bcfb4 3878 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3879 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3880 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3881 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3882 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3883 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3884 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3885 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3886 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3887 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3888 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3889 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3890 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3891 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3892 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3893
mbed_official 205:c41fc65bcfb4 3894 /******************** Bits definition for RTC_PRER register ****************/
mbed_official 205:c41fc65bcfb4 3895 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 205:c41fc65bcfb4 3896 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 205:c41fc65bcfb4 3897
mbed_official 205:c41fc65bcfb4 3898 /******************** Bits definition for RTC_WUTR register ****************/
mbed_official 205:c41fc65bcfb4 3899 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 205:c41fc65bcfb4 3900
mbed_official 205:c41fc65bcfb4 3901 /******************** Bits definition for RTC_ALRMAR register **************/
mbed_official 205:c41fc65bcfb4 3902 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 205:c41fc65bcfb4 3903 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 205:c41fc65bcfb4 3904 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 205:c41fc65bcfb4 3905 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 205:c41fc65bcfb4 3906 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 205:c41fc65bcfb4 3907 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 205:c41fc65bcfb4 3908 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 3909 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 3910 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 3911 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 3912 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 3913 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3914 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 205:c41fc65bcfb4 3915 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3916 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3917 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 205:c41fc65bcfb4 3918 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3919 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3920 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3921 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3922 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3923 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 205:c41fc65bcfb4 3924 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3925 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3926 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3927 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3928 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3929 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3930 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3931 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3932 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 3933 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 205:c41fc65bcfb4 3934 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3935 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3936 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3937 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3938 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3939 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3940 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3941 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3942
mbed_official 205:c41fc65bcfb4 3943 /******************** Bits definition for RTC_WPR register *****************/
mbed_official 205:c41fc65bcfb4 3944 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 205:c41fc65bcfb4 3945
mbed_official 205:c41fc65bcfb4 3946 /******************** Bits definition for RTC_SSR register *****************/
mbed_official 205:c41fc65bcfb4 3947 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 205:c41fc65bcfb4 3948
mbed_official 205:c41fc65bcfb4 3949 /******************** Bits definition for RTC_SHIFTR register **************/
mbed_official 205:c41fc65bcfb4 3950 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 205:c41fc65bcfb4 3951 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 205:c41fc65bcfb4 3952
mbed_official 205:c41fc65bcfb4 3953 /******************** Bits definition for RTC_TSTR register ****************/
mbed_official 205:c41fc65bcfb4 3954 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 3955 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 205:c41fc65bcfb4 3956 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 3957 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 3958 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 205:c41fc65bcfb4 3959 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 3960 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 3961 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 3962 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 3963 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 205:c41fc65bcfb4 3964 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3965 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3966 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3967 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3968 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3969 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3970 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3971 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3972 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 205:c41fc65bcfb4 3973 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3974 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3975 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 3976 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3977 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3978 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3979 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 3980 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 3981
mbed_official 205:c41fc65bcfb4 3982 /******************** Bits definition for RTC_TSDR register ****************/
mbed_official 205:c41fc65bcfb4 3983 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 205:c41fc65bcfb4 3984 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 3985 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 3986 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 3987 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 3988 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 205:c41fc65bcfb4 3989 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 3990 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 3991 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 3992 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 3993 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 205:c41fc65bcfb4 3994 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 3995 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 3996 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 205:c41fc65bcfb4 3997 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 3998 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 3999 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 4000 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 4001
mbed_official 205:c41fc65bcfb4 4002 /******************** Bits definition for RTC_TSSSR register ***************/
mbed_official 205:c41fc65bcfb4 4003 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 205:c41fc65bcfb4 4004
mbed_official 205:c41fc65bcfb4 4005 /******************** Bits definition for RTC_CALR register ****************/
mbed_official 205:c41fc65bcfb4 4006 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 4007 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 4008 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 4009 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 205:c41fc65bcfb4 4010 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 4011 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 4012 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 4013 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 4014 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 4015 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 4016 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 4017 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 4018 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 4019
mbed_official 205:c41fc65bcfb4 4020 /******************** Bits definition for RTC_TAFCR register ***************/
mbed_official 205:c41fc65bcfb4 4021 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 4022 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 4023 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 205:c41fc65bcfb4 4024 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 4025 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 4026 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 205:c41fc65bcfb4 4027 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 4028 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 4029 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 205:c41fc65bcfb4 4030 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 4031 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 4032 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 4033 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 4034 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 4035 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 4036 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 4037 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 4038 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 4039 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 4040 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 4041
mbed_official 205:c41fc65bcfb4 4042 /******************** Bits definition for RTC_ALRMASSR register ************/
mbed_official 205:c41fc65bcfb4 4043 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 205:c41fc65bcfb4 4044 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 4045 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 4046 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 4047 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 4048 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 205:c41fc65bcfb4 4049
mbed_official 205:c41fc65bcfb4 4050 /******************** Bits definition for RTC_BKP0R register ***************/
mbed_official 205:c41fc65bcfb4 4051 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 205:c41fc65bcfb4 4052
mbed_official 205:c41fc65bcfb4 4053 /******************** Bits definition for RTC_BKP1R register ***************/
mbed_official 205:c41fc65bcfb4 4054 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 205:c41fc65bcfb4 4055
mbed_official 205:c41fc65bcfb4 4056 /******************** Bits definition for RTC_BKP2R register ***************/
mbed_official 205:c41fc65bcfb4 4057 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 205:c41fc65bcfb4 4058
mbed_official 205:c41fc65bcfb4 4059 /******************** Bits definition for RTC_BKP3R register ***************/
mbed_official 205:c41fc65bcfb4 4060 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 205:c41fc65bcfb4 4061
mbed_official 205:c41fc65bcfb4 4062 /******************** Bits definition for RTC_BKP4R register ***************/
mbed_official 205:c41fc65bcfb4 4063 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 205:c41fc65bcfb4 4064
mbed_official 205:c41fc65bcfb4 4065 /******************** Number of backup registers ******************************/
mbed_official 205:c41fc65bcfb4 4066 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
mbed_official 205:c41fc65bcfb4 4067
mbed_official 205:c41fc65bcfb4 4068 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 4069 /* */
mbed_official 205:c41fc65bcfb4 4070 /* Serial Peripheral Interface (SPI) */
mbed_official 205:c41fc65bcfb4 4071 /* */
mbed_official 205:c41fc65bcfb4 4072 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 4073 /******************* Bit definition for SPI_CR1 register *******************/
mbed_official 205:c41fc65bcfb4 4074 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
mbed_official 205:c41fc65bcfb4 4075 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
mbed_official 205:c41fc65bcfb4 4076 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
mbed_official 205:c41fc65bcfb4 4077 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 205:c41fc65bcfb4 4078 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4079 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4080 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 4081 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
mbed_official 205:c41fc65bcfb4 4082 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
mbed_official 205:c41fc65bcfb4 4083 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
mbed_official 205:c41fc65bcfb4 4084 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
mbed_official 205:c41fc65bcfb4 4085 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
mbed_official 205:c41fc65bcfb4 4086 #define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
mbed_official 205:c41fc65bcfb4 4087 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
mbed_official 205:c41fc65bcfb4 4088 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
mbed_official 205:c41fc65bcfb4 4089 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
mbed_official 205:c41fc65bcfb4 4090 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
mbed_official 205:c41fc65bcfb4 4091
mbed_official 205:c41fc65bcfb4 4092 /******************* Bit definition for SPI_CR2 register *******************/
mbed_official 205:c41fc65bcfb4 4093 #define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
mbed_official 205:c41fc65bcfb4 4094 #define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
mbed_official 205:c41fc65bcfb4 4095 #define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
mbed_official 205:c41fc65bcfb4 4096 #define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
mbed_official 205:c41fc65bcfb4 4097 #define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
mbed_official 205:c41fc65bcfb4 4098 #define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4099 #define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4100 #define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4101 #define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
mbed_official 205:c41fc65bcfb4 4102 #define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4103 #define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4104 #define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 4105 #define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 4106 #define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
mbed_official 205:c41fc65bcfb4 4107 #define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
mbed_official 205:c41fc65bcfb4 4108 #define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
mbed_official 205:c41fc65bcfb4 4109
mbed_official 205:c41fc65bcfb4 4110 /******************** Bit definition for SPI_SR register *******************/
mbed_official 205:c41fc65bcfb4 4111 #define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
mbed_official 205:c41fc65bcfb4 4112 #define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
mbed_official 205:c41fc65bcfb4 4113 #define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */
mbed_official 205:c41fc65bcfb4 4114 #define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */
mbed_official 205:c41fc65bcfb4 4115 #define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
mbed_official 205:c41fc65bcfb4 4116 #define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
mbed_official 205:c41fc65bcfb4 4117 #define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
mbed_official 205:c41fc65bcfb4 4118 #define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
mbed_official 205:c41fc65bcfb4 4119 #define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
mbed_official 205:c41fc65bcfb4 4120 #define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
mbed_official 205:c41fc65bcfb4 4121 #define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4122 #define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4123 #define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
mbed_official 205:c41fc65bcfb4 4124 #define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4125 #define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4126
mbed_official 205:c41fc65bcfb4 4127 /******************** Bit definition for SPI_DR register *******************/
mbed_official 205:c41fc65bcfb4 4128 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
mbed_official 205:c41fc65bcfb4 4129
mbed_official 205:c41fc65bcfb4 4130 /******************* Bit definition for SPI_CRCPR register *****************/
mbed_official 205:c41fc65bcfb4 4131 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
mbed_official 205:c41fc65bcfb4 4132
mbed_official 205:c41fc65bcfb4 4133 /****************** Bit definition for SPI_RXCRCR register *****************/
mbed_official 205:c41fc65bcfb4 4134 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
mbed_official 205:c41fc65bcfb4 4135
mbed_official 205:c41fc65bcfb4 4136 /****************** Bit definition for SPI_TXCRCR register *****************/
mbed_official 205:c41fc65bcfb4 4137 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
mbed_official 205:c41fc65bcfb4 4138
mbed_official 205:c41fc65bcfb4 4139 /****************** Bit definition for SPI_I2SCFGR register ****************/
mbed_official 205:c41fc65bcfb4 4140 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
mbed_official 205:c41fc65bcfb4 4141 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 205:c41fc65bcfb4 4142 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4143 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4144 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
mbed_official 205:c41fc65bcfb4 4145 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 205:c41fc65bcfb4 4146 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4147 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4148 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
mbed_official 205:c41fc65bcfb4 4149 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 205:c41fc65bcfb4 4150 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4151 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4152 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
mbed_official 205:c41fc65bcfb4 4153 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
mbed_official 205:c41fc65bcfb4 4154
mbed_official 205:c41fc65bcfb4 4155 /****************** Bit definition for SPI_I2SPR register ******************/
mbed_official 205:c41fc65bcfb4 4156 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
mbed_official 205:c41fc65bcfb4 4157 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
mbed_official 205:c41fc65bcfb4 4158 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
mbed_official 205:c41fc65bcfb4 4159
mbed_official 205:c41fc65bcfb4 4160 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 4161 /* */
mbed_official 205:c41fc65bcfb4 4162 /* System Configuration (SYSCFG) */
mbed_official 205:c41fc65bcfb4 4163 /* */
mbed_official 205:c41fc65bcfb4 4164 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 4165 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
mbed_official 205:c41fc65bcfb4 4166 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 205:c41fc65bcfb4 4167 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
mbed_official 205:c41fc65bcfb4 4168 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
mbed_official 205:c41fc65bcfb4 4169 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
mbed_official 205:c41fc65bcfb4 4170 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
mbed_official 205:c41fc65bcfb4 4171 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
mbed_official 205:c41fc65bcfb4 4172 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 205:c41fc65bcfb4 4173 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 205:c41fc65bcfb4 4174 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */
mbed_official 205:c41fc65bcfb4 4175 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */
mbed_official 205:c41fc65bcfb4 4176 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 205:c41fc65bcfb4 4177 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 205:c41fc65bcfb4 4178 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 205:c41fc65bcfb4 4179 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 205:c41fc65bcfb4 4180 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
mbed_official 205:c41fc65bcfb4 4181 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
mbed_official 205:c41fc65bcfb4 4182 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap */
mbed_official 205:c41fc65bcfb4 4183 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap */
mbed_official 205:c41fc65bcfb4 4184 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
mbed_official 205:c41fc65bcfb4 4185 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap */
mbed_official 205:c41fc65bcfb4 4186 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap */
mbed_official 205:c41fc65bcfb4 4187 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap */
mbed_official 205:c41fc65bcfb4 4188 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap */
mbed_official 205:c41fc65bcfb4 4189
mbed_official 205:c41fc65bcfb4 4190 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
mbed_official 205:c41fc65bcfb4 4191 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
mbed_official 205:c41fc65bcfb4 4192 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
mbed_official 205:c41fc65bcfb4 4193 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
mbed_official 205:c41fc65bcfb4 4194 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
mbed_official 205:c41fc65bcfb4 4195
mbed_official 205:c41fc65bcfb4 4196 /**
mbed_official 205:c41fc65bcfb4 4197 * @brief EXTI0 configuration
mbed_official 205:c41fc65bcfb4 4198 */
mbed_official 205:c41fc65bcfb4 4199 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
mbed_official 205:c41fc65bcfb4 4200 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
mbed_official 205:c41fc65bcfb4 4201 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
mbed_official 205:c41fc65bcfb4 4202 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
mbed_official 205:c41fc65bcfb4 4203 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
mbed_official 205:c41fc65bcfb4 4204 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
mbed_official 205:c41fc65bcfb4 4205
mbed_official 205:c41fc65bcfb4 4206 /**
mbed_official 205:c41fc65bcfb4 4207 * @brief EXTI1 configuration
mbed_official 205:c41fc65bcfb4 4208 */
mbed_official 205:c41fc65bcfb4 4209 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
mbed_official 205:c41fc65bcfb4 4210 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
mbed_official 205:c41fc65bcfb4 4211 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
mbed_official 205:c41fc65bcfb4 4212 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
mbed_official 205:c41fc65bcfb4 4213 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
mbed_official 205:c41fc65bcfb4 4214 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
mbed_official 205:c41fc65bcfb4 4215
mbed_official 205:c41fc65bcfb4 4216 /**
mbed_official 205:c41fc65bcfb4 4217 * @brief EXTI2 configuration
mbed_official 205:c41fc65bcfb4 4218 */
mbed_official 205:c41fc65bcfb4 4219 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
mbed_official 205:c41fc65bcfb4 4220 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
mbed_official 205:c41fc65bcfb4 4221 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
mbed_official 205:c41fc65bcfb4 4222 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
mbed_official 205:c41fc65bcfb4 4223 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
mbed_official 205:c41fc65bcfb4 4224 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
mbed_official 205:c41fc65bcfb4 4225
mbed_official 205:c41fc65bcfb4 4226 /**
mbed_official 205:c41fc65bcfb4 4227 * @brief EXTI3 configuration
mbed_official 205:c41fc65bcfb4 4228 */
mbed_official 205:c41fc65bcfb4 4229 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
mbed_official 205:c41fc65bcfb4 4230 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
mbed_official 205:c41fc65bcfb4 4231 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
mbed_official 205:c41fc65bcfb4 4232 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
mbed_official 205:c41fc65bcfb4 4233 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
mbed_official 205:c41fc65bcfb4 4234 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
mbed_official 205:c41fc65bcfb4 4235
mbed_official 205:c41fc65bcfb4 4236 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
mbed_official 205:c41fc65bcfb4 4237 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
mbed_official 205:c41fc65bcfb4 4238 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
mbed_official 205:c41fc65bcfb4 4239 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
mbed_official 205:c41fc65bcfb4 4240 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
mbed_official 205:c41fc65bcfb4 4241
mbed_official 205:c41fc65bcfb4 4242 /**
mbed_official 205:c41fc65bcfb4 4243 * @brief EXTI4 configuration
mbed_official 205:c41fc65bcfb4 4244 */
mbed_official 205:c41fc65bcfb4 4245 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
mbed_official 205:c41fc65bcfb4 4246 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
mbed_official 205:c41fc65bcfb4 4247 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
mbed_official 205:c41fc65bcfb4 4248 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
mbed_official 205:c41fc65bcfb4 4249 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
mbed_official 205:c41fc65bcfb4 4250 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
mbed_official 205:c41fc65bcfb4 4251
mbed_official 205:c41fc65bcfb4 4252 /**
mbed_official 205:c41fc65bcfb4 4253 * @brief EXTI5 configuration
mbed_official 205:c41fc65bcfb4 4254 */
mbed_official 205:c41fc65bcfb4 4255 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
mbed_official 205:c41fc65bcfb4 4256 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
mbed_official 205:c41fc65bcfb4 4257 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
mbed_official 205:c41fc65bcfb4 4258 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
mbed_official 205:c41fc65bcfb4 4259 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
mbed_official 205:c41fc65bcfb4 4260 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
mbed_official 205:c41fc65bcfb4 4261
mbed_official 205:c41fc65bcfb4 4262 /**
mbed_official 205:c41fc65bcfb4 4263 * @brief EXTI6 configuration
mbed_official 205:c41fc65bcfb4 4264 */
mbed_official 205:c41fc65bcfb4 4265 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
mbed_official 205:c41fc65bcfb4 4266 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
mbed_official 205:c41fc65bcfb4 4267 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
mbed_official 205:c41fc65bcfb4 4268 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
mbed_official 205:c41fc65bcfb4 4269 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
mbed_official 205:c41fc65bcfb4 4270 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
mbed_official 205:c41fc65bcfb4 4271
mbed_official 205:c41fc65bcfb4 4272 /**
mbed_official 205:c41fc65bcfb4 4273 * @brief EXTI7 configuration
mbed_official 205:c41fc65bcfb4 4274 */
mbed_official 205:c41fc65bcfb4 4275 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
mbed_official 205:c41fc65bcfb4 4276 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
mbed_official 205:c41fc65bcfb4 4277 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
mbed_official 205:c41fc65bcfb4 4278 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
mbed_official 205:c41fc65bcfb4 4279 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
mbed_official 205:c41fc65bcfb4 4280 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
mbed_official 205:c41fc65bcfb4 4281
mbed_official 205:c41fc65bcfb4 4282 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
mbed_official 205:c41fc65bcfb4 4283 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
mbed_official 205:c41fc65bcfb4 4284 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
mbed_official 205:c41fc65bcfb4 4285 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
mbed_official 205:c41fc65bcfb4 4286 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
mbed_official 205:c41fc65bcfb4 4287
mbed_official 205:c41fc65bcfb4 4288 /**
mbed_official 205:c41fc65bcfb4 4289 * @brief EXTI8 configuration
mbed_official 205:c41fc65bcfb4 4290 */
mbed_official 205:c41fc65bcfb4 4291 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
mbed_official 205:c41fc65bcfb4 4292 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
mbed_official 205:c41fc65bcfb4 4293 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
mbed_official 205:c41fc65bcfb4 4294 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
mbed_official 205:c41fc65bcfb4 4295 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
mbed_official 205:c41fc65bcfb4 4296
mbed_official 205:c41fc65bcfb4 4297 /**
mbed_official 205:c41fc65bcfb4 4298 * @brief EXTI9 configuration
mbed_official 205:c41fc65bcfb4 4299 */
mbed_official 205:c41fc65bcfb4 4300 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
mbed_official 205:c41fc65bcfb4 4301 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
mbed_official 205:c41fc65bcfb4 4302 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
mbed_official 205:c41fc65bcfb4 4303 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
mbed_official 205:c41fc65bcfb4 4304 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
mbed_official 205:c41fc65bcfb4 4305 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
mbed_official 205:c41fc65bcfb4 4306
mbed_official 205:c41fc65bcfb4 4307 /**
mbed_official 205:c41fc65bcfb4 4308 * @brief EXTI10 configuration
mbed_official 205:c41fc65bcfb4 4309 */
mbed_official 205:c41fc65bcfb4 4310 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
mbed_official 205:c41fc65bcfb4 4311 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
mbed_official 205:c41fc65bcfb4 4312 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
mbed_official 205:c41fc65bcfb4 4313 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
mbed_official 205:c41fc65bcfb4 4314 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
mbed_official 205:c41fc65bcfb4 4315 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
mbed_official 205:c41fc65bcfb4 4316
mbed_official 205:c41fc65bcfb4 4317 /**
mbed_official 205:c41fc65bcfb4 4318 * @brief EXTI11 configuration
mbed_official 205:c41fc65bcfb4 4319 */
mbed_official 205:c41fc65bcfb4 4320 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
mbed_official 205:c41fc65bcfb4 4321 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
mbed_official 205:c41fc65bcfb4 4322 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
mbed_official 205:c41fc65bcfb4 4323 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
mbed_official 205:c41fc65bcfb4 4324 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
mbed_official 205:c41fc65bcfb4 4325
mbed_official 205:c41fc65bcfb4 4326 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
mbed_official 205:c41fc65bcfb4 4327 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
mbed_official 205:c41fc65bcfb4 4328 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
mbed_official 205:c41fc65bcfb4 4329 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
mbed_official 205:c41fc65bcfb4 4330 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
mbed_official 205:c41fc65bcfb4 4331
mbed_official 205:c41fc65bcfb4 4332 /**
mbed_official 205:c41fc65bcfb4 4333 * @brief EXTI12 configuration
mbed_official 205:c41fc65bcfb4 4334 */
mbed_official 205:c41fc65bcfb4 4335 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
mbed_official 205:c41fc65bcfb4 4336 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
mbed_official 205:c41fc65bcfb4 4337 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
mbed_official 205:c41fc65bcfb4 4338 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
mbed_official 205:c41fc65bcfb4 4339 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
mbed_official 205:c41fc65bcfb4 4340
mbed_official 205:c41fc65bcfb4 4341 /**
mbed_official 205:c41fc65bcfb4 4342 * @brief EXTI13 configuration
mbed_official 205:c41fc65bcfb4 4343 */
mbed_official 205:c41fc65bcfb4 4344 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
mbed_official 205:c41fc65bcfb4 4345 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
mbed_official 205:c41fc65bcfb4 4346 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
mbed_official 205:c41fc65bcfb4 4347 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
mbed_official 205:c41fc65bcfb4 4348 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
mbed_official 205:c41fc65bcfb4 4349
mbed_official 205:c41fc65bcfb4 4350 /**
mbed_official 205:c41fc65bcfb4 4351 * @brief EXTI14 configuration
mbed_official 205:c41fc65bcfb4 4352 */
mbed_official 205:c41fc65bcfb4 4353 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
mbed_official 205:c41fc65bcfb4 4354 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
mbed_official 205:c41fc65bcfb4 4355 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
mbed_official 205:c41fc65bcfb4 4356 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
mbed_official 205:c41fc65bcfb4 4357 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
mbed_official 205:c41fc65bcfb4 4358
mbed_official 205:c41fc65bcfb4 4359 /**
mbed_official 205:c41fc65bcfb4 4360 * @brief EXTI15 configuration
mbed_official 205:c41fc65bcfb4 4361 */
mbed_official 205:c41fc65bcfb4 4362 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
mbed_official 205:c41fc65bcfb4 4363 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
mbed_official 205:c41fc65bcfb4 4364 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
mbed_official 205:c41fc65bcfb4 4365 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
mbed_official 205:c41fc65bcfb4 4366 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
mbed_official 205:c41fc65bcfb4 4367
mbed_official 205:c41fc65bcfb4 4368 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
mbed_official 205:c41fc65bcfb4 4369 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
mbed_official 205:c41fc65bcfb4 4370 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
mbed_official 205:c41fc65bcfb4 4371 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
mbed_official 205:c41fc65bcfb4 4372 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 205:c41fc65bcfb4 4373 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
mbed_official 205:c41fc65bcfb4 4374
mbed_official 205:c41fc65bcfb4 4375 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 4376 /* */
mbed_official 205:c41fc65bcfb4 4377 /* Timers (TIM) */
mbed_official 205:c41fc65bcfb4 4378 /* */
mbed_official 205:c41fc65bcfb4 4379 /*****************************************************************************/
mbed_official 205:c41fc65bcfb4 4380 /******************* Bit definition for TIM_CR1 register *******************/
mbed_official 205:c41fc65bcfb4 4381 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
mbed_official 205:c41fc65bcfb4 4382 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
mbed_official 205:c41fc65bcfb4 4383 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
mbed_official 205:c41fc65bcfb4 4384 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
mbed_official 205:c41fc65bcfb4 4385 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
mbed_official 205:c41fc65bcfb4 4386
mbed_official 205:c41fc65bcfb4 4387 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 205:c41fc65bcfb4 4388 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4389 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4390
mbed_official 205:c41fc65bcfb4 4391 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 205:c41fc65bcfb4 4392
mbed_official 205:c41fc65bcfb4 4393 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 205:c41fc65bcfb4 4394 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4395 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4396
mbed_official 205:c41fc65bcfb4 4397 /******************* Bit definition for TIM_CR2 register *******************/
mbed_official 205:c41fc65bcfb4 4398 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 205:c41fc65bcfb4 4399 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 205:c41fc65bcfb4 4400 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 205:c41fc65bcfb4 4401
mbed_official 205:c41fc65bcfb4 4402 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 205:c41fc65bcfb4 4403 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4404 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4405 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4406
mbed_official 205:c41fc65bcfb4 4407 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
mbed_official 205:c41fc65bcfb4 4408 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 205:c41fc65bcfb4 4409 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 205:c41fc65bcfb4 4410 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 205:c41fc65bcfb4 4411 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 205:c41fc65bcfb4 4412 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 205:c41fc65bcfb4 4413 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 205:c41fc65bcfb4 4414 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 205:c41fc65bcfb4 4415
mbed_official 205:c41fc65bcfb4 4416 /******************* Bit definition for TIM_SMCR register ******************/
mbed_official 205:c41fc65bcfb4 4417 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 205:c41fc65bcfb4 4418 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4419 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4420 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4421
mbed_official 205:c41fc65bcfb4 4422 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */
mbed_official 205:c41fc65bcfb4 4423
mbed_official 205:c41fc65bcfb4 4424 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 205:c41fc65bcfb4 4425 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4426 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4427 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4428
mbed_official 205:c41fc65bcfb4 4429 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
mbed_official 205:c41fc65bcfb4 4430
mbed_official 205:c41fc65bcfb4 4431 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 205:c41fc65bcfb4 4432 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4433 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4434 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4435 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4436
mbed_official 205:c41fc65bcfb4 4437 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 205:c41fc65bcfb4 4438 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4439 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4440
mbed_official 205:c41fc65bcfb4 4441 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
mbed_official 205:c41fc65bcfb4 4442 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
mbed_official 205:c41fc65bcfb4 4443
mbed_official 205:c41fc65bcfb4 4444 /******************* Bit definition for TIM_DIER register ******************/
mbed_official 205:c41fc65bcfb4 4445 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
mbed_official 205:c41fc65bcfb4 4446 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 205:c41fc65bcfb4 4447 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 205:c41fc65bcfb4 4448 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 205:c41fc65bcfb4 4449 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 205:c41fc65bcfb4 4450 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
mbed_official 205:c41fc65bcfb4 4451 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 205:c41fc65bcfb4 4452 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
mbed_official 205:c41fc65bcfb4 4453 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
mbed_official 205:c41fc65bcfb4 4454 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 205:c41fc65bcfb4 4455 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 205:c41fc65bcfb4 4456 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 205:c41fc65bcfb4 4457 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 205:c41fc65bcfb4 4458 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
mbed_official 205:c41fc65bcfb4 4459 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 205:c41fc65bcfb4 4460
mbed_official 205:c41fc65bcfb4 4461 /******************** Bit definition for TIM_SR register *******************/
mbed_official 205:c41fc65bcfb4 4462 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
mbed_official 205:c41fc65bcfb4 4463 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 205:c41fc65bcfb4 4464 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 205:c41fc65bcfb4 4465 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 205:c41fc65bcfb4 4466 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 205:c41fc65bcfb4 4467 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
mbed_official 205:c41fc65bcfb4 4468 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 205:c41fc65bcfb4 4469 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
mbed_official 205:c41fc65bcfb4 4470 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 205:c41fc65bcfb4 4471 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 205:c41fc65bcfb4 4472 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 205:c41fc65bcfb4 4473 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 205:c41fc65bcfb4 4474
mbed_official 205:c41fc65bcfb4 4475 /******************* Bit definition for TIM_EGR register *******************/
mbed_official 205:c41fc65bcfb4 4476 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
mbed_official 205:c41fc65bcfb4 4477 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 205:c41fc65bcfb4 4478 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 205:c41fc65bcfb4 4479 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 205:c41fc65bcfb4 4480 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 205:c41fc65bcfb4 4481 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 205:c41fc65bcfb4 4482 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
mbed_official 205:c41fc65bcfb4 4483 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
mbed_official 205:c41fc65bcfb4 4484
mbed_official 205:c41fc65bcfb4 4485 /****************** Bit definition for TIM_CCMR1 register ******************/
mbed_official 205:c41fc65bcfb4 4486 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 205:c41fc65bcfb4 4487 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4488 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4489
mbed_official 205:c41fc65bcfb4 4490 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 205:c41fc65bcfb4 4491 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 205:c41fc65bcfb4 4492
mbed_official 205:c41fc65bcfb4 4493 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 205:c41fc65bcfb4 4494 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4495 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4496 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4497
mbed_official 205:c41fc65bcfb4 4498 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 205:c41fc65bcfb4 4499
mbed_official 205:c41fc65bcfb4 4500 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 205:c41fc65bcfb4 4501 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4502 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4503
mbed_official 205:c41fc65bcfb4 4504 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 205:c41fc65bcfb4 4505 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 205:c41fc65bcfb4 4506
mbed_official 205:c41fc65bcfb4 4507 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 205:c41fc65bcfb4 4508 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4509 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4510 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4511
mbed_official 205:c41fc65bcfb4 4512 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 205:c41fc65bcfb4 4513
mbed_official 205:c41fc65bcfb4 4514 /*---------------------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 4515
mbed_official 205:c41fc65bcfb4 4516 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 205:c41fc65bcfb4 4517 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4518 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4519
mbed_official 205:c41fc65bcfb4 4520 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 205:c41fc65bcfb4 4521 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4522 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4523 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4524 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4525
mbed_official 205:c41fc65bcfb4 4526 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 205:c41fc65bcfb4 4527 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4528 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4529
mbed_official 205:c41fc65bcfb4 4530 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 205:c41fc65bcfb4 4531 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4532 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4533 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4534 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4535
mbed_official 205:c41fc65bcfb4 4536 /****************** Bit definition for TIM_CCMR2 register ******************/
mbed_official 205:c41fc65bcfb4 4537 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 205:c41fc65bcfb4 4538 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4539 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4540
mbed_official 205:c41fc65bcfb4 4541 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 205:c41fc65bcfb4 4542 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 205:c41fc65bcfb4 4543
mbed_official 205:c41fc65bcfb4 4544 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 205:c41fc65bcfb4 4545 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4546 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4547 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4548
mbed_official 205:c41fc65bcfb4 4549 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 205:c41fc65bcfb4 4550
mbed_official 205:c41fc65bcfb4 4551 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 205:c41fc65bcfb4 4552 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4553 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4554
mbed_official 205:c41fc65bcfb4 4555 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 205:c41fc65bcfb4 4556 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 205:c41fc65bcfb4 4557
mbed_official 205:c41fc65bcfb4 4558 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 205:c41fc65bcfb4 4559 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4560 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4561 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4562
mbed_official 205:c41fc65bcfb4 4563 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 205:c41fc65bcfb4 4564
mbed_official 205:c41fc65bcfb4 4565 /*---------------------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 4566
mbed_official 205:c41fc65bcfb4 4567 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 205:c41fc65bcfb4 4568 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4569 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4570
mbed_official 205:c41fc65bcfb4 4571 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 205:c41fc65bcfb4 4572 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4573 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4574 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4575 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4576
mbed_official 205:c41fc65bcfb4 4577 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 205:c41fc65bcfb4 4578 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4579 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4580
mbed_official 205:c41fc65bcfb4 4581 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 205:c41fc65bcfb4 4582 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4583 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4584 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4585 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4586
mbed_official 205:c41fc65bcfb4 4587 /******************* Bit definition for TIM_CCER register ******************/
mbed_official 205:c41fc65bcfb4 4588 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 205:c41fc65bcfb4 4589 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 205:c41fc65bcfb4 4590 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 205:c41fc65bcfb4 4591 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 205:c41fc65bcfb4 4592 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 205:c41fc65bcfb4 4593 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 205:c41fc65bcfb4 4594 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 205:c41fc65bcfb4 4595 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 205:c41fc65bcfb4 4596 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 205:c41fc65bcfb4 4597 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 205:c41fc65bcfb4 4598 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 205:c41fc65bcfb4 4599 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 205:c41fc65bcfb4 4600 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 205:c41fc65bcfb4 4601 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 205:c41fc65bcfb4 4602 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 205:c41fc65bcfb4 4603
mbed_official 205:c41fc65bcfb4 4604 /******************* Bit definition for TIM_CNT register *******************/
mbed_official 205:c41fc65bcfb4 4605 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
mbed_official 205:c41fc65bcfb4 4606
mbed_official 205:c41fc65bcfb4 4607 /******************* Bit definition for TIM_PSC register *******************/
mbed_official 205:c41fc65bcfb4 4608 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
mbed_official 205:c41fc65bcfb4 4609
mbed_official 205:c41fc65bcfb4 4610 /******************* Bit definition for TIM_ARR register *******************/
mbed_official 205:c41fc65bcfb4 4611 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 205:c41fc65bcfb4 4612
mbed_official 205:c41fc65bcfb4 4613 /******************* Bit definition for TIM_RCR register *******************/
mbed_official 205:c41fc65bcfb4 4614 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
mbed_official 205:c41fc65bcfb4 4615
mbed_official 205:c41fc65bcfb4 4616 /******************* Bit definition for TIM_CCR1 register ******************/
mbed_official 205:c41fc65bcfb4 4617 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 205:c41fc65bcfb4 4618
mbed_official 205:c41fc65bcfb4 4619 /******************* Bit definition for TIM_CCR2 register ******************/
mbed_official 205:c41fc65bcfb4 4620 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 205:c41fc65bcfb4 4621
mbed_official 205:c41fc65bcfb4 4622 /******************* Bit definition for TIM_CCR3 register ******************/
mbed_official 205:c41fc65bcfb4 4623 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 205:c41fc65bcfb4 4624
mbed_official 205:c41fc65bcfb4 4625 /******************* Bit definition for TIM_CCR4 register ******************/
mbed_official 205:c41fc65bcfb4 4626 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 205:c41fc65bcfb4 4627
mbed_official 205:c41fc65bcfb4 4628 /******************* Bit definition for TIM_BDTR register ******************/
mbed_official 205:c41fc65bcfb4 4629 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 205:c41fc65bcfb4 4630 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4631 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4632 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4633 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4634 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 4635 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
mbed_official 205:c41fc65bcfb4 4636 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
mbed_official 205:c41fc65bcfb4 4637 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
mbed_official 205:c41fc65bcfb4 4638
mbed_official 205:c41fc65bcfb4 4639 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 205:c41fc65bcfb4 4640 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4641 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4642
mbed_official 205:c41fc65bcfb4 4643 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 205:c41fc65bcfb4 4644 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 205:c41fc65bcfb4 4645 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
mbed_official 205:c41fc65bcfb4 4646 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
mbed_official 205:c41fc65bcfb4 4647 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
mbed_official 205:c41fc65bcfb4 4648 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
mbed_official 205:c41fc65bcfb4 4649
mbed_official 205:c41fc65bcfb4 4650 /******************* Bit definition for TIM_DCR register *******************/
mbed_official 205:c41fc65bcfb4 4651 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 205:c41fc65bcfb4 4652 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4653 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4654 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4655 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4656 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 4657
mbed_official 205:c41fc65bcfb4 4658 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 205:c41fc65bcfb4 4659 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4660 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4661 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4662 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4663 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 4664
mbed_official 205:c41fc65bcfb4 4665 /******************* Bit definition for TIM_DMAR register ******************/
mbed_official 205:c41fc65bcfb4 4666 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 205:c41fc65bcfb4 4667
mbed_official 205:c41fc65bcfb4 4668 /******************* Bit definition for TIM_OR register ********************/
mbed_official 205:c41fc65bcfb4 4669 #define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
mbed_official 205:c41fc65bcfb4 4670 #define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4671 #define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4672
mbed_official 205:c41fc65bcfb4 4673 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 4674 /* */
mbed_official 205:c41fc65bcfb4 4675 /* Touch Sensing Controller (TSC) */
mbed_official 205:c41fc65bcfb4 4676 /* */
mbed_official 205:c41fc65bcfb4 4677 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 4678 /******************* Bit definition for TSC_CR register *********************/
mbed_official 205:c41fc65bcfb4 4679 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
mbed_official 205:c41fc65bcfb4 4680 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
mbed_official 205:c41fc65bcfb4 4681 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
mbed_official 205:c41fc65bcfb4 4682 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
mbed_official 205:c41fc65bcfb4 4683 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
mbed_official 205:c41fc65bcfb4 4684
mbed_official 205:c41fc65bcfb4 4685 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 205:c41fc65bcfb4 4686 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4687 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4688 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4689
mbed_official 205:c41fc65bcfb4 4690 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 205:c41fc65bcfb4 4691 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4692 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4693 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4694
mbed_official 205:c41fc65bcfb4 4695 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
mbed_official 205:c41fc65bcfb4 4696 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
mbed_official 205:c41fc65bcfb4 4697
mbed_official 205:c41fc65bcfb4 4698 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 205:c41fc65bcfb4 4699 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4700 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4701 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4702 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4703 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 4704 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 205:c41fc65bcfb4 4705 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 205:c41fc65bcfb4 4706
mbed_official 205:c41fc65bcfb4 4707 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 205:c41fc65bcfb4 4708 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4709 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4710 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4711 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4712
mbed_official 205:c41fc65bcfb4 4713 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 205:c41fc65bcfb4 4714 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 4715 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 4716 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 4717 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 4718
mbed_official 205:c41fc65bcfb4 4719 /******************* Bit definition for TSC_IER register ********************/
mbed_official 205:c41fc65bcfb4 4720 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
mbed_official 205:c41fc65bcfb4 4721 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
mbed_official 205:c41fc65bcfb4 4722
mbed_official 205:c41fc65bcfb4 4723 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 205:c41fc65bcfb4 4724 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
mbed_official 205:c41fc65bcfb4 4725 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
mbed_official 205:c41fc65bcfb4 4726
mbed_official 205:c41fc65bcfb4 4727 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 205:c41fc65bcfb4 4728 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
mbed_official 205:c41fc65bcfb4 4729 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
mbed_official 205:c41fc65bcfb4 4730
mbed_official 205:c41fc65bcfb4 4731 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 205:c41fc65bcfb4 4732 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4733 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4734 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4735 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4736 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4737 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4738 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4739 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4740 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4741 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4742 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4743 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4744 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4745 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4746 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4747 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4748 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4749 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4750 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4751 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4752 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4753 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4754 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4755 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4756 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4757 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4758 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4759 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4760 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4761 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4762 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4763 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
mbed_official 205:c41fc65bcfb4 4764
mbed_official 205:c41fc65bcfb4 4765 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 205:c41fc65bcfb4 4766 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4767 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4768 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4769 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4770 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4771 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4772 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4773 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4774 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4775 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4776 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4777 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4778 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4779 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4780 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4781 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4782 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4783 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4784 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4785 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4786 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4787 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4788 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4789 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4790 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4791 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4792 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4793 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4794 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
mbed_official 205:c41fc65bcfb4 4795 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
mbed_official 205:c41fc65bcfb4 4796 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
mbed_official 205:c41fc65bcfb4 4797 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
mbed_official 205:c41fc65bcfb4 4798
mbed_official 205:c41fc65bcfb4 4799 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 205:c41fc65bcfb4 4800 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4801 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4802 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4803 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4804 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4805 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4806 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4807 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4808 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4809 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4810 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4811 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4812 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4813 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4814 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4815 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4816 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4817 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4818 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4819 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4820 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4821 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4822 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4823 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4824 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4825 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4826 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4827 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4828 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
mbed_official 205:c41fc65bcfb4 4829 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
mbed_official 205:c41fc65bcfb4 4830 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
mbed_official 205:c41fc65bcfb4 4831 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
mbed_official 205:c41fc65bcfb4 4832
mbed_official 205:c41fc65bcfb4 4833 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 205:c41fc65bcfb4 4834 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4835 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4836 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4837 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4838 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4839 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4840 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4841 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4842 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4843 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4844 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4845 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4846 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4847 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4848 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4849 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4850 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4851 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4852 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4853 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4854 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4855 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4856 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4857 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4858 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4859 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4860 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4861 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4862 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
mbed_official 205:c41fc65bcfb4 4863 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
mbed_official 205:c41fc65bcfb4 4864 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
mbed_official 205:c41fc65bcfb4 4865 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
mbed_official 205:c41fc65bcfb4 4866
mbed_official 205:c41fc65bcfb4 4867 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 205:c41fc65bcfb4 4868 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
mbed_official 205:c41fc65bcfb4 4869 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
mbed_official 205:c41fc65bcfb4 4870 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
mbed_official 205:c41fc65bcfb4 4871 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
mbed_official 205:c41fc65bcfb4 4872 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
mbed_official 205:c41fc65bcfb4 4873 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
mbed_official 205:c41fc65bcfb4 4874 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
mbed_official 205:c41fc65bcfb4 4875 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
mbed_official 205:c41fc65bcfb4 4876 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
mbed_official 205:c41fc65bcfb4 4877 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
mbed_official 205:c41fc65bcfb4 4878 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
mbed_official 205:c41fc65bcfb4 4879 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
mbed_official 205:c41fc65bcfb4 4880 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
mbed_official 205:c41fc65bcfb4 4881 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
mbed_official 205:c41fc65bcfb4 4882 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
mbed_official 205:c41fc65bcfb4 4883 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
mbed_official 205:c41fc65bcfb4 4884
mbed_official 205:c41fc65bcfb4 4885 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 205:c41fc65bcfb4 4886 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
mbed_official 205:c41fc65bcfb4 4887
mbed_official 205:c41fc65bcfb4 4888 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 4889 /* */
mbed_official 205:c41fc65bcfb4 4890 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 205:c41fc65bcfb4 4891 /* */
mbed_official 205:c41fc65bcfb4 4892 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 4893 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 205:c41fc65bcfb4 4894 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 205:c41fc65bcfb4 4895 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 205:c41fc65bcfb4 4896 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 205:c41fc65bcfb4 4897 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 205:c41fc65bcfb4 4898 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4899 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4900 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4901 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4902 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4903 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 205:c41fc65bcfb4 4904 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 205:c41fc65bcfb4 4905 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 205:c41fc65bcfb4 4906 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
mbed_official 205:c41fc65bcfb4 4907 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 205:c41fc65bcfb4 4908 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 205:c41fc65bcfb4 4909 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 205:c41fc65bcfb4 4910 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 205:c41fc65bcfb4 4911 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4912 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4913 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 4914 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 4915 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 205:c41fc65bcfb4 4916 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 205:c41fc65bcfb4 4917 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4918 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4919 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 4920 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 205:c41fc65bcfb4 4921 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 205:c41fc65bcfb4 4922 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 205:c41fc65bcfb4 4923 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 205:c41fc65bcfb4 4924 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
mbed_official 205:c41fc65bcfb4 4925 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
mbed_official 205:c41fc65bcfb4 4926
mbed_official 205:c41fc65bcfb4 4927 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 205:c41fc65bcfb4 4928 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 205:c41fc65bcfb4 4929 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 205:c41fc65bcfb4 4930 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4931 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 205:c41fc65bcfb4 4932 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 205:c41fc65bcfb4 4933 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 205:c41fc65bcfb4 4934 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 205:c41fc65bcfb4 4935 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 205:c41fc65bcfb4 4936 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4937 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4938 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 205:c41fc65bcfb4 4939 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 205:c41fc65bcfb4 4940 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 205:c41fc65bcfb4 4941 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 205:c41fc65bcfb4 4942 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 205:c41fc65bcfb4 4943 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 205:c41fc65bcfb4 4944 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 205:c41fc65bcfb4 4945 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 205:c41fc65bcfb4 4946 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4947 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4948 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 205:c41fc65bcfb4 4949 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 205:c41fc65bcfb4 4950
mbed_official 205:c41fc65bcfb4 4951 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 205:c41fc65bcfb4 4952 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4953 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 205:c41fc65bcfb4 4954 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 205:c41fc65bcfb4 4955 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 205:c41fc65bcfb4 4956 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 205:c41fc65bcfb4 4957 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 205:c41fc65bcfb4 4958 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 205:c41fc65bcfb4 4959 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 205:c41fc65bcfb4 4960 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 205:c41fc65bcfb4 4961 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 205:c41fc65bcfb4 4962 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4963 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 205:c41fc65bcfb4 4964 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 205:c41fc65bcfb4 4965 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 205:c41fc65bcfb4 4966 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 205:c41fc65bcfb4 4967 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 205:c41fc65bcfb4 4968 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 205:c41fc65bcfb4 4969 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4970 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4971 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 205:c41fc65bcfb4 4972 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 205:c41fc65bcfb4 4973 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 205:c41fc65bcfb4 4974 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 205:c41fc65bcfb4 4975 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 205:c41fc65bcfb4 4976
mbed_official 205:c41fc65bcfb4 4977 /****************** Bit definition for USART_BRR register *******************/
mbed_official 205:c41fc65bcfb4 4978 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
mbed_official 205:c41fc65bcfb4 4979 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
mbed_official 205:c41fc65bcfb4 4980
mbed_official 205:c41fc65bcfb4 4981 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 205:c41fc65bcfb4 4982 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 205:c41fc65bcfb4 4983 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 205:c41fc65bcfb4 4984
mbed_official 205:c41fc65bcfb4 4985
mbed_official 205:c41fc65bcfb4 4986 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 205:c41fc65bcfb4 4987 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 205:c41fc65bcfb4 4988 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 205:c41fc65bcfb4 4989
mbed_official 205:c41fc65bcfb4 4990 /******************* Bit definition for USART_RQR register ******************/
mbed_official 205:c41fc65bcfb4 4991 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
mbed_official 205:c41fc65bcfb4 4992 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
mbed_official 205:c41fc65bcfb4 4993 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
mbed_official 205:c41fc65bcfb4 4994 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
mbed_official 205:c41fc65bcfb4 4995 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
mbed_official 205:c41fc65bcfb4 4996
mbed_official 205:c41fc65bcfb4 4997 /******************* Bit definition for USART_ISR register ******************/
mbed_official 205:c41fc65bcfb4 4998 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 205:c41fc65bcfb4 4999 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 205:c41fc65bcfb4 5000 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 205:c41fc65bcfb4 5001 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 205:c41fc65bcfb4 5002 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 205:c41fc65bcfb4 5003 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 205:c41fc65bcfb4 5004 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 205:c41fc65bcfb4 5005 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 205:c41fc65bcfb4 5006 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 205:c41fc65bcfb4 5007 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 205:c41fc65bcfb4 5008 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 205:c41fc65bcfb4 5009 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 205:c41fc65bcfb4 5010 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 205:c41fc65bcfb4 5011 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 205:c41fc65bcfb4 5012 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 205:c41fc65bcfb4 5013 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 205:c41fc65bcfb4 5014 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 205:c41fc65bcfb4 5015 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 205:c41fc65bcfb4 5016 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 205:c41fc65bcfb4 5017 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 205:c41fc65bcfb4 5018 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 205:c41fc65bcfb4 5019 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 205:c41fc65bcfb4 5020
mbed_official 205:c41fc65bcfb4 5021 /******************* Bit definition for USART_ICR register ******************/
mbed_official 205:c41fc65bcfb4 5022 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 205:c41fc65bcfb4 5023 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 205:c41fc65bcfb4 5024 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 205:c41fc65bcfb4 5025 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 205:c41fc65bcfb4 5026 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 205:c41fc65bcfb4 5027 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 205:c41fc65bcfb4 5028 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 205:c41fc65bcfb4 5029 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 205:c41fc65bcfb4 5030 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 205:c41fc65bcfb4 5031 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 205:c41fc65bcfb4 5032 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 205:c41fc65bcfb4 5033 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 205:c41fc65bcfb4 5034
mbed_official 205:c41fc65bcfb4 5035 /******************* Bit definition for USART_RDR register ******************/
mbed_official 205:c41fc65bcfb4 5036 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 205:c41fc65bcfb4 5037
mbed_official 205:c41fc65bcfb4 5038 /******************* Bit definition for USART_TDR register ******************/
mbed_official 205:c41fc65bcfb4 5039 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 205:c41fc65bcfb4 5040
mbed_official 205:c41fc65bcfb4 5041 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 5042 /* */
mbed_official 205:c41fc65bcfb4 5043 /* USB Device General registers */
mbed_official 205:c41fc65bcfb4 5044 /* */
mbed_official 205:c41fc65bcfb4 5045 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 5046 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
mbed_official 205:c41fc65bcfb4 5047 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
mbed_official 205:c41fc65bcfb4 5048 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
mbed_official 205:c41fc65bcfb4 5049 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
mbed_official 205:c41fc65bcfb4 5050 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
mbed_official 205:c41fc65bcfb4 5051 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
mbed_official 205:c41fc65bcfb4 5052 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
mbed_official 205:c41fc65bcfb4 5053
mbed_official 205:c41fc65bcfb4 5054 /**************************** ISTR interrupt events *************************/
mbed_official 205:c41fc65bcfb4 5055 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5056 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5057 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5058 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5059 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5060 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5061 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5062 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
mbed_official 205:c41fc65bcfb4 5063 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
mbed_official 205:c41fc65bcfb4 5064 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
mbed_official 205:c41fc65bcfb4 5065 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
mbed_official 205:c41fc65bcfb4 5066
mbed_official 205:c41fc65bcfb4 5067 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 205:c41fc65bcfb4 5068 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 205:c41fc65bcfb4 5069 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 205:c41fc65bcfb4 5070 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 205:c41fc65bcfb4 5071 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 205:c41fc65bcfb4 5072 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 205:c41fc65bcfb4 5073 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 205:c41fc65bcfb4 5074 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 205:c41fc65bcfb4 5075 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
mbed_official 205:c41fc65bcfb4 5076
mbed_official 205:c41fc65bcfb4 5077 /************************* CNTR control register bits definitions ***********/
mbed_official 205:c41fc65bcfb4 5078 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
mbed_official 205:c41fc65bcfb4 5079 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
mbed_official 205:c41fc65bcfb4 5080 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
mbed_official 205:c41fc65bcfb4 5081 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
mbed_official 205:c41fc65bcfb4 5082 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
mbed_official 205:c41fc65bcfb4 5083 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
mbed_official 205:c41fc65bcfb4 5084 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
mbed_official 205:c41fc65bcfb4 5085 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
mbed_official 205:c41fc65bcfb4 5086 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
mbed_official 205:c41fc65bcfb4 5087 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
mbed_official 205:c41fc65bcfb4 5088 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
mbed_official 205:c41fc65bcfb4 5089 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
mbed_official 205:c41fc65bcfb4 5090 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
mbed_official 205:c41fc65bcfb4 5091 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
mbed_official 205:c41fc65bcfb4 5092 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
mbed_official 205:c41fc65bcfb4 5093
mbed_official 205:c41fc65bcfb4 5094 /************************* BCDR control register bits definitions ***********/
mbed_official 205:c41fc65bcfb4 5095 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
mbed_official 205:c41fc65bcfb4 5096 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
mbed_official 205:c41fc65bcfb4 5097 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
mbed_official 205:c41fc65bcfb4 5098 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
mbed_official 205:c41fc65bcfb4 5099 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
mbed_official 205:c41fc65bcfb4 5100 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
mbed_official 205:c41fc65bcfb4 5101 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
mbed_official 205:c41fc65bcfb4 5102 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
mbed_official 205:c41fc65bcfb4 5103 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
mbed_official 205:c41fc65bcfb4 5104
mbed_official 205:c41fc65bcfb4 5105 /*************************** LPM register bits definitions ******************/
mbed_official 205:c41fc65bcfb4 5106 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
mbed_official 205:c41fc65bcfb4 5107 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
mbed_official 205:c41fc65bcfb4 5108 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
mbed_official 205:c41fc65bcfb4 5109 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
mbed_official 205:c41fc65bcfb4 5110
mbed_official 205:c41fc65bcfb4 5111 /******************** FNR Frame Number Register bit definitions ************/
mbed_official 205:c41fc65bcfb4 5112 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
mbed_official 205:c41fc65bcfb4 5113 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
mbed_official 205:c41fc65bcfb4 5114 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
mbed_official 205:c41fc65bcfb4 5115 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
mbed_official 205:c41fc65bcfb4 5116 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
mbed_official 205:c41fc65bcfb4 5117
mbed_official 205:c41fc65bcfb4 5118 /******************** DADDR Device ADDRess bit definitions ****************/
mbed_official 205:c41fc65bcfb4 5119 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
mbed_official 205:c41fc65bcfb4 5120 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
mbed_official 205:c41fc65bcfb4 5121
mbed_official 205:c41fc65bcfb4 5122 /****************************** Endpoint register *************************/
mbed_official 205:c41fc65bcfb4 5123 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
mbed_official 205:c41fc65bcfb4 5124 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
mbed_official 205:c41fc65bcfb4 5125 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
mbed_official 205:c41fc65bcfb4 5126 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
mbed_official 205:c41fc65bcfb4 5127 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
mbed_official 205:c41fc65bcfb4 5128 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
mbed_official 205:c41fc65bcfb4 5129 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
mbed_official 205:c41fc65bcfb4 5130 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
mbed_official 205:c41fc65bcfb4 5131 /* bit positions */
mbed_official 205:c41fc65bcfb4 5132 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
mbed_official 205:c41fc65bcfb4 5133 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
mbed_official 205:c41fc65bcfb4 5134 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
mbed_official 205:c41fc65bcfb4 5135 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
mbed_official 205:c41fc65bcfb4 5136 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
mbed_official 205:c41fc65bcfb4 5137 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
mbed_official 205:c41fc65bcfb4 5138 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
mbed_official 205:c41fc65bcfb4 5139 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
mbed_official 205:c41fc65bcfb4 5140 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
mbed_official 205:c41fc65bcfb4 5141 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
mbed_official 205:c41fc65bcfb4 5142
mbed_official 205:c41fc65bcfb4 5143 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 205:c41fc65bcfb4 5144 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 205:c41fc65bcfb4 5145 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 205:c41fc65bcfb4 5146 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
mbed_official 205:c41fc65bcfb4 5147 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
mbed_official 205:c41fc65bcfb4 5148 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
mbed_official 205:c41fc65bcfb4 5149 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
mbed_official 205:c41fc65bcfb4 5150 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
mbed_official 205:c41fc65bcfb4 5151 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 205:c41fc65bcfb4 5152
mbed_official 205:c41fc65bcfb4 5153 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 205:c41fc65bcfb4 5154 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 205:c41fc65bcfb4 5155 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
mbed_official 205:c41fc65bcfb4 5156 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
mbed_official 205:c41fc65bcfb4 5157 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
mbed_official 205:c41fc65bcfb4 5158 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
mbed_official 205:c41fc65bcfb4 5159 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 205:c41fc65bcfb4 5160 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 205:c41fc65bcfb4 5161 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 205:c41fc65bcfb4 5162 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 205:c41fc65bcfb4 5163 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
mbed_official 205:c41fc65bcfb4 5164 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
mbed_official 205:c41fc65bcfb4 5165 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
mbed_official 205:c41fc65bcfb4 5166 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
mbed_official 205:c41fc65bcfb4 5167 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 205:c41fc65bcfb4 5168 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 205:c41fc65bcfb4 5169 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 205:c41fc65bcfb4 5170
mbed_official 205:c41fc65bcfb4 5171 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 5172 /* */
mbed_official 205:c41fc65bcfb4 5173 /* Window WATCHDOG (WWDG) */
mbed_official 205:c41fc65bcfb4 5174 /* */
mbed_official 205:c41fc65bcfb4 5175 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 5176 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 205:c41fc65bcfb4 5177 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 205:c41fc65bcfb4 5178 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 5179 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 5180 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 5181 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 5182 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 5183 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 205:c41fc65bcfb4 5184 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 205:c41fc65bcfb4 5185
mbed_official 205:c41fc65bcfb4 5186 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 205:c41fc65bcfb4 5187
mbed_official 205:c41fc65bcfb4 5188 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 205:c41fc65bcfb4 5189 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 205:c41fc65bcfb4 5190 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 5191 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 5192 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 205:c41fc65bcfb4 5193 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 205:c41fc65bcfb4 5194 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 205:c41fc65bcfb4 5195 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 205:c41fc65bcfb4 5196 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 205:c41fc65bcfb4 5197
mbed_official 205:c41fc65bcfb4 5198 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 205:c41fc65bcfb4 5199 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 205:c41fc65bcfb4 5200 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 205:c41fc65bcfb4 5201
mbed_official 205:c41fc65bcfb4 5202 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 205:c41fc65bcfb4 5203
mbed_official 205:c41fc65bcfb4 5204 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 205:c41fc65bcfb4 5205 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 205:c41fc65bcfb4 5206
mbed_official 205:c41fc65bcfb4 5207 /**
mbed_official 205:c41fc65bcfb4 5208 * @}
mbed_official 205:c41fc65bcfb4 5209 */
mbed_official 205:c41fc65bcfb4 5210
mbed_official 205:c41fc65bcfb4 5211 /**
mbed_official 205:c41fc65bcfb4 5212 * @}
mbed_official 205:c41fc65bcfb4 5213 */
mbed_official 205:c41fc65bcfb4 5214
mbed_official 205:c41fc65bcfb4 5215
mbed_official 205:c41fc65bcfb4 5216 /** @addtogroup Exported_macro
mbed_official 205:c41fc65bcfb4 5217 * @{
mbed_official 205:c41fc65bcfb4 5218 */
mbed_official 205:c41fc65bcfb4 5219
mbed_official 205:c41fc65bcfb4 5220 /****************************** ADC Instances *********************************/
mbed_official 205:c41fc65bcfb4 5221 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 205:c41fc65bcfb4 5222
mbed_official 205:c41fc65bcfb4 5223 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official 205:c41fc65bcfb4 5224
mbed_official 205:c41fc65bcfb4 5225 /******************************* CAN Instances ********************************/
mbed_official 205:c41fc65bcfb4 5226 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official 205:c41fc65bcfb4 5227
mbed_official 205:c41fc65bcfb4 5228 /****************************** COMP Instances *********************************/
mbed_official 205:c41fc65bcfb4 5229 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 205:c41fc65bcfb4 5230 ((INSTANCE) == COMP2))
mbed_official 205:c41fc65bcfb4 5231
mbed_official 205:c41fc65bcfb4 5232 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
mbed_official 205:c41fc65bcfb4 5233
mbed_official 205:c41fc65bcfb4 5234 /****************************** CEC Instances *********************************/
mbed_official 205:c41fc65bcfb4 5235 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
mbed_official 205:c41fc65bcfb4 5236
mbed_official 205:c41fc65bcfb4 5237 /****************************** CRC Instances *********************************/
mbed_official 205:c41fc65bcfb4 5238 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 205:c41fc65bcfb4 5239
mbed_official 205:c41fc65bcfb4 5240 /******************************* DAC Instances ********************************/
mbed_official 205:c41fc65bcfb4 5241 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 205:c41fc65bcfb4 5242
mbed_official 205:c41fc65bcfb4 5243 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 205:c41fc65bcfb4 5244 (((INSTANCE) == DAC1) && \
mbed_official 205:c41fc65bcfb4 5245 (((CHANNEL) == DAC1_CHANNEL_1) || \
mbed_official 205:c41fc65bcfb4 5246 ((CHANNEL) == DAC1_CHANNEL_2)))
mbed_official 205:c41fc65bcfb4 5247
mbed_official 205:c41fc65bcfb4 5248 /******************************* DMA Instances ******************************/
mbed_official 205:c41fc65bcfb4 5249 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 205:c41fc65bcfb4 5250 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 205:c41fc65bcfb4 5251 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 205:c41fc65bcfb4 5252 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 205:c41fc65bcfb4 5253 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 205:c41fc65bcfb4 5254 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 205:c41fc65bcfb4 5255 ((INSTANCE) == DMA1_Channel7))
mbed_official 205:c41fc65bcfb4 5256
mbed_official 205:c41fc65bcfb4 5257 /****************************** GPIO Instances ********************************/
mbed_official 205:c41fc65bcfb4 5258 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 205:c41fc65bcfb4 5259 ((INSTANCE) == GPIOB) || \
mbed_official 205:c41fc65bcfb4 5260 ((INSTANCE) == GPIOC) || \
mbed_official 205:c41fc65bcfb4 5261 ((INSTANCE) == GPIOD) || \
mbed_official 205:c41fc65bcfb4 5262 ((INSTANCE) == GPIOE) || \
mbed_official 205:c41fc65bcfb4 5263 ((INSTANCE) == GPIOF))
mbed_official 205:c41fc65bcfb4 5264
mbed_official 205:c41fc65bcfb4 5265 /****************************** I2C Instances *********************************/
mbed_official 205:c41fc65bcfb4 5266 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 205:c41fc65bcfb4 5267 ((INSTANCE) == I2C2))
mbed_official 205:c41fc65bcfb4 5268
mbed_official 205:c41fc65bcfb4 5269 /****************************** I2S Instances *********************************/
mbed_official 205:c41fc65bcfb4 5270 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 205:c41fc65bcfb4 5271 ((INSTANCE) == SPI2))
mbed_official 205:c41fc65bcfb4 5272
mbed_official 205:c41fc65bcfb4 5273 /****************************** IWDG Instances ********************************/
mbed_official 205:c41fc65bcfb4 5274 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 205:c41fc65bcfb4 5275
mbed_official 205:c41fc65bcfb4 5276 /****************************** RTC Instances *********************************/
mbed_official 205:c41fc65bcfb4 5277 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 205:c41fc65bcfb4 5278
mbed_official 205:c41fc65bcfb4 5279 /****************************** SMBUS Instances *********************************/
mbed_official 205:c41fc65bcfb4 5280 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 205:c41fc65bcfb4 5281
mbed_official 205:c41fc65bcfb4 5282 /****************************** SPI Instances *********************************/
mbed_official 205:c41fc65bcfb4 5283 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 205:c41fc65bcfb4 5284 ((INSTANCE) == SPI2))
mbed_official 205:c41fc65bcfb4 5285
mbed_official 205:c41fc65bcfb4 5286 /****************************** TIM Instances *********************************/
mbed_official 205:c41fc65bcfb4 5287 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5288 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5289 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5290 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5291 ((INSTANCE) == TIM6) || \
mbed_official 205:c41fc65bcfb4 5292 ((INSTANCE) == TIM7) || \
mbed_official 205:c41fc65bcfb4 5293 ((INSTANCE) == TIM14) || \
mbed_official 205:c41fc65bcfb4 5294 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5295 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5296 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5297
mbed_official 205:c41fc65bcfb4 5298 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5299 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5300 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5301 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5302 ((INSTANCE) == TIM14) || \
mbed_official 205:c41fc65bcfb4 5303 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5304 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5305 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5306
mbed_official 205:c41fc65bcfb4 5307 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5308 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5309 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5310 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5311 ((INSTANCE) == TIM15))
mbed_official 205:c41fc65bcfb4 5312
mbed_official 205:c41fc65bcfb4 5313 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5314 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5315 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5316 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5317
mbed_official 205:c41fc65bcfb4 5318 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5319 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5320 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5321 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5322
mbed_official 205:c41fc65bcfb4 5323 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5324 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5325 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5326 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5327
mbed_official 205:c41fc65bcfb4 5328 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5329 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5330 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5331 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5332
mbed_official 205:c41fc65bcfb4 5333 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5334 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5335 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5336 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5337 ((INSTANCE) == TIM15))
mbed_official 205:c41fc65bcfb4 5338
mbed_official 205:c41fc65bcfb4 5339 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5340 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5341 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5342 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5343 ((INSTANCE) == TIM15))
mbed_official 205:c41fc65bcfb4 5344
mbed_official 205:c41fc65bcfb4 5345 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5346 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5347 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5348 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5349
mbed_official 205:c41fc65bcfb4 5350 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5351 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5352 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5353 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5354
mbed_official 205:c41fc65bcfb4 5355 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5356 (((INSTANCE) == TIM1))
mbed_official 205:c41fc65bcfb4 5357
mbed_official 205:c41fc65bcfb4 5358 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5359 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5360 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5361 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5362
mbed_official 205:c41fc65bcfb4 5363 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5364 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5365 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5366 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5367 ((INSTANCE) == TIM6) || \
mbed_official 205:c41fc65bcfb4 5368 ((INSTANCE) == TIM7) || \
mbed_official 205:c41fc65bcfb4 5369 ((INSTANCE) == TIM15))
mbed_official 205:c41fc65bcfb4 5370
mbed_official 205:c41fc65bcfb4 5371 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5372 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5373 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5374 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5375 ((INSTANCE) == TIM15))
mbed_official 205:c41fc65bcfb4 5376
mbed_official 205:c41fc65bcfb4 5377 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5378 ((INSTANCE) == TIM2)
mbed_official 205:c41fc65bcfb4 5379
mbed_official 205:c41fc65bcfb4 5380 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5381 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5382 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5383 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5384 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5385 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5386 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5387
mbed_official 205:c41fc65bcfb4 5388 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5389 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5390 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5391 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5392 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5393
mbed_official 205:c41fc65bcfb4 5394 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 205:c41fc65bcfb4 5395 ((((INSTANCE) == TIM1) && \
mbed_official 205:c41fc65bcfb4 5396 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 205:c41fc65bcfb4 5397 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 205:c41fc65bcfb4 5398 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 205:c41fc65bcfb4 5399 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 205:c41fc65bcfb4 5400 || \
mbed_official 205:c41fc65bcfb4 5401 (((INSTANCE) == TIM2) && \
mbed_official 205:c41fc65bcfb4 5402 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 205:c41fc65bcfb4 5403 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 205:c41fc65bcfb4 5404 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 205:c41fc65bcfb4 5405 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 205:c41fc65bcfb4 5406 || \
mbed_official 205:c41fc65bcfb4 5407 (((INSTANCE) == TIM3) && \
mbed_official 205:c41fc65bcfb4 5408 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 205:c41fc65bcfb4 5409 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 205:c41fc65bcfb4 5410 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 205:c41fc65bcfb4 5411 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 205:c41fc65bcfb4 5412 || \
mbed_official 205:c41fc65bcfb4 5413 (((INSTANCE) == TIM14) && \
mbed_official 205:c41fc65bcfb4 5414 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 205:c41fc65bcfb4 5415 || \
mbed_official 205:c41fc65bcfb4 5416 (((INSTANCE) == TIM15) && \
mbed_official 205:c41fc65bcfb4 5417 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 205:c41fc65bcfb4 5418 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 205:c41fc65bcfb4 5419 || \
mbed_official 205:c41fc65bcfb4 5420 (((INSTANCE) == TIM16) && \
mbed_official 205:c41fc65bcfb4 5421 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 205:c41fc65bcfb4 5422 || \
mbed_official 205:c41fc65bcfb4 5423 (((INSTANCE) == TIM17) && \
mbed_official 205:c41fc65bcfb4 5424 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 205:c41fc65bcfb4 5425
mbed_official 205:c41fc65bcfb4 5426 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 205:c41fc65bcfb4 5427 ((((INSTANCE) == TIM1) && \
mbed_official 205:c41fc65bcfb4 5428 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 205:c41fc65bcfb4 5429 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 205:c41fc65bcfb4 5430 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 205:c41fc65bcfb4 5431 || \
mbed_official 205:c41fc65bcfb4 5432 (((INSTANCE) == TIM15) && \
mbed_official 205:c41fc65bcfb4 5433 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 205:c41fc65bcfb4 5434 || \
mbed_official 205:c41fc65bcfb4 5435 (((INSTANCE) == TIM16) && \
mbed_official 205:c41fc65bcfb4 5436 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 205:c41fc65bcfb4 5437 || \
mbed_official 205:c41fc65bcfb4 5438 (((INSTANCE) == TIM17) && \
mbed_official 205:c41fc65bcfb4 5439 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 205:c41fc65bcfb4 5440
mbed_official 205:c41fc65bcfb4 5441 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5442 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5443 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5444 ((INSTANCE) == TIM3))
mbed_official 205:c41fc65bcfb4 5445
mbed_official 205:c41fc65bcfb4 5446 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5447 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5448 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5449 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5450 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5451
mbed_official 205:c41fc65bcfb4 5452 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5453 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5454 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5455 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5456 ((INSTANCE) == TIM14) || \
mbed_official 205:c41fc65bcfb4 5457 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5458 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5459 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5460
mbed_official 205:c41fc65bcfb4 5461 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5462 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5463 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5464 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5465 ((INSTANCE) == TIM6) || \
mbed_official 205:c41fc65bcfb4 5466 ((INSTANCE) == TIM7) || \
mbed_official 205:c41fc65bcfb4 5467 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5468 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5469 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5470
mbed_official 205:c41fc65bcfb4 5471 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5472 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5473 ((INSTANCE) == TIM2) || \
mbed_official 205:c41fc65bcfb4 5474 ((INSTANCE) == TIM3) || \
mbed_official 205:c41fc65bcfb4 5475 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5476 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5477 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5478
mbed_official 205:c41fc65bcfb4 5479 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5480 (((INSTANCE) == TIM1) || \
mbed_official 205:c41fc65bcfb4 5481 ((INSTANCE) == TIM15) || \
mbed_official 205:c41fc65bcfb4 5482 ((INSTANCE) == TIM16) || \
mbed_official 205:c41fc65bcfb4 5483 ((INSTANCE) == TIM17))
mbed_official 205:c41fc65bcfb4 5484
mbed_official 205:c41fc65bcfb4 5485 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 205:c41fc65bcfb4 5486 ((INSTANCE) == TIM14)
mbed_official 205:c41fc65bcfb4 5487
mbed_official 205:c41fc65bcfb4 5488 /****************************** TSC Instances *********************************/
mbed_official 205:c41fc65bcfb4 5489 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official 205:c41fc65bcfb4 5490
mbed_official 205:c41fc65bcfb4 5491 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 205:c41fc65bcfb4 5492 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5493 ((INSTANCE) == USART2))
mbed_official 205:c41fc65bcfb4 5494
mbed_official 205:c41fc65bcfb4 5495 /********************* UART Instances : Smard card mode ***********************/
mbed_official 205:c41fc65bcfb4 5496 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5497 ((INSTANCE) == USART2))
mbed_official 205:c41fc65bcfb4 5498
mbed_official 205:c41fc65bcfb4 5499 /******************** USART Instances : Synchronous mode **********************/
mbed_official 205:c41fc65bcfb4 5500 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5501 ((INSTANCE) == USART2) || \
mbed_official 205:c41fc65bcfb4 5502 ((INSTANCE) == USART3) || \
mbed_official 205:c41fc65bcfb4 5503 ((INSTANCE) == USART4))
mbed_official 205:c41fc65bcfb4 5504
mbed_official 205:c41fc65bcfb4 5505 /******************** USART Instances : auto Baud rate detection **************/
mbed_official 205:c41fc65bcfb4 5506 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5507 ((INSTANCE) == USART2))
mbed_official 205:c41fc65bcfb4 5508
mbed_official 205:c41fc65bcfb4 5509 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 205:c41fc65bcfb4 5510 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5511 ((INSTANCE) == USART2) || \
mbed_official 205:c41fc65bcfb4 5512 ((INSTANCE) == USART3) || \
mbed_official 205:c41fc65bcfb4 5513 ((INSTANCE) == USART4))
mbed_official 205:c41fc65bcfb4 5514
mbed_official 205:c41fc65bcfb4 5515 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 205:c41fc65bcfb4 5516 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5517 ((INSTANCE) == USART2) || \
mbed_official 205:c41fc65bcfb4 5518 ((INSTANCE) == USART3) || \
mbed_official 205:c41fc65bcfb4 5519 ((INSTANCE) == USART4))
mbed_official 205:c41fc65bcfb4 5520
mbed_official 205:c41fc65bcfb4 5521 /****************** UART Instances : Auto Baud Rate detection ********************/
mbed_official 205:c41fc65bcfb4 5522 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5523 ((INSTANCE) == USART2))
mbed_official 205:c41fc65bcfb4 5524
mbed_official 205:c41fc65bcfb4 5525 /****************** UART Instances : Driver enable detection ********************/
mbed_official 205:c41fc65bcfb4 5526 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 205:c41fc65bcfb4 5527 ((INSTANCE) == USART2) || \
mbed_official 205:c41fc65bcfb4 5528 ((INSTANCE) == USART3) || \
mbed_official 205:c41fc65bcfb4 5529 ((INSTANCE) == USART4))
mbed_official 205:c41fc65bcfb4 5530
mbed_official 205:c41fc65bcfb4 5531 /****************************** USB Instances ********************************/
mbed_official 205:c41fc65bcfb4 5532 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 205:c41fc65bcfb4 5533
mbed_official 205:c41fc65bcfb4 5534 /****************************** WWDG Instances ********************************/
mbed_official 205:c41fc65bcfb4 5535 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 205:c41fc65bcfb4 5536
mbed_official 205:c41fc65bcfb4 5537 /**
mbed_official 205:c41fc65bcfb4 5538 * @}
mbed_official 205:c41fc65bcfb4 5539 */
mbed_official 205:c41fc65bcfb4 5540
mbed_official 205:c41fc65bcfb4 5541
mbed_official 205:c41fc65bcfb4 5542 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 5543 /* For a painless codes migration between the STM32F0xx device product */
mbed_official 205:c41fc65bcfb4 5544 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 205:c41fc65bcfb4 5545 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 205:c41fc65bcfb4 5546 /* No need to update developed interrupt code when moving across */
mbed_official 205:c41fc65bcfb4 5547 /* product lines within the same STM32F0 Family */
mbed_official 205:c41fc65bcfb4 5548 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 5549
mbed_official 205:c41fc65bcfb4 5550 /* Aliases for __IRQn */
mbed_official 205:c41fc65bcfb4 5551 #define PVD_IRQn PVD_VDDIO2_IRQn
mbed_official 205:c41fc65bcfb4 5552 #define RCC_IRQn RCC_CRS_IRQn
mbed_official 205:c41fc65bcfb4 5553 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
mbed_official 205:c41fc65bcfb4 5554 #define ADC1_IRQn ADC1_COMP_IRQn
mbed_official 205:c41fc65bcfb4 5555 #define TIM6_IRQn TIM6_DAC_IRQn
mbed_official 205:c41fc65bcfb4 5556
mbed_official 205:c41fc65bcfb4 5557 /* Aliases for __IRQHandler */
mbed_official 205:c41fc65bcfb4 5558 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official 205:c41fc65bcfb4 5559 #define RCC_IRQHandler RCC_CRS_IRQHandler
mbed_official 205:c41fc65bcfb4 5560 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
mbed_official 205:c41fc65bcfb4 5561 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
mbed_official 205:c41fc65bcfb4 5562 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
mbed_official 205:c41fc65bcfb4 5563
mbed_official 205:c41fc65bcfb4 5564 #ifdef __cplusplus
mbed_official 205:c41fc65bcfb4 5565 }
mbed_official 205:c41fc65bcfb4 5566 #endif /* __cplusplus */
mbed_official 205:c41fc65bcfb4 5567
mbed_official 205:c41fc65bcfb4 5568 #endif /* __STM32F072xB_H */
mbed_official 205:c41fc65bcfb4 5569
mbed_official 205:c41fc65bcfb4 5570 /**
mbed_official 205:c41fc65bcfb4 5571 * @}
mbed_official 205:c41fc65bcfb4 5572 */
mbed_official 205:c41fc65bcfb4 5573
mbed_official 205:c41fc65bcfb4 5574 /**
mbed_official 205:c41fc65bcfb4 5575 * @}
mbed_official 205:c41fc65bcfb4 5576 */
mbed_official 205:c41fc65bcfb4 5577
mbed_official 205:c41fc65bcfb4 5578 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/