shao ziyang
mbed library sources
Dependents: frdm_kl05z_gpio_test
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by 
mbed official
targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.c@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 126:549ba18ddd81
test with CLOCK_SETUP = 0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 126:549ba18ddd81 | 1 | /** |
| mbed_official | 126:549ba18ddd81 | 2 | ****************************************************************************** |
| mbed_official | 126:549ba18ddd81 | 3 | * @file stm32f10x_dma.c |
| mbed_official | 126:549ba18ddd81 | 4 | * @author MCD Application Team |
| mbed_official | 126:549ba18ddd81 | 5 | * @version V3.6.1 |
| mbed_official | 126:549ba18ddd81 | 6 | * @date 05-March-2012 |
| mbed_official | 126:549ba18ddd81 | 7 | * @brief This file provides all the DMA firmware functions. |
| mbed_official | 126:549ba18ddd81 | 8 | ******************************************************************************* |
| mbed_official | 126:549ba18ddd81 | 9 | * Copyright (c) 2014, STMicroelectronics |
| mbed_official | 126:549ba18ddd81 | 10 | * All rights reserved. |
| mbed_official | 126:549ba18ddd81 | 11 | * |
| mbed_official | 126:549ba18ddd81 | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 126:549ba18ddd81 | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 126:549ba18ddd81 | 14 | * |
| mbed_official | 126:549ba18ddd81 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 126:549ba18ddd81 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 126:549ba18ddd81 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 126:549ba18ddd81 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 126:549ba18ddd81 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 126:549ba18ddd81 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 126:549ba18ddd81 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 126:549ba18ddd81 | 22 | * without specific prior written permission. |
| mbed_official | 126:549ba18ddd81 | 23 | * |
| mbed_official | 126:549ba18ddd81 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 126:549ba18ddd81 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 126:549ba18ddd81 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 126:549ba18ddd81 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 126:549ba18ddd81 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 126:549ba18ddd81 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 126:549ba18ddd81 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 126:549ba18ddd81 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 126:549ba18ddd81 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 126:549ba18ddd81 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 126:549ba18ddd81 | 34 | ******************************************************************************* |
| mbed_official | 126:549ba18ddd81 | 35 | */ |
| mbed_official | 126:549ba18ddd81 | 36 | |
| mbed_official | 126:549ba18ddd81 | 37 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 38 | #include "stm32f10x_dma.h" |
| mbed_official | 126:549ba18ddd81 | 39 | #include "stm32f10x_rcc.h" |
| mbed_official | 126:549ba18ddd81 | 40 | |
| mbed_official | 126:549ba18ddd81 | 41 | /** @addtogroup STM32F10x_StdPeriph_Driver |
| mbed_official | 126:549ba18ddd81 | 42 | * @{ |
| mbed_official | 126:549ba18ddd81 | 43 | */ |
| mbed_official | 126:549ba18ddd81 | 44 | |
| mbed_official | 126:549ba18ddd81 | 45 | /** @defgroup DMA |
| mbed_official | 126:549ba18ddd81 | 46 | * @brief DMA driver modules |
| mbed_official | 126:549ba18ddd81 | 47 | * @{ |
| mbed_official | 126:549ba18ddd81 | 48 | */ |
| mbed_official | 126:549ba18ddd81 | 49 | |
| mbed_official | 126:549ba18ddd81 | 50 | /** @defgroup DMA_Private_TypesDefinitions |
| mbed_official | 126:549ba18ddd81 | 51 | * @{ |
| mbed_official | 126:549ba18ddd81 | 52 | */ |
| mbed_official | 126:549ba18ddd81 | 53 | /** |
| mbed_official | 126:549ba18ddd81 | 54 | * @} |
| mbed_official | 126:549ba18ddd81 | 55 | */ |
| mbed_official | 126:549ba18ddd81 | 56 | |
| mbed_official | 126:549ba18ddd81 | 57 | /** @defgroup DMA_Private_Defines |
| mbed_official | 126:549ba18ddd81 | 58 | * @{ |
| mbed_official | 126:549ba18ddd81 | 59 | */ |
| mbed_official | 126:549ba18ddd81 | 60 | |
| mbed_official | 126:549ba18ddd81 | 61 | |
| mbed_official | 126:549ba18ddd81 | 62 | /* DMA1 Channelx interrupt pending bit masks */ |
| mbed_official | 126:549ba18ddd81 | 63 | #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
| mbed_official | 126:549ba18ddd81 | 64 | #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
| mbed_official | 126:549ba18ddd81 | 65 | #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
| mbed_official | 126:549ba18ddd81 | 66 | #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
| mbed_official | 126:549ba18ddd81 | 67 | #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
| mbed_official | 126:549ba18ddd81 | 68 | #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) |
| mbed_official | 126:549ba18ddd81 | 69 | #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) |
| mbed_official | 126:549ba18ddd81 | 70 | |
| mbed_official | 126:549ba18ddd81 | 71 | /* DMA2 Channelx interrupt pending bit masks */ |
| mbed_official | 126:549ba18ddd81 | 72 | #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
| mbed_official | 126:549ba18ddd81 | 73 | #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
| mbed_official | 126:549ba18ddd81 | 74 | #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
| mbed_official | 126:549ba18ddd81 | 75 | #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
| mbed_official | 126:549ba18ddd81 | 76 | #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
| mbed_official | 126:549ba18ddd81 | 77 | |
| mbed_official | 126:549ba18ddd81 | 78 | /* DMA2 FLAG mask */ |
| mbed_official | 126:549ba18ddd81 | 79 | #define FLAG_Mask ((uint32_t)0x10000000) |
| mbed_official | 126:549ba18ddd81 | 80 | |
| mbed_official | 126:549ba18ddd81 | 81 | /* DMA registers Masks */ |
| mbed_official | 126:549ba18ddd81 | 82 | #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) |
| mbed_official | 126:549ba18ddd81 | 83 | |
| mbed_official | 126:549ba18ddd81 | 84 | /** |
| mbed_official | 126:549ba18ddd81 | 85 | * @} |
| mbed_official | 126:549ba18ddd81 | 86 | */ |
| mbed_official | 126:549ba18ddd81 | 87 | |
| mbed_official | 126:549ba18ddd81 | 88 | /** @defgroup DMA_Private_Macros |
| mbed_official | 126:549ba18ddd81 | 89 | * @{ |
| mbed_official | 126:549ba18ddd81 | 90 | */ |
| mbed_official | 126:549ba18ddd81 | 91 | |
| mbed_official | 126:549ba18ddd81 | 92 | /** |
| mbed_official | 126:549ba18ddd81 | 93 | * @} |
| mbed_official | 126:549ba18ddd81 | 94 | */ |
| mbed_official | 126:549ba18ddd81 | 95 | |
| mbed_official | 126:549ba18ddd81 | 96 | /** @defgroup DMA_Private_Variables |
| mbed_official | 126:549ba18ddd81 | 97 | * @{ |
| mbed_official | 126:549ba18ddd81 | 98 | */ |
| mbed_official | 126:549ba18ddd81 | 99 | |
| mbed_official | 126:549ba18ddd81 | 100 | /** |
| mbed_official | 126:549ba18ddd81 | 101 | * @} |
| mbed_official | 126:549ba18ddd81 | 102 | */ |
| mbed_official | 126:549ba18ddd81 | 103 | |
| mbed_official | 126:549ba18ddd81 | 104 | /** @defgroup DMA_Private_FunctionPrototypes |
| mbed_official | 126:549ba18ddd81 | 105 | * @{ |
| mbed_official | 126:549ba18ddd81 | 106 | */ |
| mbed_official | 126:549ba18ddd81 | 107 | |
| mbed_official | 126:549ba18ddd81 | 108 | /** |
| mbed_official | 126:549ba18ddd81 | 109 | * @} |
| mbed_official | 126:549ba18ddd81 | 110 | */ |
| mbed_official | 126:549ba18ddd81 | 111 | |
| mbed_official | 126:549ba18ddd81 | 112 | /** @defgroup DMA_Private_Functions |
| mbed_official | 126:549ba18ddd81 | 113 | * @{ |
| mbed_official | 126:549ba18ddd81 | 114 | */ |
| mbed_official | 126:549ba18ddd81 | 115 | |
| mbed_official | 126:549ba18ddd81 | 116 | /** |
| mbed_official | 126:549ba18ddd81 | 117 | * @brief Deinitializes the DMAy Channelx registers to their default reset |
| mbed_official | 126:549ba18ddd81 | 118 | * values. |
| mbed_official | 126:549ba18ddd81 | 119 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| mbed_official | 126:549ba18ddd81 | 120 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 121 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 122 | */ |
| mbed_official | 126:549ba18ddd81 | 123 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) |
| mbed_official | 126:549ba18ddd81 | 124 | { |
| mbed_official | 126:549ba18ddd81 | 125 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 126 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| mbed_official | 126:549ba18ddd81 | 127 | |
| mbed_official | 126:549ba18ddd81 | 128 | /* Disable the selected DMAy Channelx */ |
| mbed_official | 126:549ba18ddd81 | 129 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); |
| mbed_official | 126:549ba18ddd81 | 130 | |
| mbed_official | 126:549ba18ddd81 | 131 | /* Reset DMAy Channelx control register */ |
| mbed_official | 126:549ba18ddd81 | 132 | DMAy_Channelx->CCR = 0; |
| mbed_official | 126:549ba18ddd81 | 133 | |
| mbed_official | 126:549ba18ddd81 | 134 | /* Reset DMAy Channelx remaining bytes register */ |
| mbed_official | 126:549ba18ddd81 | 135 | DMAy_Channelx->CNDTR = 0; |
| mbed_official | 126:549ba18ddd81 | 136 | |
| mbed_official | 126:549ba18ddd81 | 137 | /* Reset DMAy Channelx peripheral address register */ |
| mbed_official | 126:549ba18ddd81 | 138 | DMAy_Channelx->CPAR = 0; |
| mbed_official | 126:549ba18ddd81 | 139 | |
| mbed_official | 126:549ba18ddd81 | 140 | /* Reset DMAy Channelx memory address register */ |
| mbed_official | 126:549ba18ddd81 | 141 | DMAy_Channelx->CMAR = 0; |
| mbed_official | 126:549ba18ddd81 | 142 | |
| mbed_official | 126:549ba18ddd81 | 143 | if (DMAy_Channelx == DMA1_Channel1) |
| mbed_official | 126:549ba18ddd81 | 144 | { |
| mbed_official | 126:549ba18ddd81 | 145 | /* Reset interrupt pending bits for DMA1 Channel1 */ |
| mbed_official | 126:549ba18ddd81 | 146 | DMA1->IFCR |= DMA1_Channel1_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 147 | } |
| mbed_official | 126:549ba18ddd81 | 148 | else if (DMAy_Channelx == DMA1_Channel2) |
| mbed_official | 126:549ba18ddd81 | 149 | { |
| mbed_official | 126:549ba18ddd81 | 150 | /* Reset interrupt pending bits for DMA1 Channel2 */ |
| mbed_official | 126:549ba18ddd81 | 151 | DMA1->IFCR |= DMA1_Channel2_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 152 | } |
| mbed_official | 126:549ba18ddd81 | 153 | else if (DMAy_Channelx == DMA1_Channel3) |
| mbed_official | 126:549ba18ddd81 | 154 | { |
| mbed_official | 126:549ba18ddd81 | 155 | /* Reset interrupt pending bits for DMA1 Channel3 */ |
| mbed_official | 126:549ba18ddd81 | 156 | DMA1->IFCR |= DMA1_Channel3_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 157 | } |
| mbed_official | 126:549ba18ddd81 | 158 | else if (DMAy_Channelx == DMA1_Channel4) |
| mbed_official | 126:549ba18ddd81 | 159 | { |
| mbed_official | 126:549ba18ddd81 | 160 | /* Reset interrupt pending bits for DMA1 Channel4 */ |
| mbed_official | 126:549ba18ddd81 | 161 | DMA1->IFCR |= DMA1_Channel4_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 162 | } |
| mbed_official | 126:549ba18ddd81 | 163 | else if (DMAy_Channelx == DMA1_Channel5) |
| mbed_official | 126:549ba18ddd81 | 164 | { |
| mbed_official | 126:549ba18ddd81 | 165 | /* Reset interrupt pending bits for DMA1 Channel5 */ |
| mbed_official | 126:549ba18ddd81 | 166 | DMA1->IFCR |= DMA1_Channel5_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 167 | } |
| mbed_official | 126:549ba18ddd81 | 168 | else if (DMAy_Channelx == DMA1_Channel6) |
| mbed_official | 126:549ba18ddd81 | 169 | { |
| mbed_official | 126:549ba18ddd81 | 170 | /* Reset interrupt pending bits for DMA1 Channel6 */ |
| mbed_official | 126:549ba18ddd81 | 171 | DMA1->IFCR |= DMA1_Channel6_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 172 | } |
| mbed_official | 126:549ba18ddd81 | 173 | else if (DMAy_Channelx == DMA1_Channel7) |
| mbed_official | 126:549ba18ddd81 | 174 | { |
| mbed_official | 126:549ba18ddd81 | 175 | /* Reset interrupt pending bits for DMA1 Channel7 */ |
| mbed_official | 126:549ba18ddd81 | 176 | DMA1->IFCR |= DMA1_Channel7_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 177 | } |
| mbed_official | 126:549ba18ddd81 | 178 | else if (DMAy_Channelx == DMA2_Channel1) |
| mbed_official | 126:549ba18ddd81 | 179 | { |
| mbed_official | 126:549ba18ddd81 | 180 | /* Reset interrupt pending bits for DMA2 Channel1 */ |
| mbed_official | 126:549ba18ddd81 | 181 | DMA2->IFCR |= DMA2_Channel1_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 182 | } |
| mbed_official | 126:549ba18ddd81 | 183 | else if (DMAy_Channelx == DMA2_Channel2) |
| mbed_official | 126:549ba18ddd81 | 184 | { |
| mbed_official | 126:549ba18ddd81 | 185 | /* Reset interrupt pending bits for DMA2 Channel2 */ |
| mbed_official | 126:549ba18ddd81 | 186 | DMA2->IFCR |= DMA2_Channel2_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 187 | } |
| mbed_official | 126:549ba18ddd81 | 188 | else if (DMAy_Channelx == DMA2_Channel3) |
| mbed_official | 126:549ba18ddd81 | 189 | { |
| mbed_official | 126:549ba18ddd81 | 190 | /* Reset interrupt pending bits for DMA2 Channel3 */ |
| mbed_official | 126:549ba18ddd81 | 191 | DMA2->IFCR |= DMA2_Channel3_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 192 | } |
| mbed_official | 126:549ba18ddd81 | 193 | else if (DMAy_Channelx == DMA2_Channel4) |
| mbed_official | 126:549ba18ddd81 | 194 | { |
| mbed_official | 126:549ba18ddd81 | 195 | /* Reset interrupt pending bits for DMA2 Channel4 */ |
| mbed_official | 126:549ba18ddd81 | 196 | DMA2->IFCR |= DMA2_Channel4_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 197 | } |
| mbed_official | 126:549ba18ddd81 | 198 | else |
| mbed_official | 126:549ba18ddd81 | 199 | { |
| mbed_official | 126:549ba18ddd81 | 200 | if (DMAy_Channelx == DMA2_Channel5) |
| mbed_official | 126:549ba18ddd81 | 201 | { |
| mbed_official | 126:549ba18ddd81 | 202 | /* Reset interrupt pending bits for DMA2 Channel5 */ |
| mbed_official | 126:549ba18ddd81 | 203 | DMA2->IFCR |= DMA2_Channel5_IT_Mask; |
| mbed_official | 126:549ba18ddd81 | 204 | } |
| mbed_official | 126:549ba18ddd81 | 205 | } |
| mbed_official | 126:549ba18ddd81 | 206 | } |
| mbed_official | 126:549ba18ddd81 | 207 | |
| mbed_official | 126:549ba18ddd81 | 208 | /** |
| mbed_official | 126:549ba18ddd81 | 209 | * @brief Initializes the DMAy Channelx according to the specified |
| mbed_official | 126:549ba18ddd81 | 210 | * parameters in the DMA_InitStruct. |
| mbed_official | 126:549ba18ddd81 | 211 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| mbed_official | 126:549ba18ddd81 | 212 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 213 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that |
| mbed_official | 126:549ba18ddd81 | 214 | * contains the configuration information for the specified DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 215 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 216 | */ |
| mbed_official | 126:549ba18ddd81 | 217 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) |
| mbed_official | 126:549ba18ddd81 | 218 | { |
| mbed_official | 126:549ba18ddd81 | 219 | uint32_t tmpreg = 0; |
| mbed_official | 126:549ba18ddd81 | 220 | |
| mbed_official | 126:549ba18ddd81 | 221 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 222 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| mbed_official | 126:549ba18ddd81 | 223 | assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); |
| mbed_official | 126:549ba18ddd81 | 224 | assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); |
| mbed_official | 126:549ba18ddd81 | 225 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); |
| mbed_official | 126:549ba18ddd81 | 226 | assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); |
| mbed_official | 126:549ba18ddd81 | 227 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); |
| mbed_official | 126:549ba18ddd81 | 228 | assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); |
| mbed_official | 126:549ba18ddd81 | 229 | assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); |
| mbed_official | 126:549ba18ddd81 | 230 | assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); |
| mbed_official | 126:549ba18ddd81 | 231 | assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); |
| mbed_official | 126:549ba18ddd81 | 232 | |
| mbed_official | 126:549ba18ddd81 | 233 | /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ |
| mbed_official | 126:549ba18ddd81 | 234 | /* Get the DMAy_Channelx CCR value */ |
| mbed_official | 126:549ba18ddd81 | 235 | tmpreg = DMAy_Channelx->CCR; |
| mbed_official | 126:549ba18ddd81 | 236 | /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
| mbed_official | 126:549ba18ddd81 | 237 | tmpreg &= CCR_CLEAR_Mask; |
| mbed_official | 126:549ba18ddd81 | 238 | /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ |
| mbed_official | 126:549ba18ddd81 | 239 | /* Set DIR bit according to DMA_DIR value */ |
| mbed_official | 126:549ba18ddd81 | 240 | /* Set CIRC bit according to DMA_Mode value */ |
| mbed_official | 126:549ba18ddd81 | 241 | /* Set PINC bit according to DMA_PeripheralInc value */ |
| mbed_official | 126:549ba18ddd81 | 242 | /* Set MINC bit according to DMA_MemoryInc value */ |
| mbed_official | 126:549ba18ddd81 | 243 | /* Set PSIZE bits according to DMA_PeripheralDataSize value */ |
| mbed_official | 126:549ba18ddd81 | 244 | /* Set MSIZE bits according to DMA_MemoryDataSize value */ |
| mbed_official | 126:549ba18ddd81 | 245 | /* Set PL bits according to DMA_Priority value */ |
| mbed_official | 126:549ba18ddd81 | 246 | /* Set the MEM2MEM bit according to DMA_M2M value */ |
| mbed_official | 126:549ba18ddd81 | 247 | tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | |
| mbed_official | 126:549ba18ddd81 | 248 | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | |
| mbed_official | 126:549ba18ddd81 | 249 | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | |
| mbed_official | 126:549ba18ddd81 | 250 | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; |
| mbed_official | 126:549ba18ddd81 | 251 | |
| mbed_official | 126:549ba18ddd81 | 252 | /* Write to DMAy Channelx CCR */ |
| mbed_official | 126:549ba18ddd81 | 253 | DMAy_Channelx->CCR = tmpreg; |
| mbed_official | 126:549ba18ddd81 | 254 | |
| mbed_official | 126:549ba18ddd81 | 255 | /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ |
| mbed_official | 126:549ba18ddd81 | 256 | /* Write to DMAy Channelx CNDTR */ |
| mbed_official | 126:549ba18ddd81 | 257 | DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; |
| mbed_official | 126:549ba18ddd81 | 258 | |
| mbed_official | 126:549ba18ddd81 | 259 | /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ |
| mbed_official | 126:549ba18ddd81 | 260 | /* Write to DMAy Channelx CPAR */ |
| mbed_official | 126:549ba18ddd81 | 261 | DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; |
| mbed_official | 126:549ba18ddd81 | 262 | |
| mbed_official | 126:549ba18ddd81 | 263 | /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ |
| mbed_official | 126:549ba18ddd81 | 264 | /* Write to DMAy Channelx CMAR */ |
| mbed_official | 126:549ba18ddd81 | 265 | DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; |
| mbed_official | 126:549ba18ddd81 | 266 | } |
| mbed_official | 126:549ba18ddd81 | 267 | |
| mbed_official | 126:549ba18ddd81 | 268 | /** |
| mbed_official | 126:549ba18ddd81 | 269 | * @brief Fills each DMA_InitStruct member with its default value. |
| mbed_official | 126:549ba18ddd81 | 270 | * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will |
| mbed_official | 126:549ba18ddd81 | 271 | * be initialized. |
| mbed_official | 126:549ba18ddd81 | 272 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 273 | */ |
| mbed_official | 126:549ba18ddd81 | 274 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) |
| mbed_official | 126:549ba18ddd81 | 275 | { |
| mbed_official | 126:549ba18ddd81 | 276 | /*-------------- Reset DMA init structure parameters values ------------------*/ |
| mbed_official | 126:549ba18ddd81 | 277 | /* Initialize the DMA_PeripheralBaseAddr member */ |
| mbed_official | 126:549ba18ddd81 | 278 | DMA_InitStruct->DMA_PeripheralBaseAddr = 0; |
| mbed_official | 126:549ba18ddd81 | 279 | /* Initialize the DMA_MemoryBaseAddr member */ |
| mbed_official | 126:549ba18ddd81 | 280 | DMA_InitStruct->DMA_MemoryBaseAddr = 0; |
| mbed_official | 126:549ba18ddd81 | 281 | /* Initialize the DMA_DIR member */ |
| mbed_official | 126:549ba18ddd81 | 282 | DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; |
| mbed_official | 126:549ba18ddd81 | 283 | /* Initialize the DMA_BufferSize member */ |
| mbed_official | 126:549ba18ddd81 | 284 | DMA_InitStruct->DMA_BufferSize = 0; |
| mbed_official | 126:549ba18ddd81 | 285 | /* Initialize the DMA_PeripheralInc member */ |
| mbed_official | 126:549ba18ddd81 | 286 | DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; |
| mbed_official | 126:549ba18ddd81 | 287 | /* Initialize the DMA_MemoryInc member */ |
| mbed_official | 126:549ba18ddd81 | 288 | DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; |
| mbed_official | 126:549ba18ddd81 | 289 | /* Initialize the DMA_PeripheralDataSize member */ |
| mbed_official | 126:549ba18ddd81 | 290 | DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; |
| mbed_official | 126:549ba18ddd81 | 291 | /* Initialize the DMA_MemoryDataSize member */ |
| mbed_official | 126:549ba18ddd81 | 292 | DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; |
| mbed_official | 126:549ba18ddd81 | 293 | /* Initialize the DMA_Mode member */ |
| mbed_official | 126:549ba18ddd81 | 294 | DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; |
| mbed_official | 126:549ba18ddd81 | 295 | /* Initialize the DMA_Priority member */ |
| mbed_official | 126:549ba18ddd81 | 296 | DMA_InitStruct->DMA_Priority = DMA_Priority_Low; |
| mbed_official | 126:549ba18ddd81 | 297 | /* Initialize the DMA_M2M member */ |
| mbed_official | 126:549ba18ddd81 | 298 | DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; |
| mbed_official | 126:549ba18ddd81 | 299 | } |
| mbed_official | 126:549ba18ddd81 | 300 | |
| mbed_official | 126:549ba18ddd81 | 301 | /** |
| mbed_official | 126:549ba18ddd81 | 302 | * @brief Enables or disables the specified DMAy Channelx. |
| mbed_official | 126:549ba18ddd81 | 303 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| mbed_official | 126:549ba18ddd81 | 304 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 305 | * @param NewState: new state of the DMAy Channelx. |
| mbed_official | 126:549ba18ddd81 | 306 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 307 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 308 | */ |
| mbed_official | 126:549ba18ddd81 | 309 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 310 | { |
| mbed_official | 126:549ba18ddd81 | 311 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 312 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| mbed_official | 126:549ba18ddd81 | 313 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 314 | |
| mbed_official | 126:549ba18ddd81 | 315 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 316 | { |
| mbed_official | 126:549ba18ddd81 | 317 | /* Enable the selected DMAy Channelx */ |
| mbed_official | 126:549ba18ddd81 | 318 | DMAy_Channelx->CCR |= DMA_CCR1_EN; |
| mbed_official | 126:549ba18ddd81 | 319 | } |
| mbed_official | 126:549ba18ddd81 | 320 | else |
| mbed_official | 126:549ba18ddd81 | 321 | { |
| mbed_official | 126:549ba18ddd81 | 322 | /* Disable the selected DMAy Channelx */ |
| mbed_official | 126:549ba18ddd81 | 323 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); |
| mbed_official | 126:549ba18ddd81 | 324 | } |
| mbed_official | 126:549ba18ddd81 | 325 | } |
| mbed_official | 126:549ba18ddd81 | 326 | |
| mbed_official | 126:549ba18ddd81 | 327 | /** |
| mbed_official | 126:549ba18ddd81 | 328 | * @brief Enables or disables the specified DMAy Channelx interrupts. |
| mbed_official | 126:549ba18ddd81 | 329 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| mbed_official | 126:549ba18ddd81 | 330 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 331 | * @param DMA_IT: specifies the DMA interrupts sources to be enabled |
| mbed_official | 126:549ba18ddd81 | 332 | * or disabled. |
| mbed_official | 126:549ba18ddd81 | 333 | * This parameter can be any combination of the following values: |
| mbed_official | 126:549ba18ddd81 | 334 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| mbed_official | 126:549ba18ddd81 | 335 | * @arg DMA_IT_HT: Half transfer interrupt mask |
| mbed_official | 126:549ba18ddd81 | 336 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| mbed_official | 126:549ba18ddd81 | 337 | * @param NewState: new state of the specified DMA interrupts. |
| mbed_official | 126:549ba18ddd81 | 338 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 126:549ba18ddd81 | 339 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 340 | */ |
| mbed_official | 126:549ba18ddd81 | 341 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) |
| mbed_official | 126:549ba18ddd81 | 342 | { |
| mbed_official | 126:549ba18ddd81 | 343 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 344 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| mbed_official | 126:549ba18ddd81 | 345 | assert_param(IS_DMA_CONFIG_IT(DMA_IT)); |
| mbed_official | 126:549ba18ddd81 | 346 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 126:549ba18ddd81 | 347 | if (NewState != DISABLE) |
| mbed_official | 126:549ba18ddd81 | 348 | { |
| mbed_official | 126:549ba18ddd81 | 349 | /* Enable the selected DMA interrupts */ |
| mbed_official | 126:549ba18ddd81 | 350 | DMAy_Channelx->CCR |= DMA_IT; |
| mbed_official | 126:549ba18ddd81 | 351 | } |
| mbed_official | 126:549ba18ddd81 | 352 | else |
| mbed_official | 126:549ba18ddd81 | 353 | { |
| mbed_official | 126:549ba18ddd81 | 354 | /* Disable the selected DMA interrupts */ |
| mbed_official | 126:549ba18ddd81 | 355 | DMAy_Channelx->CCR &= ~DMA_IT; |
| mbed_official | 126:549ba18ddd81 | 356 | } |
| mbed_official | 126:549ba18ddd81 | 357 | } |
| mbed_official | 126:549ba18ddd81 | 358 | |
| mbed_official | 126:549ba18ddd81 | 359 | /** |
| mbed_official | 126:549ba18ddd81 | 360 | * @brief Sets the number of data units in the current DMAy Channelx transfer. |
| mbed_official | 126:549ba18ddd81 | 361 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| mbed_official | 126:549ba18ddd81 | 362 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 363 | * @param DataNumber: The number of data units in the current DMAy Channelx |
| mbed_official | 126:549ba18ddd81 | 364 | * transfer. |
| mbed_official | 126:549ba18ddd81 | 365 | * @note This function can only be used when the DMAy_Channelx is disabled. |
| mbed_official | 126:549ba18ddd81 | 366 | * @retval None. |
| mbed_official | 126:549ba18ddd81 | 367 | */ |
| mbed_official | 126:549ba18ddd81 | 368 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) |
| mbed_official | 126:549ba18ddd81 | 369 | { |
| mbed_official | 126:549ba18ddd81 | 370 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 371 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| mbed_official | 126:549ba18ddd81 | 372 | |
| mbed_official | 126:549ba18ddd81 | 373 | /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ |
| mbed_official | 126:549ba18ddd81 | 374 | /* Write to DMAy Channelx CNDTR */ |
| mbed_official | 126:549ba18ddd81 | 375 | DMAy_Channelx->CNDTR = DataNumber; |
| mbed_official | 126:549ba18ddd81 | 376 | } |
| mbed_official | 126:549ba18ddd81 | 377 | |
| mbed_official | 126:549ba18ddd81 | 378 | /** |
| mbed_official | 126:549ba18ddd81 | 379 | * @brief Returns the number of remaining data units in the current |
| mbed_official | 126:549ba18ddd81 | 380 | * DMAy Channelx transfer. |
| mbed_official | 126:549ba18ddd81 | 381 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| mbed_official | 126:549ba18ddd81 | 382 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| mbed_official | 126:549ba18ddd81 | 383 | * @retval The number of remaining data units in the current DMAy Channelx |
| mbed_official | 126:549ba18ddd81 | 384 | * transfer. |
| mbed_official | 126:549ba18ddd81 | 385 | */ |
| mbed_official | 126:549ba18ddd81 | 386 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) |
| mbed_official | 126:549ba18ddd81 | 387 | { |
| mbed_official | 126:549ba18ddd81 | 388 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 389 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| mbed_official | 126:549ba18ddd81 | 390 | /* Return the number of remaining data units for DMAy Channelx */ |
| mbed_official | 126:549ba18ddd81 | 391 | return ((uint16_t)(DMAy_Channelx->CNDTR)); |
| mbed_official | 126:549ba18ddd81 | 392 | } |
| mbed_official | 126:549ba18ddd81 | 393 | |
| mbed_official | 126:549ba18ddd81 | 394 | /** |
| mbed_official | 126:549ba18ddd81 | 395 | * @brief Checks whether the specified DMAy Channelx flag is set or not. |
| mbed_official | 126:549ba18ddd81 | 396 | * @param DMAy_FLAG: specifies the flag to check. |
| mbed_official | 126:549ba18ddd81 | 397 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 398 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
| mbed_official | 126:549ba18ddd81 | 399 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 400 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 401 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 402 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
| mbed_official | 126:549ba18ddd81 | 403 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 404 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 405 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 406 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
| mbed_official | 126:549ba18ddd81 | 407 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 408 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 409 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 410 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
| mbed_official | 126:549ba18ddd81 | 411 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 412 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 413 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 414 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
| mbed_official | 126:549ba18ddd81 | 415 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 416 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 417 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 418 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. |
| mbed_official | 126:549ba18ddd81 | 419 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 420 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 421 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 422 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. |
| mbed_official | 126:549ba18ddd81 | 423 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 424 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 425 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 426 | * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. |
| mbed_official | 126:549ba18ddd81 | 427 | * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 428 | * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 429 | * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 430 | * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. |
| mbed_official | 126:549ba18ddd81 | 431 | * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 432 | * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 433 | * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 434 | * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. |
| mbed_official | 126:549ba18ddd81 | 435 | * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 436 | * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 437 | * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 438 | * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. |
| mbed_official | 126:549ba18ddd81 | 439 | * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 440 | * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 441 | * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 442 | * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. |
| mbed_official | 126:549ba18ddd81 | 443 | * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 444 | * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 445 | * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 446 | * @retval The new state of DMAy_FLAG (SET or RESET). |
| mbed_official | 126:549ba18ddd81 | 447 | */ |
| mbed_official | 126:549ba18ddd81 | 448 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) |
| mbed_official | 126:549ba18ddd81 | 449 | { |
| mbed_official | 126:549ba18ddd81 | 450 | FlagStatus bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 451 | uint32_t tmpreg = 0; |
| mbed_official | 126:549ba18ddd81 | 452 | |
| mbed_official | 126:549ba18ddd81 | 453 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 454 | assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); |
| mbed_official | 126:549ba18ddd81 | 455 | |
| mbed_official | 126:549ba18ddd81 | 456 | /* Calculate the used DMAy */ |
| mbed_official | 126:549ba18ddd81 | 457 | if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) |
| mbed_official | 126:549ba18ddd81 | 458 | { |
| mbed_official | 126:549ba18ddd81 | 459 | /* Get DMA2 ISR register value */ |
| mbed_official | 126:549ba18ddd81 | 460 | tmpreg = DMA2->ISR ; |
| mbed_official | 126:549ba18ddd81 | 461 | } |
| mbed_official | 126:549ba18ddd81 | 462 | else |
| mbed_official | 126:549ba18ddd81 | 463 | { |
| mbed_official | 126:549ba18ddd81 | 464 | /* Get DMA1 ISR register value */ |
| mbed_official | 126:549ba18ddd81 | 465 | tmpreg = DMA1->ISR ; |
| mbed_official | 126:549ba18ddd81 | 466 | } |
| mbed_official | 126:549ba18ddd81 | 467 | |
| mbed_official | 126:549ba18ddd81 | 468 | /* Check the status of the specified DMAy flag */ |
| mbed_official | 126:549ba18ddd81 | 469 | if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) |
| mbed_official | 126:549ba18ddd81 | 470 | { |
| mbed_official | 126:549ba18ddd81 | 471 | /* DMAy_FLAG is set */ |
| mbed_official | 126:549ba18ddd81 | 472 | bitstatus = SET; |
| mbed_official | 126:549ba18ddd81 | 473 | } |
| mbed_official | 126:549ba18ddd81 | 474 | else |
| mbed_official | 126:549ba18ddd81 | 475 | { |
| mbed_official | 126:549ba18ddd81 | 476 | /* DMAy_FLAG is reset */ |
| mbed_official | 126:549ba18ddd81 | 477 | bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 478 | } |
| mbed_official | 126:549ba18ddd81 | 479 | |
| mbed_official | 126:549ba18ddd81 | 480 | /* Return the DMAy_FLAG status */ |
| mbed_official | 126:549ba18ddd81 | 481 | return bitstatus; |
| mbed_official | 126:549ba18ddd81 | 482 | } |
| mbed_official | 126:549ba18ddd81 | 483 | |
| mbed_official | 126:549ba18ddd81 | 484 | /** |
| mbed_official | 126:549ba18ddd81 | 485 | * @brief Clears the DMAy Channelx's pending flags. |
| mbed_official | 126:549ba18ddd81 | 486 | * @param DMAy_FLAG: specifies the flag to clear. |
| mbed_official | 126:549ba18ddd81 | 487 | * This parameter can be any combination (for the same DMA) of the following values: |
| mbed_official | 126:549ba18ddd81 | 488 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
| mbed_official | 126:549ba18ddd81 | 489 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 490 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 491 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 492 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
| mbed_official | 126:549ba18ddd81 | 493 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 494 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 495 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 496 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
| mbed_official | 126:549ba18ddd81 | 497 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 498 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 499 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 500 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
| mbed_official | 126:549ba18ddd81 | 501 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 502 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 503 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 504 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
| mbed_official | 126:549ba18ddd81 | 505 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 506 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 507 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 508 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. |
| mbed_official | 126:549ba18ddd81 | 509 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 510 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 511 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 512 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. |
| mbed_official | 126:549ba18ddd81 | 513 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 514 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 515 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 516 | * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. |
| mbed_official | 126:549ba18ddd81 | 517 | * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 518 | * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 519 | * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 520 | * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. |
| mbed_official | 126:549ba18ddd81 | 521 | * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 522 | * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 523 | * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 524 | * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. |
| mbed_official | 126:549ba18ddd81 | 525 | * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 526 | * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 527 | * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 528 | * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. |
| mbed_official | 126:549ba18ddd81 | 529 | * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 530 | * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 531 | * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 532 | * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. |
| mbed_official | 126:549ba18ddd81 | 533 | * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. |
| mbed_official | 126:549ba18ddd81 | 534 | * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. |
| mbed_official | 126:549ba18ddd81 | 535 | * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. |
| mbed_official | 126:549ba18ddd81 | 536 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 537 | */ |
| mbed_official | 126:549ba18ddd81 | 538 | void DMA_ClearFlag(uint32_t DMAy_FLAG) |
| mbed_official | 126:549ba18ddd81 | 539 | { |
| mbed_official | 126:549ba18ddd81 | 540 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 541 | assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); |
| mbed_official | 126:549ba18ddd81 | 542 | |
| mbed_official | 126:549ba18ddd81 | 543 | /* Calculate the used DMAy */ |
| mbed_official | 126:549ba18ddd81 | 544 | if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) |
| mbed_official | 126:549ba18ddd81 | 545 | { |
| mbed_official | 126:549ba18ddd81 | 546 | /* Clear the selected DMAy flags */ |
| mbed_official | 126:549ba18ddd81 | 547 | DMA2->IFCR = DMAy_FLAG; |
| mbed_official | 126:549ba18ddd81 | 548 | } |
| mbed_official | 126:549ba18ddd81 | 549 | else |
| mbed_official | 126:549ba18ddd81 | 550 | { |
| mbed_official | 126:549ba18ddd81 | 551 | /* Clear the selected DMAy flags */ |
| mbed_official | 126:549ba18ddd81 | 552 | DMA1->IFCR = DMAy_FLAG; |
| mbed_official | 126:549ba18ddd81 | 553 | } |
| mbed_official | 126:549ba18ddd81 | 554 | } |
| mbed_official | 126:549ba18ddd81 | 555 | |
| mbed_official | 126:549ba18ddd81 | 556 | /** |
| mbed_official | 126:549ba18ddd81 | 557 | * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. |
| mbed_official | 126:549ba18ddd81 | 558 | * @param DMAy_IT: specifies the DMAy interrupt source to check. |
| mbed_official | 126:549ba18ddd81 | 559 | * This parameter can be one of the following values: |
| mbed_official | 126:549ba18ddd81 | 560 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 561 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 562 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 563 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 564 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 565 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 566 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 567 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 568 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 569 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 570 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 571 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 572 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 573 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 574 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 575 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 576 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 577 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 578 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 579 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 580 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 581 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 582 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 583 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 584 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 585 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 586 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 587 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 588 | * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 589 | * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 590 | * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 591 | * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 592 | * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 593 | * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 594 | * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 595 | * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 596 | * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 597 | * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 598 | * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 599 | * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 600 | * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 601 | * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 602 | * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 603 | * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 604 | * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 605 | * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 606 | * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 607 | * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 608 | * @retval The new state of DMAy_IT (SET or RESET). |
| mbed_official | 126:549ba18ddd81 | 609 | */ |
| mbed_official | 126:549ba18ddd81 | 610 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT) |
| mbed_official | 126:549ba18ddd81 | 611 | { |
| mbed_official | 126:549ba18ddd81 | 612 | ITStatus bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 613 | uint32_t tmpreg = 0; |
| mbed_official | 126:549ba18ddd81 | 614 | |
| mbed_official | 126:549ba18ddd81 | 615 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 616 | assert_param(IS_DMA_GET_IT(DMAy_IT)); |
| mbed_official | 126:549ba18ddd81 | 617 | |
| mbed_official | 126:549ba18ddd81 | 618 | /* Calculate the used DMA */ |
| mbed_official | 126:549ba18ddd81 | 619 | if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) |
| mbed_official | 126:549ba18ddd81 | 620 | { |
| mbed_official | 126:549ba18ddd81 | 621 | /* Get DMA2 ISR register value */ |
| mbed_official | 126:549ba18ddd81 | 622 | tmpreg = DMA2->ISR; |
| mbed_official | 126:549ba18ddd81 | 623 | } |
| mbed_official | 126:549ba18ddd81 | 624 | else |
| mbed_official | 126:549ba18ddd81 | 625 | { |
| mbed_official | 126:549ba18ddd81 | 626 | /* Get DMA1 ISR register value */ |
| mbed_official | 126:549ba18ddd81 | 627 | tmpreg = DMA1->ISR; |
| mbed_official | 126:549ba18ddd81 | 628 | } |
| mbed_official | 126:549ba18ddd81 | 629 | |
| mbed_official | 126:549ba18ddd81 | 630 | /* Check the status of the specified DMAy interrupt */ |
| mbed_official | 126:549ba18ddd81 | 631 | if ((tmpreg & DMAy_IT) != (uint32_t)RESET) |
| mbed_official | 126:549ba18ddd81 | 632 | { |
| mbed_official | 126:549ba18ddd81 | 633 | /* DMAy_IT is set */ |
| mbed_official | 126:549ba18ddd81 | 634 | bitstatus = SET; |
| mbed_official | 126:549ba18ddd81 | 635 | } |
| mbed_official | 126:549ba18ddd81 | 636 | else |
| mbed_official | 126:549ba18ddd81 | 637 | { |
| mbed_official | 126:549ba18ddd81 | 638 | /* DMAy_IT is reset */ |
| mbed_official | 126:549ba18ddd81 | 639 | bitstatus = RESET; |
| mbed_official | 126:549ba18ddd81 | 640 | } |
| mbed_official | 126:549ba18ddd81 | 641 | /* Return the DMA_IT status */ |
| mbed_official | 126:549ba18ddd81 | 642 | return bitstatus; |
| mbed_official | 126:549ba18ddd81 | 643 | } |
| mbed_official | 126:549ba18ddd81 | 644 | |
| mbed_official | 126:549ba18ddd81 | 645 | /** |
| mbed_official | 126:549ba18ddd81 | 646 | * @brief Clears the DMAy Channelx's interrupt pending bits. |
| mbed_official | 126:549ba18ddd81 | 647 | * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. |
| mbed_official | 126:549ba18ddd81 | 648 | * This parameter can be any combination (for the same DMA) of the following values: |
| mbed_official | 126:549ba18ddd81 | 649 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 650 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 651 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 652 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 653 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 654 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 655 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 656 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 657 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 658 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 659 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 660 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 661 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 662 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 663 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 664 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 665 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 666 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 667 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 668 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 669 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 670 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 671 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 672 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 673 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 674 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 675 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 676 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 677 | * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 678 | * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 679 | * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 680 | * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 681 | * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 682 | * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 683 | * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 684 | * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 685 | * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 686 | * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 687 | * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 688 | * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 689 | * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 690 | * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 691 | * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 692 | * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 693 | * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. |
| mbed_official | 126:549ba18ddd81 | 694 | * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. |
| mbed_official | 126:549ba18ddd81 | 695 | * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. |
| mbed_official | 126:549ba18ddd81 | 696 | * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. |
| mbed_official | 126:549ba18ddd81 | 697 | * @retval None |
| mbed_official | 126:549ba18ddd81 | 698 | */ |
| mbed_official | 126:549ba18ddd81 | 699 | void DMA_ClearITPendingBit(uint32_t DMAy_IT) |
| mbed_official | 126:549ba18ddd81 | 700 | { |
| mbed_official | 126:549ba18ddd81 | 701 | /* Check the parameters */ |
| mbed_official | 126:549ba18ddd81 | 702 | assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); |
| mbed_official | 126:549ba18ddd81 | 703 | |
| mbed_official | 126:549ba18ddd81 | 704 | /* Calculate the used DMAy */ |
| mbed_official | 126:549ba18ddd81 | 705 | if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) |
| mbed_official | 126:549ba18ddd81 | 706 | { |
| mbed_official | 126:549ba18ddd81 | 707 | /* Clear the selected DMAy interrupt pending bits */ |
| mbed_official | 126:549ba18ddd81 | 708 | DMA2->IFCR = DMAy_IT; |
| mbed_official | 126:549ba18ddd81 | 709 | } |
| mbed_official | 126:549ba18ddd81 | 710 | else |
| mbed_official | 126:549ba18ddd81 | 711 | { |
| mbed_official | 126:549ba18ddd81 | 712 | /* Clear the selected DMAy interrupt pending bits */ |
| mbed_official | 126:549ba18ddd81 | 713 | DMA1->IFCR = DMAy_IT; |
| mbed_official | 126:549ba18ddd81 | 714 | } |
| mbed_official | 126:549ba18ddd81 | 715 | } |
| mbed_official | 126:549ba18ddd81 | 716 | |
| mbed_official | 126:549ba18ddd81 | 717 | /** |
| mbed_official | 126:549ba18ddd81 | 718 | * @} |
| mbed_official | 126:549ba18ddd81 | 719 | */ |
| mbed_official | 126:549ba18ddd81 | 720 | |
| mbed_official | 126:549ba18ddd81 | 721 | /** |
| mbed_official | 126:549ba18ddd81 | 722 | * @} |
| mbed_official | 126:549ba18ddd81 | 723 | */ |
| mbed_official | 126:549ba18ddd81 | 724 | |
| mbed_official | 126:549ba18ddd81 | 725 | /** |
| mbed_official | 126:549ba18ddd81 | 726 | * @} |
| mbed_official | 126:549ba18ddd81 | 727 | */ |
| mbed_official | 126:549ba18ddd81 | 728 | |
| mbed_official | 126:549ba18ddd81 | 729 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |