shao ziyang
mbed library sources
Dependents: frdm_kl05z_gpio_test
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mbed official
targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 126:549ba18ddd81
test with CLOCK_SETUP = 0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 126:549ba18ddd81 | 1 | /** |
| mbed_official | 126:549ba18ddd81 | 2 | ****************************************************************************** |
| mbed_official | 126:549ba18ddd81 | 3 | * @file stm32f10x.h |
| mbed_official | 126:549ba18ddd81 | 4 | * @author MCD Application Team |
| mbed_official | 126:549ba18ddd81 | 5 | * @version V3.6.2 |
| mbed_official | 126:549ba18ddd81 | 6 | * @date 28-February-2013 |
| mbed_official | 126:549ba18ddd81 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
| mbed_official | 126:549ba18ddd81 | 8 | * This file contains all the peripheral register's definitions, bits |
| mbed_official | 126:549ba18ddd81 | 9 | * definitions and memory mapping for STM32F10x Connectivity line, |
| mbed_official | 126:549ba18ddd81 | 10 | * High density, High density value line, Medium density, |
| mbed_official | 126:549ba18ddd81 | 11 | * Medium density Value line, Low density, Low density Value line |
| mbed_official | 126:549ba18ddd81 | 12 | * and XL-density devices. |
| mbed_official | 126:549ba18ddd81 | 13 | * |
| mbed_official | 126:549ba18ddd81 | 14 | * The file is the unique include file that the application programmer |
| mbed_official | 126:549ba18ddd81 | 15 | * is using in the C source code, usually in main.c. This file contains: |
| mbed_official | 126:549ba18ddd81 | 16 | * - Configuration section that allows to select: |
| mbed_official | 126:549ba18ddd81 | 17 | * - The device used in the target application |
| mbed_official | 126:549ba18ddd81 | 18 | * - To use or not the peripherals drivers in application code(i.e. |
| mbed_official | 126:549ba18ddd81 | 19 | * code will be based on direct access to peripherals registers |
| mbed_official | 126:549ba18ddd81 | 20 | * rather than drivers API), this option is controlled by |
| mbed_official | 126:549ba18ddd81 | 21 | * "#define USE_STDPERIPH_DRIVER" |
| mbed_official | 126:549ba18ddd81 | 22 | * - To change few application-specific parameters such as the HSE |
| mbed_official | 126:549ba18ddd81 | 23 | * crystal frequency |
| mbed_official | 126:549ba18ddd81 | 24 | * - Data structures and the address mapping for all peripherals |
| mbed_official | 126:549ba18ddd81 | 25 | * - Peripheral's registers declarations and bits definition |
| mbed_official | 126:549ba18ddd81 | 26 | * - Macros to access peripherals registers hardware |
| mbed_official | 126:549ba18ddd81 | 27 | * |
| mbed_official | 126:549ba18ddd81 | 28 | ******************************************************************************* |
| mbed_official | 126:549ba18ddd81 | 29 | * Copyright (c) 2014, STMicroelectronics |
| mbed_official | 126:549ba18ddd81 | 30 | * All rights reserved. |
| mbed_official | 126:549ba18ddd81 | 31 | * |
| mbed_official | 126:549ba18ddd81 | 32 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 126:549ba18ddd81 | 33 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 126:549ba18ddd81 | 34 | * |
| mbed_official | 126:549ba18ddd81 | 35 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 126:549ba18ddd81 | 36 | * this list of conditions and the following disclaimer. |
| mbed_official | 126:549ba18ddd81 | 37 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 126:549ba18ddd81 | 38 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 126:549ba18ddd81 | 39 | * and/or other materials provided with the distribution. |
| mbed_official | 126:549ba18ddd81 | 40 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 126:549ba18ddd81 | 41 | * may be used to endorse or promote products derived from this software |
| mbed_official | 126:549ba18ddd81 | 42 | * without specific prior written permission. |
| mbed_official | 126:549ba18ddd81 | 43 | * |
| mbed_official | 126:549ba18ddd81 | 44 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 126:549ba18ddd81 | 45 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 126:549ba18ddd81 | 46 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 126:549ba18ddd81 | 47 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 126:549ba18ddd81 | 48 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 126:549ba18ddd81 | 49 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 126:549ba18ddd81 | 50 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 126:549ba18ddd81 | 51 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 126:549ba18ddd81 | 52 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 126:549ba18ddd81 | 53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 126:549ba18ddd81 | 54 | ******************************************************************************* |
| mbed_official | 126:549ba18ddd81 | 55 | */ |
| mbed_official | 126:549ba18ddd81 | 56 | |
| mbed_official | 126:549ba18ddd81 | 57 | /** @addtogroup CMSIS |
| mbed_official | 126:549ba18ddd81 | 58 | * @{ |
| mbed_official | 126:549ba18ddd81 | 59 | */ |
| mbed_official | 126:549ba18ddd81 | 60 | |
| mbed_official | 126:549ba18ddd81 | 61 | /** @addtogroup stm32f10x |
| mbed_official | 126:549ba18ddd81 | 62 | * @{ |
| mbed_official | 126:549ba18ddd81 | 63 | */ |
| mbed_official | 126:549ba18ddd81 | 64 | |
| mbed_official | 126:549ba18ddd81 | 65 | #ifndef __STM32F10x_H |
| mbed_official | 126:549ba18ddd81 | 66 | #define __STM32F10x_H |
| mbed_official | 126:549ba18ddd81 | 67 | |
| mbed_official | 126:549ba18ddd81 | 68 | #ifdef __cplusplus |
| mbed_official | 126:549ba18ddd81 | 69 | extern "C" { |
| mbed_official | 126:549ba18ddd81 | 70 | #endif /* __cplusplus */ |
| mbed_official | 126:549ba18ddd81 | 71 | |
| mbed_official | 126:549ba18ddd81 | 72 | /** @addtogroup Library_configuration_section |
| mbed_official | 126:549ba18ddd81 | 73 | * @{ |
| mbed_official | 126:549ba18ddd81 | 74 | */ |
| mbed_official | 126:549ba18ddd81 | 75 | |
| mbed_official | 126:549ba18ddd81 | 76 | /* Uncomment the line below according to the target STM32 device used in your |
| mbed_official | 126:549ba18ddd81 | 77 | application |
| mbed_official | 126:549ba18ddd81 | 78 | */ |
| mbed_official | 126:549ba18ddd81 | 79 | |
| mbed_official | 126:549ba18ddd81 | 80 | #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
| mbed_official | 126:549ba18ddd81 | 81 | /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ |
| mbed_official | 126:549ba18ddd81 | 82 | /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ |
| mbed_official | 126:549ba18ddd81 | 83 | /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ |
| mbed_official | 126:549ba18ddd81 | 84 | #define STM32F10X_MD_VL /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ |
| mbed_official | 126:549ba18ddd81 | 85 | /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ |
| mbed_official | 126:549ba18ddd81 | 86 | /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ |
| mbed_official | 126:549ba18ddd81 | 87 | /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ |
| mbed_official | 126:549ba18ddd81 | 88 | /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ |
| mbed_official | 126:549ba18ddd81 | 89 | #endif |
| mbed_official | 126:549ba18ddd81 | 90 | /* Tip: To avoid modifying this file each time you need to switch between these |
| mbed_official | 126:549ba18ddd81 | 91 | devices, you can define the device in your toolchain compiler preprocessor. |
| mbed_official | 126:549ba18ddd81 | 92 | |
| mbed_official | 126:549ba18ddd81 | 93 | - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
| mbed_official | 126:549ba18ddd81 | 94 | where the Flash memory density ranges between 16 and 32 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 95 | - Low-density value line devices are STM32F100xx microcontrollers where the Flash |
| mbed_official | 126:549ba18ddd81 | 96 | memory density ranges between 16 and 32 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 97 | - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
| mbed_official | 126:549ba18ddd81 | 98 | where the Flash memory density ranges between 64 and 128 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 99 | - Medium-density value line devices are STM32F100xx microcontrollers where the |
| mbed_official | 126:549ba18ddd81 | 100 | Flash memory density ranges between 64 and 128 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 101 | - High-density devices are STM32F101xx and STM32F103xx microcontrollers where |
| mbed_official | 126:549ba18ddd81 | 102 | the Flash memory density ranges between 256 and 512 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 103 | - High-density value line devices are STM32F100xx microcontrollers where the |
| mbed_official | 126:549ba18ddd81 | 104 | Flash memory density ranges between 256 and 512 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 105 | - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where |
| mbed_official | 126:549ba18ddd81 | 106 | the Flash memory density ranges between 512 and 1024 Kbytes. |
| mbed_official | 126:549ba18ddd81 | 107 | - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. |
| mbed_official | 126:549ba18ddd81 | 108 | */ |
| mbed_official | 126:549ba18ddd81 | 109 | |
| mbed_official | 126:549ba18ddd81 | 110 | #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
| mbed_official | 126:549ba18ddd81 | 111 | #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" |
| mbed_official | 126:549ba18ddd81 | 112 | #endif |
| mbed_official | 126:549ba18ddd81 | 113 | |
| mbed_official | 126:549ba18ddd81 | 114 | #if !defined (USE_STDPERIPH_DRIVER) |
| mbed_official | 126:549ba18ddd81 | 115 | /** |
| mbed_official | 126:549ba18ddd81 | 116 | * @brief Comment the line below if you will not use the peripherals drivers. |
| mbed_official | 126:549ba18ddd81 | 117 | In this case, these drivers will not be included and the application code will |
| mbed_official | 126:549ba18ddd81 | 118 | be based on direct access to peripherals registers |
| mbed_official | 126:549ba18ddd81 | 119 | */ |
| mbed_official | 126:549ba18ddd81 | 120 | #define USE_STDPERIPH_DRIVER |
| mbed_official | 126:549ba18ddd81 | 121 | #endif /* USE_STDPERIPH_DRIVER */ |
| mbed_official | 126:549ba18ddd81 | 122 | |
| mbed_official | 126:549ba18ddd81 | 123 | /** |
| mbed_official | 126:549ba18ddd81 | 124 | * @brief In the following line adjust the value of External High Speed oscillator (HSE) |
| mbed_official | 126:549ba18ddd81 | 125 | used in your application |
| mbed_official | 126:549ba18ddd81 | 126 | |
| mbed_official | 126:549ba18ddd81 | 127 | Tip: To avoid modifying this file each time you need to use different HSE, you |
| mbed_official | 126:549ba18ddd81 | 128 | can define the HSE value in your toolchain compiler preprocessor. |
| mbed_official | 126:549ba18ddd81 | 129 | */ |
| mbed_official | 126:549ba18ddd81 | 130 | #if !defined HSE_VALUE |
| mbed_official | 126:549ba18ddd81 | 131 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 132 | #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ |
| mbed_official | 126:549ba18ddd81 | 133 | #else |
| mbed_official | 126:549ba18ddd81 | 134 | #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
| mbed_official | 126:549ba18ddd81 | 135 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 136 | #endif /* HSE_VALUE */ |
| mbed_official | 126:549ba18ddd81 | 137 | |
| mbed_official | 126:549ba18ddd81 | 138 | /** |
| mbed_official | 126:549ba18ddd81 | 139 | * @brief In the following line adjust the External High Speed oscillator (HSE) Startup |
| mbed_official | 126:549ba18ddd81 | 140 | Timeout value |
| mbed_official | 126:549ba18ddd81 | 141 | */ |
| mbed_official | 126:549ba18ddd81 | 142 | #if !defined (HSE_STARTUP_TIMEOUT) |
| mbed_official | 126:549ba18ddd81 | 143 | #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ |
| mbed_official | 126:549ba18ddd81 | 144 | #endif /* HSE_STARTUP_TIMEOUT */ |
| mbed_official | 126:549ba18ddd81 | 145 | |
| mbed_official | 126:549ba18ddd81 | 146 | #if !defined (HSI_VALUE) |
| mbed_official | 126:549ba18ddd81 | 147 | #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ |
| mbed_official | 126:549ba18ddd81 | 148 | #endif /* HSI_VALUE */ |
| mbed_official | 126:549ba18ddd81 | 149 | |
| mbed_official | 126:549ba18ddd81 | 150 | /** |
| mbed_official | 126:549ba18ddd81 | 151 | * @brief STM32F10x Standard Peripheral Library version number |
| mbed_official | 126:549ba18ddd81 | 152 | */ |
| mbed_official | 126:549ba18ddd81 | 153 | #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ |
| mbed_official | 126:549ba18ddd81 | 154 | #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ |
| mbed_official | 126:549ba18ddd81 | 155 | #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ |
| mbed_official | 126:549ba18ddd81 | 156 | #define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ |
| mbed_official | 126:549ba18ddd81 | 157 | #define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ |
| mbed_official | 126:549ba18ddd81 | 158 | |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ |
| mbed_official | 126:549ba18ddd81 | 159 | |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ |
| mbed_official | 126:549ba18ddd81 | 160 | |(__STM32F10X_STDPERIPH_VERSION_RC)) |
| mbed_official | 126:549ba18ddd81 | 161 | |
| mbed_official | 126:549ba18ddd81 | 162 | /** |
| mbed_official | 126:549ba18ddd81 | 163 | * @} |
| mbed_official | 126:549ba18ddd81 | 164 | */ |
| mbed_official | 126:549ba18ddd81 | 165 | |
| mbed_official | 126:549ba18ddd81 | 166 | /** @addtogroup Configuration_section_for_CMSIS |
| mbed_official | 126:549ba18ddd81 | 167 | * @{ |
| mbed_official | 126:549ba18ddd81 | 168 | */ |
| mbed_official | 126:549ba18ddd81 | 169 | |
| mbed_official | 126:549ba18ddd81 | 170 | /** |
| mbed_official | 126:549ba18ddd81 | 171 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
| mbed_official | 126:549ba18ddd81 | 172 | */ |
| mbed_official | 126:549ba18ddd81 | 173 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 174 | #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ |
| mbed_official | 126:549ba18ddd81 | 175 | #else |
| mbed_official | 126:549ba18ddd81 | 176 | #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ |
| mbed_official | 126:549ba18ddd81 | 177 | #endif /* STM32F10X_XL */ |
| mbed_official | 126:549ba18ddd81 | 178 | #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ |
| mbed_official | 126:549ba18ddd81 | 179 | #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
| mbed_official | 126:549ba18ddd81 | 180 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| mbed_official | 126:549ba18ddd81 | 181 | |
| mbed_official | 126:549ba18ddd81 | 182 | /** |
| mbed_official | 126:549ba18ddd81 | 183 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
| mbed_official | 126:549ba18ddd81 | 184 | * in @ref Library_configuration_section |
| mbed_official | 126:549ba18ddd81 | 185 | */ |
| mbed_official | 126:549ba18ddd81 | 186 | typedef enum IRQn |
| mbed_official | 126:549ba18ddd81 | 187 | { |
| mbed_official | 126:549ba18ddd81 | 188 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
| mbed_official | 126:549ba18ddd81 | 189 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 190 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 191 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 192 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 193 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 194 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 195 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 196 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 197 | |
| mbed_official | 126:549ba18ddd81 | 198 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
| mbed_official | 126:549ba18ddd81 | 199 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 200 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 201 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 202 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 203 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 204 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 205 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 206 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 207 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 208 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 209 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 210 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 211 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 212 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 213 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 214 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 215 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 216 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 217 | |
| mbed_official | 126:549ba18ddd81 | 218 | #ifdef STM32F10X_LD |
| mbed_official | 126:549ba18ddd81 | 219 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 220 | USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 221 | USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 222 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 223 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 224 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 225 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 226 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 227 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 228 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 229 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 230 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 231 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 232 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 233 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 234 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 235 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 236 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 237 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 238 | USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 239 | #endif /* STM32F10X_LD */ |
| mbed_official | 126:549ba18ddd81 | 240 | |
| mbed_official | 126:549ba18ddd81 | 241 | #ifdef STM32F10X_LD_VL |
| mbed_official | 126:549ba18ddd81 | 242 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 243 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 244 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 245 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 246 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 247 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 248 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 249 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 250 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 251 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 252 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 253 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 254 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 255 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 256 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 257 | CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 258 | TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 259 | TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 260 | #endif /* STM32F10X_LD_VL */ |
| mbed_official | 126:549ba18ddd81 | 261 | |
| mbed_official | 126:549ba18ddd81 | 262 | #ifdef STM32F10X_MD |
| mbed_official | 126:549ba18ddd81 | 263 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 264 | USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 265 | USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 266 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 267 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 268 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 269 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 270 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 271 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 272 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 273 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 274 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 275 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 276 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 277 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 278 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 279 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 280 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 281 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 282 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 283 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 284 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 285 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 286 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 287 | USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 288 | #endif /* STM32F10X_MD */ |
| mbed_official | 126:549ba18ddd81 | 289 | |
| mbed_official | 126:549ba18ddd81 | 290 | #ifdef STM32F10X_MD_VL |
| mbed_official | 126:549ba18ddd81 | 291 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 292 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 293 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 294 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 295 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 296 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 297 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 298 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 299 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 300 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 301 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 302 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 303 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 304 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 305 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 306 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 307 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 308 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 309 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 310 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 311 | CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 312 | TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 313 | TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 314 | #endif /* STM32F10X_MD_VL */ |
| mbed_official | 126:549ba18ddd81 | 315 | |
| mbed_official | 126:549ba18ddd81 | 316 | #ifdef STM32F10X_HD |
| mbed_official | 126:549ba18ddd81 | 317 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 318 | USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 319 | USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 320 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 321 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 322 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 323 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 324 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 325 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 326 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 327 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 328 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 329 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 330 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 331 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 332 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 333 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 334 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 335 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 336 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 337 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 338 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 339 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 340 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 341 | USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 342 | TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 343 | TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 344 | TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 345 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 346 | ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 347 | FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 348 | SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 349 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 350 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 351 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 352 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 353 | TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 354 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 355 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 356 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 357 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 358 | DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 359 | #endif /* STM32F10X_HD */ |
| mbed_official | 126:549ba18ddd81 | 360 | |
| mbed_official | 126:549ba18ddd81 | 361 | #ifdef STM32F10X_HD_VL |
| mbed_official | 126:549ba18ddd81 | 362 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 363 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 364 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 365 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 366 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 367 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 368 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 369 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 370 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 371 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 372 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 373 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 374 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 375 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 376 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 377 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 378 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 379 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 380 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 381 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 382 | CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 383 | TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 384 | TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 385 | TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 386 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 387 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 388 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 389 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 390 | TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 391 | TIM7_IRQn = 55, /*!< TIM7 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 392 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 393 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 394 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 395 | DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 396 | DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is |
| mbed_official | 126:549ba18ddd81 | 397 | mapped at position 60 only if the MISC_REMAP bit in |
| mbed_official | 126:549ba18ddd81 | 398 | the AFIO_MAPR2 register is set) */ |
| mbed_official | 126:549ba18ddd81 | 399 | #endif /* STM32F10X_HD_VL */ |
| mbed_official | 126:549ba18ddd81 | 400 | |
| mbed_official | 126:549ba18ddd81 | 401 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 402 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 403 | USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 404 | USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 405 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 406 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 407 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 408 | TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 409 | TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 410 | TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
| mbed_official | 126:549ba18ddd81 | 411 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 412 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 413 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 414 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 415 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 416 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 417 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 418 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 419 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 420 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 421 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 422 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 423 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 424 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 425 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 426 | USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 427 | TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 428 | TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 429 | TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
| mbed_official | 126:549ba18ddd81 | 430 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 431 | ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 432 | FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 433 | SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 434 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 435 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 436 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 437 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 438 | TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 439 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 440 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 441 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 442 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 443 | DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 444 | #endif /* STM32F10X_XL */ |
| mbed_official | 126:549ba18ddd81 | 445 | |
| mbed_official | 126:549ba18ddd81 | 446 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 447 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 448 | CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 449 | CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 450 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 451 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 452 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 453 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 454 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 455 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 456 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 457 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 458 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 459 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 460 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 461 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 462 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 463 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 464 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 465 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 466 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 467 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 468 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 469 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 126:549ba18ddd81 | 470 | RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 471 | OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 472 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 473 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 474 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 475 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 476 | TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 477 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 478 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 479 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 480 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 481 | DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 482 | DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 483 | ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 484 | ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 485 | CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 486 | CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 487 | CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 488 | CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 489 | OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 490 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 491 | } IRQn_Type; |
| mbed_official | 126:549ba18ddd81 | 492 | |
| mbed_official | 126:549ba18ddd81 | 493 | /** |
| mbed_official | 126:549ba18ddd81 | 494 | * @} |
| mbed_official | 126:549ba18ddd81 | 495 | */ |
| mbed_official | 126:549ba18ddd81 | 496 | |
| mbed_official | 126:549ba18ddd81 | 497 | #include "core_cm3.h" |
| mbed_official | 126:549ba18ddd81 | 498 | #include "system_stm32f10x.h" |
| mbed_official | 126:549ba18ddd81 | 499 | #include <stdint.h> |
| mbed_official | 126:549ba18ddd81 | 500 | |
| mbed_official | 126:549ba18ddd81 | 501 | /** @addtogroup Exported_types |
| mbed_official | 126:549ba18ddd81 | 502 | * @{ |
| mbed_official | 126:549ba18ddd81 | 503 | */ |
| mbed_official | 126:549ba18ddd81 | 504 | |
| mbed_official | 126:549ba18ddd81 | 505 | /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ |
| mbed_official | 126:549ba18ddd81 | 506 | typedef int32_t s32; |
| mbed_official | 126:549ba18ddd81 | 507 | typedef int16_t s16; |
| mbed_official | 126:549ba18ddd81 | 508 | typedef int8_t s8; |
| mbed_official | 126:549ba18ddd81 | 509 | |
| mbed_official | 126:549ba18ddd81 | 510 | typedef const int32_t sc32; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 511 | typedef const int16_t sc16; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 512 | typedef const int8_t sc8; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 513 | |
| mbed_official | 126:549ba18ddd81 | 514 | typedef __IO int32_t vs32; |
| mbed_official | 126:549ba18ddd81 | 515 | typedef __IO int16_t vs16; |
| mbed_official | 126:549ba18ddd81 | 516 | typedef __IO int8_t vs8; |
| mbed_official | 126:549ba18ddd81 | 517 | |
| mbed_official | 126:549ba18ddd81 | 518 | typedef __I int32_t vsc32; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 519 | typedef __I int16_t vsc16; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 520 | typedef __I int8_t vsc8; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 521 | |
| mbed_official | 126:549ba18ddd81 | 522 | typedef uint32_t u32; |
| mbed_official | 126:549ba18ddd81 | 523 | typedef uint16_t u16; |
| mbed_official | 126:549ba18ddd81 | 524 | typedef uint8_t u8; |
| mbed_official | 126:549ba18ddd81 | 525 | |
| mbed_official | 126:549ba18ddd81 | 526 | typedef const uint32_t uc32; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 527 | typedef const uint16_t uc16; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 528 | typedef const uint8_t uc8; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 529 | |
| mbed_official | 126:549ba18ddd81 | 530 | typedef __IO uint32_t vu32; |
| mbed_official | 126:549ba18ddd81 | 531 | typedef __IO uint16_t vu16; |
| mbed_official | 126:549ba18ddd81 | 532 | typedef __IO uint8_t vu8; |
| mbed_official | 126:549ba18ddd81 | 533 | |
| mbed_official | 126:549ba18ddd81 | 534 | typedef __I uint32_t vuc32; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 535 | typedef __I uint16_t vuc16; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 536 | typedef __I uint8_t vuc8; /*!< Read Only */ |
| mbed_official | 126:549ba18ddd81 | 537 | |
| mbed_official | 126:549ba18ddd81 | 538 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; |
| mbed_official | 126:549ba18ddd81 | 539 | |
| mbed_official | 126:549ba18ddd81 | 540 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; |
| mbed_official | 126:549ba18ddd81 | 541 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
| mbed_official | 126:549ba18ddd81 | 542 | |
| mbed_official | 126:549ba18ddd81 | 543 | typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; |
| mbed_official | 126:549ba18ddd81 | 544 | |
| mbed_official | 126:549ba18ddd81 | 545 | /*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ |
| mbed_official | 126:549ba18ddd81 | 546 | #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT |
| mbed_official | 126:549ba18ddd81 | 547 | #define HSE_Value HSE_VALUE |
| mbed_official | 126:549ba18ddd81 | 548 | #define HSI_Value HSI_VALUE |
| mbed_official | 126:549ba18ddd81 | 549 | /** |
| mbed_official | 126:549ba18ddd81 | 550 | * @} |
| mbed_official | 126:549ba18ddd81 | 551 | */ |
| mbed_official | 126:549ba18ddd81 | 552 | |
| mbed_official | 126:549ba18ddd81 | 553 | /** @addtogroup Peripheral_registers_structures |
| mbed_official | 126:549ba18ddd81 | 554 | * @{ |
| mbed_official | 126:549ba18ddd81 | 555 | */ |
| mbed_official | 126:549ba18ddd81 | 556 | |
| mbed_official | 126:549ba18ddd81 | 557 | /** |
| mbed_official | 126:549ba18ddd81 | 558 | * @brief Analog to Digital Converter |
| mbed_official | 126:549ba18ddd81 | 559 | */ |
| mbed_official | 126:549ba18ddd81 | 560 | |
| mbed_official | 126:549ba18ddd81 | 561 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 562 | { |
| mbed_official | 126:549ba18ddd81 | 563 | __IO uint32_t SR; |
| mbed_official | 126:549ba18ddd81 | 564 | __IO uint32_t CR1; |
| mbed_official | 126:549ba18ddd81 | 565 | __IO uint32_t CR2; |
| mbed_official | 126:549ba18ddd81 | 566 | __IO uint32_t SMPR1; |
| mbed_official | 126:549ba18ddd81 | 567 | __IO uint32_t SMPR2; |
| mbed_official | 126:549ba18ddd81 | 568 | __IO uint32_t JOFR1; |
| mbed_official | 126:549ba18ddd81 | 569 | __IO uint32_t JOFR2; |
| mbed_official | 126:549ba18ddd81 | 570 | __IO uint32_t JOFR3; |
| mbed_official | 126:549ba18ddd81 | 571 | __IO uint32_t JOFR4; |
| mbed_official | 126:549ba18ddd81 | 572 | __IO uint32_t HTR; |
| mbed_official | 126:549ba18ddd81 | 573 | __IO uint32_t LTR; |
| mbed_official | 126:549ba18ddd81 | 574 | __IO uint32_t SQR1; |
| mbed_official | 126:549ba18ddd81 | 575 | __IO uint32_t SQR2; |
| mbed_official | 126:549ba18ddd81 | 576 | __IO uint32_t SQR3; |
| mbed_official | 126:549ba18ddd81 | 577 | __IO uint32_t JSQR; |
| mbed_official | 126:549ba18ddd81 | 578 | __IO uint32_t JDR1; |
| mbed_official | 126:549ba18ddd81 | 579 | __IO uint32_t JDR2; |
| mbed_official | 126:549ba18ddd81 | 580 | __IO uint32_t JDR3; |
| mbed_official | 126:549ba18ddd81 | 581 | __IO uint32_t JDR4; |
| mbed_official | 126:549ba18ddd81 | 582 | __IO uint32_t DR; |
| mbed_official | 126:549ba18ddd81 | 583 | } ADC_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 584 | |
| mbed_official | 126:549ba18ddd81 | 585 | /** |
| mbed_official | 126:549ba18ddd81 | 586 | * @brief Backup Registers |
| mbed_official | 126:549ba18ddd81 | 587 | */ |
| mbed_official | 126:549ba18ddd81 | 588 | |
| mbed_official | 126:549ba18ddd81 | 589 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 590 | { |
| mbed_official | 126:549ba18ddd81 | 591 | uint32_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 592 | __IO uint16_t DR1; |
| mbed_official | 126:549ba18ddd81 | 593 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 594 | __IO uint16_t DR2; |
| mbed_official | 126:549ba18ddd81 | 595 | uint16_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 596 | __IO uint16_t DR3; |
| mbed_official | 126:549ba18ddd81 | 597 | uint16_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 598 | __IO uint16_t DR4; |
| mbed_official | 126:549ba18ddd81 | 599 | uint16_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 600 | __IO uint16_t DR5; |
| mbed_official | 126:549ba18ddd81 | 601 | uint16_t RESERVED5; |
| mbed_official | 126:549ba18ddd81 | 602 | __IO uint16_t DR6; |
| mbed_official | 126:549ba18ddd81 | 603 | uint16_t RESERVED6; |
| mbed_official | 126:549ba18ddd81 | 604 | __IO uint16_t DR7; |
| mbed_official | 126:549ba18ddd81 | 605 | uint16_t RESERVED7; |
| mbed_official | 126:549ba18ddd81 | 606 | __IO uint16_t DR8; |
| mbed_official | 126:549ba18ddd81 | 607 | uint16_t RESERVED8; |
| mbed_official | 126:549ba18ddd81 | 608 | __IO uint16_t DR9; |
| mbed_official | 126:549ba18ddd81 | 609 | uint16_t RESERVED9; |
| mbed_official | 126:549ba18ddd81 | 610 | __IO uint16_t DR10; |
| mbed_official | 126:549ba18ddd81 | 611 | uint16_t RESERVED10; |
| mbed_official | 126:549ba18ddd81 | 612 | __IO uint16_t RTCCR; |
| mbed_official | 126:549ba18ddd81 | 613 | uint16_t RESERVED11; |
| mbed_official | 126:549ba18ddd81 | 614 | __IO uint16_t CR; |
| mbed_official | 126:549ba18ddd81 | 615 | uint16_t RESERVED12; |
| mbed_official | 126:549ba18ddd81 | 616 | __IO uint16_t CSR; |
| mbed_official | 126:549ba18ddd81 | 617 | uint16_t RESERVED13[5]; |
| mbed_official | 126:549ba18ddd81 | 618 | __IO uint16_t DR11; |
| mbed_official | 126:549ba18ddd81 | 619 | uint16_t RESERVED14; |
| mbed_official | 126:549ba18ddd81 | 620 | __IO uint16_t DR12; |
| mbed_official | 126:549ba18ddd81 | 621 | uint16_t RESERVED15; |
| mbed_official | 126:549ba18ddd81 | 622 | __IO uint16_t DR13; |
| mbed_official | 126:549ba18ddd81 | 623 | uint16_t RESERVED16; |
| mbed_official | 126:549ba18ddd81 | 624 | __IO uint16_t DR14; |
| mbed_official | 126:549ba18ddd81 | 625 | uint16_t RESERVED17; |
| mbed_official | 126:549ba18ddd81 | 626 | __IO uint16_t DR15; |
| mbed_official | 126:549ba18ddd81 | 627 | uint16_t RESERVED18; |
| mbed_official | 126:549ba18ddd81 | 628 | __IO uint16_t DR16; |
| mbed_official | 126:549ba18ddd81 | 629 | uint16_t RESERVED19; |
| mbed_official | 126:549ba18ddd81 | 630 | __IO uint16_t DR17; |
| mbed_official | 126:549ba18ddd81 | 631 | uint16_t RESERVED20; |
| mbed_official | 126:549ba18ddd81 | 632 | __IO uint16_t DR18; |
| mbed_official | 126:549ba18ddd81 | 633 | uint16_t RESERVED21; |
| mbed_official | 126:549ba18ddd81 | 634 | __IO uint16_t DR19; |
| mbed_official | 126:549ba18ddd81 | 635 | uint16_t RESERVED22; |
| mbed_official | 126:549ba18ddd81 | 636 | __IO uint16_t DR20; |
| mbed_official | 126:549ba18ddd81 | 637 | uint16_t RESERVED23; |
| mbed_official | 126:549ba18ddd81 | 638 | __IO uint16_t DR21; |
| mbed_official | 126:549ba18ddd81 | 639 | uint16_t RESERVED24; |
| mbed_official | 126:549ba18ddd81 | 640 | __IO uint16_t DR22; |
| mbed_official | 126:549ba18ddd81 | 641 | uint16_t RESERVED25; |
| mbed_official | 126:549ba18ddd81 | 642 | __IO uint16_t DR23; |
| mbed_official | 126:549ba18ddd81 | 643 | uint16_t RESERVED26; |
| mbed_official | 126:549ba18ddd81 | 644 | __IO uint16_t DR24; |
| mbed_official | 126:549ba18ddd81 | 645 | uint16_t RESERVED27; |
| mbed_official | 126:549ba18ddd81 | 646 | __IO uint16_t DR25; |
| mbed_official | 126:549ba18ddd81 | 647 | uint16_t RESERVED28; |
| mbed_official | 126:549ba18ddd81 | 648 | __IO uint16_t DR26; |
| mbed_official | 126:549ba18ddd81 | 649 | uint16_t RESERVED29; |
| mbed_official | 126:549ba18ddd81 | 650 | __IO uint16_t DR27; |
| mbed_official | 126:549ba18ddd81 | 651 | uint16_t RESERVED30; |
| mbed_official | 126:549ba18ddd81 | 652 | __IO uint16_t DR28; |
| mbed_official | 126:549ba18ddd81 | 653 | uint16_t RESERVED31; |
| mbed_official | 126:549ba18ddd81 | 654 | __IO uint16_t DR29; |
| mbed_official | 126:549ba18ddd81 | 655 | uint16_t RESERVED32; |
| mbed_official | 126:549ba18ddd81 | 656 | __IO uint16_t DR30; |
| mbed_official | 126:549ba18ddd81 | 657 | uint16_t RESERVED33; |
| mbed_official | 126:549ba18ddd81 | 658 | __IO uint16_t DR31; |
| mbed_official | 126:549ba18ddd81 | 659 | uint16_t RESERVED34; |
| mbed_official | 126:549ba18ddd81 | 660 | __IO uint16_t DR32; |
| mbed_official | 126:549ba18ddd81 | 661 | uint16_t RESERVED35; |
| mbed_official | 126:549ba18ddd81 | 662 | __IO uint16_t DR33; |
| mbed_official | 126:549ba18ddd81 | 663 | uint16_t RESERVED36; |
| mbed_official | 126:549ba18ddd81 | 664 | __IO uint16_t DR34; |
| mbed_official | 126:549ba18ddd81 | 665 | uint16_t RESERVED37; |
| mbed_official | 126:549ba18ddd81 | 666 | __IO uint16_t DR35; |
| mbed_official | 126:549ba18ddd81 | 667 | uint16_t RESERVED38; |
| mbed_official | 126:549ba18ddd81 | 668 | __IO uint16_t DR36; |
| mbed_official | 126:549ba18ddd81 | 669 | uint16_t RESERVED39; |
| mbed_official | 126:549ba18ddd81 | 670 | __IO uint16_t DR37; |
| mbed_official | 126:549ba18ddd81 | 671 | uint16_t RESERVED40; |
| mbed_official | 126:549ba18ddd81 | 672 | __IO uint16_t DR38; |
| mbed_official | 126:549ba18ddd81 | 673 | uint16_t RESERVED41; |
| mbed_official | 126:549ba18ddd81 | 674 | __IO uint16_t DR39; |
| mbed_official | 126:549ba18ddd81 | 675 | uint16_t RESERVED42; |
| mbed_official | 126:549ba18ddd81 | 676 | __IO uint16_t DR40; |
| mbed_official | 126:549ba18ddd81 | 677 | uint16_t RESERVED43; |
| mbed_official | 126:549ba18ddd81 | 678 | __IO uint16_t DR41; |
| mbed_official | 126:549ba18ddd81 | 679 | uint16_t RESERVED44; |
| mbed_official | 126:549ba18ddd81 | 680 | __IO uint16_t DR42; |
| mbed_official | 126:549ba18ddd81 | 681 | uint16_t RESERVED45; |
| mbed_official | 126:549ba18ddd81 | 682 | } BKP_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 683 | |
| mbed_official | 126:549ba18ddd81 | 684 | /** |
| mbed_official | 126:549ba18ddd81 | 685 | * @brief Controller Area Network TxMailBox |
| mbed_official | 126:549ba18ddd81 | 686 | */ |
| mbed_official | 126:549ba18ddd81 | 687 | |
| mbed_official | 126:549ba18ddd81 | 688 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 689 | { |
| mbed_official | 126:549ba18ddd81 | 690 | __IO uint32_t TIR; |
| mbed_official | 126:549ba18ddd81 | 691 | __IO uint32_t TDTR; |
| mbed_official | 126:549ba18ddd81 | 692 | __IO uint32_t TDLR; |
| mbed_official | 126:549ba18ddd81 | 693 | __IO uint32_t TDHR; |
| mbed_official | 126:549ba18ddd81 | 694 | } CAN_TxMailBox_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 695 | |
| mbed_official | 126:549ba18ddd81 | 696 | /** |
| mbed_official | 126:549ba18ddd81 | 697 | * @brief Controller Area Network FIFOMailBox |
| mbed_official | 126:549ba18ddd81 | 698 | */ |
| mbed_official | 126:549ba18ddd81 | 699 | |
| mbed_official | 126:549ba18ddd81 | 700 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 701 | { |
| mbed_official | 126:549ba18ddd81 | 702 | __IO uint32_t RIR; |
| mbed_official | 126:549ba18ddd81 | 703 | __IO uint32_t RDTR; |
| mbed_official | 126:549ba18ddd81 | 704 | __IO uint32_t RDLR; |
| mbed_official | 126:549ba18ddd81 | 705 | __IO uint32_t RDHR; |
| mbed_official | 126:549ba18ddd81 | 706 | } CAN_FIFOMailBox_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 707 | |
| mbed_official | 126:549ba18ddd81 | 708 | /** |
| mbed_official | 126:549ba18ddd81 | 709 | * @brief Controller Area Network FilterRegister |
| mbed_official | 126:549ba18ddd81 | 710 | */ |
| mbed_official | 126:549ba18ddd81 | 711 | |
| mbed_official | 126:549ba18ddd81 | 712 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 713 | { |
| mbed_official | 126:549ba18ddd81 | 714 | __IO uint32_t FR1; |
| mbed_official | 126:549ba18ddd81 | 715 | __IO uint32_t FR2; |
| mbed_official | 126:549ba18ddd81 | 716 | } CAN_FilterRegister_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 717 | |
| mbed_official | 126:549ba18ddd81 | 718 | /** |
| mbed_official | 126:549ba18ddd81 | 719 | * @brief Controller Area Network |
| mbed_official | 126:549ba18ddd81 | 720 | */ |
| mbed_official | 126:549ba18ddd81 | 721 | |
| mbed_official | 126:549ba18ddd81 | 722 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 723 | { |
| mbed_official | 126:549ba18ddd81 | 724 | __IO uint32_t MCR; |
| mbed_official | 126:549ba18ddd81 | 725 | __IO uint32_t MSR; |
| mbed_official | 126:549ba18ddd81 | 726 | __IO uint32_t TSR; |
| mbed_official | 126:549ba18ddd81 | 727 | __IO uint32_t RF0R; |
| mbed_official | 126:549ba18ddd81 | 728 | __IO uint32_t RF1R; |
| mbed_official | 126:549ba18ddd81 | 729 | __IO uint32_t IER; |
| mbed_official | 126:549ba18ddd81 | 730 | __IO uint32_t ESR; |
| mbed_official | 126:549ba18ddd81 | 731 | __IO uint32_t BTR; |
| mbed_official | 126:549ba18ddd81 | 732 | uint32_t RESERVED0[88]; |
| mbed_official | 126:549ba18ddd81 | 733 | CAN_TxMailBox_TypeDef sTxMailBox[3]; |
| mbed_official | 126:549ba18ddd81 | 734 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
| mbed_official | 126:549ba18ddd81 | 735 | uint32_t RESERVED1[12]; |
| mbed_official | 126:549ba18ddd81 | 736 | __IO uint32_t FMR; |
| mbed_official | 126:549ba18ddd81 | 737 | __IO uint32_t FM1R; |
| mbed_official | 126:549ba18ddd81 | 738 | uint32_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 739 | __IO uint32_t FS1R; |
| mbed_official | 126:549ba18ddd81 | 740 | uint32_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 741 | __IO uint32_t FFA1R; |
| mbed_official | 126:549ba18ddd81 | 742 | uint32_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 743 | __IO uint32_t FA1R; |
| mbed_official | 126:549ba18ddd81 | 744 | uint32_t RESERVED5[8]; |
| mbed_official | 126:549ba18ddd81 | 745 | #ifndef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 746 | CAN_FilterRegister_TypeDef sFilterRegister[14]; |
| mbed_official | 126:549ba18ddd81 | 747 | #else |
| mbed_official | 126:549ba18ddd81 | 748 | CAN_FilterRegister_TypeDef sFilterRegister[28]; |
| mbed_official | 126:549ba18ddd81 | 749 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 750 | } CAN_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 751 | |
| mbed_official | 126:549ba18ddd81 | 752 | /** |
| mbed_official | 126:549ba18ddd81 | 753 | * @brief Consumer Electronics Control (CEC) |
| mbed_official | 126:549ba18ddd81 | 754 | */ |
| mbed_official | 126:549ba18ddd81 | 755 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 756 | { |
| mbed_official | 126:549ba18ddd81 | 757 | __IO uint32_t CFGR; |
| mbed_official | 126:549ba18ddd81 | 758 | __IO uint32_t OAR; |
| mbed_official | 126:549ba18ddd81 | 759 | __IO uint32_t PRES; |
| mbed_official | 126:549ba18ddd81 | 760 | __IO uint32_t ESR; |
| mbed_official | 126:549ba18ddd81 | 761 | __IO uint32_t CSR; |
| mbed_official | 126:549ba18ddd81 | 762 | __IO uint32_t TXD; |
| mbed_official | 126:549ba18ddd81 | 763 | __IO uint32_t RXD; |
| mbed_official | 126:549ba18ddd81 | 764 | } CEC_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 765 | |
| mbed_official | 126:549ba18ddd81 | 766 | /** |
| mbed_official | 126:549ba18ddd81 | 767 | * @brief CRC calculation unit |
| mbed_official | 126:549ba18ddd81 | 768 | */ |
| mbed_official | 126:549ba18ddd81 | 769 | |
| mbed_official | 126:549ba18ddd81 | 770 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 771 | { |
| mbed_official | 126:549ba18ddd81 | 772 | __IO uint32_t DR; |
| mbed_official | 126:549ba18ddd81 | 773 | __IO uint8_t IDR; |
| mbed_official | 126:549ba18ddd81 | 774 | uint8_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 775 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 776 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 777 | } CRC_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 778 | |
| mbed_official | 126:549ba18ddd81 | 779 | /** |
| mbed_official | 126:549ba18ddd81 | 780 | * @brief Digital to Analog Converter |
| mbed_official | 126:549ba18ddd81 | 781 | */ |
| mbed_official | 126:549ba18ddd81 | 782 | |
| mbed_official | 126:549ba18ddd81 | 783 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 784 | { |
| mbed_official | 126:549ba18ddd81 | 785 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 786 | __IO uint32_t SWTRIGR; |
| mbed_official | 126:549ba18ddd81 | 787 | __IO uint32_t DHR12R1; |
| mbed_official | 126:549ba18ddd81 | 788 | __IO uint32_t DHR12L1; |
| mbed_official | 126:549ba18ddd81 | 789 | __IO uint32_t DHR8R1; |
| mbed_official | 126:549ba18ddd81 | 790 | __IO uint32_t DHR12R2; |
| mbed_official | 126:549ba18ddd81 | 791 | __IO uint32_t DHR12L2; |
| mbed_official | 126:549ba18ddd81 | 792 | __IO uint32_t DHR8R2; |
| mbed_official | 126:549ba18ddd81 | 793 | __IO uint32_t DHR12RD; |
| mbed_official | 126:549ba18ddd81 | 794 | __IO uint32_t DHR12LD; |
| mbed_official | 126:549ba18ddd81 | 795 | __IO uint32_t DHR8RD; |
| mbed_official | 126:549ba18ddd81 | 796 | __IO uint32_t DOR1; |
| mbed_official | 126:549ba18ddd81 | 797 | __IO uint32_t DOR2; |
| mbed_official | 126:549ba18ddd81 | 798 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 799 | __IO uint32_t SR; |
| mbed_official | 126:549ba18ddd81 | 800 | #endif |
| mbed_official | 126:549ba18ddd81 | 801 | } DAC_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 802 | |
| mbed_official | 126:549ba18ddd81 | 803 | /** |
| mbed_official | 126:549ba18ddd81 | 804 | * @brief Debug MCU |
| mbed_official | 126:549ba18ddd81 | 805 | */ |
| mbed_official | 126:549ba18ddd81 | 806 | |
| mbed_official | 126:549ba18ddd81 | 807 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 808 | { |
| mbed_official | 126:549ba18ddd81 | 809 | __IO uint32_t IDCODE; |
| mbed_official | 126:549ba18ddd81 | 810 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 811 | }DBGMCU_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 812 | |
| mbed_official | 126:549ba18ddd81 | 813 | /** |
| mbed_official | 126:549ba18ddd81 | 814 | * @brief DMA Controller |
| mbed_official | 126:549ba18ddd81 | 815 | */ |
| mbed_official | 126:549ba18ddd81 | 816 | |
| mbed_official | 126:549ba18ddd81 | 817 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 818 | { |
| mbed_official | 126:549ba18ddd81 | 819 | __IO uint32_t CCR; |
| mbed_official | 126:549ba18ddd81 | 820 | __IO uint32_t CNDTR; |
| mbed_official | 126:549ba18ddd81 | 821 | __IO uint32_t CPAR; |
| mbed_official | 126:549ba18ddd81 | 822 | __IO uint32_t CMAR; |
| mbed_official | 126:549ba18ddd81 | 823 | } DMA_Channel_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 824 | |
| mbed_official | 126:549ba18ddd81 | 825 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 826 | { |
| mbed_official | 126:549ba18ddd81 | 827 | __IO uint32_t ISR; |
| mbed_official | 126:549ba18ddd81 | 828 | __IO uint32_t IFCR; |
| mbed_official | 126:549ba18ddd81 | 829 | } DMA_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 830 | |
| mbed_official | 126:549ba18ddd81 | 831 | /** |
| mbed_official | 126:549ba18ddd81 | 832 | * @brief Ethernet MAC |
| mbed_official | 126:549ba18ddd81 | 833 | */ |
| mbed_official | 126:549ba18ddd81 | 834 | |
| mbed_official | 126:549ba18ddd81 | 835 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 836 | { |
| mbed_official | 126:549ba18ddd81 | 837 | __IO uint32_t MACCR; |
| mbed_official | 126:549ba18ddd81 | 838 | __IO uint32_t MACFFR; |
| mbed_official | 126:549ba18ddd81 | 839 | __IO uint32_t MACHTHR; |
| mbed_official | 126:549ba18ddd81 | 840 | __IO uint32_t MACHTLR; |
| mbed_official | 126:549ba18ddd81 | 841 | __IO uint32_t MACMIIAR; |
| mbed_official | 126:549ba18ddd81 | 842 | __IO uint32_t MACMIIDR; |
| mbed_official | 126:549ba18ddd81 | 843 | __IO uint32_t MACFCR; |
| mbed_official | 126:549ba18ddd81 | 844 | __IO uint32_t MACVLANTR; /* 8 */ |
| mbed_official | 126:549ba18ddd81 | 845 | uint32_t RESERVED0[2]; |
| mbed_official | 126:549ba18ddd81 | 846 | __IO uint32_t MACRWUFFR; /* 11 */ |
| mbed_official | 126:549ba18ddd81 | 847 | __IO uint32_t MACPMTCSR; |
| mbed_official | 126:549ba18ddd81 | 848 | uint32_t RESERVED1[2]; |
| mbed_official | 126:549ba18ddd81 | 849 | __IO uint32_t MACSR; /* 15 */ |
| mbed_official | 126:549ba18ddd81 | 850 | __IO uint32_t MACIMR; |
| mbed_official | 126:549ba18ddd81 | 851 | __IO uint32_t MACA0HR; |
| mbed_official | 126:549ba18ddd81 | 852 | __IO uint32_t MACA0LR; |
| mbed_official | 126:549ba18ddd81 | 853 | __IO uint32_t MACA1HR; |
| mbed_official | 126:549ba18ddd81 | 854 | __IO uint32_t MACA1LR; |
| mbed_official | 126:549ba18ddd81 | 855 | __IO uint32_t MACA2HR; |
| mbed_official | 126:549ba18ddd81 | 856 | __IO uint32_t MACA2LR; |
| mbed_official | 126:549ba18ddd81 | 857 | __IO uint32_t MACA3HR; |
| mbed_official | 126:549ba18ddd81 | 858 | __IO uint32_t MACA3LR; /* 24 */ |
| mbed_official | 126:549ba18ddd81 | 859 | uint32_t RESERVED2[40]; |
| mbed_official | 126:549ba18ddd81 | 860 | __IO uint32_t MMCCR; /* 65 */ |
| mbed_official | 126:549ba18ddd81 | 861 | __IO uint32_t MMCRIR; |
| mbed_official | 126:549ba18ddd81 | 862 | __IO uint32_t MMCTIR; |
| mbed_official | 126:549ba18ddd81 | 863 | __IO uint32_t MMCRIMR; |
| mbed_official | 126:549ba18ddd81 | 864 | __IO uint32_t MMCTIMR; /* 69 */ |
| mbed_official | 126:549ba18ddd81 | 865 | uint32_t RESERVED3[14]; |
| mbed_official | 126:549ba18ddd81 | 866 | __IO uint32_t MMCTGFSCCR; /* 84 */ |
| mbed_official | 126:549ba18ddd81 | 867 | __IO uint32_t MMCTGFMSCCR; |
| mbed_official | 126:549ba18ddd81 | 868 | uint32_t RESERVED4[5]; |
| mbed_official | 126:549ba18ddd81 | 869 | __IO uint32_t MMCTGFCR; |
| mbed_official | 126:549ba18ddd81 | 870 | uint32_t RESERVED5[10]; |
| mbed_official | 126:549ba18ddd81 | 871 | __IO uint32_t MMCRFCECR; |
| mbed_official | 126:549ba18ddd81 | 872 | __IO uint32_t MMCRFAECR; |
| mbed_official | 126:549ba18ddd81 | 873 | uint32_t RESERVED6[10]; |
| mbed_official | 126:549ba18ddd81 | 874 | __IO uint32_t MMCRGUFCR; |
| mbed_official | 126:549ba18ddd81 | 875 | uint32_t RESERVED7[334]; |
| mbed_official | 126:549ba18ddd81 | 876 | __IO uint32_t PTPTSCR; |
| mbed_official | 126:549ba18ddd81 | 877 | __IO uint32_t PTPSSIR; |
| mbed_official | 126:549ba18ddd81 | 878 | __IO uint32_t PTPTSHR; |
| mbed_official | 126:549ba18ddd81 | 879 | __IO uint32_t PTPTSLR; |
| mbed_official | 126:549ba18ddd81 | 880 | __IO uint32_t PTPTSHUR; |
| mbed_official | 126:549ba18ddd81 | 881 | __IO uint32_t PTPTSLUR; |
| mbed_official | 126:549ba18ddd81 | 882 | __IO uint32_t PTPTSAR; |
| mbed_official | 126:549ba18ddd81 | 883 | __IO uint32_t PTPTTHR; |
| mbed_official | 126:549ba18ddd81 | 884 | __IO uint32_t PTPTTLR; |
| mbed_official | 126:549ba18ddd81 | 885 | uint32_t RESERVED8[567]; |
| mbed_official | 126:549ba18ddd81 | 886 | __IO uint32_t DMABMR; |
| mbed_official | 126:549ba18ddd81 | 887 | __IO uint32_t DMATPDR; |
| mbed_official | 126:549ba18ddd81 | 888 | __IO uint32_t DMARPDR; |
| mbed_official | 126:549ba18ddd81 | 889 | __IO uint32_t DMARDLAR; |
| mbed_official | 126:549ba18ddd81 | 890 | __IO uint32_t DMATDLAR; |
| mbed_official | 126:549ba18ddd81 | 891 | __IO uint32_t DMASR; |
| mbed_official | 126:549ba18ddd81 | 892 | __IO uint32_t DMAOMR; |
| mbed_official | 126:549ba18ddd81 | 893 | __IO uint32_t DMAIER; |
| mbed_official | 126:549ba18ddd81 | 894 | __IO uint32_t DMAMFBOCR; |
| mbed_official | 126:549ba18ddd81 | 895 | uint32_t RESERVED9[9]; |
| mbed_official | 126:549ba18ddd81 | 896 | __IO uint32_t DMACHTDR; |
| mbed_official | 126:549ba18ddd81 | 897 | __IO uint32_t DMACHRDR; |
| mbed_official | 126:549ba18ddd81 | 898 | __IO uint32_t DMACHTBAR; |
| mbed_official | 126:549ba18ddd81 | 899 | __IO uint32_t DMACHRBAR; |
| mbed_official | 126:549ba18ddd81 | 900 | } ETH_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 901 | |
| mbed_official | 126:549ba18ddd81 | 902 | /** |
| mbed_official | 126:549ba18ddd81 | 903 | * @brief External Interrupt/Event Controller |
| mbed_official | 126:549ba18ddd81 | 904 | */ |
| mbed_official | 126:549ba18ddd81 | 905 | |
| mbed_official | 126:549ba18ddd81 | 906 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 907 | { |
| mbed_official | 126:549ba18ddd81 | 908 | __IO uint32_t IMR; |
| mbed_official | 126:549ba18ddd81 | 909 | __IO uint32_t EMR; |
| mbed_official | 126:549ba18ddd81 | 910 | __IO uint32_t RTSR; |
| mbed_official | 126:549ba18ddd81 | 911 | __IO uint32_t FTSR; |
| mbed_official | 126:549ba18ddd81 | 912 | __IO uint32_t SWIER; |
| mbed_official | 126:549ba18ddd81 | 913 | __IO uint32_t PR; |
| mbed_official | 126:549ba18ddd81 | 914 | } EXTI_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 915 | |
| mbed_official | 126:549ba18ddd81 | 916 | /** |
| mbed_official | 126:549ba18ddd81 | 917 | * @brief FLASH Registers |
| mbed_official | 126:549ba18ddd81 | 918 | */ |
| mbed_official | 126:549ba18ddd81 | 919 | |
| mbed_official | 126:549ba18ddd81 | 920 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 921 | { |
| mbed_official | 126:549ba18ddd81 | 922 | __IO uint32_t ACR; |
| mbed_official | 126:549ba18ddd81 | 923 | __IO uint32_t KEYR; |
| mbed_official | 126:549ba18ddd81 | 924 | __IO uint32_t OPTKEYR; |
| mbed_official | 126:549ba18ddd81 | 925 | __IO uint32_t SR; |
| mbed_official | 126:549ba18ddd81 | 926 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 927 | __IO uint32_t AR; |
| mbed_official | 126:549ba18ddd81 | 928 | __IO uint32_t RESERVED; |
| mbed_official | 126:549ba18ddd81 | 929 | __IO uint32_t OBR; |
| mbed_official | 126:549ba18ddd81 | 930 | __IO uint32_t WRPR; |
| mbed_official | 126:549ba18ddd81 | 931 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 932 | uint32_t RESERVED1[8]; |
| mbed_official | 126:549ba18ddd81 | 933 | __IO uint32_t KEYR2; |
| mbed_official | 126:549ba18ddd81 | 934 | uint32_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 935 | __IO uint32_t SR2; |
| mbed_official | 126:549ba18ddd81 | 936 | __IO uint32_t CR2; |
| mbed_official | 126:549ba18ddd81 | 937 | __IO uint32_t AR2; |
| mbed_official | 126:549ba18ddd81 | 938 | #endif /* STM32F10X_XL */ |
| mbed_official | 126:549ba18ddd81 | 939 | } FLASH_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 940 | |
| mbed_official | 126:549ba18ddd81 | 941 | /** |
| mbed_official | 126:549ba18ddd81 | 942 | * @brief Option Bytes Registers |
| mbed_official | 126:549ba18ddd81 | 943 | */ |
| mbed_official | 126:549ba18ddd81 | 944 | |
| mbed_official | 126:549ba18ddd81 | 945 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 946 | { |
| mbed_official | 126:549ba18ddd81 | 947 | __IO uint16_t RDP; |
| mbed_official | 126:549ba18ddd81 | 948 | __IO uint16_t USER; |
| mbed_official | 126:549ba18ddd81 | 949 | __IO uint16_t Data0; |
| mbed_official | 126:549ba18ddd81 | 950 | __IO uint16_t Data1; |
| mbed_official | 126:549ba18ddd81 | 951 | __IO uint16_t WRP0; |
| mbed_official | 126:549ba18ddd81 | 952 | __IO uint16_t WRP1; |
| mbed_official | 126:549ba18ddd81 | 953 | __IO uint16_t WRP2; |
| mbed_official | 126:549ba18ddd81 | 954 | __IO uint16_t WRP3; |
| mbed_official | 126:549ba18ddd81 | 955 | } OB_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 956 | |
| mbed_official | 126:549ba18ddd81 | 957 | /** |
| mbed_official | 126:549ba18ddd81 | 958 | * @brief Flexible Static Memory Controller |
| mbed_official | 126:549ba18ddd81 | 959 | */ |
| mbed_official | 126:549ba18ddd81 | 960 | |
| mbed_official | 126:549ba18ddd81 | 961 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 962 | { |
| mbed_official | 126:549ba18ddd81 | 963 | __IO uint32_t BTCR[8]; |
| mbed_official | 126:549ba18ddd81 | 964 | } FSMC_Bank1_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 965 | |
| mbed_official | 126:549ba18ddd81 | 966 | /** |
| mbed_official | 126:549ba18ddd81 | 967 | * @brief Flexible Static Memory Controller Bank1E |
| mbed_official | 126:549ba18ddd81 | 968 | */ |
| mbed_official | 126:549ba18ddd81 | 969 | |
| mbed_official | 126:549ba18ddd81 | 970 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 971 | { |
| mbed_official | 126:549ba18ddd81 | 972 | __IO uint32_t BWTR[7]; |
| mbed_official | 126:549ba18ddd81 | 973 | } FSMC_Bank1E_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 974 | |
| mbed_official | 126:549ba18ddd81 | 975 | /** |
| mbed_official | 126:549ba18ddd81 | 976 | * @brief Flexible Static Memory Controller Bank2 |
| mbed_official | 126:549ba18ddd81 | 977 | */ |
| mbed_official | 126:549ba18ddd81 | 978 | |
| mbed_official | 126:549ba18ddd81 | 979 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 980 | { |
| mbed_official | 126:549ba18ddd81 | 981 | __IO uint32_t PCR2; |
| mbed_official | 126:549ba18ddd81 | 982 | __IO uint32_t SR2; |
| mbed_official | 126:549ba18ddd81 | 983 | __IO uint32_t PMEM2; |
| mbed_official | 126:549ba18ddd81 | 984 | __IO uint32_t PATT2; |
| mbed_official | 126:549ba18ddd81 | 985 | uint32_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 986 | __IO uint32_t ECCR2; |
| mbed_official | 126:549ba18ddd81 | 987 | } FSMC_Bank2_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 988 | |
| mbed_official | 126:549ba18ddd81 | 989 | /** |
| mbed_official | 126:549ba18ddd81 | 990 | * @brief Flexible Static Memory Controller Bank3 |
| mbed_official | 126:549ba18ddd81 | 991 | */ |
| mbed_official | 126:549ba18ddd81 | 992 | |
| mbed_official | 126:549ba18ddd81 | 993 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 994 | { |
| mbed_official | 126:549ba18ddd81 | 995 | __IO uint32_t PCR3; |
| mbed_official | 126:549ba18ddd81 | 996 | __IO uint32_t SR3; |
| mbed_official | 126:549ba18ddd81 | 997 | __IO uint32_t PMEM3; |
| mbed_official | 126:549ba18ddd81 | 998 | __IO uint32_t PATT3; |
| mbed_official | 126:549ba18ddd81 | 999 | uint32_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1000 | __IO uint32_t ECCR3; |
| mbed_official | 126:549ba18ddd81 | 1001 | } FSMC_Bank3_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1002 | |
| mbed_official | 126:549ba18ddd81 | 1003 | /** |
| mbed_official | 126:549ba18ddd81 | 1004 | * @brief Flexible Static Memory Controller Bank4 |
| mbed_official | 126:549ba18ddd81 | 1005 | */ |
| mbed_official | 126:549ba18ddd81 | 1006 | |
| mbed_official | 126:549ba18ddd81 | 1007 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1008 | { |
| mbed_official | 126:549ba18ddd81 | 1009 | __IO uint32_t PCR4; |
| mbed_official | 126:549ba18ddd81 | 1010 | __IO uint32_t SR4; |
| mbed_official | 126:549ba18ddd81 | 1011 | __IO uint32_t PMEM4; |
| mbed_official | 126:549ba18ddd81 | 1012 | __IO uint32_t PATT4; |
| mbed_official | 126:549ba18ddd81 | 1013 | __IO uint32_t PIO4; |
| mbed_official | 126:549ba18ddd81 | 1014 | } FSMC_Bank4_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1015 | |
| mbed_official | 126:549ba18ddd81 | 1016 | /** |
| mbed_official | 126:549ba18ddd81 | 1017 | * @brief General Purpose I/O |
| mbed_official | 126:549ba18ddd81 | 1018 | */ |
| mbed_official | 126:549ba18ddd81 | 1019 | |
| mbed_official | 126:549ba18ddd81 | 1020 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1021 | { |
| mbed_official | 126:549ba18ddd81 | 1022 | __IO uint32_t CRL; |
| mbed_official | 126:549ba18ddd81 | 1023 | __IO uint32_t CRH; |
| mbed_official | 126:549ba18ddd81 | 1024 | __IO uint32_t IDR; |
| mbed_official | 126:549ba18ddd81 | 1025 | __IO uint32_t ODR; |
| mbed_official | 126:549ba18ddd81 | 1026 | __IO uint32_t BSRR; |
| mbed_official | 126:549ba18ddd81 | 1027 | __IO uint32_t BRR; |
| mbed_official | 126:549ba18ddd81 | 1028 | __IO uint32_t LCKR; |
| mbed_official | 126:549ba18ddd81 | 1029 | } GPIO_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1030 | |
| mbed_official | 126:549ba18ddd81 | 1031 | /** |
| mbed_official | 126:549ba18ddd81 | 1032 | * @brief Alternate Function I/O |
| mbed_official | 126:549ba18ddd81 | 1033 | */ |
| mbed_official | 126:549ba18ddd81 | 1034 | |
| mbed_official | 126:549ba18ddd81 | 1035 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1036 | { |
| mbed_official | 126:549ba18ddd81 | 1037 | __IO uint32_t EVCR; |
| mbed_official | 126:549ba18ddd81 | 1038 | __IO uint32_t MAPR; |
| mbed_official | 126:549ba18ddd81 | 1039 | __IO uint32_t EXTICR[4]; |
| mbed_official | 126:549ba18ddd81 | 1040 | uint32_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1041 | __IO uint32_t MAPR2; |
| mbed_official | 126:549ba18ddd81 | 1042 | } AFIO_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1043 | /** |
| mbed_official | 126:549ba18ddd81 | 1044 | * @brief Inter Integrated Circuit Interface |
| mbed_official | 126:549ba18ddd81 | 1045 | */ |
| mbed_official | 126:549ba18ddd81 | 1046 | |
| mbed_official | 126:549ba18ddd81 | 1047 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1048 | { |
| mbed_official | 126:549ba18ddd81 | 1049 | __IO uint16_t CR1; |
| mbed_official | 126:549ba18ddd81 | 1050 | uint16_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1051 | __IO uint16_t CR2; |
| mbed_official | 126:549ba18ddd81 | 1052 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 1053 | __IO uint16_t OAR1; |
| mbed_official | 126:549ba18ddd81 | 1054 | uint16_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 1055 | __IO uint16_t OAR2; |
| mbed_official | 126:549ba18ddd81 | 1056 | uint16_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 1057 | __IO uint16_t DR; |
| mbed_official | 126:549ba18ddd81 | 1058 | uint16_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 1059 | __IO uint16_t SR1; |
| mbed_official | 126:549ba18ddd81 | 1060 | uint16_t RESERVED5; |
| mbed_official | 126:549ba18ddd81 | 1061 | __IO uint16_t SR2; |
| mbed_official | 126:549ba18ddd81 | 1062 | uint16_t RESERVED6; |
| mbed_official | 126:549ba18ddd81 | 1063 | __IO uint16_t CCR; |
| mbed_official | 126:549ba18ddd81 | 1064 | uint16_t RESERVED7; |
| mbed_official | 126:549ba18ddd81 | 1065 | __IO uint16_t TRISE; |
| mbed_official | 126:549ba18ddd81 | 1066 | uint16_t RESERVED8; |
| mbed_official | 126:549ba18ddd81 | 1067 | } I2C_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1068 | |
| mbed_official | 126:549ba18ddd81 | 1069 | /** |
| mbed_official | 126:549ba18ddd81 | 1070 | * @brief Independent WATCHDOG |
| mbed_official | 126:549ba18ddd81 | 1071 | */ |
| mbed_official | 126:549ba18ddd81 | 1072 | |
| mbed_official | 126:549ba18ddd81 | 1073 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1074 | { |
| mbed_official | 126:549ba18ddd81 | 1075 | __IO uint32_t KR; |
| mbed_official | 126:549ba18ddd81 | 1076 | __IO uint32_t PR; |
| mbed_official | 126:549ba18ddd81 | 1077 | __IO uint32_t RLR; |
| mbed_official | 126:549ba18ddd81 | 1078 | __IO uint32_t SR; |
| mbed_official | 126:549ba18ddd81 | 1079 | } IWDG_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1080 | |
| mbed_official | 126:549ba18ddd81 | 1081 | /** |
| mbed_official | 126:549ba18ddd81 | 1082 | * @brief Power Control |
| mbed_official | 126:549ba18ddd81 | 1083 | */ |
| mbed_official | 126:549ba18ddd81 | 1084 | |
| mbed_official | 126:549ba18ddd81 | 1085 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1086 | { |
| mbed_official | 126:549ba18ddd81 | 1087 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 1088 | __IO uint32_t CSR; |
| mbed_official | 126:549ba18ddd81 | 1089 | } PWR_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1090 | |
| mbed_official | 126:549ba18ddd81 | 1091 | /** |
| mbed_official | 126:549ba18ddd81 | 1092 | * @brief Reset and Clock Control |
| mbed_official | 126:549ba18ddd81 | 1093 | */ |
| mbed_official | 126:549ba18ddd81 | 1094 | |
| mbed_official | 126:549ba18ddd81 | 1095 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1096 | { |
| mbed_official | 126:549ba18ddd81 | 1097 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 1098 | __IO uint32_t CFGR; |
| mbed_official | 126:549ba18ddd81 | 1099 | __IO uint32_t CIR; |
| mbed_official | 126:549ba18ddd81 | 1100 | __IO uint32_t APB2RSTR; |
| mbed_official | 126:549ba18ddd81 | 1101 | __IO uint32_t APB1RSTR; |
| mbed_official | 126:549ba18ddd81 | 1102 | __IO uint32_t AHBENR; |
| mbed_official | 126:549ba18ddd81 | 1103 | __IO uint32_t APB2ENR; |
| mbed_official | 126:549ba18ddd81 | 1104 | __IO uint32_t APB1ENR; |
| mbed_official | 126:549ba18ddd81 | 1105 | __IO uint32_t BDCR; |
| mbed_official | 126:549ba18ddd81 | 1106 | __IO uint32_t CSR; |
| mbed_official | 126:549ba18ddd81 | 1107 | |
| mbed_official | 126:549ba18ddd81 | 1108 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 1109 | __IO uint32_t AHBRSTR; |
| mbed_official | 126:549ba18ddd81 | 1110 | __IO uint32_t CFGR2; |
| mbed_official | 126:549ba18ddd81 | 1111 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 1112 | |
| mbed_official | 126:549ba18ddd81 | 1113 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 1114 | uint32_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1115 | __IO uint32_t CFGR2; |
| mbed_official | 126:549ba18ddd81 | 1116 | #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ |
| mbed_official | 126:549ba18ddd81 | 1117 | } RCC_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1118 | |
| mbed_official | 126:549ba18ddd81 | 1119 | /** |
| mbed_official | 126:549ba18ddd81 | 1120 | * @brief Real-Time Clock |
| mbed_official | 126:549ba18ddd81 | 1121 | */ |
| mbed_official | 126:549ba18ddd81 | 1122 | |
| mbed_official | 126:549ba18ddd81 | 1123 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1124 | { |
| mbed_official | 126:549ba18ddd81 | 1125 | __IO uint16_t CRH; |
| mbed_official | 126:549ba18ddd81 | 1126 | uint16_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1127 | __IO uint16_t CRL; |
| mbed_official | 126:549ba18ddd81 | 1128 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 1129 | __IO uint16_t PRLH; |
| mbed_official | 126:549ba18ddd81 | 1130 | uint16_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 1131 | __IO uint16_t PRLL; |
| mbed_official | 126:549ba18ddd81 | 1132 | uint16_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 1133 | __IO uint16_t DIVH; |
| mbed_official | 126:549ba18ddd81 | 1134 | uint16_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 1135 | __IO uint16_t DIVL; |
| mbed_official | 126:549ba18ddd81 | 1136 | uint16_t RESERVED5; |
| mbed_official | 126:549ba18ddd81 | 1137 | __IO uint16_t CNTH; |
| mbed_official | 126:549ba18ddd81 | 1138 | uint16_t RESERVED6; |
| mbed_official | 126:549ba18ddd81 | 1139 | __IO uint16_t CNTL; |
| mbed_official | 126:549ba18ddd81 | 1140 | uint16_t RESERVED7; |
| mbed_official | 126:549ba18ddd81 | 1141 | __IO uint16_t ALRH; |
| mbed_official | 126:549ba18ddd81 | 1142 | uint16_t RESERVED8; |
| mbed_official | 126:549ba18ddd81 | 1143 | __IO uint16_t ALRL; |
| mbed_official | 126:549ba18ddd81 | 1144 | uint16_t RESERVED9; |
| mbed_official | 126:549ba18ddd81 | 1145 | } RTC_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1146 | |
| mbed_official | 126:549ba18ddd81 | 1147 | /** |
| mbed_official | 126:549ba18ddd81 | 1148 | * @brief SD host Interface |
| mbed_official | 126:549ba18ddd81 | 1149 | */ |
| mbed_official | 126:549ba18ddd81 | 1150 | |
| mbed_official | 126:549ba18ddd81 | 1151 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1152 | { |
| mbed_official | 126:549ba18ddd81 | 1153 | __IO uint32_t POWER; |
| mbed_official | 126:549ba18ddd81 | 1154 | __IO uint32_t CLKCR; |
| mbed_official | 126:549ba18ddd81 | 1155 | __IO uint32_t ARG; |
| mbed_official | 126:549ba18ddd81 | 1156 | __IO uint32_t CMD; |
| mbed_official | 126:549ba18ddd81 | 1157 | __I uint32_t RESPCMD; |
| mbed_official | 126:549ba18ddd81 | 1158 | __I uint32_t RESP1; |
| mbed_official | 126:549ba18ddd81 | 1159 | __I uint32_t RESP2; |
| mbed_official | 126:549ba18ddd81 | 1160 | __I uint32_t RESP3; |
| mbed_official | 126:549ba18ddd81 | 1161 | __I uint32_t RESP4; |
| mbed_official | 126:549ba18ddd81 | 1162 | __IO uint32_t DTIMER; |
| mbed_official | 126:549ba18ddd81 | 1163 | __IO uint32_t DLEN; |
| mbed_official | 126:549ba18ddd81 | 1164 | __IO uint32_t DCTRL; |
| mbed_official | 126:549ba18ddd81 | 1165 | __I uint32_t DCOUNT; |
| mbed_official | 126:549ba18ddd81 | 1166 | __I uint32_t STA; |
| mbed_official | 126:549ba18ddd81 | 1167 | __IO uint32_t ICR; |
| mbed_official | 126:549ba18ddd81 | 1168 | __IO uint32_t MASK; |
| mbed_official | 126:549ba18ddd81 | 1169 | uint32_t RESERVED0[2]; |
| mbed_official | 126:549ba18ddd81 | 1170 | __I uint32_t FIFOCNT; |
| mbed_official | 126:549ba18ddd81 | 1171 | uint32_t RESERVED1[13]; |
| mbed_official | 126:549ba18ddd81 | 1172 | __IO uint32_t FIFO; |
| mbed_official | 126:549ba18ddd81 | 1173 | } SDIO_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1174 | |
| mbed_official | 126:549ba18ddd81 | 1175 | /** |
| mbed_official | 126:549ba18ddd81 | 1176 | * @brief Serial Peripheral Interface |
| mbed_official | 126:549ba18ddd81 | 1177 | */ |
| mbed_official | 126:549ba18ddd81 | 1178 | |
| mbed_official | 126:549ba18ddd81 | 1179 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1180 | { |
| mbed_official | 126:549ba18ddd81 | 1181 | __IO uint16_t CR1; |
| mbed_official | 126:549ba18ddd81 | 1182 | uint16_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1183 | __IO uint16_t CR2; |
| mbed_official | 126:549ba18ddd81 | 1184 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 1185 | __IO uint16_t SR; |
| mbed_official | 126:549ba18ddd81 | 1186 | uint16_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 1187 | __IO uint16_t DR; |
| mbed_official | 126:549ba18ddd81 | 1188 | uint16_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 1189 | __IO uint16_t CRCPR; |
| mbed_official | 126:549ba18ddd81 | 1190 | uint16_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 1191 | __IO uint16_t RXCRCR; |
| mbed_official | 126:549ba18ddd81 | 1192 | uint16_t RESERVED5; |
| mbed_official | 126:549ba18ddd81 | 1193 | __IO uint16_t TXCRCR; |
| mbed_official | 126:549ba18ddd81 | 1194 | uint16_t RESERVED6; |
| mbed_official | 126:549ba18ddd81 | 1195 | __IO uint16_t I2SCFGR; |
| mbed_official | 126:549ba18ddd81 | 1196 | uint16_t RESERVED7; |
| mbed_official | 126:549ba18ddd81 | 1197 | __IO uint16_t I2SPR; |
| mbed_official | 126:549ba18ddd81 | 1198 | uint16_t RESERVED8; |
| mbed_official | 126:549ba18ddd81 | 1199 | } SPI_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1200 | |
| mbed_official | 126:549ba18ddd81 | 1201 | /** |
| mbed_official | 126:549ba18ddd81 | 1202 | * @brief TIM |
| mbed_official | 126:549ba18ddd81 | 1203 | */ |
| mbed_official | 126:549ba18ddd81 | 1204 | |
| mbed_official | 126:549ba18ddd81 | 1205 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1206 | { |
| mbed_official | 126:549ba18ddd81 | 1207 | __IO uint16_t CR1; |
| mbed_official | 126:549ba18ddd81 | 1208 | uint16_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1209 | __IO uint16_t CR2; |
| mbed_official | 126:549ba18ddd81 | 1210 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 1211 | __IO uint16_t SMCR; |
| mbed_official | 126:549ba18ddd81 | 1212 | uint16_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 1213 | __IO uint16_t DIER; |
| mbed_official | 126:549ba18ddd81 | 1214 | uint16_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 1215 | __IO uint16_t SR; |
| mbed_official | 126:549ba18ddd81 | 1216 | uint16_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 1217 | __IO uint16_t EGR; |
| mbed_official | 126:549ba18ddd81 | 1218 | uint16_t RESERVED5; |
| mbed_official | 126:549ba18ddd81 | 1219 | __IO uint16_t CCMR1; |
| mbed_official | 126:549ba18ddd81 | 1220 | uint16_t RESERVED6; |
| mbed_official | 126:549ba18ddd81 | 1221 | __IO uint16_t CCMR2; |
| mbed_official | 126:549ba18ddd81 | 1222 | uint16_t RESERVED7; |
| mbed_official | 126:549ba18ddd81 | 1223 | __IO uint16_t CCER; |
| mbed_official | 126:549ba18ddd81 | 1224 | uint16_t RESERVED8; |
| mbed_official | 126:549ba18ddd81 | 1225 | __IO uint16_t CNT; |
| mbed_official | 126:549ba18ddd81 | 1226 | uint16_t RESERVED9; |
| mbed_official | 126:549ba18ddd81 | 1227 | __IO uint16_t PSC; |
| mbed_official | 126:549ba18ddd81 | 1228 | uint16_t RESERVED10; |
| mbed_official | 126:549ba18ddd81 | 1229 | __IO uint16_t ARR; |
| mbed_official | 126:549ba18ddd81 | 1230 | uint16_t RESERVED11; |
| mbed_official | 126:549ba18ddd81 | 1231 | __IO uint16_t RCR; |
| mbed_official | 126:549ba18ddd81 | 1232 | uint16_t RESERVED12; |
| mbed_official | 126:549ba18ddd81 | 1233 | __IO uint16_t CCR1; |
| mbed_official | 126:549ba18ddd81 | 1234 | uint16_t RESERVED13; |
| mbed_official | 126:549ba18ddd81 | 1235 | __IO uint16_t CCR2; |
| mbed_official | 126:549ba18ddd81 | 1236 | uint16_t RESERVED14; |
| mbed_official | 126:549ba18ddd81 | 1237 | __IO uint16_t CCR3; |
| mbed_official | 126:549ba18ddd81 | 1238 | uint16_t RESERVED15; |
| mbed_official | 126:549ba18ddd81 | 1239 | __IO uint16_t CCR4; |
| mbed_official | 126:549ba18ddd81 | 1240 | uint16_t RESERVED16; |
| mbed_official | 126:549ba18ddd81 | 1241 | __IO uint16_t BDTR; |
| mbed_official | 126:549ba18ddd81 | 1242 | uint16_t RESERVED17; |
| mbed_official | 126:549ba18ddd81 | 1243 | __IO uint16_t DCR; |
| mbed_official | 126:549ba18ddd81 | 1244 | uint16_t RESERVED18; |
| mbed_official | 126:549ba18ddd81 | 1245 | __IO uint16_t DMAR; |
| mbed_official | 126:549ba18ddd81 | 1246 | uint16_t RESERVED19; |
| mbed_official | 126:549ba18ddd81 | 1247 | } TIM_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1248 | |
| mbed_official | 126:549ba18ddd81 | 1249 | /** |
| mbed_official | 126:549ba18ddd81 | 1250 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| mbed_official | 126:549ba18ddd81 | 1251 | */ |
| mbed_official | 126:549ba18ddd81 | 1252 | |
| mbed_official | 126:549ba18ddd81 | 1253 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1254 | { |
| mbed_official | 126:549ba18ddd81 | 1255 | __IO uint16_t SR; |
| mbed_official | 126:549ba18ddd81 | 1256 | uint16_t RESERVED0; |
| mbed_official | 126:549ba18ddd81 | 1257 | __IO uint16_t DR; |
| mbed_official | 126:549ba18ddd81 | 1258 | uint16_t RESERVED1; |
| mbed_official | 126:549ba18ddd81 | 1259 | __IO uint16_t BRR; |
| mbed_official | 126:549ba18ddd81 | 1260 | uint16_t RESERVED2; |
| mbed_official | 126:549ba18ddd81 | 1261 | __IO uint16_t CR1; |
| mbed_official | 126:549ba18ddd81 | 1262 | uint16_t RESERVED3; |
| mbed_official | 126:549ba18ddd81 | 1263 | __IO uint16_t CR2; |
| mbed_official | 126:549ba18ddd81 | 1264 | uint16_t RESERVED4; |
| mbed_official | 126:549ba18ddd81 | 1265 | __IO uint16_t CR3; |
| mbed_official | 126:549ba18ddd81 | 1266 | uint16_t RESERVED5; |
| mbed_official | 126:549ba18ddd81 | 1267 | __IO uint16_t GTPR; |
| mbed_official | 126:549ba18ddd81 | 1268 | uint16_t RESERVED6; |
| mbed_official | 126:549ba18ddd81 | 1269 | } USART_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1270 | |
| mbed_official | 126:549ba18ddd81 | 1271 | /** |
| mbed_official | 126:549ba18ddd81 | 1272 | * @brief Window WATCHDOG |
| mbed_official | 126:549ba18ddd81 | 1273 | */ |
| mbed_official | 126:549ba18ddd81 | 1274 | |
| mbed_official | 126:549ba18ddd81 | 1275 | typedef struct |
| mbed_official | 126:549ba18ddd81 | 1276 | { |
| mbed_official | 126:549ba18ddd81 | 1277 | __IO uint32_t CR; |
| mbed_official | 126:549ba18ddd81 | 1278 | __IO uint32_t CFR; |
| mbed_official | 126:549ba18ddd81 | 1279 | __IO uint32_t SR; |
| mbed_official | 126:549ba18ddd81 | 1280 | } WWDG_TypeDef; |
| mbed_official | 126:549ba18ddd81 | 1281 | |
| mbed_official | 126:549ba18ddd81 | 1282 | /** |
| mbed_official | 126:549ba18ddd81 | 1283 | * @} |
| mbed_official | 126:549ba18ddd81 | 1284 | */ |
| mbed_official | 126:549ba18ddd81 | 1285 | |
| mbed_official | 126:549ba18ddd81 | 1286 | /** @addtogroup Peripheral_memory_map |
| mbed_official | 126:549ba18ddd81 | 1287 | * @{ |
| mbed_official | 126:549ba18ddd81 | 1288 | */ |
| mbed_official | 126:549ba18ddd81 | 1289 | |
| mbed_official | 126:549ba18ddd81 | 1290 | |
| mbed_official | 126:549ba18ddd81 | 1291 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
| mbed_official | 126:549ba18ddd81 | 1292 | #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
| mbed_official | 126:549ba18ddd81 | 1293 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
| mbed_official | 126:549ba18ddd81 | 1294 | |
| mbed_official | 126:549ba18ddd81 | 1295 | #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
| mbed_official | 126:549ba18ddd81 | 1296 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
| mbed_official | 126:549ba18ddd81 | 1297 | |
| mbed_official | 126:549ba18ddd81 | 1298 | #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1299 | |
| mbed_official | 126:549ba18ddd81 | 1300 | /*!< Peripheral memory map */ |
| mbed_official | 126:549ba18ddd81 | 1301 | #define APB1PERIPH_BASE PERIPH_BASE |
| mbed_official | 126:549ba18ddd81 | 1302 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| mbed_official | 126:549ba18ddd81 | 1303 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| mbed_official | 126:549ba18ddd81 | 1304 | |
| mbed_official | 126:549ba18ddd81 | 1305 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| mbed_official | 126:549ba18ddd81 | 1306 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| mbed_official | 126:549ba18ddd81 | 1307 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| mbed_official | 126:549ba18ddd81 | 1308 | #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| mbed_official | 126:549ba18ddd81 | 1309 | #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| mbed_official | 126:549ba18ddd81 | 1310 | #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| mbed_official | 126:549ba18ddd81 | 1311 | #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| mbed_official | 126:549ba18ddd81 | 1312 | #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| mbed_official | 126:549ba18ddd81 | 1313 | #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| mbed_official | 126:549ba18ddd81 | 1314 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| mbed_official | 126:549ba18ddd81 | 1315 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| mbed_official | 126:549ba18ddd81 | 1316 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| mbed_official | 126:549ba18ddd81 | 1317 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| mbed_official | 126:549ba18ddd81 | 1318 | #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| mbed_official | 126:549ba18ddd81 | 1319 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| mbed_official | 126:549ba18ddd81 | 1320 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| mbed_official | 126:549ba18ddd81 | 1321 | #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| mbed_official | 126:549ba18ddd81 | 1322 | #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| mbed_official | 126:549ba18ddd81 | 1323 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| mbed_official | 126:549ba18ddd81 | 1324 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| mbed_official | 126:549ba18ddd81 | 1325 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| mbed_official | 126:549ba18ddd81 | 1326 | #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| mbed_official | 126:549ba18ddd81 | 1327 | #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
| mbed_official | 126:549ba18ddd81 | 1328 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| mbed_official | 126:549ba18ddd81 | 1329 | #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| mbed_official | 126:549ba18ddd81 | 1330 | #define CEC_BASE (APB1PERIPH_BASE + 0x7800) |
| mbed_official | 126:549ba18ddd81 | 1331 | |
| mbed_official | 126:549ba18ddd81 | 1332 | #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
| mbed_official | 126:549ba18ddd81 | 1333 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| mbed_official | 126:549ba18ddd81 | 1334 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
| mbed_official | 126:549ba18ddd81 | 1335 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
| mbed_official | 126:549ba18ddd81 | 1336 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
| mbed_official | 126:549ba18ddd81 | 1337 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
| mbed_official | 126:549ba18ddd81 | 1338 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
| mbed_official | 126:549ba18ddd81 | 1339 | #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
| mbed_official | 126:549ba18ddd81 | 1340 | #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
| mbed_official | 126:549ba18ddd81 | 1341 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
| mbed_official | 126:549ba18ddd81 | 1342 | #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
| mbed_official | 126:549ba18ddd81 | 1343 | #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
| mbed_official | 126:549ba18ddd81 | 1344 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| mbed_official | 126:549ba18ddd81 | 1345 | #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
| mbed_official | 126:549ba18ddd81 | 1346 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| mbed_official | 126:549ba18ddd81 | 1347 | #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
| mbed_official | 126:549ba18ddd81 | 1348 | #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
| mbed_official | 126:549ba18ddd81 | 1349 | #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
| mbed_official | 126:549ba18ddd81 | 1350 | #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
| mbed_official | 126:549ba18ddd81 | 1351 | #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
| mbed_official | 126:549ba18ddd81 | 1352 | #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
| mbed_official | 126:549ba18ddd81 | 1353 | #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
| mbed_official | 126:549ba18ddd81 | 1354 | |
| mbed_official | 126:549ba18ddd81 | 1355 | #define SDIO_BASE (PERIPH_BASE + 0x18000) |
| mbed_official | 126:549ba18ddd81 | 1356 | |
| mbed_official | 126:549ba18ddd81 | 1357 | #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
| mbed_official | 126:549ba18ddd81 | 1358 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
| mbed_official | 126:549ba18ddd81 | 1359 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
| mbed_official | 126:549ba18ddd81 | 1360 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
| mbed_official | 126:549ba18ddd81 | 1361 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
| mbed_official | 126:549ba18ddd81 | 1362 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
| mbed_official | 126:549ba18ddd81 | 1363 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
| mbed_official | 126:549ba18ddd81 | 1364 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
| mbed_official | 126:549ba18ddd81 | 1365 | #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
| mbed_official | 126:549ba18ddd81 | 1366 | #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
| mbed_official | 126:549ba18ddd81 | 1367 | #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
| mbed_official | 126:549ba18ddd81 | 1368 | #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
| mbed_official | 126:549ba18ddd81 | 1369 | #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
| mbed_official | 126:549ba18ddd81 | 1370 | #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
| mbed_official | 126:549ba18ddd81 | 1371 | #define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
| mbed_official | 126:549ba18ddd81 | 1372 | #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
| mbed_official | 126:549ba18ddd81 | 1373 | |
| mbed_official | 126:549ba18ddd81 | 1374 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1375 | #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
| mbed_official | 126:549ba18ddd81 | 1376 | |
| mbed_official | 126:549ba18ddd81 | 1377 | #define ETH_BASE (AHBPERIPH_BASE + 0x8000) |
| mbed_official | 126:549ba18ddd81 | 1378 | #define ETH_MAC_BASE (ETH_BASE) |
| mbed_official | 126:549ba18ddd81 | 1379 | #define ETH_MMC_BASE (ETH_BASE + 0x0100) |
| mbed_official | 126:549ba18ddd81 | 1380 | #define ETH_PTP_BASE (ETH_BASE + 0x0700) |
| mbed_official | 126:549ba18ddd81 | 1381 | #define ETH_DMA_BASE (ETH_BASE + 0x1000) |
| mbed_official | 126:549ba18ddd81 | 1382 | |
| mbed_official | 126:549ba18ddd81 | 1383 | #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1384 | #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1385 | #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1386 | #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1387 | #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1388 | |
| mbed_official | 126:549ba18ddd81 | 1389 | #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
| mbed_official | 126:549ba18ddd81 | 1390 | |
| mbed_official | 126:549ba18ddd81 | 1391 | /** |
| mbed_official | 126:549ba18ddd81 | 1392 | * @} |
| mbed_official | 126:549ba18ddd81 | 1393 | */ |
| mbed_official | 126:549ba18ddd81 | 1394 | |
| mbed_official | 126:549ba18ddd81 | 1395 | /** @addtogroup Peripheral_declaration |
| mbed_official | 126:549ba18ddd81 | 1396 | * @{ |
| mbed_official | 126:549ba18ddd81 | 1397 | */ |
| mbed_official | 126:549ba18ddd81 | 1398 | |
| mbed_official | 126:549ba18ddd81 | 1399 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1400 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| mbed_official | 126:549ba18ddd81 | 1401 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| mbed_official | 126:549ba18ddd81 | 1402 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| mbed_official | 126:549ba18ddd81 | 1403 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| mbed_official | 126:549ba18ddd81 | 1404 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| mbed_official | 126:549ba18ddd81 | 1405 | #define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
| mbed_official | 126:549ba18ddd81 | 1406 | #define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
| mbed_official | 126:549ba18ddd81 | 1407 | #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
| mbed_official | 126:549ba18ddd81 | 1408 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
| mbed_official | 126:549ba18ddd81 | 1409 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| mbed_official | 126:549ba18ddd81 | 1410 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| mbed_official | 126:549ba18ddd81 | 1411 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1412 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| mbed_official | 126:549ba18ddd81 | 1413 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1414 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
| mbed_official | 126:549ba18ddd81 | 1415 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
| mbed_official | 126:549ba18ddd81 | 1416 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
| mbed_official | 126:549ba18ddd81 | 1417 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1418 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1419 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1420 | #define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1421 | #define BKP ((BKP_TypeDef *) BKP_BASE) |
| mbed_official | 126:549ba18ddd81 | 1422 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
| mbed_official | 126:549ba18ddd81 | 1423 | #define DAC ((DAC_TypeDef *) DAC_BASE) |
| mbed_official | 126:549ba18ddd81 | 1424 | #define CEC ((CEC_TypeDef *) CEC_BASE) |
| mbed_official | 126:549ba18ddd81 | 1425 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
| mbed_official | 126:549ba18ddd81 | 1426 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| mbed_official | 126:549ba18ddd81 | 1427 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| mbed_official | 126:549ba18ddd81 | 1428 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| mbed_official | 126:549ba18ddd81 | 1429 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| mbed_official | 126:549ba18ddd81 | 1430 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| mbed_official | 126:549ba18ddd81 | 1431 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| mbed_official | 126:549ba18ddd81 | 1432 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| mbed_official | 126:549ba18ddd81 | 1433 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| mbed_official | 126:549ba18ddd81 | 1434 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1435 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1436 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1437 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1438 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| mbed_official | 126:549ba18ddd81 | 1439 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1440 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
| mbed_official | 126:549ba18ddd81 | 1441 | #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
| mbed_official | 126:549ba18ddd81 | 1442 | #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| mbed_official | 126:549ba18ddd81 | 1443 | #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| mbed_official | 126:549ba18ddd81 | 1444 | #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
| mbed_official | 126:549ba18ddd81 | 1445 | #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
| mbed_official | 126:549ba18ddd81 | 1446 | #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
| mbed_official | 126:549ba18ddd81 | 1447 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
| mbed_official | 126:549ba18ddd81 | 1448 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1449 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1450 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1451 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1452 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| mbed_official | 126:549ba18ddd81 | 1453 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| mbed_official | 126:549ba18ddd81 | 1454 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| mbed_official | 126:549ba18ddd81 | 1455 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| mbed_official | 126:549ba18ddd81 | 1456 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| mbed_official | 126:549ba18ddd81 | 1457 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
| mbed_official | 126:549ba18ddd81 | 1458 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
| mbed_official | 126:549ba18ddd81 | 1459 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
| mbed_official | 126:549ba18ddd81 | 1460 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
| mbed_official | 126:549ba18ddd81 | 1461 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
| mbed_official | 126:549ba18ddd81 | 1462 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
| mbed_official | 126:549ba18ddd81 | 1463 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
| mbed_official | 126:549ba18ddd81 | 1464 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| mbed_official | 126:549ba18ddd81 | 1465 | #define OB ((OB_TypeDef *) OB_BASE) |
| mbed_official | 126:549ba18ddd81 | 1466 | #define ETH ((ETH_TypeDef *) ETH_BASE) |
| mbed_official | 126:549ba18ddd81 | 1467 | #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
| mbed_official | 126:549ba18ddd81 | 1468 | #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
| mbed_official | 126:549ba18ddd81 | 1469 | #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) |
| mbed_official | 126:549ba18ddd81 | 1470 | #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) |
| mbed_official | 126:549ba18ddd81 | 1471 | #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
| mbed_official | 126:549ba18ddd81 | 1472 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| mbed_official | 126:549ba18ddd81 | 1473 | |
| mbed_official | 126:549ba18ddd81 | 1474 | /** |
| mbed_official | 126:549ba18ddd81 | 1475 | * @} |
| mbed_official | 126:549ba18ddd81 | 1476 | */ |
| mbed_official | 126:549ba18ddd81 | 1477 | |
| mbed_official | 126:549ba18ddd81 | 1478 | /** @addtogroup Exported_constants |
| mbed_official | 126:549ba18ddd81 | 1479 | * @{ |
| mbed_official | 126:549ba18ddd81 | 1480 | */ |
| mbed_official | 126:549ba18ddd81 | 1481 | |
| mbed_official | 126:549ba18ddd81 | 1482 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| mbed_official | 126:549ba18ddd81 | 1483 | * @{ |
| mbed_official | 126:549ba18ddd81 | 1484 | */ |
| mbed_official | 126:549ba18ddd81 | 1485 | |
| mbed_official | 126:549ba18ddd81 | 1486 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1487 | /* Peripheral Registers_Bits_Definition */ |
| mbed_official | 126:549ba18ddd81 | 1488 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1489 | |
| mbed_official | 126:549ba18ddd81 | 1490 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1491 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1492 | /* CRC calculation unit */ |
| mbed_official | 126:549ba18ddd81 | 1493 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1494 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1495 | |
| mbed_official | 126:549ba18ddd81 | 1496 | /******************* Bit definition for CRC_DR register *********************/ |
| mbed_official | 126:549ba18ddd81 | 1497 | #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
| mbed_official | 126:549ba18ddd81 | 1498 | |
| mbed_official | 126:549ba18ddd81 | 1499 | |
| mbed_official | 126:549ba18ddd81 | 1500 | /******************* Bit definition for CRC_IDR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1501 | #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
| mbed_official | 126:549ba18ddd81 | 1502 | |
| mbed_official | 126:549ba18ddd81 | 1503 | |
| mbed_official | 126:549ba18ddd81 | 1504 | /******************** Bit definition for CRC_CR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1505 | #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ |
| mbed_official | 126:549ba18ddd81 | 1506 | |
| mbed_official | 126:549ba18ddd81 | 1507 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1508 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1509 | /* Power Control */ |
| mbed_official | 126:549ba18ddd81 | 1510 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1511 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1512 | |
| mbed_official | 126:549ba18ddd81 | 1513 | /******************** Bit definition for PWR_CR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1514 | #define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ |
| mbed_official | 126:549ba18ddd81 | 1515 | #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ |
| mbed_official | 126:549ba18ddd81 | 1516 | #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ |
| mbed_official | 126:549ba18ddd81 | 1517 | #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ |
| mbed_official | 126:549ba18ddd81 | 1518 | #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ |
| mbed_official | 126:549ba18ddd81 | 1519 | |
| mbed_official | 126:549ba18ddd81 | 1520 | #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
| mbed_official | 126:549ba18ddd81 | 1521 | #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1522 | #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1523 | #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1524 | |
| mbed_official | 126:549ba18ddd81 | 1525 | /*!< PVD level configuration */ |
| mbed_official | 126:549ba18ddd81 | 1526 | #define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ |
| mbed_official | 126:549ba18ddd81 | 1527 | #define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ |
| mbed_official | 126:549ba18ddd81 | 1528 | #define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ |
| mbed_official | 126:549ba18ddd81 | 1529 | #define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ |
| mbed_official | 126:549ba18ddd81 | 1530 | #define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ |
| mbed_official | 126:549ba18ddd81 | 1531 | #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ |
| mbed_official | 126:549ba18ddd81 | 1532 | #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ |
| mbed_official | 126:549ba18ddd81 | 1533 | #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ |
| mbed_official | 126:549ba18ddd81 | 1534 | |
| mbed_official | 126:549ba18ddd81 | 1535 | #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ |
| mbed_official | 126:549ba18ddd81 | 1536 | |
| mbed_official | 126:549ba18ddd81 | 1537 | |
| mbed_official | 126:549ba18ddd81 | 1538 | /******************* Bit definition for PWR_CSR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1539 | #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ |
| mbed_official | 126:549ba18ddd81 | 1540 | #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ |
| mbed_official | 126:549ba18ddd81 | 1541 | #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ |
| mbed_official | 126:549ba18ddd81 | 1542 | #define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ |
| mbed_official | 126:549ba18ddd81 | 1543 | |
| mbed_official | 126:549ba18ddd81 | 1544 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1545 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1546 | /* Backup registers */ |
| mbed_official | 126:549ba18ddd81 | 1547 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1548 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1549 | |
| mbed_official | 126:549ba18ddd81 | 1550 | /******************* Bit definition for BKP_DR1 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1551 | #define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1552 | |
| mbed_official | 126:549ba18ddd81 | 1553 | /******************* Bit definition for BKP_DR2 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1554 | #define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1555 | |
| mbed_official | 126:549ba18ddd81 | 1556 | /******************* Bit definition for BKP_DR3 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1557 | #define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1558 | |
| mbed_official | 126:549ba18ddd81 | 1559 | /******************* Bit definition for BKP_DR4 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1560 | #define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1561 | |
| mbed_official | 126:549ba18ddd81 | 1562 | /******************* Bit definition for BKP_DR5 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1563 | #define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1564 | |
| mbed_official | 126:549ba18ddd81 | 1565 | /******************* Bit definition for BKP_DR6 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1566 | #define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1567 | |
| mbed_official | 126:549ba18ddd81 | 1568 | /******************* Bit definition for BKP_DR7 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1569 | #define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1570 | |
| mbed_official | 126:549ba18ddd81 | 1571 | /******************* Bit definition for BKP_DR8 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1572 | #define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1573 | |
| mbed_official | 126:549ba18ddd81 | 1574 | /******************* Bit definition for BKP_DR9 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1575 | #define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1576 | |
| mbed_official | 126:549ba18ddd81 | 1577 | /******************* Bit definition for BKP_DR10 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1578 | #define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1579 | |
| mbed_official | 126:549ba18ddd81 | 1580 | /******************* Bit definition for BKP_DR11 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1581 | #define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1582 | |
| mbed_official | 126:549ba18ddd81 | 1583 | /******************* Bit definition for BKP_DR12 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1584 | #define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1585 | |
| mbed_official | 126:549ba18ddd81 | 1586 | /******************* Bit definition for BKP_DR13 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1587 | #define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1588 | |
| mbed_official | 126:549ba18ddd81 | 1589 | /******************* Bit definition for BKP_DR14 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1590 | #define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1591 | |
| mbed_official | 126:549ba18ddd81 | 1592 | /******************* Bit definition for BKP_DR15 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1593 | #define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1594 | |
| mbed_official | 126:549ba18ddd81 | 1595 | /******************* Bit definition for BKP_DR16 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1596 | #define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1597 | |
| mbed_official | 126:549ba18ddd81 | 1598 | /******************* Bit definition for BKP_DR17 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1599 | #define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1600 | |
| mbed_official | 126:549ba18ddd81 | 1601 | /****************** Bit definition for BKP_DR18 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1602 | #define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1603 | |
| mbed_official | 126:549ba18ddd81 | 1604 | /******************* Bit definition for BKP_DR19 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1605 | #define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1606 | |
| mbed_official | 126:549ba18ddd81 | 1607 | /******************* Bit definition for BKP_DR20 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1608 | #define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1609 | |
| mbed_official | 126:549ba18ddd81 | 1610 | /******************* Bit definition for BKP_DR21 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1611 | #define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1612 | |
| mbed_official | 126:549ba18ddd81 | 1613 | /******************* Bit definition for BKP_DR22 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1614 | #define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1615 | |
| mbed_official | 126:549ba18ddd81 | 1616 | /******************* Bit definition for BKP_DR23 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1617 | #define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1618 | |
| mbed_official | 126:549ba18ddd81 | 1619 | /******************* Bit definition for BKP_DR24 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1620 | #define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1621 | |
| mbed_official | 126:549ba18ddd81 | 1622 | /******************* Bit definition for BKP_DR25 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1623 | #define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1624 | |
| mbed_official | 126:549ba18ddd81 | 1625 | /******************* Bit definition for BKP_DR26 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1626 | #define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1627 | |
| mbed_official | 126:549ba18ddd81 | 1628 | /******************* Bit definition for BKP_DR27 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1629 | #define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1630 | |
| mbed_official | 126:549ba18ddd81 | 1631 | /******************* Bit definition for BKP_DR28 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1632 | #define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1633 | |
| mbed_official | 126:549ba18ddd81 | 1634 | /******************* Bit definition for BKP_DR29 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1635 | #define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1636 | |
| mbed_official | 126:549ba18ddd81 | 1637 | /******************* Bit definition for BKP_DR30 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1638 | #define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1639 | |
| mbed_official | 126:549ba18ddd81 | 1640 | /******************* Bit definition for BKP_DR31 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1641 | #define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1642 | |
| mbed_official | 126:549ba18ddd81 | 1643 | /******************* Bit definition for BKP_DR32 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1644 | #define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1645 | |
| mbed_official | 126:549ba18ddd81 | 1646 | /******************* Bit definition for BKP_DR33 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1647 | #define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1648 | |
| mbed_official | 126:549ba18ddd81 | 1649 | /******************* Bit definition for BKP_DR34 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1650 | #define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1651 | |
| mbed_official | 126:549ba18ddd81 | 1652 | /******************* Bit definition for BKP_DR35 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1653 | #define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1654 | |
| mbed_official | 126:549ba18ddd81 | 1655 | /******************* Bit definition for BKP_DR36 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1656 | #define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1657 | |
| mbed_official | 126:549ba18ddd81 | 1658 | /******************* Bit definition for BKP_DR37 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1659 | #define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1660 | |
| mbed_official | 126:549ba18ddd81 | 1661 | /******************* Bit definition for BKP_DR38 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1662 | #define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1663 | |
| mbed_official | 126:549ba18ddd81 | 1664 | /******************* Bit definition for BKP_DR39 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1665 | #define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1666 | |
| mbed_official | 126:549ba18ddd81 | 1667 | /******************* Bit definition for BKP_DR40 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1668 | #define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1669 | |
| mbed_official | 126:549ba18ddd81 | 1670 | /******************* Bit definition for BKP_DR41 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1671 | #define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1672 | |
| mbed_official | 126:549ba18ddd81 | 1673 | /******************* Bit definition for BKP_DR42 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1674 | #define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ |
| mbed_official | 126:549ba18ddd81 | 1675 | |
| mbed_official | 126:549ba18ddd81 | 1676 | /****************** Bit definition for BKP_RTCCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1677 | #define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ |
| mbed_official | 126:549ba18ddd81 | 1678 | #define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ |
| mbed_official | 126:549ba18ddd81 | 1679 | #define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ |
| mbed_official | 126:549ba18ddd81 | 1680 | #define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ |
| mbed_official | 126:549ba18ddd81 | 1681 | |
| mbed_official | 126:549ba18ddd81 | 1682 | /******************** Bit definition for BKP_CR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1683 | #define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ |
| mbed_official | 126:549ba18ddd81 | 1684 | #define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ |
| mbed_official | 126:549ba18ddd81 | 1685 | |
| mbed_official | 126:549ba18ddd81 | 1686 | /******************* Bit definition for BKP_CSR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1687 | #define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ |
| mbed_official | 126:549ba18ddd81 | 1688 | #define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 1689 | #define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 1690 | #define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ |
| mbed_official | 126:549ba18ddd81 | 1691 | #define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 1692 | |
| mbed_official | 126:549ba18ddd81 | 1693 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1694 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1695 | /* Reset and Clock Control */ |
| mbed_official | 126:549ba18ddd81 | 1696 | /* */ |
| mbed_official | 126:549ba18ddd81 | 1697 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 1698 | |
| mbed_official | 126:549ba18ddd81 | 1699 | /******************** Bit definition for RCC_CR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1700 | #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ |
| mbed_official | 126:549ba18ddd81 | 1701 | #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ |
| mbed_official | 126:549ba18ddd81 | 1702 | #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ |
| mbed_official | 126:549ba18ddd81 | 1703 | #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ |
| mbed_official | 126:549ba18ddd81 | 1704 | #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
| mbed_official | 126:549ba18ddd81 | 1705 | #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ |
| mbed_official | 126:549ba18ddd81 | 1706 | #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
| mbed_official | 126:549ba18ddd81 | 1707 | #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ |
| mbed_official | 126:549ba18ddd81 | 1708 | #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ |
| mbed_official | 126:549ba18ddd81 | 1709 | #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ |
| mbed_official | 126:549ba18ddd81 | 1710 | |
| mbed_official | 126:549ba18ddd81 | 1711 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 1712 | #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ |
| mbed_official | 126:549ba18ddd81 | 1713 | #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ |
| mbed_official | 126:549ba18ddd81 | 1714 | #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ |
| mbed_official | 126:549ba18ddd81 | 1715 | #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ |
| mbed_official | 126:549ba18ddd81 | 1716 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 1717 | |
| mbed_official | 126:549ba18ddd81 | 1718 | /******************* Bit definition for RCC_CFGR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 1719 | /*!< SW configuration */ |
| mbed_official | 126:549ba18ddd81 | 1720 | #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
| mbed_official | 126:549ba18ddd81 | 1721 | #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1722 | #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1723 | |
| mbed_official | 126:549ba18ddd81 | 1724 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
| mbed_official | 126:549ba18ddd81 | 1725 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
| mbed_official | 126:549ba18ddd81 | 1726 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
| mbed_official | 126:549ba18ddd81 | 1727 | |
| mbed_official | 126:549ba18ddd81 | 1728 | /*!< SWS configuration */ |
| mbed_official | 126:549ba18ddd81 | 1729 | #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| mbed_official | 126:549ba18ddd81 | 1730 | #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1731 | #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1732 | |
| mbed_official | 126:549ba18ddd81 | 1733 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
| mbed_official | 126:549ba18ddd81 | 1734 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
| mbed_official | 126:549ba18ddd81 | 1735 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
| mbed_official | 126:549ba18ddd81 | 1736 | |
| mbed_official | 126:549ba18ddd81 | 1737 | /*!< HPRE configuration */ |
| mbed_official | 126:549ba18ddd81 | 1738 | #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 1739 | #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1740 | #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1741 | #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1742 | #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 1743 | |
| mbed_official | 126:549ba18ddd81 | 1744 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
| mbed_official | 126:549ba18ddd81 | 1745 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 1746 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 1747 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 1748 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
| mbed_official | 126:549ba18ddd81 | 1749 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
| mbed_official | 126:549ba18ddd81 | 1750 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
| mbed_official | 126:549ba18ddd81 | 1751 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
| mbed_official | 126:549ba18ddd81 | 1752 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
| mbed_official | 126:549ba18ddd81 | 1753 | |
| mbed_official | 126:549ba18ddd81 | 1754 | /*!< PPRE1 configuration */ |
| mbed_official | 126:549ba18ddd81 | 1755 | #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 1756 | #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1757 | #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1758 | #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1759 | |
| mbed_official | 126:549ba18ddd81 | 1760 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| mbed_official | 126:549ba18ddd81 | 1761 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 1762 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 1763 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 1764 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
| mbed_official | 126:549ba18ddd81 | 1765 | |
| mbed_official | 126:549ba18ddd81 | 1766 | /*!< PPRE2 configuration */ |
| mbed_official | 126:549ba18ddd81 | 1767 | #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 1768 | #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1769 | #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1770 | #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1771 | |
| mbed_official | 126:549ba18ddd81 | 1772 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| mbed_official | 126:549ba18ddd81 | 1773 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 1774 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 1775 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 1776 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
| mbed_official | 126:549ba18ddd81 | 1777 | |
| mbed_official | 126:549ba18ddd81 | 1778 | /*!< ADCPPRE configuration */ |
| mbed_official | 126:549ba18ddd81 | 1779 | #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 1780 | #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1781 | #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1782 | |
| mbed_official | 126:549ba18ddd81 | 1783 | #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 1784 | #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 1785 | #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
| mbed_official | 126:549ba18ddd81 | 1786 | #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 1787 | |
| mbed_official | 126:549ba18ddd81 | 1788 | #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1789 | |
| mbed_official | 126:549ba18ddd81 | 1790 | #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1791 | |
| mbed_official | 126:549ba18ddd81 | 1792 | /*!< PLLMUL configuration */ |
| mbed_official | 126:549ba18ddd81 | 1793 | #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
| mbed_official | 126:549ba18ddd81 | 1794 | #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1795 | #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1796 | #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1797 | #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 1798 | |
| mbed_official | 126:549ba18ddd81 | 1799 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 1800 | #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1801 | #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1802 | |
| mbed_official | 126:549ba18ddd81 | 1803 | #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1804 | #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1805 | |
| mbed_official | 126:549ba18ddd81 | 1806 | #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ |
| mbed_official | 126:549ba18ddd81 | 1807 | #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ |
| mbed_official | 126:549ba18ddd81 | 1808 | #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ |
| mbed_official | 126:549ba18ddd81 | 1809 | #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ |
| mbed_official | 126:549ba18ddd81 | 1810 | #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ |
| mbed_official | 126:549ba18ddd81 | 1811 | #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ |
| mbed_official | 126:549ba18ddd81 | 1812 | #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ |
| mbed_official | 126:549ba18ddd81 | 1813 | |
| mbed_official | 126:549ba18ddd81 | 1814 | #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ |
| mbed_official | 126:549ba18ddd81 | 1815 | |
| mbed_official | 126:549ba18ddd81 | 1816 | /*!< MCO configuration */ |
| mbed_official | 126:549ba18ddd81 | 1817 | #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ |
| mbed_official | 126:549ba18ddd81 | 1818 | #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1819 | #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1820 | #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1821 | #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 1822 | |
| mbed_official | 126:549ba18ddd81 | 1823 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
| mbed_official | 126:549ba18ddd81 | 1824 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1825 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1826 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1827 | #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1828 | #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ |
| mbed_official | 126:549ba18ddd81 | 1829 | #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ |
| mbed_official | 126:549ba18ddd81 | 1830 | #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1831 | #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1832 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 1833 | #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1834 | #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1835 | |
| mbed_official | 126:549ba18ddd81 | 1836 | #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1837 | #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1838 | |
| mbed_official | 126:549ba18ddd81 | 1839 | #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
| mbed_official | 126:549ba18ddd81 | 1840 | #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
| mbed_official | 126:549ba18ddd81 | 1841 | #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
| mbed_official | 126:549ba18ddd81 | 1842 | #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
| mbed_official | 126:549ba18ddd81 | 1843 | #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
| mbed_official | 126:549ba18ddd81 | 1844 | #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
| mbed_official | 126:549ba18ddd81 | 1845 | #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
| mbed_official | 126:549ba18ddd81 | 1846 | #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
| mbed_official | 126:549ba18ddd81 | 1847 | #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
| mbed_official | 126:549ba18ddd81 | 1848 | #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
| mbed_official | 126:549ba18ddd81 | 1849 | #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
| mbed_official | 126:549ba18ddd81 | 1850 | #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
| mbed_official | 126:549ba18ddd81 | 1851 | #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
| mbed_official | 126:549ba18ddd81 | 1852 | #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
| mbed_official | 126:549ba18ddd81 | 1853 | #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
| mbed_official | 126:549ba18ddd81 | 1854 | |
| mbed_official | 126:549ba18ddd81 | 1855 | /*!< MCO configuration */ |
| mbed_official | 126:549ba18ddd81 | 1856 | #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
| mbed_official | 126:549ba18ddd81 | 1857 | #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1858 | #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1859 | #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1860 | |
| mbed_official | 126:549ba18ddd81 | 1861 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
| mbed_official | 126:549ba18ddd81 | 1862 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1863 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1864 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1865 | #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1866 | #else |
| mbed_official | 126:549ba18ddd81 | 1867 | #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1868 | #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 1869 | |
| mbed_official | 126:549ba18ddd81 | 1870 | #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1871 | #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
| mbed_official | 126:549ba18ddd81 | 1872 | |
| mbed_official | 126:549ba18ddd81 | 1873 | #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
| mbed_official | 126:549ba18ddd81 | 1874 | #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
| mbed_official | 126:549ba18ddd81 | 1875 | #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
| mbed_official | 126:549ba18ddd81 | 1876 | #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
| mbed_official | 126:549ba18ddd81 | 1877 | #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
| mbed_official | 126:549ba18ddd81 | 1878 | #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
| mbed_official | 126:549ba18ddd81 | 1879 | #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
| mbed_official | 126:549ba18ddd81 | 1880 | #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
| mbed_official | 126:549ba18ddd81 | 1881 | #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
| mbed_official | 126:549ba18ddd81 | 1882 | #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
| mbed_official | 126:549ba18ddd81 | 1883 | #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
| mbed_official | 126:549ba18ddd81 | 1884 | #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
| mbed_official | 126:549ba18ddd81 | 1885 | #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
| mbed_official | 126:549ba18ddd81 | 1886 | #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
| mbed_official | 126:549ba18ddd81 | 1887 | #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
| mbed_official | 126:549ba18ddd81 | 1888 | #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ |
| mbed_official | 126:549ba18ddd81 | 1889 | |
| mbed_official | 126:549ba18ddd81 | 1890 | /*!< MCO configuration */ |
| mbed_official | 126:549ba18ddd81 | 1891 | #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
| mbed_official | 126:549ba18ddd81 | 1892 | #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 1893 | #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 1894 | #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 1895 | |
| mbed_official | 126:549ba18ddd81 | 1896 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
| mbed_official | 126:549ba18ddd81 | 1897 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1898 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1899 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1900 | #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
| mbed_official | 126:549ba18ddd81 | 1901 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 1902 | |
| mbed_official | 126:549ba18ddd81 | 1903 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 1904 | #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1905 | #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1906 | #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1907 | #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1908 | #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1909 | #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1910 | #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1911 | #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1912 | #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1913 | #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1914 | #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1915 | #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1916 | #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1917 | #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1918 | #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1919 | #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1920 | #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1921 | |
| mbed_official | 126:549ba18ddd81 | 1922 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 1923 | #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1924 | #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 1925 | #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1926 | #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 1927 | #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1928 | #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ |
| mbed_official | 126:549ba18ddd81 | 1929 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 1930 | |
| mbed_official | 126:549ba18ddd81 | 1931 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
| mbed_official | 126:549ba18ddd81 | 1932 | #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ |
| mbed_official | 126:549ba18ddd81 | 1933 | #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ |
| mbed_official | 126:549ba18ddd81 | 1934 | #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ |
| mbed_official | 126:549ba18ddd81 | 1935 | #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ |
| mbed_official | 126:549ba18ddd81 | 1936 | #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ |
| mbed_official | 126:549ba18ddd81 | 1937 | #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ |
| mbed_official | 126:549ba18ddd81 | 1938 | |
| mbed_official | 126:549ba18ddd81 | 1939 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 1940 | #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ |
| mbed_official | 126:549ba18ddd81 | 1941 | #endif |
| mbed_official | 126:549ba18ddd81 | 1942 | |
| mbed_official | 126:549ba18ddd81 | 1943 | #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1944 | #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ |
| mbed_official | 126:549ba18ddd81 | 1945 | #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
| mbed_official | 126:549ba18ddd81 | 1946 | |
| mbed_official | 126:549ba18ddd81 | 1947 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 1948 | #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1949 | #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1950 | #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1951 | #endif |
| mbed_official | 126:549ba18ddd81 | 1952 | |
| mbed_official | 126:549ba18ddd81 | 1953 | #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
| mbed_official | 126:549ba18ddd81 | 1954 | #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ |
| mbed_official | 126:549ba18ddd81 | 1955 | #endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
| mbed_official | 126:549ba18ddd81 | 1956 | |
| mbed_official | 126:549ba18ddd81 | 1957 | #if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
| mbed_official | 126:549ba18ddd81 | 1958 | #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
| mbed_official | 126:549ba18ddd81 | 1959 | #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
| mbed_official | 126:549ba18ddd81 | 1960 | #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1961 | #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ |
| mbed_official | 126:549ba18ddd81 | 1962 | #endif |
| mbed_official | 126:549ba18ddd81 | 1963 | |
| mbed_official | 126:549ba18ddd81 | 1964 | #if defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 1965 | #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
| mbed_official | 126:549ba18ddd81 | 1966 | #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
| mbed_official | 126:549ba18ddd81 | 1967 | #endif |
| mbed_official | 126:549ba18ddd81 | 1968 | |
| mbed_official | 126:549ba18ddd81 | 1969 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 1970 | #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1971 | #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1972 | #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 1973 | #endif /* STM32F10X_XL */ |
| mbed_official | 126:549ba18ddd81 | 1974 | |
| mbed_official | 126:549ba18ddd81 | 1975 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
| mbed_official | 126:549ba18ddd81 | 1976 | #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
| mbed_official | 126:549ba18ddd81 | 1977 | #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
| mbed_official | 126:549ba18ddd81 | 1978 | #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
| mbed_official | 126:549ba18ddd81 | 1979 | #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
| mbed_official | 126:549ba18ddd81 | 1980 | #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
| mbed_official | 126:549ba18ddd81 | 1981 | |
| mbed_official | 126:549ba18ddd81 | 1982 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 1983 | #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ |
| mbed_official | 126:549ba18ddd81 | 1984 | #endif |
| mbed_official | 126:549ba18ddd81 | 1985 | |
| mbed_official | 126:549ba18ddd81 | 1986 | #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ |
| mbed_official | 126:549ba18ddd81 | 1987 | #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ |
| mbed_official | 126:549ba18ddd81 | 1988 | |
| mbed_official | 126:549ba18ddd81 | 1989 | #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
| mbed_official | 126:549ba18ddd81 | 1990 | #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ |
| mbed_official | 126:549ba18ddd81 | 1991 | #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ |
| mbed_official | 126:549ba18ddd81 | 1992 | #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ |
| mbed_official | 126:549ba18ddd81 | 1993 | #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ |
| mbed_official | 126:549ba18ddd81 | 1994 | #endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
| mbed_official | 126:549ba18ddd81 | 1995 | |
| mbed_official | 126:549ba18ddd81 | 1996 | #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) |
| mbed_official | 126:549ba18ddd81 | 1997 | #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ |
| mbed_official | 126:549ba18ddd81 | 1998 | #endif |
| mbed_official | 126:549ba18ddd81 | 1999 | |
| mbed_official | 126:549ba18ddd81 | 2000 | #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) |
| mbed_official | 126:549ba18ddd81 | 2001 | #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
| mbed_official | 126:549ba18ddd81 | 2002 | #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
| mbed_official | 126:549ba18ddd81 | 2003 | #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
| mbed_official | 126:549ba18ddd81 | 2004 | #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
| mbed_official | 126:549ba18ddd81 | 2005 | #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
| mbed_official | 126:549ba18ddd81 | 2006 | #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
| mbed_official | 126:549ba18ddd81 | 2007 | #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
| mbed_official | 126:549ba18ddd81 | 2008 | #endif |
| mbed_official | 126:549ba18ddd81 | 2009 | |
| mbed_official | 126:549ba18ddd81 | 2010 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2011 | #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
| mbed_official | 126:549ba18ddd81 | 2012 | #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
| mbed_official | 126:549ba18ddd81 | 2013 | #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
| mbed_official | 126:549ba18ddd81 | 2014 | #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ |
| mbed_official | 126:549ba18ddd81 | 2015 | #endif |
| mbed_official | 126:549ba18ddd81 | 2016 | |
| mbed_official | 126:549ba18ddd81 | 2017 | #if defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2018 | #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
| mbed_official | 126:549ba18ddd81 | 2019 | #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 2020 | #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 2021 | #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 2022 | #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
| mbed_official | 126:549ba18ddd81 | 2023 | #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
| mbed_official | 126:549ba18ddd81 | 2024 | #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
| mbed_official | 126:549ba18ddd81 | 2025 | #endif |
| mbed_official | 126:549ba18ddd81 | 2026 | |
| mbed_official | 126:549ba18ddd81 | 2027 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 2028 | #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ |
| mbed_official | 126:549ba18ddd81 | 2029 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 2030 | |
| mbed_official | 126:549ba18ddd81 | 2031 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 2032 | #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 2033 | #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 2034 | #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
| mbed_official | 126:549ba18ddd81 | 2035 | #endif /* STM32F10X_XL */ |
| mbed_official | 126:549ba18ddd81 | 2036 | |
| mbed_official | 126:549ba18ddd81 | 2037 | /****************** Bit definition for RCC_AHBENR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2038 | #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2039 | #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2040 | #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2041 | #define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2042 | |
| mbed_official | 126:549ba18ddd81 | 2043 | #if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2044 | #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2045 | #endif |
| mbed_official | 126:549ba18ddd81 | 2046 | |
| mbed_official | 126:549ba18ddd81 | 2047 | #if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
| mbed_official | 126:549ba18ddd81 | 2048 | #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2049 | #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2050 | #endif |
| mbed_official | 126:549ba18ddd81 | 2051 | |
| mbed_official | 126:549ba18ddd81 | 2052 | #if defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2053 | #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2054 | #endif |
| mbed_official | 126:549ba18ddd81 | 2055 | |
| mbed_official | 126:549ba18ddd81 | 2056 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 2057 | #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2058 | #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2059 | #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2060 | #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2061 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 2062 | |
| mbed_official | 126:549ba18ddd81 | 2063 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2064 | #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2065 | #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2066 | #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2067 | #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2068 | #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2069 | #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2070 | |
| mbed_official | 126:549ba18ddd81 | 2071 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2072 | #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2073 | #endif |
| mbed_official | 126:549ba18ddd81 | 2074 | |
| mbed_official | 126:549ba18ddd81 | 2075 | #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2076 | #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2077 | #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2078 | |
| mbed_official | 126:549ba18ddd81 | 2079 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2080 | #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2081 | #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2082 | #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2083 | #endif |
| mbed_official | 126:549ba18ddd81 | 2084 | |
| mbed_official | 126:549ba18ddd81 | 2085 | #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
| mbed_official | 126:549ba18ddd81 | 2086 | #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2087 | #endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
| mbed_official | 126:549ba18ddd81 | 2088 | |
| mbed_official | 126:549ba18ddd81 | 2089 | #if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
| mbed_official | 126:549ba18ddd81 | 2090 | #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2091 | #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2092 | #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2093 | #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2094 | #endif |
| mbed_official | 126:549ba18ddd81 | 2095 | |
| mbed_official | 126:549ba18ddd81 | 2096 | #if defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2097 | #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2098 | #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2099 | #endif |
| mbed_official | 126:549ba18ddd81 | 2100 | |
| mbed_official | 126:549ba18ddd81 | 2101 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 2102 | #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2103 | #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2104 | #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2105 | #endif |
| mbed_official | 126:549ba18ddd81 | 2106 | |
| mbed_official | 126:549ba18ddd81 | 2107 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2108 | #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ |
| mbed_official | 126:549ba18ddd81 | 2109 | #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2110 | #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2111 | #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2112 | #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2113 | |
| mbed_official | 126:549ba18ddd81 | 2114 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2115 | #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2116 | #endif |
| mbed_official | 126:549ba18ddd81 | 2117 | |
| mbed_official | 126:549ba18ddd81 | 2118 | #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2119 | #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2120 | |
| mbed_official | 126:549ba18ddd81 | 2121 | #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
| mbed_official | 126:549ba18ddd81 | 2122 | #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2123 | #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2124 | #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2125 | #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2126 | #endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
| mbed_official | 126:549ba18ddd81 | 2127 | |
| mbed_official | 126:549ba18ddd81 | 2128 | #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) |
| mbed_official | 126:549ba18ddd81 | 2129 | #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2130 | #endif |
| mbed_official | 126:549ba18ddd81 | 2131 | |
| mbed_official | 126:549ba18ddd81 | 2132 | #if defined (STM32F10X_HD) || defined (STM32F10X_CL) |
| mbed_official | 126:549ba18ddd81 | 2133 | #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2134 | #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2135 | #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2136 | #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2137 | #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2138 | #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2139 | #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2140 | #endif |
| mbed_official | 126:549ba18ddd81 | 2141 | |
| mbed_official | 126:549ba18ddd81 | 2142 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2143 | #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2144 | #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2145 | #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2146 | #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2147 | #endif |
| mbed_official | 126:549ba18ddd81 | 2148 | |
| mbed_official | 126:549ba18ddd81 | 2149 | #ifdef STM32F10X_HD_VL |
| mbed_official | 126:549ba18ddd81 | 2150 | #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2151 | #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2152 | #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2153 | #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2154 | #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2155 | #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2156 | #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2157 | #endif /* STM32F10X_HD_VL */ |
| mbed_official | 126:549ba18ddd81 | 2158 | |
| mbed_official | 126:549ba18ddd81 | 2159 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 2160 | #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2161 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 2162 | |
| mbed_official | 126:549ba18ddd81 | 2163 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 2164 | #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2165 | #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2166 | #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2167 | #endif /* STM32F10X_XL */ |
| mbed_official | 126:549ba18ddd81 | 2168 | |
| mbed_official | 126:549ba18ddd81 | 2169 | /******************* Bit definition for RCC_BDCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2170 | #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
| mbed_official | 126:549ba18ddd81 | 2171 | #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
| mbed_official | 126:549ba18ddd81 | 2172 | #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
| mbed_official | 126:549ba18ddd81 | 2173 | |
| mbed_official | 126:549ba18ddd81 | 2174 | #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
| mbed_official | 126:549ba18ddd81 | 2175 | #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2176 | #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2177 | |
| mbed_official | 126:549ba18ddd81 | 2178 | /*!< RTC congiguration */ |
| mbed_official | 126:549ba18ddd81 | 2179 | #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
| mbed_official | 126:549ba18ddd81 | 2180 | #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
| mbed_official | 126:549ba18ddd81 | 2181 | #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
| mbed_official | 126:549ba18ddd81 | 2182 | #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
| mbed_official | 126:549ba18ddd81 | 2183 | |
| mbed_official | 126:549ba18ddd81 | 2184 | #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
| mbed_official | 126:549ba18ddd81 | 2185 | #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
| mbed_official | 126:549ba18ddd81 | 2186 | |
| mbed_official | 126:549ba18ddd81 | 2187 | /******************* Bit definition for RCC_CSR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 2188 | #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
| mbed_official | 126:549ba18ddd81 | 2189 | #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
| mbed_official | 126:549ba18ddd81 | 2190 | #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2191 | #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2192 | #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2193 | #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2194 | #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2195 | #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2196 | #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
| mbed_official | 126:549ba18ddd81 | 2197 | |
| mbed_official | 126:549ba18ddd81 | 2198 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 2199 | /******************* Bit definition for RCC_AHBRSTR register ****************/ |
| mbed_official | 126:549ba18ddd81 | 2200 | #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ |
| mbed_official | 126:549ba18ddd81 | 2201 | #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ |
| mbed_official | 126:549ba18ddd81 | 2202 | |
| mbed_official | 126:549ba18ddd81 | 2203 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2204 | /*!< PREDIV1 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2205 | #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 2206 | #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2207 | #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2208 | #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2209 | #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2210 | |
| mbed_official | 126:549ba18ddd81 | 2211 | #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
| mbed_official | 126:549ba18ddd81 | 2212 | #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 2213 | #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
| mbed_official | 126:549ba18ddd81 | 2214 | #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 2215 | #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
| mbed_official | 126:549ba18ddd81 | 2216 | #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
| mbed_official | 126:549ba18ddd81 | 2217 | #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
| mbed_official | 126:549ba18ddd81 | 2218 | #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 2219 | #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
| mbed_official | 126:549ba18ddd81 | 2220 | #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
| mbed_official | 126:549ba18ddd81 | 2221 | #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
| mbed_official | 126:549ba18ddd81 | 2222 | #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
| mbed_official | 126:549ba18ddd81 | 2223 | #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
| mbed_official | 126:549ba18ddd81 | 2224 | #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
| mbed_official | 126:549ba18ddd81 | 2225 | #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
| mbed_official | 126:549ba18ddd81 | 2226 | #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
| mbed_official | 126:549ba18ddd81 | 2227 | |
| mbed_official | 126:549ba18ddd81 | 2228 | /*!< PREDIV2 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2229 | #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 2230 | #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2231 | #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2232 | #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2233 | #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2234 | |
| mbed_official | 126:549ba18ddd81 | 2235 | #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ |
| mbed_official | 126:549ba18ddd81 | 2236 | #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 2237 | #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ |
| mbed_official | 126:549ba18ddd81 | 2238 | #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 2239 | #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ |
| mbed_official | 126:549ba18ddd81 | 2240 | #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ |
| mbed_official | 126:549ba18ddd81 | 2241 | #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ |
| mbed_official | 126:549ba18ddd81 | 2242 | #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 2243 | #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ |
| mbed_official | 126:549ba18ddd81 | 2244 | #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ |
| mbed_official | 126:549ba18ddd81 | 2245 | #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ |
| mbed_official | 126:549ba18ddd81 | 2246 | #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ |
| mbed_official | 126:549ba18ddd81 | 2247 | #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ |
| mbed_official | 126:549ba18ddd81 | 2248 | #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ |
| mbed_official | 126:549ba18ddd81 | 2249 | #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ |
| mbed_official | 126:549ba18ddd81 | 2250 | #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ |
| mbed_official | 126:549ba18ddd81 | 2251 | |
| mbed_official | 126:549ba18ddd81 | 2252 | /*!< PLL2MUL configuration */ |
| mbed_official | 126:549ba18ddd81 | 2253 | #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 2254 | #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2255 | #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2256 | #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2257 | #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2258 | |
| mbed_official | 126:549ba18ddd81 | 2259 | #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ |
| mbed_official | 126:549ba18ddd81 | 2260 | #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ |
| mbed_official | 126:549ba18ddd81 | 2261 | #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ |
| mbed_official | 126:549ba18ddd81 | 2262 | #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ |
| mbed_official | 126:549ba18ddd81 | 2263 | #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ |
| mbed_official | 126:549ba18ddd81 | 2264 | #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ |
| mbed_official | 126:549ba18ddd81 | 2265 | #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ |
| mbed_official | 126:549ba18ddd81 | 2266 | #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ |
| mbed_official | 126:549ba18ddd81 | 2267 | #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ |
| mbed_official | 126:549ba18ddd81 | 2268 | |
| mbed_official | 126:549ba18ddd81 | 2269 | /*!< PLL3MUL configuration */ |
| mbed_official | 126:549ba18ddd81 | 2270 | #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 2271 | #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2272 | #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2273 | #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2274 | #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2275 | |
| mbed_official | 126:549ba18ddd81 | 2276 | #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ |
| mbed_official | 126:549ba18ddd81 | 2277 | #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ |
| mbed_official | 126:549ba18ddd81 | 2278 | #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ |
| mbed_official | 126:549ba18ddd81 | 2279 | #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ |
| mbed_official | 126:549ba18ddd81 | 2280 | #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ |
| mbed_official | 126:549ba18ddd81 | 2281 | #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ |
| mbed_official | 126:549ba18ddd81 | 2282 | #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ |
| mbed_official | 126:549ba18ddd81 | 2283 | #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ |
| mbed_official | 126:549ba18ddd81 | 2284 | #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ |
| mbed_official | 126:549ba18ddd81 | 2285 | |
| mbed_official | 126:549ba18ddd81 | 2286 | #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 2287 | #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 2288 | #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 2289 | #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ |
| mbed_official | 126:549ba18ddd81 | 2290 | #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ |
| mbed_official | 126:549ba18ddd81 | 2291 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 2292 | |
| mbed_official | 126:549ba18ddd81 | 2293 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2294 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2295 | /*!< PREDIV1 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2296 | #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 2297 | #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2298 | #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2299 | #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2300 | #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2301 | |
| mbed_official | 126:549ba18ddd81 | 2302 | #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
| mbed_official | 126:549ba18ddd81 | 2303 | #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
| mbed_official | 126:549ba18ddd81 | 2304 | #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
| mbed_official | 126:549ba18ddd81 | 2305 | #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
| mbed_official | 126:549ba18ddd81 | 2306 | #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
| mbed_official | 126:549ba18ddd81 | 2307 | #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
| mbed_official | 126:549ba18ddd81 | 2308 | #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
| mbed_official | 126:549ba18ddd81 | 2309 | #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
| mbed_official | 126:549ba18ddd81 | 2310 | #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
| mbed_official | 126:549ba18ddd81 | 2311 | #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
| mbed_official | 126:549ba18ddd81 | 2312 | #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
| mbed_official | 126:549ba18ddd81 | 2313 | #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
| mbed_official | 126:549ba18ddd81 | 2314 | #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
| mbed_official | 126:549ba18ddd81 | 2315 | #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
| mbed_official | 126:549ba18ddd81 | 2316 | #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
| mbed_official | 126:549ba18ddd81 | 2317 | #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
| mbed_official | 126:549ba18ddd81 | 2318 | #endif |
| mbed_official | 126:549ba18ddd81 | 2319 | |
| mbed_official | 126:549ba18ddd81 | 2320 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 2321 | /* */ |
| mbed_official | 126:549ba18ddd81 | 2322 | /* General Purpose and Alternate Function I/O */ |
| mbed_official | 126:549ba18ddd81 | 2323 | /* */ |
| mbed_official | 126:549ba18ddd81 | 2324 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 2325 | |
| mbed_official | 126:549ba18ddd81 | 2326 | /******************* Bit definition for GPIO_CRL register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2327 | #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
| mbed_official | 126:549ba18ddd81 | 2328 | |
| mbed_official | 126:549ba18ddd81 | 2329 | #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
| mbed_official | 126:549ba18ddd81 | 2330 | #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2331 | #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2332 | |
| mbed_official | 126:549ba18ddd81 | 2333 | #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
| mbed_official | 126:549ba18ddd81 | 2334 | #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2335 | #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2336 | |
| mbed_official | 126:549ba18ddd81 | 2337 | #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
| mbed_official | 126:549ba18ddd81 | 2338 | #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2339 | #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2340 | |
| mbed_official | 126:549ba18ddd81 | 2341 | #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
| mbed_official | 126:549ba18ddd81 | 2342 | #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2343 | #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2344 | |
| mbed_official | 126:549ba18ddd81 | 2345 | #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
| mbed_official | 126:549ba18ddd81 | 2346 | #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2347 | #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2348 | |
| mbed_official | 126:549ba18ddd81 | 2349 | #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
| mbed_official | 126:549ba18ddd81 | 2350 | #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2351 | #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2352 | |
| mbed_official | 126:549ba18ddd81 | 2353 | #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
| mbed_official | 126:549ba18ddd81 | 2354 | #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2355 | #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2356 | |
| mbed_official | 126:549ba18ddd81 | 2357 | #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
| mbed_official | 126:549ba18ddd81 | 2358 | #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2359 | #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2360 | |
| mbed_official | 126:549ba18ddd81 | 2361 | #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
| mbed_official | 126:549ba18ddd81 | 2362 | |
| mbed_official | 126:549ba18ddd81 | 2363 | #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
| mbed_official | 126:549ba18ddd81 | 2364 | #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2365 | #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2366 | |
| mbed_official | 126:549ba18ddd81 | 2367 | #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
| mbed_official | 126:549ba18ddd81 | 2368 | #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2369 | #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2370 | |
| mbed_official | 126:549ba18ddd81 | 2371 | #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
| mbed_official | 126:549ba18ddd81 | 2372 | #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2373 | #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2374 | |
| mbed_official | 126:549ba18ddd81 | 2375 | #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
| mbed_official | 126:549ba18ddd81 | 2376 | #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2377 | #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2378 | |
| mbed_official | 126:549ba18ddd81 | 2379 | #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
| mbed_official | 126:549ba18ddd81 | 2380 | #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2381 | #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2382 | |
| mbed_official | 126:549ba18ddd81 | 2383 | #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
| mbed_official | 126:549ba18ddd81 | 2384 | #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2385 | #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2386 | |
| mbed_official | 126:549ba18ddd81 | 2387 | #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
| mbed_official | 126:549ba18ddd81 | 2388 | #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2389 | #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2390 | |
| mbed_official | 126:549ba18ddd81 | 2391 | #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
| mbed_official | 126:549ba18ddd81 | 2392 | #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2393 | #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2394 | |
| mbed_official | 126:549ba18ddd81 | 2395 | /******************* Bit definition for GPIO_CRH register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2396 | #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
| mbed_official | 126:549ba18ddd81 | 2397 | |
| mbed_official | 126:549ba18ddd81 | 2398 | #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
| mbed_official | 126:549ba18ddd81 | 2399 | #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2400 | #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2401 | |
| mbed_official | 126:549ba18ddd81 | 2402 | #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
| mbed_official | 126:549ba18ddd81 | 2403 | #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2404 | #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2405 | |
| mbed_official | 126:549ba18ddd81 | 2406 | #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
| mbed_official | 126:549ba18ddd81 | 2407 | #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2408 | #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2409 | |
| mbed_official | 126:549ba18ddd81 | 2410 | #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
| mbed_official | 126:549ba18ddd81 | 2411 | #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2412 | #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2413 | |
| mbed_official | 126:549ba18ddd81 | 2414 | #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
| mbed_official | 126:549ba18ddd81 | 2415 | #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2416 | #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2417 | |
| mbed_official | 126:549ba18ddd81 | 2418 | #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
| mbed_official | 126:549ba18ddd81 | 2419 | #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2420 | #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2421 | |
| mbed_official | 126:549ba18ddd81 | 2422 | #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
| mbed_official | 126:549ba18ddd81 | 2423 | #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2424 | #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2425 | |
| mbed_official | 126:549ba18ddd81 | 2426 | #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
| mbed_official | 126:549ba18ddd81 | 2427 | #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2428 | #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2429 | |
| mbed_official | 126:549ba18ddd81 | 2430 | #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
| mbed_official | 126:549ba18ddd81 | 2431 | |
| mbed_official | 126:549ba18ddd81 | 2432 | #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
| mbed_official | 126:549ba18ddd81 | 2433 | #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2434 | #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2435 | |
| mbed_official | 126:549ba18ddd81 | 2436 | #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
| mbed_official | 126:549ba18ddd81 | 2437 | #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2438 | #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2439 | |
| mbed_official | 126:549ba18ddd81 | 2440 | #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
| mbed_official | 126:549ba18ddd81 | 2441 | #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2442 | #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2443 | |
| mbed_official | 126:549ba18ddd81 | 2444 | #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
| mbed_official | 126:549ba18ddd81 | 2445 | #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2446 | #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2447 | |
| mbed_official | 126:549ba18ddd81 | 2448 | #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
| mbed_official | 126:549ba18ddd81 | 2449 | #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2450 | #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2451 | |
| mbed_official | 126:549ba18ddd81 | 2452 | #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
| mbed_official | 126:549ba18ddd81 | 2453 | #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2454 | #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2455 | |
| mbed_official | 126:549ba18ddd81 | 2456 | #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
| mbed_official | 126:549ba18ddd81 | 2457 | #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2458 | #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2459 | |
| mbed_official | 126:549ba18ddd81 | 2460 | #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
| mbed_official | 126:549ba18ddd81 | 2461 | #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2462 | #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2463 | |
| mbed_official | 126:549ba18ddd81 | 2464 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2465 | #define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2466 | #define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2467 | #define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2468 | #define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2469 | #define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2470 | #define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2471 | #define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2472 | #define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2473 | #define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2474 | #define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2475 | #define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2476 | #define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2477 | #define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2478 | #define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2479 | #define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2480 | #define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2481 | |
| mbed_official | 126:549ba18ddd81 | 2482 | /******************* Bit definition for GPIO_ODR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2483 | #define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2484 | #define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2485 | #define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2486 | #define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2487 | #define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2488 | #define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2489 | #define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2490 | #define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2491 | #define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2492 | #define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2493 | #define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2494 | #define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2495 | #define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2496 | #define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2497 | #define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2498 | #define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2499 | |
| mbed_official | 126:549ba18ddd81 | 2500 | /****************** Bit definition for GPIO_BSRR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2501 | #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2502 | #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2503 | #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2504 | #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2505 | #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2506 | #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2507 | #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2508 | #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2509 | #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2510 | #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2511 | #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2512 | #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2513 | #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2514 | #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2515 | #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2516 | #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2517 | |
| mbed_official | 126:549ba18ddd81 | 2518 | #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2519 | #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2520 | #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2521 | #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2522 | #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2523 | #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2524 | #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2525 | #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2526 | #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2527 | #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2528 | #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2529 | #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2530 | #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2531 | #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2532 | #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2533 | #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2534 | |
| mbed_official | 126:549ba18ddd81 | 2535 | /******************* Bit definition for GPIO_BRR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2536 | #define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2537 | #define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2538 | #define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2539 | #define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2540 | #define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2541 | #define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2542 | #define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2543 | #define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2544 | #define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2545 | #define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2546 | #define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2547 | #define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2548 | #define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2549 | #define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2550 | #define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2551 | #define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2552 | |
| mbed_official | 126:549ba18ddd81 | 2553 | /****************** Bit definition for GPIO_LCKR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2554 | #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2555 | #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2556 | #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2557 | #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2558 | #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2559 | #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2560 | #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2561 | #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2562 | #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2563 | #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2564 | #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2565 | #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2566 | #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2567 | #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2568 | #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2569 | #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2570 | #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ |
| mbed_official | 126:549ba18ddd81 | 2571 | |
| mbed_official | 126:549ba18ddd81 | 2572 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 2573 | |
| mbed_official | 126:549ba18ddd81 | 2574 | /****************** Bit definition for AFIO_EVCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2575 | #define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ |
| mbed_official | 126:549ba18ddd81 | 2576 | #define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2577 | #define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2578 | #define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2579 | #define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2580 | |
| mbed_official | 126:549ba18ddd81 | 2581 | /*!< PIN configuration */ |
| mbed_official | 126:549ba18ddd81 | 2582 | #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ |
| mbed_official | 126:549ba18ddd81 | 2583 | #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ |
| mbed_official | 126:549ba18ddd81 | 2584 | #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ |
| mbed_official | 126:549ba18ddd81 | 2585 | #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ |
| mbed_official | 126:549ba18ddd81 | 2586 | #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ |
| mbed_official | 126:549ba18ddd81 | 2587 | #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ |
| mbed_official | 126:549ba18ddd81 | 2588 | #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ |
| mbed_official | 126:549ba18ddd81 | 2589 | #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ |
| mbed_official | 126:549ba18ddd81 | 2590 | #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ |
| mbed_official | 126:549ba18ddd81 | 2591 | #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ |
| mbed_official | 126:549ba18ddd81 | 2592 | #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ |
| mbed_official | 126:549ba18ddd81 | 2593 | #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ |
| mbed_official | 126:549ba18ddd81 | 2594 | #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ |
| mbed_official | 126:549ba18ddd81 | 2595 | #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ |
| mbed_official | 126:549ba18ddd81 | 2596 | #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ |
| mbed_official | 126:549ba18ddd81 | 2597 | #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ |
| mbed_official | 126:549ba18ddd81 | 2598 | |
| mbed_official | 126:549ba18ddd81 | 2599 | #define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ |
| mbed_official | 126:549ba18ddd81 | 2600 | #define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2601 | #define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2602 | #define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2603 | |
| mbed_official | 126:549ba18ddd81 | 2604 | /*!< PORT configuration */ |
| mbed_official | 126:549ba18ddd81 | 2605 | #define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ |
| mbed_official | 126:549ba18ddd81 | 2606 | #define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ |
| mbed_official | 126:549ba18ddd81 | 2607 | #define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ |
| mbed_official | 126:549ba18ddd81 | 2608 | #define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ |
| mbed_official | 126:549ba18ddd81 | 2609 | #define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ |
| mbed_official | 126:549ba18ddd81 | 2610 | |
| mbed_official | 126:549ba18ddd81 | 2611 | #define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ |
| mbed_official | 126:549ba18ddd81 | 2612 | |
| mbed_official | 126:549ba18ddd81 | 2613 | /****************** Bit definition for AFIO_MAPR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2614 | #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2615 | #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2616 | #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2617 | #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2618 | |
| mbed_official | 126:549ba18ddd81 | 2619 | #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2620 | #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2621 | #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2622 | |
| mbed_official | 126:549ba18ddd81 | 2623 | /* USART3_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2624 | #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
| mbed_official | 126:549ba18ddd81 | 2625 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
| mbed_official | 126:549ba18ddd81 | 2626 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
| mbed_official | 126:549ba18ddd81 | 2627 | |
| mbed_official | 126:549ba18ddd81 | 2628 | #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2629 | #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2630 | #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2631 | |
| mbed_official | 126:549ba18ddd81 | 2632 | /*!< TIM1_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2633 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
| mbed_official | 126:549ba18ddd81 | 2634 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
| mbed_official | 126:549ba18ddd81 | 2635 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
| mbed_official | 126:549ba18ddd81 | 2636 | |
| mbed_official | 126:549ba18ddd81 | 2637 | #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2638 | #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2639 | #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2640 | |
| mbed_official | 126:549ba18ddd81 | 2641 | /*!< TIM2_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2642 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
| mbed_official | 126:549ba18ddd81 | 2643 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
| mbed_official | 126:549ba18ddd81 | 2644 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
| mbed_official | 126:549ba18ddd81 | 2645 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
| mbed_official | 126:549ba18ddd81 | 2646 | |
| mbed_official | 126:549ba18ddd81 | 2647 | #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2648 | #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2649 | #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2650 | |
| mbed_official | 126:549ba18ddd81 | 2651 | /*!< TIM3_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2652 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
| mbed_official | 126:549ba18ddd81 | 2653 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
| mbed_official | 126:549ba18ddd81 | 2654 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
| mbed_official | 126:549ba18ddd81 | 2655 | |
| mbed_official | 126:549ba18ddd81 | 2656 | #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2657 | |
| mbed_official | 126:549ba18ddd81 | 2658 | #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2659 | #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2660 | #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2661 | |
| mbed_official | 126:549ba18ddd81 | 2662 | /*!< CAN_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2663 | #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
| mbed_official | 126:549ba18ddd81 | 2664 | #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
| mbed_official | 126:549ba18ddd81 | 2665 | #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
| mbed_official | 126:549ba18ddd81 | 2666 | |
| mbed_official | 126:549ba18ddd81 | 2667 | #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
| mbed_official | 126:549ba18ddd81 | 2668 | #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ |
| mbed_official | 126:549ba18ddd81 | 2669 | #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ |
| mbed_official | 126:549ba18ddd81 | 2670 | #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ |
| mbed_official | 126:549ba18ddd81 | 2671 | #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ |
| mbed_official | 126:549ba18ddd81 | 2672 | #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ |
| mbed_official | 126:549ba18ddd81 | 2673 | |
| mbed_official | 126:549ba18ddd81 | 2674 | /*!< SWJ_CFG configuration */ |
| mbed_official | 126:549ba18ddd81 | 2675 | #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
| mbed_official | 126:549ba18ddd81 | 2676 | #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2677 | #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2678 | #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2679 | |
| mbed_official | 126:549ba18ddd81 | 2680 | #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
| mbed_official | 126:549ba18ddd81 | 2681 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
| mbed_official | 126:549ba18ddd81 | 2682 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
| mbed_official | 126:549ba18ddd81 | 2683 | #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ |
| mbed_official | 126:549ba18ddd81 | 2684 | |
| mbed_official | 126:549ba18ddd81 | 2685 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 2686 | /*!< ETH_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2687 | #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2688 | |
| mbed_official | 126:549ba18ddd81 | 2689 | /*!< CAN2_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2690 | #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2691 | |
| mbed_official | 126:549ba18ddd81 | 2692 | /*!< MII_RMII_SEL configuration */ |
| mbed_official | 126:549ba18ddd81 | 2693 | #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ |
| mbed_official | 126:549ba18ddd81 | 2694 | |
| mbed_official | 126:549ba18ddd81 | 2695 | /*!< SPI3_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2696 | #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2697 | |
| mbed_official | 126:549ba18ddd81 | 2698 | /*!< TIM2ITR1_IREMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2699 | #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2700 | |
| mbed_official | 126:549ba18ddd81 | 2701 | /*!< PTP_PPS_REMAP configuration */ |
| mbed_official | 126:549ba18ddd81 | 2702 | #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ |
| mbed_official | 126:549ba18ddd81 | 2703 | #endif |
| mbed_official | 126:549ba18ddd81 | 2704 | |
| mbed_official | 126:549ba18ddd81 | 2705 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2706 | #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2707 | #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2708 | #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2709 | #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2710 | |
| mbed_official | 126:549ba18ddd81 | 2711 | /*!< EXTI0 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2712 | #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2713 | #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2714 | #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2715 | #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2716 | #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2717 | #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2718 | #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ |
| mbed_official | 126:549ba18ddd81 | 2719 | |
| mbed_official | 126:549ba18ddd81 | 2720 | /*!< EXTI1 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2721 | #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2722 | #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2723 | #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2724 | #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2725 | #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2726 | #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2727 | #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ |
| mbed_official | 126:549ba18ddd81 | 2728 | |
| mbed_official | 126:549ba18ddd81 | 2729 | /*!< EXTI2 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2730 | #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2731 | #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2732 | #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2733 | #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2734 | #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2735 | #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2736 | #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ |
| mbed_official | 126:549ba18ddd81 | 2737 | |
| mbed_official | 126:549ba18ddd81 | 2738 | /*!< EXTI3 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2739 | #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2740 | #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2741 | #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2742 | #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2743 | #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2744 | #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2745 | #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ |
| mbed_official | 126:549ba18ddd81 | 2746 | |
| mbed_official | 126:549ba18ddd81 | 2747 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2748 | #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2749 | #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2750 | #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2751 | #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2752 | |
| mbed_official | 126:549ba18ddd81 | 2753 | /*!< EXTI4 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2754 | #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2755 | #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2756 | #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2757 | #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2758 | #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2759 | #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2760 | #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ |
| mbed_official | 126:549ba18ddd81 | 2761 | |
| mbed_official | 126:549ba18ddd81 | 2762 | /* EXTI5 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2763 | #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2764 | #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2765 | #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2766 | #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2767 | #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2768 | #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2769 | #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ |
| mbed_official | 126:549ba18ddd81 | 2770 | |
| mbed_official | 126:549ba18ddd81 | 2771 | /*!< EXTI6 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2772 | #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2773 | #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2774 | #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2775 | #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2776 | #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2777 | #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2778 | #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ |
| mbed_official | 126:549ba18ddd81 | 2779 | |
| mbed_official | 126:549ba18ddd81 | 2780 | /*!< EXTI7 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2781 | #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2782 | #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2783 | #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2784 | #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2785 | #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2786 | #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2787 | #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ |
| mbed_official | 126:549ba18ddd81 | 2788 | |
| mbed_official | 126:549ba18ddd81 | 2789 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2790 | #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2791 | #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2792 | #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2793 | #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2794 | |
| mbed_official | 126:549ba18ddd81 | 2795 | /*!< EXTI8 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2796 | #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2797 | #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2798 | #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2799 | #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2800 | #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2801 | #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2802 | #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ |
| mbed_official | 126:549ba18ddd81 | 2803 | |
| mbed_official | 126:549ba18ddd81 | 2804 | /*!< EXTI9 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2805 | #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2806 | #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2807 | #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2808 | #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2809 | #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2810 | #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2811 | #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ |
| mbed_official | 126:549ba18ddd81 | 2812 | |
| mbed_official | 126:549ba18ddd81 | 2813 | /*!< EXTI10 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2814 | #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2815 | #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2816 | #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2817 | #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2818 | #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2819 | #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2820 | #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ |
| mbed_official | 126:549ba18ddd81 | 2821 | |
| mbed_official | 126:549ba18ddd81 | 2822 | /*!< EXTI11 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2823 | #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2824 | #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2825 | #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2826 | #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2827 | #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2828 | #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2829 | #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ |
| mbed_official | 126:549ba18ddd81 | 2830 | |
| mbed_official | 126:549ba18ddd81 | 2831 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2832 | #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2833 | #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2834 | #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2835 | #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2836 | |
| mbed_official | 126:549ba18ddd81 | 2837 | /* EXTI12 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2838 | #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2839 | #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2840 | #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2841 | #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2842 | #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2843 | #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2844 | #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ |
| mbed_official | 126:549ba18ddd81 | 2845 | |
| mbed_official | 126:549ba18ddd81 | 2846 | /* EXTI13 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2847 | #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2848 | #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2849 | #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2850 | #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2851 | #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2852 | #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2853 | #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ |
| mbed_official | 126:549ba18ddd81 | 2854 | |
| mbed_official | 126:549ba18ddd81 | 2855 | /*!< EXTI14 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2856 | #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2857 | #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2858 | #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2859 | #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2860 | #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2861 | #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2862 | #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ |
| mbed_official | 126:549ba18ddd81 | 2863 | |
| mbed_official | 126:549ba18ddd81 | 2864 | /*!< EXTI15 configuration */ |
| mbed_official | 126:549ba18ddd81 | 2865 | #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2866 | #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2867 | #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2868 | #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2869 | #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2870 | #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2871 | #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ |
| mbed_official | 126:549ba18ddd81 | 2872 | |
| mbed_official | 126:549ba18ddd81 | 2873 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 2874 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2875 | #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2876 | #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2877 | #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2878 | #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ |
| mbed_official | 126:549ba18ddd81 | 2879 | #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ |
| mbed_official | 126:549ba18ddd81 | 2880 | #endif |
| mbed_official | 126:549ba18ddd81 | 2881 | |
| mbed_official | 126:549ba18ddd81 | 2882 | #ifdef STM32F10X_HD_VL |
| mbed_official | 126:549ba18ddd81 | 2883 | #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2884 | #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2885 | #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
| mbed_official | 126:549ba18ddd81 | 2886 | #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ |
| mbed_official | 126:549ba18ddd81 | 2887 | #define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2888 | #define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ |
| mbed_official | 126:549ba18ddd81 | 2889 | #endif |
| mbed_official | 126:549ba18ddd81 | 2890 | |
| mbed_official | 126:549ba18ddd81 | 2891 | #ifdef STM32F10X_XL |
| mbed_official | 126:549ba18ddd81 | 2892 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2893 | #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2894 | #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2895 | #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2896 | #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2897 | #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
| mbed_official | 126:549ba18ddd81 | 2898 | #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
| mbed_official | 126:549ba18ddd81 | 2899 | #endif |
| mbed_official | 126:549ba18ddd81 | 2900 | |
| mbed_official | 126:549ba18ddd81 | 2901 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 2902 | /* */ |
| mbed_official | 126:549ba18ddd81 | 2903 | /* SystemTick */ |
| mbed_official | 126:549ba18ddd81 | 2904 | /* */ |
| mbed_official | 126:549ba18ddd81 | 2905 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 2906 | |
| mbed_official | 126:549ba18ddd81 | 2907 | /***************** Bit definition for SysTick_CTRL register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2908 | #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ |
| mbed_official | 126:549ba18ddd81 | 2909 | #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ |
| mbed_official | 126:549ba18ddd81 | 2910 | #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ |
| mbed_official | 126:549ba18ddd81 | 2911 | #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ |
| mbed_official | 126:549ba18ddd81 | 2912 | |
| mbed_official | 126:549ba18ddd81 | 2913 | /***************** Bit definition for SysTick_LOAD register *****************/ |
| mbed_official | 126:549ba18ddd81 | 2914 | #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
| mbed_official | 126:549ba18ddd81 | 2915 | |
| mbed_official | 126:549ba18ddd81 | 2916 | /***************** Bit definition for SysTick_VAL register ******************/ |
| mbed_official | 126:549ba18ddd81 | 2917 | #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ |
| mbed_official | 126:549ba18ddd81 | 2918 | |
| mbed_official | 126:549ba18ddd81 | 2919 | /***************** Bit definition for SysTick_CALIB register ****************/ |
| mbed_official | 126:549ba18ddd81 | 2920 | #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ |
| mbed_official | 126:549ba18ddd81 | 2921 | #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ |
| mbed_official | 126:549ba18ddd81 | 2922 | #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ |
| mbed_official | 126:549ba18ddd81 | 2923 | |
| mbed_official | 126:549ba18ddd81 | 2924 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 2925 | /* */ |
| mbed_official | 126:549ba18ddd81 | 2926 | /* Nested Vectored Interrupt Controller */ |
| mbed_official | 126:549ba18ddd81 | 2927 | /* */ |
| mbed_official | 126:549ba18ddd81 | 2928 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 2929 | |
| mbed_official | 126:549ba18ddd81 | 2930 | /****************** Bit definition for NVIC_ISER register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2931 | #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ |
| mbed_official | 126:549ba18ddd81 | 2932 | #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2933 | #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2934 | #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2935 | #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2936 | #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2937 | #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2938 | #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2939 | #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2940 | #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2941 | #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2942 | #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2943 | #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2944 | #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2945 | #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2946 | #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2947 | #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2948 | #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 2949 | #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 2950 | #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 2951 | #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 2952 | #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 2953 | #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 2954 | #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 2955 | #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 2956 | #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 2957 | #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 2958 | #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 2959 | #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 2960 | #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 2961 | #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 2962 | #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 2963 | #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 2964 | |
| mbed_official | 126:549ba18ddd81 | 2965 | /****************** Bit definition for NVIC_ICER register *******************/ |
| mbed_official | 126:549ba18ddd81 | 2966 | #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ |
| mbed_official | 126:549ba18ddd81 | 2967 | #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 2968 | #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 2969 | #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 2970 | #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 2971 | #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 2972 | #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 2973 | #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 2974 | #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 2975 | #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 2976 | #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 2977 | #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 2978 | #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 2979 | #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 2980 | #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 2981 | #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 2982 | #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 2983 | #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 2984 | #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 2985 | #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 2986 | #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 2987 | #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 2988 | #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 2989 | #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 2990 | #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 2991 | #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 2992 | #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 2993 | #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 2994 | #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 2995 | #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 2996 | #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 2997 | #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 2998 | #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 2999 | |
| mbed_official | 126:549ba18ddd81 | 3000 | /****************** Bit definition for NVIC_ISPR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3001 | #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ |
| mbed_official | 126:549ba18ddd81 | 3002 | #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3003 | #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3004 | #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3005 | #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3006 | #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3007 | #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 3008 | #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 3009 | #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 3010 | #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 3011 | #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 3012 | #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 3013 | #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 3014 | #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 3015 | #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 3016 | #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 3017 | #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 3018 | #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 3019 | #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 3020 | #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 3021 | #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 3022 | #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 3023 | #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 3024 | #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 3025 | #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 3026 | #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 3027 | #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 3028 | #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 3029 | #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 3030 | #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 3031 | #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 3032 | #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 3033 | #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 3034 | |
| mbed_official | 126:549ba18ddd81 | 3035 | /****************** Bit definition for NVIC_ICPR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3036 | #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ |
| mbed_official | 126:549ba18ddd81 | 3037 | #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3038 | #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3039 | #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3040 | #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3041 | #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3042 | #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 3043 | #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 3044 | #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 3045 | #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 3046 | #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 3047 | #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 3048 | #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 3049 | #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 3050 | #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 3051 | #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 3052 | #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 3053 | #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 3054 | #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 3055 | #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 3056 | #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 3057 | #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 3058 | #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 3059 | #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 3060 | #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 3061 | #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 3062 | #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 3063 | #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 3064 | #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 3065 | #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 3066 | #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 3067 | #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 3068 | #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 3069 | |
| mbed_official | 126:549ba18ddd81 | 3070 | /****************** Bit definition for NVIC_IABR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3071 | #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ |
| mbed_official | 126:549ba18ddd81 | 3072 | #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3073 | #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3074 | #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3075 | #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3076 | #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3077 | #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 3078 | #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 3079 | #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 3080 | #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 3081 | #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 3082 | #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 3083 | #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 3084 | #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 3085 | #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 3086 | #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 3087 | #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 3088 | #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 3089 | #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 3090 | #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 3091 | #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 3092 | #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 3093 | #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 3094 | #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 3095 | #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 3096 | #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 3097 | #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 3098 | #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 3099 | #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 3100 | #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 3101 | #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 3102 | #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 3103 | #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 3104 | |
| mbed_official | 126:549ba18ddd81 | 3105 | /****************** Bit definition for NVIC_PRI0 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3106 | #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ |
| mbed_official | 126:549ba18ddd81 | 3107 | #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ |
| mbed_official | 126:549ba18ddd81 | 3108 | #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ |
| mbed_official | 126:549ba18ddd81 | 3109 | #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ |
| mbed_official | 126:549ba18ddd81 | 3110 | |
| mbed_official | 126:549ba18ddd81 | 3111 | /****************** Bit definition for NVIC_PRI1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3112 | #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ |
| mbed_official | 126:549ba18ddd81 | 3113 | #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ |
| mbed_official | 126:549ba18ddd81 | 3114 | #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ |
| mbed_official | 126:549ba18ddd81 | 3115 | #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ |
| mbed_official | 126:549ba18ddd81 | 3116 | |
| mbed_official | 126:549ba18ddd81 | 3117 | /****************** Bit definition for NVIC_PRI2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3118 | #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ |
| mbed_official | 126:549ba18ddd81 | 3119 | #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ |
| mbed_official | 126:549ba18ddd81 | 3120 | #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ |
| mbed_official | 126:549ba18ddd81 | 3121 | #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ |
| mbed_official | 126:549ba18ddd81 | 3122 | |
| mbed_official | 126:549ba18ddd81 | 3123 | /****************** Bit definition for NVIC_PRI3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3124 | #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ |
| mbed_official | 126:549ba18ddd81 | 3125 | #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ |
| mbed_official | 126:549ba18ddd81 | 3126 | #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ |
| mbed_official | 126:549ba18ddd81 | 3127 | #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ |
| mbed_official | 126:549ba18ddd81 | 3128 | |
| mbed_official | 126:549ba18ddd81 | 3129 | /****************** Bit definition for NVIC_PRI4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3130 | #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ |
| mbed_official | 126:549ba18ddd81 | 3131 | #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ |
| mbed_official | 126:549ba18ddd81 | 3132 | #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ |
| mbed_official | 126:549ba18ddd81 | 3133 | #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ |
| mbed_official | 126:549ba18ddd81 | 3134 | |
| mbed_official | 126:549ba18ddd81 | 3135 | /****************** Bit definition for NVIC_PRI5 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3136 | #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ |
| mbed_official | 126:549ba18ddd81 | 3137 | #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ |
| mbed_official | 126:549ba18ddd81 | 3138 | #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ |
| mbed_official | 126:549ba18ddd81 | 3139 | #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ |
| mbed_official | 126:549ba18ddd81 | 3140 | |
| mbed_official | 126:549ba18ddd81 | 3141 | /****************** Bit definition for NVIC_PRI6 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3142 | #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ |
| mbed_official | 126:549ba18ddd81 | 3143 | #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ |
| mbed_official | 126:549ba18ddd81 | 3144 | #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ |
| mbed_official | 126:549ba18ddd81 | 3145 | #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ |
| mbed_official | 126:549ba18ddd81 | 3146 | |
| mbed_official | 126:549ba18ddd81 | 3147 | /****************** Bit definition for NVIC_PRI7 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3148 | #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ |
| mbed_official | 126:549ba18ddd81 | 3149 | #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ |
| mbed_official | 126:549ba18ddd81 | 3150 | #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ |
| mbed_official | 126:549ba18ddd81 | 3151 | #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ |
| mbed_official | 126:549ba18ddd81 | 3152 | |
| mbed_official | 126:549ba18ddd81 | 3153 | /****************** Bit definition for SCB_CPUID register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3154 | #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ |
| mbed_official | 126:549ba18ddd81 | 3155 | #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ |
| mbed_official | 126:549ba18ddd81 | 3156 | #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ |
| mbed_official | 126:549ba18ddd81 | 3157 | #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ |
| mbed_official | 126:549ba18ddd81 | 3158 | #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ |
| mbed_official | 126:549ba18ddd81 | 3159 | |
| mbed_official | 126:549ba18ddd81 | 3160 | /******************* Bit definition for SCB_ICSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3161 | #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ |
| mbed_official | 126:549ba18ddd81 | 3162 | #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
| mbed_official | 126:549ba18ddd81 | 3163 | #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ |
| mbed_official | 126:549ba18ddd81 | 3164 | #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ |
| mbed_official | 126:549ba18ddd81 | 3165 | #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
| mbed_official | 126:549ba18ddd81 | 3166 | #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ |
| mbed_official | 126:549ba18ddd81 | 3167 | #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ |
| mbed_official | 126:549ba18ddd81 | 3168 | #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ |
| mbed_official | 126:549ba18ddd81 | 3169 | #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ |
| mbed_official | 126:549ba18ddd81 | 3170 | #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ |
| mbed_official | 126:549ba18ddd81 | 3171 | |
| mbed_official | 126:549ba18ddd81 | 3172 | /******************* Bit definition for SCB_VTOR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3173 | #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ |
| mbed_official | 126:549ba18ddd81 | 3174 | #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ |
| mbed_official | 126:549ba18ddd81 | 3175 | |
| mbed_official | 126:549ba18ddd81 | 3176 | /*!<***************** Bit definition for SCB_AIRCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3177 | #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ |
| mbed_official | 126:549ba18ddd81 | 3178 | #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ |
| mbed_official | 126:549ba18ddd81 | 3179 | #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ |
| mbed_official | 126:549ba18ddd81 | 3180 | |
| mbed_official | 126:549ba18ddd81 | 3181 | #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ |
| mbed_official | 126:549ba18ddd81 | 3182 | #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3183 | #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3184 | #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3185 | |
| mbed_official | 126:549ba18ddd81 | 3186 | /* prority group configuration */ |
| mbed_official | 126:549ba18ddd81 | 3187 | #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3188 | #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3189 | #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3190 | #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3191 | #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3192 | #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3193 | #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3194 | #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
| mbed_official | 126:549ba18ddd81 | 3195 | |
| mbed_official | 126:549ba18ddd81 | 3196 | #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ |
| mbed_official | 126:549ba18ddd81 | 3197 | #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
| mbed_official | 126:549ba18ddd81 | 3198 | |
| mbed_official | 126:549ba18ddd81 | 3199 | /******************* Bit definition for SCB_SCR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3200 | #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ |
| mbed_official | 126:549ba18ddd81 | 3201 | #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ |
| mbed_official | 126:549ba18ddd81 | 3202 | #define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ |
| mbed_official | 126:549ba18ddd81 | 3203 | |
| mbed_official | 126:549ba18ddd81 | 3204 | /******************** Bit definition for SCB_CCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3205 | #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
| mbed_official | 126:549ba18ddd81 | 3206 | #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
| mbed_official | 126:549ba18ddd81 | 3207 | #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ |
| mbed_official | 126:549ba18ddd81 | 3208 | #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ |
| mbed_official | 126:549ba18ddd81 | 3209 | #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ |
| mbed_official | 126:549ba18ddd81 | 3210 | #define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
| mbed_official | 126:549ba18ddd81 | 3211 | |
| mbed_official | 126:549ba18ddd81 | 3212 | /******************* Bit definition for SCB_SHPR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3213 | #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
| mbed_official | 126:549ba18ddd81 | 3214 | #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
| mbed_official | 126:549ba18ddd81 | 3215 | #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
| mbed_official | 126:549ba18ddd81 | 3216 | #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
| mbed_official | 126:549ba18ddd81 | 3217 | |
| mbed_official | 126:549ba18ddd81 | 3218 | /****************** Bit definition for SCB_SHCSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3219 | #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ |
| mbed_official | 126:549ba18ddd81 | 3220 | #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ |
| mbed_official | 126:549ba18ddd81 | 3221 | #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ |
| mbed_official | 126:549ba18ddd81 | 3222 | #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ |
| mbed_official | 126:549ba18ddd81 | 3223 | #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ |
| mbed_official | 126:549ba18ddd81 | 3224 | #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ |
| mbed_official | 126:549ba18ddd81 | 3225 | #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ |
| mbed_official | 126:549ba18ddd81 | 3226 | #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ |
| mbed_official | 126:549ba18ddd81 | 3227 | #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ |
| mbed_official | 126:549ba18ddd81 | 3228 | #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ |
| mbed_official | 126:549ba18ddd81 | 3229 | #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ |
| mbed_official | 126:549ba18ddd81 | 3230 | #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ |
| mbed_official | 126:549ba18ddd81 | 3231 | #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ |
| mbed_official | 126:549ba18ddd81 | 3232 | #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ |
| mbed_official | 126:549ba18ddd81 | 3233 | |
| mbed_official | 126:549ba18ddd81 | 3234 | /******************* Bit definition for SCB_CFSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3235 | /*!< MFSR */ |
| mbed_official | 126:549ba18ddd81 | 3236 | #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ |
| mbed_official | 126:549ba18ddd81 | 3237 | #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ |
| mbed_official | 126:549ba18ddd81 | 3238 | #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ |
| mbed_official | 126:549ba18ddd81 | 3239 | #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ |
| mbed_official | 126:549ba18ddd81 | 3240 | #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ |
| mbed_official | 126:549ba18ddd81 | 3241 | /*!< BFSR */ |
| mbed_official | 126:549ba18ddd81 | 3242 | #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ |
| mbed_official | 126:549ba18ddd81 | 3243 | #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ |
| mbed_official | 126:549ba18ddd81 | 3244 | #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ |
| mbed_official | 126:549ba18ddd81 | 3245 | #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ |
| mbed_official | 126:549ba18ddd81 | 3246 | #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ |
| mbed_official | 126:549ba18ddd81 | 3247 | #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ |
| mbed_official | 126:549ba18ddd81 | 3248 | /*!< UFSR */ |
| mbed_official | 126:549ba18ddd81 | 3249 | #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ |
| mbed_official | 126:549ba18ddd81 | 3250 | #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ |
| mbed_official | 126:549ba18ddd81 | 3251 | #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ |
| mbed_official | 126:549ba18ddd81 | 3252 | #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ |
| mbed_official | 126:549ba18ddd81 | 3253 | #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
| mbed_official | 126:549ba18ddd81 | 3254 | #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
| mbed_official | 126:549ba18ddd81 | 3255 | |
| mbed_official | 126:549ba18ddd81 | 3256 | /******************* Bit definition for SCB_HFSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3257 | #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ |
| mbed_official | 126:549ba18ddd81 | 3258 | #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
| mbed_official | 126:549ba18ddd81 | 3259 | #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ |
| mbed_official | 126:549ba18ddd81 | 3260 | |
| mbed_official | 126:549ba18ddd81 | 3261 | /******************* Bit definition for SCB_DFSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3262 | #define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ |
| mbed_official | 126:549ba18ddd81 | 3263 | #define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ |
| mbed_official | 126:549ba18ddd81 | 3264 | #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ |
| mbed_official | 126:549ba18ddd81 | 3265 | #define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ |
| mbed_official | 126:549ba18ddd81 | 3266 | #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ |
| mbed_official | 126:549ba18ddd81 | 3267 | |
| mbed_official | 126:549ba18ddd81 | 3268 | /******************* Bit definition for SCB_MMFAR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3269 | #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ |
| mbed_official | 126:549ba18ddd81 | 3270 | |
| mbed_official | 126:549ba18ddd81 | 3271 | /******************* Bit definition for SCB_BFAR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3272 | #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ |
| mbed_official | 126:549ba18ddd81 | 3273 | |
| mbed_official | 126:549ba18ddd81 | 3274 | /******************* Bit definition for SCB_afsr register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3275 | #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ |
| mbed_official | 126:549ba18ddd81 | 3276 | |
| mbed_official | 126:549ba18ddd81 | 3277 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 3278 | /* */ |
| mbed_official | 126:549ba18ddd81 | 3279 | /* External Interrupt/Event Controller */ |
| mbed_official | 126:549ba18ddd81 | 3280 | /* */ |
| mbed_official | 126:549ba18ddd81 | 3281 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 3282 | |
| mbed_official | 126:549ba18ddd81 | 3283 | /******************* Bit definition for EXTI_IMR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3284 | #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
| mbed_official | 126:549ba18ddd81 | 3285 | #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
| mbed_official | 126:549ba18ddd81 | 3286 | #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
| mbed_official | 126:549ba18ddd81 | 3287 | #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
| mbed_official | 126:549ba18ddd81 | 3288 | #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
| mbed_official | 126:549ba18ddd81 | 3289 | #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
| mbed_official | 126:549ba18ddd81 | 3290 | #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
| mbed_official | 126:549ba18ddd81 | 3291 | #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
| mbed_official | 126:549ba18ddd81 | 3292 | #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
| mbed_official | 126:549ba18ddd81 | 3293 | #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
| mbed_official | 126:549ba18ddd81 | 3294 | #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
| mbed_official | 126:549ba18ddd81 | 3295 | #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
| mbed_official | 126:549ba18ddd81 | 3296 | #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
| mbed_official | 126:549ba18ddd81 | 3297 | #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
| mbed_official | 126:549ba18ddd81 | 3298 | #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
| mbed_official | 126:549ba18ddd81 | 3299 | #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
| mbed_official | 126:549ba18ddd81 | 3300 | #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
| mbed_official | 126:549ba18ddd81 | 3301 | #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
| mbed_official | 126:549ba18ddd81 | 3302 | #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
| mbed_official | 126:549ba18ddd81 | 3303 | #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
| mbed_official | 126:549ba18ddd81 | 3304 | |
| mbed_official | 126:549ba18ddd81 | 3305 | /******************* Bit definition for EXTI_EMR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3306 | #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
| mbed_official | 126:549ba18ddd81 | 3307 | #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
| mbed_official | 126:549ba18ddd81 | 3308 | #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
| mbed_official | 126:549ba18ddd81 | 3309 | #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
| mbed_official | 126:549ba18ddd81 | 3310 | #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
| mbed_official | 126:549ba18ddd81 | 3311 | #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
| mbed_official | 126:549ba18ddd81 | 3312 | #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
| mbed_official | 126:549ba18ddd81 | 3313 | #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
| mbed_official | 126:549ba18ddd81 | 3314 | #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
| mbed_official | 126:549ba18ddd81 | 3315 | #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
| mbed_official | 126:549ba18ddd81 | 3316 | #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
| mbed_official | 126:549ba18ddd81 | 3317 | #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
| mbed_official | 126:549ba18ddd81 | 3318 | #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
| mbed_official | 126:549ba18ddd81 | 3319 | #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
| mbed_official | 126:549ba18ddd81 | 3320 | #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
| mbed_official | 126:549ba18ddd81 | 3321 | #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
| mbed_official | 126:549ba18ddd81 | 3322 | #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
| mbed_official | 126:549ba18ddd81 | 3323 | #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
| mbed_official | 126:549ba18ddd81 | 3324 | #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
| mbed_official | 126:549ba18ddd81 | 3325 | #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
| mbed_official | 126:549ba18ddd81 | 3326 | |
| mbed_official | 126:549ba18ddd81 | 3327 | /****************** Bit definition for EXTI_RTSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3328 | #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
| mbed_official | 126:549ba18ddd81 | 3329 | #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
| mbed_official | 126:549ba18ddd81 | 3330 | #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
| mbed_official | 126:549ba18ddd81 | 3331 | #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
| mbed_official | 126:549ba18ddd81 | 3332 | #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
| mbed_official | 126:549ba18ddd81 | 3333 | #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
| mbed_official | 126:549ba18ddd81 | 3334 | #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
| mbed_official | 126:549ba18ddd81 | 3335 | #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
| mbed_official | 126:549ba18ddd81 | 3336 | #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
| mbed_official | 126:549ba18ddd81 | 3337 | #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
| mbed_official | 126:549ba18ddd81 | 3338 | #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
| mbed_official | 126:549ba18ddd81 | 3339 | #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
| mbed_official | 126:549ba18ddd81 | 3340 | #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
| mbed_official | 126:549ba18ddd81 | 3341 | #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
| mbed_official | 126:549ba18ddd81 | 3342 | #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
| mbed_official | 126:549ba18ddd81 | 3343 | #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
| mbed_official | 126:549ba18ddd81 | 3344 | #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
| mbed_official | 126:549ba18ddd81 | 3345 | #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
| mbed_official | 126:549ba18ddd81 | 3346 | #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
| mbed_official | 126:549ba18ddd81 | 3347 | #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
| mbed_official | 126:549ba18ddd81 | 3348 | |
| mbed_official | 126:549ba18ddd81 | 3349 | /****************** Bit definition for EXTI_FTSR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3350 | #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
| mbed_official | 126:549ba18ddd81 | 3351 | #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
| mbed_official | 126:549ba18ddd81 | 3352 | #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
| mbed_official | 126:549ba18ddd81 | 3353 | #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
| mbed_official | 126:549ba18ddd81 | 3354 | #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
| mbed_official | 126:549ba18ddd81 | 3355 | #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
| mbed_official | 126:549ba18ddd81 | 3356 | #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
| mbed_official | 126:549ba18ddd81 | 3357 | #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
| mbed_official | 126:549ba18ddd81 | 3358 | #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
| mbed_official | 126:549ba18ddd81 | 3359 | #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
| mbed_official | 126:549ba18ddd81 | 3360 | #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
| mbed_official | 126:549ba18ddd81 | 3361 | #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
| mbed_official | 126:549ba18ddd81 | 3362 | #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
| mbed_official | 126:549ba18ddd81 | 3363 | #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
| mbed_official | 126:549ba18ddd81 | 3364 | #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
| mbed_official | 126:549ba18ddd81 | 3365 | #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
| mbed_official | 126:549ba18ddd81 | 3366 | #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
| mbed_official | 126:549ba18ddd81 | 3367 | #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
| mbed_official | 126:549ba18ddd81 | 3368 | #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
| mbed_official | 126:549ba18ddd81 | 3369 | #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
| mbed_official | 126:549ba18ddd81 | 3370 | |
| mbed_official | 126:549ba18ddd81 | 3371 | /****************** Bit definition for EXTI_SWIER register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3372 | #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
| mbed_official | 126:549ba18ddd81 | 3373 | #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
| mbed_official | 126:549ba18ddd81 | 3374 | #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
| mbed_official | 126:549ba18ddd81 | 3375 | #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
| mbed_official | 126:549ba18ddd81 | 3376 | #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
| mbed_official | 126:549ba18ddd81 | 3377 | #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
| mbed_official | 126:549ba18ddd81 | 3378 | #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
| mbed_official | 126:549ba18ddd81 | 3379 | #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
| mbed_official | 126:549ba18ddd81 | 3380 | #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
| mbed_official | 126:549ba18ddd81 | 3381 | #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
| mbed_official | 126:549ba18ddd81 | 3382 | #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
| mbed_official | 126:549ba18ddd81 | 3383 | #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
| mbed_official | 126:549ba18ddd81 | 3384 | #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
| mbed_official | 126:549ba18ddd81 | 3385 | #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
| mbed_official | 126:549ba18ddd81 | 3386 | #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
| mbed_official | 126:549ba18ddd81 | 3387 | #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
| mbed_official | 126:549ba18ddd81 | 3388 | #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
| mbed_official | 126:549ba18ddd81 | 3389 | #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
| mbed_official | 126:549ba18ddd81 | 3390 | #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
| mbed_official | 126:549ba18ddd81 | 3391 | #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
| mbed_official | 126:549ba18ddd81 | 3392 | |
| mbed_official | 126:549ba18ddd81 | 3393 | /******************* Bit definition for EXTI_PR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3394 | #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
| mbed_official | 126:549ba18ddd81 | 3395 | #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
| mbed_official | 126:549ba18ddd81 | 3396 | #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
| mbed_official | 126:549ba18ddd81 | 3397 | #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
| mbed_official | 126:549ba18ddd81 | 3398 | #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
| mbed_official | 126:549ba18ddd81 | 3399 | #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
| mbed_official | 126:549ba18ddd81 | 3400 | #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
| mbed_official | 126:549ba18ddd81 | 3401 | #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
| mbed_official | 126:549ba18ddd81 | 3402 | #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
| mbed_official | 126:549ba18ddd81 | 3403 | #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
| mbed_official | 126:549ba18ddd81 | 3404 | #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
| mbed_official | 126:549ba18ddd81 | 3405 | #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
| mbed_official | 126:549ba18ddd81 | 3406 | #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
| mbed_official | 126:549ba18ddd81 | 3407 | #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
| mbed_official | 126:549ba18ddd81 | 3408 | #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
| mbed_official | 126:549ba18ddd81 | 3409 | #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
| mbed_official | 126:549ba18ddd81 | 3410 | #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
| mbed_official | 126:549ba18ddd81 | 3411 | #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
| mbed_official | 126:549ba18ddd81 | 3412 | #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
| mbed_official | 126:549ba18ddd81 | 3413 | #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
| mbed_official | 126:549ba18ddd81 | 3414 | |
| mbed_official | 126:549ba18ddd81 | 3415 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 3416 | /* */ |
| mbed_official | 126:549ba18ddd81 | 3417 | /* DMA Controller */ |
| mbed_official | 126:549ba18ddd81 | 3418 | /* */ |
| mbed_official | 126:549ba18ddd81 | 3419 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 3420 | |
| mbed_official | 126:549ba18ddd81 | 3421 | /******************* Bit definition for DMA_ISR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3422 | #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3423 | #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3424 | #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3425 | #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3426 | #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3427 | #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3428 | #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3429 | #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3430 | #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3431 | #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3432 | #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3433 | #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3434 | #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3435 | #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3436 | #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3437 | #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3438 | #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3439 | #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3440 | #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3441 | #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3442 | #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3443 | #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3444 | #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3445 | #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3446 | #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
| mbed_official | 126:549ba18ddd81 | 3447 | #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
| mbed_official | 126:549ba18ddd81 | 3448 | #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
| mbed_official | 126:549ba18ddd81 | 3449 | #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
| mbed_official | 126:549ba18ddd81 | 3450 | |
| mbed_official | 126:549ba18ddd81 | 3451 | /******************* Bit definition for DMA_IFCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3452 | #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3453 | #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3454 | #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3455 | #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3456 | #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3457 | #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3458 | #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3459 | #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3460 | #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3461 | #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3462 | #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3463 | #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3464 | #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3465 | #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3466 | #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3467 | #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3468 | #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3469 | #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3470 | #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3471 | #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3472 | #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3473 | #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3474 | #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3475 | #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3476 | #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
| mbed_official | 126:549ba18ddd81 | 3477 | #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
| mbed_official | 126:549ba18ddd81 | 3478 | #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
| mbed_official | 126:549ba18ddd81 | 3479 | #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
| mbed_official | 126:549ba18ddd81 | 3480 | |
| mbed_official | 126:549ba18ddd81 | 3481 | /******************* Bit definition for DMA_CCR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3482 | #define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ |
| mbed_official | 126:549ba18ddd81 | 3483 | #define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3484 | #define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3485 | #define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3486 | #define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3487 | #define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3488 | #define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3489 | #define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3490 | |
| mbed_official | 126:549ba18ddd81 | 3491 | #define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3492 | #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3493 | #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3494 | |
| mbed_official | 126:549ba18ddd81 | 3495 | #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3496 | #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3497 | #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3498 | |
| mbed_official | 126:549ba18ddd81 | 3499 | #define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3500 | #define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3501 | #define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3502 | |
| mbed_official | 126:549ba18ddd81 | 3503 | #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
| mbed_official | 126:549ba18ddd81 | 3504 | |
| mbed_official | 126:549ba18ddd81 | 3505 | /******************* Bit definition for DMA_CCR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3506 | #define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ |
| mbed_official | 126:549ba18ddd81 | 3507 | #define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3508 | #define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3509 | #define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3510 | #define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3511 | #define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3512 | #define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3513 | #define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3514 | |
| mbed_official | 126:549ba18ddd81 | 3515 | #define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3516 | #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3517 | #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3518 | |
| mbed_official | 126:549ba18ddd81 | 3519 | #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3520 | #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3521 | #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3522 | |
| mbed_official | 126:549ba18ddd81 | 3523 | #define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3524 | #define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3525 | #define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3526 | |
| mbed_official | 126:549ba18ddd81 | 3527 | #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
| mbed_official | 126:549ba18ddd81 | 3528 | |
| mbed_official | 126:549ba18ddd81 | 3529 | /******************* Bit definition for DMA_CCR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3530 | #define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ |
| mbed_official | 126:549ba18ddd81 | 3531 | #define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3532 | #define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3533 | #define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3534 | #define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3535 | #define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3536 | #define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3537 | #define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3538 | |
| mbed_official | 126:549ba18ddd81 | 3539 | #define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3540 | #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3541 | #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3542 | |
| mbed_official | 126:549ba18ddd81 | 3543 | #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3544 | #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3545 | #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3546 | |
| mbed_official | 126:549ba18ddd81 | 3547 | #define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3548 | #define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3549 | #define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3550 | |
| mbed_official | 126:549ba18ddd81 | 3551 | #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
| mbed_official | 126:549ba18ddd81 | 3552 | |
| mbed_official | 126:549ba18ddd81 | 3553 | /*!<****************** Bit definition for DMA_CCR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3554 | #define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ |
| mbed_official | 126:549ba18ddd81 | 3555 | #define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3556 | #define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3557 | #define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3558 | #define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3559 | #define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3560 | #define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3561 | #define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3562 | |
| mbed_official | 126:549ba18ddd81 | 3563 | #define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3564 | #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3565 | #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3566 | |
| mbed_official | 126:549ba18ddd81 | 3567 | #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3568 | #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3569 | #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3570 | |
| mbed_official | 126:549ba18ddd81 | 3571 | #define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3572 | #define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3573 | #define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3574 | |
| mbed_official | 126:549ba18ddd81 | 3575 | #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
| mbed_official | 126:549ba18ddd81 | 3576 | |
| mbed_official | 126:549ba18ddd81 | 3577 | /****************** Bit definition for DMA_CCR5 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3578 | #define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ |
| mbed_official | 126:549ba18ddd81 | 3579 | #define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3580 | #define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3581 | #define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3582 | #define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3583 | #define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3584 | #define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3585 | #define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3586 | |
| mbed_official | 126:549ba18ddd81 | 3587 | #define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3588 | #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3589 | #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3590 | |
| mbed_official | 126:549ba18ddd81 | 3591 | #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3592 | #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3593 | #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3594 | |
| mbed_official | 126:549ba18ddd81 | 3595 | #define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3596 | #define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3597 | #define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3598 | |
| mbed_official | 126:549ba18ddd81 | 3599 | #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ |
| mbed_official | 126:549ba18ddd81 | 3600 | |
| mbed_official | 126:549ba18ddd81 | 3601 | /******************* Bit definition for DMA_CCR6 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3602 | #define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ |
| mbed_official | 126:549ba18ddd81 | 3603 | #define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3604 | #define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3605 | #define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3606 | #define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3607 | #define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3608 | #define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3609 | #define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3610 | |
| mbed_official | 126:549ba18ddd81 | 3611 | #define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3612 | #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3613 | #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3614 | |
| mbed_official | 126:549ba18ddd81 | 3615 | #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3616 | #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3617 | #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3618 | |
| mbed_official | 126:549ba18ddd81 | 3619 | #define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3620 | #define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3621 | #define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3622 | |
| mbed_official | 126:549ba18ddd81 | 3623 | #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
| mbed_official | 126:549ba18ddd81 | 3624 | |
| mbed_official | 126:549ba18ddd81 | 3625 | /******************* Bit definition for DMA_CCR7 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3626 | #define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ |
| mbed_official | 126:549ba18ddd81 | 3627 | #define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3628 | #define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3629 | #define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3630 | #define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
| mbed_official | 126:549ba18ddd81 | 3631 | #define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
| mbed_official | 126:549ba18ddd81 | 3632 | #define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3633 | #define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
| mbed_official | 126:549ba18ddd81 | 3634 | |
| mbed_official | 126:549ba18ddd81 | 3635 | #define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 126:549ba18ddd81 | 3636 | #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3637 | #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3638 | |
| mbed_official | 126:549ba18ddd81 | 3639 | #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 126:549ba18ddd81 | 3640 | #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3641 | #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3642 | |
| mbed_official | 126:549ba18ddd81 | 3643 | #define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
| mbed_official | 126:549ba18ddd81 | 3644 | #define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3645 | #define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3646 | |
| mbed_official | 126:549ba18ddd81 | 3647 | #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ |
| mbed_official | 126:549ba18ddd81 | 3648 | |
| mbed_official | 126:549ba18ddd81 | 3649 | /****************** Bit definition for DMA_CNDTR1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3650 | #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3651 | |
| mbed_official | 126:549ba18ddd81 | 3652 | /****************** Bit definition for DMA_CNDTR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3653 | #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3654 | |
| mbed_official | 126:549ba18ddd81 | 3655 | /****************** Bit definition for DMA_CNDTR3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3656 | #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3657 | |
| mbed_official | 126:549ba18ddd81 | 3658 | /****************** Bit definition for DMA_CNDTR4 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3659 | #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3660 | |
| mbed_official | 126:549ba18ddd81 | 3661 | /****************** Bit definition for DMA_CNDTR5 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3662 | #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3663 | |
| mbed_official | 126:549ba18ddd81 | 3664 | /****************** Bit definition for DMA_CNDTR6 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3665 | #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3666 | |
| mbed_official | 126:549ba18ddd81 | 3667 | /****************** Bit definition for DMA_CNDTR7 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 3668 | #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ |
| mbed_official | 126:549ba18ddd81 | 3669 | |
| mbed_official | 126:549ba18ddd81 | 3670 | /****************** Bit definition for DMA_CPAR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3671 | #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3672 | |
| mbed_official | 126:549ba18ddd81 | 3673 | /****************** Bit definition for DMA_CPAR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3674 | #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3675 | |
| mbed_official | 126:549ba18ddd81 | 3676 | /****************** Bit definition for DMA_CPAR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3677 | #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3678 | |
| mbed_official | 126:549ba18ddd81 | 3679 | |
| mbed_official | 126:549ba18ddd81 | 3680 | /****************** Bit definition for DMA_CPAR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3681 | #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3682 | |
| mbed_official | 126:549ba18ddd81 | 3683 | /****************** Bit definition for DMA_CPAR5 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3684 | #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3685 | |
| mbed_official | 126:549ba18ddd81 | 3686 | /****************** Bit definition for DMA_CPAR6 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3687 | #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3688 | |
| mbed_official | 126:549ba18ddd81 | 3689 | |
| mbed_official | 126:549ba18ddd81 | 3690 | /****************** Bit definition for DMA_CPAR7 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3691 | #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 126:549ba18ddd81 | 3692 | |
| mbed_official | 126:549ba18ddd81 | 3693 | /****************** Bit definition for DMA_CMAR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3694 | #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3695 | |
| mbed_official | 126:549ba18ddd81 | 3696 | /****************** Bit definition for DMA_CMAR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3697 | #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3698 | |
| mbed_official | 126:549ba18ddd81 | 3699 | /****************** Bit definition for DMA_CMAR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3700 | #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3701 | |
| mbed_official | 126:549ba18ddd81 | 3702 | |
| mbed_official | 126:549ba18ddd81 | 3703 | /****************** Bit definition for DMA_CMAR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3704 | #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3705 | |
| mbed_official | 126:549ba18ddd81 | 3706 | /****************** Bit definition for DMA_CMAR5 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3707 | #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3708 | |
| mbed_official | 126:549ba18ddd81 | 3709 | /****************** Bit definition for DMA_CMAR6 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3710 | #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3711 | |
| mbed_official | 126:549ba18ddd81 | 3712 | /****************** Bit definition for DMA_CMAR7 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3713 | #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 126:549ba18ddd81 | 3714 | |
| mbed_official | 126:549ba18ddd81 | 3715 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 3716 | /* */ |
| mbed_official | 126:549ba18ddd81 | 3717 | /* Analog to Digital Converter */ |
| mbed_official | 126:549ba18ddd81 | 3718 | /* */ |
| mbed_official | 126:549ba18ddd81 | 3719 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 3720 | |
| mbed_official | 126:549ba18ddd81 | 3721 | /******************** Bit definition for ADC_SR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3722 | #define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ |
| mbed_official | 126:549ba18ddd81 | 3723 | #define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ |
| mbed_official | 126:549ba18ddd81 | 3724 | #define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ |
| mbed_official | 126:549ba18ddd81 | 3725 | #define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ |
| mbed_official | 126:549ba18ddd81 | 3726 | #define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ |
| mbed_official | 126:549ba18ddd81 | 3727 | |
| mbed_official | 126:549ba18ddd81 | 3728 | /******************* Bit definition for ADC_CR1 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3729 | #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| mbed_official | 126:549ba18ddd81 | 3730 | #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3731 | #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3732 | #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3733 | #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3734 | #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3735 | |
| mbed_official | 126:549ba18ddd81 | 3736 | #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ |
| mbed_official | 126:549ba18ddd81 | 3737 | #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 3738 | #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ |
| mbed_official | 126:549ba18ddd81 | 3739 | #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ |
| mbed_official | 126:549ba18ddd81 | 3740 | #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ |
| mbed_official | 126:549ba18ddd81 | 3741 | #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ |
| mbed_official | 126:549ba18ddd81 | 3742 | #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ |
| mbed_official | 126:549ba18ddd81 | 3743 | #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ |
| mbed_official | 126:549ba18ddd81 | 3744 | |
| mbed_official | 126:549ba18ddd81 | 3745 | #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
| mbed_official | 126:549ba18ddd81 | 3746 | #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3747 | #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3748 | #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3749 | |
| mbed_official | 126:549ba18ddd81 | 3750 | #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ |
| mbed_official | 126:549ba18ddd81 | 3751 | #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3752 | #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3753 | #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3754 | #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3755 | |
| mbed_official | 126:549ba18ddd81 | 3756 | #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ |
| mbed_official | 126:549ba18ddd81 | 3757 | #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ |
| mbed_official | 126:549ba18ddd81 | 3758 | |
| mbed_official | 126:549ba18ddd81 | 3759 | |
| mbed_official | 126:549ba18ddd81 | 3760 | /******************* Bit definition for ADC_CR2 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3761 | #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ |
| mbed_official | 126:549ba18ddd81 | 3762 | #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ |
| mbed_official | 126:549ba18ddd81 | 3763 | #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ |
| mbed_official | 126:549ba18ddd81 | 3764 | #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ |
| mbed_official | 126:549ba18ddd81 | 3765 | #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ |
| mbed_official | 126:549ba18ddd81 | 3766 | #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ |
| mbed_official | 126:549ba18ddd81 | 3767 | |
| mbed_official | 126:549ba18ddd81 | 3768 | #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ |
| mbed_official | 126:549ba18ddd81 | 3769 | #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3770 | #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3771 | #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3772 | |
| mbed_official | 126:549ba18ddd81 | 3773 | #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ |
| mbed_official | 126:549ba18ddd81 | 3774 | |
| mbed_official | 126:549ba18ddd81 | 3775 | #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ |
| mbed_official | 126:549ba18ddd81 | 3776 | #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3777 | #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3778 | #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3779 | |
| mbed_official | 126:549ba18ddd81 | 3780 | #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ |
| mbed_official | 126:549ba18ddd81 | 3781 | #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ |
| mbed_official | 126:549ba18ddd81 | 3782 | #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ |
| mbed_official | 126:549ba18ddd81 | 3783 | #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ |
| mbed_official | 126:549ba18ddd81 | 3784 | |
| mbed_official | 126:549ba18ddd81 | 3785 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3786 | #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3787 | #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3788 | #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3789 | #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3790 | |
| mbed_official | 126:549ba18ddd81 | 3791 | #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3792 | #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3793 | #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3794 | #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3795 | |
| mbed_official | 126:549ba18ddd81 | 3796 | #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3797 | #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3798 | #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3799 | #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3800 | |
| mbed_official | 126:549ba18ddd81 | 3801 | #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3802 | #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3803 | #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3804 | #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3805 | |
| mbed_official | 126:549ba18ddd81 | 3806 | #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3807 | #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3808 | #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3809 | #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3810 | |
| mbed_official | 126:549ba18ddd81 | 3811 | #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3812 | #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3813 | #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3814 | #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3815 | |
| mbed_official | 126:549ba18ddd81 | 3816 | #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3817 | #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3818 | #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3819 | #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3820 | |
| mbed_official | 126:549ba18ddd81 | 3821 | #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3822 | #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3823 | #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3824 | #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3825 | |
| mbed_official | 126:549ba18ddd81 | 3826 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3827 | #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3828 | #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3829 | #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3830 | #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3831 | |
| mbed_official | 126:549ba18ddd81 | 3832 | #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3833 | #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3834 | #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3835 | #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3836 | |
| mbed_official | 126:549ba18ddd81 | 3837 | #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3838 | #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3839 | #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3840 | #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3841 | |
| mbed_official | 126:549ba18ddd81 | 3842 | #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3843 | #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3844 | #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3845 | #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3846 | |
| mbed_official | 126:549ba18ddd81 | 3847 | #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3848 | #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3849 | #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3850 | #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3851 | |
| mbed_official | 126:549ba18ddd81 | 3852 | #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3853 | #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3854 | #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3855 | #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3856 | |
| mbed_official | 126:549ba18ddd81 | 3857 | #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3858 | #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3859 | #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3860 | #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3861 | |
| mbed_official | 126:549ba18ddd81 | 3862 | #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3863 | #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3864 | #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3865 | #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3866 | |
| mbed_official | 126:549ba18ddd81 | 3867 | #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3868 | #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3869 | #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3870 | #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3871 | |
| mbed_official | 126:549ba18ddd81 | 3872 | #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ |
| mbed_official | 126:549ba18ddd81 | 3873 | #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3874 | #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3875 | #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3876 | |
| mbed_official | 126:549ba18ddd81 | 3877 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3878 | #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ |
| mbed_official | 126:549ba18ddd81 | 3879 | |
| mbed_official | 126:549ba18ddd81 | 3880 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3881 | #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ |
| mbed_official | 126:549ba18ddd81 | 3882 | |
| mbed_official | 126:549ba18ddd81 | 3883 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3884 | #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ |
| mbed_official | 126:549ba18ddd81 | 3885 | |
| mbed_official | 126:549ba18ddd81 | 3886 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3887 | #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ |
| mbed_official | 126:549ba18ddd81 | 3888 | |
| mbed_official | 126:549ba18ddd81 | 3889 | /******************* Bit definition for ADC_HTR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3890 | #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ |
| mbed_official | 126:549ba18ddd81 | 3891 | |
| mbed_official | 126:549ba18ddd81 | 3892 | /******************* Bit definition for ADC_LTR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 3893 | #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ |
| mbed_official | 126:549ba18ddd81 | 3894 | |
| mbed_official | 126:549ba18ddd81 | 3895 | /******************* Bit definition for ADC_SQR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3896 | #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3897 | #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3898 | #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3899 | #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3900 | #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3901 | #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3902 | |
| mbed_official | 126:549ba18ddd81 | 3903 | #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3904 | #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3905 | #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3906 | #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3907 | #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3908 | #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3909 | |
| mbed_official | 126:549ba18ddd81 | 3910 | #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3911 | #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3912 | #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3913 | #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3914 | #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3915 | #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3916 | |
| mbed_official | 126:549ba18ddd81 | 3917 | #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3918 | #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3919 | #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3920 | #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3921 | #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3922 | #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3923 | |
| mbed_official | 126:549ba18ddd81 | 3924 | #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ |
| mbed_official | 126:549ba18ddd81 | 3925 | #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3926 | #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3927 | #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3928 | #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3929 | |
| mbed_official | 126:549ba18ddd81 | 3930 | /******************* Bit definition for ADC_SQR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3931 | #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3932 | #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3933 | #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3934 | #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3935 | #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3936 | #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3937 | |
| mbed_official | 126:549ba18ddd81 | 3938 | #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3939 | #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3940 | #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3941 | #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3942 | #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3943 | #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3944 | |
| mbed_official | 126:549ba18ddd81 | 3945 | #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3946 | #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3947 | #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3948 | #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3949 | #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3950 | #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3951 | |
| mbed_official | 126:549ba18ddd81 | 3952 | #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3953 | #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3954 | #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3955 | #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3956 | #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3957 | #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3958 | |
| mbed_official | 126:549ba18ddd81 | 3959 | #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3960 | #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3961 | #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3962 | #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3963 | #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3964 | #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3965 | |
| mbed_official | 126:549ba18ddd81 | 3966 | #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3967 | #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3968 | #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3969 | #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3970 | #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3971 | #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3972 | |
| mbed_official | 126:549ba18ddd81 | 3973 | /******************* Bit definition for ADC_SQR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 3974 | #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3975 | #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3976 | #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3977 | #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3978 | #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3979 | #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3980 | |
| mbed_official | 126:549ba18ddd81 | 3981 | #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3982 | #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3983 | #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3984 | #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3985 | #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3986 | #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3987 | |
| mbed_official | 126:549ba18ddd81 | 3988 | #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3989 | #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3990 | #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3991 | #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3992 | #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 3993 | #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 3994 | |
| mbed_official | 126:549ba18ddd81 | 3995 | #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 3996 | #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 3997 | #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 3998 | #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 3999 | #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4000 | #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4001 | |
| mbed_official | 126:549ba18ddd81 | 4002 | #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 4003 | #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4004 | #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4005 | #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4006 | #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4007 | #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4008 | |
| mbed_official | 126:549ba18ddd81 | 4009 | #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ |
| mbed_official | 126:549ba18ddd81 | 4010 | #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4011 | #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4012 | #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4013 | #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4014 | #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4015 | |
| mbed_official | 126:549ba18ddd81 | 4016 | /******************* Bit definition for ADC_JSQR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4017 | #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ |
| mbed_official | 126:549ba18ddd81 | 4018 | #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4019 | #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4020 | #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4021 | #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4022 | #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4023 | |
| mbed_official | 126:549ba18ddd81 | 4024 | #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
| mbed_official | 126:549ba18ddd81 | 4025 | #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4026 | #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4027 | #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4028 | #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4029 | #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4030 | |
| mbed_official | 126:549ba18ddd81 | 4031 | #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
| mbed_official | 126:549ba18ddd81 | 4032 | #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4033 | #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4034 | #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4035 | #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4036 | #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4037 | |
| mbed_official | 126:549ba18ddd81 | 4038 | #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ |
| mbed_official | 126:549ba18ddd81 | 4039 | #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4040 | #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4041 | #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4042 | #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4043 | #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4044 | |
| mbed_official | 126:549ba18ddd81 | 4045 | #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ |
| mbed_official | 126:549ba18ddd81 | 4046 | #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4047 | #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4048 | |
| mbed_official | 126:549ba18ddd81 | 4049 | /******************* Bit definition for ADC_JDR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4050 | #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ |
| mbed_official | 126:549ba18ddd81 | 4051 | |
| mbed_official | 126:549ba18ddd81 | 4052 | /******************* Bit definition for ADC_JDR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4053 | #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ |
| mbed_official | 126:549ba18ddd81 | 4054 | |
| mbed_official | 126:549ba18ddd81 | 4055 | /******************* Bit definition for ADC_JDR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4056 | #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ |
| mbed_official | 126:549ba18ddd81 | 4057 | |
| mbed_official | 126:549ba18ddd81 | 4058 | /******************* Bit definition for ADC_JDR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4059 | #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ |
| mbed_official | 126:549ba18ddd81 | 4060 | |
| mbed_official | 126:549ba18ddd81 | 4061 | /******************** Bit definition for ADC_DR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4062 | #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ |
| mbed_official | 126:549ba18ddd81 | 4063 | #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ |
| mbed_official | 126:549ba18ddd81 | 4064 | |
| mbed_official | 126:549ba18ddd81 | 4065 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4066 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4067 | /* Digital to Analog Converter */ |
| mbed_official | 126:549ba18ddd81 | 4068 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4069 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4070 | |
| mbed_official | 126:549ba18ddd81 | 4071 | /******************** Bit definition for DAC_CR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4072 | #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ |
| mbed_official | 126:549ba18ddd81 | 4073 | #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ |
| mbed_official | 126:549ba18ddd81 | 4074 | #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ |
| mbed_official | 126:549ba18ddd81 | 4075 | |
| mbed_official | 126:549ba18ddd81 | 4076 | #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
| mbed_official | 126:549ba18ddd81 | 4077 | #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4078 | #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4079 | #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4080 | |
| mbed_official | 126:549ba18ddd81 | 4081 | #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| mbed_official | 126:549ba18ddd81 | 4082 | #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4083 | #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4084 | |
| mbed_official | 126:549ba18ddd81 | 4085 | #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| mbed_official | 126:549ba18ddd81 | 4086 | #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4087 | #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4088 | #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4089 | #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4090 | |
| mbed_official | 126:549ba18ddd81 | 4091 | #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ |
| mbed_official | 126:549ba18ddd81 | 4092 | #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ |
| mbed_official | 126:549ba18ddd81 | 4093 | #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ |
| mbed_official | 126:549ba18ddd81 | 4094 | #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ |
| mbed_official | 126:549ba18ddd81 | 4095 | |
| mbed_official | 126:549ba18ddd81 | 4096 | #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
| mbed_official | 126:549ba18ddd81 | 4097 | #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4098 | #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4099 | #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4100 | |
| mbed_official | 126:549ba18ddd81 | 4101 | #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| mbed_official | 126:549ba18ddd81 | 4102 | #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4103 | #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4104 | |
| mbed_official | 126:549ba18ddd81 | 4105 | #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| mbed_official | 126:549ba18ddd81 | 4106 | #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4107 | #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4108 | #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4109 | #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4110 | |
| mbed_official | 126:549ba18ddd81 | 4111 | #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ |
| mbed_official | 126:549ba18ddd81 | 4112 | |
| mbed_official | 126:549ba18ddd81 | 4113 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| mbed_official | 126:549ba18ddd81 | 4114 | #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4115 | #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4116 | #endif |
| mbed_official | 126:549ba18ddd81 | 4117 | |
| mbed_official | 126:549ba18ddd81 | 4118 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4119 | #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ |
| mbed_official | 126:549ba18ddd81 | 4120 | #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ |
| mbed_official | 126:549ba18ddd81 | 4121 | |
| mbed_official | 126:549ba18ddd81 | 4122 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4123 | #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4124 | |
| mbed_official | 126:549ba18ddd81 | 4125 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4126 | #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4127 | |
| mbed_official | 126:549ba18ddd81 | 4128 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4129 | #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4130 | |
| mbed_official | 126:549ba18ddd81 | 4131 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4132 | #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4133 | |
| mbed_official | 126:549ba18ddd81 | 4134 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4135 | #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4136 | |
| mbed_official | 126:549ba18ddd81 | 4137 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4138 | #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4139 | |
| mbed_official | 126:549ba18ddd81 | 4140 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4141 | #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4142 | #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4143 | |
| mbed_official | 126:549ba18ddd81 | 4144 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4145 | #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4146 | #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4147 | |
| mbed_official | 126:549ba18ddd81 | 4148 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4149 | #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4150 | #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ |
| mbed_official | 126:549ba18ddd81 | 4151 | |
| mbed_official | 126:549ba18ddd81 | 4152 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4153 | #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ |
| mbed_official | 126:549ba18ddd81 | 4154 | |
| mbed_official | 126:549ba18ddd81 | 4155 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4156 | #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ |
| mbed_official | 126:549ba18ddd81 | 4157 | |
| mbed_official | 126:549ba18ddd81 | 4158 | /******************** Bit definition for DAC_SR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4159 | #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ |
| mbed_official | 126:549ba18ddd81 | 4160 | #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ |
| mbed_official | 126:549ba18ddd81 | 4161 | |
| mbed_official | 126:549ba18ddd81 | 4162 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4163 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4164 | /* CEC */ |
| mbed_official | 126:549ba18ddd81 | 4165 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4166 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4167 | /******************** Bit definition for CEC_CFGR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4168 | #define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ |
| mbed_official | 126:549ba18ddd81 | 4169 | #define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 4170 | #define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ |
| mbed_official | 126:549ba18ddd81 | 4171 | #define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ |
| mbed_official | 126:549ba18ddd81 | 4172 | |
| mbed_official | 126:549ba18ddd81 | 4173 | /******************** Bit definition for CEC_OAR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4174 | #define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ |
| mbed_official | 126:549ba18ddd81 | 4175 | #define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4176 | #define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4177 | #define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4178 | #define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4179 | |
| mbed_official | 126:549ba18ddd81 | 4180 | /******************** Bit definition for CEC_PRES register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4181 | #define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ |
| mbed_official | 126:549ba18ddd81 | 4182 | |
| mbed_official | 126:549ba18ddd81 | 4183 | /******************** Bit definition for CEC_ESR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4184 | #define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ |
| mbed_official | 126:549ba18ddd81 | 4185 | #define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ |
| mbed_official | 126:549ba18ddd81 | 4186 | #define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ |
| mbed_official | 126:549ba18ddd81 | 4187 | #define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ |
| mbed_official | 126:549ba18ddd81 | 4188 | #define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ |
| mbed_official | 126:549ba18ddd81 | 4189 | #define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ |
| mbed_official | 126:549ba18ddd81 | 4190 | #define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ |
| mbed_official | 126:549ba18ddd81 | 4191 | |
| mbed_official | 126:549ba18ddd81 | 4192 | /******************** Bit definition for CEC_CSR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4193 | #define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ |
| mbed_official | 126:549ba18ddd81 | 4194 | #define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ |
| mbed_official | 126:549ba18ddd81 | 4195 | #define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ |
| mbed_official | 126:549ba18ddd81 | 4196 | #define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ |
| mbed_official | 126:549ba18ddd81 | 4197 | #define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ |
| mbed_official | 126:549ba18ddd81 | 4198 | #define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ |
| mbed_official | 126:549ba18ddd81 | 4199 | #define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ |
| mbed_official | 126:549ba18ddd81 | 4200 | #define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ |
| mbed_official | 126:549ba18ddd81 | 4201 | |
| mbed_official | 126:549ba18ddd81 | 4202 | /******************** Bit definition for CEC_TXD register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4203 | #define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ |
| mbed_official | 126:549ba18ddd81 | 4204 | |
| mbed_official | 126:549ba18ddd81 | 4205 | /******************** Bit definition for CEC_RXD register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4206 | #define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ |
| mbed_official | 126:549ba18ddd81 | 4207 | |
| mbed_official | 126:549ba18ddd81 | 4208 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4209 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4210 | /* TIM */ |
| mbed_official | 126:549ba18ddd81 | 4211 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4212 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4213 | |
| mbed_official | 126:549ba18ddd81 | 4214 | /******************* Bit definition for TIM_CR1 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4215 | #define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ |
| mbed_official | 126:549ba18ddd81 | 4216 | #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ |
| mbed_official | 126:549ba18ddd81 | 4217 | #define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ |
| mbed_official | 126:549ba18ddd81 | 4218 | #define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ |
| mbed_official | 126:549ba18ddd81 | 4219 | #define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ |
| mbed_official | 126:549ba18ddd81 | 4220 | |
| mbed_official | 126:549ba18ddd81 | 4221 | #define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ |
| mbed_official | 126:549ba18ddd81 | 4222 | #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4223 | #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4224 | |
| mbed_official | 126:549ba18ddd81 | 4225 | #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ |
| mbed_official | 126:549ba18ddd81 | 4226 | |
| mbed_official | 126:549ba18ddd81 | 4227 | #define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ |
| mbed_official | 126:549ba18ddd81 | 4228 | #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4229 | #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4230 | |
| mbed_official | 126:549ba18ddd81 | 4231 | /******************* Bit definition for TIM_CR2 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4232 | #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ |
| mbed_official | 126:549ba18ddd81 | 4233 | #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ |
| mbed_official | 126:549ba18ddd81 | 4234 | #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ |
| mbed_official | 126:549ba18ddd81 | 4235 | |
| mbed_official | 126:549ba18ddd81 | 4236 | #define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ |
| mbed_official | 126:549ba18ddd81 | 4237 | #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4238 | #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4239 | #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4240 | |
| mbed_official | 126:549ba18ddd81 | 4241 | #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ |
| mbed_official | 126:549ba18ddd81 | 4242 | #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ |
| mbed_official | 126:549ba18ddd81 | 4243 | #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ |
| mbed_official | 126:549ba18ddd81 | 4244 | #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ |
| mbed_official | 126:549ba18ddd81 | 4245 | #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ |
| mbed_official | 126:549ba18ddd81 | 4246 | #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ |
| mbed_official | 126:549ba18ddd81 | 4247 | #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ |
| mbed_official | 126:549ba18ddd81 | 4248 | #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ |
| mbed_official | 126:549ba18ddd81 | 4249 | |
| mbed_official | 126:549ba18ddd81 | 4250 | /******************* Bit definition for TIM_SMCR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4251 | #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ |
| mbed_official | 126:549ba18ddd81 | 4252 | #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4253 | #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4254 | #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4255 | |
| mbed_official | 126:549ba18ddd81 | 4256 | #define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ |
| mbed_official | 126:549ba18ddd81 | 4257 | #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4258 | #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4259 | #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4260 | |
| mbed_official | 126:549ba18ddd81 | 4261 | #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ |
| mbed_official | 126:549ba18ddd81 | 4262 | |
| mbed_official | 126:549ba18ddd81 | 4263 | #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ |
| mbed_official | 126:549ba18ddd81 | 4264 | #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4265 | #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4266 | #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4267 | #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4268 | |
| mbed_official | 126:549ba18ddd81 | 4269 | #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 4270 | #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4271 | #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4272 | |
| mbed_official | 126:549ba18ddd81 | 4273 | #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ |
| mbed_official | 126:549ba18ddd81 | 4274 | #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ |
| mbed_official | 126:549ba18ddd81 | 4275 | |
| mbed_official | 126:549ba18ddd81 | 4276 | /******************* Bit definition for TIM_DIER register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4277 | #define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4278 | #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4279 | #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4280 | #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4281 | #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4282 | #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4283 | #define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4284 | #define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 4285 | #define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4286 | #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4287 | #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4288 | #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4289 | #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4290 | #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4291 | #define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ |
| mbed_official | 126:549ba18ddd81 | 4292 | |
| mbed_official | 126:549ba18ddd81 | 4293 | /******************** Bit definition for TIM_SR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4294 | #define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4295 | #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4296 | #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4297 | #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4298 | #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4299 | #define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4300 | #define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4301 | #define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4302 | #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ |
| mbed_official | 126:549ba18ddd81 | 4303 | #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ |
| mbed_official | 126:549ba18ddd81 | 4304 | #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ |
| mbed_official | 126:549ba18ddd81 | 4305 | #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ |
| mbed_official | 126:549ba18ddd81 | 4306 | |
| mbed_official | 126:549ba18ddd81 | 4307 | /******************* Bit definition for TIM_EGR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4308 | #define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ |
| mbed_official | 126:549ba18ddd81 | 4309 | #define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ |
| mbed_official | 126:549ba18ddd81 | 4310 | #define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ |
| mbed_official | 126:549ba18ddd81 | 4311 | #define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ |
| mbed_official | 126:549ba18ddd81 | 4312 | #define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ |
| mbed_official | 126:549ba18ddd81 | 4313 | #define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ |
| mbed_official | 126:549ba18ddd81 | 4314 | #define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ |
| mbed_official | 126:549ba18ddd81 | 4315 | #define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ |
| mbed_official | 126:549ba18ddd81 | 4316 | |
| mbed_official | 126:549ba18ddd81 | 4317 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4318 | #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| mbed_official | 126:549ba18ddd81 | 4319 | #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4320 | #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4321 | |
| mbed_official | 126:549ba18ddd81 | 4322 | #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ |
| mbed_official | 126:549ba18ddd81 | 4323 | #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ |
| mbed_official | 126:549ba18ddd81 | 4324 | |
| mbed_official | 126:549ba18ddd81 | 4325 | #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ |
| mbed_official | 126:549ba18ddd81 | 4326 | #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4327 | #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4328 | #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4329 | |
| mbed_official | 126:549ba18ddd81 | 4330 | #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ |
| mbed_official | 126:549ba18ddd81 | 4331 | |
| mbed_official | 126:549ba18ddd81 | 4332 | #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| mbed_official | 126:549ba18ddd81 | 4333 | #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4334 | #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4335 | |
| mbed_official | 126:549ba18ddd81 | 4336 | #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ |
| mbed_official | 126:549ba18ddd81 | 4337 | #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ |
| mbed_official | 126:549ba18ddd81 | 4338 | |
| mbed_official | 126:549ba18ddd81 | 4339 | #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ |
| mbed_official | 126:549ba18ddd81 | 4340 | #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4341 | #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4342 | #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4343 | |
| mbed_official | 126:549ba18ddd81 | 4344 | #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ |
| mbed_official | 126:549ba18ddd81 | 4345 | |
| mbed_official | 126:549ba18ddd81 | 4346 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 4347 | |
| mbed_official | 126:549ba18ddd81 | 4348 | #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 4349 | #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4350 | #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4351 | |
| mbed_official | 126:549ba18ddd81 | 4352 | #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ |
| mbed_official | 126:549ba18ddd81 | 4353 | #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4354 | #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4355 | #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4356 | #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4357 | |
| mbed_official | 126:549ba18ddd81 | 4358 | #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 4359 | #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4360 | #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4361 | |
| mbed_official | 126:549ba18ddd81 | 4362 | #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ |
| mbed_official | 126:549ba18ddd81 | 4363 | #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4364 | #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4365 | #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4366 | #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4367 | |
| mbed_official | 126:549ba18ddd81 | 4368 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4369 | #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| mbed_official | 126:549ba18ddd81 | 4370 | #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4371 | #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4372 | |
| mbed_official | 126:549ba18ddd81 | 4373 | #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ |
| mbed_official | 126:549ba18ddd81 | 4374 | #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ |
| mbed_official | 126:549ba18ddd81 | 4375 | |
| mbed_official | 126:549ba18ddd81 | 4376 | #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ |
| mbed_official | 126:549ba18ddd81 | 4377 | #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4378 | #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4379 | #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4380 | |
| mbed_official | 126:549ba18ddd81 | 4381 | #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ |
| mbed_official | 126:549ba18ddd81 | 4382 | |
| mbed_official | 126:549ba18ddd81 | 4383 | #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| mbed_official | 126:549ba18ddd81 | 4384 | #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4385 | #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4386 | |
| mbed_official | 126:549ba18ddd81 | 4387 | #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ |
| mbed_official | 126:549ba18ddd81 | 4388 | #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ |
| mbed_official | 126:549ba18ddd81 | 4389 | |
| mbed_official | 126:549ba18ddd81 | 4390 | #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ |
| mbed_official | 126:549ba18ddd81 | 4391 | #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4392 | #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4393 | #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4394 | |
| mbed_official | 126:549ba18ddd81 | 4395 | #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ |
| mbed_official | 126:549ba18ddd81 | 4396 | |
| mbed_official | 126:549ba18ddd81 | 4397 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 4398 | |
| mbed_official | 126:549ba18ddd81 | 4399 | #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 4400 | #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4401 | #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4402 | |
| mbed_official | 126:549ba18ddd81 | 4403 | #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ |
| mbed_official | 126:549ba18ddd81 | 4404 | #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4405 | #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4406 | #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4407 | #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4408 | |
| mbed_official | 126:549ba18ddd81 | 4409 | #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| mbed_official | 126:549ba18ddd81 | 4410 | #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4411 | #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4412 | |
| mbed_official | 126:549ba18ddd81 | 4413 | #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ |
| mbed_official | 126:549ba18ddd81 | 4414 | #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4415 | #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4416 | #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4417 | #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4418 | |
| mbed_official | 126:549ba18ddd81 | 4419 | /******************* Bit definition for TIM_CCER register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4420 | #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ |
| mbed_official | 126:549ba18ddd81 | 4421 | #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4422 | #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ |
| mbed_official | 126:549ba18ddd81 | 4423 | #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4424 | #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ |
| mbed_official | 126:549ba18ddd81 | 4425 | #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4426 | #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ |
| mbed_official | 126:549ba18ddd81 | 4427 | #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4428 | #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ |
| mbed_official | 126:549ba18ddd81 | 4429 | #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4430 | #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ |
| mbed_official | 126:549ba18ddd81 | 4431 | #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4432 | #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ |
| mbed_official | 126:549ba18ddd81 | 4433 | #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4434 | #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4435 | |
| mbed_official | 126:549ba18ddd81 | 4436 | /******************* Bit definition for TIM_CNT register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4437 | #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ |
| mbed_official | 126:549ba18ddd81 | 4438 | |
| mbed_official | 126:549ba18ddd81 | 4439 | /******************* Bit definition for TIM_PSC register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4440 | #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ |
| mbed_official | 126:549ba18ddd81 | 4441 | |
| mbed_official | 126:549ba18ddd81 | 4442 | /******************* Bit definition for TIM_ARR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4443 | #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ |
| mbed_official | 126:549ba18ddd81 | 4444 | |
| mbed_official | 126:549ba18ddd81 | 4445 | /******************* Bit definition for TIM_RCR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4446 | #define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ |
| mbed_official | 126:549ba18ddd81 | 4447 | |
| mbed_official | 126:549ba18ddd81 | 4448 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4449 | #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ |
| mbed_official | 126:549ba18ddd81 | 4450 | |
| mbed_official | 126:549ba18ddd81 | 4451 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4452 | #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ |
| mbed_official | 126:549ba18ddd81 | 4453 | |
| mbed_official | 126:549ba18ddd81 | 4454 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4455 | #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ |
| mbed_official | 126:549ba18ddd81 | 4456 | |
| mbed_official | 126:549ba18ddd81 | 4457 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4458 | #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ |
| mbed_official | 126:549ba18ddd81 | 4459 | |
| mbed_official | 126:549ba18ddd81 | 4460 | /******************* Bit definition for TIM_BDTR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4461 | #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ |
| mbed_official | 126:549ba18ddd81 | 4462 | #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4463 | #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4464 | #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4465 | #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4466 | #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4467 | #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4468 | #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4469 | #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4470 | |
| mbed_official | 126:549ba18ddd81 | 4471 | #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ |
| mbed_official | 126:549ba18ddd81 | 4472 | #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4473 | #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4474 | |
| mbed_official | 126:549ba18ddd81 | 4475 | #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ |
| mbed_official | 126:549ba18ddd81 | 4476 | #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ |
| mbed_official | 126:549ba18ddd81 | 4477 | #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ |
| mbed_official | 126:549ba18ddd81 | 4478 | #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ |
| mbed_official | 126:549ba18ddd81 | 4479 | #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ |
| mbed_official | 126:549ba18ddd81 | 4480 | #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ |
| mbed_official | 126:549ba18ddd81 | 4481 | |
| mbed_official | 126:549ba18ddd81 | 4482 | /******************* Bit definition for TIM_DCR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4483 | #define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ |
| mbed_official | 126:549ba18ddd81 | 4484 | #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4485 | #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4486 | #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4487 | #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4488 | #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4489 | |
| mbed_official | 126:549ba18ddd81 | 4490 | #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ |
| mbed_official | 126:549ba18ddd81 | 4491 | #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4492 | #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4493 | #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4494 | #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4495 | #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4496 | |
| mbed_official | 126:549ba18ddd81 | 4497 | /******************* Bit definition for TIM_DMAR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4498 | #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ |
| mbed_official | 126:549ba18ddd81 | 4499 | |
| mbed_official | 126:549ba18ddd81 | 4500 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4501 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4502 | /* Real-Time Clock */ |
| mbed_official | 126:549ba18ddd81 | 4503 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4504 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4505 | |
| mbed_official | 126:549ba18ddd81 | 4506 | /******************* Bit definition for RTC_CRH register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4507 | #define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 4508 | #define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 4509 | #define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 4510 | |
| mbed_official | 126:549ba18ddd81 | 4511 | /******************* Bit definition for RTC_CRL register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4512 | #define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ |
| mbed_official | 126:549ba18ddd81 | 4513 | #define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ |
| mbed_official | 126:549ba18ddd81 | 4514 | #define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ |
| mbed_official | 126:549ba18ddd81 | 4515 | #define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ |
| mbed_official | 126:549ba18ddd81 | 4516 | #define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ |
| mbed_official | 126:549ba18ddd81 | 4517 | #define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ |
| mbed_official | 126:549ba18ddd81 | 4518 | |
| mbed_official | 126:549ba18ddd81 | 4519 | /******************* Bit definition for RTC_PRLH register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4520 | #define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ |
| mbed_official | 126:549ba18ddd81 | 4521 | |
| mbed_official | 126:549ba18ddd81 | 4522 | /******************* Bit definition for RTC_PRLL register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4523 | #define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ |
| mbed_official | 126:549ba18ddd81 | 4524 | |
| mbed_official | 126:549ba18ddd81 | 4525 | /******************* Bit definition for RTC_DIVH register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4526 | #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ |
| mbed_official | 126:549ba18ddd81 | 4527 | |
| mbed_official | 126:549ba18ddd81 | 4528 | /******************* Bit definition for RTC_DIVL register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4529 | #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ |
| mbed_official | 126:549ba18ddd81 | 4530 | |
| mbed_official | 126:549ba18ddd81 | 4531 | /******************* Bit definition for RTC_CNTH register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4532 | #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ |
| mbed_official | 126:549ba18ddd81 | 4533 | |
| mbed_official | 126:549ba18ddd81 | 4534 | /******************* Bit definition for RTC_CNTL register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4535 | #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ |
| mbed_official | 126:549ba18ddd81 | 4536 | |
| mbed_official | 126:549ba18ddd81 | 4537 | /******************* Bit definition for RTC_ALRH register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4538 | #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ |
| mbed_official | 126:549ba18ddd81 | 4539 | |
| mbed_official | 126:549ba18ddd81 | 4540 | /******************* Bit definition for RTC_ALRL register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4541 | #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ |
| mbed_official | 126:549ba18ddd81 | 4542 | |
| mbed_official | 126:549ba18ddd81 | 4543 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4544 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4545 | /* Independent WATCHDOG */ |
| mbed_official | 126:549ba18ddd81 | 4546 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4547 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4548 | |
| mbed_official | 126:549ba18ddd81 | 4549 | /******************* Bit definition for IWDG_KR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4550 | #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ |
| mbed_official | 126:549ba18ddd81 | 4551 | |
| mbed_official | 126:549ba18ddd81 | 4552 | /******************* Bit definition for IWDG_PR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4553 | #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ |
| mbed_official | 126:549ba18ddd81 | 4554 | #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4555 | #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4556 | #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4557 | |
| mbed_official | 126:549ba18ddd81 | 4558 | /******************* Bit definition for IWDG_RLR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4559 | #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ |
| mbed_official | 126:549ba18ddd81 | 4560 | |
| mbed_official | 126:549ba18ddd81 | 4561 | /******************* Bit definition for IWDG_SR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4562 | #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ |
| mbed_official | 126:549ba18ddd81 | 4563 | #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ |
| mbed_official | 126:549ba18ddd81 | 4564 | |
| mbed_official | 126:549ba18ddd81 | 4565 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4566 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4567 | /* Window WATCHDOG */ |
| mbed_official | 126:549ba18ddd81 | 4568 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4569 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4570 | |
| mbed_official | 126:549ba18ddd81 | 4571 | /******************* Bit definition for WWDG_CR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4572 | #define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| mbed_official | 126:549ba18ddd81 | 4573 | #define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4574 | #define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4575 | #define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4576 | #define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4577 | #define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4578 | #define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4579 | #define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4580 | |
| mbed_official | 126:549ba18ddd81 | 4581 | #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ |
| mbed_official | 126:549ba18ddd81 | 4582 | |
| mbed_official | 126:549ba18ddd81 | 4583 | /******************* Bit definition for WWDG_CFR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4584 | #define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ |
| mbed_official | 126:549ba18ddd81 | 4585 | #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4586 | #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4587 | #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4588 | #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4589 | #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4590 | #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4591 | #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4592 | |
| mbed_official | 126:549ba18ddd81 | 4593 | #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ |
| mbed_official | 126:549ba18ddd81 | 4594 | #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4595 | #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4596 | |
| mbed_official | 126:549ba18ddd81 | 4597 | #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 4598 | |
| mbed_official | 126:549ba18ddd81 | 4599 | /******************* Bit definition for WWDG_SR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 4600 | #define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ |
| mbed_official | 126:549ba18ddd81 | 4601 | |
| mbed_official | 126:549ba18ddd81 | 4602 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4603 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4604 | /* Flexible Static Memory Controller */ |
| mbed_official | 126:549ba18ddd81 | 4605 | /* */ |
| mbed_official | 126:549ba18ddd81 | 4606 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 4607 | |
| mbed_official | 126:549ba18ddd81 | 4608 | /****************** Bit definition for FSMC_BCR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4609 | #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4610 | #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4611 | |
| mbed_official | 126:549ba18ddd81 | 4612 | #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ |
| mbed_official | 126:549ba18ddd81 | 4613 | #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4614 | #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4615 | |
| mbed_official | 126:549ba18ddd81 | 4616 | #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 126:549ba18ddd81 | 4617 | #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4618 | #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4619 | |
| mbed_official | 126:549ba18ddd81 | 4620 | #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ |
| mbed_official | 126:549ba18ddd81 | 4621 | #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4622 | #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ |
| mbed_official | 126:549ba18ddd81 | 4623 | #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ |
| mbed_official | 126:549ba18ddd81 | 4624 | #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ |
| mbed_official | 126:549ba18ddd81 | 4625 | #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4626 | #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4627 | #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ |
| mbed_official | 126:549ba18ddd81 | 4628 | #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ |
| mbed_official | 126:549ba18ddd81 | 4629 | #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ |
| mbed_official | 126:549ba18ddd81 | 4630 | |
| mbed_official | 126:549ba18ddd81 | 4631 | /****************** Bit definition for FSMC_BCR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4632 | #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4633 | #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4634 | |
| mbed_official | 126:549ba18ddd81 | 4635 | #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ |
| mbed_official | 126:549ba18ddd81 | 4636 | #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4637 | #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4638 | |
| mbed_official | 126:549ba18ddd81 | 4639 | #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 126:549ba18ddd81 | 4640 | #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4641 | #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4642 | |
| mbed_official | 126:549ba18ddd81 | 4643 | #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ |
| mbed_official | 126:549ba18ddd81 | 4644 | #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4645 | #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ |
| mbed_official | 126:549ba18ddd81 | 4646 | #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ |
| mbed_official | 126:549ba18ddd81 | 4647 | #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ |
| mbed_official | 126:549ba18ddd81 | 4648 | #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4649 | #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4650 | #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ |
| mbed_official | 126:549ba18ddd81 | 4651 | #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ |
| mbed_official | 126:549ba18ddd81 | 4652 | #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ |
| mbed_official | 126:549ba18ddd81 | 4653 | |
| mbed_official | 126:549ba18ddd81 | 4654 | /****************** Bit definition for FSMC_BCR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4655 | #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4656 | #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4657 | |
| mbed_official | 126:549ba18ddd81 | 4658 | #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ |
| mbed_official | 126:549ba18ddd81 | 4659 | #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4660 | #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4661 | |
| mbed_official | 126:549ba18ddd81 | 4662 | #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 126:549ba18ddd81 | 4663 | #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4664 | #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4665 | |
| mbed_official | 126:549ba18ddd81 | 4666 | #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ |
| mbed_official | 126:549ba18ddd81 | 4667 | #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4668 | #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ |
| mbed_official | 126:549ba18ddd81 | 4669 | #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ |
| mbed_official | 126:549ba18ddd81 | 4670 | #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ |
| mbed_official | 126:549ba18ddd81 | 4671 | #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4672 | #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4673 | #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ |
| mbed_official | 126:549ba18ddd81 | 4674 | #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ |
| mbed_official | 126:549ba18ddd81 | 4675 | #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ |
| mbed_official | 126:549ba18ddd81 | 4676 | |
| mbed_official | 126:549ba18ddd81 | 4677 | /****************** Bit definition for FSMC_BCR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4678 | #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4679 | #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4680 | |
| mbed_official | 126:549ba18ddd81 | 4681 | #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ |
| mbed_official | 126:549ba18ddd81 | 4682 | #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4683 | #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4684 | |
| mbed_official | 126:549ba18ddd81 | 4685 | #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 126:549ba18ddd81 | 4686 | #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4687 | #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4688 | |
| mbed_official | 126:549ba18ddd81 | 4689 | #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ |
| mbed_official | 126:549ba18ddd81 | 4690 | #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4691 | #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ |
| mbed_official | 126:549ba18ddd81 | 4692 | #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ |
| mbed_official | 126:549ba18ddd81 | 4693 | #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ |
| mbed_official | 126:549ba18ddd81 | 4694 | #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4695 | #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ |
| mbed_official | 126:549ba18ddd81 | 4696 | #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ |
| mbed_official | 126:549ba18ddd81 | 4697 | #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ |
| mbed_official | 126:549ba18ddd81 | 4698 | #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ |
| mbed_official | 126:549ba18ddd81 | 4699 | |
| mbed_official | 126:549ba18ddd81 | 4700 | /****************** Bit definition for FSMC_BTR1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4701 | #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4702 | #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4703 | #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4704 | #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4705 | #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4706 | |
| mbed_official | 126:549ba18ddd81 | 4707 | #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4708 | #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4709 | #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4710 | #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4711 | #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4712 | |
| mbed_official | 126:549ba18ddd81 | 4713 | #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4714 | #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4715 | #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4716 | #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4717 | #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4718 | #define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4719 | #define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4720 | #define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4721 | #define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4722 | |
| mbed_official | 126:549ba18ddd81 | 4723 | #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4724 | #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4725 | #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4726 | #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4727 | #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4728 | |
| mbed_official | 126:549ba18ddd81 | 4729 | #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4730 | #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4731 | #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4732 | #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4733 | #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4734 | |
| mbed_official | 126:549ba18ddd81 | 4735 | #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4736 | #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4737 | #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4738 | #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4739 | #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4740 | |
| mbed_official | 126:549ba18ddd81 | 4741 | #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4742 | #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4743 | #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4744 | |
| mbed_official | 126:549ba18ddd81 | 4745 | /****************** Bit definition for FSMC_BTR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4746 | #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4747 | #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4748 | #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4749 | #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4750 | #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4751 | |
| mbed_official | 126:549ba18ddd81 | 4752 | #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4753 | #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4754 | #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4755 | #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4756 | #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4757 | |
| mbed_official | 126:549ba18ddd81 | 4758 | #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4759 | #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4760 | #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4761 | #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4762 | #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4763 | #define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4764 | #define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4765 | #define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4766 | #define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4767 | |
| mbed_official | 126:549ba18ddd81 | 4768 | #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4769 | #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4770 | #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4771 | #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4772 | #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4773 | |
| mbed_official | 126:549ba18ddd81 | 4774 | #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4775 | #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4776 | #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4777 | #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4778 | #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4779 | |
| mbed_official | 126:549ba18ddd81 | 4780 | #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4781 | #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4782 | #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4783 | #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4784 | #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4785 | |
| mbed_official | 126:549ba18ddd81 | 4786 | #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4787 | #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4788 | #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4789 | |
| mbed_official | 126:549ba18ddd81 | 4790 | /******************* Bit definition for FSMC_BTR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4791 | #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4792 | #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4793 | #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4794 | #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4795 | #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4796 | |
| mbed_official | 126:549ba18ddd81 | 4797 | #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4798 | #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4799 | #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4800 | #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4801 | #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4802 | |
| mbed_official | 126:549ba18ddd81 | 4803 | #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4804 | #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4805 | #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4806 | #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4807 | #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4808 | #define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4809 | #define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4810 | #define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4811 | #define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4812 | |
| mbed_official | 126:549ba18ddd81 | 4813 | #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4814 | #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4815 | #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4816 | #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4817 | #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4818 | |
| mbed_official | 126:549ba18ddd81 | 4819 | #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4820 | #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4821 | #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4822 | #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4823 | #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4824 | |
| mbed_official | 126:549ba18ddd81 | 4825 | #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4826 | #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4827 | #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4828 | #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4829 | #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4830 | |
| mbed_official | 126:549ba18ddd81 | 4831 | #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4832 | #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4833 | #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4834 | |
| mbed_official | 126:549ba18ddd81 | 4835 | /****************** Bit definition for FSMC_BTR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 4836 | #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4837 | #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4838 | #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4839 | #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4840 | #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4841 | |
| mbed_official | 126:549ba18ddd81 | 4842 | #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4843 | #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4844 | #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4845 | #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4846 | #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4847 | |
| mbed_official | 126:549ba18ddd81 | 4848 | #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4849 | #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4850 | #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4851 | #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4852 | #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4853 | #define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4854 | #define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4855 | #define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4856 | #define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4857 | |
| mbed_official | 126:549ba18ddd81 | 4858 | #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4859 | #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4860 | #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4861 | #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4862 | #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4863 | |
| mbed_official | 126:549ba18ddd81 | 4864 | #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4865 | #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4866 | #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4867 | #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4868 | #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4869 | |
| mbed_official | 126:549ba18ddd81 | 4870 | #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4871 | #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4872 | #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4873 | #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4874 | #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4875 | |
| mbed_official | 126:549ba18ddd81 | 4876 | #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4877 | #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4878 | #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4879 | |
| mbed_official | 126:549ba18ddd81 | 4880 | /****************** Bit definition for FSMC_BWTR1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4881 | #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4882 | #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4883 | #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4884 | #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4885 | #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4886 | |
| mbed_official | 126:549ba18ddd81 | 4887 | #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4888 | #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4889 | #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4890 | #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4891 | #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4892 | |
| mbed_official | 126:549ba18ddd81 | 4893 | #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4894 | #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4895 | #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4896 | #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4897 | #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4898 | #define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4899 | #define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4900 | #define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4901 | #define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4902 | |
| mbed_official | 126:549ba18ddd81 | 4903 | #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4904 | #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4905 | #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4906 | #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4907 | #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4908 | |
| mbed_official | 126:549ba18ddd81 | 4909 | #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4910 | #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4911 | #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4912 | #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4913 | #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4914 | |
| mbed_official | 126:549ba18ddd81 | 4915 | #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4916 | #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4917 | #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4918 | |
| mbed_official | 126:549ba18ddd81 | 4919 | /****************** Bit definition for FSMC_BWTR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4920 | #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4921 | #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4922 | #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4923 | #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4924 | #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4925 | |
| mbed_official | 126:549ba18ddd81 | 4926 | #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4927 | #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4928 | #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4929 | #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4930 | #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4931 | |
| mbed_official | 126:549ba18ddd81 | 4932 | #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4933 | #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4934 | #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4935 | #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4936 | #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4937 | #define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4938 | #define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4939 | #define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4940 | #define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4941 | |
| mbed_official | 126:549ba18ddd81 | 4942 | #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4943 | #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4944 | #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ |
| mbed_official | 126:549ba18ddd81 | 4945 | #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4946 | #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4947 | |
| mbed_official | 126:549ba18ddd81 | 4948 | #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4949 | #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4950 | #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4951 | #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4952 | #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4953 | |
| mbed_official | 126:549ba18ddd81 | 4954 | #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4955 | #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4956 | #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4957 | |
| mbed_official | 126:549ba18ddd81 | 4958 | /****************** Bit definition for FSMC_BWTR3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4959 | #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4960 | #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4961 | #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4962 | #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4963 | #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4964 | |
| mbed_official | 126:549ba18ddd81 | 4965 | #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4966 | #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4967 | #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4968 | #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4969 | #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4970 | |
| mbed_official | 126:549ba18ddd81 | 4971 | #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4972 | #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4973 | #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4974 | #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4975 | #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4976 | #define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 4977 | #define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 4978 | #define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 4979 | #define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 4980 | |
| mbed_official | 126:549ba18ddd81 | 4981 | #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 4982 | #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4983 | #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4984 | #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4985 | #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4986 | |
| mbed_official | 126:549ba18ddd81 | 4987 | #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 4988 | #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4989 | #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4990 | #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 4991 | #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 4992 | |
| mbed_official | 126:549ba18ddd81 | 4993 | #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 4994 | #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 4995 | #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 4996 | |
| mbed_official | 126:549ba18ddd81 | 4997 | /****************** Bit definition for FSMC_BWTR4 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 4998 | #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 4999 | #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5000 | #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5001 | #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5002 | #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5003 | |
| mbed_official | 126:549ba18ddd81 | 5004 | #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 5005 | #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5006 | #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5007 | #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5008 | #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5009 | |
| mbed_official | 126:549ba18ddd81 | 5010 | #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 126:549ba18ddd81 | 5011 | #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5012 | #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5013 | #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5014 | #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5015 | #define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5016 | #define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5017 | #define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5018 | #define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5019 | |
| mbed_official | 126:549ba18ddd81 | 5020 | #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 126:549ba18ddd81 | 5021 | #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5022 | #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5023 | #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5024 | #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5025 | |
| mbed_official | 126:549ba18ddd81 | 5026 | #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
| mbed_official | 126:549ba18ddd81 | 5027 | #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5028 | #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5029 | #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5030 | #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5031 | |
| mbed_official | 126:549ba18ddd81 | 5032 | #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 126:549ba18ddd81 | 5033 | #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5034 | #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5035 | |
| mbed_official | 126:549ba18ddd81 | 5036 | /****************** Bit definition for FSMC_PCR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5037 | #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5038 | #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5039 | #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ |
| mbed_official | 126:549ba18ddd81 | 5040 | |
| mbed_official | 126:549ba18ddd81 | 5041 | #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 126:549ba18ddd81 | 5042 | #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5043 | #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5044 | |
| mbed_official | 126:549ba18ddd81 | 5045 | #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5046 | |
| mbed_official | 126:549ba18ddd81 | 5047 | #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 126:549ba18ddd81 | 5048 | #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5049 | #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5050 | #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5051 | #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5052 | |
| mbed_official | 126:549ba18ddd81 | 5053 | #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 126:549ba18ddd81 | 5054 | #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5055 | #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5056 | #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5057 | #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5058 | |
| mbed_official | 126:549ba18ddd81 | 5059 | #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ |
| mbed_official | 126:549ba18ddd81 | 5060 | #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5061 | #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5062 | #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5063 | |
| mbed_official | 126:549ba18ddd81 | 5064 | /****************** Bit definition for FSMC_PCR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5065 | #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5066 | #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5067 | #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ |
| mbed_official | 126:549ba18ddd81 | 5068 | |
| mbed_official | 126:549ba18ddd81 | 5069 | #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 126:549ba18ddd81 | 5070 | #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5071 | #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5072 | |
| mbed_official | 126:549ba18ddd81 | 5073 | #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5074 | |
| mbed_official | 126:549ba18ddd81 | 5075 | #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 126:549ba18ddd81 | 5076 | #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5077 | #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5078 | #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5079 | #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5080 | |
| mbed_official | 126:549ba18ddd81 | 5081 | #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 126:549ba18ddd81 | 5082 | #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5083 | #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5084 | #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5085 | #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5086 | |
| mbed_official | 126:549ba18ddd81 | 5087 | #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ |
| mbed_official | 126:549ba18ddd81 | 5088 | #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5089 | #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5090 | #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5091 | |
| mbed_official | 126:549ba18ddd81 | 5092 | /****************** Bit definition for FSMC_PCR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5093 | #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5094 | #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5095 | #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ |
| mbed_official | 126:549ba18ddd81 | 5096 | |
| mbed_official | 126:549ba18ddd81 | 5097 | #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 126:549ba18ddd81 | 5098 | #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5099 | #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5100 | |
| mbed_official | 126:549ba18ddd81 | 5101 | #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5102 | |
| mbed_official | 126:549ba18ddd81 | 5103 | #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 126:549ba18ddd81 | 5104 | #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5105 | #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5106 | #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5107 | #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5108 | |
| mbed_official | 126:549ba18ddd81 | 5109 | #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 126:549ba18ddd81 | 5110 | #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5111 | #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5112 | #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5113 | #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5114 | |
| mbed_official | 126:549ba18ddd81 | 5115 | #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ |
| mbed_official | 126:549ba18ddd81 | 5116 | #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5117 | #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5118 | #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5119 | |
| mbed_official | 126:549ba18ddd81 | 5120 | /******************* Bit definition for FSMC_SR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5121 | #define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ |
| mbed_official | 126:549ba18ddd81 | 5122 | #define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ |
| mbed_official | 126:549ba18ddd81 | 5123 | #define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ |
| mbed_official | 126:549ba18ddd81 | 5124 | #define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5125 | #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5126 | #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5127 | #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ |
| mbed_official | 126:549ba18ddd81 | 5128 | |
| mbed_official | 126:549ba18ddd81 | 5129 | /******************* Bit definition for FSMC_SR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5130 | #define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ |
| mbed_official | 126:549ba18ddd81 | 5131 | #define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ |
| mbed_official | 126:549ba18ddd81 | 5132 | #define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ |
| mbed_official | 126:549ba18ddd81 | 5133 | #define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5134 | #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5135 | #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5136 | #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ |
| mbed_official | 126:549ba18ddd81 | 5137 | |
| mbed_official | 126:549ba18ddd81 | 5138 | /******************* Bit definition for FSMC_SR4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5139 | #define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ |
| mbed_official | 126:549ba18ddd81 | 5140 | #define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ |
| mbed_official | 126:549ba18ddd81 | 5141 | #define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ |
| mbed_official | 126:549ba18ddd81 | 5142 | #define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5143 | #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5144 | #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5145 | #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ |
| mbed_official | 126:549ba18ddd81 | 5146 | |
| mbed_official | 126:549ba18ddd81 | 5147 | /****************** Bit definition for FSMC_PMEM2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5148 | #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5149 | #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5150 | #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5151 | #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5152 | #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5153 | #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5154 | #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5155 | #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5156 | #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5157 | |
| mbed_official | 126:549ba18ddd81 | 5158 | #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5159 | #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5160 | #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5161 | #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5162 | #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5163 | #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5164 | #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5165 | #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5166 | #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5167 | |
| mbed_official | 126:549ba18ddd81 | 5168 | #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5169 | #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5170 | #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5171 | #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5172 | #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5173 | #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5174 | #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5175 | #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5176 | #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5177 | |
| mbed_official | 126:549ba18ddd81 | 5178 | #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5179 | #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5180 | #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5181 | #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5182 | #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5183 | #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5184 | #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5185 | #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5186 | #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5187 | |
| mbed_official | 126:549ba18ddd81 | 5188 | /****************** Bit definition for FSMC_PMEM3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5189 | #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5190 | #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5191 | #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5192 | #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5193 | #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5194 | #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5195 | #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5196 | #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5197 | #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5198 | |
| mbed_official | 126:549ba18ddd81 | 5199 | #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5200 | #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5201 | #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5202 | #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5203 | #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5204 | #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5205 | #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5206 | #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5207 | #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5208 | |
| mbed_official | 126:549ba18ddd81 | 5209 | #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5210 | #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5211 | #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5212 | #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5213 | #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5214 | #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5215 | #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5216 | #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5217 | #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5218 | |
| mbed_official | 126:549ba18ddd81 | 5219 | #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5220 | #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5221 | #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5222 | #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5223 | #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5224 | #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5225 | #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5226 | #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5227 | #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5228 | |
| mbed_official | 126:549ba18ddd81 | 5229 | /****************** Bit definition for FSMC_PMEM4 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5230 | #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5231 | #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5232 | #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5233 | #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5234 | #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5235 | #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5236 | #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5237 | #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5238 | #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5239 | |
| mbed_official | 126:549ba18ddd81 | 5240 | #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5241 | #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5242 | #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5243 | #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5244 | #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5245 | #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5246 | #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5247 | #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5248 | #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5249 | |
| mbed_official | 126:549ba18ddd81 | 5250 | #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5251 | #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5252 | #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5253 | #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5254 | #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5255 | #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5256 | #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5257 | #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5258 | #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5259 | |
| mbed_official | 126:549ba18ddd81 | 5260 | #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5261 | #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5262 | #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5263 | #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5264 | #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5265 | #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5266 | #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5267 | #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5268 | #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5269 | |
| mbed_official | 126:549ba18ddd81 | 5270 | /****************** Bit definition for FSMC_PATT2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5271 | #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5272 | #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5273 | #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5274 | #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5275 | #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5276 | #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5277 | #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5278 | #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5279 | #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5280 | |
| mbed_official | 126:549ba18ddd81 | 5281 | #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5282 | #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5283 | #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5284 | #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5285 | #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5286 | #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5287 | #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5288 | #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5289 | #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5290 | |
| mbed_official | 126:549ba18ddd81 | 5291 | #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5292 | #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5293 | #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5294 | #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5295 | #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5296 | #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5297 | #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5298 | #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5299 | #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5300 | |
| mbed_official | 126:549ba18ddd81 | 5301 | #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5302 | #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5303 | #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5304 | #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5305 | #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5306 | #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5307 | #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5308 | #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5309 | #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5310 | |
| mbed_official | 126:549ba18ddd81 | 5311 | /****************** Bit definition for FSMC_PATT3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5312 | #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5313 | #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5314 | #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5315 | #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5316 | #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5317 | #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5318 | #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5319 | #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5320 | #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5321 | |
| mbed_official | 126:549ba18ddd81 | 5322 | #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5323 | #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5324 | #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5325 | #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5326 | #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5327 | #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5328 | #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5329 | #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5330 | #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5331 | |
| mbed_official | 126:549ba18ddd81 | 5332 | #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5333 | #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5334 | #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5335 | #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5336 | #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5337 | #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5338 | #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5339 | #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5340 | #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5341 | |
| mbed_official | 126:549ba18ddd81 | 5342 | #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5343 | #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5344 | #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5345 | #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5346 | #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5347 | #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5348 | #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5349 | #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5350 | #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5351 | |
| mbed_official | 126:549ba18ddd81 | 5352 | /****************** Bit definition for FSMC_PATT4 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5353 | #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5354 | #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5355 | #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5356 | #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5357 | #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5358 | #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5359 | #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5360 | #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5361 | #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5362 | |
| mbed_official | 126:549ba18ddd81 | 5363 | #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5364 | #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5365 | #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5366 | #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5367 | #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5368 | #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5369 | #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5370 | #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5371 | #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5372 | |
| mbed_official | 126:549ba18ddd81 | 5373 | #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5374 | #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5375 | #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5376 | #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5377 | #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5378 | #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5379 | #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5380 | #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5381 | #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5382 | |
| mbed_official | 126:549ba18ddd81 | 5383 | #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5384 | #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5385 | #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5386 | #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5387 | #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5388 | #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5389 | #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5390 | #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5391 | #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5392 | |
| mbed_official | 126:549ba18ddd81 | 5393 | /****************** Bit definition for FSMC_PIO4 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5394 | #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ |
| mbed_official | 126:549ba18ddd81 | 5395 | #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5396 | #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5397 | #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5398 | #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5399 | #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5400 | #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5401 | #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5402 | #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5403 | |
| mbed_official | 126:549ba18ddd81 | 5404 | #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ |
| mbed_official | 126:549ba18ddd81 | 5405 | #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5406 | #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5407 | #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5408 | #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5409 | #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5410 | #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5411 | #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5412 | #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5413 | |
| mbed_official | 126:549ba18ddd81 | 5414 | #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ |
| mbed_official | 126:549ba18ddd81 | 5415 | #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5416 | #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5417 | #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5418 | #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5419 | #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5420 | #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5421 | #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5422 | #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5423 | |
| mbed_official | 126:549ba18ddd81 | 5424 | #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ |
| mbed_official | 126:549ba18ddd81 | 5425 | #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5426 | #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5427 | #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5428 | #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5429 | #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5430 | #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5431 | #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5432 | #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 5433 | |
| mbed_official | 126:549ba18ddd81 | 5434 | /****************** Bit definition for FSMC_ECCR2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5435 | #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ |
| mbed_official | 126:549ba18ddd81 | 5436 | |
| mbed_official | 126:549ba18ddd81 | 5437 | /****************** Bit definition for FSMC_ECCR3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5438 | #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ |
| mbed_official | 126:549ba18ddd81 | 5439 | |
| mbed_official | 126:549ba18ddd81 | 5440 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 5441 | /* */ |
| mbed_official | 126:549ba18ddd81 | 5442 | /* SD host Interface */ |
| mbed_official | 126:549ba18ddd81 | 5443 | /* */ |
| mbed_official | 126:549ba18ddd81 | 5444 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 5445 | |
| mbed_official | 126:549ba18ddd81 | 5446 | /****************** Bit definition for SDIO_POWER register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5447 | #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ |
| mbed_official | 126:549ba18ddd81 | 5448 | #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5449 | #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5450 | |
| mbed_official | 126:549ba18ddd81 | 5451 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5452 | #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ |
| mbed_official | 126:549ba18ddd81 | 5453 | #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5454 | #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ |
| mbed_official | 126:549ba18ddd81 | 5455 | #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5456 | |
| mbed_official | 126:549ba18ddd81 | 5457 | #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
| mbed_official | 126:549ba18ddd81 | 5458 | #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5459 | #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5460 | |
| mbed_official | 126:549ba18ddd81 | 5461 | #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ |
| mbed_official | 126:549ba18ddd81 | 5462 | #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ |
| mbed_official | 126:549ba18ddd81 | 5463 | |
| mbed_official | 126:549ba18ddd81 | 5464 | /******************* Bit definition for SDIO_ARG register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5465 | #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ |
| mbed_official | 126:549ba18ddd81 | 5466 | |
| mbed_official | 126:549ba18ddd81 | 5467 | /******************* Bit definition for SDIO_CMD register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5468 | #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ |
| mbed_official | 126:549ba18ddd81 | 5469 | |
| mbed_official | 126:549ba18ddd81 | 5470 | #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ |
| mbed_official | 126:549ba18ddd81 | 5471 | #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5472 | #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5473 | |
| mbed_official | 126:549ba18ddd81 | 5474 | #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ |
| mbed_official | 126:549ba18ddd81 | 5475 | #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
| mbed_official | 126:549ba18ddd81 | 5476 | #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ |
| mbed_official | 126:549ba18ddd81 | 5477 | #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ |
| mbed_official | 126:549ba18ddd81 | 5478 | #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ |
| mbed_official | 126:549ba18ddd81 | 5479 | #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5480 | #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ |
| mbed_official | 126:549ba18ddd81 | 5481 | |
| mbed_official | 126:549ba18ddd81 | 5482 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5483 | #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ |
| mbed_official | 126:549ba18ddd81 | 5484 | |
| mbed_official | 126:549ba18ddd81 | 5485 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5486 | #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
| mbed_official | 126:549ba18ddd81 | 5487 | |
| mbed_official | 126:549ba18ddd81 | 5488 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5489 | #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
| mbed_official | 126:549ba18ddd81 | 5490 | |
| mbed_official | 126:549ba18ddd81 | 5491 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5492 | #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
| mbed_official | 126:549ba18ddd81 | 5493 | |
| mbed_official | 126:549ba18ddd81 | 5494 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5495 | #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
| mbed_official | 126:549ba18ddd81 | 5496 | |
| mbed_official | 126:549ba18ddd81 | 5497 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5498 | #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
| mbed_official | 126:549ba18ddd81 | 5499 | |
| mbed_official | 126:549ba18ddd81 | 5500 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5501 | #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ |
| mbed_official | 126:549ba18ddd81 | 5502 | |
| mbed_official | 126:549ba18ddd81 | 5503 | /****************** Bit definition for SDIO_DLEN register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5504 | #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ |
| mbed_official | 126:549ba18ddd81 | 5505 | |
| mbed_official | 126:549ba18ddd81 | 5506 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5507 | #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ |
| mbed_official | 126:549ba18ddd81 | 5508 | #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ |
| mbed_official | 126:549ba18ddd81 | 5509 | #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ |
| mbed_official | 126:549ba18ddd81 | 5510 | #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ |
| mbed_official | 126:549ba18ddd81 | 5511 | |
| mbed_official | 126:549ba18ddd81 | 5512 | #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ |
| mbed_official | 126:549ba18ddd81 | 5513 | #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5514 | #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5515 | #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5516 | #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5517 | |
| mbed_official | 126:549ba18ddd81 | 5518 | #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ |
| mbed_official | 126:549ba18ddd81 | 5519 | #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ |
| mbed_official | 126:549ba18ddd81 | 5520 | #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ |
| mbed_official | 126:549ba18ddd81 | 5521 | #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ |
| mbed_official | 126:549ba18ddd81 | 5522 | |
| mbed_official | 126:549ba18ddd81 | 5523 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5524 | #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ |
| mbed_official | 126:549ba18ddd81 | 5525 | |
| mbed_official | 126:549ba18ddd81 | 5526 | /****************** Bit definition for SDIO_STA register ********************/ |
| mbed_official | 126:549ba18ddd81 | 5527 | #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ |
| mbed_official | 126:549ba18ddd81 | 5528 | #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ |
| mbed_official | 126:549ba18ddd81 | 5529 | #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ |
| mbed_official | 126:549ba18ddd81 | 5530 | #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ |
| mbed_official | 126:549ba18ddd81 | 5531 | #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ |
| mbed_official | 126:549ba18ddd81 | 5532 | #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ |
| mbed_official | 126:549ba18ddd81 | 5533 | #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ |
| mbed_official | 126:549ba18ddd81 | 5534 | #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ |
| mbed_official | 126:549ba18ddd81 | 5535 | #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ |
| mbed_official | 126:549ba18ddd81 | 5536 | #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ |
| mbed_official | 126:549ba18ddd81 | 5537 | #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ |
| mbed_official | 126:549ba18ddd81 | 5538 | #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ |
| mbed_official | 126:549ba18ddd81 | 5539 | #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ |
| mbed_official | 126:549ba18ddd81 | 5540 | #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ |
| mbed_official | 126:549ba18ddd81 | 5541 | #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
| mbed_official | 126:549ba18ddd81 | 5542 | #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
| mbed_official | 126:549ba18ddd81 | 5543 | #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ |
| mbed_official | 126:549ba18ddd81 | 5544 | #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ |
| mbed_official | 126:549ba18ddd81 | 5545 | #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ |
| mbed_official | 126:549ba18ddd81 | 5546 | #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ |
| mbed_official | 126:549ba18ddd81 | 5547 | #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ |
| mbed_official | 126:549ba18ddd81 | 5548 | #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ |
| mbed_official | 126:549ba18ddd81 | 5549 | #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ |
| mbed_official | 126:549ba18ddd81 | 5550 | #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ |
| mbed_official | 126:549ba18ddd81 | 5551 | |
| mbed_official | 126:549ba18ddd81 | 5552 | /******************* Bit definition for SDIO_ICR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5553 | #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5554 | #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5555 | #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5556 | #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5557 | #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5558 | #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5559 | #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5560 | #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5561 | #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5562 | #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5563 | #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5564 | #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5565 | #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ |
| mbed_official | 126:549ba18ddd81 | 5566 | |
| mbed_official | 126:549ba18ddd81 | 5567 | /****************** Bit definition for SDIO_MASK register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5568 | #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5569 | #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5570 | #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5571 | #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5572 | #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5573 | #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5574 | #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5575 | #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5576 | #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5577 | #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5578 | #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5579 | #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5580 | #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5581 | #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ |
| mbed_official | 126:549ba18ddd81 | 5582 | #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5583 | #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5584 | #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5585 | #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5586 | #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5587 | #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5588 | #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5589 | #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5590 | #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5591 | #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 5592 | |
| mbed_official | 126:549ba18ddd81 | 5593 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5594 | #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ |
| mbed_official | 126:549ba18ddd81 | 5595 | |
| mbed_official | 126:549ba18ddd81 | 5596 | /****************** Bit definition for SDIO_FIFO register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5597 | #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ |
| mbed_official | 126:549ba18ddd81 | 5598 | |
| mbed_official | 126:549ba18ddd81 | 5599 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 5600 | /* */ |
| mbed_official | 126:549ba18ddd81 | 5601 | /* USB Device FS */ |
| mbed_official | 126:549ba18ddd81 | 5602 | /* */ |
| mbed_official | 126:549ba18ddd81 | 5603 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 5604 | |
| mbed_official | 126:549ba18ddd81 | 5605 | /*!< Endpoint-specific registers */ |
| mbed_official | 126:549ba18ddd81 | 5606 | /******************* Bit definition for USB_EP0R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5607 | #define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5608 | |
| mbed_official | 126:549ba18ddd81 | 5609 | #define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5610 | #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5611 | #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5612 | |
| mbed_official | 126:549ba18ddd81 | 5613 | #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5614 | #define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5615 | #define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5616 | |
| mbed_official | 126:549ba18ddd81 | 5617 | #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5618 | #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5619 | #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5620 | |
| mbed_official | 126:549ba18ddd81 | 5621 | #define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5622 | |
| mbed_official | 126:549ba18ddd81 | 5623 | #define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5624 | #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5625 | #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5626 | |
| mbed_official | 126:549ba18ddd81 | 5627 | #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5628 | #define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5629 | |
| mbed_official | 126:549ba18ddd81 | 5630 | /******************* Bit definition for USB_EP1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5631 | #define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5632 | |
| mbed_official | 126:549ba18ddd81 | 5633 | #define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5634 | #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5635 | #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5636 | |
| mbed_official | 126:549ba18ddd81 | 5637 | #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5638 | #define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5639 | #define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5640 | |
| mbed_official | 126:549ba18ddd81 | 5641 | #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5642 | #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5643 | #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5644 | |
| mbed_official | 126:549ba18ddd81 | 5645 | #define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5646 | |
| mbed_official | 126:549ba18ddd81 | 5647 | #define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5648 | #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5649 | #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5650 | |
| mbed_official | 126:549ba18ddd81 | 5651 | #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5652 | #define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5653 | |
| mbed_official | 126:549ba18ddd81 | 5654 | /******************* Bit definition for USB_EP2R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5655 | #define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5656 | |
| mbed_official | 126:549ba18ddd81 | 5657 | #define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5658 | #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5659 | #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5660 | |
| mbed_official | 126:549ba18ddd81 | 5661 | #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5662 | #define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5663 | #define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5664 | |
| mbed_official | 126:549ba18ddd81 | 5665 | #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5666 | #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5667 | #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5668 | |
| mbed_official | 126:549ba18ddd81 | 5669 | #define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5670 | |
| mbed_official | 126:549ba18ddd81 | 5671 | #define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5672 | #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5673 | #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5674 | |
| mbed_official | 126:549ba18ddd81 | 5675 | #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5676 | #define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5677 | |
| mbed_official | 126:549ba18ddd81 | 5678 | /******************* Bit definition for USB_EP3R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5679 | #define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5680 | |
| mbed_official | 126:549ba18ddd81 | 5681 | #define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5682 | #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5683 | #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5684 | |
| mbed_official | 126:549ba18ddd81 | 5685 | #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5686 | #define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5687 | #define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5688 | |
| mbed_official | 126:549ba18ddd81 | 5689 | #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5690 | #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5691 | #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5692 | |
| mbed_official | 126:549ba18ddd81 | 5693 | #define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5694 | |
| mbed_official | 126:549ba18ddd81 | 5695 | #define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5696 | #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5697 | #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5698 | |
| mbed_official | 126:549ba18ddd81 | 5699 | #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5700 | #define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5701 | |
| mbed_official | 126:549ba18ddd81 | 5702 | /******************* Bit definition for USB_EP4R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5703 | #define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5704 | |
| mbed_official | 126:549ba18ddd81 | 5705 | #define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5706 | #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5707 | #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5708 | |
| mbed_official | 126:549ba18ddd81 | 5709 | #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5710 | #define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5711 | #define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5712 | |
| mbed_official | 126:549ba18ddd81 | 5713 | #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5714 | #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5715 | #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5716 | |
| mbed_official | 126:549ba18ddd81 | 5717 | #define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5718 | |
| mbed_official | 126:549ba18ddd81 | 5719 | #define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5720 | #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5721 | #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5722 | |
| mbed_official | 126:549ba18ddd81 | 5723 | #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5724 | #define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5725 | |
| mbed_official | 126:549ba18ddd81 | 5726 | /******************* Bit definition for USB_EP5R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5727 | #define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5728 | |
| mbed_official | 126:549ba18ddd81 | 5729 | #define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5730 | #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5731 | #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5732 | |
| mbed_official | 126:549ba18ddd81 | 5733 | #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5734 | #define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5735 | #define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5736 | |
| mbed_official | 126:549ba18ddd81 | 5737 | #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5738 | #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5739 | #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5740 | |
| mbed_official | 126:549ba18ddd81 | 5741 | #define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5742 | |
| mbed_official | 126:549ba18ddd81 | 5743 | #define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5744 | #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5745 | #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5746 | |
| mbed_official | 126:549ba18ddd81 | 5747 | #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5748 | #define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5749 | |
| mbed_official | 126:549ba18ddd81 | 5750 | /******************* Bit definition for USB_EP6R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5751 | #define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5752 | |
| mbed_official | 126:549ba18ddd81 | 5753 | #define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5754 | #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5755 | #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5756 | |
| mbed_official | 126:549ba18ddd81 | 5757 | #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5758 | #define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5759 | #define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5760 | |
| mbed_official | 126:549ba18ddd81 | 5761 | #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5762 | #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5763 | #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5764 | |
| mbed_official | 126:549ba18ddd81 | 5765 | #define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5766 | |
| mbed_official | 126:549ba18ddd81 | 5767 | #define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5768 | #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5769 | #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5770 | |
| mbed_official | 126:549ba18ddd81 | 5771 | #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5772 | #define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5773 | |
| mbed_official | 126:549ba18ddd81 | 5774 | /******************* Bit definition for USB_EP7R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5775 | #define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ |
| mbed_official | 126:549ba18ddd81 | 5776 | |
| mbed_official | 126:549ba18ddd81 | 5777 | #define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5778 | #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5779 | #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5780 | |
| mbed_official | 126:549ba18ddd81 | 5781 | #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ |
| mbed_official | 126:549ba18ddd81 | 5782 | #define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ |
| mbed_official | 126:549ba18ddd81 | 5783 | #define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ |
| mbed_official | 126:549ba18ddd81 | 5784 | |
| mbed_official | 126:549ba18ddd81 | 5785 | #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| mbed_official | 126:549ba18ddd81 | 5786 | #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5787 | #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5788 | |
| mbed_official | 126:549ba18ddd81 | 5789 | #define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ |
| mbed_official | 126:549ba18ddd81 | 5790 | |
| mbed_official | 126:549ba18ddd81 | 5791 | #define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| mbed_official | 126:549ba18ddd81 | 5792 | #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5793 | #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5794 | |
| mbed_official | 126:549ba18ddd81 | 5795 | #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ |
| mbed_official | 126:549ba18ddd81 | 5796 | #define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ |
| mbed_official | 126:549ba18ddd81 | 5797 | |
| mbed_official | 126:549ba18ddd81 | 5798 | /*!< Common registers */ |
| mbed_official | 126:549ba18ddd81 | 5799 | /******************* Bit definition for USB_CNTR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5800 | #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ |
| mbed_official | 126:549ba18ddd81 | 5801 | #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ |
| mbed_official | 126:549ba18ddd81 | 5802 | #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ |
| mbed_official | 126:549ba18ddd81 | 5803 | #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ |
| mbed_official | 126:549ba18ddd81 | 5804 | #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ |
| mbed_official | 126:549ba18ddd81 | 5805 | #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5806 | #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5807 | #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5808 | #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5809 | #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5810 | #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5811 | #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5812 | #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ |
| mbed_official | 126:549ba18ddd81 | 5813 | |
| mbed_official | 126:549ba18ddd81 | 5814 | /******************* Bit definition for USB_ISTR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5815 | #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ |
| mbed_official | 126:549ba18ddd81 | 5816 | #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ |
| mbed_official | 126:549ba18ddd81 | 5817 | #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ |
| mbed_official | 126:549ba18ddd81 | 5818 | #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ |
| mbed_official | 126:549ba18ddd81 | 5819 | #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ |
| mbed_official | 126:549ba18ddd81 | 5820 | #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ |
| mbed_official | 126:549ba18ddd81 | 5821 | #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ |
| mbed_official | 126:549ba18ddd81 | 5822 | #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ |
| mbed_official | 126:549ba18ddd81 | 5823 | #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ |
| mbed_official | 126:549ba18ddd81 | 5824 | #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ |
| mbed_official | 126:549ba18ddd81 | 5825 | |
| mbed_official | 126:549ba18ddd81 | 5826 | /******************* Bit definition for USB_FNR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 5827 | #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ |
| mbed_official | 126:549ba18ddd81 | 5828 | #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ |
| mbed_official | 126:549ba18ddd81 | 5829 | #define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ |
| mbed_official | 126:549ba18ddd81 | 5830 | #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ |
| mbed_official | 126:549ba18ddd81 | 5831 | #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ |
| mbed_official | 126:549ba18ddd81 | 5832 | |
| mbed_official | 126:549ba18ddd81 | 5833 | /****************** Bit definition for USB_DADDR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 5834 | #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ |
| mbed_official | 126:549ba18ddd81 | 5835 | #define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5836 | #define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5837 | #define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5838 | #define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5839 | #define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5840 | #define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 5841 | #define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 5842 | |
| mbed_official | 126:549ba18ddd81 | 5843 | #define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ |
| mbed_official | 126:549ba18ddd81 | 5844 | |
| mbed_official | 126:549ba18ddd81 | 5845 | /****************** Bit definition for USB_BTABLE register ******************/ |
| mbed_official | 126:549ba18ddd81 | 5846 | #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ |
| mbed_official | 126:549ba18ddd81 | 5847 | |
| mbed_official | 126:549ba18ddd81 | 5848 | /*!< Buffer descriptor table */ |
| mbed_official | 126:549ba18ddd81 | 5849 | /***************** Bit definition for USB_ADDR0_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5850 | #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ |
| mbed_official | 126:549ba18ddd81 | 5851 | |
| mbed_official | 126:549ba18ddd81 | 5852 | /***************** Bit definition for USB_ADDR1_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5853 | #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ |
| mbed_official | 126:549ba18ddd81 | 5854 | |
| mbed_official | 126:549ba18ddd81 | 5855 | /***************** Bit definition for USB_ADDR2_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5856 | #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ |
| mbed_official | 126:549ba18ddd81 | 5857 | |
| mbed_official | 126:549ba18ddd81 | 5858 | /***************** Bit definition for USB_ADDR3_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5859 | #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ |
| mbed_official | 126:549ba18ddd81 | 5860 | |
| mbed_official | 126:549ba18ddd81 | 5861 | /***************** Bit definition for USB_ADDR4_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5862 | #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ |
| mbed_official | 126:549ba18ddd81 | 5863 | |
| mbed_official | 126:549ba18ddd81 | 5864 | /***************** Bit definition for USB_ADDR5_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5865 | #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ |
| mbed_official | 126:549ba18ddd81 | 5866 | |
| mbed_official | 126:549ba18ddd81 | 5867 | /***************** Bit definition for USB_ADDR6_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5868 | #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ |
| mbed_official | 126:549ba18ddd81 | 5869 | |
| mbed_official | 126:549ba18ddd81 | 5870 | /***************** Bit definition for USB_ADDR7_TX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5871 | #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ |
| mbed_official | 126:549ba18ddd81 | 5872 | |
| mbed_official | 126:549ba18ddd81 | 5873 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 5874 | |
| mbed_official | 126:549ba18ddd81 | 5875 | /***************** Bit definition for USB_COUNT0_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5876 | #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ |
| mbed_official | 126:549ba18ddd81 | 5877 | |
| mbed_official | 126:549ba18ddd81 | 5878 | /***************** Bit definition for USB_COUNT1_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5879 | #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ |
| mbed_official | 126:549ba18ddd81 | 5880 | |
| mbed_official | 126:549ba18ddd81 | 5881 | /***************** Bit definition for USB_COUNT2_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5882 | #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ |
| mbed_official | 126:549ba18ddd81 | 5883 | |
| mbed_official | 126:549ba18ddd81 | 5884 | /***************** Bit definition for USB_COUNT3_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5885 | #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ |
| mbed_official | 126:549ba18ddd81 | 5886 | |
| mbed_official | 126:549ba18ddd81 | 5887 | /***************** Bit definition for USB_COUNT4_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5888 | #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ |
| mbed_official | 126:549ba18ddd81 | 5889 | |
| mbed_official | 126:549ba18ddd81 | 5890 | /***************** Bit definition for USB_COUNT5_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5891 | #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ |
| mbed_official | 126:549ba18ddd81 | 5892 | |
| mbed_official | 126:549ba18ddd81 | 5893 | /***************** Bit definition for USB_COUNT6_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5894 | #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ |
| mbed_official | 126:549ba18ddd81 | 5895 | |
| mbed_official | 126:549ba18ddd81 | 5896 | /***************** Bit definition for USB_COUNT7_TX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5897 | #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ |
| mbed_official | 126:549ba18ddd81 | 5898 | |
| mbed_official | 126:549ba18ddd81 | 5899 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 5900 | |
| mbed_official | 126:549ba18ddd81 | 5901 | /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5902 | #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5903 | |
| mbed_official | 126:549ba18ddd81 | 5904 | /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5905 | #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5906 | |
| mbed_official | 126:549ba18ddd81 | 5907 | /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5908 | #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5909 | |
| mbed_official | 126:549ba18ddd81 | 5910 | /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5911 | #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5912 | |
| mbed_official | 126:549ba18ddd81 | 5913 | /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5914 | #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5915 | |
| mbed_official | 126:549ba18ddd81 | 5916 | /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5917 | #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5918 | |
| mbed_official | 126:549ba18ddd81 | 5919 | /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5920 | #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5921 | |
| mbed_official | 126:549ba18ddd81 | 5922 | /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5923 | #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5924 | |
| mbed_official | 126:549ba18ddd81 | 5925 | /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5926 | #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5927 | |
| mbed_official | 126:549ba18ddd81 | 5928 | /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5929 | #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5930 | |
| mbed_official | 126:549ba18ddd81 | 5931 | /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5932 | #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5933 | |
| mbed_official | 126:549ba18ddd81 | 5934 | /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5935 | #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5936 | |
| mbed_official | 126:549ba18ddd81 | 5937 | /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5938 | #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5939 | |
| mbed_official | 126:549ba18ddd81 | 5940 | /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5941 | #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5942 | |
| mbed_official | 126:549ba18ddd81 | 5943 | /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5944 | #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ |
| mbed_official | 126:549ba18ddd81 | 5945 | |
| mbed_official | 126:549ba18ddd81 | 5946 | /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 5947 | #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ |
| mbed_official | 126:549ba18ddd81 | 5948 | |
| mbed_official | 126:549ba18ddd81 | 5949 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 5950 | |
| mbed_official | 126:549ba18ddd81 | 5951 | /***************** Bit definition for USB_ADDR0_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5952 | #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ |
| mbed_official | 126:549ba18ddd81 | 5953 | |
| mbed_official | 126:549ba18ddd81 | 5954 | /***************** Bit definition for USB_ADDR1_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5955 | #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ |
| mbed_official | 126:549ba18ddd81 | 5956 | |
| mbed_official | 126:549ba18ddd81 | 5957 | /***************** Bit definition for USB_ADDR2_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5958 | #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ |
| mbed_official | 126:549ba18ddd81 | 5959 | |
| mbed_official | 126:549ba18ddd81 | 5960 | /***************** Bit definition for USB_ADDR3_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5961 | #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ |
| mbed_official | 126:549ba18ddd81 | 5962 | |
| mbed_official | 126:549ba18ddd81 | 5963 | /***************** Bit definition for USB_ADDR4_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5964 | #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ |
| mbed_official | 126:549ba18ddd81 | 5965 | |
| mbed_official | 126:549ba18ddd81 | 5966 | /***************** Bit definition for USB_ADDR5_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5967 | #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ |
| mbed_official | 126:549ba18ddd81 | 5968 | |
| mbed_official | 126:549ba18ddd81 | 5969 | /***************** Bit definition for USB_ADDR6_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5970 | #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ |
| mbed_official | 126:549ba18ddd81 | 5971 | |
| mbed_official | 126:549ba18ddd81 | 5972 | /***************** Bit definition for USB_ADDR7_RX register *****************/ |
| mbed_official | 126:549ba18ddd81 | 5973 | #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ |
| mbed_official | 126:549ba18ddd81 | 5974 | |
| mbed_official | 126:549ba18ddd81 | 5975 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 5976 | |
| mbed_official | 126:549ba18ddd81 | 5977 | /***************** Bit definition for USB_COUNT0_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5978 | #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 5979 | |
| mbed_official | 126:549ba18ddd81 | 5980 | #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 5981 | #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5982 | #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5983 | #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5984 | #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5985 | #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5986 | |
| mbed_official | 126:549ba18ddd81 | 5987 | #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 5988 | |
| mbed_official | 126:549ba18ddd81 | 5989 | /***************** Bit definition for USB_COUNT1_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 5990 | #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 5991 | |
| mbed_official | 126:549ba18ddd81 | 5992 | #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 5993 | #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 5994 | #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 5995 | #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 5996 | #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 5997 | #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 5998 | |
| mbed_official | 126:549ba18ddd81 | 5999 | #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6000 | |
| mbed_official | 126:549ba18ddd81 | 6001 | /***************** Bit definition for USB_COUNT2_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6002 | #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 6003 | |
| mbed_official | 126:549ba18ddd81 | 6004 | #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 6005 | #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6006 | #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6007 | #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6008 | #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6009 | #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6010 | |
| mbed_official | 126:549ba18ddd81 | 6011 | #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6012 | |
| mbed_official | 126:549ba18ddd81 | 6013 | /***************** Bit definition for USB_COUNT3_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6014 | #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 6015 | |
| mbed_official | 126:549ba18ddd81 | 6016 | #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 6017 | #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6018 | #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6019 | #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6020 | #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6021 | #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6022 | |
| mbed_official | 126:549ba18ddd81 | 6023 | #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6024 | |
| mbed_official | 126:549ba18ddd81 | 6025 | /***************** Bit definition for USB_COUNT4_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6026 | #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 6027 | |
| mbed_official | 126:549ba18ddd81 | 6028 | #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 6029 | #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6030 | #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6031 | #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6032 | #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6033 | #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6034 | |
| mbed_official | 126:549ba18ddd81 | 6035 | #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6036 | |
| mbed_official | 126:549ba18ddd81 | 6037 | /***************** Bit definition for USB_COUNT5_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6038 | #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 6039 | |
| mbed_official | 126:549ba18ddd81 | 6040 | #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 6041 | #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6042 | #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6043 | #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6044 | #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6045 | #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6046 | |
| mbed_official | 126:549ba18ddd81 | 6047 | #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6048 | |
| mbed_official | 126:549ba18ddd81 | 6049 | /***************** Bit definition for USB_COUNT6_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6050 | #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 6051 | |
| mbed_official | 126:549ba18ddd81 | 6052 | #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 6053 | #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6054 | #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6055 | #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6056 | #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6057 | #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6058 | |
| mbed_official | 126:549ba18ddd81 | 6059 | #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6060 | |
| mbed_official | 126:549ba18ddd81 | 6061 | /***************** Bit definition for USB_COUNT7_RX register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6062 | #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ |
| mbed_official | 126:549ba18ddd81 | 6063 | |
| mbed_official | 126:549ba18ddd81 | 6064 | #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| mbed_official | 126:549ba18ddd81 | 6065 | #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6066 | #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6067 | #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6068 | #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6069 | #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6070 | |
| mbed_official | 126:549ba18ddd81 | 6071 | #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ |
| mbed_official | 126:549ba18ddd81 | 6072 | |
| mbed_official | 126:549ba18ddd81 | 6073 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 6074 | |
| mbed_official | 126:549ba18ddd81 | 6075 | /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6076 | #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6077 | |
| mbed_official | 126:549ba18ddd81 | 6078 | #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6079 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6080 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6081 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6082 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6083 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6084 | |
| mbed_official | 126:549ba18ddd81 | 6085 | #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6086 | |
| mbed_official | 126:549ba18ddd81 | 6087 | /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6088 | #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6089 | |
| mbed_official | 126:549ba18ddd81 | 6090 | #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6091 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6092 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6093 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6094 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6095 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6096 | |
| mbed_official | 126:549ba18ddd81 | 6097 | #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6098 | |
| mbed_official | 126:549ba18ddd81 | 6099 | /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6100 | #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6101 | |
| mbed_official | 126:549ba18ddd81 | 6102 | #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6103 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6104 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6105 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6106 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6107 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6108 | |
| mbed_official | 126:549ba18ddd81 | 6109 | #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6110 | |
| mbed_official | 126:549ba18ddd81 | 6111 | /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6112 | #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6113 | |
| mbed_official | 126:549ba18ddd81 | 6114 | #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6115 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6116 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6117 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6118 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6119 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6120 | |
| mbed_official | 126:549ba18ddd81 | 6121 | #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6122 | |
| mbed_official | 126:549ba18ddd81 | 6123 | /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6124 | #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6125 | |
| mbed_official | 126:549ba18ddd81 | 6126 | #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6127 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6128 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6129 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6130 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6131 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6132 | |
| mbed_official | 126:549ba18ddd81 | 6133 | #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6134 | |
| mbed_official | 126:549ba18ddd81 | 6135 | /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6136 | #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6137 | |
| mbed_official | 126:549ba18ddd81 | 6138 | #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6139 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6140 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6141 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6142 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6143 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6144 | |
| mbed_official | 126:549ba18ddd81 | 6145 | #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6146 | |
| mbed_official | 126:549ba18ddd81 | 6147 | /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6148 | #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6149 | |
| mbed_official | 126:549ba18ddd81 | 6150 | #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6151 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6152 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6153 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6154 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6155 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6156 | |
| mbed_official | 126:549ba18ddd81 | 6157 | #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6158 | |
| mbed_official | 126:549ba18ddd81 | 6159 | /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6160 | #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6161 | |
| mbed_official | 126:549ba18ddd81 | 6162 | #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6163 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6164 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6165 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6166 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6167 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6168 | |
| mbed_official | 126:549ba18ddd81 | 6169 | #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6170 | |
| mbed_official | 126:549ba18ddd81 | 6171 | /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6172 | #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6173 | |
| mbed_official | 126:549ba18ddd81 | 6174 | #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6175 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6176 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6177 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6178 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6179 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6180 | |
| mbed_official | 126:549ba18ddd81 | 6181 | #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6182 | |
| mbed_official | 126:549ba18ddd81 | 6183 | /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6184 | #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6185 | |
| mbed_official | 126:549ba18ddd81 | 6186 | #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6187 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6188 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6189 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6190 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6191 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6192 | |
| mbed_official | 126:549ba18ddd81 | 6193 | #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6194 | |
| mbed_official | 126:549ba18ddd81 | 6195 | /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6196 | #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6197 | |
| mbed_official | 126:549ba18ddd81 | 6198 | #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6199 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6200 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6201 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6202 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6203 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6204 | |
| mbed_official | 126:549ba18ddd81 | 6205 | #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6206 | |
| mbed_official | 126:549ba18ddd81 | 6207 | /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6208 | #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6209 | |
| mbed_official | 126:549ba18ddd81 | 6210 | #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6211 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6212 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6213 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6214 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6215 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6216 | |
| mbed_official | 126:549ba18ddd81 | 6217 | #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6218 | |
| mbed_official | 126:549ba18ddd81 | 6219 | /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6220 | #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6221 | |
| mbed_official | 126:549ba18ddd81 | 6222 | #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6223 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6224 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6225 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6226 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6227 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6228 | |
| mbed_official | 126:549ba18ddd81 | 6229 | #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6230 | |
| mbed_official | 126:549ba18ddd81 | 6231 | /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
| mbed_official | 126:549ba18ddd81 | 6232 | #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6233 | |
| mbed_official | 126:549ba18ddd81 | 6234 | #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6235 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6236 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6237 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6238 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6239 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6240 | |
| mbed_official | 126:549ba18ddd81 | 6241 | #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6242 | |
| mbed_official | 126:549ba18ddd81 | 6243 | /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6244 | #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| mbed_official | 126:549ba18ddd81 | 6245 | |
| mbed_official | 126:549ba18ddd81 | 6246 | #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| mbed_official | 126:549ba18ddd81 | 6247 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6248 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6249 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6250 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6251 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6252 | |
| mbed_official | 126:549ba18ddd81 | 6253 | #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| mbed_official | 126:549ba18ddd81 | 6254 | |
| mbed_official | 126:549ba18ddd81 | 6255 | /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
| mbed_official | 126:549ba18ddd81 | 6256 | #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| mbed_official | 126:549ba18ddd81 | 6257 | |
| mbed_official | 126:549ba18ddd81 | 6258 | #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| mbed_official | 126:549ba18ddd81 | 6259 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6260 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6261 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6262 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6263 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6264 | |
| mbed_official | 126:549ba18ddd81 | 6265 | #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| mbed_official | 126:549ba18ddd81 | 6266 | |
| mbed_official | 126:549ba18ddd81 | 6267 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 6268 | /* */ |
| mbed_official | 126:549ba18ddd81 | 6269 | /* Controller Area Network */ |
| mbed_official | 126:549ba18ddd81 | 6270 | /* */ |
| mbed_official | 126:549ba18ddd81 | 6271 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 6272 | |
| mbed_official | 126:549ba18ddd81 | 6273 | /*!< CAN control and status registers */ |
| mbed_official | 126:549ba18ddd81 | 6274 | /******************* Bit definition for CAN_MCR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 6275 | #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ |
| mbed_official | 126:549ba18ddd81 | 6276 | #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ |
| mbed_official | 126:549ba18ddd81 | 6277 | #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ |
| mbed_official | 126:549ba18ddd81 | 6278 | #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ |
| mbed_official | 126:549ba18ddd81 | 6279 | #define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ |
| mbed_official | 126:549ba18ddd81 | 6280 | #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ |
| mbed_official | 126:549ba18ddd81 | 6281 | #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ |
| mbed_official | 126:549ba18ddd81 | 6282 | #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ |
| mbed_official | 126:549ba18ddd81 | 6283 | #define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ |
| mbed_official | 126:549ba18ddd81 | 6284 | |
| mbed_official | 126:549ba18ddd81 | 6285 | /******************* Bit definition for CAN_MSR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 6286 | #define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ |
| mbed_official | 126:549ba18ddd81 | 6287 | #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ |
| mbed_official | 126:549ba18ddd81 | 6288 | #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 6289 | #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 6290 | #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ |
| mbed_official | 126:549ba18ddd81 | 6291 | #define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ |
| mbed_official | 126:549ba18ddd81 | 6292 | #define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ |
| mbed_official | 126:549ba18ddd81 | 6293 | #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ |
| mbed_official | 126:549ba18ddd81 | 6294 | #define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ |
| mbed_official | 126:549ba18ddd81 | 6295 | |
| mbed_official | 126:549ba18ddd81 | 6296 | /******************* Bit definition for CAN_TSR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 6297 | #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ |
| mbed_official | 126:549ba18ddd81 | 6298 | #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ |
| mbed_official | 126:549ba18ddd81 | 6299 | #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ |
| mbed_official | 126:549ba18ddd81 | 6300 | #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ |
| mbed_official | 126:549ba18ddd81 | 6301 | #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ |
| mbed_official | 126:549ba18ddd81 | 6302 | #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ |
| mbed_official | 126:549ba18ddd81 | 6303 | #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ |
| mbed_official | 126:549ba18ddd81 | 6304 | #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ |
| mbed_official | 126:549ba18ddd81 | 6305 | #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ |
| mbed_official | 126:549ba18ddd81 | 6306 | #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ |
| mbed_official | 126:549ba18ddd81 | 6307 | #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ |
| mbed_official | 126:549ba18ddd81 | 6308 | #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ |
| mbed_official | 126:549ba18ddd81 | 6309 | #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ |
| mbed_official | 126:549ba18ddd81 | 6310 | #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ |
| mbed_official | 126:549ba18ddd81 | 6311 | #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ |
| mbed_official | 126:549ba18ddd81 | 6312 | #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ |
| mbed_official | 126:549ba18ddd81 | 6313 | |
| mbed_official | 126:549ba18ddd81 | 6314 | #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 6315 | #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ |
| mbed_official | 126:549ba18ddd81 | 6316 | #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ |
| mbed_official | 126:549ba18ddd81 | 6317 | #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ |
| mbed_official | 126:549ba18ddd81 | 6318 | |
| mbed_official | 126:549ba18ddd81 | 6319 | #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ |
| mbed_official | 126:549ba18ddd81 | 6320 | #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ |
| mbed_official | 126:549ba18ddd81 | 6321 | #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ |
| mbed_official | 126:549ba18ddd81 | 6322 | #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ |
| mbed_official | 126:549ba18ddd81 | 6323 | |
| mbed_official | 126:549ba18ddd81 | 6324 | /******************* Bit definition for CAN_RF0R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6325 | #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ |
| mbed_official | 126:549ba18ddd81 | 6326 | #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ |
| mbed_official | 126:549ba18ddd81 | 6327 | #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ |
| mbed_official | 126:549ba18ddd81 | 6328 | #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ |
| mbed_official | 126:549ba18ddd81 | 6329 | |
| mbed_official | 126:549ba18ddd81 | 6330 | /******************* Bit definition for CAN_RF1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6331 | #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ |
| mbed_official | 126:549ba18ddd81 | 6332 | #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ |
| mbed_official | 126:549ba18ddd81 | 6333 | #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ |
| mbed_official | 126:549ba18ddd81 | 6334 | #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ |
| mbed_official | 126:549ba18ddd81 | 6335 | |
| mbed_official | 126:549ba18ddd81 | 6336 | /******************** Bit definition for CAN_IER register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6337 | #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6338 | #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6339 | #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6340 | #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6341 | #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6342 | #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6343 | #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6344 | #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6345 | #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6346 | #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6347 | #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6348 | #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6349 | #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6350 | #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 6351 | |
| mbed_official | 126:549ba18ddd81 | 6352 | /******************** Bit definition for CAN_ESR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6353 | #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ |
| mbed_official | 126:549ba18ddd81 | 6354 | #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ |
| mbed_official | 126:549ba18ddd81 | 6355 | #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ |
| mbed_official | 126:549ba18ddd81 | 6356 | |
| mbed_official | 126:549ba18ddd81 | 6357 | #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ |
| mbed_official | 126:549ba18ddd81 | 6358 | #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6359 | #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6360 | #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6361 | |
| mbed_official | 126:549ba18ddd81 | 6362 | #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ |
| mbed_official | 126:549ba18ddd81 | 6363 | #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ |
| mbed_official | 126:549ba18ddd81 | 6364 | |
| mbed_official | 126:549ba18ddd81 | 6365 | /******************* Bit definition for CAN_BTR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 6366 | #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ |
| mbed_official | 126:549ba18ddd81 | 6367 | #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ |
| mbed_official | 126:549ba18ddd81 | 6368 | #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ |
| mbed_official | 126:549ba18ddd81 | 6369 | #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ |
| mbed_official | 126:549ba18ddd81 | 6370 | #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ |
| mbed_official | 126:549ba18ddd81 | 6371 | #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ |
| mbed_official | 126:549ba18ddd81 | 6372 | |
| mbed_official | 126:549ba18ddd81 | 6373 | /*!< Mailbox registers */ |
| mbed_official | 126:549ba18ddd81 | 6374 | /****************** Bit definition for CAN_TI0R register ********************/ |
| mbed_official | 126:549ba18ddd81 | 6375 | #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ |
| mbed_official | 126:549ba18ddd81 | 6376 | #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
| mbed_official | 126:549ba18ddd81 | 6377 | #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
| mbed_official | 126:549ba18ddd81 | 6378 | #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6379 | #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6380 | |
| mbed_official | 126:549ba18ddd81 | 6381 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6382 | #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
| mbed_official | 126:549ba18ddd81 | 6383 | #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ |
| mbed_official | 126:549ba18ddd81 | 6384 | #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
| mbed_official | 126:549ba18ddd81 | 6385 | |
| mbed_official | 126:549ba18ddd81 | 6386 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6387 | #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
| mbed_official | 126:549ba18ddd81 | 6388 | #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
| mbed_official | 126:549ba18ddd81 | 6389 | #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
| mbed_official | 126:549ba18ddd81 | 6390 | #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
| mbed_official | 126:549ba18ddd81 | 6391 | |
| mbed_official | 126:549ba18ddd81 | 6392 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6393 | #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
| mbed_official | 126:549ba18ddd81 | 6394 | #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
| mbed_official | 126:549ba18ddd81 | 6395 | #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
| mbed_official | 126:549ba18ddd81 | 6396 | #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
| mbed_official | 126:549ba18ddd81 | 6397 | |
| mbed_official | 126:549ba18ddd81 | 6398 | /******************* Bit definition for CAN_TI1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6399 | #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ |
| mbed_official | 126:549ba18ddd81 | 6400 | #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
| mbed_official | 126:549ba18ddd81 | 6401 | #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
| mbed_official | 126:549ba18ddd81 | 6402 | #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6403 | #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6404 | |
| mbed_official | 126:549ba18ddd81 | 6405 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6406 | #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
| mbed_official | 126:549ba18ddd81 | 6407 | #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ |
| mbed_official | 126:549ba18ddd81 | 6408 | #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
| mbed_official | 126:549ba18ddd81 | 6409 | |
| mbed_official | 126:549ba18ddd81 | 6410 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6411 | #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
| mbed_official | 126:549ba18ddd81 | 6412 | #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
| mbed_official | 126:549ba18ddd81 | 6413 | #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
| mbed_official | 126:549ba18ddd81 | 6414 | #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
| mbed_official | 126:549ba18ddd81 | 6415 | |
| mbed_official | 126:549ba18ddd81 | 6416 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6417 | #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
| mbed_official | 126:549ba18ddd81 | 6418 | #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
| mbed_official | 126:549ba18ddd81 | 6419 | #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
| mbed_official | 126:549ba18ddd81 | 6420 | #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
| mbed_official | 126:549ba18ddd81 | 6421 | |
| mbed_official | 126:549ba18ddd81 | 6422 | /******************* Bit definition for CAN_TI2R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6423 | #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ |
| mbed_official | 126:549ba18ddd81 | 6424 | #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
| mbed_official | 126:549ba18ddd81 | 6425 | #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
| mbed_official | 126:549ba18ddd81 | 6426 | #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ |
| mbed_official | 126:549ba18ddd81 | 6427 | #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6428 | |
| mbed_official | 126:549ba18ddd81 | 6429 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6430 | #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
| mbed_official | 126:549ba18ddd81 | 6431 | #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ |
| mbed_official | 126:549ba18ddd81 | 6432 | #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
| mbed_official | 126:549ba18ddd81 | 6433 | |
| mbed_official | 126:549ba18ddd81 | 6434 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6435 | #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
| mbed_official | 126:549ba18ddd81 | 6436 | #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
| mbed_official | 126:549ba18ddd81 | 6437 | #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
| mbed_official | 126:549ba18ddd81 | 6438 | #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
| mbed_official | 126:549ba18ddd81 | 6439 | |
| mbed_official | 126:549ba18ddd81 | 6440 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6441 | #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
| mbed_official | 126:549ba18ddd81 | 6442 | #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
| mbed_official | 126:549ba18ddd81 | 6443 | #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
| mbed_official | 126:549ba18ddd81 | 6444 | #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
| mbed_official | 126:549ba18ddd81 | 6445 | |
| mbed_official | 126:549ba18ddd81 | 6446 | /******************* Bit definition for CAN_RI0R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6447 | #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
| mbed_official | 126:549ba18ddd81 | 6448 | #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
| mbed_official | 126:549ba18ddd81 | 6449 | #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6450 | #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6451 | |
| mbed_official | 126:549ba18ddd81 | 6452 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6453 | #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
| mbed_official | 126:549ba18ddd81 | 6454 | #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ |
| mbed_official | 126:549ba18ddd81 | 6455 | #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
| mbed_official | 126:549ba18ddd81 | 6456 | |
| mbed_official | 126:549ba18ddd81 | 6457 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6458 | #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
| mbed_official | 126:549ba18ddd81 | 6459 | #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
| mbed_official | 126:549ba18ddd81 | 6460 | #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
| mbed_official | 126:549ba18ddd81 | 6461 | #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
| mbed_official | 126:549ba18ddd81 | 6462 | |
| mbed_official | 126:549ba18ddd81 | 6463 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6464 | #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
| mbed_official | 126:549ba18ddd81 | 6465 | #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
| mbed_official | 126:549ba18ddd81 | 6466 | #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
| mbed_official | 126:549ba18ddd81 | 6467 | #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
| mbed_official | 126:549ba18ddd81 | 6468 | |
| mbed_official | 126:549ba18ddd81 | 6469 | /******************* Bit definition for CAN_RI1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6470 | #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
| mbed_official | 126:549ba18ddd81 | 6471 | #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
| mbed_official | 126:549ba18ddd81 | 6472 | #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ |
| mbed_official | 126:549ba18ddd81 | 6473 | #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
| mbed_official | 126:549ba18ddd81 | 6474 | |
| mbed_official | 126:549ba18ddd81 | 6475 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6476 | #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
| mbed_official | 126:549ba18ddd81 | 6477 | #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ |
| mbed_official | 126:549ba18ddd81 | 6478 | #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
| mbed_official | 126:549ba18ddd81 | 6479 | |
| mbed_official | 126:549ba18ddd81 | 6480 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6481 | #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
| mbed_official | 126:549ba18ddd81 | 6482 | #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
| mbed_official | 126:549ba18ddd81 | 6483 | #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
| mbed_official | 126:549ba18ddd81 | 6484 | #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
| mbed_official | 126:549ba18ddd81 | 6485 | |
| mbed_official | 126:549ba18ddd81 | 6486 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6487 | #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
| mbed_official | 126:549ba18ddd81 | 6488 | #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
| mbed_official | 126:549ba18ddd81 | 6489 | #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
| mbed_official | 126:549ba18ddd81 | 6490 | #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
| mbed_official | 126:549ba18ddd81 | 6491 | |
| mbed_official | 126:549ba18ddd81 | 6492 | /*!< CAN filter registers */ |
| mbed_official | 126:549ba18ddd81 | 6493 | /******************* Bit definition for CAN_FMR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 6494 | #define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ |
| mbed_official | 126:549ba18ddd81 | 6495 | |
| mbed_official | 126:549ba18ddd81 | 6496 | /******************* Bit definition for CAN_FM1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6497 | #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ |
| mbed_official | 126:549ba18ddd81 | 6498 | #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6499 | #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6500 | #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6501 | #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6502 | #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6503 | #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6504 | #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6505 | #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6506 | #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6507 | #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6508 | #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6509 | #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6510 | #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6511 | #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6512 | |
| mbed_official | 126:549ba18ddd81 | 6513 | /******************* Bit definition for CAN_FS1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6514 | #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ |
| mbed_official | 126:549ba18ddd81 | 6515 | #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6516 | #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6517 | #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6518 | #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6519 | #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6520 | #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6521 | #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6522 | #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6523 | #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6524 | #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6525 | #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6526 | #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6527 | #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6528 | #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6529 | |
| mbed_official | 126:549ba18ddd81 | 6530 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6531 | #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ |
| mbed_official | 126:549ba18ddd81 | 6532 | #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ |
| mbed_official | 126:549ba18ddd81 | 6533 | #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ |
| mbed_official | 126:549ba18ddd81 | 6534 | #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ |
| mbed_official | 126:549ba18ddd81 | 6535 | #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ |
| mbed_official | 126:549ba18ddd81 | 6536 | #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ |
| mbed_official | 126:549ba18ddd81 | 6537 | #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ |
| mbed_official | 126:549ba18ddd81 | 6538 | #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ |
| mbed_official | 126:549ba18ddd81 | 6539 | #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ |
| mbed_official | 126:549ba18ddd81 | 6540 | #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ |
| mbed_official | 126:549ba18ddd81 | 6541 | #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ |
| mbed_official | 126:549ba18ddd81 | 6542 | #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ |
| mbed_official | 126:549ba18ddd81 | 6543 | #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ |
| mbed_official | 126:549ba18ddd81 | 6544 | #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ |
| mbed_official | 126:549ba18ddd81 | 6545 | #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ |
| mbed_official | 126:549ba18ddd81 | 6546 | |
| mbed_official | 126:549ba18ddd81 | 6547 | /******************* Bit definition for CAN_FA1R register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6548 | #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ |
| mbed_official | 126:549ba18ddd81 | 6549 | #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ |
| mbed_official | 126:549ba18ddd81 | 6550 | #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ |
| mbed_official | 126:549ba18ddd81 | 6551 | #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ |
| mbed_official | 126:549ba18ddd81 | 6552 | #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ |
| mbed_official | 126:549ba18ddd81 | 6553 | #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ |
| mbed_official | 126:549ba18ddd81 | 6554 | #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ |
| mbed_official | 126:549ba18ddd81 | 6555 | #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ |
| mbed_official | 126:549ba18ddd81 | 6556 | #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ |
| mbed_official | 126:549ba18ddd81 | 6557 | #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ |
| mbed_official | 126:549ba18ddd81 | 6558 | #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ |
| mbed_official | 126:549ba18ddd81 | 6559 | #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ |
| mbed_official | 126:549ba18ddd81 | 6560 | #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ |
| mbed_official | 126:549ba18ddd81 | 6561 | #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ |
| mbed_official | 126:549ba18ddd81 | 6562 | #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ |
| mbed_official | 126:549ba18ddd81 | 6563 | |
| mbed_official | 126:549ba18ddd81 | 6564 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6565 | #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6566 | #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6567 | #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6568 | #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6569 | #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6570 | #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6571 | #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6572 | #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6573 | #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6574 | #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6575 | #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6576 | #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6577 | #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6578 | #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6579 | #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6580 | #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6581 | #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6582 | #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6583 | #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6584 | #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6585 | #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6586 | #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6587 | #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6588 | #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6589 | #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6590 | #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6591 | #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6592 | #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6593 | #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6594 | #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6595 | #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6596 | #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6597 | |
| mbed_official | 126:549ba18ddd81 | 6598 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6599 | #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6600 | #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6601 | #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6602 | #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6603 | #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6604 | #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6605 | #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6606 | #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6607 | #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6608 | #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6609 | #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6610 | #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6611 | #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6612 | #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6613 | #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6614 | #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6615 | #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6616 | #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6617 | #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6618 | #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6619 | #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6620 | #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6621 | #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6622 | #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6623 | #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6624 | #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6625 | #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6626 | #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6627 | #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6628 | #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6629 | #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6630 | #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6631 | |
| mbed_official | 126:549ba18ddd81 | 6632 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6633 | #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6634 | #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6635 | #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6636 | #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6637 | #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6638 | #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6639 | #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6640 | #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6641 | #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6642 | #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6643 | #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6644 | #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6645 | #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6646 | #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6647 | #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6648 | #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6649 | #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6650 | #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6651 | #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6652 | #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6653 | #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6654 | #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6655 | #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6656 | #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6657 | #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6658 | #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6659 | #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6660 | #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6661 | #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6662 | #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6663 | #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6664 | #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6665 | |
| mbed_official | 126:549ba18ddd81 | 6666 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6667 | #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6668 | #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6669 | #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6670 | #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6671 | #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6672 | #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6673 | #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6674 | #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6675 | #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6676 | #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6677 | #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6678 | #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6679 | #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6680 | #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6681 | #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6682 | #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6683 | #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6684 | #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6685 | #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6686 | #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6687 | #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6688 | #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6689 | #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6690 | #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6691 | #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6692 | #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6693 | #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6694 | #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6695 | #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6696 | #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6697 | #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6698 | #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6699 | |
| mbed_official | 126:549ba18ddd81 | 6700 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6701 | #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6702 | #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6703 | #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6704 | #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6705 | #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6706 | #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6707 | #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6708 | #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6709 | #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6710 | #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6711 | #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6712 | #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6713 | #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6714 | #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6715 | #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6716 | #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6717 | #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6718 | #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6719 | #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6720 | #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6721 | #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6722 | #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6723 | #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6724 | #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6725 | #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6726 | #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6727 | #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6728 | #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6729 | #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6730 | #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6731 | #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6732 | #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6733 | |
| mbed_official | 126:549ba18ddd81 | 6734 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6735 | #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6736 | #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6737 | #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6738 | #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6739 | #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6740 | #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6741 | #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6742 | #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6743 | #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6744 | #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6745 | #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6746 | #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6747 | #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6748 | #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6749 | #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6750 | #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6751 | #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6752 | #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6753 | #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6754 | #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6755 | #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6756 | #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6757 | #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6758 | #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6759 | #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6760 | #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6761 | #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6762 | #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6763 | #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6764 | #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6765 | #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6766 | #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6767 | |
| mbed_official | 126:549ba18ddd81 | 6768 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6769 | #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6770 | #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6771 | #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6772 | #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6773 | #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6774 | #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6775 | #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6776 | #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6777 | #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6778 | #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6779 | #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6780 | #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6781 | #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6782 | #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6783 | #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6784 | #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6785 | #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6786 | #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6787 | #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6788 | #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6789 | #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6790 | #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6791 | #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6792 | #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6793 | #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6794 | #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6795 | #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6796 | #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6797 | #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6798 | #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6799 | #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6800 | #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6801 | |
| mbed_official | 126:549ba18ddd81 | 6802 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6803 | #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6804 | #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6805 | #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6806 | #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6807 | #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6808 | #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6809 | #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6810 | #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6811 | #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6812 | #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6813 | #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6814 | #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6815 | #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6816 | #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6817 | #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6818 | #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6819 | #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6820 | #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6821 | #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6822 | #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6823 | #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6824 | #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6825 | #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6826 | #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6827 | #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6828 | #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6829 | #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6830 | #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6831 | #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6832 | #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6833 | #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6834 | #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6835 | |
| mbed_official | 126:549ba18ddd81 | 6836 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6837 | #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6838 | #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6839 | #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6840 | #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6841 | #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6842 | #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6843 | #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6844 | #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6845 | #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6846 | #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6847 | #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6848 | #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6849 | #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6850 | #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6851 | #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6852 | #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6853 | #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6854 | #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6855 | #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6856 | #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6857 | #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6858 | #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6859 | #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6860 | #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6861 | #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6862 | #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6863 | #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6864 | #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6865 | #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6866 | #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6867 | #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6868 | #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6869 | |
| mbed_official | 126:549ba18ddd81 | 6870 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 6871 | #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6872 | #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6873 | #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6874 | #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6875 | #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6876 | #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6877 | #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6878 | #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6879 | #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6880 | #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6881 | #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6882 | #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6883 | #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6884 | #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6885 | #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6886 | #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6887 | #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6888 | #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6889 | #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6890 | #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6891 | #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6892 | #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6893 | #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6894 | #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6895 | #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6896 | #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6897 | #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6898 | #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6899 | #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6900 | #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6901 | #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6902 | #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6903 | |
| mbed_official | 126:549ba18ddd81 | 6904 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6905 | #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6906 | #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6907 | #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6908 | #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6909 | #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6910 | #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6911 | #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6912 | #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6913 | #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6914 | #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6915 | #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6916 | #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6917 | #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6918 | #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6919 | #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6920 | #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6921 | #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6922 | #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6923 | #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6924 | #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6925 | #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6926 | #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6927 | #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6928 | #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6929 | #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6930 | #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6931 | #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6932 | #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6933 | #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6934 | #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6935 | #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6936 | #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6937 | |
| mbed_official | 126:549ba18ddd81 | 6938 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6939 | #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6940 | #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6941 | #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6942 | #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6943 | #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6944 | #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6945 | #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6946 | #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6947 | #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6948 | #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6949 | #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6950 | #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6951 | #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6952 | #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6953 | #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6954 | #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6955 | #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6956 | #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6957 | #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6958 | #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6959 | #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6960 | #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6961 | #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6962 | #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6963 | #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6964 | #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6965 | #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 6966 | #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 6967 | #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 6968 | #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 6969 | #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 6970 | #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 6971 | |
| mbed_official | 126:549ba18ddd81 | 6972 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 6973 | #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 6974 | #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 6975 | #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 6976 | #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 6977 | #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 6978 | #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 6979 | #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 6980 | #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 6981 | #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 6982 | #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 6983 | #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 6984 | #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 6985 | #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 6986 | #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 6987 | #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 6988 | #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 6989 | #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 6990 | #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 6991 | #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 6992 | #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 6993 | #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 6994 | #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 6995 | #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 6996 | #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 6997 | #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 6998 | #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 6999 | #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7000 | #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7001 | #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7002 | #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7003 | #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7004 | #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7005 | |
| mbed_official | 126:549ba18ddd81 | 7006 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7007 | #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7008 | #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7009 | #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7010 | #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7011 | #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7012 | #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7013 | #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7014 | #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7015 | #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7016 | #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7017 | #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7018 | #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7019 | #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7020 | #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7021 | #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7022 | #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7023 | #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7024 | #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7025 | #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7026 | #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7027 | #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7028 | #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7029 | #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7030 | #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7031 | #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7032 | #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7033 | #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7034 | #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7035 | #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7036 | #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7037 | #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7038 | #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7039 | |
| mbed_official | 126:549ba18ddd81 | 7040 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7041 | #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7042 | #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7043 | #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7044 | #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7045 | #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7046 | #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7047 | #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7048 | #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7049 | #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7050 | #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7051 | #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7052 | #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7053 | #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7054 | #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7055 | #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7056 | #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7057 | #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7058 | #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7059 | #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7060 | #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7061 | #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7062 | #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7063 | #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7064 | #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7065 | #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7066 | #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7067 | #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7068 | #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7069 | #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7070 | #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7071 | #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7072 | #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7073 | |
| mbed_official | 126:549ba18ddd81 | 7074 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7075 | #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7076 | #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7077 | #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7078 | #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7079 | #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7080 | #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7081 | #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7082 | #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7083 | #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7084 | #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7085 | #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7086 | #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7087 | #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7088 | #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7089 | #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7090 | #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7091 | #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7092 | #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7093 | #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7094 | #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7095 | #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7096 | #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7097 | #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7098 | #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7099 | #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7100 | #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7101 | #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7102 | #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7103 | #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7104 | #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7105 | #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7106 | #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7107 | |
| mbed_official | 126:549ba18ddd81 | 7108 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7109 | #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7110 | #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7111 | #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7112 | #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7113 | #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7114 | #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7115 | #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7116 | #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7117 | #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7118 | #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7119 | #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7120 | #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7121 | #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7122 | #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7123 | #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7124 | #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7125 | #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7126 | #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7127 | #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7128 | #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7129 | #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7130 | #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7131 | #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7132 | #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7133 | #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7134 | #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7135 | #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7136 | #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7137 | #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7138 | #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7139 | #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7140 | #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7141 | |
| mbed_official | 126:549ba18ddd81 | 7142 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7143 | #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7144 | #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7145 | #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7146 | #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7147 | #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7148 | #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7149 | #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7150 | #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7151 | #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7152 | #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7153 | #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7154 | #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7155 | #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7156 | #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7157 | #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7158 | #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7159 | #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7160 | #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7161 | #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7162 | #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7163 | #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7164 | #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7165 | #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7166 | #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7167 | #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7168 | #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7169 | #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7170 | #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7171 | #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7172 | #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7173 | #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7174 | #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7175 | |
| mbed_official | 126:549ba18ddd81 | 7176 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7177 | #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7178 | #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7179 | #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7180 | #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7181 | #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7182 | #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7183 | #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7184 | #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7185 | #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7186 | #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7187 | #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7188 | #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7189 | #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7190 | #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7191 | #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7192 | #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7193 | #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7194 | #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7195 | #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7196 | #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7197 | #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7198 | #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7199 | #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7200 | #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7201 | #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7202 | #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7203 | #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7204 | #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7205 | #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7206 | #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7207 | #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7208 | #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7209 | |
| mbed_official | 126:549ba18ddd81 | 7210 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7211 | #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7212 | #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7213 | #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7214 | #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7215 | #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7216 | #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7217 | #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7218 | #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7219 | #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7220 | #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7221 | #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7222 | #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7223 | #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7224 | #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7225 | #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7226 | #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7227 | #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7228 | #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7229 | #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7230 | #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7231 | #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7232 | #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7233 | #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7234 | #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7235 | #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7236 | #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7237 | #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7238 | #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7239 | #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7240 | #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7241 | #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7242 | #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7243 | |
| mbed_official | 126:549ba18ddd81 | 7244 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7245 | #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7246 | #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7247 | #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7248 | #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7249 | #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7250 | #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7251 | #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7252 | #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7253 | #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7254 | #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7255 | #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7256 | #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7257 | #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7258 | #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7259 | #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7260 | #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7261 | #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7262 | #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7263 | #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7264 | #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7265 | #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7266 | #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7267 | #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7268 | #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7269 | #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7270 | #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7271 | #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7272 | #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7273 | #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7274 | #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7275 | #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7276 | #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7277 | |
| mbed_official | 126:549ba18ddd81 | 7278 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7279 | #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7280 | #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7281 | #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7282 | #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7283 | #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7284 | #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7285 | #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7286 | #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7287 | #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7288 | #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7289 | #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7290 | #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7291 | #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7292 | #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7293 | #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7294 | #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7295 | #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7296 | #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7297 | #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7298 | #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7299 | #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7300 | #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7301 | #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7302 | #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7303 | #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7304 | #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7305 | #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7306 | #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7307 | #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7308 | #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7309 | #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7310 | #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7311 | |
| mbed_official | 126:549ba18ddd81 | 7312 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7313 | #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7314 | #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7315 | #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7316 | #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7317 | #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7318 | #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7319 | #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7320 | #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7321 | #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7322 | #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7323 | #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7324 | #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7325 | #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7326 | #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7327 | #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7328 | #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7329 | #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7330 | #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7331 | #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7332 | #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7333 | #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7334 | #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7335 | #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7336 | #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7337 | #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7338 | #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7339 | #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7340 | #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7341 | #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7342 | #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7343 | #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7344 | #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7345 | |
| mbed_official | 126:549ba18ddd81 | 7346 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7347 | #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7348 | #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7349 | #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7350 | #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7351 | #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7352 | #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7353 | #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7354 | #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7355 | #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7356 | #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7357 | #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7358 | #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7359 | #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7360 | #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7361 | #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7362 | #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7363 | #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7364 | #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7365 | #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7366 | #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7367 | #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7368 | #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7369 | #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7370 | #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7371 | #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7372 | #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7373 | #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7374 | #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7375 | #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7376 | #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7377 | #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7378 | #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7379 | |
| mbed_official | 126:549ba18ddd81 | 7380 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7381 | #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7382 | #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7383 | #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7384 | #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7385 | #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7386 | #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7387 | #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7388 | #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7389 | #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7390 | #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7391 | #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7392 | #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7393 | #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7394 | #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7395 | #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7396 | #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7397 | #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7398 | #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7399 | #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7400 | #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7401 | #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7402 | #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7403 | #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7404 | #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7405 | #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7406 | #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7407 | #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7408 | #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7409 | #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7410 | #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7411 | #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7412 | #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7413 | |
| mbed_official | 126:549ba18ddd81 | 7414 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7415 | #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7416 | #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7417 | #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7418 | #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7419 | #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7420 | #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7421 | #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7422 | #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7423 | #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7424 | #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7425 | #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7426 | #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7427 | #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7428 | #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7429 | #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7430 | #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7431 | #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7432 | #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7433 | #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7434 | #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7435 | #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7436 | #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7437 | #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7438 | #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7439 | #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7440 | #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7441 | #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7442 | #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7443 | #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7444 | #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7445 | #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7446 | #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7447 | |
| mbed_official | 126:549ba18ddd81 | 7448 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7449 | #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7450 | #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7451 | #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7452 | #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7453 | #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7454 | #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7455 | #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7456 | #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7457 | #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7458 | #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7459 | #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7460 | #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7461 | #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7462 | #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7463 | #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7464 | #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7465 | #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7466 | #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7467 | #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7468 | #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7469 | #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7470 | #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7471 | #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7472 | #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7473 | #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7474 | #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7475 | #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7476 | #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7477 | #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7478 | #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7479 | #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7480 | #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7481 | |
| mbed_official | 126:549ba18ddd81 | 7482 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7483 | #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7484 | #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7485 | #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7486 | #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7487 | #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7488 | #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7489 | #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7490 | #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7491 | #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7492 | #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7493 | #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7494 | #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7495 | #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7496 | #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7497 | #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7498 | #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7499 | #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
| mbed_official | 126:549ba18ddd81 | 7500 | #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
| mbed_official | 126:549ba18ddd81 | 7501 | #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
| mbed_official | 126:549ba18ddd81 | 7502 | #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
| mbed_official | 126:549ba18ddd81 | 7503 | #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
| mbed_official | 126:549ba18ddd81 | 7504 | #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
| mbed_official | 126:549ba18ddd81 | 7505 | #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
| mbed_official | 126:549ba18ddd81 | 7506 | #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
| mbed_official | 126:549ba18ddd81 | 7507 | #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
| mbed_official | 126:549ba18ddd81 | 7508 | #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
| mbed_official | 126:549ba18ddd81 | 7509 | #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
| mbed_official | 126:549ba18ddd81 | 7510 | #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
| mbed_official | 126:549ba18ddd81 | 7511 | #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
| mbed_official | 126:549ba18ddd81 | 7512 | #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
| mbed_official | 126:549ba18ddd81 | 7513 | #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
| mbed_official | 126:549ba18ddd81 | 7514 | #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
| mbed_official | 126:549ba18ddd81 | 7515 | |
| mbed_official | 126:549ba18ddd81 | 7516 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7517 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7518 | /* Serial Peripheral Interface */ |
| mbed_official | 126:549ba18ddd81 | 7519 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7520 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7521 | |
| mbed_official | 126:549ba18ddd81 | 7522 | /******************* Bit definition for SPI_CR1 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7523 | #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ |
| mbed_official | 126:549ba18ddd81 | 7524 | #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ |
| mbed_official | 126:549ba18ddd81 | 7525 | #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ |
| mbed_official | 126:549ba18ddd81 | 7526 | |
| mbed_official | 126:549ba18ddd81 | 7527 | #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ |
| mbed_official | 126:549ba18ddd81 | 7528 | #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7529 | #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7530 | #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7531 | |
| mbed_official | 126:549ba18ddd81 | 7532 | #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ |
| mbed_official | 126:549ba18ddd81 | 7533 | #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ |
| mbed_official | 126:549ba18ddd81 | 7534 | #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ |
| mbed_official | 126:549ba18ddd81 | 7535 | #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ |
| mbed_official | 126:549ba18ddd81 | 7536 | #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ |
| mbed_official | 126:549ba18ddd81 | 7537 | #define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ |
| mbed_official | 126:549ba18ddd81 | 7538 | #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ |
| mbed_official | 126:549ba18ddd81 | 7539 | #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ |
| mbed_official | 126:549ba18ddd81 | 7540 | #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ |
| mbed_official | 126:549ba18ddd81 | 7541 | #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ |
| mbed_official | 126:549ba18ddd81 | 7542 | |
| mbed_official | 126:549ba18ddd81 | 7543 | /******************* Bit definition for SPI_CR2 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7544 | #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ |
| mbed_official | 126:549ba18ddd81 | 7545 | #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ |
| mbed_official | 126:549ba18ddd81 | 7546 | #define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ |
| mbed_official | 126:549ba18ddd81 | 7547 | #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7548 | #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7549 | #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7550 | |
| mbed_official | 126:549ba18ddd81 | 7551 | /******************** Bit definition for SPI_SR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7552 | #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ |
| mbed_official | 126:549ba18ddd81 | 7553 | #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ |
| mbed_official | 126:549ba18ddd81 | 7554 | #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ |
| mbed_official | 126:549ba18ddd81 | 7555 | #define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ |
| mbed_official | 126:549ba18ddd81 | 7556 | #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ |
| mbed_official | 126:549ba18ddd81 | 7557 | #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ |
| mbed_official | 126:549ba18ddd81 | 7558 | #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ |
| mbed_official | 126:549ba18ddd81 | 7559 | #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ |
| mbed_official | 126:549ba18ddd81 | 7560 | |
| mbed_official | 126:549ba18ddd81 | 7561 | /******************** Bit definition for SPI_DR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7562 | #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ |
| mbed_official | 126:549ba18ddd81 | 7563 | |
| mbed_official | 126:549ba18ddd81 | 7564 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7565 | #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ |
| mbed_official | 126:549ba18ddd81 | 7566 | |
| mbed_official | 126:549ba18ddd81 | 7567 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7568 | #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ |
| mbed_official | 126:549ba18ddd81 | 7569 | |
| mbed_official | 126:549ba18ddd81 | 7570 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7571 | #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ |
| mbed_official | 126:549ba18ddd81 | 7572 | |
| mbed_official | 126:549ba18ddd81 | 7573 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
| mbed_official | 126:549ba18ddd81 | 7574 | #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ |
| mbed_official | 126:549ba18ddd81 | 7575 | |
| mbed_official | 126:549ba18ddd81 | 7576 | #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ |
| mbed_official | 126:549ba18ddd81 | 7577 | #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7578 | #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7579 | |
| mbed_official | 126:549ba18ddd81 | 7580 | #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ |
| mbed_official | 126:549ba18ddd81 | 7581 | |
| mbed_official | 126:549ba18ddd81 | 7582 | #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ |
| mbed_official | 126:549ba18ddd81 | 7583 | #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7584 | #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7585 | |
| mbed_official | 126:549ba18ddd81 | 7586 | #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ |
| mbed_official | 126:549ba18ddd81 | 7587 | |
| mbed_official | 126:549ba18ddd81 | 7588 | #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ |
| mbed_official | 126:549ba18ddd81 | 7589 | #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7590 | #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7591 | |
| mbed_official | 126:549ba18ddd81 | 7592 | #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ |
| mbed_official | 126:549ba18ddd81 | 7593 | #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ |
| mbed_official | 126:549ba18ddd81 | 7594 | |
| mbed_official | 126:549ba18ddd81 | 7595 | /****************** Bit definition for SPI_I2SPR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7596 | #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ |
| mbed_official | 126:549ba18ddd81 | 7597 | #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ |
| mbed_official | 126:549ba18ddd81 | 7598 | #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ |
| mbed_official | 126:549ba18ddd81 | 7599 | |
| mbed_official | 126:549ba18ddd81 | 7600 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7601 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7602 | /* Inter-integrated Circuit Interface */ |
| mbed_official | 126:549ba18ddd81 | 7603 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7604 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7605 | |
| mbed_official | 126:549ba18ddd81 | 7606 | /******************* Bit definition for I2C_CR1 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7607 | #define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ |
| mbed_official | 126:549ba18ddd81 | 7608 | #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ |
| mbed_official | 126:549ba18ddd81 | 7609 | #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ |
| mbed_official | 126:549ba18ddd81 | 7610 | #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ |
| mbed_official | 126:549ba18ddd81 | 7611 | #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ |
| mbed_official | 126:549ba18ddd81 | 7612 | #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ |
| mbed_official | 126:549ba18ddd81 | 7613 | #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7614 | #define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ |
| mbed_official | 126:549ba18ddd81 | 7615 | #define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ |
| mbed_official | 126:549ba18ddd81 | 7616 | #define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ |
| mbed_official | 126:549ba18ddd81 | 7617 | #define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ |
| mbed_official | 126:549ba18ddd81 | 7618 | #define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ |
| mbed_official | 126:549ba18ddd81 | 7619 | #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ |
| mbed_official | 126:549ba18ddd81 | 7620 | #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ |
| mbed_official | 126:549ba18ddd81 | 7621 | |
| mbed_official | 126:549ba18ddd81 | 7622 | /******************* Bit definition for I2C_CR2 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7623 | #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
| mbed_official | 126:549ba18ddd81 | 7624 | #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7625 | #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7626 | #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7627 | #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7628 | #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7629 | #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7630 | |
| mbed_official | 126:549ba18ddd81 | 7631 | #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7632 | #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7633 | #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7634 | #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ |
| mbed_official | 126:549ba18ddd81 | 7635 | #define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ |
| mbed_official | 126:549ba18ddd81 | 7636 | |
| mbed_official | 126:549ba18ddd81 | 7637 | /******************* Bit definition for I2C_OAR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7638 | #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ |
| mbed_official | 126:549ba18ddd81 | 7639 | #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ |
| mbed_official | 126:549ba18ddd81 | 7640 | |
| mbed_official | 126:549ba18ddd81 | 7641 | #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7642 | #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7643 | #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7644 | #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7645 | #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7646 | #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7647 | #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7648 | #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7649 | #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7650 | #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7651 | |
| mbed_official | 126:549ba18ddd81 | 7652 | #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7653 | |
| mbed_official | 126:549ba18ddd81 | 7654 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7655 | #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ |
| mbed_official | 126:549ba18ddd81 | 7656 | #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ |
| mbed_official | 126:549ba18ddd81 | 7657 | |
| mbed_official | 126:549ba18ddd81 | 7658 | /******************** Bit definition for I2C_DR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7659 | #define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ |
| mbed_official | 126:549ba18ddd81 | 7660 | |
| mbed_official | 126:549ba18ddd81 | 7661 | /******************* Bit definition for I2C_SR1 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7662 | #define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ |
| mbed_official | 126:549ba18ddd81 | 7663 | #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7664 | #define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ |
| mbed_official | 126:549ba18ddd81 | 7665 | #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ |
| mbed_official | 126:549ba18ddd81 | 7666 | #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7667 | #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ |
| mbed_official | 126:549ba18ddd81 | 7668 | #define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ |
| mbed_official | 126:549ba18ddd81 | 7669 | #define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ |
| mbed_official | 126:549ba18ddd81 | 7670 | #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ |
| mbed_official | 126:549ba18ddd81 | 7671 | #define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ |
| mbed_official | 126:549ba18ddd81 | 7672 | #define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ |
| mbed_official | 126:549ba18ddd81 | 7673 | #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ |
| mbed_official | 126:549ba18ddd81 | 7674 | #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ |
| mbed_official | 126:549ba18ddd81 | 7675 | #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ |
| mbed_official | 126:549ba18ddd81 | 7676 | |
| mbed_official | 126:549ba18ddd81 | 7677 | /******************* Bit definition for I2C_SR2 register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7678 | #define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ |
| mbed_official | 126:549ba18ddd81 | 7679 | #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ |
| mbed_official | 126:549ba18ddd81 | 7680 | #define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ |
| mbed_official | 126:549ba18ddd81 | 7681 | #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7682 | #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7683 | #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7684 | #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ |
| mbed_official | 126:549ba18ddd81 | 7685 | #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ |
| mbed_official | 126:549ba18ddd81 | 7686 | |
| mbed_official | 126:549ba18ddd81 | 7687 | /******************* Bit definition for I2C_CCR register ********************/ |
| mbed_official | 126:549ba18ddd81 | 7688 | #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
| mbed_official | 126:549ba18ddd81 | 7689 | #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ |
| mbed_official | 126:549ba18ddd81 | 7690 | #define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ |
| mbed_official | 126:549ba18ddd81 | 7691 | |
| mbed_official | 126:549ba18ddd81 | 7692 | /****************** Bit definition for I2C_TRISE register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7693 | #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
| mbed_official | 126:549ba18ddd81 | 7694 | |
| mbed_official | 126:549ba18ddd81 | 7695 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7696 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7697 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
| mbed_official | 126:549ba18ddd81 | 7698 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7699 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7700 | |
| mbed_official | 126:549ba18ddd81 | 7701 | /******************* Bit definition for USART_SR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7702 | #define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ |
| mbed_official | 126:549ba18ddd81 | 7703 | #define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ |
| mbed_official | 126:549ba18ddd81 | 7704 | #define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ |
| mbed_official | 126:549ba18ddd81 | 7705 | #define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ |
| mbed_official | 126:549ba18ddd81 | 7706 | #define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ |
| mbed_official | 126:549ba18ddd81 | 7707 | #define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ |
| mbed_official | 126:549ba18ddd81 | 7708 | #define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ |
| mbed_official | 126:549ba18ddd81 | 7709 | #define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ |
| mbed_official | 126:549ba18ddd81 | 7710 | #define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ |
| mbed_official | 126:549ba18ddd81 | 7711 | #define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ |
| mbed_official | 126:549ba18ddd81 | 7712 | |
| mbed_official | 126:549ba18ddd81 | 7713 | /******************* Bit definition for USART_DR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7714 | #define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ |
| mbed_official | 126:549ba18ddd81 | 7715 | |
| mbed_official | 126:549ba18ddd81 | 7716 | /****************** Bit definition for USART_BRR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7717 | #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ |
| mbed_official | 126:549ba18ddd81 | 7718 | #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ |
| mbed_official | 126:549ba18ddd81 | 7719 | |
| mbed_official | 126:549ba18ddd81 | 7720 | /****************** Bit definition for USART_CR1 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7721 | #define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ |
| mbed_official | 126:549ba18ddd81 | 7722 | #define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ |
| mbed_official | 126:549ba18ddd81 | 7723 | #define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ |
| mbed_official | 126:549ba18ddd81 | 7724 | #define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ |
| mbed_official | 126:549ba18ddd81 | 7725 | #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7726 | #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7727 | #define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7728 | #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7729 | #define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7730 | #define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ |
| mbed_official | 126:549ba18ddd81 | 7731 | #define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ |
| mbed_official | 126:549ba18ddd81 | 7732 | #define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ |
| mbed_official | 126:549ba18ddd81 | 7733 | #define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ |
| mbed_official | 126:549ba18ddd81 | 7734 | #define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ |
| mbed_official | 126:549ba18ddd81 | 7735 | #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ |
| mbed_official | 126:549ba18ddd81 | 7736 | |
| mbed_official | 126:549ba18ddd81 | 7737 | /****************** Bit definition for USART_CR2 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7738 | #define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ |
| mbed_official | 126:549ba18ddd81 | 7739 | #define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ |
| mbed_official | 126:549ba18ddd81 | 7740 | #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7741 | #define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ |
| mbed_official | 126:549ba18ddd81 | 7742 | #define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ |
| mbed_official | 126:549ba18ddd81 | 7743 | #define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ |
| mbed_official | 126:549ba18ddd81 | 7744 | #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ |
| mbed_official | 126:549ba18ddd81 | 7745 | |
| mbed_official | 126:549ba18ddd81 | 7746 | #define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ |
| mbed_official | 126:549ba18ddd81 | 7747 | #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7748 | #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7749 | |
| mbed_official | 126:549ba18ddd81 | 7750 | #define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ |
| mbed_official | 126:549ba18ddd81 | 7751 | |
| mbed_official | 126:549ba18ddd81 | 7752 | /****************** Bit definition for USART_CR3 register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7753 | #define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7754 | #define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ |
| mbed_official | 126:549ba18ddd81 | 7755 | #define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ |
| mbed_official | 126:549ba18ddd81 | 7756 | #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ |
| mbed_official | 126:549ba18ddd81 | 7757 | #define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ |
| mbed_official | 126:549ba18ddd81 | 7758 | #define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ |
| mbed_official | 126:549ba18ddd81 | 7759 | #define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ |
| mbed_official | 126:549ba18ddd81 | 7760 | #define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ |
| mbed_official | 126:549ba18ddd81 | 7761 | #define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ |
| mbed_official | 126:549ba18ddd81 | 7762 | #define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ |
| mbed_official | 126:549ba18ddd81 | 7763 | #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7764 | #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ |
| mbed_official | 126:549ba18ddd81 | 7765 | |
| mbed_official | 126:549ba18ddd81 | 7766 | /****************** Bit definition for USART_GTPR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7767 | #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ |
| mbed_official | 126:549ba18ddd81 | 7768 | #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7769 | #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7770 | #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7771 | #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7772 | #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7773 | #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7774 | #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7775 | #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7776 | |
| mbed_official | 126:549ba18ddd81 | 7777 | #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ |
| mbed_official | 126:549ba18ddd81 | 7778 | |
| mbed_official | 126:549ba18ddd81 | 7779 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7780 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7781 | /* Debug MCU */ |
| mbed_official | 126:549ba18ddd81 | 7782 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7783 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7784 | |
| mbed_official | 126:549ba18ddd81 | 7785 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
| mbed_official | 126:549ba18ddd81 | 7786 | #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ |
| mbed_official | 126:549ba18ddd81 | 7787 | |
| mbed_official | 126:549ba18ddd81 | 7788 | #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ |
| mbed_official | 126:549ba18ddd81 | 7789 | #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7790 | #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7791 | #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 126:549ba18ddd81 | 7792 | #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 126:549ba18ddd81 | 7793 | #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 126:549ba18ddd81 | 7794 | #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
| mbed_official | 126:549ba18ddd81 | 7795 | #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
| mbed_official | 126:549ba18ddd81 | 7796 | #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
| mbed_official | 126:549ba18ddd81 | 7797 | #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ |
| mbed_official | 126:549ba18ddd81 | 7798 | #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ |
| mbed_official | 126:549ba18ddd81 | 7799 | #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ |
| mbed_official | 126:549ba18ddd81 | 7800 | #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ |
| mbed_official | 126:549ba18ddd81 | 7801 | #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ |
| mbed_official | 126:549ba18ddd81 | 7802 | #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ |
| mbed_official | 126:549ba18ddd81 | 7803 | #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ |
| mbed_official | 126:549ba18ddd81 | 7804 | #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ |
| mbed_official | 126:549ba18ddd81 | 7805 | |
| mbed_official | 126:549ba18ddd81 | 7806 | /****************** Bit definition for DBGMCU_CR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7807 | #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ |
| mbed_official | 126:549ba18ddd81 | 7808 | #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ |
| mbed_official | 126:549ba18ddd81 | 7809 | #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ |
| mbed_official | 126:549ba18ddd81 | 7810 | #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ |
| mbed_official | 126:549ba18ddd81 | 7811 | |
| mbed_official | 126:549ba18ddd81 | 7812 | #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
| mbed_official | 126:549ba18ddd81 | 7813 | #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7814 | #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7815 | |
| mbed_official | 126:549ba18ddd81 | 7816 | #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7817 | #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7818 | #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7819 | #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7820 | #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7821 | #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7822 | #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7823 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7824 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7825 | #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7826 | #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7827 | #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7828 | #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7829 | #define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7830 | #define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7831 | #define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7832 | #define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7833 | #define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7834 | #define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7835 | #define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7836 | #define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7837 | #define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7838 | #define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ |
| mbed_official | 126:549ba18ddd81 | 7839 | |
| mbed_official | 126:549ba18ddd81 | 7840 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7841 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7842 | /* FLASH and Option Bytes Registers */ |
| mbed_official | 126:549ba18ddd81 | 7843 | /* */ |
| mbed_official | 126:549ba18ddd81 | 7844 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7845 | |
| mbed_official | 126:549ba18ddd81 | 7846 | /******************* Bit definition for FLASH_ACR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7847 | #define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!< LATENCY[2:0] bits (Latency) */ |
| mbed_official | 126:549ba18ddd81 | 7848 | #define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7849 | #define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ |
| mbed_official | 126:549ba18ddd81 | 7850 | #define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ |
| mbed_official | 126:549ba18ddd81 | 7851 | |
| mbed_official | 126:549ba18ddd81 | 7852 | #define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ |
| mbed_official | 126:549ba18ddd81 | 7853 | #define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ |
| mbed_official | 126:549ba18ddd81 | 7854 | #define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ |
| mbed_official | 126:549ba18ddd81 | 7855 | |
| mbed_official | 126:549ba18ddd81 | 7856 | /****************** Bit definition for FLASH_KEYR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7857 | #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ |
| mbed_official | 126:549ba18ddd81 | 7858 | |
| mbed_official | 126:549ba18ddd81 | 7859 | /****************** FLASH Keys **********************************************/ |
| mbed_official | 126:549ba18ddd81 | 7860 | #define RDP_Key ((uint16_t)0x00A5) |
| mbed_official | 126:549ba18ddd81 | 7861 | #define FLASH_KEY1 ((uint32_t)0x45670123) |
| mbed_official | 126:549ba18ddd81 | 7862 | #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| mbed_official | 126:549ba18ddd81 | 7863 | |
| mbed_official | 126:549ba18ddd81 | 7864 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
| mbed_official | 126:549ba18ddd81 | 7865 | #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ |
| mbed_official | 126:549ba18ddd81 | 7866 | |
| mbed_official | 126:549ba18ddd81 | 7867 | /****************** Bit definition for FLASH_SR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7868 | #define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ |
| mbed_official | 126:549ba18ddd81 | 7869 | #define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ |
| mbed_official | 126:549ba18ddd81 | 7870 | #define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ |
| mbed_official | 126:549ba18ddd81 | 7871 | #define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ |
| mbed_official | 126:549ba18ddd81 | 7872 | |
| mbed_official | 126:549ba18ddd81 | 7873 | /******************* Bit definition for FLASH_CR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7874 | #define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ |
| mbed_official | 126:549ba18ddd81 | 7875 | #define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ |
| mbed_official | 126:549ba18ddd81 | 7876 | #define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ |
| mbed_official | 126:549ba18ddd81 | 7877 | #define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ |
| mbed_official | 126:549ba18ddd81 | 7878 | #define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ |
| mbed_official | 126:549ba18ddd81 | 7879 | #define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ |
| mbed_official | 126:549ba18ddd81 | 7880 | #define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ |
| mbed_official | 126:549ba18ddd81 | 7881 | #define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ |
| mbed_official | 126:549ba18ddd81 | 7882 | #define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ |
| mbed_official | 126:549ba18ddd81 | 7883 | #define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 7884 | |
| mbed_official | 126:549ba18ddd81 | 7885 | /******************* Bit definition for FLASH_AR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7886 | #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ |
| mbed_official | 126:549ba18ddd81 | 7887 | |
| mbed_official | 126:549ba18ddd81 | 7888 | /****************** Bit definition for FLASH_OBR register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7889 | #define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ |
| mbed_official | 126:549ba18ddd81 | 7890 | #define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ |
| mbed_official | 126:549ba18ddd81 | 7891 | |
| mbed_official | 126:549ba18ddd81 | 7892 | #define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ |
| mbed_official | 126:549ba18ddd81 | 7893 | #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ |
| mbed_official | 126:549ba18ddd81 | 7894 | #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ |
| mbed_official | 126:549ba18ddd81 | 7895 | #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ |
| mbed_official | 126:549ba18ddd81 | 7896 | #define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ |
| mbed_official | 126:549ba18ddd81 | 7897 | |
| mbed_official | 126:549ba18ddd81 | 7898 | /****************** Bit definition for FLASH_WRPR register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7899 | #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ |
| mbed_official | 126:549ba18ddd81 | 7900 | |
| mbed_official | 126:549ba18ddd81 | 7901 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 126:549ba18ddd81 | 7902 | |
| mbed_official | 126:549ba18ddd81 | 7903 | /****************** Bit definition for FLASH_RDP register *******************/ |
| mbed_official | 126:549ba18ddd81 | 7904 | #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ |
| mbed_official | 126:549ba18ddd81 | 7905 | #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ |
| mbed_official | 126:549ba18ddd81 | 7906 | |
| mbed_official | 126:549ba18ddd81 | 7907 | /****************** Bit definition for FLASH_USER register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7908 | #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ |
| mbed_official | 126:549ba18ddd81 | 7909 | #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ |
| mbed_official | 126:549ba18ddd81 | 7910 | |
| mbed_official | 126:549ba18ddd81 | 7911 | /****************** Bit definition for FLASH_Data0 register *****************/ |
| mbed_official | 126:549ba18ddd81 | 7912 | #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ |
| mbed_official | 126:549ba18ddd81 | 7913 | #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ |
| mbed_official | 126:549ba18ddd81 | 7914 | |
| mbed_official | 126:549ba18ddd81 | 7915 | /****************** Bit definition for FLASH_Data1 register *****************/ |
| mbed_official | 126:549ba18ddd81 | 7916 | #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ |
| mbed_official | 126:549ba18ddd81 | 7917 | #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ |
| mbed_official | 126:549ba18ddd81 | 7918 | |
| mbed_official | 126:549ba18ddd81 | 7919 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7920 | #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7921 | #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7922 | |
| mbed_official | 126:549ba18ddd81 | 7923 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7924 | #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7925 | #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7926 | |
| mbed_official | 126:549ba18ddd81 | 7927 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7928 | #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7929 | #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7930 | |
| mbed_official | 126:549ba18ddd81 | 7931 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
| mbed_official | 126:549ba18ddd81 | 7932 | #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7933 | #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
| mbed_official | 126:549ba18ddd81 | 7934 | |
| mbed_official | 126:549ba18ddd81 | 7935 | #ifdef STM32F10X_CL |
| mbed_official | 126:549ba18ddd81 | 7936 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7937 | /* Ethernet MAC Registers bits definitions */ |
| mbed_official | 126:549ba18ddd81 | 7938 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 7939 | /* Bit definition for Ethernet MAC Control Register register */ |
| mbed_official | 126:549ba18ddd81 | 7940 | #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| mbed_official | 126:549ba18ddd81 | 7941 | #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| mbed_official | 126:549ba18ddd81 | 7942 | #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| mbed_official | 126:549ba18ddd81 | 7943 | #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| mbed_official | 126:549ba18ddd81 | 7944 | #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| mbed_official | 126:549ba18ddd81 | 7945 | #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| mbed_official | 126:549ba18ddd81 | 7946 | #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| mbed_official | 126:549ba18ddd81 | 7947 | #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| mbed_official | 126:549ba18ddd81 | 7948 | #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| mbed_official | 126:549ba18ddd81 | 7949 | #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| mbed_official | 126:549ba18ddd81 | 7950 | #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| mbed_official | 126:549ba18ddd81 | 7951 | #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| mbed_official | 126:549ba18ddd81 | 7952 | #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| mbed_official | 126:549ba18ddd81 | 7953 | #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| mbed_official | 126:549ba18ddd81 | 7954 | #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| mbed_official | 126:549ba18ddd81 | 7955 | #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| mbed_official | 126:549ba18ddd81 | 7956 | #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| mbed_official | 126:549ba18ddd81 | 7957 | #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| mbed_official | 126:549ba18ddd81 | 7958 | #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| mbed_official | 126:549ba18ddd81 | 7959 | #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
| mbed_official | 126:549ba18ddd81 | 7960 | a transmission attempt during retries after a collision: 0 =< r <2^k */ |
| mbed_official | 126:549ba18ddd81 | 7961 | #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| mbed_official | 126:549ba18ddd81 | 7962 | #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| mbed_official | 126:549ba18ddd81 | 7963 | #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| mbed_official | 126:549ba18ddd81 | 7964 | #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| mbed_official | 126:549ba18ddd81 | 7965 | #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| mbed_official | 126:549ba18ddd81 | 7966 | #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| mbed_official | 126:549ba18ddd81 | 7967 | #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| mbed_official | 126:549ba18ddd81 | 7968 | |
| mbed_official | 126:549ba18ddd81 | 7969 | /* Bit definition for Ethernet MAC Frame Filter Register */ |
| mbed_official | 126:549ba18ddd81 | 7970 | #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| mbed_official | 126:549ba18ddd81 | 7971 | #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| mbed_official | 126:549ba18ddd81 | 7972 | #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| mbed_official | 126:549ba18ddd81 | 7973 | #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| mbed_official | 126:549ba18ddd81 | 7974 | #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| mbed_official | 126:549ba18ddd81 | 7975 | #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| mbed_official | 126:549ba18ddd81 | 7976 | #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| mbed_official | 126:549ba18ddd81 | 7977 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| mbed_official | 126:549ba18ddd81 | 7978 | #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| mbed_official | 126:549ba18ddd81 | 7979 | #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| mbed_official | 126:549ba18ddd81 | 7980 | #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| mbed_official | 126:549ba18ddd81 | 7981 | #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| mbed_official | 126:549ba18ddd81 | 7982 | #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| mbed_official | 126:549ba18ddd81 | 7983 | #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| mbed_official | 126:549ba18ddd81 | 7984 | |
| mbed_official | 126:549ba18ddd81 | 7985 | /* Bit definition for Ethernet MAC Hash Table High Register */ |
| mbed_official | 126:549ba18ddd81 | 7986 | #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| mbed_official | 126:549ba18ddd81 | 7987 | |
| mbed_official | 126:549ba18ddd81 | 7988 | /* Bit definition for Ethernet MAC Hash Table Low Register */ |
| mbed_official | 126:549ba18ddd81 | 7989 | #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| mbed_official | 126:549ba18ddd81 | 7990 | |
| mbed_official | 126:549ba18ddd81 | 7991 | /* Bit definition for Ethernet MAC MII Address Register */ |
| mbed_official | 126:549ba18ddd81 | 7992 | #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| mbed_official | 126:549ba18ddd81 | 7993 | #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| mbed_official | 126:549ba18ddd81 | 7994 | #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| mbed_official | 126:549ba18ddd81 | 7995 | #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
| mbed_official | 126:549ba18ddd81 | 7996 | #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| mbed_official | 126:549ba18ddd81 | 7997 | #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| mbed_official | 126:549ba18ddd81 | 7998 | #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| mbed_official | 126:549ba18ddd81 | 7999 | #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| mbed_official | 126:549ba18ddd81 | 8000 | |
| mbed_official | 126:549ba18ddd81 | 8001 | /* Bit definition for Ethernet MAC MII Data Register */ |
| mbed_official | 126:549ba18ddd81 | 8002 | #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| mbed_official | 126:549ba18ddd81 | 8003 | |
| mbed_official | 126:549ba18ddd81 | 8004 | /* Bit definition for Ethernet MAC Flow Control Register */ |
| mbed_official | 126:549ba18ddd81 | 8005 | #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| mbed_official | 126:549ba18ddd81 | 8006 | #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| mbed_official | 126:549ba18ddd81 | 8007 | #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| mbed_official | 126:549ba18ddd81 | 8008 | #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| mbed_official | 126:549ba18ddd81 | 8009 | #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| mbed_official | 126:549ba18ddd81 | 8010 | #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| mbed_official | 126:549ba18ddd81 | 8011 | #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| mbed_official | 126:549ba18ddd81 | 8012 | #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| mbed_official | 126:549ba18ddd81 | 8013 | #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| mbed_official | 126:549ba18ddd81 | 8014 | #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| mbed_official | 126:549ba18ddd81 | 8015 | #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| mbed_official | 126:549ba18ddd81 | 8016 | |
| mbed_official | 126:549ba18ddd81 | 8017 | /* Bit definition for Ethernet MAC VLAN Tag Register */ |
| mbed_official | 126:549ba18ddd81 | 8018 | #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| mbed_official | 126:549ba18ddd81 | 8019 | #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| mbed_official | 126:549ba18ddd81 | 8020 | |
| mbed_official | 126:549ba18ddd81 | 8021 | /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
| mbed_official | 126:549ba18ddd81 | 8022 | #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| mbed_official | 126:549ba18ddd81 | 8023 | /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
| mbed_official | 126:549ba18ddd81 | 8024 | Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
| mbed_official | 126:549ba18ddd81 | 8025 | /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
| mbed_official | 126:549ba18ddd81 | 8026 | Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
| mbed_official | 126:549ba18ddd81 | 8027 | Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
| mbed_official | 126:549ba18ddd81 | 8028 | Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
| mbed_official | 126:549ba18ddd81 | 8029 | Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
| mbed_official | 126:549ba18ddd81 | 8030 | RSVD - Filter1 Command - RSVD - Filter0 Command |
| mbed_official | 126:549ba18ddd81 | 8031 | Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
| mbed_official | 126:549ba18ddd81 | 8032 | Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
| mbed_official | 126:549ba18ddd81 | 8033 | Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
| mbed_official | 126:549ba18ddd81 | 8034 | |
| mbed_official | 126:549ba18ddd81 | 8035 | /* Bit definition for Ethernet MAC PMT Control and Status Register */ |
| mbed_official | 126:549ba18ddd81 | 8036 | #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| mbed_official | 126:549ba18ddd81 | 8037 | #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| mbed_official | 126:549ba18ddd81 | 8038 | #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| mbed_official | 126:549ba18ddd81 | 8039 | #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| mbed_official | 126:549ba18ddd81 | 8040 | #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| mbed_official | 126:549ba18ddd81 | 8041 | #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| mbed_official | 126:549ba18ddd81 | 8042 | #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| mbed_official | 126:549ba18ddd81 | 8043 | |
| mbed_official | 126:549ba18ddd81 | 8044 | /* Bit definition for Ethernet MAC Status Register */ |
| mbed_official | 126:549ba18ddd81 | 8045 | #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| mbed_official | 126:549ba18ddd81 | 8046 | #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| mbed_official | 126:549ba18ddd81 | 8047 | #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| mbed_official | 126:549ba18ddd81 | 8048 | #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| mbed_official | 126:549ba18ddd81 | 8049 | #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| mbed_official | 126:549ba18ddd81 | 8050 | |
| mbed_official | 126:549ba18ddd81 | 8051 | /* Bit definition for Ethernet MAC Interrupt Mask Register */ |
| mbed_official | 126:549ba18ddd81 | 8052 | #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| mbed_official | 126:549ba18ddd81 | 8053 | #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| mbed_official | 126:549ba18ddd81 | 8054 | |
| mbed_official | 126:549ba18ddd81 | 8055 | /* Bit definition for Ethernet MAC Address0 High Register */ |
| mbed_official | 126:549ba18ddd81 | 8056 | #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| mbed_official | 126:549ba18ddd81 | 8057 | |
| mbed_official | 126:549ba18ddd81 | 8058 | /* Bit definition for Ethernet MAC Address0 Low Register */ |
| mbed_official | 126:549ba18ddd81 | 8059 | #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| mbed_official | 126:549ba18ddd81 | 8060 | |
| mbed_official | 126:549ba18ddd81 | 8061 | /* Bit definition for Ethernet MAC Address1 High Register */ |
| mbed_official | 126:549ba18ddd81 | 8062 | #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| mbed_official | 126:549ba18ddd81 | 8063 | #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| mbed_official | 126:549ba18ddd81 | 8064 | #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| mbed_official | 126:549ba18ddd81 | 8065 | #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| mbed_official | 126:549ba18ddd81 | 8066 | #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| mbed_official | 126:549ba18ddd81 | 8067 | #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| mbed_official | 126:549ba18ddd81 | 8068 | #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| mbed_official | 126:549ba18ddd81 | 8069 | #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| mbed_official | 126:549ba18ddd81 | 8070 | #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| mbed_official | 126:549ba18ddd81 | 8071 | #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| mbed_official | 126:549ba18ddd81 | 8072 | |
| mbed_official | 126:549ba18ddd81 | 8073 | /* Bit definition for Ethernet MAC Address1 Low Register */ |
| mbed_official | 126:549ba18ddd81 | 8074 | #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| mbed_official | 126:549ba18ddd81 | 8075 | |
| mbed_official | 126:549ba18ddd81 | 8076 | /* Bit definition for Ethernet MAC Address2 High Register */ |
| mbed_official | 126:549ba18ddd81 | 8077 | #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| mbed_official | 126:549ba18ddd81 | 8078 | #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| mbed_official | 126:549ba18ddd81 | 8079 | #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| mbed_official | 126:549ba18ddd81 | 8080 | #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| mbed_official | 126:549ba18ddd81 | 8081 | #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| mbed_official | 126:549ba18ddd81 | 8082 | #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| mbed_official | 126:549ba18ddd81 | 8083 | #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| mbed_official | 126:549ba18ddd81 | 8084 | #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| mbed_official | 126:549ba18ddd81 | 8085 | #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| mbed_official | 126:549ba18ddd81 | 8086 | #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| mbed_official | 126:549ba18ddd81 | 8087 | |
| mbed_official | 126:549ba18ddd81 | 8088 | /* Bit definition for Ethernet MAC Address2 Low Register */ |
| mbed_official | 126:549ba18ddd81 | 8089 | #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| mbed_official | 126:549ba18ddd81 | 8090 | |
| mbed_official | 126:549ba18ddd81 | 8091 | /* Bit definition for Ethernet MAC Address3 High Register */ |
| mbed_official | 126:549ba18ddd81 | 8092 | #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| mbed_official | 126:549ba18ddd81 | 8093 | #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| mbed_official | 126:549ba18ddd81 | 8094 | #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| mbed_official | 126:549ba18ddd81 | 8095 | #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| mbed_official | 126:549ba18ddd81 | 8096 | #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| mbed_official | 126:549ba18ddd81 | 8097 | #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| mbed_official | 126:549ba18ddd81 | 8098 | #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| mbed_official | 126:549ba18ddd81 | 8099 | #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| mbed_official | 126:549ba18ddd81 | 8100 | #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| mbed_official | 126:549ba18ddd81 | 8101 | #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| mbed_official | 126:549ba18ddd81 | 8102 | |
| mbed_official | 126:549ba18ddd81 | 8103 | /* Bit definition for Ethernet MAC Address3 Low Register */ |
| mbed_official | 126:549ba18ddd81 | 8104 | #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| mbed_official | 126:549ba18ddd81 | 8105 | |
| mbed_official | 126:549ba18ddd81 | 8106 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 8107 | /* Ethernet MMC Registers bits definition */ |
| mbed_official | 126:549ba18ddd81 | 8108 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 8109 | |
| mbed_official | 126:549ba18ddd81 | 8110 | /* Bit definition for Ethernet MMC Contol Register */ |
| mbed_official | 126:549ba18ddd81 | 8111 | #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| mbed_official | 126:549ba18ddd81 | 8112 | #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| mbed_official | 126:549ba18ddd81 | 8113 | #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| mbed_official | 126:549ba18ddd81 | 8114 | #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| mbed_official | 126:549ba18ddd81 | 8115 | |
| mbed_official | 126:549ba18ddd81 | 8116 | /* Bit definition for Ethernet MMC Receive Interrupt Register */ |
| mbed_official | 126:549ba18ddd81 | 8117 | #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8118 | #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8119 | #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8120 | |
| mbed_official | 126:549ba18ddd81 | 8121 | /* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
| mbed_official | 126:549ba18ddd81 | 8122 | #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8123 | #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8124 | #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8125 | |
| mbed_official | 126:549ba18ddd81 | 8126 | /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
| mbed_official | 126:549ba18ddd81 | 8127 | #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8128 | #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8129 | #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8130 | |
| mbed_official | 126:549ba18ddd81 | 8131 | /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
| mbed_official | 126:549ba18ddd81 | 8132 | #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8133 | #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8134 | #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| mbed_official | 126:549ba18ddd81 | 8135 | |
| mbed_official | 126:549ba18ddd81 | 8136 | /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8137 | #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| mbed_official | 126:549ba18ddd81 | 8138 | |
| mbed_official | 126:549ba18ddd81 | 8139 | /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8140 | #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| mbed_official | 126:549ba18ddd81 | 8141 | |
| mbed_official | 126:549ba18ddd81 | 8142 | /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8143 | #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| mbed_official | 126:549ba18ddd81 | 8144 | |
| mbed_official | 126:549ba18ddd81 | 8145 | /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8146 | #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| mbed_official | 126:549ba18ddd81 | 8147 | |
| mbed_official | 126:549ba18ddd81 | 8148 | /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8149 | #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| mbed_official | 126:549ba18ddd81 | 8150 | |
| mbed_official | 126:549ba18ddd81 | 8151 | /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8152 | #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| mbed_official | 126:549ba18ddd81 | 8153 | |
| mbed_official | 126:549ba18ddd81 | 8154 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 8155 | /* Ethernet PTP Registers bits definition */ |
| mbed_official | 126:549ba18ddd81 | 8156 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 8157 | |
| mbed_official | 126:549ba18ddd81 | 8158 | /* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
| mbed_official | 126:549ba18ddd81 | 8159 | #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| mbed_official | 126:549ba18ddd81 | 8160 | #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| mbed_official | 126:549ba18ddd81 | 8161 | #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| mbed_official | 126:549ba18ddd81 | 8162 | #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| mbed_official | 126:549ba18ddd81 | 8163 | #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| mbed_official | 126:549ba18ddd81 | 8164 | #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| mbed_official | 126:549ba18ddd81 | 8165 | |
| mbed_official | 126:549ba18ddd81 | 8166 | /* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
| mbed_official | 126:549ba18ddd81 | 8167 | #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| mbed_official | 126:549ba18ddd81 | 8168 | |
| mbed_official | 126:549ba18ddd81 | 8169 | /* Bit definition for Ethernet PTP Time Stamp High Register */ |
| mbed_official | 126:549ba18ddd81 | 8170 | #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| mbed_official | 126:549ba18ddd81 | 8171 | |
| mbed_official | 126:549ba18ddd81 | 8172 | /* Bit definition for Ethernet PTP Time Stamp Low Register */ |
| mbed_official | 126:549ba18ddd81 | 8173 | #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| mbed_official | 126:549ba18ddd81 | 8174 | #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| mbed_official | 126:549ba18ddd81 | 8175 | |
| mbed_official | 126:549ba18ddd81 | 8176 | /* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
| mbed_official | 126:549ba18ddd81 | 8177 | #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| mbed_official | 126:549ba18ddd81 | 8178 | |
| mbed_official | 126:549ba18ddd81 | 8179 | /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
| mbed_official | 126:549ba18ddd81 | 8180 | #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| mbed_official | 126:549ba18ddd81 | 8181 | #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| mbed_official | 126:549ba18ddd81 | 8182 | |
| mbed_official | 126:549ba18ddd81 | 8183 | /* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
| mbed_official | 126:549ba18ddd81 | 8184 | #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| mbed_official | 126:549ba18ddd81 | 8185 | |
| mbed_official | 126:549ba18ddd81 | 8186 | /* Bit definition for Ethernet PTP Target Time High Register */ |
| mbed_official | 126:549ba18ddd81 | 8187 | #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| mbed_official | 126:549ba18ddd81 | 8188 | |
| mbed_official | 126:549ba18ddd81 | 8189 | /* Bit definition for Ethernet PTP Target Time Low Register */ |
| mbed_official | 126:549ba18ddd81 | 8190 | #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| mbed_official | 126:549ba18ddd81 | 8191 | |
| mbed_official | 126:549ba18ddd81 | 8192 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 8193 | /* Ethernet DMA Registers bits definition */ |
| mbed_official | 126:549ba18ddd81 | 8194 | /******************************************************************************/ |
| mbed_official | 126:549ba18ddd81 | 8195 | |
| mbed_official | 126:549ba18ddd81 | 8196 | /* Bit definition for Ethernet DMA Bus Mode Register */ |
| mbed_official | 126:549ba18ddd81 | 8197 | #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| mbed_official | 126:549ba18ddd81 | 8198 | #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| mbed_official | 126:549ba18ddd81 | 8199 | #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| mbed_official | 126:549ba18ddd81 | 8200 | #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| mbed_official | 126:549ba18ddd81 | 8201 | #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| mbed_official | 126:549ba18ddd81 | 8202 | #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| mbed_official | 126:549ba18ddd81 | 8203 | #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| mbed_official | 126:549ba18ddd81 | 8204 | #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| mbed_official | 126:549ba18ddd81 | 8205 | #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| mbed_official | 126:549ba18ddd81 | 8206 | #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| mbed_official | 126:549ba18ddd81 | 8207 | #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| mbed_official | 126:549ba18ddd81 | 8208 | #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| mbed_official | 126:549ba18ddd81 | 8209 | #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| mbed_official | 126:549ba18ddd81 | 8210 | #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| mbed_official | 126:549ba18ddd81 | 8211 | #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| mbed_official | 126:549ba18ddd81 | 8212 | #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| mbed_official | 126:549ba18ddd81 | 8213 | #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| mbed_official | 126:549ba18ddd81 | 8214 | #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| mbed_official | 126:549ba18ddd81 | 8215 | #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| mbed_official | 126:549ba18ddd81 | 8216 | #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| mbed_official | 126:549ba18ddd81 | 8217 | #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| mbed_official | 126:549ba18ddd81 | 8218 | #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| mbed_official | 126:549ba18ddd81 | 8219 | #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| mbed_official | 126:549ba18ddd81 | 8220 | #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| mbed_official | 126:549ba18ddd81 | 8221 | #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| mbed_official | 126:549ba18ddd81 | 8222 | #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| mbed_official | 126:549ba18ddd81 | 8223 | #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| mbed_official | 126:549ba18ddd81 | 8224 | #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| mbed_official | 126:549ba18ddd81 | 8225 | #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| mbed_official | 126:549ba18ddd81 | 8226 | #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| mbed_official | 126:549ba18ddd81 | 8227 | #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| mbed_official | 126:549ba18ddd81 | 8228 | #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| mbed_official | 126:549ba18ddd81 | 8229 | #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| mbed_official | 126:549ba18ddd81 | 8230 | #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| mbed_official | 126:549ba18ddd81 | 8231 | #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| mbed_official | 126:549ba18ddd81 | 8232 | #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| mbed_official | 126:549ba18ddd81 | 8233 | #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| mbed_official | 126:549ba18ddd81 | 8234 | #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| mbed_official | 126:549ba18ddd81 | 8235 | |
| mbed_official | 126:549ba18ddd81 | 8236 | /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
| mbed_official | 126:549ba18ddd81 | 8237 | #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| mbed_official | 126:549ba18ddd81 | 8238 | |
| mbed_official | 126:549ba18ddd81 | 8239 | /* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
| mbed_official | 126:549ba18ddd81 | 8240 | #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| mbed_official | 126:549ba18ddd81 | 8241 | |
| mbed_official | 126:549ba18ddd81 | 8242 | /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
| mbed_official | 126:549ba18ddd81 | 8243 | #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| mbed_official | 126:549ba18ddd81 | 8244 | |
| mbed_official | 126:549ba18ddd81 | 8245 | /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
| mbed_official | 126:549ba18ddd81 | 8246 | #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| mbed_official | 126:549ba18ddd81 | 8247 | |
| mbed_official | 126:549ba18ddd81 | 8248 | /* Bit definition for Ethernet DMA Status Register */ |
| mbed_official | 126:549ba18ddd81 | 8249 | #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| mbed_official | 126:549ba18ddd81 | 8250 | #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| mbed_official | 126:549ba18ddd81 | 8251 | #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| mbed_official | 126:549ba18ddd81 | 8252 | #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| mbed_official | 126:549ba18ddd81 | 8253 | /* combination with EBS[2:0] for GetFlagStatus function */ |
| mbed_official | 126:549ba18ddd81 | 8254 | #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| mbed_official | 126:549ba18ddd81 | 8255 | #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| mbed_official | 126:549ba18ddd81 | 8256 | #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| mbed_official | 126:549ba18ddd81 | 8257 | #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| mbed_official | 126:549ba18ddd81 | 8258 | #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| mbed_official | 126:549ba18ddd81 | 8259 | #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| mbed_official | 126:549ba18ddd81 | 8260 | #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| mbed_official | 126:549ba18ddd81 | 8261 | #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| mbed_official | 126:549ba18ddd81 | 8262 | #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| mbed_official | 126:549ba18ddd81 | 8263 | #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| mbed_official | 126:549ba18ddd81 | 8264 | #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| mbed_official | 126:549ba18ddd81 | 8265 | #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| mbed_official | 126:549ba18ddd81 | 8266 | #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| mbed_official | 126:549ba18ddd81 | 8267 | #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| mbed_official | 126:549ba18ddd81 | 8268 | #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| mbed_official | 126:549ba18ddd81 | 8269 | #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| mbed_official | 126:549ba18ddd81 | 8270 | #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| mbed_official | 126:549ba18ddd81 | 8271 | #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| mbed_official | 126:549ba18ddd81 | 8272 | #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| mbed_official | 126:549ba18ddd81 | 8273 | #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| mbed_official | 126:549ba18ddd81 | 8274 | #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| mbed_official | 126:549ba18ddd81 | 8275 | #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| mbed_official | 126:549ba18ddd81 | 8276 | #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| mbed_official | 126:549ba18ddd81 | 8277 | #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| mbed_official | 126:549ba18ddd81 | 8278 | #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| mbed_official | 126:549ba18ddd81 | 8279 | #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| mbed_official | 126:549ba18ddd81 | 8280 | #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| mbed_official | 126:549ba18ddd81 | 8281 | #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| mbed_official | 126:549ba18ddd81 | 8282 | #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| mbed_official | 126:549ba18ddd81 | 8283 | #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| mbed_official | 126:549ba18ddd81 | 8284 | #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| mbed_official | 126:549ba18ddd81 | 8285 | #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| mbed_official | 126:549ba18ddd81 | 8286 | |
| mbed_official | 126:549ba18ddd81 | 8287 | /* Bit definition for Ethernet DMA Operation Mode Register */ |
| mbed_official | 126:549ba18ddd81 | 8288 | #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| mbed_official | 126:549ba18ddd81 | 8289 | #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| mbed_official | 126:549ba18ddd81 | 8290 | #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| mbed_official | 126:549ba18ddd81 | 8291 | #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| mbed_official | 126:549ba18ddd81 | 8292 | #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| mbed_official | 126:549ba18ddd81 | 8293 | #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| mbed_official | 126:549ba18ddd81 | 8294 | #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8295 | #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8296 | #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8297 | #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8298 | #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8299 | #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8300 | #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8301 | #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8302 | #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| mbed_official | 126:549ba18ddd81 | 8303 | #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| mbed_official | 126:549ba18ddd81 | 8304 | #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| mbed_official | 126:549ba18ddd81 | 8305 | #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| mbed_official | 126:549ba18ddd81 | 8306 | #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8307 | #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8308 | #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8309 | #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| mbed_official | 126:549ba18ddd81 | 8310 | #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| mbed_official | 126:549ba18ddd81 | 8311 | #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| mbed_official | 126:549ba18ddd81 | 8312 | |
| mbed_official | 126:549ba18ddd81 | 8313 | /* Bit definition for Ethernet DMA Interrupt Enable Register */ |
| mbed_official | 126:549ba18ddd81 | 8314 | #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| mbed_official | 126:549ba18ddd81 | 8315 | #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| mbed_official | 126:549ba18ddd81 | 8316 | #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8317 | #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8318 | #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8319 | #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8320 | #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8321 | #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8322 | #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8323 | #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8324 | #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8325 | #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8326 | #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8327 | #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8328 | #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| mbed_official | 126:549ba18ddd81 | 8329 | |
| mbed_official | 126:549ba18ddd81 | 8330 | /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
| mbed_official | 126:549ba18ddd81 | 8331 | #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| mbed_official | 126:549ba18ddd81 | 8332 | #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| mbed_official | 126:549ba18ddd81 | 8333 | #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| mbed_official | 126:549ba18ddd81 | 8334 | #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| mbed_official | 126:549ba18ddd81 | 8335 | |
| mbed_official | 126:549ba18ddd81 | 8336 | /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
| mbed_official | 126:549ba18ddd81 | 8337 | #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| mbed_official | 126:549ba18ddd81 | 8338 | |
| mbed_official | 126:549ba18ddd81 | 8339 | /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
| mbed_official | 126:549ba18ddd81 | 8340 | #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| mbed_official | 126:549ba18ddd81 | 8341 | |
| mbed_official | 126:549ba18ddd81 | 8342 | /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
| mbed_official | 126:549ba18ddd81 | 8343 | #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| mbed_official | 126:549ba18ddd81 | 8344 | |
| mbed_official | 126:549ba18ddd81 | 8345 | /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
| mbed_official | 126:549ba18ddd81 | 8346 | #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| mbed_official | 126:549ba18ddd81 | 8347 | #endif /* STM32F10X_CL */ |
| mbed_official | 126:549ba18ddd81 | 8348 | |
| mbed_official | 126:549ba18ddd81 | 8349 | /** |
| mbed_official | 126:549ba18ddd81 | 8350 | * @} |
| mbed_official | 126:549ba18ddd81 | 8351 | */ |
| mbed_official | 126:549ba18ddd81 | 8352 | |
| mbed_official | 126:549ba18ddd81 | 8353 | /** |
| mbed_official | 126:549ba18ddd81 | 8354 | * @} |
| mbed_official | 126:549ba18ddd81 | 8355 | */ |
| mbed_official | 126:549ba18ddd81 | 8356 | |
| mbed_official | 126:549ba18ddd81 | 8357 | #ifdef USE_STDPERIPH_DRIVER |
| mbed_official | 126:549ba18ddd81 | 8358 | #include "stm32f10x_conf.h" |
| mbed_official | 126:549ba18ddd81 | 8359 | #endif |
| mbed_official | 126:549ba18ddd81 | 8360 | |
| mbed_official | 126:549ba18ddd81 | 8361 | /** @addtogroup Exported_macro |
| mbed_official | 126:549ba18ddd81 | 8362 | * @{ |
| mbed_official | 126:549ba18ddd81 | 8363 | */ |
| mbed_official | 126:549ba18ddd81 | 8364 | |
| mbed_official | 126:549ba18ddd81 | 8365 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
| mbed_official | 126:549ba18ddd81 | 8366 | |
| mbed_official | 126:549ba18ddd81 | 8367 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
| mbed_official | 126:549ba18ddd81 | 8368 | |
| mbed_official | 126:549ba18ddd81 | 8369 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) |
| mbed_official | 126:549ba18ddd81 | 8370 | |
| mbed_official | 126:549ba18ddd81 | 8371 | #define CLEAR_REG(REG) ((REG) = (0x0)) |
| mbed_official | 126:549ba18ddd81 | 8372 | |
| mbed_official | 126:549ba18ddd81 | 8373 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
| mbed_official | 126:549ba18ddd81 | 8374 | |
| mbed_official | 126:549ba18ddd81 | 8375 | #define READ_REG(REG) ((REG)) |
| mbed_official | 126:549ba18ddd81 | 8376 | |
| mbed_official | 126:549ba18ddd81 | 8377 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
| mbed_official | 126:549ba18ddd81 | 8378 | |
| mbed_official | 126:549ba18ddd81 | 8379 | /** |
| mbed_official | 126:549ba18ddd81 | 8380 | * @} |
| mbed_official | 126:549ba18ddd81 | 8381 | */ |
| mbed_official | 126:549ba18ddd81 | 8382 | |
| mbed_official | 126:549ba18ddd81 | 8383 | #ifdef __cplusplus |
| mbed_official | 126:549ba18ddd81 | 8384 | } |
| mbed_official | 126:549ba18ddd81 | 8385 | #endif /* __cplusplus */ |
| mbed_official | 126:549ba18ddd81 | 8386 | |
| mbed_official | 126:549ba18ddd81 | 8387 | #endif /* __STM32F10x_H */ |
| mbed_official | 126:549ba18ddd81 | 8388 | |
| mbed_official | 126:549ba18ddd81 | 8389 | /** |
| mbed_official | 126:549ba18ddd81 | 8390 | * @} |
| mbed_official | 126:549ba18ddd81 | 8391 | */ |
| mbed_official | 126:549ba18ddd81 | 8392 | |
| mbed_official | 126:549ba18ddd81 | 8393 | /** |
| mbed_official | 126:549ba18ddd81 | 8394 | * @} |
| mbed_official | 126:549ba18ddd81 | 8395 | */ |
| mbed_official | 126:549ba18ddd81 | 8396 | |
| mbed_official | 126:549ba18ddd81 | 8397 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |