shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_rcc.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
130:1dec54e4aec3 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 130:1dec54e4aec3 1 /**
mbed_official 130:1dec54e4aec3 2 ******************************************************************************
mbed_official 130:1dec54e4aec3 3 * @file stm32f0xx_rcc.c
mbed_official 130:1dec54e4aec3 4 * @author MCD Application Team
mbed_official 130:1dec54e4aec3 5 * @version V1.3.0
mbed_official 130:1dec54e4aec3 6 * @date 16-January-2014
mbed_official 130:1dec54e4aec3 7 * @brief This file provides firmware functions to manage the following
mbed_official 130:1dec54e4aec3 8 * functionalities of the Reset and clock control (RCC) peripheral:
mbed_official 130:1dec54e4aec3 9 * + Internal/external clocks, PLL, CSS and MCO configuration
mbed_official 130:1dec54e4aec3 10 * + System, AHB and APB busses clocks configuration
mbed_official 130:1dec54e4aec3 11 * + Peripheral clocks configuration
mbed_official 130:1dec54e4aec3 12 * + Interrupts and flags management
mbed_official 130:1dec54e4aec3 13 *
mbed_official 130:1dec54e4aec3 14 @verbatim
mbed_official 130:1dec54e4aec3 15
mbed_official 130:1dec54e4aec3 16 ===============================================================================
mbed_official 130:1dec54e4aec3 17 ##### RCC specific features #####
mbed_official 130:1dec54e4aec3 18 ===============================================================================
mbed_official 130:1dec54e4aec3 19 [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
mbed_official 130:1dec54e4aec3 20 all peripherals are off except internal SRAM, Flash and SWD.
mbed_official 130:1dec54e4aec3 21 (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official 130:1dec54e4aec3 22 all peripherals mapped on these busses are running at HSI speed.
mbed_official 130:1dec54e4aec3 23 (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official 130:1dec54e4aec3 24 (#) All GPIOs are in input floating state, except the SWD pins which
mbed_official 130:1dec54e4aec3 25 are assigned to be used for debug purpose.
mbed_official 130:1dec54e4aec3 26 [..] Once the device started from reset, the user application has to:
mbed_official 130:1dec54e4aec3 27 (#) Configure the clock source to be used to drive the System clock
mbed_official 130:1dec54e4aec3 28 (if the application needs higher frequency/performance)
mbed_official 130:1dec54e4aec3 29 (#) Configure the System clock frequency and Flash settings
mbed_official 130:1dec54e4aec3 30 (#) Configure the AHB and APB busses prescalers
mbed_official 130:1dec54e4aec3 31 (#) Enable the clock for the peripheral(s) to be used
mbed_official 130:1dec54e4aec3 32 (#) Configure the clock source(s) for peripherals which clocks are not
mbed_official 130:1dec54e4aec3 33 derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
mbed_official 130:1dec54e4aec3 34
mbed_official 130:1dec54e4aec3 35 @endverbatim
mbed_official 130:1dec54e4aec3 36
mbed_official 130:1dec54e4aec3 37 ******************************************************************************
mbed_official 130:1dec54e4aec3 38 * @attention
mbed_official 130:1dec54e4aec3 39 *
mbed_official 130:1dec54e4aec3 40 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 130:1dec54e4aec3 41 *
mbed_official 130:1dec54e4aec3 42 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 130:1dec54e4aec3 43 * are permitted provided that the following conditions are met:
mbed_official 130:1dec54e4aec3 44 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 130:1dec54e4aec3 45 * this list of conditions and the following disclaimer.
mbed_official 130:1dec54e4aec3 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 130:1dec54e4aec3 47 * this list of conditions and the following disclaimer in the documentation
mbed_official 130:1dec54e4aec3 48 * and/or other materials provided with the distribution.
mbed_official 130:1dec54e4aec3 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 130:1dec54e4aec3 50 * may be used to endorse or promote products derived from this software
mbed_official 130:1dec54e4aec3 51 * without specific prior written permission.
mbed_official 130:1dec54e4aec3 52 *
mbed_official 130:1dec54e4aec3 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 130:1dec54e4aec3 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 130:1dec54e4aec3 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 130:1dec54e4aec3 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 130:1dec54e4aec3 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 130:1dec54e4aec3 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 130:1dec54e4aec3 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 130:1dec54e4aec3 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 130:1dec54e4aec3 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 130:1dec54e4aec3 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 130:1dec54e4aec3 63 *
mbed_official 130:1dec54e4aec3 64 ******************************************************************************
mbed_official 130:1dec54e4aec3 65 */
mbed_official 130:1dec54e4aec3 66
mbed_official 130:1dec54e4aec3 67 /* Includes ------------------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 68 #include "stm32f0xx_rcc.h"
mbed_official 130:1dec54e4aec3 69
mbed_official 130:1dec54e4aec3 70 /** @addtogroup STM32F0xx_StdPeriph_Driver
mbed_official 130:1dec54e4aec3 71 * @{
mbed_official 130:1dec54e4aec3 72 */
mbed_official 130:1dec54e4aec3 73
mbed_official 130:1dec54e4aec3 74 /** @defgroup RCC
mbed_official 130:1dec54e4aec3 75 * @brief RCC driver modules
mbed_official 130:1dec54e4aec3 76 * @{
mbed_official 130:1dec54e4aec3 77 */
mbed_official 130:1dec54e4aec3 78
mbed_official 130:1dec54e4aec3 79 /* Private typedef -----------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 80 /* Private define ------------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 81
mbed_official 130:1dec54e4aec3 82 /* ---------------------- RCC registers mask -------------------------------- */
mbed_official 130:1dec54e4aec3 83 /* RCC Flag Mask */
mbed_official 130:1dec54e4aec3 84 #define FLAG_MASK ((uint8_t)0x1F)
mbed_official 130:1dec54e4aec3 85
mbed_official 130:1dec54e4aec3 86 /* CR register byte 2 (Bits[23:16]) base address */
mbed_official 130:1dec54e4aec3 87 #define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
mbed_official 130:1dec54e4aec3 88
mbed_official 130:1dec54e4aec3 89 /* CFGR register byte 3 (Bits[31:23]) base address */
mbed_official 130:1dec54e4aec3 90 #define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
mbed_official 130:1dec54e4aec3 91
mbed_official 130:1dec54e4aec3 92 /* CIR register byte 1 (Bits[15:8]) base address */
mbed_official 130:1dec54e4aec3 93 #define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009)
mbed_official 130:1dec54e4aec3 94
mbed_official 130:1dec54e4aec3 95 /* CIR register byte 2 (Bits[23:16]) base address */
mbed_official 130:1dec54e4aec3 96 #define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)
mbed_official 130:1dec54e4aec3 97
mbed_official 130:1dec54e4aec3 98 /* Private macro -------------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 99 /* Private variables ---------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 100 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 130:1dec54e4aec3 101
mbed_official 130:1dec54e4aec3 102 /* Private function prototypes -----------------------------------------------*/
mbed_official 130:1dec54e4aec3 103 /* Private functions ---------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 104
mbed_official 130:1dec54e4aec3 105 /** @defgroup RCC_Private_Functions
mbed_official 130:1dec54e4aec3 106 * @{
mbed_official 130:1dec54e4aec3 107 */
mbed_official 130:1dec54e4aec3 108
mbed_official 130:1dec54e4aec3 109 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official 130:1dec54e4aec3 110 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official 130:1dec54e4aec3 111 *
mbed_official 130:1dec54e4aec3 112 @verbatim
mbed_official 130:1dec54e4aec3 113 ===============================================================================
mbed_official 130:1dec54e4aec3 114 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
mbed_official 130:1dec54e4aec3 115 ===============================================================================
mbed_official 130:1dec54e4aec3 116 [..] This section provides functions allowing to configure the internal/external clocks,
mbed_official 130:1dec54e4aec3 117 PLL, CSS and MCO.
mbed_official 130:1dec54e4aec3 118 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
mbed_official 130:1dec54e4aec3 119 or through the PLL as System clock source.
mbed_official 130:1dec54e4aec3 120 The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
mbed_official 130:1dec54e4aec3 121 (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
mbed_official 130:1dec54e4aec3 122 the ADC peripheral.
mbed_official 130:1dec54e4aec3 123 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
mbed_official 130:1dec54e4aec3 124 clock source.
mbed_official 130:1dec54e4aec3 125 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
mbed_official 130:1dec54e4aec3 126 through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official 130:1dec54e4aec3 127 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official 130:1dec54e4aec3 128 LSE can be used also to clock the USART and CEC peripherals.
mbed_official 130:1dec54e4aec3 129 (#) PLL (clocked by HSI or HSE), for System clock.
mbed_official 130:1dec54e4aec3 130 (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
mbed_official 130:1dec54e4aec3 131 (HSE used directly or through PLL as System clock source), the System clock
mbed_official 130:1dec54e4aec3 132 is automatically switched to HSI and an interrupt is generated if enabled.
mbed_official 130:1dec54e4aec3 133 The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt)
mbed_official 130:1dec54e4aec3 134 exception vector.
mbed_official 130:1dec54e4aec3 135 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
mbed_official 130:1dec54e4aec3 136 HSE, LSE or PLL (divided by 2) clock on PA8 pin.
mbed_official 130:1dec54e4aec3 137
mbed_official 130:1dec54e4aec3 138 @endverbatim
mbed_official 130:1dec54e4aec3 139 * @{
mbed_official 130:1dec54e4aec3 140 */
mbed_official 130:1dec54e4aec3 141
mbed_official 130:1dec54e4aec3 142 /**
mbed_official 130:1dec54e4aec3 143 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 130:1dec54e4aec3 144 * @note The default reset state of the clock configuration is given below:
mbed_official 130:1dec54e4aec3 145 * @note HSI ON and used as system clock source
mbed_official 130:1dec54e4aec3 146 * @note HSI14, HSE and PLL OFF
mbed_official 130:1dec54e4aec3 147 * @note AHB, APB prescaler set to 1.
mbed_official 130:1dec54e4aec3 148 * @note CSS and MCO OFF
mbed_official 130:1dec54e4aec3 149 * @note All interrupts disabled
mbed_official 130:1dec54e4aec3 150 * @note However, this function doesn't modify the configuration of the
mbed_official 130:1dec54e4aec3 151 * @note Peripheral clocks
mbed_official 130:1dec54e4aec3 152 * @note LSI, LSE and RTC clocks
mbed_official 130:1dec54e4aec3 153 * @param None
mbed_official 130:1dec54e4aec3 154 * @retval None
mbed_official 130:1dec54e4aec3 155 */
mbed_official 130:1dec54e4aec3 156 void RCC_DeInit(void)
mbed_official 130:1dec54e4aec3 157 {
mbed_official 130:1dec54e4aec3 158 /* Set HSION bit */
mbed_official 130:1dec54e4aec3 159 RCC->CR |= (uint32_t)0x00000001;
mbed_official 130:1dec54e4aec3 160
mbed_official 130:1dec54e4aec3 161 #if defined (STM32F051)
mbed_official 130:1dec54e4aec3 162 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
mbed_official 130:1dec54e4aec3 163 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 130:1dec54e4aec3 164 #else
mbed_official 130:1dec54e4aec3 165 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official 130:1dec54e4aec3 166 RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official 130:1dec54e4aec3 167 #endif /* STM32F051 */
mbed_official 130:1dec54e4aec3 168
mbed_official 130:1dec54e4aec3 169 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 130:1dec54e4aec3 170 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 130:1dec54e4aec3 171
mbed_official 130:1dec54e4aec3 172 /* Reset HSEBYP bit */
mbed_official 130:1dec54e4aec3 173 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 130:1dec54e4aec3 174
mbed_official 130:1dec54e4aec3 175 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 130:1dec54e4aec3 176 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 130:1dec54e4aec3 177
mbed_official 130:1dec54e4aec3 178 /* Reset PREDIV1[3:0] bits */
mbed_official 130:1dec54e4aec3 179 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 130:1dec54e4aec3 180
mbed_official 130:1dec54e4aec3 181 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
mbed_official 130:1dec54e4aec3 182 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
mbed_official 130:1dec54e4aec3 183
mbed_official 130:1dec54e4aec3 184 /* Reset HSI14 bit */
mbed_official 130:1dec54e4aec3 185 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 130:1dec54e4aec3 186
mbed_official 130:1dec54e4aec3 187 /* Disable all interrupts */
mbed_official 130:1dec54e4aec3 188 RCC->CIR = 0x00000000;
mbed_official 130:1dec54e4aec3 189 }
mbed_official 130:1dec54e4aec3 190
mbed_official 130:1dec54e4aec3 191 /**
mbed_official 130:1dec54e4aec3 192 * @brief Configures the External High Speed oscillator (HSE).
mbed_official 130:1dec54e4aec3 193 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official 130:1dec54e4aec3 194 * software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official 130:1dec54e4aec3 195 * is stable and can be used to clock the PLL and/or system clock.
mbed_official 130:1dec54e4aec3 196 * @note HSE state can not be changed if it is used directly or through the
mbed_official 130:1dec54e4aec3 197 * PLL as system clock. In this case, you have to select another source
mbed_official 130:1dec54e4aec3 198 * of the system clock then change the HSE state (ex. disable it).
mbed_official 130:1dec54e4aec3 199 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 200 * @note This function resets the CSSON bit, so if the Clock security system(CSS)
mbed_official 130:1dec54e4aec3 201 * was previously enabled you have to enable it again after calling this
mbed_official 130:1dec54e4aec3 202 * function.
mbed_official 130:1dec54e4aec3 203 * @param RCC_HSE: specifies the new state of the HSE.
mbed_official 130:1dec54e4aec3 204 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 205 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official 130:1dec54e4aec3 206 * 6 HSE oscillator clock cycles.
mbed_official 130:1dec54e4aec3 207 * @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official 130:1dec54e4aec3 208 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
mbed_official 130:1dec54e4aec3 209 * @retval None
mbed_official 130:1dec54e4aec3 210 */
mbed_official 130:1dec54e4aec3 211 void RCC_HSEConfig(uint8_t RCC_HSE)
mbed_official 130:1dec54e4aec3 212 {
mbed_official 130:1dec54e4aec3 213 /* Check the parameters */
mbed_official 130:1dec54e4aec3 214 assert_param(IS_RCC_HSE(RCC_HSE));
mbed_official 130:1dec54e4aec3 215
mbed_official 130:1dec54e4aec3 216 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
mbed_official 130:1dec54e4aec3 217 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
mbed_official 130:1dec54e4aec3 218
mbed_official 130:1dec54e4aec3 219 /* Set the new HSE configuration -------------------------------------------*/
mbed_official 130:1dec54e4aec3 220 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
mbed_official 130:1dec54e4aec3 221
mbed_official 130:1dec54e4aec3 222 }
mbed_official 130:1dec54e4aec3 223
mbed_official 130:1dec54e4aec3 224 /**
mbed_official 130:1dec54e4aec3 225 * @brief Waits for HSE start-up.
mbed_official 130:1dec54e4aec3 226 * @note This function waits on HSERDY flag to be set and return SUCCESS if
mbed_official 130:1dec54e4aec3 227 * this flag is set, otherwise returns ERROR if the timeout is reached
mbed_official 130:1dec54e4aec3 228 * and this flag is not set. The timeout value is defined by the constant
mbed_official 130:1dec54e4aec3 229 * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
mbed_official 130:1dec54e4aec3 230 * on the HSE crystal used in your application.
mbed_official 130:1dec54e4aec3 231 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 232 * @param None
mbed_official 130:1dec54e4aec3 233 * @retval An ErrorStatus enumeration value:
mbed_official 130:1dec54e4aec3 234 * - SUCCESS: HSE oscillator is stable and ready to use
mbed_official 130:1dec54e4aec3 235 * - ERROR: HSE oscillator not yet ready
mbed_official 130:1dec54e4aec3 236 */
mbed_official 130:1dec54e4aec3 237 ErrorStatus RCC_WaitForHSEStartUp(void)
mbed_official 130:1dec54e4aec3 238 {
mbed_official 130:1dec54e4aec3 239 __IO uint32_t StartUpCounter = 0;
mbed_official 130:1dec54e4aec3 240 ErrorStatus status = ERROR;
mbed_official 130:1dec54e4aec3 241 FlagStatus HSEStatus = RESET;
mbed_official 130:1dec54e4aec3 242
mbed_official 130:1dec54e4aec3 243 /* Wait till HSE is ready and if timeout is reached exit */
mbed_official 130:1dec54e4aec3 244 do
mbed_official 130:1dec54e4aec3 245 {
mbed_official 130:1dec54e4aec3 246 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
mbed_official 130:1dec54e4aec3 247 StartUpCounter++;
mbed_official 130:1dec54e4aec3 248 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
mbed_official 130:1dec54e4aec3 249
mbed_official 130:1dec54e4aec3 250 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
mbed_official 130:1dec54e4aec3 251 {
mbed_official 130:1dec54e4aec3 252 status = SUCCESS;
mbed_official 130:1dec54e4aec3 253 }
mbed_official 130:1dec54e4aec3 254 else
mbed_official 130:1dec54e4aec3 255 {
mbed_official 130:1dec54e4aec3 256 status = ERROR;
mbed_official 130:1dec54e4aec3 257 }
mbed_official 130:1dec54e4aec3 258 return (status);
mbed_official 130:1dec54e4aec3 259 }
mbed_official 130:1dec54e4aec3 260
mbed_official 130:1dec54e4aec3 261 /**
mbed_official 130:1dec54e4aec3 262 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
mbed_official 130:1dec54e4aec3 263 * @note The calibration is used to compensate for the variations in voltage
mbed_official 130:1dec54e4aec3 264 * and temperature that influence the frequency of the internal HSI RC.
mbed_official 130:1dec54e4aec3 265 * Refer to the Application Note AN4067 for more details on how to
mbed_official 130:1dec54e4aec3 266 * calibrate the HSI.
mbed_official 130:1dec54e4aec3 267 * @param HSICalibrationValue: specifies the HSI calibration trimming value.
mbed_official 130:1dec54e4aec3 268 * This parameter must be a number between 0 and 0x1F.
mbed_official 130:1dec54e4aec3 269 * @retval None
mbed_official 130:1dec54e4aec3 270 */
mbed_official 130:1dec54e4aec3 271 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
mbed_official 130:1dec54e4aec3 272 {
mbed_official 130:1dec54e4aec3 273 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 274
mbed_official 130:1dec54e4aec3 275 /* Check the parameters */
mbed_official 130:1dec54e4aec3 276 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
mbed_official 130:1dec54e4aec3 277
mbed_official 130:1dec54e4aec3 278 tmpreg = RCC->CR;
mbed_official 130:1dec54e4aec3 279
mbed_official 130:1dec54e4aec3 280 /* Clear HSITRIM[4:0] bits */
mbed_official 130:1dec54e4aec3 281 tmpreg &= ~RCC_CR_HSITRIM;
mbed_official 130:1dec54e4aec3 282
mbed_official 130:1dec54e4aec3 283 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
mbed_official 130:1dec54e4aec3 284 tmpreg |= (uint32_t)HSICalibrationValue << 3;
mbed_official 130:1dec54e4aec3 285
mbed_official 130:1dec54e4aec3 286 /* Store the new value */
mbed_official 130:1dec54e4aec3 287 RCC->CR = tmpreg;
mbed_official 130:1dec54e4aec3 288 }
mbed_official 130:1dec54e4aec3 289
mbed_official 130:1dec54e4aec3 290 /**
mbed_official 130:1dec54e4aec3 291 * @brief Enables or disables the Internal High Speed oscillator (HSI).
mbed_official 130:1dec54e4aec3 292 * @note After enabling the HSI, the application software should wait on
mbed_official 130:1dec54e4aec3 293 * HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official 130:1dec54e4aec3 294 * be used to clock the PLL and/or system clock.
mbed_official 130:1dec54e4aec3 295 * @note HSI can not be stopped if it is used directly or through the PLL
mbed_official 130:1dec54e4aec3 296 * as system clock. In this case, you have to select another source
mbed_official 130:1dec54e4aec3 297 * of the system clock then stop the HSI.
mbed_official 130:1dec54e4aec3 298 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 299 * @param NewState: new state of the HSI.
mbed_official 130:1dec54e4aec3 300 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 301 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official 130:1dec54e4aec3 302 * clock cycles.
mbed_official 130:1dec54e4aec3 303 * @retval None
mbed_official 130:1dec54e4aec3 304 */
mbed_official 130:1dec54e4aec3 305 void RCC_HSICmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 306 {
mbed_official 130:1dec54e4aec3 307 /* Check the parameters */
mbed_official 130:1dec54e4aec3 308 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 309
mbed_official 130:1dec54e4aec3 310 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 311 {
mbed_official 130:1dec54e4aec3 312 RCC->CR |= RCC_CR_HSION;
mbed_official 130:1dec54e4aec3 313 }
mbed_official 130:1dec54e4aec3 314 else
mbed_official 130:1dec54e4aec3 315 {
mbed_official 130:1dec54e4aec3 316 RCC->CR &= ~RCC_CR_HSION;
mbed_official 130:1dec54e4aec3 317 }
mbed_official 130:1dec54e4aec3 318 }
mbed_official 130:1dec54e4aec3 319
mbed_official 130:1dec54e4aec3 320 /**
mbed_official 130:1dec54e4aec3 321 * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14)
mbed_official 130:1dec54e4aec3 322 * calibration value.
mbed_official 130:1dec54e4aec3 323 * @note The calibration is used to compensate for the variations in voltage
mbed_official 130:1dec54e4aec3 324 * and temperature that influence the frequency of the internal HSI RC.
mbed_official 130:1dec54e4aec3 325 * Refer to the Application Note AN4067 for more details on how to
mbed_official 130:1dec54e4aec3 326 * calibrate the HSI14.
mbed_official 130:1dec54e4aec3 327 * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
mbed_official 130:1dec54e4aec3 328 * This parameter must be a number between 0 and 0x1F.
mbed_official 130:1dec54e4aec3 329 * @retval None
mbed_official 130:1dec54e4aec3 330 */
mbed_official 130:1dec54e4aec3 331 void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
mbed_official 130:1dec54e4aec3 332 {
mbed_official 130:1dec54e4aec3 333 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 334
mbed_official 130:1dec54e4aec3 335 /* Check the parameters */
mbed_official 130:1dec54e4aec3 336 assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
mbed_official 130:1dec54e4aec3 337
mbed_official 130:1dec54e4aec3 338 tmpreg = RCC->CR2;
mbed_official 130:1dec54e4aec3 339
mbed_official 130:1dec54e4aec3 340 /* Clear HSI14TRIM[4:0] bits */
mbed_official 130:1dec54e4aec3 341 tmpreg &= ~RCC_CR2_HSI14TRIM;
mbed_official 130:1dec54e4aec3 342
mbed_official 130:1dec54e4aec3 343 /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
mbed_official 130:1dec54e4aec3 344 tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
mbed_official 130:1dec54e4aec3 345
mbed_official 130:1dec54e4aec3 346 /* Store the new value */
mbed_official 130:1dec54e4aec3 347 RCC->CR2 = tmpreg;
mbed_official 130:1dec54e4aec3 348 }
mbed_official 130:1dec54e4aec3 349
mbed_official 130:1dec54e4aec3 350 /**
mbed_official 130:1dec54e4aec3 351 * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14).
mbed_official 130:1dec54e4aec3 352 * @note After enabling the HSI14, the application software should wait on
mbed_official 130:1dec54e4aec3 353 * HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official 130:1dec54e4aec3 354 * be used to clock the ADC.
mbed_official 130:1dec54e4aec3 355 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 356 * @param NewState: new state of the HSI14.
mbed_official 130:1dec54e4aec3 357 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 358 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
mbed_official 130:1dec54e4aec3 359 * clock cycles.
mbed_official 130:1dec54e4aec3 360 * @retval None
mbed_official 130:1dec54e4aec3 361 */
mbed_official 130:1dec54e4aec3 362 void RCC_HSI14Cmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 363 {
mbed_official 130:1dec54e4aec3 364 /* Check the parameters */
mbed_official 130:1dec54e4aec3 365 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 366
mbed_official 130:1dec54e4aec3 367 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 368 {
mbed_official 130:1dec54e4aec3 369 RCC->CR2 |= RCC_CR2_HSI14ON;
mbed_official 130:1dec54e4aec3 370 }
mbed_official 130:1dec54e4aec3 371 else
mbed_official 130:1dec54e4aec3 372 {
mbed_official 130:1dec54e4aec3 373 RCC->CR2 &= ~RCC_CR2_HSI14ON;
mbed_official 130:1dec54e4aec3 374 }
mbed_official 130:1dec54e4aec3 375 }
mbed_official 130:1dec54e4aec3 376
mbed_official 130:1dec54e4aec3 377 /**
mbed_official 130:1dec54e4aec3 378 * @brief Enables or disables the Internal High Speed oscillator request from ADC.
mbed_official 130:1dec54e4aec3 379 * @param NewState: new state of the HSI14 ADC request.
mbed_official 130:1dec54e4aec3 380 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 381 * @retval None
mbed_official 130:1dec54e4aec3 382 */
mbed_official 130:1dec54e4aec3 383 void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 384 {
mbed_official 130:1dec54e4aec3 385 /* Check the parameters */
mbed_official 130:1dec54e4aec3 386 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 387
mbed_official 130:1dec54e4aec3 388 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 389 {
mbed_official 130:1dec54e4aec3 390 RCC->CR2 &= ~RCC_CR2_HSI14DIS;
mbed_official 130:1dec54e4aec3 391 }
mbed_official 130:1dec54e4aec3 392 else
mbed_official 130:1dec54e4aec3 393 {
mbed_official 130:1dec54e4aec3 394 RCC->CR2 |= RCC_CR2_HSI14DIS;
mbed_official 130:1dec54e4aec3 395 }
mbed_official 130:1dec54e4aec3 396 }
mbed_official 130:1dec54e4aec3 397
mbed_official 130:1dec54e4aec3 398 /**
mbed_official 130:1dec54e4aec3 399 * @brief Configures the External Low Speed oscillator (LSE).
mbed_official 130:1dec54e4aec3 400 * @note As the LSE is in the Backup domain and write access is denied to this
mbed_official 130:1dec54e4aec3 401 * domain after reset, you have to enable write access using
mbed_official 130:1dec54e4aec3 402 * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
mbed_official 130:1dec54e4aec3 403 * (to be done once after reset).
mbed_official 130:1dec54e4aec3 404 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
mbed_official 130:1dec54e4aec3 405 * software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official 130:1dec54e4aec3 406 * is stable and can be used to clock the RTC.
mbed_official 130:1dec54e4aec3 407 * @param RCC_LSE: specifies the new state of the LSE.
mbed_official 130:1dec54e4aec3 408 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 409 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official 130:1dec54e4aec3 410 * 6 LSE oscillator clock cycles.
mbed_official 130:1dec54e4aec3 411 * @arg RCC_LSE_ON: turn ON the LSE oscillator
mbed_official 130:1dec54e4aec3 412 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
mbed_official 130:1dec54e4aec3 413 * @retval None
mbed_official 130:1dec54e4aec3 414 */
mbed_official 130:1dec54e4aec3 415 void RCC_LSEConfig(uint32_t RCC_LSE)
mbed_official 130:1dec54e4aec3 416 {
mbed_official 130:1dec54e4aec3 417 /* Check the parameters */
mbed_official 130:1dec54e4aec3 418 assert_param(IS_RCC_LSE(RCC_LSE));
mbed_official 130:1dec54e4aec3 419
mbed_official 130:1dec54e4aec3 420 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
mbed_official 130:1dec54e4aec3 421 /* Reset LSEON bit */
mbed_official 130:1dec54e4aec3 422 RCC->BDCR &= ~(RCC_BDCR_LSEON);
mbed_official 130:1dec54e4aec3 423
mbed_official 130:1dec54e4aec3 424 /* Reset LSEBYP bit */
mbed_official 130:1dec54e4aec3 425 RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
mbed_official 130:1dec54e4aec3 426
mbed_official 130:1dec54e4aec3 427 /* Configure LSE */
mbed_official 130:1dec54e4aec3 428 RCC->BDCR |= RCC_LSE;
mbed_official 130:1dec54e4aec3 429 }
mbed_official 130:1dec54e4aec3 430
mbed_official 130:1dec54e4aec3 431 /**
mbed_official 130:1dec54e4aec3 432 * @brief Configures the External Low Speed oscillator (LSE) drive capability.
mbed_official 130:1dec54e4aec3 433 * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
mbed_official 130:1dec54e4aec3 434 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 435 * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
mbed_official 130:1dec54e4aec3 436 * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
mbed_official 130:1dec54e4aec3 437 * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
mbed_official 130:1dec54e4aec3 438 * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
mbed_official 130:1dec54e4aec3 439 * @retval None
mbed_official 130:1dec54e4aec3 440 */
mbed_official 130:1dec54e4aec3 441 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
mbed_official 130:1dec54e4aec3 442 {
mbed_official 130:1dec54e4aec3 443 /* Check the parameters */
mbed_official 130:1dec54e4aec3 444 assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
mbed_official 130:1dec54e4aec3 445
mbed_official 130:1dec54e4aec3 446 /* Clear LSEDRV[1:0] bits */
mbed_official 130:1dec54e4aec3 447 RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
mbed_official 130:1dec54e4aec3 448
mbed_official 130:1dec54e4aec3 449 /* Set the LSE Drive */
mbed_official 130:1dec54e4aec3 450 RCC->BDCR |= RCC_LSEDrive;
mbed_official 130:1dec54e4aec3 451 }
mbed_official 130:1dec54e4aec3 452
mbed_official 130:1dec54e4aec3 453 /**
mbed_official 130:1dec54e4aec3 454 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
mbed_official 130:1dec54e4aec3 455 * @note After enabling the LSI, the application software should wait on
mbed_official 130:1dec54e4aec3 456 * LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official 130:1dec54e4aec3 457 * be used to clock the IWDG and/or the RTC.
mbed_official 130:1dec54e4aec3 458 * @note LSI can not be disabled if the IWDG is running.
mbed_official 130:1dec54e4aec3 459 * @param NewState: new state of the LSI.
mbed_official 130:1dec54e4aec3 460 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 461 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official 130:1dec54e4aec3 462 * clock cycles.
mbed_official 130:1dec54e4aec3 463 * @retval None
mbed_official 130:1dec54e4aec3 464 */
mbed_official 130:1dec54e4aec3 465 void RCC_LSICmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 466 {
mbed_official 130:1dec54e4aec3 467 /* Check the parameters */
mbed_official 130:1dec54e4aec3 468 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 469
mbed_official 130:1dec54e4aec3 470 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 471 {
mbed_official 130:1dec54e4aec3 472 RCC->CSR |= RCC_CSR_LSION;
mbed_official 130:1dec54e4aec3 473 }
mbed_official 130:1dec54e4aec3 474 else
mbed_official 130:1dec54e4aec3 475 {
mbed_official 130:1dec54e4aec3 476 RCC->CSR &= ~RCC_CSR_LSION;
mbed_official 130:1dec54e4aec3 477 }
mbed_official 130:1dec54e4aec3 478 }
mbed_official 130:1dec54e4aec3 479
mbed_official 130:1dec54e4aec3 480 /**
mbed_official 130:1dec54e4aec3 481 * @brief Configures the PLL clock source and multiplication factor.
mbed_official 130:1dec54e4aec3 482 * @note This function must be used only when the PLL is disabled.
mbed_official 130:1dec54e4aec3 483 *
mbed_official 130:1dec54e4aec3 484 * @param RCC_PLLSource: specifies the PLL entry clock source.
mbed_official 130:1dec54e4aec3 485 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 486 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
mbed_official 130:1dec54e4aec3 487 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
mbed_official 130:1dec54e4aec3 488 * @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 489 * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 490 * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
mbed_official 130:1dec54e4aec3 491 * PLL source).
mbed_official 130:1dec54e4aec3 492 *
mbed_official 130:1dec54e4aec3 493 * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
mbed_official 130:1dec54e4aec3 494 * This parameter can be RCC_PLLMul_x where x:[2,16]
mbed_official 130:1dec54e4aec3 495 *
mbed_official 130:1dec54e4aec3 496 * @retval None
mbed_official 130:1dec54e4aec3 497 */
mbed_official 130:1dec54e4aec3 498 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
mbed_official 130:1dec54e4aec3 499 {
mbed_official 130:1dec54e4aec3 500 /* Check the parameters */
mbed_official 130:1dec54e4aec3 501 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
mbed_official 130:1dec54e4aec3 502 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
mbed_official 130:1dec54e4aec3 503
mbed_official 130:1dec54e4aec3 504 /* Clear PLL Source [16] and Multiplier [21:18] bits */
mbed_official 130:1dec54e4aec3 505 RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
mbed_official 130:1dec54e4aec3 506
mbed_official 130:1dec54e4aec3 507 /* Set the PLL Source and Multiplier */
mbed_official 130:1dec54e4aec3 508 RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
mbed_official 130:1dec54e4aec3 509 }
mbed_official 130:1dec54e4aec3 510
mbed_official 130:1dec54e4aec3 511 /**
mbed_official 130:1dec54e4aec3 512 * @brief Enables or disables the PLL.
mbed_official 130:1dec54e4aec3 513 * @note After enabling the PLL, the application software should wait on
mbed_official 130:1dec54e4aec3 514 * PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official 130:1dec54e4aec3 515 * be used as system clock source.
mbed_official 130:1dec54e4aec3 516 * @note The PLL can not be disabled if it is used as system clock source
mbed_official 130:1dec54e4aec3 517 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 518 * @param NewState: new state of the PLL.
mbed_official 130:1dec54e4aec3 519 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 520 * @retval None
mbed_official 130:1dec54e4aec3 521 */
mbed_official 130:1dec54e4aec3 522 void RCC_PLLCmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 523 {
mbed_official 130:1dec54e4aec3 524 /* Check the parameters */
mbed_official 130:1dec54e4aec3 525 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 526
mbed_official 130:1dec54e4aec3 527 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 528 {
mbed_official 130:1dec54e4aec3 529 RCC->CR |= RCC_CR_PLLON;
mbed_official 130:1dec54e4aec3 530 }
mbed_official 130:1dec54e4aec3 531 else
mbed_official 130:1dec54e4aec3 532 {
mbed_official 130:1dec54e4aec3 533 RCC->CR &= ~RCC_CR_PLLON;
mbed_official 130:1dec54e4aec3 534 }
mbed_official 130:1dec54e4aec3 535 }
mbed_official 130:1dec54e4aec3 536
mbed_official 130:1dec54e4aec3 537 /**
mbed_official 130:1dec54e4aec3 538 * @brief Enables or disables the Internal High Speed oscillator for USB (HSI48).
mbed_official 130:1dec54e4aec3 539 * This function is only applicable for STM32F072 devices.
mbed_official 130:1dec54e4aec3 540 * @note After enabling the HSI48, the application software should wait on
mbed_official 130:1dec54e4aec3 541 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
mbed_official 130:1dec54e4aec3 542 * be used to clock the USB.
mbed_official 130:1dec54e4aec3 543 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 544 * @param NewState: new state of the HSI48.
mbed_official 130:1dec54e4aec3 545 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 546 * @retval None
mbed_official 130:1dec54e4aec3 547 */
mbed_official 130:1dec54e4aec3 548 void RCC_HSI48Cmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 549 {
mbed_official 130:1dec54e4aec3 550 /* Check the parameters */
mbed_official 130:1dec54e4aec3 551 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 552
mbed_official 130:1dec54e4aec3 553 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 554 {
mbed_official 130:1dec54e4aec3 555 RCC->CR2 |= RCC_CR2_HSI48ON;
mbed_official 130:1dec54e4aec3 556 }
mbed_official 130:1dec54e4aec3 557 else
mbed_official 130:1dec54e4aec3 558 {
mbed_official 130:1dec54e4aec3 559 RCC->CR2 &= ~RCC_CR2_HSI48ON;
mbed_official 130:1dec54e4aec3 560 }
mbed_official 130:1dec54e4aec3 561 }
mbed_official 130:1dec54e4aec3 562
mbed_official 130:1dec54e4aec3 563 /**
mbed_official 130:1dec54e4aec3 564 * @brief Configures the PREDIV1 division factor.
mbed_official 130:1dec54e4aec3 565 * @note This function must be used only when the PLL is disabled.
mbed_official 130:1dec54e4aec3 566 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
mbed_official 130:1dec54e4aec3 567 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
mbed_official 130:1dec54e4aec3 568 * @retval None
mbed_official 130:1dec54e4aec3 569 */
mbed_official 130:1dec54e4aec3 570 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
mbed_official 130:1dec54e4aec3 571 {
mbed_official 130:1dec54e4aec3 572 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 573
mbed_official 130:1dec54e4aec3 574 /* Check the parameters */
mbed_official 130:1dec54e4aec3 575 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
mbed_official 130:1dec54e4aec3 576
mbed_official 130:1dec54e4aec3 577 tmpreg = RCC->CFGR2;
mbed_official 130:1dec54e4aec3 578 /* Clear PREDIV1[3:0] bits */
mbed_official 130:1dec54e4aec3 579 tmpreg &= ~(RCC_CFGR2_PREDIV1);
mbed_official 130:1dec54e4aec3 580 /* Set the PREDIV1 division factor */
mbed_official 130:1dec54e4aec3 581 tmpreg |= RCC_PREDIV1_Div;
mbed_official 130:1dec54e4aec3 582 /* Store the new value */
mbed_official 130:1dec54e4aec3 583 RCC->CFGR2 = tmpreg;
mbed_official 130:1dec54e4aec3 584 }
mbed_official 130:1dec54e4aec3 585
mbed_official 130:1dec54e4aec3 586 /**
mbed_official 130:1dec54e4aec3 587 * @brief Enables or disables the Clock Security System.
mbed_official 130:1dec54e4aec3 588 * @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official 130:1dec54e4aec3 589 * is automatically disabled and an interrupt is generated to inform the
mbed_official 130:1dec54e4aec3 590 * software about the failure (Clock Security System Interrupt, CSSI),
mbed_official 130:1dec54e4aec3 591 * allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official 130:1dec54e4aec3 592 * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
mbed_official 130:1dec54e4aec3 593 * @param NewState: new state of the Clock Security System.
mbed_official 130:1dec54e4aec3 594 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 595 * @retval None
mbed_official 130:1dec54e4aec3 596 */
mbed_official 130:1dec54e4aec3 597 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 598 {
mbed_official 130:1dec54e4aec3 599 /* Check the parameters */
mbed_official 130:1dec54e4aec3 600 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 601
mbed_official 130:1dec54e4aec3 602 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 603 {
mbed_official 130:1dec54e4aec3 604 RCC->CR |= RCC_CR_CSSON;
mbed_official 130:1dec54e4aec3 605 }
mbed_official 130:1dec54e4aec3 606 else
mbed_official 130:1dec54e4aec3 607 {
mbed_official 130:1dec54e4aec3 608 RCC->CR &= ~RCC_CR_CSSON;
mbed_official 130:1dec54e4aec3 609 }
mbed_official 130:1dec54e4aec3 610 }
mbed_official 130:1dec54e4aec3 611
mbed_official 130:1dec54e4aec3 612 #ifdef STM32F051
mbed_official 130:1dec54e4aec3 613 /**
mbed_official 130:1dec54e4aec3 614 * @brief Selects the clock source to output on MCO pin (PA8).
mbed_official 130:1dec54e4aec3 615 * @note PA8 should be configured in alternate function mode.
mbed_official 130:1dec54e4aec3 616 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 130:1dec54e4aec3 617 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 618 * @arg RCC_MCOSource_NoClock: No clock selected.
mbed_official 130:1dec54e4aec3 619 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
mbed_official 130:1dec54e4aec3 620 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
mbed_official 130:1dec54e4aec3 621 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
mbed_official 130:1dec54e4aec3 622 * @arg RCC_MCOSource_SYSCLK: System clock selected.
mbed_official 130:1dec54e4aec3 623 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
mbed_official 130:1dec54e4aec3 624 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
mbed_official 130:1dec54e4aec3 625 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
mbed_official 130:1dec54e4aec3 626 * @retval None
mbed_official 130:1dec54e4aec3 627 */
mbed_official 130:1dec54e4aec3 628 void RCC_MCOConfig(uint8_t RCC_MCOSource)
mbed_official 130:1dec54e4aec3 629 {
mbed_official 130:1dec54e4aec3 630 /* Check the parameters */
mbed_official 130:1dec54e4aec3 631 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official 130:1dec54e4aec3 632
mbed_official 130:1dec54e4aec3 633 /* Select MCO clock source and prescaler */
mbed_official 130:1dec54e4aec3 634 *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource;
mbed_official 130:1dec54e4aec3 635 }
mbed_official 130:1dec54e4aec3 636 #else
mbed_official 130:1dec54e4aec3 637
mbed_official 130:1dec54e4aec3 638 /**
mbed_official 130:1dec54e4aec3 639 * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
mbed_official 130:1dec54e4aec3 640 * prescsaler.
mbed_official 130:1dec54e4aec3 641 * @note PA8 should be configured in alternate function mode.
mbed_official 130:1dec54e4aec3 642 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 130:1dec54e4aec3 643 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 644 * @arg RCC_MCOSource_NoClock: No clock selected.
mbed_official 130:1dec54e4aec3 645 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
mbed_official 130:1dec54e4aec3 646 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
mbed_official 130:1dec54e4aec3 647 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
mbed_official 130:1dec54e4aec3 648 * @arg RCC_MCOSource_SYSCLK: System clock selected.
mbed_official 130:1dec54e4aec3 649 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
mbed_official 130:1dec54e4aec3 650 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
mbed_official 130:1dec54e4aec3 651 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
mbed_official 130:1dec54e4aec3 652 * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
mbed_official 130:1dec54e4aec3 653 * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
mbed_official 130:1dec54e4aec3 654 * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
mbed_official 130:1dec54e4aec3 655 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 656 * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
mbed_official 130:1dec54e4aec3 657 * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
mbed_official 130:1dec54e4aec3 658 * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
mbed_official 130:1dec54e4aec3 659 * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
mbed_official 130:1dec54e4aec3 660 * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
mbed_official 130:1dec54e4aec3 661 * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
mbed_official 130:1dec54e4aec3 662 * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
mbed_official 130:1dec54e4aec3 663 * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
mbed_official 130:1dec54e4aec3 664 * @retval None
mbed_official 130:1dec54e4aec3 665 */
mbed_official 130:1dec54e4aec3 666 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
mbed_official 130:1dec54e4aec3 667 {
mbed_official 130:1dec54e4aec3 668 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 669
mbed_official 130:1dec54e4aec3 670 /* Check the parameters */
mbed_official 130:1dec54e4aec3 671 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official 130:1dec54e4aec3 672 assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
mbed_official 130:1dec54e4aec3 673
mbed_official 130:1dec54e4aec3 674 /* Get CFGR value */
mbed_official 130:1dec54e4aec3 675 tmpreg = RCC->CFGR;
mbed_official 130:1dec54e4aec3 676 /* Clear MCOPRE[2:0] bits */
mbed_official 130:1dec54e4aec3 677 tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
mbed_official 130:1dec54e4aec3 678 /* Set the RCC_MCOSource and RCC_MCOPrescaler */
mbed_official 130:1dec54e4aec3 679 tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24));
mbed_official 130:1dec54e4aec3 680 /* Store the new value */
mbed_official 130:1dec54e4aec3 681 RCC->CFGR = tmpreg;
mbed_official 130:1dec54e4aec3 682 }
mbed_official 130:1dec54e4aec3 683 #endif /* STM32F072 */
mbed_official 130:1dec54e4aec3 684
mbed_official 130:1dec54e4aec3 685 /**
mbed_official 130:1dec54e4aec3 686 * @}
mbed_official 130:1dec54e4aec3 687 */
mbed_official 130:1dec54e4aec3 688
mbed_official 130:1dec54e4aec3 689 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
mbed_official 130:1dec54e4aec3 690 * @brief System, AHB and APB busses clocks configuration functions
mbed_official 130:1dec54e4aec3 691 *
mbed_official 130:1dec54e4aec3 692 @verbatim
mbed_official 130:1dec54e4aec3 693 ===============================================================================
mbed_official 130:1dec54e4aec3 694 ##### System, AHB and APB busses clocks configuration functions #####
mbed_official 130:1dec54e4aec3 695 ===============================================================================
mbed_official 130:1dec54e4aec3 696
mbed_official 130:1dec54e4aec3 697 [..] This section provide functions allowing to configure the System, AHB and
mbed_official 130:1dec54e4aec3 698 APB busses clocks.
mbed_official 130:1dec54e4aec3 699 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official 130:1dec54e4aec3 700 HSE and PLL.
mbed_official 130:1dec54e4aec3 701 The AHB clock (HCLK) is derived from System clock through configurable prescaler
mbed_official 130:1dec54e4aec3 702 and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
mbed_official 130:1dec54e4aec3 703 and APB (PCLK) clocks are derived from AHB clock through
mbed_official 130:1dec54e4aec3 704 configurable prescalers and used to clock the peripherals mapped on these busses.
mbed_official 130:1dec54e4aec3 705 You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
mbed_official 130:1dec54e4aec3 706
mbed_official 130:1dec54e4aec3 707 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official 130:1dec54e4aec3 708 (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
mbed_official 130:1dec54e4aec3 709 programmable prescaler: 2 or 4).
mbed_official 130:1dec54e4aec3 710 (+@) The CEC clock which is derived from LSE or HSI divided by 244.
mbed_official 130:1dec54e4aec3 711 (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
mbed_official 130:1dec54e4aec3 712 (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
mbed_official 130:1dec54e4aec3 713 (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
mbed_official 130:1dec54e4aec3 714 divided by a programmable prescaler).
mbed_official 130:1dec54e4aec3 715 The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
mbed_official 130:1dec54e4aec3 716 clock frequency.
mbed_official 130:1dec54e4aec3 717 (+@) IWDG clock which is always the LSI clock.
mbed_official 130:1dec54e4aec3 718
mbed_official 130:1dec54e4aec3 719 (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
mbed_official 130:1dec54e4aec3 720 Depending on the maximum frequency, the FLASH wait states (WS) should be
mbed_official 130:1dec54e4aec3 721 adapted accordingly:
mbed_official 130:1dec54e4aec3 722 +--------------------------------------------- +
mbed_official 130:1dec54e4aec3 723 | Wait states | HCLK clock frequency (MHz) |
mbed_official 130:1dec54e4aec3 724 |---------------|------------------------------|
mbed_official 130:1dec54e4aec3 725 |0WS(1CPU cycle)| 0 < HCLK <= 24 |
mbed_official 130:1dec54e4aec3 726 |---------------|------------------------------|
mbed_official 130:1dec54e4aec3 727 |1WS(2CPU cycle)| 24 < HCLK <= 48 |
mbed_official 130:1dec54e4aec3 728 +----------------------------------------------+
mbed_official 130:1dec54e4aec3 729
mbed_official 130:1dec54e4aec3 730 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
mbed_official 130:1dec54e4aec3 731 prefetch is disabled.
mbed_official 130:1dec54e4aec3 732
mbed_official 130:1dec54e4aec3 733 [..] It is recommended to use the following software sequences to tune the number
mbed_official 130:1dec54e4aec3 734 of wait states needed to access the Flash memory with the CPU frequency (HCLK).
mbed_official 130:1dec54e4aec3 735 (+) Increasing the CPU frequency
mbed_official 130:1dec54e4aec3 736 (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
mbed_official 130:1dec54e4aec3 737 function
mbed_official 130:1dec54e4aec3 738 (++) Check that Flash Prefetch buffer activation is taken into account by
mbed_official 130:1dec54e4aec3 739 reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
mbed_official 130:1dec54e4aec3 740 (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
mbed_official 130:1dec54e4aec3 741 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
mbed_official 130:1dec54e4aec3 742 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official 130:1dec54e4aec3 743 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
mbed_official 130:1dec54e4aec3 744 (++) Check that the new CPU clock source is taken into account by reading
mbed_official 130:1dec54e4aec3 745 the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official 130:1dec54e4aec3 746 (+) Decreasing the CPU frequency
mbed_official 130:1dec54e4aec3 747 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official 130:1dec54e4aec3 748 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
mbed_official 130:1dec54e4aec3 749 (++) Check that the new CPU clock source is taken into account by reading
mbed_official 130:1dec54e4aec3 750 the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official 130:1dec54e4aec3 751 (++) Program the new number of WS, using "FLASH_SetLatency()" function
mbed_official 130:1dec54e4aec3 752 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
mbed_official 130:1dec54e4aec3 753 (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
mbed_official 130:1dec54e4aec3 754 function
mbed_official 130:1dec54e4aec3 755 (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
mbed_official 130:1dec54e4aec3 756 using the FLASH_GetPrefetchBufferStatus() function.
mbed_official 130:1dec54e4aec3 757
mbed_official 130:1dec54e4aec3 758 @endverbatim
mbed_official 130:1dec54e4aec3 759 * @{
mbed_official 130:1dec54e4aec3 760 */
mbed_official 130:1dec54e4aec3 761
mbed_official 130:1dec54e4aec3 762 /**
mbed_official 130:1dec54e4aec3 763 * @brief Configures the system clock (SYSCLK).
mbed_official 130:1dec54e4aec3 764 * @note The HSI is used (enabled by hardware) as system clock source after
mbed_official 130:1dec54e4aec3 765 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 130:1dec54e4aec3 766 * of failure of the HSE used directly or indirectly as system clock
mbed_official 130:1dec54e4aec3 767 * (if the Clock Security System CSS is enabled).
mbed_official 130:1dec54e4aec3 768 * @note A switch from one clock source to another occurs only if the target
mbed_official 130:1dec54e4aec3 769 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 130:1dec54e4aec3 770 * If a clock source which is not yet ready is selected, the switch will
mbed_official 130:1dec54e4aec3 771 * occur when the clock source will be ready.
mbed_official 130:1dec54e4aec3 772 * You can use RCC_GetSYSCLKSource() function to know which clock is
mbed_official 130:1dec54e4aec3 773 * currently used as system clock source.
mbed_official 130:1dec54e4aec3 774 * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
mbed_official 130:1dec54e4aec3 775 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 776 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
mbed_official 130:1dec54e4aec3 777 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
mbed_official 130:1dec54e4aec3 778 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
mbed_official 130:1dec54e4aec3 779 * @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 780 * @retval None
mbed_official 130:1dec54e4aec3 781 */
mbed_official 130:1dec54e4aec3 782 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
mbed_official 130:1dec54e4aec3 783 {
mbed_official 130:1dec54e4aec3 784 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 785
mbed_official 130:1dec54e4aec3 786 /* Check the parameters */
mbed_official 130:1dec54e4aec3 787 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
mbed_official 130:1dec54e4aec3 788
mbed_official 130:1dec54e4aec3 789 tmpreg = RCC->CFGR;
mbed_official 130:1dec54e4aec3 790
mbed_official 130:1dec54e4aec3 791 /* Clear SW[1:0] bits */
mbed_official 130:1dec54e4aec3 792 tmpreg &= ~RCC_CFGR_SW;
mbed_official 130:1dec54e4aec3 793
mbed_official 130:1dec54e4aec3 794 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
mbed_official 130:1dec54e4aec3 795 tmpreg |= RCC_SYSCLKSource;
mbed_official 130:1dec54e4aec3 796
mbed_official 130:1dec54e4aec3 797 /* Store the new value */
mbed_official 130:1dec54e4aec3 798 RCC->CFGR = tmpreg;
mbed_official 130:1dec54e4aec3 799 }
mbed_official 130:1dec54e4aec3 800
mbed_official 130:1dec54e4aec3 801 /**
mbed_official 130:1dec54e4aec3 802 * @brief Returns the clock source used as system clock.
mbed_official 130:1dec54e4aec3 803 * @param None
mbed_official 130:1dec54e4aec3 804 * @retval The clock source used as system clock. The returned value can be one
mbed_official 130:1dec54e4aec3 805 * of the following values:
mbed_official 130:1dec54e4aec3 806 * - 0x00: HSI used as system clock
mbed_official 130:1dec54e4aec3 807 * - 0x04: HSE used as system clock
mbed_official 130:1dec54e4aec3 808 * - 0x08: PLL used as system clock
mbed_official 130:1dec54e4aec3 809 * - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 810 */
mbed_official 130:1dec54e4aec3 811 uint8_t RCC_GetSYSCLKSource(void)
mbed_official 130:1dec54e4aec3 812 {
mbed_official 130:1dec54e4aec3 813 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
mbed_official 130:1dec54e4aec3 814 }
mbed_official 130:1dec54e4aec3 815
mbed_official 130:1dec54e4aec3 816 /**
mbed_official 130:1dec54e4aec3 817 * @brief Configures the AHB clock (HCLK).
mbed_official 130:1dec54e4aec3 818 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
mbed_official 130:1dec54e4aec3 819 * the system clock (SYSCLK).
mbed_official 130:1dec54e4aec3 820 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 821 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
mbed_official 130:1dec54e4aec3 822 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
mbed_official 130:1dec54e4aec3 823 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
mbed_official 130:1dec54e4aec3 824 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
mbed_official 130:1dec54e4aec3 825 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
mbed_official 130:1dec54e4aec3 826 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
mbed_official 130:1dec54e4aec3 827 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
mbed_official 130:1dec54e4aec3 828 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
mbed_official 130:1dec54e4aec3 829 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
mbed_official 130:1dec54e4aec3 830 * @retval None
mbed_official 130:1dec54e4aec3 831 */
mbed_official 130:1dec54e4aec3 832 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
mbed_official 130:1dec54e4aec3 833 {
mbed_official 130:1dec54e4aec3 834 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 835
mbed_official 130:1dec54e4aec3 836 /* Check the parameters */
mbed_official 130:1dec54e4aec3 837 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
mbed_official 130:1dec54e4aec3 838
mbed_official 130:1dec54e4aec3 839 tmpreg = RCC->CFGR;
mbed_official 130:1dec54e4aec3 840
mbed_official 130:1dec54e4aec3 841 /* Clear HPRE[3:0] bits */
mbed_official 130:1dec54e4aec3 842 tmpreg &= ~RCC_CFGR_HPRE;
mbed_official 130:1dec54e4aec3 843
mbed_official 130:1dec54e4aec3 844 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
mbed_official 130:1dec54e4aec3 845 tmpreg |= RCC_SYSCLK;
mbed_official 130:1dec54e4aec3 846
mbed_official 130:1dec54e4aec3 847 /* Store the new value */
mbed_official 130:1dec54e4aec3 848 RCC->CFGR = tmpreg;
mbed_official 130:1dec54e4aec3 849 }
mbed_official 130:1dec54e4aec3 850
mbed_official 130:1dec54e4aec3 851 /**
mbed_official 130:1dec54e4aec3 852 * @brief Configures the APB clock (PCLK).
mbed_official 130:1dec54e4aec3 853 * @param RCC_HCLK: defines the APB clock divider. This clock is derived from
mbed_official 130:1dec54e4aec3 854 * the AHB clock (HCLK).
mbed_official 130:1dec54e4aec3 855 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 856 * @arg RCC_HCLK_Div1: APB clock = HCLK
mbed_official 130:1dec54e4aec3 857 * @arg RCC_HCLK_Div2: APB clock = HCLK/2
mbed_official 130:1dec54e4aec3 858 * @arg RCC_HCLK_Div4: APB clock = HCLK/4
mbed_official 130:1dec54e4aec3 859 * @arg RCC_HCLK_Div8: APB clock = HCLK/8
mbed_official 130:1dec54e4aec3 860 * @arg RCC_HCLK_Div16: APB clock = HCLK/16
mbed_official 130:1dec54e4aec3 861 * @retval None
mbed_official 130:1dec54e4aec3 862 */
mbed_official 130:1dec54e4aec3 863 void RCC_PCLKConfig(uint32_t RCC_HCLK)
mbed_official 130:1dec54e4aec3 864 {
mbed_official 130:1dec54e4aec3 865 uint32_t tmpreg = 0;
mbed_official 130:1dec54e4aec3 866
mbed_official 130:1dec54e4aec3 867 /* Check the parameters */
mbed_official 130:1dec54e4aec3 868 assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official 130:1dec54e4aec3 869
mbed_official 130:1dec54e4aec3 870 tmpreg = RCC->CFGR;
mbed_official 130:1dec54e4aec3 871
mbed_official 130:1dec54e4aec3 872 /* Clear PPRE[2:0] bits */
mbed_official 130:1dec54e4aec3 873 tmpreg &= ~RCC_CFGR_PPRE;
mbed_official 130:1dec54e4aec3 874
mbed_official 130:1dec54e4aec3 875 /* Set PPRE[2:0] bits according to RCC_HCLK value */
mbed_official 130:1dec54e4aec3 876 tmpreg |= RCC_HCLK;
mbed_official 130:1dec54e4aec3 877
mbed_official 130:1dec54e4aec3 878 /* Store the new value */
mbed_official 130:1dec54e4aec3 879 RCC->CFGR = tmpreg;
mbed_official 130:1dec54e4aec3 880 }
mbed_official 130:1dec54e4aec3 881
mbed_official 130:1dec54e4aec3 882 /**
mbed_official 130:1dec54e4aec3 883 * @brief Configures the ADC clock (ADCCLK).
mbed_official 130:1dec54e4aec3 884 * @note This function is obsolete.
mbed_official 130:1dec54e4aec3 885 * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
mbed_official 130:1dec54e4aec3 886 * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived
mbed_official 130:1dec54e4aec3 887 * from the HSI14 or APB clock (PCLK).
mbed_official 130:1dec54e4aec3 888 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 889 * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
mbed_official 130:1dec54e4aec3 890 * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
mbed_official 130:1dec54e4aec3 891 * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4
mbed_official 130:1dec54e4aec3 892 * @retval None
mbed_official 130:1dec54e4aec3 893 */
mbed_official 130:1dec54e4aec3 894 void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
mbed_official 130:1dec54e4aec3 895 {
mbed_official 130:1dec54e4aec3 896 /* Check the parameters */
mbed_official 130:1dec54e4aec3 897 assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
mbed_official 130:1dec54e4aec3 898
mbed_official 130:1dec54e4aec3 899 /* Clear ADCPRE bit */
mbed_official 130:1dec54e4aec3 900 RCC->CFGR &= ~RCC_CFGR_ADCPRE;
mbed_official 130:1dec54e4aec3 901 /* Set ADCPRE bits according to RCC_PCLK value */
mbed_official 130:1dec54e4aec3 902 RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
mbed_official 130:1dec54e4aec3 903
mbed_official 130:1dec54e4aec3 904 /* Clear ADCSW bit */
mbed_official 130:1dec54e4aec3 905 RCC->CFGR3 &= ~RCC_CFGR3_ADCSW;
mbed_official 130:1dec54e4aec3 906 /* Set ADCSW bits according to RCC_ADCCLK value */
mbed_official 130:1dec54e4aec3 907 RCC->CFGR3 |= RCC_ADCCLK >> 16;
mbed_official 130:1dec54e4aec3 908 }
mbed_official 130:1dec54e4aec3 909
mbed_official 130:1dec54e4aec3 910 /**
mbed_official 130:1dec54e4aec3 911 * @brief Configures the CEC clock (CECCLK).
mbed_official 130:1dec54e4aec3 912 * @param RCC_CECCLK: defines the CEC clock source. This clock is derived
mbed_official 130:1dec54e4aec3 913 * from the HSI or LSE clock.
mbed_official 130:1dec54e4aec3 914 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 915 * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
mbed_official 130:1dec54e4aec3 916 * @arg RCC_CECCLK_LSE: CEC clock = LSE
mbed_official 130:1dec54e4aec3 917 * @retval None
mbed_official 130:1dec54e4aec3 918 */
mbed_official 130:1dec54e4aec3 919 void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
mbed_official 130:1dec54e4aec3 920 {
mbed_official 130:1dec54e4aec3 921 /* Check the parameters */
mbed_official 130:1dec54e4aec3 922 assert_param(IS_RCC_CECCLK(RCC_CECCLK));
mbed_official 130:1dec54e4aec3 923
mbed_official 130:1dec54e4aec3 924 /* Clear CECSW bit */
mbed_official 130:1dec54e4aec3 925 RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
mbed_official 130:1dec54e4aec3 926 /* Set CECSW bits according to RCC_CECCLK value */
mbed_official 130:1dec54e4aec3 927 RCC->CFGR3 |= RCC_CECCLK;
mbed_official 130:1dec54e4aec3 928 }
mbed_official 130:1dec54e4aec3 929
mbed_official 130:1dec54e4aec3 930 /**
mbed_official 130:1dec54e4aec3 931 * @brief Configures the I2C1 clock (I2C1CLK).
mbed_official 130:1dec54e4aec3 932 * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
mbed_official 130:1dec54e4aec3 933 * from the HSI or System clock.
mbed_official 130:1dec54e4aec3 934 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 935 * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
mbed_official 130:1dec54e4aec3 936 * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
mbed_official 130:1dec54e4aec3 937 * @retval None
mbed_official 130:1dec54e4aec3 938 */
mbed_official 130:1dec54e4aec3 939 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
mbed_official 130:1dec54e4aec3 940 {
mbed_official 130:1dec54e4aec3 941 /* Check the parameters */
mbed_official 130:1dec54e4aec3 942 assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
mbed_official 130:1dec54e4aec3 943
mbed_official 130:1dec54e4aec3 944 /* Clear I2CSW bit */
mbed_official 130:1dec54e4aec3 945 RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
mbed_official 130:1dec54e4aec3 946 /* Set I2CSW bits according to RCC_I2CCLK value */
mbed_official 130:1dec54e4aec3 947 RCC->CFGR3 |= RCC_I2CCLK;
mbed_official 130:1dec54e4aec3 948 }
mbed_official 130:1dec54e4aec3 949
mbed_official 130:1dec54e4aec3 950 /**
mbed_official 130:1dec54e4aec3 951 * @brief Configures the USART1 clock (USART1CLK).
mbed_official 130:1dec54e4aec3 952 * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
mbed_official 130:1dec54e4aec3 953 * from the HSI or System clock.
mbed_official 130:1dec54e4aec3 954 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 955 * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
mbed_official 130:1dec54e4aec3 956 * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
mbed_official 130:1dec54e4aec3 957 * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
mbed_official 130:1dec54e4aec3 958 * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
mbed_official 130:1dec54e4aec3 959 * @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 960 * @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 961 * @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 962 * @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 963 * @retval None
mbed_official 130:1dec54e4aec3 964 */
mbed_official 130:1dec54e4aec3 965 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
mbed_official 130:1dec54e4aec3 966 {
mbed_official 130:1dec54e4aec3 967 uint32_t tmp = 0;
mbed_official 130:1dec54e4aec3 968
mbed_official 130:1dec54e4aec3 969 /* Check the parameters */
mbed_official 130:1dec54e4aec3 970 assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
mbed_official 130:1dec54e4aec3 971
mbed_official 130:1dec54e4aec3 972 /* Get USART index */
mbed_official 130:1dec54e4aec3 973 tmp = (RCC_USARTCLK >> 28);
mbed_official 130:1dec54e4aec3 974
mbed_official 130:1dec54e4aec3 975 /* Clear USARTSW[1:0] bit */
mbed_official 130:1dec54e4aec3 976 if (tmp == (uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 977 {
mbed_official 130:1dec54e4aec3 978 /* Clear USART1SW[1:0] bit */
mbed_official 130:1dec54e4aec3 979 RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
mbed_official 130:1dec54e4aec3 980 }
mbed_official 130:1dec54e4aec3 981 else
mbed_official 130:1dec54e4aec3 982 {
mbed_official 130:1dec54e4aec3 983 /* Clear USART2SW[1:0] bit */
mbed_official 130:1dec54e4aec3 984 RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
mbed_official 130:1dec54e4aec3 985 }
mbed_official 130:1dec54e4aec3 986
mbed_official 130:1dec54e4aec3 987 /* Set USARTxSW bits according to RCC_USARTCLK value */
mbed_official 130:1dec54e4aec3 988 RCC->CFGR3 |= RCC_USARTCLK;
mbed_official 130:1dec54e4aec3 989 }
mbed_official 130:1dec54e4aec3 990
mbed_official 130:1dec54e4aec3 991 /**
mbed_official 130:1dec54e4aec3 992 * @brief Configures the USB clock (USBCLK).
mbed_official 130:1dec54e4aec3 993 * This function is only applicable for STM32F072 devices.
mbed_official 130:1dec54e4aec3 994 * @param RCC_USBCLK: defines the USB clock source. This clock is derived
mbed_official 130:1dec54e4aec3 995 * from the HSI48 or system clock.
mbed_official 130:1dec54e4aec3 996 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 997 * @arg RCC_USBCLK_HSI48: USB clock = HSI48
mbed_official 130:1dec54e4aec3 998 * @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
mbed_official 130:1dec54e4aec3 999 * @retval None
mbed_official 130:1dec54e4aec3 1000 */
mbed_official 130:1dec54e4aec3 1001 void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
mbed_official 130:1dec54e4aec3 1002 {
mbed_official 130:1dec54e4aec3 1003 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1004 assert_param(IS_RCC_USBCLK(RCC_USBCLK));
mbed_official 130:1dec54e4aec3 1005
mbed_official 130:1dec54e4aec3 1006 /* Clear USBSW bit */
mbed_official 130:1dec54e4aec3 1007 RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
mbed_official 130:1dec54e4aec3 1008 /* Set USBSW bits according to RCC_USBCLK value */
mbed_official 130:1dec54e4aec3 1009 RCC->CFGR3 |= RCC_USBCLK;
mbed_official 130:1dec54e4aec3 1010 }
mbed_official 130:1dec54e4aec3 1011
mbed_official 130:1dec54e4aec3 1012 /**
mbed_official 130:1dec54e4aec3 1013 * @brief Returns the frequencies of the System, AHB and APB busses clocks.
mbed_official 130:1dec54e4aec3 1014 * @note The frequency returned by this function is not the real frequency
mbed_official 130:1dec54e4aec3 1015 * in the chip. It is calculated based on the predefined constant and
mbed_official 130:1dec54e4aec3 1016 * the source selected by RCC_SYSCLKConfig():
mbed_official 130:1dec54e4aec3 1017 *
mbed_official 130:1dec54e4aec3 1018 * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
mbed_official 130:1dec54e4aec3 1019 *
mbed_official 130:1dec54e4aec3 1020 * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
mbed_official 130:1dec54e4aec3 1021 *
mbed_official 130:1dec54e4aec3 1022 * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
mbed_official 130:1dec54e4aec3 1023 * or HSI_VALUE(*) multiplied by the PLL factors.
mbed_official 130:1dec54e4aec3 1024 *
mbed_official 130:1dec54e4aec3 1025 * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***)
mbed_official 130:1dec54e4aec3 1026 *
mbed_official 130:1dec54e4aec3 1027 * @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 1028 * 8 MHz) but the real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 1029 * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
mbed_official 130:1dec54e4aec3 1030 *
mbed_official 130:1dec54e4aec3 1031 * @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 1032 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 130:1dec54e4aec3 1033 * frequency of the crystal used. Otherwise, this function may
mbed_official 130:1dec54e4aec3 1034 * return wrong result.
mbed_official 130:1dec54e4aec3 1035 *
mbed_official 130:1dec54e4aec3 1036 * @note (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official 130:1dec54e4aec3 1037 * 48 MHz) but the real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 1038 * in voltage and temperature.
mbed_official 130:1dec54e4aec3 1039 *
mbed_official 130:1dec54e4aec3 1040 * @note The result of this function could be not correct when using fractional
mbed_official 130:1dec54e4aec3 1041 * value for HSE crystal.
mbed_official 130:1dec54e4aec3 1042 *
mbed_official 130:1dec54e4aec3 1043 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
mbed_official 130:1dec54e4aec3 1044 * the clocks frequencies.
mbed_official 130:1dec54e4aec3 1045 *
mbed_official 130:1dec54e4aec3 1046 * @note This function can be used by the user application to compute the
mbed_official 130:1dec54e4aec3 1047 * baudrate for the communication peripherals or configure other parameters.
mbed_official 130:1dec54e4aec3 1048 * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function
mbed_official 130:1dec54e4aec3 1049 * must be called to update the structure's field. Otherwise, any
mbed_official 130:1dec54e4aec3 1050 * configuration based on this function will be incorrect.
mbed_official 130:1dec54e4aec3 1051 *
mbed_official 130:1dec54e4aec3 1052 * @retval None
mbed_official 130:1dec54e4aec3 1053 */
mbed_official 130:1dec54e4aec3 1054 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
mbed_official 130:1dec54e4aec3 1055 {
mbed_official 130:1dec54e4aec3 1056 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
mbed_official 130:1dec54e4aec3 1057
mbed_official 130:1dec54e4aec3 1058 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 1059 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 130:1dec54e4aec3 1060
mbed_official 130:1dec54e4aec3 1061 switch (tmp)
mbed_official 130:1dec54e4aec3 1062 {
mbed_official 130:1dec54e4aec3 1063 case 0x00: /* HSI used as system clock */
mbed_official 130:1dec54e4aec3 1064 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official 130:1dec54e4aec3 1065 break;
mbed_official 130:1dec54e4aec3 1066 case 0x04: /* HSE used as system clock */
mbed_official 130:1dec54e4aec3 1067 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
mbed_official 130:1dec54e4aec3 1068 break;
mbed_official 130:1dec54e4aec3 1069 case 0x08: /* PLL used as system clock */
mbed_official 130:1dec54e4aec3 1070 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 130:1dec54e4aec3 1071 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 130:1dec54e4aec3 1072 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 130:1dec54e4aec3 1073 pllmull = ( pllmull >> 18) + 2;
mbed_official 130:1dec54e4aec3 1074
mbed_official 130:1dec54e4aec3 1075 if (pllsource == 0x00)
mbed_official 130:1dec54e4aec3 1076 {
mbed_official 130:1dec54e4aec3 1077 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 130:1dec54e4aec3 1078 pllclk = (HSI_VALUE >> 1) * pllmull;
mbed_official 130:1dec54e4aec3 1079 }
mbed_official 130:1dec54e4aec3 1080 else
mbed_official 130:1dec54e4aec3 1081 {
mbed_official 130:1dec54e4aec3 1082 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 130:1dec54e4aec3 1083 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 130:1dec54e4aec3 1084 pllclk = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 130:1dec54e4aec3 1085 }
mbed_official 130:1dec54e4aec3 1086 RCC_Clocks->SYSCLK_Frequency = pllclk;
mbed_official 130:1dec54e4aec3 1087 break;
mbed_official 130:1dec54e4aec3 1088 case 0x0C: /* HSI48 used as system clock */
mbed_official 130:1dec54e4aec3 1089 RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
mbed_official 130:1dec54e4aec3 1090 break;
mbed_official 130:1dec54e4aec3 1091 default: /* HSI used as system clock */
mbed_official 130:1dec54e4aec3 1092 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official 130:1dec54e4aec3 1093 break;
mbed_official 130:1dec54e4aec3 1094 }
mbed_official 130:1dec54e4aec3 1095 /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
mbed_official 130:1dec54e4aec3 1096 /* Get HCLK prescaler */
mbed_official 130:1dec54e4aec3 1097 tmp = RCC->CFGR & RCC_CFGR_HPRE;
mbed_official 130:1dec54e4aec3 1098 tmp = tmp >> 4;
mbed_official 130:1dec54e4aec3 1099 presc = APBAHBPrescTable[tmp];
mbed_official 130:1dec54e4aec3 1100 /* HCLK clock frequency */
mbed_official 130:1dec54e4aec3 1101 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
mbed_official 130:1dec54e4aec3 1102
mbed_official 130:1dec54e4aec3 1103 /* Get PCLK prescaler */
mbed_official 130:1dec54e4aec3 1104 tmp = RCC->CFGR & RCC_CFGR_PPRE;
mbed_official 130:1dec54e4aec3 1105 tmp = tmp >> 8;
mbed_official 130:1dec54e4aec3 1106 presc = APBAHBPrescTable[tmp];
mbed_official 130:1dec54e4aec3 1107 /* PCLK clock frequency */
mbed_official 130:1dec54e4aec3 1108 RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official 130:1dec54e4aec3 1109
mbed_official 130:1dec54e4aec3 1110 /* ADCCLK clock frequency */
mbed_official 130:1dec54e4aec3 1111 if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
mbed_official 130:1dec54e4aec3 1112 {
mbed_official 130:1dec54e4aec3 1113 /* ADC Clock is HSI14 Osc. */
mbed_official 130:1dec54e4aec3 1114 RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
mbed_official 130:1dec54e4aec3 1115 }
mbed_official 130:1dec54e4aec3 1116 else
mbed_official 130:1dec54e4aec3 1117 {
mbed_official 130:1dec54e4aec3 1118 if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
mbed_official 130:1dec54e4aec3 1119 {
mbed_official 130:1dec54e4aec3 1120 /* ADC Clock is derived from PCLK/2 */
mbed_official 130:1dec54e4aec3 1121 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
mbed_official 130:1dec54e4aec3 1122 }
mbed_official 130:1dec54e4aec3 1123 else
mbed_official 130:1dec54e4aec3 1124 {
mbed_official 130:1dec54e4aec3 1125 /* ADC Clock is derived from PCLK/4 */
mbed_official 130:1dec54e4aec3 1126 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
mbed_official 130:1dec54e4aec3 1127 }
mbed_official 130:1dec54e4aec3 1128
mbed_official 130:1dec54e4aec3 1129 }
mbed_official 130:1dec54e4aec3 1130
mbed_official 130:1dec54e4aec3 1131 /* CECCLK clock frequency */
mbed_official 130:1dec54e4aec3 1132 if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
mbed_official 130:1dec54e4aec3 1133 {
mbed_official 130:1dec54e4aec3 1134 /* CEC Clock is HSI/244 */
mbed_official 130:1dec54e4aec3 1135 RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
mbed_official 130:1dec54e4aec3 1136 }
mbed_official 130:1dec54e4aec3 1137 else
mbed_official 130:1dec54e4aec3 1138 {
mbed_official 130:1dec54e4aec3 1139 /* CECC Clock is LSE Osc. */
mbed_official 130:1dec54e4aec3 1140 RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
mbed_official 130:1dec54e4aec3 1141 }
mbed_official 130:1dec54e4aec3 1142
mbed_official 130:1dec54e4aec3 1143 /* I2C1CLK clock frequency */
mbed_official 130:1dec54e4aec3 1144 if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
mbed_official 130:1dec54e4aec3 1145 {
mbed_official 130:1dec54e4aec3 1146 /* I2C1 Clock is HSI Osc. */
mbed_official 130:1dec54e4aec3 1147 RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
mbed_official 130:1dec54e4aec3 1148 }
mbed_official 130:1dec54e4aec3 1149 else
mbed_official 130:1dec54e4aec3 1150 {
mbed_official 130:1dec54e4aec3 1151 /* I2C1 Clock is System Clock */
mbed_official 130:1dec54e4aec3 1152 RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 130:1dec54e4aec3 1153 }
mbed_official 130:1dec54e4aec3 1154
mbed_official 130:1dec54e4aec3 1155 /* USART1CLK clock frequency */
mbed_official 130:1dec54e4aec3 1156 if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
mbed_official 130:1dec54e4aec3 1157 {
mbed_official 130:1dec54e4aec3 1158 /* USART1 Clock is PCLK */
mbed_official 130:1dec54e4aec3 1159 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
mbed_official 130:1dec54e4aec3 1160 }
mbed_official 130:1dec54e4aec3 1161 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
mbed_official 130:1dec54e4aec3 1162 {
mbed_official 130:1dec54e4aec3 1163 /* USART1 Clock is System Clock */
mbed_official 130:1dec54e4aec3 1164 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 130:1dec54e4aec3 1165 }
mbed_official 130:1dec54e4aec3 1166 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
mbed_official 130:1dec54e4aec3 1167 {
mbed_official 130:1dec54e4aec3 1168 /* USART1 Clock is LSE Osc. */
mbed_official 130:1dec54e4aec3 1169 RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
mbed_official 130:1dec54e4aec3 1170 }
mbed_official 130:1dec54e4aec3 1171 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
mbed_official 130:1dec54e4aec3 1172 {
mbed_official 130:1dec54e4aec3 1173 /* USART1 Clock is HSI Osc. */
mbed_official 130:1dec54e4aec3 1174 RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
mbed_official 130:1dec54e4aec3 1175 }
mbed_official 130:1dec54e4aec3 1176
mbed_official 130:1dec54e4aec3 1177 /* USART2CLK clock frequency */
mbed_official 130:1dec54e4aec3 1178 if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
mbed_official 130:1dec54e4aec3 1179 {
mbed_official 130:1dec54e4aec3 1180 /* USART Clock is PCLK */
mbed_official 130:1dec54e4aec3 1181 RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
mbed_official 130:1dec54e4aec3 1182 }
mbed_official 130:1dec54e4aec3 1183 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
mbed_official 130:1dec54e4aec3 1184 {
mbed_official 130:1dec54e4aec3 1185 /* USART Clock is System Clock */
mbed_official 130:1dec54e4aec3 1186 RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 130:1dec54e4aec3 1187 }
mbed_official 130:1dec54e4aec3 1188 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
mbed_official 130:1dec54e4aec3 1189 {
mbed_official 130:1dec54e4aec3 1190 /* USART Clock is LSE Osc. */
mbed_official 130:1dec54e4aec3 1191 RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
mbed_official 130:1dec54e4aec3 1192 }
mbed_official 130:1dec54e4aec3 1193 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
mbed_official 130:1dec54e4aec3 1194 {
mbed_official 130:1dec54e4aec3 1195 /* USART Clock is HSI Osc. */
mbed_official 130:1dec54e4aec3 1196 RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
mbed_official 130:1dec54e4aec3 1197 }
mbed_official 130:1dec54e4aec3 1198
mbed_official 130:1dec54e4aec3 1199 /* USBCLK clock frequency */
mbed_official 130:1dec54e4aec3 1200 if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
mbed_official 130:1dec54e4aec3 1201 {
mbed_official 130:1dec54e4aec3 1202 /* USB Clock is HSI48 */
mbed_official 130:1dec54e4aec3 1203 RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
mbed_official 130:1dec54e4aec3 1204 }
mbed_official 130:1dec54e4aec3 1205 else
mbed_official 130:1dec54e4aec3 1206 {
mbed_official 130:1dec54e4aec3 1207 /* USB Clock is PLL clock */
mbed_official 130:1dec54e4aec3 1208 RCC_Clocks->USBCLK_Frequency = pllclk;
mbed_official 130:1dec54e4aec3 1209 }
mbed_official 130:1dec54e4aec3 1210 }
mbed_official 130:1dec54e4aec3 1211
mbed_official 130:1dec54e4aec3 1212 /**
mbed_official 130:1dec54e4aec3 1213 * @}
mbed_official 130:1dec54e4aec3 1214 */
mbed_official 130:1dec54e4aec3 1215
mbed_official 130:1dec54e4aec3 1216 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
mbed_official 130:1dec54e4aec3 1217 * @brief Peripheral clocks configuration functions
mbed_official 130:1dec54e4aec3 1218 *
mbed_official 130:1dec54e4aec3 1219 @verbatim
mbed_official 130:1dec54e4aec3 1220 ===============================================================================
mbed_official 130:1dec54e4aec3 1221 #####Peripheral clocks configuration functions #####
mbed_official 130:1dec54e4aec3 1222 ===============================================================================
mbed_official 130:1dec54e4aec3 1223
mbed_official 130:1dec54e4aec3 1224 [..] This section provide functions allowing to configure the Peripheral clocks.
mbed_official 130:1dec54e4aec3 1225 (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE
mbed_official 130:1dec54e4aec3 1226 divided by 32).
mbed_official 130:1dec54e4aec3 1227 (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
mbed_official 130:1dec54e4aec3 1228 except internal SRAM, Flash and SWD. Before to start using a peripheral you
mbed_official 130:1dec54e4aec3 1229 have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
mbed_official 130:1dec54e4aec3 1230 RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
mbed_official 130:1dec54e4aec3 1231 (#) To reset the peripherals configuration (to the default state after device reset)
mbed_official 130:1dec54e4aec3 1232 you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
mbed_official 130:1dec54e4aec3 1233 RCC_APB1PeriphResetCmd() functions.
mbed_official 130:1dec54e4aec3 1234
mbed_official 130:1dec54e4aec3 1235 @endverbatim
mbed_official 130:1dec54e4aec3 1236 * @{
mbed_official 130:1dec54e4aec3 1237 */
mbed_official 130:1dec54e4aec3 1238
mbed_official 130:1dec54e4aec3 1239 /**
mbed_official 130:1dec54e4aec3 1240 * @brief Configures the RTC clock (RTCCLK).
mbed_official 130:1dec54e4aec3 1241 * @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official 130:1dec54e4aec3 1242 * access is denied to this domain after reset, you have to enable write
mbed_official 130:1dec54e4aec3 1243 * access using PWR_BackupAccessCmd(ENABLE) function before to configure
mbed_official 130:1dec54e4aec3 1244 * the RTC clock source (to be done once after reset).
mbed_official 130:1dec54e4aec3 1245 * @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official 130:1dec54e4aec3 1246 * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
mbed_official 130:1dec54e4aec3 1247 *
mbed_official 130:1dec54e4aec3 1248 * @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official 130:1dec54e4aec3 1249 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 1250 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
mbed_official 130:1dec54e4aec3 1251 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
mbed_official 130:1dec54e4aec3 1252 * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
mbed_official 130:1dec54e4aec3 1253 *
mbed_official 130:1dec54e4aec3 1254 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official 130:1dec54e4aec3 1255 * work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official 130:1dec54e4aec3 1256 * However, when the HSE clock is used as RTC clock source, the RTC
mbed_official 130:1dec54e4aec3 1257 * cannot be used in STOP and STANDBY modes.
mbed_official 130:1dec54e4aec3 1258 *
mbed_official 130:1dec54e4aec3 1259 * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
mbed_official 130:1dec54e4aec3 1260 * RTC clock source).
mbed_official 130:1dec54e4aec3 1261 *
mbed_official 130:1dec54e4aec3 1262 * @retval None
mbed_official 130:1dec54e4aec3 1263 */
mbed_official 130:1dec54e4aec3 1264 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
mbed_official 130:1dec54e4aec3 1265 {
mbed_official 130:1dec54e4aec3 1266 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1267 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
mbed_official 130:1dec54e4aec3 1268
mbed_official 130:1dec54e4aec3 1269 /* Select the RTC clock source */
mbed_official 130:1dec54e4aec3 1270 RCC->BDCR |= RCC_RTCCLKSource;
mbed_official 130:1dec54e4aec3 1271 }
mbed_official 130:1dec54e4aec3 1272
mbed_official 130:1dec54e4aec3 1273 /**
mbed_official 130:1dec54e4aec3 1274 * @brief Enables or disables the RTC clock.
mbed_official 130:1dec54e4aec3 1275 * @note This function must be used only after the RTC clock source was selected
mbed_official 130:1dec54e4aec3 1276 * using the RCC_RTCCLKConfig function.
mbed_official 130:1dec54e4aec3 1277 * @param NewState: new state of the RTC clock.
mbed_official 130:1dec54e4aec3 1278 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1279 * @retval None
mbed_official 130:1dec54e4aec3 1280 */
mbed_official 130:1dec54e4aec3 1281 void RCC_RTCCLKCmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1282 {
mbed_official 130:1dec54e4aec3 1283 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1284 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1285
mbed_official 130:1dec54e4aec3 1286 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1287 {
mbed_official 130:1dec54e4aec3 1288 RCC->BDCR |= RCC_BDCR_RTCEN;
mbed_official 130:1dec54e4aec3 1289 }
mbed_official 130:1dec54e4aec3 1290 else
mbed_official 130:1dec54e4aec3 1291 {
mbed_official 130:1dec54e4aec3 1292 RCC->BDCR &= ~RCC_BDCR_RTCEN;
mbed_official 130:1dec54e4aec3 1293 }
mbed_official 130:1dec54e4aec3 1294 }
mbed_official 130:1dec54e4aec3 1295
mbed_official 130:1dec54e4aec3 1296 /**
mbed_official 130:1dec54e4aec3 1297 * @brief Forces or releases the Backup domain reset.
mbed_official 130:1dec54e4aec3 1298 * @note This function resets the RTC peripheral (including the backup registers)
mbed_official 130:1dec54e4aec3 1299 * and the RTC clock source selection in RCC_BDCR register.
mbed_official 130:1dec54e4aec3 1300 * @param NewState: new state of the Backup domain reset.
mbed_official 130:1dec54e4aec3 1301 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1302 * @retval None
mbed_official 130:1dec54e4aec3 1303 */
mbed_official 130:1dec54e4aec3 1304 void RCC_BackupResetCmd(FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1305 {
mbed_official 130:1dec54e4aec3 1306 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1307 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1308
mbed_official 130:1dec54e4aec3 1309 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1310 {
mbed_official 130:1dec54e4aec3 1311 RCC->BDCR |= RCC_BDCR_BDRST;
mbed_official 130:1dec54e4aec3 1312 }
mbed_official 130:1dec54e4aec3 1313 else
mbed_official 130:1dec54e4aec3 1314 {
mbed_official 130:1dec54e4aec3 1315 RCC->BDCR &= ~RCC_BDCR_BDRST;
mbed_official 130:1dec54e4aec3 1316 }
mbed_official 130:1dec54e4aec3 1317 }
mbed_official 130:1dec54e4aec3 1318
mbed_official 130:1dec54e4aec3 1319 /**
mbed_official 130:1dec54e4aec3 1320 * @brief Enables or disables the AHB peripheral clock.
mbed_official 130:1dec54e4aec3 1321 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 130:1dec54e4aec3 1322 * is disabled and the application software has to enable this clock before
mbed_official 130:1dec54e4aec3 1323 * using it.
mbed_official 130:1dec54e4aec3 1324 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official 130:1dec54e4aec3 1325 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1326 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official 130:1dec54e4aec3 1327 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official 130:1dec54e4aec3 1328 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official 130:1dec54e4aec3 1329 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official 130:1dec54e4aec3 1330 * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1331 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official 130:1dec54e4aec3 1332 * @arg RCC_AHBPeriph_TS: TS clock
mbed_official 130:1dec54e4aec3 1333 * @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official 130:1dec54e4aec3 1334 * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official 130:1dec54e4aec3 1335 * @arg RCC_AHBPeriph_SRAM: SRAM clock
mbed_official 130:1dec54e4aec3 1336 * @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official 130:1dec54e4aec3 1337 * @param NewState: new state of the specified peripheral clock.
mbed_official 130:1dec54e4aec3 1338 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1339 * @retval None
mbed_official 130:1dec54e4aec3 1340 */
mbed_official 130:1dec54e4aec3 1341 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1342 {
mbed_official 130:1dec54e4aec3 1343 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1344 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official 130:1dec54e4aec3 1345 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1346
mbed_official 130:1dec54e4aec3 1347 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1348 {
mbed_official 130:1dec54e4aec3 1349 RCC->AHBENR |= RCC_AHBPeriph;
mbed_official 130:1dec54e4aec3 1350 }
mbed_official 130:1dec54e4aec3 1351 else
mbed_official 130:1dec54e4aec3 1352 {
mbed_official 130:1dec54e4aec3 1353 RCC->AHBENR &= ~RCC_AHBPeriph;
mbed_official 130:1dec54e4aec3 1354 }
mbed_official 130:1dec54e4aec3 1355 }
mbed_official 130:1dec54e4aec3 1356
mbed_official 130:1dec54e4aec3 1357 /**
mbed_official 130:1dec54e4aec3 1358 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
mbed_official 130:1dec54e4aec3 1359 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 130:1dec54e4aec3 1360 * is disabled and the application software has to enable this clock before
mbed_official 130:1dec54e4aec3 1361 * using it.
mbed_official 130:1dec54e4aec3 1362 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official 130:1dec54e4aec3 1363 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1364 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official 130:1dec54e4aec3 1365 * @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official 130:1dec54e4aec3 1366 * @arg RCC_APB2Periph_TIM1: TIM1 clock
mbed_official 130:1dec54e4aec3 1367 * @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official 130:1dec54e4aec3 1368 * @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official 130:1dec54e4aec3 1369 * @arg RCC_APB2Periph_TIM15: TIM15 clock
mbed_official 130:1dec54e4aec3 1370 * @arg RCC_APB2Periph_TIM16: TIM16 clock
mbed_official 130:1dec54e4aec3 1371 * @arg RCC_APB2Periph_TIM17: TIM17 clock
mbed_official 130:1dec54e4aec3 1372 * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
mbed_official 130:1dec54e4aec3 1373 * @param NewState: new state of the specified peripheral clock.
mbed_official 130:1dec54e4aec3 1374 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1375 * @retval None
mbed_official 130:1dec54e4aec3 1376 */
mbed_official 130:1dec54e4aec3 1377 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1378 {
mbed_official 130:1dec54e4aec3 1379 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1380 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 130:1dec54e4aec3 1381 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1382
mbed_official 130:1dec54e4aec3 1383 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1384 {
mbed_official 130:1dec54e4aec3 1385 RCC->APB2ENR |= RCC_APB2Periph;
mbed_official 130:1dec54e4aec3 1386 }
mbed_official 130:1dec54e4aec3 1387 else
mbed_official 130:1dec54e4aec3 1388 {
mbed_official 130:1dec54e4aec3 1389 RCC->APB2ENR &= ~RCC_APB2Periph;
mbed_official 130:1dec54e4aec3 1390 }
mbed_official 130:1dec54e4aec3 1391 }
mbed_official 130:1dec54e4aec3 1392
mbed_official 130:1dec54e4aec3 1393 /**
mbed_official 130:1dec54e4aec3 1394 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
mbed_official 130:1dec54e4aec3 1395 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 130:1dec54e4aec3 1396 * is disabled and the application software has to enable this clock before
mbed_official 130:1dec54e4aec3 1397 * using it.
mbed_official 130:1dec54e4aec3 1398 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official 130:1dec54e4aec3 1399 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1400 * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1401 * @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official 130:1dec54e4aec3 1402 * @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official 130:1dec54e4aec3 1403 * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1404 * @arg RCC_APB1Periph_TIM14: TIM14 clock
mbed_official 130:1dec54e4aec3 1405 * @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official 130:1dec54e4aec3 1406 * @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official 130:1dec54e4aec3 1407 * @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official 130:1dec54e4aec3 1408 * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1409 * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1410 * @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official 130:1dec54e4aec3 1411 * @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official 130:1dec54e4aec3 1412 * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1413 * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1414 * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1415 * @arg RCC_APB1Periph_PWR: PWR clock
mbed_official 130:1dec54e4aec3 1416 * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1417 * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1418 * @param NewState: new state of the specified peripheral clock.
mbed_official 130:1dec54e4aec3 1419 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1420 * @retval None
mbed_official 130:1dec54e4aec3 1421 */
mbed_official 130:1dec54e4aec3 1422 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1423 {
mbed_official 130:1dec54e4aec3 1424 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1425 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 130:1dec54e4aec3 1426 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1427
mbed_official 130:1dec54e4aec3 1428 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1429 {
mbed_official 130:1dec54e4aec3 1430 RCC->APB1ENR |= RCC_APB1Periph;
mbed_official 130:1dec54e4aec3 1431 }
mbed_official 130:1dec54e4aec3 1432 else
mbed_official 130:1dec54e4aec3 1433 {
mbed_official 130:1dec54e4aec3 1434 RCC->APB1ENR &= ~RCC_APB1Periph;
mbed_official 130:1dec54e4aec3 1435 }
mbed_official 130:1dec54e4aec3 1436 }
mbed_official 130:1dec54e4aec3 1437
mbed_official 130:1dec54e4aec3 1438 /**
mbed_official 130:1dec54e4aec3 1439 * @brief Forces or releases AHB peripheral reset.
mbed_official 130:1dec54e4aec3 1440 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
mbed_official 130:1dec54e4aec3 1441 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1442 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official 130:1dec54e4aec3 1443 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official 130:1dec54e4aec3 1444 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official 130:1dec54e4aec3 1445 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official 130:1dec54e4aec3 1446 * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1447 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official 130:1dec54e4aec3 1448 * @arg RCC_AHBPeriph_TS: TS clock
mbed_official 130:1dec54e4aec3 1449 * @param NewState: new state of the specified peripheral reset.
mbed_official 130:1dec54e4aec3 1450 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1451 * @retval None
mbed_official 130:1dec54e4aec3 1452 */
mbed_official 130:1dec54e4aec3 1453 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1454 {
mbed_official 130:1dec54e4aec3 1455 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1456 assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
mbed_official 130:1dec54e4aec3 1457 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1458
mbed_official 130:1dec54e4aec3 1459 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1460 {
mbed_official 130:1dec54e4aec3 1461 RCC->AHBRSTR |= RCC_AHBPeriph;
mbed_official 130:1dec54e4aec3 1462 }
mbed_official 130:1dec54e4aec3 1463 else
mbed_official 130:1dec54e4aec3 1464 {
mbed_official 130:1dec54e4aec3 1465 RCC->AHBRSTR &= ~RCC_AHBPeriph;
mbed_official 130:1dec54e4aec3 1466 }
mbed_official 130:1dec54e4aec3 1467 }
mbed_official 130:1dec54e4aec3 1468
mbed_official 130:1dec54e4aec3 1469 /**
mbed_official 130:1dec54e4aec3 1470 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
mbed_official 130:1dec54e4aec3 1471 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
mbed_official 130:1dec54e4aec3 1472 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1473 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official 130:1dec54e4aec3 1474 * @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official 130:1dec54e4aec3 1475 * @arg RCC_APB2Periph_TIM1: TIM1 clock
mbed_official 130:1dec54e4aec3 1476 * @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official 130:1dec54e4aec3 1477 * @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official 130:1dec54e4aec3 1478 * @arg RCC_APB2Periph_TIM15: TIM15 clock
mbed_official 130:1dec54e4aec3 1479 * @arg RCC_APB2Periph_TIM16: TIM16 clock
mbed_official 130:1dec54e4aec3 1480 * @arg RCC_APB2Periph_TIM17: TIM17 clock
mbed_official 130:1dec54e4aec3 1481 * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
mbed_official 130:1dec54e4aec3 1482 * @param NewState: new state of the specified peripheral reset.
mbed_official 130:1dec54e4aec3 1483 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1484 * @retval None
mbed_official 130:1dec54e4aec3 1485 */
mbed_official 130:1dec54e4aec3 1486 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1487 {
mbed_official 130:1dec54e4aec3 1488 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1489 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 130:1dec54e4aec3 1490 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1491
mbed_official 130:1dec54e4aec3 1492 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1493 {
mbed_official 130:1dec54e4aec3 1494 RCC->APB2RSTR |= RCC_APB2Periph;
mbed_official 130:1dec54e4aec3 1495 }
mbed_official 130:1dec54e4aec3 1496 else
mbed_official 130:1dec54e4aec3 1497 {
mbed_official 130:1dec54e4aec3 1498 RCC->APB2RSTR &= ~RCC_APB2Periph;
mbed_official 130:1dec54e4aec3 1499 }
mbed_official 130:1dec54e4aec3 1500 }
mbed_official 130:1dec54e4aec3 1501
mbed_official 130:1dec54e4aec3 1502 /**
mbed_official 130:1dec54e4aec3 1503 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
mbed_official 130:1dec54e4aec3 1504 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
mbed_official 130:1dec54e4aec3 1505 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1506 * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1507 * @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official 130:1dec54e4aec3 1508 * @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official 130:1dec54e4aec3 1509 * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1510 * @arg RCC_APB1Periph_TIM14: TIM14 clock
mbed_official 130:1dec54e4aec3 1511 * @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official 130:1dec54e4aec3 1512 * @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official 130:1dec54e4aec3 1513 * @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official 130:1dec54e4aec3 1514 * @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official 130:1dec54e4aec3 1515 * @arg RCC_APB1Periph_USART4: USART4 clock
mbed_official 130:1dec54e4aec3 1516 * @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official 130:1dec54e4aec3 1517 * @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official 130:1dec54e4aec3 1518 * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1519 * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1520 * @arg RCC_APB1Periph_CRS: CRS clock, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1521 * @arg RCC_APB1Periph_PWR: PWR clock
mbed_official 130:1dec54e4aec3 1522 * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1523 * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051 and STM32F072 devices
mbed_official 130:1dec54e4aec3 1524 * @param NewState: new state of the specified peripheral clock.
mbed_official 130:1dec54e4aec3 1525 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1526 * @retval None
mbed_official 130:1dec54e4aec3 1527 */
mbed_official 130:1dec54e4aec3 1528 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1529 {
mbed_official 130:1dec54e4aec3 1530 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1531 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 130:1dec54e4aec3 1532 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1533
mbed_official 130:1dec54e4aec3 1534 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1535 {
mbed_official 130:1dec54e4aec3 1536 RCC->APB1RSTR |= RCC_APB1Periph;
mbed_official 130:1dec54e4aec3 1537 }
mbed_official 130:1dec54e4aec3 1538 else
mbed_official 130:1dec54e4aec3 1539 {
mbed_official 130:1dec54e4aec3 1540 RCC->APB1RSTR &= ~RCC_APB1Periph;
mbed_official 130:1dec54e4aec3 1541 }
mbed_official 130:1dec54e4aec3 1542 }
mbed_official 130:1dec54e4aec3 1543
mbed_official 130:1dec54e4aec3 1544 /**
mbed_official 130:1dec54e4aec3 1545 * @}
mbed_official 130:1dec54e4aec3 1546 */
mbed_official 130:1dec54e4aec3 1547
mbed_official 130:1dec54e4aec3 1548 /** @defgroup RCC_Group4 Interrupts and flags management functions
mbed_official 130:1dec54e4aec3 1549 * @brief Interrupts and flags management functions
mbed_official 130:1dec54e4aec3 1550 *
mbed_official 130:1dec54e4aec3 1551 @verbatim
mbed_official 130:1dec54e4aec3 1552 ===============================================================================
mbed_official 130:1dec54e4aec3 1553 ##### Interrupts and flags management functions #####
mbed_official 130:1dec54e4aec3 1554 ===============================================================================
mbed_official 130:1dec54e4aec3 1555 @endverbatim
mbed_official 130:1dec54e4aec3 1556 * @{
mbed_official 130:1dec54e4aec3 1557 */
mbed_official 130:1dec54e4aec3 1558
mbed_official 130:1dec54e4aec3 1559 /**
mbed_official 130:1dec54e4aec3 1560 * @brief Enables or disables the specified RCC interrupts.
mbed_official 130:1dec54e4aec3 1561 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official 130:1dec54e4aec3 1562 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official 130:1dec54e4aec3 1563 * automatically generated. The NMI will be executed indefinitely, and
mbed_official 130:1dec54e4aec3 1564 * since NMI has higher priority than any other IRQ (and main program)
mbed_official 130:1dec54e4aec3 1565 * the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official 130:1dec54e4aec3 1566 * pending bit is cleared.
mbed_official 130:1dec54e4aec3 1567 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
mbed_official 130:1dec54e4aec3 1568 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1569 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 130:1dec54e4aec3 1570 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 130:1dec54e4aec3 1571 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 130:1dec54e4aec3 1572 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 130:1dec54e4aec3 1573 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 130:1dec54e4aec3 1574 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
mbed_official 130:1dec54e4aec3 1575 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1576 * @param NewState: new state of the specified RCC interrupts.
mbed_official 130:1dec54e4aec3 1577 * This parameter can be: ENABLE or DISABLE.
mbed_official 130:1dec54e4aec3 1578 * @retval None
mbed_official 130:1dec54e4aec3 1579 */
mbed_official 130:1dec54e4aec3 1580 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
mbed_official 130:1dec54e4aec3 1581 {
mbed_official 130:1dec54e4aec3 1582 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1583 assert_param(IS_RCC_IT(RCC_IT));
mbed_official 130:1dec54e4aec3 1584 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 130:1dec54e4aec3 1585
mbed_official 130:1dec54e4aec3 1586 if (NewState != DISABLE)
mbed_official 130:1dec54e4aec3 1587 {
mbed_official 130:1dec54e4aec3 1588 /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
mbed_official 130:1dec54e4aec3 1589 *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
mbed_official 130:1dec54e4aec3 1590 }
mbed_official 130:1dec54e4aec3 1591 else
mbed_official 130:1dec54e4aec3 1592 {
mbed_official 130:1dec54e4aec3 1593 /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
mbed_official 130:1dec54e4aec3 1594 *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
mbed_official 130:1dec54e4aec3 1595 }
mbed_official 130:1dec54e4aec3 1596 }
mbed_official 130:1dec54e4aec3 1597
mbed_official 130:1dec54e4aec3 1598 /**
mbed_official 130:1dec54e4aec3 1599 * @brief Checks whether the specified RCC flag is set or not.
mbed_official 130:1dec54e4aec3 1600 * @param RCC_FLAG: specifies the flag to check.
mbed_official 130:1dec54e4aec3 1601 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 1602 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official 130:1dec54e4aec3 1603 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official 130:1dec54e4aec3 1604 * @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official 130:1dec54e4aec3 1605 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official 130:1dec54e4aec3 1606 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official 130:1dec54e4aec3 1607 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official 130:1dec54e4aec3 1608 * @arg RCC_FLAG_PINRST: Pin reset
mbed_official 130:1dec54e4aec3 1609 * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset
mbed_official 130:1dec54e4aec3 1610 * @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official 130:1dec54e4aec3 1611 * @arg RCC_FLAG_SFTRST: Software reset
mbed_official 130:1dec54e4aec3 1612 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official 130:1dec54e4aec3 1613 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official 130:1dec54e4aec3 1614 * @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official 130:1dec54e4aec3 1615 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
mbed_official 130:1dec54e4aec3 1616 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1617 * @retval The new state of RCC_FLAG (SET or RESET).
mbed_official 130:1dec54e4aec3 1618 */
mbed_official 130:1dec54e4aec3 1619 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
mbed_official 130:1dec54e4aec3 1620 {
mbed_official 130:1dec54e4aec3 1621 uint32_t tmp = 0;
mbed_official 130:1dec54e4aec3 1622 uint32_t statusreg = 0;
mbed_official 130:1dec54e4aec3 1623 FlagStatus bitstatus = RESET;
mbed_official 130:1dec54e4aec3 1624
mbed_official 130:1dec54e4aec3 1625 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1626 assert_param(IS_RCC_FLAG(RCC_FLAG));
mbed_official 130:1dec54e4aec3 1627
mbed_official 130:1dec54e4aec3 1628 /* Get the RCC register index */
mbed_official 130:1dec54e4aec3 1629 tmp = RCC_FLAG >> 5;
mbed_official 130:1dec54e4aec3 1630
mbed_official 130:1dec54e4aec3 1631 if (tmp == 0) /* The flag to check is in CR register */
mbed_official 130:1dec54e4aec3 1632 {
mbed_official 130:1dec54e4aec3 1633 statusreg = RCC->CR;
mbed_official 130:1dec54e4aec3 1634 }
mbed_official 130:1dec54e4aec3 1635 else if (tmp == 1) /* The flag to check is in BDCR register */
mbed_official 130:1dec54e4aec3 1636 {
mbed_official 130:1dec54e4aec3 1637 statusreg = RCC->BDCR;
mbed_official 130:1dec54e4aec3 1638 }
mbed_official 130:1dec54e4aec3 1639 else if (tmp == 2) /* The flag to check is in CSR register */
mbed_official 130:1dec54e4aec3 1640 {
mbed_official 130:1dec54e4aec3 1641 statusreg = RCC->CSR;
mbed_official 130:1dec54e4aec3 1642 }
mbed_official 130:1dec54e4aec3 1643 else /* The flag to check is in CR2 register */
mbed_official 130:1dec54e4aec3 1644 {
mbed_official 130:1dec54e4aec3 1645 statusreg = RCC->CR2;
mbed_official 130:1dec54e4aec3 1646 }
mbed_official 130:1dec54e4aec3 1647
mbed_official 130:1dec54e4aec3 1648 /* Get the flag position */
mbed_official 130:1dec54e4aec3 1649 tmp = RCC_FLAG & FLAG_MASK;
mbed_official 130:1dec54e4aec3 1650
mbed_official 130:1dec54e4aec3 1651 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
mbed_official 130:1dec54e4aec3 1652 {
mbed_official 130:1dec54e4aec3 1653 bitstatus = SET;
mbed_official 130:1dec54e4aec3 1654 }
mbed_official 130:1dec54e4aec3 1655 else
mbed_official 130:1dec54e4aec3 1656 {
mbed_official 130:1dec54e4aec3 1657 bitstatus = RESET;
mbed_official 130:1dec54e4aec3 1658 }
mbed_official 130:1dec54e4aec3 1659 /* Return the flag status */
mbed_official 130:1dec54e4aec3 1660 return bitstatus;
mbed_official 130:1dec54e4aec3 1661 }
mbed_official 130:1dec54e4aec3 1662
mbed_official 130:1dec54e4aec3 1663 /**
mbed_official 130:1dec54e4aec3 1664 * @brief Clears the RCC reset flags.
mbed_official 130:1dec54e4aec3 1665 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
mbed_official 130:1dec54e4aec3 1666 * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
mbed_official 130:1dec54e4aec3 1667 * RCC_FLAG_LPWRRST.
mbed_official 130:1dec54e4aec3 1668 * @param None
mbed_official 130:1dec54e4aec3 1669 * @retval None
mbed_official 130:1dec54e4aec3 1670 */
mbed_official 130:1dec54e4aec3 1671 void RCC_ClearFlag(void)
mbed_official 130:1dec54e4aec3 1672 {
mbed_official 130:1dec54e4aec3 1673 /* Set RMVF bit to clear the reset flags */
mbed_official 130:1dec54e4aec3 1674 RCC->CSR |= RCC_CSR_RMVF;
mbed_official 130:1dec54e4aec3 1675 }
mbed_official 130:1dec54e4aec3 1676
mbed_official 130:1dec54e4aec3 1677 /**
mbed_official 130:1dec54e4aec3 1678 * @brief Checks whether the specified RCC interrupt has occurred or not.
mbed_official 130:1dec54e4aec3 1679 * @param RCC_IT: specifies the RCC interrupt source to check.
mbed_official 130:1dec54e4aec3 1680 * This parameter can be one of the following values:
mbed_official 130:1dec54e4aec3 1681 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 130:1dec54e4aec3 1682 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 130:1dec54e4aec3 1683 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 130:1dec54e4aec3 1684 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 130:1dec54e4aec3 1685 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 130:1dec54e4aec3 1686 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
mbed_official 130:1dec54e4aec3 1687 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1688 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 130:1dec54e4aec3 1689 * @retval The new state of RCC_IT (SET or RESET).
mbed_official 130:1dec54e4aec3 1690 */
mbed_official 130:1dec54e4aec3 1691 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
mbed_official 130:1dec54e4aec3 1692 {
mbed_official 130:1dec54e4aec3 1693 ITStatus bitstatus = RESET;
mbed_official 130:1dec54e4aec3 1694
mbed_official 130:1dec54e4aec3 1695 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1696 assert_param(IS_RCC_GET_IT(RCC_IT));
mbed_official 130:1dec54e4aec3 1697
mbed_official 130:1dec54e4aec3 1698 /* Check the status of the specified RCC interrupt */
mbed_official 130:1dec54e4aec3 1699 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
mbed_official 130:1dec54e4aec3 1700 {
mbed_official 130:1dec54e4aec3 1701 bitstatus = SET;
mbed_official 130:1dec54e4aec3 1702 }
mbed_official 130:1dec54e4aec3 1703 else
mbed_official 130:1dec54e4aec3 1704 {
mbed_official 130:1dec54e4aec3 1705 bitstatus = RESET;
mbed_official 130:1dec54e4aec3 1706 }
mbed_official 130:1dec54e4aec3 1707 /* Return the RCC_IT status */
mbed_official 130:1dec54e4aec3 1708 return bitstatus;
mbed_official 130:1dec54e4aec3 1709 }
mbed_official 130:1dec54e4aec3 1710
mbed_official 130:1dec54e4aec3 1711 /**
mbed_official 130:1dec54e4aec3 1712 * @brief Clears the RCC's interrupt pending bits.
mbed_official 130:1dec54e4aec3 1713 * @param RCC_IT: specifies the interrupt pending bit to clear.
mbed_official 130:1dec54e4aec3 1714 * This parameter can be any combination of the following values:
mbed_official 130:1dec54e4aec3 1715 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 130:1dec54e4aec3 1716 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 130:1dec54e4aec3 1717 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 130:1dec54e4aec3 1718 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 130:1dec54e4aec3 1719 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 130:1dec54e4aec3 1720 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
mbed_official 130:1dec54e4aec3 1721 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
mbed_official 130:1dec54e4aec3 1722 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 130:1dec54e4aec3 1723 * @retval None
mbed_official 130:1dec54e4aec3 1724 */
mbed_official 130:1dec54e4aec3 1725 void RCC_ClearITPendingBit(uint8_t RCC_IT)
mbed_official 130:1dec54e4aec3 1726 {
mbed_official 130:1dec54e4aec3 1727 /* Check the parameters */
mbed_official 130:1dec54e4aec3 1728 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
mbed_official 130:1dec54e4aec3 1729
mbed_official 130:1dec54e4aec3 1730 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
mbed_official 130:1dec54e4aec3 1731 pending bits */
mbed_official 130:1dec54e4aec3 1732 *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
mbed_official 130:1dec54e4aec3 1733 }
mbed_official 130:1dec54e4aec3 1734
mbed_official 130:1dec54e4aec3 1735 /**
mbed_official 130:1dec54e4aec3 1736 * @}
mbed_official 130:1dec54e4aec3 1737 */
mbed_official 130:1dec54e4aec3 1738
mbed_official 130:1dec54e4aec3 1739 /**
mbed_official 130:1dec54e4aec3 1740 * @}
mbed_official 130:1dec54e4aec3 1741 */
mbed_official 130:1dec54e4aec3 1742
mbed_official 130:1dec54e4aec3 1743 /**
mbed_official 130:1dec54e4aec3 1744 * @}
mbed_official 130:1dec54e4aec3 1745 */
mbed_official 130:1dec54e4aec3 1746
mbed_official 130:1dec54e4aec3 1747 /**
mbed_official 130:1dec54e4aec3 1748 * @}
mbed_official 130:1dec54e4aec3 1749 */
mbed_official 130:1dec54e4aec3 1750
mbed_official 130:1dec54e4aec3 1751 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/