shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/spi_api.c@265:9632ea190e16, 2014-07-23 (annotated)

Committer:
mbed_official
Date:
Wed Jul 23 21:15:06 2014 +0100
Revision:
265:9632ea190e16
Parent:
251:de9a1e4ffd79
Child:
267:8673334f2cbe
Synchronized with git revision 7a5896cba254ab45829b43f6cef5563706ebba2b



Full URL: https://github.com/mbedmicro/mbed/commit/7a5896cba254ab45829b43f6cef5563706ebba2b/



[MTS_GAMBIT] Add new target support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /* mbed Microcontroller Library
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 ARM Limited
mbed_official 146:f64d43ff0c18 3 *
mbed_official 146:f64d43ff0c18 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 146:f64d43ff0c18 5 * you may not use this file except in compliance with the License.
mbed_official 146:f64d43ff0c18 6 * You may obtain a copy of the License at
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 146:f64d43ff0c18 9 *
mbed_official 146:f64d43ff0c18 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 146:f64d43ff0c18 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 146:f64d43ff0c18 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 146:f64d43ff0c18 13 * See the License for the specific language governing permissions and
mbed_official 146:f64d43ff0c18 14 * limitations under the License.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 227:7bd0639b8911 16 #include <math.h>
mbed_official 227:7bd0639b8911 17 #include "mbed_assert.h"
mbed_official 146:f64d43ff0c18 18
mbed_official 227:7bd0639b8911 19 #include "spi_api.h"
mbed_official 146:f64d43ff0c18 20 #include "cmsis.h"
mbed_official 146:f64d43ff0c18 21 #include "pinmap.h"
mbed_official 251:de9a1e4ffd79 22 #include "error.h"
mbed_official 146:f64d43ff0c18 23 #include "fsl_clock_manager.h"
mbed_official 146:f64d43ff0c18 24 #include "fsl_dspi_hal.h"
mbed_official 265:9632ea190e16 25 #include "PeripheralPins.h"
mbed_official 146:f64d43ff0c18 26
mbed_official 146:f64d43ff0c18 27 static void spi_set_delays(uint32_t instance) {
mbed_official 146:f64d43ff0c18 28 dspi_delay_settings_config_t delay_config;
mbed_official 146:f64d43ff0c18 29 delay_config.pcsToSck = 1; /*!< PCS to SCK delay (CSSCK): initialize the scalar
mbed_official 146:f64d43ff0c18 30 * value to '1' to provide the master with a little
mbed_official 146:f64d43ff0c18 31 * more data-in read setup time.
mbed_official 146:f64d43ff0c18 32 */
mbed_official 146:f64d43ff0c18 33 delay_config.pcsToSckPre = 0; /*!< PCS to SCK delay prescalar (PCSSCK) */
mbed_official 146:f64d43ff0c18 34 delay_config.afterSckPre = 0; /*!< After SCK delay prescalar (PASC)*/
mbed_official 146:f64d43ff0c18 35 delay_config.afterSck = 0; /*!< After SCK delay scalar (ASC)*/
mbed_official 146:f64d43ff0c18 36 delay_config.afterTransferPre = 0; /*!< Delay after transfer prescalar (PDT)*/
mbed_official 146:f64d43ff0c18 37 delay_config.afterTransfer = 0;
mbed_official 146:f64d43ff0c18 38 dspi_hal_configure_delays(instance, kDspiCtar0, &delay_config);
mbed_official 146:f64d43ff0c18 39 }
mbed_official 146:f64d43ff0c18 40
mbed_official 146:f64d43ff0c18 41 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 146:f64d43ff0c18 42 // determine the SPI to use
mbed_official 146:f64d43ff0c18 43 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 146:f64d43ff0c18 44 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 146:f64d43ff0c18 45 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 146:f64d43ff0c18 46 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 146:f64d43ff0c18 47 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
mbed_official 146:f64d43ff0c18 48 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
mbed_official 146:f64d43ff0c18 49
mbed_official 146:f64d43ff0c18 50 obj->instance = pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 51 MBED_ASSERT((int)obj->instance != NC);
mbed_official 146:f64d43ff0c18 52
mbed_official 146:f64d43ff0c18 53 // enable power and clocking
mbed_official 146:f64d43ff0c18 54 clock_manager_set_gate(kClockModuleSPI, obj->instance, true);
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 dspi_hal_disable(obj->instance);
mbed_official 146:f64d43ff0c18 57 // set default format and frequency
mbed_official 146:f64d43ff0c18 58 if (ssel == NC) {
mbed_official 146:f64d43ff0c18 59 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 146:f64d43ff0c18 60 } else {
mbed_official 146:f64d43ff0c18 61 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 146:f64d43ff0c18 62 }
mbed_official 146:f64d43ff0c18 63 spi_set_delays(obj->instance);
mbed_official 146:f64d43ff0c18 64 spi_frequency(obj, 1000000);
mbed_official 146:f64d43ff0c18 65
mbed_official 146:f64d43ff0c18 66 dspi_hal_enable(obj->instance);
mbed_official 146:f64d43ff0c18 67 dspi_hal_start_transfer(obj->instance);
mbed_official 146:f64d43ff0c18 68
mbed_official 146:f64d43ff0c18 69 // pin out the spi pins
mbed_official 146:f64d43ff0c18 70 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 146:f64d43ff0c18 71 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 146:f64d43ff0c18 72 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 146:f64d43ff0c18 73 if (ssel != NC) {
mbed_official 146:f64d43ff0c18 74 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 146:f64d43ff0c18 75 }
mbed_official 146:f64d43ff0c18 76 }
mbed_official 146:f64d43ff0c18 77
mbed_official 146:f64d43ff0c18 78 void spi_free(spi_t *obj) {
mbed_official 146:f64d43ff0c18 79 // [TODO]
mbed_official 146:f64d43ff0c18 80 }
mbed_official 146:f64d43ff0c18 81 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 146:f64d43ff0c18 82 dspi_data_format_config_t config = {0};
mbed_official 146:f64d43ff0c18 83 config.bitsPerFrame = (uint32_t)bits;
mbed_official 146:f64d43ff0c18 84 config.clkPolarity = (mode & 0x2) ? kDspiClockPolarity_ActiveLow : kDspiClockPolarity_ActiveHigh;
mbed_official 146:f64d43ff0c18 85 config.clkPhase = (mode & 0x1) ? kDspiClockPhase_SecondEdge : kDspiClockPhase_FirstEdge;
mbed_official 146:f64d43ff0c18 86 config.direction = kDspiMsbFirst;
mbed_official 146:f64d43ff0c18 87 dspi_status_t result = dspi_hal_configure_data_format(obj->instance, kDspiCtar0, &config);
mbed_official 146:f64d43ff0c18 88 if (result != kStatus_DSPI_Success) {
mbed_official 146:f64d43ff0c18 89 error("Failed to configure SPI data format");
mbed_official 146:f64d43ff0c18 90 }
mbed_official 146:f64d43ff0c18 91
mbed_official 146:f64d43ff0c18 92 if (slave) {
mbed_official 146:f64d43ff0c18 93 dspi_hal_set_master_slave(obj->instance, kDspiSlave);
mbed_official 146:f64d43ff0c18 94 } else {
mbed_official 146:f64d43ff0c18 95 dspi_hal_set_master_slave(obj->instance, kDspiMaster);
mbed_official 146:f64d43ff0c18 96 }
mbed_official 146:f64d43ff0c18 97 }
mbed_official 146:f64d43ff0c18 98
mbed_official 146:f64d43ff0c18 99 void spi_frequency(spi_t *obj, int hz) {
mbed_official 146:f64d43ff0c18 100 uint32_t busClock;
mbed_official 146:f64d43ff0c18 101 clock_manager_get_frequency(kBusClock, &busClock);
mbed_official 146:f64d43ff0c18 102 dspi_hal_set_baud(obj->instance, kDspiCtar0, (uint32_t)hz, busClock);
mbed_official 146:f64d43ff0c18 103 }
mbed_official 146:f64d43ff0c18 104
mbed_official 146:f64d43ff0c18 105 static inline int spi_writeable(spi_t * obj) {
mbed_official 146:f64d43ff0c18 106 return dspi_hal_get_status_flag(obj->instance, kDspiTxFifoFillRequest);
mbed_official 146:f64d43ff0c18 107 }
mbed_official 146:f64d43ff0c18 108
mbed_official 146:f64d43ff0c18 109 static inline int spi_readable(spi_t * obj) {
mbed_official 146:f64d43ff0c18 110 return dspi_hal_get_status_flag(obj->instance, kDspiRxFifoDrainRequest);
mbed_official 146:f64d43ff0c18 111 }
mbed_official 146:f64d43ff0c18 112
mbed_official 146:f64d43ff0c18 113 int spi_master_write(spi_t *obj, int value) {
mbed_official 146:f64d43ff0c18 114 // wait tx buffer empty
mbed_official 146:f64d43ff0c18 115 while(!spi_writeable(obj));
mbed_official 146:f64d43ff0c18 116 dspi_command_config_t command = {0};
mbed_official 146:f64d43ff0c18 117 command.isEndOfQueue = true;
mbed_official 146:f64d43ff0c18 118 command.isChipSelectContinuous = 0;
mbed_official 146:f64d43ff0c18 119 dspi_hal_write_data_master_mode(obj->instance, &command, (uint16_t)value);
mbed_official 146:f64d43ff0c18 120 dspi_hal_clear_status_flag(obj->instance, kDspiTxFifoFillRequest);
mbed_official 146:f64d43ff0c18 121
mbed_official 146:f64d43ff0c18 122 // wait rx buffer full
mbed_official 146:f64d43ff0c18 123 while (!spi_readable(obj));
mbed_official 146:f64d43ff0c18 124 dspi_hal_clear_status_flag(obj->instance, kDspiRxFifoDrainRequest);
mbed_official 146:f64d43ff0c18 125 return dspi_hal_read_data(obj->instance) & 0xff;
mbed_official 146:f64d43ff0c18 126 }
mbed_official 146:f64d43ff0c18 127
mbed_official 146:f64d43ff0c18 128 int spi_slave_receive(spi_t *obj) {
mbed_official 146:f64d43ff0c18 129 return spi_readable(obj);
mbed_official 146:f64d43ff0c18 130 }
mbed_official 146:f64d43ff0c18 131
mbed_official 146:f64d43ff0c18 132 int spi_slave_read(spi_t *obj) {
mbed_official 146:f64d43ff0c18 133 return dspi_hal_read_data(obj->instance);
mbed_official 146:f64d43ff0c18 134 }
mbed_official 146:f64d43ff0c18 135
mbed_official 146:f64d43ff0c18 136 void spi_slave_write(spi_t *obj, int value) {
mbed_official 146:f64d43ff0c18 137 while (!spi_writeable(obj));
mbed_official 146:f64d43ff0c18 138 dspi_hal_write_data_slave_mode(obj->instance, (uint32_t)value);
mbed_official 146:f64d43ff0c18 139 }