mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@218:44081b78fdc2, 2014-05-30 (annotated)
- Committer:
- mbed_official
- Date:
- Fri May 30 15:30:09 2014 +0100
- Revision:
- 218:44081b78fdc2
- Parent:
- 205:c41fc65bcfb4
Synchronized with git revision d854859072d318241476ccc5f335965444d4c1d8
Full URL: https://github.com/mbedmicro/mbed/commit/d854859072d318241476ccc5f335965444d4c1d8/
[NUCLEO_F072RB] Update CubeF0 HAL driver
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 205:c41fc65bcfb4 | 1 | /** |
mbed_official | 205:c41fc65bcfb4 | 2 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 3 | * @file stm32f0xx_hal_rcc_ex.h |
mbed_official | 205:c41fc65bcfb4 | 4 | * @author MCD Application Team |
mbed_official | 205:c41fc65bcfb4 | 5 | * @version V1.0.0 |
mbed_official | 218:44081b78fdc2 | 6 | * @date 28-May-2014 |
mbed_official | 205:c41fc65bcfb4 | 7 | * @brief Header file of RCC HAL Extension module. |
mbed_official | 205:c41fc65bcfb4 | 8 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 9 | * @attention |
mbed_official | 205:c41fc65bcfb4 | 10 | * |
mbed_official | 205:c41fc65bcfb4 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 205:c41fc65bcfb4 | 12 | * |
mbed_official | 205:c41fc65bcfb4 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 205:c41fc65bcfb4 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 205:c41fc65bcfb4 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 205:c41fc65bcfb4 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 205:c41fc65bcfb4 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 205:c41fc65bcfb4 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 205:c41fc65bcfb4 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 205:c41fc65bcfb4 | 22 | * without specific prior written permission. |
mbed_official | 205:c41fc65bcfb4 | 23 | * |
mbed_official | 205:c41fc65bcfb4 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 205:c41fc65bcfb4 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 205:c41fc65bcfb4 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 205:c41fc65bcfb4 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 205:c41fc65bcfb4 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 205:c41fc65bcfb4 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 205:c41fc65bcfb4 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 205:c41fc65bcfb4 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 205:c41fc65bcfb4 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 205:c41fc65bcfb4 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 205:c41fc65bcfb4 | 34 | * |
mbed_official | 205:c41fc65bcfb4 | 35 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 36 | */ |
mbed_official | 205:c41fc65bcfb4 | 37 | |
mbed_official | 205:c41fc65bcfb4 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 39 | #ifndef __STM32F0xx_HAL_RCC_EX_H |
mbed_official | 205:c41fc65bcfb4 | 40 | #define __STM32F0xx_HAL_RCC_EX_H |
mbed_official | 205:c41fc65bcfb4 | 41 | |
mbed_official | 205:c41fc65bcfb4 | 42 | #ifdef __cplusplus |
mbed_official | 205:c41fc65bcfb4 | 43 | extern "C" { |
mbed_official | 205:c41fc65bcfb4 | 44 | #endif |
mbed_official | 205:c41fc65bcfb4 | 45 | |
mbed_official | 205:c41fc65bcfb4 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 47 | #include "stm32f0xx_hal_def.h" |
mbed_official | 205:c41fc65bcfb4 | 48 | |
mbed_official | 205:c41fc65bcfb4 | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 205:c41fc65bcfb4 | 50 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 51 | */ |
mbed_official | 205:c41fc65bcfb4 | 52 | |
mbed_official | 205:c41fc65bcfb4 | 53 | /** @addtogroup RCCEx |
mbed_official | 205:c41fc65bcfb4 | 54 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 55 | */ |
mbed_official | 205:c41fc65bcfb4 | 56 | |
mbed_official | 205:c41fc65bcfb4 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 58 | |
mbed_official | 205:c41fc65bcfb4 | 59 | /** |
mbed_official | 205:c41fc65bcfb4 | 60 | * @brief RCC extended clocks structure definition |
mbed_official | 205:c41fc65bcfb4 | 61 | */ |
mbed_official | 205:c41fc65bcfb4 | 62 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) |
mbed_official | 205:c41fc65bcfb4 | 63 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 64 | { |
mbed_official | 205:c41fc65bcfb4 | 65 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 66 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 67 | |
mbed_official | 205:c41fc65bcfb4 | 68 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 205:c41fc65bcfb4 | 69 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 70 | |
mbed_official | 205:c41fc65bcfb4 | 71 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 205:c41fc65bcfb4 | 72 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 73 | |
mbed_official | 205:c41fc65bcfb4 | 74 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 205:c41fc65bcfb4 | 75 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 76 | |
mbed_official | 205:c41fc65bcfb4 | 77 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 78 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */ |
mbed_official | 205:c41fc65bcfb4 | 79 | |
mbed_official | 205:c41fc65bcfb4 | 80 | #if defined(STM32F042x6) || defined(STM32F048xx) |
mbed_official | 205:c41fc65bcfb4 | 81 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 82 | { |
mbed_official | 205:c41fc65bcfb4 | 83 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 84 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 85 | |
mbed_official | 205:c41fc65bcfb4 | 86 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 205:c41fc65bcfb4 | 87 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 88 | |
mbed_official | 205:c41fc65bcfb4 | 89 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 205:c41fc65bcfb4 | 90 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 91 | |
mbed_official | 205:c41fc65bcfb4 | 92 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 205:c41fc65bcfb4 | 93 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 94 | |
mbed_official | 205:c41fc65bcfb4 | 95 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
mbed_official | 205:c41fc65bcfb4 | 96 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 97 | |
mbed_official | 205:c41fc65bcfb4 | 98 | uint32_t UsbClockSelection; /*!< USB clock source |
mbed_official | 205:c41fc65bcfb4 | 99 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 100 | |
mbed_official | 205:c41fc65bcfb4 | 101 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 102 | #endif /* STM32F042x6 || STM32F048xx */ |
mbed_official | 205:c41fc65bcfb4 | 103 | |
mbed_official | 205:c41fc65bcfb4 | 104 | #if defined(STM32F051x8) || defined(STM32F058xx) |
mbed_official | 205:c41fc65bcfb4 | 105 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 106 | { |
mbed_official | 205:c41fc65bcfb4 | 107 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 108 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 109 | |
mbed_official | 205:c41fc65bcfb4 | 110 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 205:c41fc65bcfb4 | 111 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 112 | |
mbed_official | 205:c41fc65bcfb4 | 113 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 205:c41fc65bcfb4 | 114 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 115 | |
mbed_official | 205:c41fc65bcfb4 | 116 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 205:c41fc65bcfb4 | 117 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 118 | |
mbed_official | 205:c41fc65bcfb4 | 119 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
mbed_official | 205:c41fc65bcfb4 | 120 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 121 | |
mbed_official | 205:c41fc65bcfb4 | 122 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 123 | #endif /* STM32F051x8 || STM32F058xx */ |
mbed_official | 205:c41fc65bcfb4 | 124 | |
mbed_official | 205:c41fc65bcfb4 | 125 | #if defined(STM32F071xB) |
mbed_official | 205:c41fc65bcfb4 | 126 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 127 | { |
mbed_official | 205:c41fc65bcfb4 | 128 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 129 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 130 | |
mbed_official | 205:c41fc65bcfb4 | 131 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 205:c41fc65bcfb4 | 132 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 133 | |
mbed_official | 205:c41fc65bcfb4 | 134 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 205:c41fc65bcfb4 | 135 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 136 | |
mbed_official | 205:c41fc65bcfb4 | 137 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
mbed_official | 205:c41fc65bcfb4 | 138 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 139 | |
mbed_official | 205:c41fc65bcfb4 | 140 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 205:c41fc65bcfb4 | 141 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 142 | |
mbed_official | 205:c41fc65bcfb4 | 143 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
mbed_official | 205:c41fc65bcfb4 | 144 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 145 | |
mbed_official | 205:c41fc65bcfb4 | 146 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 147 | #endif /* STM32F071xB */ |
mbed_official | 205:c41fc65bcfb4 | 148 | |
mbed_official | 205:c41fc65bcfb4 | 149 | #if defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 150 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 151 | { |
mbed_official | 205:c41fc65bcfb4 | 152 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 153 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 154 | |
mbed_official | 205:c41fc65bcfb4 | 155 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 205:c41fc65bcfb4 | 156 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 157 | |
mbed_official | 205:c41fc65bcfb4 | 158 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 205:c41fc65bcfb4 | 159 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 160 | |
mbed_official | 205:c41fc65bcfb4 | 161 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
mbed_official | 205:c41fc65bcfb4 | 162 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 163 | |
mbed_official | 205:c41fc65bcfb4 | 164 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 205:c41fc65bcfb4 | 165 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 166 | |
mbed_official | 205:c41fc65bcfb4 | 167 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
mbed_official | 205:c41fc65bcfb4 | 168 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 169 | |
mbed_official | 205:c41fc65bcfb4 | 170 | uint32_t UsbClockSelection; /*!< USB clock source |
mbed_official | 205:c41fc65bcfb4 | 171 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 172 | |
mbed_official | 205:c41fc65bcfb4 | 173 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 174 | #endif /* STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 175 | |
mbed_official | 205:c41fc65bcfb4 | 176 | #if defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 177 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 178 | { |
mbed_official | 205:c41fc65bcfb4 | 179 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 180 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 181 | |
mbed_official | 205:c41fc65bcfb4 | 182 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 205:c41fc65bcfb4 | 183 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 184 | |
mbed_official | 205:c41fc65bcfb4 | 185 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 205:c41fc65bcfb4 | 186 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 187 | |
mbed_official | 205:c41fc65bcfb4 | 188 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
mbed_official | 205:c41fc65bcfb4 | 189 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 190 | |
mbed_official | 205:c41fc65bcfb4 | 191 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 205:c41fc65bcfb4 | 192 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 193 | |
mbed_official | 205:c41fc65bcfb4 | 194 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
mbed_official | 205:c41fc65bcfb4 | 195 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 196 | |
mbed_official | 205:c41fc65bcfb4 | 197 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 198 | #endif /* STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 199 | |
mbed_official | 205:c41fc65bcfb4 | 200 | |
mbed_official | 205:c41fc65bcfb4 | 201 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 202 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 203 | /** |
mbed_official | 205:c41fc65bcfb4 | 204 | * @brief RCC CRS Status structures definition |
mbed_official | 205:c41fc65bcfb4 | 205 | */ |
mbed_official | 205:c41fc65bcfb4 | 206 | typedef enum |
mbed_official | 205:c41fc65bcfb4 | 207 | { |
mbed_official | 205:c41fc65bcfb4 | 208 | RCC_CRS_NONE = 0x00, |
mbed_official | 205:c41fc65bcfb4 | 209 | RCC_CRS_TIMEOUT = 0x01, |
mbed_official | 205:c41fc65bcfb4 | 210 | RCC_CRS_SYNCOK = 0x02, |
mbed_official | 205:c41fc65bcfb4 | 211 | RCC_CRS_SYNCWARM = 0x04, |
mbed_official | 205:c41fc65bcfb4 | 212 | RCC_CRS_SYNCERR = 0x08, |
mbed_official | 205:c41fc65bcfb4 | 213 | RCC_CRS_SYNCMISS = 0x10, |
mbed_official | 205:c41fc65bcfb4 | 214 | RCC_CRS_TRIMOV = 0x20 |
mbed_official | 205:c41fc65bcfb4 | 215 | } RCC_CRSStatusTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 216 | |
mbed_official | 205:c41fc65bcfb4 | 217 | /** |
mbed_official | 205:c41fc65bcfb4 | 218 | * @brief RCC_CRS Init structure definition |
mbed_official | 205:c41fc65bcfb4 | 219 | */ |
mbed_official | 205:c41fc65bcfb4 | 220 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 221 | { |
mbed_official | 205:c41fc65bcfb4 | 222 | uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. |
mbed_official | 205:c41fc65bcfb4 | 223 | This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ |
mbed_official | 205:c41fc65bcfb4 | 224 | |
mbed_official | 205:c41fc65bcfb4 | 225 | uint32_t Source; /*!< Specifies the SYNC signal source. |
mbed_official | 205:c41fc65bcfb4 | 226 | This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ |
mbed_official | 205:c41fc65bcfb4 | 227 | |
mbed_official | 205:c41fc65bcfb4 | 228 | uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. |
mbed_official | 205:c41fc65bcfb4 | 229 | This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ |
mbed_official | 205:c41fc65bcfb4 | 230 | |
mbed_official | 205:c41fc65bcfb4 | 231 | uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. |
mbed_official | 205:c41fc65bcfb4 | 232 | It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) |
mbed_official | 205:c41fc65bcfb4 | 233 | This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ |
mbed_official | 205:c41fc65bcfb4 | 234 | |
mbed_official | 205:c41fc65bcfb4 | 235 | uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. |
mbed_official | 205:c41fc65bcfb4 | 236 | This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ |
mbed_official | 205:c41fc65bcfb4 | 237 | |
mbed_official | 205:c41fc65bcfb4 | 238 | uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. |
mbed_official | 205:c41fc65bcfb4 | 239 | This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ |
mbed_official | 205:c41fc65bcfb4 | 240 | |
mbed_official | 205:c41fc65bcfb4 | 241 | }RCC_CRSInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 242 | |
mbed_official | 205:c41fc65bcfb4 | 243 | /** |
mbed_official | 205:c41fc65bcfb4 | 244 | * @brief RCC_CRS Synchronization structure definition |
mbed_official | 205:c41fc65bcfb4 | 245 | */ |
mbed_official | 205:c41fc65bcfb4 | 246 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 247 | { |
mbed_official | 205:c41fc65bcfb4 | 248 | uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. |
mbed_official | 205:c41fc65bcfb4 | 249 | This parameter must be a number between 0 and 0xFFFF*/ |
mbed_official | 205:c41fc65bcfb4 | 250 | |
mbed_official | 205:c41fc65bcfb4 | 251 | uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. |
mbed_official | 205:c41fc65bcfb4 | 252 | This parameter must be a number between 0 and 0x3F */ |
mbed_official | 205:c41fc65bcfb4 | 253 | |
mbed_official | 205:c41fc65bcfb4 | 254 | uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter |
mbed_official | 205:c41fc65bcfb4 | 255 | value latched in the time of the last SYNC event. |
mbed_official | 205:c41fc65bcfb4 | 256 | This parameter must be a number between 0 and 0xFFFF */ |
mbed_official | 205:c41fc65bcfb4 | 257 | |
mbed_official | 205:c41fc65bcfb4 | 258 | uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the |
mbed_official | 205:c41fc65bcfb4 | 259 | frequency error counter latched in the time of the last SYNC event. |
mbed_official | 205:c41fc65bcfb4 | 260 | It shows whether the actual frequency is below or above the target. |
mbed_official | 205:c41fc65bcfb4 | 261 | This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ |
mbed_official | 205:c41fc65bcfb4 | 262 | |
mbed_official | 205:c41fc65bcfb4 | 263 | }RCC_CRSSynchroInfoTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 264 | |
mbed_official | 205:c41fc65bcfb4 | 265 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 266 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 267 | |
mbed_official | 205:c41fc65bcfb4 | 268 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 269 | /** @defgroup RCCEx_Exported_Constants |
mbed_official | 205:c41fc65bcfb4 | 270 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 271 | */ |
mbed_official | 205:c41fc65bcfb4 | 272 | |
mbed_official | 205:c41fc65bcfb4 | 273 | /** @defgroup RCCEx_Periph_Clock_Selection |
mbed_official | 205:c41fc65bcfb4 | 274 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 275 | */ |
mbed_official | 205:c41fc65bcfb4 | 276 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) |
mbed_official | 205:c41fc65bcfb4 | 277 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 278 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 279 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
mbed_official | 205:c41fc65bcfb4 | 280 | |
mbed_official | 205:c41fc65bcfb4 | 281 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
mbed_official | 205:c41fc65bcfb4 | 282 | RCC_PERIPHCLK_RTC)) |
mbed_official | 205:c41fc65bcfb4 | 283 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 */ |
mbed_official | 205:c41fc65bcfb4 | 284 | |
mbed_official | 205:c41fc65bcfb4 | 285 | #if defined(STM32F051x8) || defined(STM32F058xx) |
mbed_official | 205:c41fc65bcfb4 | 286 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 287 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 288 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
mbed_official | 205:c41fc65bcfb4 | 289 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
mbed_official | 205:c41fc65bcfb4 | 290 | |
mbed_official | 205:c41fc65bcfb4 | 291 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
mbed_official | 205:c41fc65bcfb4 | 292 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) |
mbed_official | 205:c41fc65bcfb4 | 293 | #endif /* STM32F051x8 || STM32F058xx */ |
mbed_official | 205:c41fc65bcfb4 | 294 | |
mbed_official | 205:c41fc65bcfb4 | 295 | #if defined(STM32F071xB) |
mbed_official | 205:c41fc65bcfb4 | 296 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 297 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
mbed_official | 205:c41fc65bcfb4 | 298 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 299 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
mbed_official | 205:c41fc65bcfb4 | 300 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
mbed_official | 205:c41fc65bcfb4 | 301 | |
mbed_official | 205:c41fc65bcfb4 | 302 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
mbed_official | 205:c41fc65bcfb4 | 303 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
mbed_official | 205:c41fc65bcfb4 | 304 | RCC_PERIPHCLK_RTC)) |
mbed_official | 205:c41fc65bcfb4 | 305 | #endif /* STM32F071xB */ |
mbed_official | 205:c41fc65bcfb4 | 306 | |
mbed_official | 205:c41fc65bcfb4 | 307 | #if defined(STM32F042x6) || defined(STM32F048xx) |
mbed_official | 205:c41fc65bcfb4 | 308 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 309 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 310 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
mbed_official | 205:c41fc65bcfb4 | 311 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
mbed_official | 205:c41fc65bcfb4 | 312 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
mbed_official | 205:c41fc65bcfb4 | 313 | |
mbed_official | 205:c41fc65bcfb4 | 314 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
mbed_official | 205:c41fc65bcfb4 | 315 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ |
mbed_official | 205:c41fc65bcfb4 | 316 | RCC_PERIPHCLK_USB)) |
mbed_official | 205:c41fc65bcfb4 | 317 | #endif /* STM32F042x6 || STM32F048xx */ |
mbed_official | 205:c41fc65bcfb4 | 318 | |
mbed_official | 205:c41fc65bcfb4 | 319 | #if defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 320 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 321 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
mbed_official | 205:c41fc65bcfb4 | 322 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 323 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
mbed_official | 205:c41fc65bcfb4 | 324 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
mbed_official | 205:c41fc65bcfb4 | 325 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
mbed_official | 205:c41fc65bcfb4 | 326 | |
mbed_official | 205:c41fc65bcfb4 | 327 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
mbed_official | 205:c41fc65bcfb4 | 328 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
mbed_official | 205:c41fc65bcfb4 | 329 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) |
mbed_official | 205:c41fc65bcfb4 | 330 | #endif /* STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 331 | |
mbed_official | 205:c41fc65bcfb4 | 332 | #if defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 333 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 334 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
mbed_official | 205:c41fc65bcfb4 | 335 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 336 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
mbed_official | 205:c41fc65bcfb4 | 337 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
mbed_official | 205:c41fc65bcfb4 | 338 | |
mbed_official | 205:c41fc65bcfb4 | 339 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
mbed_official | 205:c41fc65bcfb4 | 340 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
mbed_official | 205:c41fc65bcfb4 | 341 | RCC_PERIPHCLK_RTC)) |
mbed_official | 205:c41fc65bcfb4 | 342 | #endif /* STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 343 | |
mbed_official | 205:c41fc65bcfb4 | 344 | /** |
mbed_official | 205:c41fc65bcfb4 | 345 | * @} |
mbed_official | 205:c41fc65bcfb4 | 346 | */ |
mbed_official | 205:c41fc65bcfb4 | 347 | |
mbed_official | 205:c41fc65bcfb4 | 348 | #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) |
mbed_official | 205:c41fc65bcfb4 | 349 | |
mbed_official | 205:c41fc65bcfb4 | 350 | /** @defgroup RCCEx_MCO_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 351 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 352 | */ |
mbed_official | 205:c41fc65bcfb4 | 353 | #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) |
mbed_official | 205:c41fc65bcfb4 | 354 | |
mbed_official | 205:c41fc65bcfb4 | 355 | #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ |
mbed_official | 205:c41fc65bcfb4 | 356 | ((SOURCE) == RCC_MCOSOURCE_LSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 357 | ((SOURCE) == RCC_MCOSOURCE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 358 | ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 359 | ((SOURCE) == RCC_MCOSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 360 | ((SOURCE) == RCC_MCOSOURCE_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 361 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ |
mbed_official | 205:c41fc65bcfb4 | 362 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 363 | ((SOURCE) == RCC_MCOSOURCE_HSI14)) |
mbed_official | 205:c41fc65bcfb4 | 364 | /** |
mbed_official | 205:c41fc65bcfb4 | 365 | * @} |
mbed_official | 205:c41fc65bcfb4 | 366 | */ |
mbed_official | 205:c41fc65bcfb4 | 367 | |
mbed_official | 205:c41fc65bcfb4 | 368 | #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx */ |
mbed_official | 205:c41fc65bcfb4 | 369 | |
mbed_official | 205:c41fc65bcfb4 | 370 | #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) |
mbed_official | 205:c41fc65bcfb4 | 371 | |
mbed_official | 205:c41fc65bcfb4 | 372 | /** @defgroup RCCEx_MCO_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 373 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 374 | */ |
mbed_official | 205:c41fc65bcfb4 | 375 | #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ |
mbed_official | 205:c41fc65bcfb4 | 376 | ((SOURCE) == RCC_MCOSOURCE_LSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 377 | ((SOURCE) == RCC_MCOSOURCE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 378 | ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 379 | ((SOURCE) == RCC_MCOSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 380 | ((SOURCE) == RCC_MCOSOURCE_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 381 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 382 | ((SOURCE) == RCC_MCOSOURCE_HSI14)) |
mbed_official | 205:c41fc65bcfb4 | 383 | /** |
mbed_official | 205:c41fc65bcfb4 | 384 | * @} |
mbed_official | 205:c41fc65bcfb4 | 385 | */ |
mbed_official | 205:c41fc65bcfb4 | 386 | |
mbed_official | 205:c41fc65bcfb4 | 387 | #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ |
mbed_official | 205:c41fc65bcfb4 | 388 | |
mbed_official | 205:c41fc65bcfb4 | 389 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 390 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 391 | /** @defgroup RCCEx_MCO_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 392 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 393 | */ |
mbed_official | 205:c41fc65bcfb4 | 394 | #define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48 |
mbed_official | 205:c41fc65bcfb4 | 395 | #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) |
mbed_official | 205:c41fc65bcfb4 | 396 | |
mbed_official | 205:c41fc65bcfb4 | 397 | #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ |
mbed_official | 205:c41fc65bcfb4 | 398 | ((SOURCE) == RCC_MCOSOURCE_LSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 399 | ((SOURCE) == RCC_MCOSOURCE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 400 | ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 401 | ((SOURCE) == RCC_MCOSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 402 | ((SOURCE) == RCC_MCOSOURCE_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 403 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ |
mbed_official | 205:c41fc65bcfb4 | 404 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 405 | ((SOURCE) == RCC_MCOSOURCE_HSI14) || \ |
mbed_official | 205:c41fc65bcfb4 | 406 | ((SOURCE) == RCC_MCOSOURCE_HSI48)) |
mbed_official | 205:c41fc65bcfb4 | 407 | /** |
mbed_official | 205:c41fc65bcfb4 | 408 | * @} |
mbed_official | 205:c41fc65bcfb4 | 409 | */ |
mbed_official | 205:c41fc65bcfb4 | 410 | |
mbed_official | 205:c41fc65bcfb4 | 411 | /** @defgroup RCCEx_Interrupt |
mbed_official | 205:c41fc65bcfb4 | 412 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 413 | */ |
mbed_official | 205:c41fc65bcfb4 | 414 | #define RCC_IT_HSI48 ((uint8_t)0x40) |
mbed_official | 205:c41fc65bcfb4 | 415 | /** |
mbed_official | 205:c41fc65bcfb4 | 416 | * @} |
mbed_official | 205:c41fc65bcfb4 | 417 | */ |
mbed_official | 205:c41fc65bcfb4 | 418 | |
mbed_official | 205:c41fc65bcfb4 | 419 | /* Flags in the CR2 register */ |
mbed_official | 205:c41fc65bcfb4 | 420 | #define RCC_CR2_HSI48RDY_BitNumber 16 |
mbed_official | 205:c41fc65bcfb4 | 421 | |
mbed_official | 205:c41fc65bcfb4 | 422 | #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 423 | |
mbed_official | 205:c41fc65bcfb4 | 424 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 425 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 426 | |
mbed_official | 205:c41fc65bcfb4 | 427 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 428 | |
mbed_official | 205:c41fc65bcfb4 | 429 | /** @defgroup RCCEx_USB_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 430 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 431 | */ |
mbed_official | 205:c41fc65bcfb4 | 432 | #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 |
mbed_official | 205:c41fc65bcfb4 | 433 | #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK |
mbed_official | 205:c41fc65bcfb4 | 434 | |
mbed_official | 205:c41fc65bcfb4 | 435 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ |
mbed_official | 205:c41fc65bcfb4 | 436 | ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) |
mbed_official | 205:c41fc65bcfb4 | 437 | /** |
mbed_official | 205:c41fc65bcfb4 | 438 | * @} |
mbed_official | 205:c41fc65bcfb4 | 439 | */ |
mbed_official | 205:c41fc65bcfb4 | 440 | |
mbed_official | 205:c41fc65bcfb4 | 441 | #endif /* STM32F042x6 || STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 442 | |
mbed_official | 205:c41fc65bcfb4 | 443 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 444 | |
mbed_official | 205:c41fc65bcfb4 | 445 | /** @defgroup RCCEx_USART2_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 446 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 447 | */ |
mbed_official | 205:c41fc65bcfb4 | 448 | #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK |
mbed_official | 205:c41fc65bcfb4 | 449 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK |
mbed_official | 205:c41fc65bcfb4 | 450 | #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE |
mbed_official | 205:c41fc65bcfb4 | 451 | #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI |
mbed_official | 205:c41fc65bcfb4 | 452 | |
mbed_official | 205:c41fc65bcfb4 | 453 | #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
mbed_official | 205:c41fc65bcfb4 | 454 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 455 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 456 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
mbed_official | 205:c41fc65bcfb4 | 457 | /** |
mbed_official | 205:c41fc65bcfb4 | 458 | * @} |
mbed_official | 205:c41fc65bcfb4 | 459 | */ |
mbed_official | 205:c41fc65bcfb4 | 460 | |
mbed_official | 205:c41fc65bcfb4 | 461 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 462 | |
mbed_official | 205:c41fc65bcfb4 | 463 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 464 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 465 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 466 | |
mbed_official | 205:c41fc65bcfb4 | 467 | /** @defgroup RCCEx_CEC_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 468 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 469 | */ |
mbed_official | 205:c41fc65bcfb4 | 470 | #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 |
mbed_official | 205:c41fc65bcfb4 | 471 | #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE |
mbed_official | 205:c41fc65bcfb4 | 472 | |
mbed_official | 205:c41fc65bcfb4 | 473 | #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 474 | ((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
mbed_official | 205:c41fc65bcfb4 | 475 | /** |
mbed_official | 205:c41fc65bcfb4 | 476 | * @} |
mbed_official | 205:c41fc65bcfb4 | 477 | */ |
mbed_official | 205:c41fc65bcfb4 | 478 | |
mbed_official | 205:c41fc65bcfb4 | 479 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 480 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 481 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 482 | |
mbed_official | 205:c41fc65bcfb4 | 483 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 484 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 485 | /** @addtogroup RCC_PLL_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 486 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 487 | */ |
mbed_official | 205:c41fc65bcfb4 | 488 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV |
mbed_official | 205:c41fc65bcfb4 | 489 | #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV |
mbed_official | 205:c41fc65bcfb4 | 490 | |
mbed_official | 205:c41fc65bcfb4 | 491 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 492 | ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ |
mbed_official | 205:c41fc65bcfb4 | 493 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
mbed_official | 205:c41fc65bcfb4 | 494 | /** |
mbed_official | 205:c41fc65bcfb4 | 495 | * @} |
mbed_official | 205:c41fc65bcfb4 | 496 | */ |
mbed_official | 205:c41fc65bcfb4 | 497 | |
mbed_official | 205:c41fc65bcfb4 | 498 | /** @addtogroup RCC_System_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 499 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 500 | */ |
mbed_official | 205:c41fc65bcfb4 | 501 | #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 |
mbed_official | 205:c41fc65bcfb4 | 502 | |
mbed_official | 205:c41fc65bcfb4 | 503 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 504 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 505 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 506 | ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) |
mbed_official | 205:c41fc65bcfb4 | 507 | /** |
mbed_official | 205:c41fc65bcfb4 | 508 | * @} |
mbed_official | 205:c41fc65bcfb4 | 509 | */ |
mbed_official | 205:c41fc65bcfb4 | 510 | |
mbed_official | 205:c41fc65bcfb4 | 511 | /** @addtogroup RCC_System_Clock_Source_Status |
mbed_official | 205:c41fc65bcfb4 | 512 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 513 | */ |
mbed_official | 205:c41fc65bcfb4 | 514 | #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 |
mbed_official | 205:c41fc65bcfb4 | 515 | |
mbed_official | 205:c41fc65bcfb4 | 516 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 517 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 518 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 519 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) |
mbed_official | 205:c41fc65bcfb4 | 520 | /** |
mbed_official | 205:c41fc65bcfb4 | 521 | * @} |
mbed_official | 205:c41fc65bcfb4 | 522 | */ |
mbed_official | 205:c41fc65bcfb4 | 523 | |
mbed_official | 205:c41fc65bcfb4 | 524 | /** @defgroup RCCEx_HSI48_Config |
mbed_official | 205:c41fc65bcfb4 | 525 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 526 | */ |
mbed_official | 205:c41fc65bcfb4 | 527 | #define RCC_HSI48_OFF ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 528 | #define RCC_HSI48_ON ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 529 | |
mbed_official | 205:c41fc65bcfb4 | 530 | #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) |
mbed_official | 205:c41fc65bcfb4 | 531 | /** |
mbed_official | 205:c41fc65bcfb4 | 532 | * @} |
mbed_official | 205:c41fc65bcfb4 | 533 | */ |
mbed_official | 205:c41fc65bcfb4 | 534 | |
mbed_official | 205:c41fc65bcfb4 | 535 | #else |
mbed_official | 205:c41fc65bcfb4 | 536 | /** @addtogroup RCC_PLL_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 537 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 538 | */ |
mbed_official | 205:c41fc65bcfb4 | 539 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 |
mbed_official | 205:c41fc65bcfb4 | 540 | /** |
mbed_official | 205:c41fc65bcfb4 | 541 | * @} |
mbed_official | 205:c41fc65bcfb4 | 542 | */ |
mbed_official | 205:c41fc65bcfb4 | 543 | |
mbed_official | 205:c41fc65bcfb4 | 544 | /** @addtogroup RCC_PLL_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 545 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 546 | */ |
mbed_official | 205:c41fc65bcfb4 | 547 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 548 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
mbed_official | 205:c41fc65bcfb4 | 549 | /** |
mbed_official | 205:c41fc65bcfb4 | 550 | * @} |
mbed_official | 205:c41fc65bcfb4 | 551 | */ |
mbed_official | 205:c41fc65bcfb4 | 552 | /** @addtogroup RCC_System_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 553 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 554 | */ |
mbed_official | 205:c41fc65bcfb4 | 555 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 556 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 557 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
mbed_official | 205:c41fc65bcfb4 | 558 | /** |
mbed_official | 205:c41fc65bcfb4 | 559 | * @} |
mbed_official | 205:c41fc65bcfb4 | 560 | */ |
mbed_official | 205:c41fc65bcfb4 | 561 | |
mbed_official | 205:c41fc65bcfb4 | 562 | /** @addtogroup RCC_System_Clock_Source_Status |
mbed_official | 205:c41fc65bcfb4 | 563 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 564 | */ |
mbed_official | 205:c41fc65bcfb4 | 565 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 566 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 567 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) |
mbed_official | 205:c41fc65bcfb4 | 568 | /** |
mbed_official | 205:c41fc65bcfb4 | 569 | * @} |
mbed_official | 205:c41fc65bcfb4 | 570 | */ |
mbed_official | 205:c41fc65bcfb4 | 571 | |
mbed_official | 205:c41fc65bcfb4 | 572 | /** @defgroup RCCEx_HSI48_Config |
mbed_official | 205:c41fc65bcfb4 | 573 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 574 | */ |
mbed_official | 205:c41fc65bcfb4 | 575 | #define RCC_HSI48_OFF ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 576 | |
mbed_official | 205:c41fc65bcfb4 | 577 | #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF)) |
mbed_official | 205:c41fc65bcfb4 | 578 | /** |
mbed_official | 205:c41fc65bcfb4 | 579 | * @} |
mbed_official | 205:c41fc65bcfb4 | 580 | */ |
mbed_official | 205:c41fc65bcfb4 | 581 | |
mbed_official | 205:c41fc65bcfb4 | 582 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 583 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 584 | |
mbed_official | 205:c41fc65bcfb4 | 585 | |
mbed_official | 205:c41fc65bcfb4 | 586 | #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) |
mbed_official | 205:c41fc65bcfb4 | 587 | |
mbed_official | 205:c41fc65bcfb4 | 588 | /** @defgroup RCCEx_MCOx_Clock_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 589 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 590 | */ |
mbed_official | 205:c41fc65bcfb4 | 591 | #define RCC_MCO_NODIV ((uint32_t)0x00000000) |
mbed_official | 205:c41fc65bcfb4 | 592 | |
mbed_official | 205:c41fc65bcfb4 | 593 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV)) |
mbed_official | 205:c41fc65bcfb4 | 594 | /** |
mbed_official | 205:c41fc65bcfb4 | 595 | * @} |
mbed_official | 205:c41fc65bcfb4 | 596 | */ |
mbed_official | 205:c41fc65bcfb4 | 597 | |
mbed_official | 205:c41fc65bcfb4 | 598 | #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ |
mbed_official | 205:c41fc65bcfb4 | 599 | |
mbed_official | 205:c41fc65bcfb4 | 600 | #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 601 | defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \ |
mbed_official | 205:c41fc65bcfb4 | 602 | defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 603 | |
mbed_official | 205:c41fc65bcfb4 | 604 | /** @defgroup RCCEx_MCOx_Clock_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 605 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 606 | */ |
mbed_official | 205:c41fc65bcfb4 | 607 | #define RCC_MCO_DIV1 ((uint32_t)0x00000000) |
mbed_official | 205:c41fc65bcfb4 | 608 | #define RCC_MCO_DIV2 ((uint32_t)0x10000000) |
mbed_official | 205:c41fc65bcfb4 | 609 | #define RCC_MCO_DIV4 ((uint32_t)0x20000000) |
mbed_official | 205:c41fc65bcfb4 | 610 | #define RCC_MCO_DIV8 ((uint32_t)0x30000000) |
mbed_official | 205:c41fc65bcfb4 | 611 | #define RCC_MCO_DIV16 ((uint32_t)0x40000000) |
mbed_official | 205:c41fc65bcfb4 | 612 | #define RCC_MCO_DIV32 ((uint32_t)0x50000000) |
mbed_official | 205:c41fc65bcfb4 | 613 | #define RCC_MCO_DIV64 ((uint32_t)0x60000000) |
mbed_official | 205:c41fc65bcfb4 | 614 | #define RCC_MCO_DIV128 ((uint32_t)0x70000000) |
mbed_official | 205:c41fc65bcfb4 | 615 | |
mbed_official | 205:c41fc65bcfb4 | 616 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 617 | ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \ |
mbed_official | 205:c41fc65bcfb4 | 618 | ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \ |
mbed_official | 205:c41fc65bcfb4 | 619 | ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128)) |
mbed_official | 205:c41fc65bcfb4 | 620 | /** |
mbed_official | 205:c41fc65bcfb4 | 621 | * @} |
mbed_official | 205:c41fc65bcfb4 | 622 | */ |
mbed_official | 205:c41fc65bcfb4 | 623 | |
mbed_official | 205:c41fc65bcfb4 | 624 | #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */ |
mbed_official | 205:c41fc65bcfb4 | 625 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 626 | |
mbed_official | 205:c41fc65bcfb4 | 627 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 628 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 629 | /** @defgroup RCCEx_CRS_SynchroSource |
mbed_official | 205:c41fc65bcfb4 | 630 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 631 | */ |
mbed_official | 205:c41fc65bcfb4 | 632 | #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ |
mbed_official | 205:c41fc65bcfb4 | 633 | #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
mbed_official | 205:c41fc65bcfb4 | 634 | #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
mbed_official | 205:c41fc65bcfb4 | 635 | |
mbed_official | 205:c41fc65bcfb4 | 636 | #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ |
mbed_official | 205:c41fc65bcfb4 | 637 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) ||\ |
mbed_official | 205:c41fc65bcfb4 | 638 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) |
mbed_official | 205:c41fc65bcfb4 | 639 | /** |
mbed_official | 205:c41fc65bcfb4 | 640 | * @} |
mbed_official | 205:c41fc65bcfb4 | 641 | */ |
mbed_official | 205:c41fc65bcfb4 | 642 | |
mbed_official | 205:c41fc65bcfb4 | 643 | /** @defgroup RCCEx_CRS_SynchroDivider |
mbed_official | 205:c41fc65bcfb4 | 644 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 645 | */ |
mbed_official | 205:c41fc65bcfb4 | 646 | #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */ |
mbed_official | 205:c41fc65bcfb4 | 647 | #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
mbed_official | 205:c41fc65bcfb4 | 648 | #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
mbed_official | 205:c41fc65bcfb4 | 649 | #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
mbed_official | 205:c41fc65bcfb4 | 650 | #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
mbed_official | 205:c41fc65bcfb4 | 651 | #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
mbed_official | 205:c41fc65bcfb4 | 652 | #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
mbed_official | 205:c41fc65bcfb4 | 653 | #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
mbed_official | 205:c41fc65bcfb4 | 654 | |
mbed_official | 205:c41fc65bcfb4 | 655 | #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) ||\ |
mbed_official | 205:c41fc65bcfb4 | 656 | ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ |
mbed_official | 205:c41fc65bcfb4 | 657 | ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ |
mbed_official | 205:c41fc65bcfb4 | 658 | ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) |
mbed_official | 205:c41fc65bcfb4 | 659 | /** |
mbed_official | 205:c41fc65bcfb4 | 660 | * @} |
mbed_official | 205:c41fc65bcfb4 | 661 | */ |
mbed_official | 205:c41fc65bcfb4 | 662 | |
mbed_official | 205:c41fc65bcfb4 | 663 | /** @defgroup RCCEx_CRS_SynchroPolarity |
mbed_official | 205:c41fc65bcfb4 | 664 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 665 | */ |
mbed_official | 205:c41fc65bcfb4 | 666 | #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ |
mbed_official | 205:c41fc65bcfb4 | 667 | #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
mbed_official | 205:c41fc65bcfb4 | 668 | |
mbed_official | 205:c41fc65bcfb4 | 669 | #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ |
mbed_official | 205:c41fc65bcfb4 | 670 | ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) |
mbed_official | 205:c41fc65bcfb4 | 671 | /** |
mbed_official | 205:c41fc65bcfb4 | 672 | * @} |
mbed_official | 205:c41fc65bcfb4 | 673 | */ |
mbed_official | 205:c41fc65bcfb4 | 674 | |
mbed_official | 205:c41fc65bcfb4 | 675 | /** @defgroup RCCEx_CRS_ReloadValueDefault |
mbed_official | 205:c41fc65bcfb4 | 676 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 677 | */ |
mbed_official | 205:c41fc65bcfb4 | 678 | #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds |
mbed_official | 205:c41fc65bcfb4 | 679 | to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ |
mbed_official | 205:c41fc65bcfb4 | 680 | |
mbed_official | 205:c41fc65bcfb4 | 681 | #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF)) |
mbed_official | 205:c41fc65bcfb4 | 682 | /** |
mbed_official | 205:c41fc65bcfb4 | 683 | * @} |
mbed_official | 205:c41fc65bcfb4 | 684 | */ |
mbed_official | 205:c41fc65bcfb4 | 685 | |
mbed_official | 205:c41fc65bcfb4 | 686 | /** @defgroup RCCEx_CRS_ErrorLimitDefault |
mbed_official | 205:c41fc65bcfb4 | 687 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 688 | */ |
mbed_official | 205:c41fc65bcfb4 | 689 | #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ |
mbed_official | 205:c41fc65bcfb4 | 690 | |
mbed_official | 205:c41fc65bcfb4 | 691 | #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF)) |
mbed_official | 205:c41fc65bcfb4 | 692 | /** |
mbed_official | 205:c41fc65bcfb4 | 693 | * @} |
mbed_official | 205:c41fc65bcfb4 | 694 | */ |
mbed_official | 205:c41fc65bcfb4 | 695 | |
mbed_official | 205:c41fc65bcfb4 | 696 | /** @defgroup RCCEx_CRS_HSI48CalibrationDefault |
mbed_official | 205:c41fc65bcfb4 | 697 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 698 | */ |
mbed_official | 205:c41fc65bcfb4 | 699 | #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval. |
mbed_official | 205:c41fc65bcfb4 | 700 | The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value |
mbed_official | 205:c41fc65bcfb4 | 701 | corresponds to a higher output frequency */ |
mbed_official | 205:c41fc65bcfb4 | 702 | |
mbed_official | 205:c41fc65bcfb4 | 703 | #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F)) |
mbed_official | 205:c41fc65bcfb4 | 704 | /** |
mbed_official | 205:c41fc65bcfb4 | 705 | * @} |
mbed_official | 205:c41fc65bcfb4 | 706 | */ |
mbed_official | 205:c41fc65bcfb4 | 707 | |
mbed_official | 205:c41fc65bcfb4 | 708 | /** @defgroup RCCEx_CRS_FreqErrorDirection |
mbed_official | 205:c41fc65bcfb4 | 709 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 710 | */ |
mbed_official | 205:c41fc65bcfb4 | 711 | #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ |
mbed_official | 205:c41fc65bcfb4 | 712 | #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ |
mbed_official | 205:c41fc65bcfb4 | 713 | |
mbed_official | 205:c41fc65bcfb4 | 714 | #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ |
mbed_official | 205:c41fc65bcfb4 | 715 | ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) |
mbed_official | 205:c41fc65bcfb4 | 716 | /** |
mbed_official | 205:c41fc65bcfb4 | 717 | * @} |
mbed_official | 205:c41fc65bcfb4 | 718 | */ |
mbed_official | 205:c41fc65bcfb4 | 719 | |
mbed_official | 205:c41fc65bcfb4 | 720 | /** @defgroup RCCEx_CRS_Interrupt_Sources |
mbed_official | 205:c41fc65bcfb4 | 721 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 722 | */ |
mbed_official | 205:c41fc65bcfb4 | 723 | #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ |
mbed_official | 205:c41fc65bcfb4 | 724 | #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ |
mbed_official | 205:c41fc65bcfb4 | 725 | #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */ |
mbed_official | 205:c41fc65bcfb4 | 726 | #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ |
mbed_official | 205:c41fc65bcfb4 | 727 | #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
mbed_official | 205:c41fc65bcfb4 | 728 | #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
mbed_official | 205:c41fc65bcfb4 | 729 | #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
mbed_official | 205:c41fc65bcfb4 | 730 | |
mbed_official | 205:c41fc65bcfb4 | 731 | /** |
mbed_official | 205:c41fc65bcfb4 | 732 | * @} |
mbed_official | 205:c41fc65bcfb4 | 733 | */ |
mbed_official | 205:c41fc65bcfb4 | 734 | |
mbed_official | 205:c41fc65bcfb4 | 735 | /** @defgroup RCCEx_CRS_Flags |
mbed_official | 205:c41fc65bcfb4 | 736 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 737 | */ |
mbed_official | 205:c41fc65bcfb4 | 738 | #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */ |
mbed_official | 205:c41fc65bcfb4 | 739 | #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */ |
mbed_official | 205:c41fc65bcfb4 | 740 | #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */ |
mbed_official | 205:c41fc65bcfb4 | 741 | #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */ |
mbed_official | 205:c41fc65bcfb4 | 742 | #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
mbed_official | 205:c41fc65bcfb4 | 743 | #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
mbed_official | 205:c41fc65bcfb4 | 744 | #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
mbed_official | 205:c41fc65bcfb4 | 745 | |
mbed_official | 205:c41fc65bcfb4 | 746 | /** |
mbed_official | 205:c41fc65bcfb4 | 747 | * @} |
mbed_official | 205:c41fc65bcfb4 | 748 | */ |
mbed_official | 205:c41fc65bcfb4 | 749 | |
mbed_official | 205:c41fc65bcfb4 | 750 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 751 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 752 | |
mbed_official | 205:c41fc65bcfb4 | 753 | /** |
mbed_official | 205:c41fc65bcfb4 | 754 | * @} |
mbed_official | 205:c41fc65bcfb4 | 755 | */ |
mbed_official | 205:c41fc65bcfb4 | 756 | |
mbed_official | 205:c41fc65bcfb4 | 757 | /* Exported macros -----------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 758 | /** @defgroup RCCEx_Exported_Macros |
mbed_official | 205:c41fc65bcfb4 | 759 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 760 | */ |
mbed_official | 205:c41fc65bcfb4 | 761 | |
mbed_official | 205:c41fc65bcfb4 | 762 | /** @brief Enable or disable the AHB peripheral clock. |
mbed_official | 205:c41fc65bcfb4 | 763 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 205:c41fc65bcfb4 | 764 | * is disabled and the application software has to enable this clock before |
mbed_official | 205:c41fc65bcfb4 | 765 | * using it. |
mbed_official | 205:c41fc65bcfb4 | 766 | */ |
mbed_official | 205:c41fc65bcfb4 | 767 | #if defined(STM32F030x6) || defined(STM32F030x8) || \ |
mbed_official | 205:c41fc65bcfb4 | 768 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 769 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 770 | |
mbed_official | 205:c41fc65bcfb4 | 771 | #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) |
mbed_official | 205:c41fc65bcfb4 | 772 | |
mbed_official | 205:c41fc65bcfb4 | 773 | #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
mbed_official | 205:c41fc65bcfb4 | 774 | |
mbed_official | 205:c41fc65bcfb4 | 775 | #endif /* STM32F030x6 || STM32F030x8 || */ |
mbed_official | 205:c41fc65bcfb4 | 776 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 777 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 778 | |
mbed_official | 205:c41fc65bcfb4 | 779 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 780 | |
mbed_official | 205:c41fc65bcfb4 | 781 | #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) |
mbed_official | 205:c41fc65bcfb4 | 782 | |
mbed_official | 205:c41fc65bcfb4 | 783 | #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
mbed_official | 205:c41fc65bcfb4 | 784 | |
mbed_official | 205:c41fc65bcfb4 | 785 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 786 | |
mbed_official | 205:c41fc65bcfb4 | 787 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 788 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 789 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 790 | |
mbed_official | 205:c41fc65bcfb4 | 791 | #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) |
mbed_official | 205:c41fc65bcfb4 | 792 | |
mbed_official | 205:c41fc65bcfb4 | 793 | #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
mbed_official | 205:c41fc65bcfb4 | 794 | |
mbed_official | 205:c41fc65bcfb4 | 795 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 796 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 797 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 798 | |
mbed_official | 205:c41fc65bcfb4 | 799 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
mbed_official | 205:c41fc65bcfb4 | 800 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 205:c41fc65bcfb4 | 801 | * is disabled and the application software has to enable this clock before |
mbed_official | 205:c41fc65bcfb4 | 802 | * using it. |
mbed_official | 205:c41fc65bcfb4 | 803 | */ |
mbed_official | 205:c41fc65bcfb4 | 804 | #if defined(STM32F030x8) || \ |
mbed_official | 205:c41fc65bcfb4 | 805 | defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 806 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 807 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 808 | |
mbed_official | 205:c41fc65bcfb4 | 809 | #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) |
mbed_official | 205:c41fc65bcfb4 | 810 | #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) |
mbed_official | 205:c41fc65bcfb4 | 811 | |
mbed_official | 205:c41fc65bcfb4 | 812 | #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
mbed_official | 205:c41fc65bcfb4 | 813 | #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
mbed_official | 205:c41fc65bcfb4 | 814 | |
mbed_official | 205:c41fc65bcfb4 | 815 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
mbed_official | 205:c41fc65bcfb4 | 816 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 817 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 818 | |
mbed_official | 205:c41fc65bcfb4 | 819 | #if defined(STM32F031x6) || defined(STM32F038xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 820 | defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 821 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 822 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 823 | |
mbed_official | 205:c41fc65bcfb4 | 824 | #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) |
mbed_official | 205:c41fc65bcfb4 | 825 | |
mbed_official | 205:c41fc65bcfb4 | 826 | #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
mbed_official | 205:c41fc65bcfb4 | 827 | |
mbed_official | 205:c41fc65bcfb4 | 828 | #endif /* STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 829 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 830 | |
mbed_official | 205:c41fc65bcfb4 | 831 | #if defined(STM32F030x8) || \ |
mbed_official | 205:c41fc65bcfb4 | 832 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 833 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 834 | |
mbed_official | 205:c41fc65bcfb4 | 835 | #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) |
mbed_official | 205:c41fc65bcfb4 | 836 | #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) |
mbed_official | 205:c41fc65bcfb4 | 837 | |
mbed_official | 205:c41fc65bcfb4 | 838 | #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
mbed_official | 205:c41fc65bcfb4 | 839 | #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
mbed_official | 205:c41fc65bcfb4 | 840 | |
mbed_official | 205:c41fc65bcfb4 | 841 | #endif /* STM32F030x8 || */ |
mbed_official | 205:c41fc65bcfb4 | 842 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 843 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 844 | |
mbed_official | 205:c41fc65bcfb4 | 845 | #if defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 846 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 847 | |
mbed_official | 205:c41fc65bcfb4 | 848 | #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) |
mbed_official | 205:c41fc65bcfb4 | 849 | |
mbed_official | 205:c41fc65bcfb4 | 850 | #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
mbed_official | 205:c41fc65bcfb4 | 851 | |
mbed_official | 205:c41fc65bcfb4 | 852 | #endif /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 853 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 854 | |
mbed_official | 205:c41fc65bcfb4 | 855 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 856 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 857 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 858 | |
mbed_official | 205:c41fc65bcfb4 | 859 | #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN)) |
mbed_official | 205:c41fc65bcfb4 | 860 | |
mbed_official | 205:c41fc65bcfb4 | 861 | #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
mbed_official | 205:c41fc65bcfb4 | 862 | |
mbed_official | 205:c41fc65bcfb4 | 863 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 864 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 865 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 866 | |
mbed_official | 205:c41fc65bcfb4 | 867 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 868 | |
mbed_official | 205:c41fc65bcfb4 | 869 | #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) |
mbed_official | 205:c41fc65bcfb4 | 870 | #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) |
mbed_official | 205:c41fc65bcfb4 | 871 | #define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN)) |
mbed_official | 205:c41fc65bcfb4 | 872 | |
mbed_official | 205:c41fc65bcfb4 | 873 | #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
mbed_official | 205:c41fc65bcfb4 | 874 | #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
mbed_official | 205:c41fc65bcfb4 | 875 | #define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) |
mbed_official | 205:c41fc65bcfb4 | 876 | |
mbed_official | 205:c41fc65bcfb4 | 877 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 878 | |
mbed_official | 205:c41fc65bcfb4 | 879 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 880 | |
mbed_official | 205:c41fc65bcfb4 | 881 | #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) |
mbed_official | 205:c41fc65bcfb4 | 882 | |
mbed_official | 205:c41fc65bcfb4 | 883 | #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) |
mbed_official | 205:c41fc65bcfb4 | 884 | |
mbed_official | 205:c41fc65bcfb4 | 885 | #endif /* STM32F042x6 || STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 886 | |
mbed_official | 205:c41fc65bcfb4 | 887 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 888 | |
mbed_official | 205:c41fc65bcfb4 | 889 | #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN)) |
mbed_official | 205:c41fc65bcfb4 | 890 | #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) |
mbed_official | 205:c41fc65bcfb4 | 891 | |
mbed_official | 205:c41fc65bcfb4 | 892 | #endif /* STM32F042x6 || STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 893 | |
mbed_official | 205:c41fc65bcfb4 | 894 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 895 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 896 | |
mbed_official | 205:c41fc65bcfb4 | 897 | #define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN)) |
mbed_official | 205:c41fc65bcfb4 | 898 | |
mbed_official | 205:c41fc65bcfb4 | 899 | #define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) |
mbed_official | 205:c41fc65bcfb4 | 900 | |
mbed_official | 205:c41fc65bcfb4 | 901 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 902 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 903 | |
mbed_official | 205:c41fc65bcfb4 | 904 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
mbed_official | 205:c41fc65bcfb4 | 905 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 205:c41fc65bcfb4 | 906 | * is disabled and the application software has to enable this clock before |
mbed_official | 205:c41fc65bcfb4 | 907 | * using it. |
mbed_official | 205:c41fc65bcfb4 | 908 | */ |
mbed_official | 205:c41fc65bcfb4 | 909 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 910 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 911 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 912 | |
mbed_official | 205:c41fc65bcfb4 | 913 | #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN)) |
mbed_official | 205:c41fc65bcfb4 | 914 | |
mbed_official | 205:c41fc65bcfb4 | 915 | #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
mbed_official | 205:c41fc65bcfb4 | 916 | |
mbed_official | 205:c41fc65bcfb4 | 917 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
mbed_official | 205:c41fc65bcfb4 | 918 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 919 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 920 | |
mbed_official | 205:c41fc65bcfb4 | 921 | /** @brief Force or release AHB peripheral reset. |
mbed_official | 205:c41fc65bcfb4 | 922 | */ |
mbed_official | 205:c41fc65bcfb4 | 923 | #if defined(STM32F030x6) || defined(STM32F030x8) || \ |
mbed_official | 205:c41fc65bcfb4 | 924 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 925 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 926 | |
mbed_official | 205:c41fc65bcfb4 | 927 | #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
mbed_official | 205:c41fc65bcfb4 | 928 | |
mbed_official | 205:c41fc65bcfb4 | 929 | #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
mbed_official | 205:c41fc65bcfb4 | 930 | |
mbed_official | 205:c41fc65bcfb4 | 931 | #endif /* STM32F030x6 || STM32F030x8 || */ |
mbed_official | 205:c41fc65bcfb4 | 932 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 933 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 934 | |
mbed_official | 205:c41fc65bcfb4 | 935 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 936 | |
mbed_official | 205:c41fc65bcfb4 | 937 | #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
mbed_official | 205:c41fc65bcfb4 | 938 | |
mbed_official | 205:c41fc65bcfb4 | 939 | #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
mbed_official | 205:c41fc65bcfb4 | 940 | |
mbed_official | 205:c41fc65bcfb4 | 941 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 942 | |
mbed_official | 205:c41fc65bcfb4 | 943 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 944 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 945 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 946 | |
mbed_official | 205:c41fc65bcfb4 | 947 | #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
mbed_official | 205:c41fc65bcfb4 | 948 | |
mbed_official | 205:c41fc65bcfb4 | 949 | #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
mbed_official | 205:c41fc65bcfb4 | 950 | |
mbed_official | 205:c41fc65bcfb4 | 951 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 952 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 953 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 954 | |
mbed_official | 205:c41fc65bcfb4 | 955 | /** @brief Force or release APB1 peripheral reset. |
mbed_official | 205:c41fc65bcfb4 | 956 | */ |
mbed_official | 205:c41fc65bcfb4 | 957 | #if defined(STM32F030x8) || \ |
mbed_official | 205:c41fc65bcfb4 | 958 | defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 959 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 960 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 961 | |
mbed_official | 205:c41fc65bcfb4 | 962 | #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
mbed_official | 205:c41fc65bcfb4 | 963 | #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
mbed_official | 205:c41fc65bcfb4 | 964 | |
mbed_official | 205:c41fc65bcfb4 | 965 | #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
mbed_official | 205:c41fc65bcfb4 | 966 | #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
mbed_official | 205:c41fc65bcfb4 | 967 | |
mbed_official | 205:c41fc65bcfb4 | 968 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
mbed_official | 205:c41fc65bcfb4 | 969 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 970 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 971 | |
mbed_official | 205:c41fc65bcfb4 | 972 | #if defined(STM32F031x6) || defined(STM32F038xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 973 | defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 974 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 975 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 976 | |
mbed_official | 205:c41fc65bcfb4 | 977 | #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
mbed_official | 205:c41fc65bcfb4 | 978 | |
mbed_official | 205:c41fc65bcfb4 | 979 | #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
mbed_official | 205:c41fc65bcfb4 | 980 | |
mbed_official | 205:c41fc65bcfb4 | 981 | #endif /* STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 982 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 983 | |
mbed_official | 205:c41fc65bcfb4 | 984 | #if defined(STM32F030x8) || \ |
mbed_official | 205:c41fc65bcfb4 | 985 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 986 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 987 | |
mbed_official | 205:c41fc65bcfb4 | 988 | #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
mbed_official | 205:c41fc65bcfb4 | 989 | #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
mbed_official | 205:c41fc65bcfb4 | 990 | |
mbed_official | 205:c41fc65bcfb4 | 991 | #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
mbed_official | 205:c41fc65bcfb4 | 992 | #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
mbed_official | 205:c41fc65bcfb4 | 993 | |
mbed_official | 205:c41fc65bcfb4 | 994 | #endif /* STM32F030x8 || */ |
mbed_official | 205:c41fc65bcfb4 | 995 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 996 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 997 | |
mbed_official | 205:c41fc65bcfb4 | 998 | #if defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 999 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1000 | |
mbed_official | 205:c41fc65bcfb4 | 1001 | #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
mbed_official | 205:c41fc65bcfb4 | 1002 | |
mbed_official | 205:c41fc65bcfb4 | 1003 | #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
mbed_official | 205:c41fc65bcfb4 | 1004 | |
mbed_official | 205:c41fc65bcfb4 | 1005 | #endif /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 1006 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1007 | |
mbed_official | 205:c41fc65bcfb4 | 1008 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1009 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1010 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1011 | |
mbed_official | 205:c41fc65bcfb4 | 1012 | #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
mbed_official | 205:c41fc65bcfb4 | 1013 | |
mbed_official | 205:c41fc65bcfb4 | 1014 | #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
mbed_official | 205:c41fc65bcfb4 | 1015 | |
mbed_official | 205:c41fc65bcfb4 | 1016 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 1017 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 1018 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1019 | |
mbed_official | 205:c41fc65bcfb4 | 1020 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1021 | |
mbed_official | 205:c41fc65bcfb4 | 1022 | #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
mbed_official | 205:c41fc65bcfb4 | 1023 | #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
mbed_official | 205:c41fc65bcfb4 | 1024 | #define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) |
mbed_official | 205:c41fc65bcfb4 | 1025 | |
mbed_official | 205:c41fc65bcfb4 | 1026 | #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
mbed_official | 205:c41fc65bcfb4 | 1027 | #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
mbed_official | 205:c41fc65bcfb4 | 1028 | #define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) |
mbed_official | 205:c41fc65bcfb4 | 1029 | |
mbed_official | 205:c41fc65bcfb4 | 1030 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1031 | |
mbed_official | 205:c41fc65bcfb4 | 1032 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 1033 | |
mbed_official | 205:c41fc65bcfb4 | 1034 | #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) |
mbed_official | 205:c41fc65bcfb4 | 1035 | |
mbed_official | 205:c41fc65bcfb4 | 1036 | #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) |
mbed_official | 205:c41fc65bcfb4 | 1037 | |
mbed_official | 205:c41fc65bcfb4 | 1038 | #endif /* STM32F042x6 || STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 1039 | |
mbed_official | 205:c41fc65bcfb4 | 1040 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 1041 | |
mbed_official | 205:c41fc65bcfb4 | 1042 | #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) |
mbed_official | 205:c41fc65bcfb4 | 1043 | |
mbed_official | 205:c41fc65bcfb4 | 1044 | #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) |
mbed_official | 205:c41fc65bcfb4 | 1045 | |
mbed_official | 205:c41fc65bcfb4 | 1046 | #endif /* STM32F042x6 || STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 1047 | |
mbed_official | 205:c41fc65bcfb4 | 1048 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1049 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1050 | |
mbed_official | 205:c41fc65bcfb4 | 1051 | #define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) |
mbed_official | 205:c41fc65bcfb4 | 1052 | |
mbed_official | 205:c41fc65bcfb4 | 1053 | #define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) |
mbed_official | 205:c41fc65bcfb4 | 1054 | |
mbed_official | 205:c41fc65bcfb4 | 1055 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 1056 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1057 | |
mbed_official | 205:c41fc65bcfb4 | 1058 | |
mbed_official | 205:c41fc65bcfb4 | 1059 | /** @brief Force or release APB2 peripheral reset. |
mbed_official | 205:c41fc65bcfb4 | 1060 | */ |
mbed_official | 205:c41fc65bcfb4 | 1061 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1062 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1063 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1064 | |
mbed_official | 205:c41fc65bcfb4 | 1065 | #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
mbed_official | 205:c41fc65bcfb4 | 1066 | |
mbed_official | 205:c41fc65bcfb4 | 1067 | #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
mbed_official | 205:c41fc65bcfb4 | 1068 | |
mbed_official | 205:c41fc65bcfb4 | 1069 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
mbed_official | 205:c41fc65bcfb4 | 1070 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 1071 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1072 | |
mbed_official | 205:c41fc65bcfb4 | 1073 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1074 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1075 | |
mbed_official | 205:c41fc65bcfb4 | 1076 | /** @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). |
mbed_official | 205:c41fc65bcfb4 | 1077 | * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 205:c41fc65bcfb4 | 1078 | * @note HSI48 can not be stopped if it is used as system clock source. In this case, |
mbed_official | 205:c41fc65bcfb4 | 1079 | * you have to select another source of the system clock then stop the HSI14. |
mbed_official | 205:c41fc65bcfb4 | 1080 | * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software |
mbed_official | 205:c41fc65bcfb4 | 1081 | * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be |
mbed_official | 205:c41fc65bcfb4 | 1082 | * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. |
mbed_official | 205:c41fc65bcfb4 | 1083 | * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator |
mbed_official | 205:c41fc65bcfb4 | 1084 | * clock cycles. |
mbed_official | 205:c41fc65bcfb4 | 1085 | */ |
mbed_official | 205:c41fc65bcfb4 | 1086 | #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) |
mbed_official | 205:c41fc65bcfb4 | 1087 | #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) |
mbed_official | 205:c41fc65bcfb4 | 1088 | |
mbed_official | 205:c41fc65bcfb4 | 1089 | /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. |
mbed_official | 205:c41fc65bcfb4 | 1090 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1091 | * @arg RCC_HSI48_ON: HSI48 enabled |
mbed_official | 205:c41fc65bcfb4 | 1092 | * @arg RCC_HSI48_OFF: HSI48 disabled |
mbed_official | 205:c41fc65bcfb4 | 1093 | */ |
mbed_official | 205:c41fc65bcfb4 | 1094 | #define __HAL_RCC_GET_HSI48_STATE() \ |
mbed_official | 205:c41fc65bcfb4 | 1095 | (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) |
mbed_official | 205:c41fc65bcfb4 | 1096 | |
mbed_official | 205:c41fc65bcfb4 | 1097 | #else |
mbed_official | 205:c41fc65bcfb4 | 1098 | |
mbed_official | 205:c41fc65bcfb4 | 1099 | /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. |
mbed_official | 205:c41fc65bcfb4 | 1100 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1101 | * @arg RCC_HSI_OFF: HSI48 disabled |
mbed_official | 205:c41fc65bcfb4 | 1102 | */ |
mbed_official | 205:c41fc65bcfb4 | 1103 | #define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF |
mbed_official | 205:c41fc65bcfb4 | 1104 | |
mbed_official | 205:c41fc65bcfb4 | 1105 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 1106 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1107 | |
mbed_official | 205:c41fc65bcfb4 | 1108 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
mbed_official | 205:c41fc65bcfb4 | 1109 | |
mbed_official | 205:c41fc65bcfb4 | 1110 | /** @brief Macro to configure the USB clock (USBCLK). |
mbed_official | 205:c41fc65bcfb4 | 1111 | * @param __USBCLKSource__: specifies the USB clock source. |
mbed_official | 205:c41fc65bcfb4 | 1112 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1113 | * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock |
mbed_official | 205:c41fc65bcfb4 | 1114 | * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock |
mbed_official | 205:c41fc65bcfb4 | 1115 | */ |
mbed_official | 205:c41fc65bcfb4 | 1116 | #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ |
mbed_official | 205:c41fc65bcfb4 | 1117 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__)) |
mbed_official | 205:c41fc65bcfb4 | 1118 | |
mbed_official | 205:c41fc65bcfb4 | 1119 | /** @brief Macro to get the USB clock source. |
mbed_official | 205:c41fc65bcfb4 | 1120 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1121 | * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock |
mbed_official | 205:c41fc65bcfb4 | 1122 | * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock |
mbed_official | 205:c41fc65bcfb4 | 1123 | */ |
mbed_official | 205:c41fc65bcfb4 | 1124 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) |
mbed_official | 205:c41fc65bcfb4 | 1125 | |
mbed_official | 205:c41fc65bcfb4 | 1126 | #endif /* STM32F042x6 || STM32F072xB */ |
mbed_official | 205:c41fc65bcfb4 | 1127 | |
mbed_official | 205:c41fc65bcfb4 | 1128 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1129 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1130 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1131 | |
mbed_official | 205:c41fc65bcfb4 | 1132 | /** @brief Macro to configure the CEC clock. |
mbed_official | 205:c41fc65bcfb4 | 1133 | * @param __CECCLKSource__: specifies the CEC clock source. |
mbed_official | 205:c41fc65bcfb4 | 1134 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1135 | * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
mbed_official | 205:c41fc65bcfb4 | 1136 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
mbed_official | 205:c41fc65bcfb4 | 1137 | */ |
mbed_official | 205:c41fc65bcfb4 | 1138 | #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ |
mbed_official | 205:c41fc65bcfb4 | 1139 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__)) |
mbed_official | 205:c41fc65bcfb4 | 1140 | |
mbed_official | 205:c41fc65bcfb4 | 1141 | /** @brief Macro to get the HDMI CEC clock source. |
mbed_official | 205:c41fc65bcfb4 | 1142 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1143 | * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
mbed_official | 205:c41fc65bcfb4 | 1144 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
mbed_official | 205:c41fc65bcfb4 | 1145 | */ |
mbed_official | 205:c41fc65bcfb4 | 1146 | #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) |
mbed_official | 205:c41fc65bcfb4 | 1147 | |
mbed_official | 205:c41fc65bcfb4 | 1148 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 1149 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 205:c41fc65bcfb4 | 1150 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1151 | |
mbed_official | 205:c41fc65bcfb4 | 1152 | #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1153 | defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \ |
mbed_official | 205:c41fc65bcfb4 | 1154 | defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1155 | |
mbed_official | 205:c41fc65bcfb4 | 1156 | /** @brief Macro to configure the MCO clock. |
mbed_official | 205:c41fc65bcfb4 | 1157 | * @param __MCOCLKSource__: specifies the MCO clock source. |
mbed_official | 205:c41fc65bcfb4 | 1158 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1159 | * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1160 | * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1161 | * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1162 | * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1163 | * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1164 | * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1165 | * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1166 | * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1167 | * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1168 | * @param __MCODiv__: specifies the MCO clock prescaler. |
mbed_official | 205:c41fc65bcfb4 | 1169 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1170 | * @arg RCC_MCO_DIV1: MCO clock source is divided by 1 |
mbed_official | 205:c41fc65bcfb4 | 1171 | * @arg RCC_MCO_DIV2: MCO clock source is divided by 2 |
mbed_official | 205:c41fc65bcfb4 | 1172 | * @arg RCC_MCO_DIV4: MCO clock source is divided by 4 |
mbed_official | 205:c41fc65bcfb4 | 1173 | * @arg RCC_MCO_DIV8: MCO clock source is divided by 8 |
mbed_official | 205:c41fc65bcfb4 | 1174 | * @arg RCC_MCO_DIV16: MCO clock source is divided by 16 |
mbed_official | 205:c41fc65bcfb4 | 1175 | * @arg RCC_MCO_DIV32: MCO clock source is divided by 32 |
mbed_official | 205:c41fc65bcfb4 | 1176 | * @arg RCC_MCO_DIV64: MCO clock source is divided by 64 |
mbed_official | 205:c41fc65bcfb4 | 1177 | * @arg RCC_MCO_DIV128: MCO clock source is divided by 128 |
mbed_official | 205:c41fc65bcfb4 | 1178 | */ |
mbed_official | 205:c41fc65bcfb4 | 1179 | #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ |
mbed_official | 205:c41fc65bcfb4 | 1180 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__))) |
mbed_official | 205:c41fc65bcfb4 | 1181 | #else |
mbed_official | 205:c41fc65bcfb4 | 1182 | |
mbed_official | 205:c41fc65bcfb4 | 1183 | /** @brief Macro to configure the MCO clock. |
mbed_official | 205:c41fc65bcfb4 | 1184 | * @param __MCOCLKSource__: specifies the MCO clock source. |
mbed_official | 205:c41fc65bcfb4 | 1185 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1186 | * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1187 | * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1188 | * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1189 | * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1190 | * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1191 | * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1192 | * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1193 | * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock |
mbed_official | 205:c41fc65bcfb4 | 1194 | * @param __MCODiv__: specifies the MCO clock prescaler. |
mbed_official | 205:c41fc65bcfb4 | 1195 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1196 | * @arg RCC_MCO_NODIV: No division applied on MCO clock source |
mbed_official | 205:c41fc65bcfb4 | 1197 | */ |
mbed_official | 205:c41fc65bcfb4 | 1198 | #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ |
mbed_official | 205:c41fc65bcfb4 | 1199 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__) |
mbed_official | 205:c41fc65bcfb4 | 1200 | |
mbed_official | 205:c41fc65bcfb4 | 1201 | #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || */ |
mbed_official | 205:c41fc65bcfb4 | 1202 | /* STM32F042x6 || STM32F071xB || */ |
mbed_official | 205:c41fc65bcfb4 | 1203 | /* STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1204 | |
mbed_official | 205:c41fc65bcfb4 | 1205 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1206 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1207 | /* Interrupt & Flag management */ |
mbed_official | 205:c41fc65bcfb4 | 1208 | |
mbed_official | 205:c41fc65bcfb4 | 1209 | /** |
mbed_official | 205:c41fc65bcfb4 | 1210 | * @brief Enables the specified CRS interrupts. |
mbed_official | 205:c41fc65bcfb4 | 1211 | * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled. |
mbed_official | 205:c41fc65bcfb4 | 1212 | * This parameter can be any combination of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1213 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 205:c41fc65bcfb4 | 1214 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 205:c41fc65bcfb4 | 1215 | * @arg RCC_CRS_IT_ERR |
mbed_official | 205:c41fc65bcfb4 | 1216 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 205:c41fc65bcfb4 | 1217 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1218 | */ |
mbed_official | 205:c41fc65bcfb4 | 1219 | #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 1220 | |
mbed_official | 205:c41fc65bcfb4 | 1221 | /** |
mbed_official | 205:c41fc65bcfb4 | 1222 | * @brief Disables the specified CRS interrupts. |
mbed_official | 205:c41fc65bcfb4 | 1223 | * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled. |
mbed_official | 205:c41fc65bcfb4 | 1224 | * This parameter can be any combination of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1225 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 205:c41fc65bcfb4 | 1226 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 205:c41fc65bcfb4 | 1227 | * @arg RCC_CRS_IT_ERR |
mbed_official | 205:c41fc65bcfb4 | 1228 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 205:c41fc65bcfb4 | 1229 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1230 | */ |
mbed_official | 205:c41fc65bcfb4 | 1231 | #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 1232 | |
mbed_official | 205:c41fc65bcfb4 | 1233 | /** @brief Check the CRS's interrupt has occurred or not. |
mbed_official | 205:c41fc65bcfb4 | 1234 | * @param __INTERRUPT__: specifies the CRS interrupt source to check. |
mbed_official | 205:c41fc65bcfb4 | 1235 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1236 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 205:c41fc65bcfb4 | 1237 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 205:c41fc65bcfb4 | 1238 | * @arg RCC_CRS_IT_ERR |
mbed_official | 205:c41fc65bcfb4 | 1239 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 205:c41fc65bcfb4 | 1240 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
mbed_official | 205:c41fc65bcfb4 | 1241 | */ |
mbed_official | 205:c41fc65bcfb4 | 1242 | #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) |
mbed_official | 205:c41fc65bcfb4 | 1243 | |
mbed_official | 205:c41fc65bcfb4 | 1244 | /** @brief Clear the CRS's interrupt pending bits |
mbed_official | 205:c41fc65bcfb4 | 1245 | * bits to clear the selected interrupt pending bits. |
mbed_official | 205:c41fc65bcfb4 | 1246 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
mbed_official | 205:c41fc65bcfb4 | 1247 | * This parameter can be any combination of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1248 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 205:c41fc65bcfb4 | 1249 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 205:c41fc65bcfb4 | 1250 | * @arg RCC_CRS_IT_ERR |
mbed_official | 205:c41fc65bcfb4 | 1251 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 205:c41fc65bcfb4 | 1252 | * @arg RCC_CRS_IT_TRIMOVF |
mbed_official | 205:c41fc65bcfb4 | 1253 | * @arg RCC_CRS_IT_SYNCERR |
mbed_official | 205:c41fc65bcfb4 | 1254 | * @arg RCC_CRS_IT_SYNCMISS |
mbed_official | 205:c41fc65bcfb4 | 1255 | */ |
mbed_official | 205:c41fc65bcfb4 | 1256 | /* CRS IT Error Mask */ |
mbed_official | 205:c41fc65bcfb4 | 1257 | #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
mbed_official | 205:c41fc65bcfb4 | 1258 | |
mbed_official | 205:c41fc65bcfb4 | 1259 | #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ |
mbed_official | 205:c41fc65bcfb4 | 1260 | (CRS->ICR |= (__INTERRUPT__))) |
mbed_official | 205:c41fc65bcfb4 | 1261 | |
mbed_official | 205:c41fc65bcfb4 | 1262 | /** |
mbed_official | 205:c41fc65bcfb4 | 1263 | * @brief Checks whether the specified CRS flag is set or not. |
mbed_official | 205:c41fc65bcfb4 | 1264 | * @param _FLAG_: specifies the flag to check. |
mbed_official | 205:c41fc65bcfb4 | 1265 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1266 | * @arg RCC_CRS_FLAG_SYNCOK |
mbed_official | 205:c41fc65bcfb4 | 1267 | * @arg RCC_CRS_FLAG_SYNCWARN |
mbed_official | 205:c41fc65bcfb4 | 1268 | * @arg RCC_CRS_FLAG_ERR |
mbed_official | 205:c41fc65bcfb4 | 1269 | * @arg RCC_CRS_FLAG_ESYNC |
mbed_official | 205:c41fc65bcfb4 | 1270 | * @arg RCC_CRS_FLAG_TRIMOVF |
mbed_official | 205:c41fc65bcfb4 | 1271 | * @arg RCC_CRS_FLAG_SYNCERR |
mbed_official | 205:c41fc65bcfb4 | 1272 | * @arg RCC_CRS_FLAG_SYNCMISS |
mbed_official | 205:c41fc65bcfb4 | 1273 | * @retval The new state of _FLAG_ (TRUE or FALSE). |
mbed_official | 205:c41fc65bcfb4 | 1274 | */ |
mbed_official | 205:c41fc65bcfb4 | 1275 | #define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_)) |
mbed_official | 205:c41fc65bcfb4 | 1276 | |
mbed_official | 205:c41fc65bcfb4 | 1277 | /** |
mbed_official | 205:c41fc65bcfb4 | 1278 | * @brief Clears the CRS specified FLAG. |
mbed_official | 205:c41fc65bcfb4 | 1279 | * @param _FLAG_: specifies the flag to clear. |
mbed_official | 205:c41fc65bcfb4 | 1280 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1281 | * @arg RCC_CRS_FLAG_SYNCOK |
mbed_official | 205:c41fc65bcfb4 | 1282 | * @arg RCC_CRS_FLAG_SYNCWARN |
mbed_official | 205:c41fc65bcfb4 | 1283 | * @arg RCC_CRS_FLAG_ERR |
mbed_official | 205:c41fc65bcfb4 | 1284 | * @arg RCC_CRS_FLAG_ESYNC |
mbed_official | 205:c41fc65bcfb4 | 1285 | * @arg RCC_CRS_FLAG_TRIMOVF |
mbed_official | 205:c41fc65bcfb4 | 1286 | * @arg RCC_CRS_FLAG_SYNCERR |
mbed_official | 205:c41fc65bcfb4 | 1287 | * @arg RCC_CRS_FLAG_SYNCMISS |
mbed_official | 205:c41fc65bcfb4 | 1288 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1289 | */ |
mbed_official | 205:c41fc65bcfb4 | 1290 | |
mbed_official | 205:c41fc65bcfb4 | 1291 | /* CRS Flag Error Mask */ |
mbed_official | 205:c41fc65bcfb4 | 1292 | #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
mbed_official | 205:c41fc65bcfb4 | 1293 | |
mbed_official | 205:c41fc65bcfb4 | 1294 | #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ |
mbed_official | 205:c41fc65bcfb4 | 1295 | (CRS->ICR |= (__FLAG__))) |
mbed_official | 205:c41fc65bcfb4 | 1296 | |
mbed_official | 205:c41fc65bcfb4 | 1297 | |
mbed_official | 205:c41fc65bcfb4 | 1298 | /** |
mbed_official | 205:c41fc65bcfb4 | 1299 | * @brief Enables the oscillator clock for frequency error counter. |
mbed_official | 205:c41fc65bcfb4 | 1300 | * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. |
mbed_official | 205:c41fc65bcfb4 | 1301 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 1302 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1303 | */ |
mbed_official | 205:c41fc65bcfb4 | 1304 | #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN) |
mbed_official | 205:c41fc65bcfb4 | 1305 | |
mbed_official | 205:c41fc65bcfb4 | 1306 | /** |
mbed_official | 205:c41fc65bcfb4 | 1307 | * @brief Disables the oscillator clock for frequency error counter. |
mbed_official | 205:c41fc65bcfb4 | 1308 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 1309 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1310 | */ |
mbed_official | 205:c41fc65bcfb4 | 1311 | #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN) |
mbed_official | 205:c41fc65bcfb4 | 1312 | |
mbed_official | 205:c41fc65bcfb4 | 1313 | /** |
mbed_official | 205:c41fc65bcfb4 | 1314 | * @brief Enables the automatic hardware adjustement of TRIM bits. |
mbed_official | 205:c41fc65bcfb4 | 1315 | * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. |
mbed_official | 205:c41fc65bcfb4 | 1316 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 1317 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1318 | */ |
mbed_official | 205:c41fc65bcfb4 | 1319 | #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN) |
mbed_official | 205:c41fc65bcfb4 | 1320 | |
mbed_official | 205:c41fc65bcfb4 | 1321 | /** |
mbed_official | 205:c41fc65bcfb4 | 1322 | * @brief Enables or disables the automatic hardware adjustement of TRIM bits. |
mbed_official | 205:c41fc65bcfb4 | 1323 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 1324 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1325 | */ |
mbed_official | 205:c41fc65bcfb4 | 1326 | #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN) |
mbed_official | 205:c41fc65bcfb4 | 1327 | |
mbed_official | 205:c41fc65bcfb4 | 1328 | /** |
mbed_official | 205:c41fc65bcfb4 | 1329 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
mbed_official | 205:c41fc65bcfb4 | 1330 | * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency |
mbed_official | 205:c41fc65bcfb4 | 1331 | * of the synchronization source after prescaling. It is then decreased by one in order to |
mbed_official | 205:c41fc65bcfb4 | 1332 | * reach the expected synchronization on the zero value. The formula is the following: |
mbed_official | 205:c41fc65bcfb4 | 1333 | * RELOAD = (fTARGET / fSYNC) -1 |
mbed_official | 205:c41fc65bcfb4 | 1334 | * @param _FTARGET_ Target frequency (value in Hz) |
mbed_official | 205:c41fc65bcfb4 | 1335 | * @param _FSYNC_ Synchronization signal frequency (value in Hz) |
mbed_official | 205:c41fc65bcfb4 | 1336 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1337 | */ |
mbed_official | 205:c41fc65bcfb4 | 1338 | #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1) |
mbed_official | 205:c41fc65bcfb4 | 1339 | |
mbed_official | 205:c41fc65bcfb4 | 1340 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 1341 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1342 | |
mbed_official | 205:c41fc65bcfb4 | 1343 | /** |
mbed_official | 205:c41fc65bcfb4 | 1344 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1345 | */ |
mbed_official | 205:c41fc65bcfb4 | 1346 | |
mbed_official | 205:c41fc65bcfb4 | 1347 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 1348 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
mbed_official | 205:c41fc65bcfb4 | 1349 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
mbed_official | 205:c41fc65bcfb4 | 1350 | |
mbed_official | 205:c41fc65bcfb4 | 1351 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 205:c41fc65bcfb4 | 1352 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 205:c41fc65bcfb4 | 1353 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); |
mbed_official | 205:c41fc65bcfb4 | 1354 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); |
mbed_official | 205:c41fc65bcfb4 | 1355 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); |
mbed_official | 205:c41fc65bcfb4 | 1356 | RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); |
mbed_official | 205:c41fc65bcfb4 | 1357 | #endif /* STM32F042x6 || */ |
mbed_official | 205:c41fc65bcfb4 | 1358 | /* STM32F071xB || STM32F072xB || STM32F078xx */ |
mbed_official | 205:c41fc65bcfb4 | 1359 | |
mbed_official | 205:c41fc65bcfb4 | 1360 | |
mbed_official | 205:c41fc65bcfb4 | 1361 | /** |
mbed_official | 205:c41fc65bcfb4 | 1362 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1363 | */ |
mbed_official | 205:c41fc65bcfb4 | 1364 | |
mbed_official | 205:c41fc65bcfb4 | 1365 | /** |
mbed_official | 205:c41fc65bcfb4 | 1366 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1367 | */ |
mbed_official | 205:c41fc65bcfb4 | 1368 | |
mbed_official | 205:c41fc65bcfb4 | 1369 | #ifdef __cplusplus |
mbed_official | 205:c41fc65bcfb4 | 1370 | } |
mbed_official | 205:c41fc65bcfb4 | 1371 | #endif |
mbed_official | 205:c41fc65bcfb4 | 1372 | |
mbed_official | 205:c41fc65bcfb4 | 1373 | #endif /* __STM32F0xx_HAL_RCC_EX_H */ |
mbed_official | 205:c41fc65bcfb4 | 1374 | |
mbed_official | 205:c41fc65bcfb4 | 1375 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |