mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_wdog.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_wdog.h@146:f64d43ff0c18
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_WDOG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_WDOG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 WDOG |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Generation 2008 Watchdog Timer |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_WDOG_WINH - Watchdog Window Register High |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_WDOG_WINL - Watchdog Window Register Low |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_WDOG_REFRESH - Watchdog Refresh register |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_WDOG_UNLOCK - Watchdog Unlock register |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_WDOG_RSTCNT - Watchdog Reset Count register |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_WDOG_PRESC - Watchdog Prescaler register |
mbed_official | 146:f64d43ff0c18 | 44 | * |
mbed_official | 146:f64d43ff0c18 | 45 | * - hw_wdog_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 46 | */ |
mbed_official | 146:f64d43ff0c18 | 47 | |
mbed_official | 146:f64d43ff0c18 | 48 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 49 | //@{ |
mbed_official | 146:f64d43ff0c18 | 50 | #ifndef REGS_WDOG_BASE |
mbed_official | 146:f64d43ff0c18 | 51 | #define HW_WDOG_INSTANCE_COUNT (1U) //!< Number of instances of the WDOG module. |
mbed_official | 146:f64d43ff0c18 | 52 | #define REGS_WDOG_BASE (0x40052000U) //!< Base address for WDOG. |
mbed_official | 146:f64d43ff0c18 | 53 | #endif |
mbed_official | 146:f64d43ff0c18 | 54 | //@} |
mbed_official | 146:f64d43ff0c18 | 55 | |
mbed_official | 146:f64d43ff0c18 | 56 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 57 | // HW_WDOG_STCTRLH - Watchdog Status and Control Register High |
mbed_official | 146:f64d43ff0c18 | 58 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 59 | |
mbed_official | 146:f64d43ff0c18 | 60 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 61 | /*! |
mbed_official | 146:f64d43ff0c18 | 62 | * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW) |
mbed_official | 146:f64d43ff0c18 | 63 | * |
mbed_official | 146:f64d43ff0c18 | 64 | * Reset value: 0x01D3U |
mbed_official | 146:f64d43ff0c18 | 65 | */ |
mbed_official | 146:f64d43ff0c18 | 66 | typedef union _hw_wdog_stctrlh |
mbed_official | 146:f64d43ff0c18 | 67 | { |
mbed_official | 146:f64d43ff0c18 | 68 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 69 | struct _hw_wdog_stctrlh_bitfields |
mbed_official | 146:f64d43ff0c18 | 70 | { |
mbed_official | 146:f64d43ff0c18 | 71 | uint16_t WDOGEN : 1; //!< [0] |
mbed_official | 146:f64d43ff0c18 | 72 | uint16_t CLKSRC : 1; //!< [1] |
mbed_official | 146:f64d43ff0c18 | 73 | uint16_t IRQRSTEN : 1; //!< [2] |
mbed_official | 146:f64d43ff0c18 | 74 | uint16_t WINEN : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 75 | uint16_t ALLOWUPDATE : 1; //!< [4] |
mbed_official | 146:f64d43ff0c18 | 76 | uint16_t DBGEN : 1; //!< [5] |
mbed_official | 146:f64d43ff0c18 | 77 | uint16_t STOPEN : 1; //!< [6] |
mbed_official | 146:f64d43ff0c18 | 78 | uint16_t WAITEN : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 79 | uint16_t RESERVED0 : 2; //!< [9:8] |
mbed_official | 146:f64d43ff0c18 | 80 | uint16_t TESTWDOG : 1; //!< [10] |
mbed_official | 146:f64d43ff0c18 | 81 | uint16_t TESTSEL : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 82 | uint16_t BYTESEL : 2; //!< [13:12] |
mbed_official | 146:f64d43ff0c18 | 83 | uint16_t DISTESTWDOG : 1; //!< [14] |
mbed_official | 146:f64d43ff0c18 | 84 | uint16_t RESERVED1 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 85 | } B; |
mbed_official | 146:f64d43ff0c18 | 86 | } hw_wdog_stctrlh_t; |
mbed_official | 146:f64d43ff0c18 | 87 | #endif |
mbed_official | 146:f64d43ff0c18 | 88 | |
mbed_official | 146:f64d43ff0c18 | 89 | /*! |
mbed_official | 146:f64d43ff0c18 | 90 | * @name Constants and macros for entire WDOG_STCTRLH register |
mbed_official | 146:f64d43ff0c18 | 91 | */ |
mbed_official | 146:f64d43ff0c18 | 92 | //@{ |
mbed_official | 146:f64d43ff0c18 | 93 | #define HW_WDOG_STCTRLH_ADDR (REGS_WDOG_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 94 | |
mbed_official | 146:f64d43ff0c18 | 95 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 96 | #define HW_WDOG_STCTRLH (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 97 | #define HW_WDOG_STCTRLH_RD() (HW_WDOG_STCTRLH.U) |
mbed_official | 146:f64d43ff0c18 | 98 | #define HW_WDOG_STCTRLH_WR(v) (HW_WDOG_STCTRLH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 99 | #define HW_WDOG_STCTRLH_SET(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 100 | #define HW_WDOG_STCTRLH_CLR(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 101 | #define HW_WDOG_STCTRLH_TOG(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 102 | #endif |
mbed_official | 146:f64d43ff0c18 | 103 | //@} |
mbed_official | 146:f64d43ff0c18 | 104 | |
mbed_official | 146:f64d43ff0c18 | 105 | /* |
mbed_official | 146:f64d43ff0c18 | 106 | * Constants & macros for individual WDOG_STCTRLH bitfields |
mbed_official | 146:f64d43ff0c18 | 107 | */ |
mbed_official | 146:f64d43ff0c18 | 108 | |
mbed_official | 146:f64d43ff0c18 | 109 | /*! |
mbed_official | 146:f64d43ff0c18 | 110 | * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 111 | * |
mbed_official | 146:f64d43ff0c18 | 112 | * Enables or disables the WDOG's operation. In the disabled state, the watchdog |
mbed_official | 146:f64d43ff0c18 | 113 | * timer is kept in the reset state, but the other exception conditions can |
mbed_official | 146:f64d43ff0c18 | 114 | * still trigger a reset/interrupt. A change in the value of this bit must be held |
mbed_official | 146:f64d43ff0c18 | 115 | * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. |
mbed_official | 146:f64d43ff0c18 | 116 | * |
mbed_official | 146:f64d43ff0c18 | 117 | * Values: |
mbed_official | 146:f64d43ff0c18 | 118 | * - 0 - WDOG is disabled. |
mbed_official | 146:f64d43ff0c18 | 119 | * - 1 - WDOG is enabled. |
mbed_official | 146:f64d43ff0c18 | 120 | */ |
mbed_official | 146:f64d43ff0c18 | 121 | //@{ |
mbed_official | 146:f64d43ff0c18 | 122 | #define BP_WDOG_STCTRLH_WDOGEN (0U) //!< Bit position for WDOG_STCTRLH_WDOGEN. |
mbed_official | 146:f64d43ff0c18 | 123 | #define BM_WDOG_STCTRLH_WDOGEN (0x0001U) //!< Bit mask for WDOG_STCTRLH_WDOGEN. |
mbed_official | 146:f64d43ff0c18 | 124 | #define BS_WDOG_STCTRLH_WDOGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. |
mbed_official | 146:f64d43ff0c18 | 125 | |
mbed_official | 146:f64d43ff0c18 | 126 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 127 | //! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. |
mbed_official | 146:f64d43ff0c18 | 128 | #define BR_WDOG_STCTRLH_WDOGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN)) |
mbed_official | 146:f64d43ff0c18 | 129 | #endif |
mbed_official | 146:f64d43ff0c18 | 130 | |
mbed_official | 146:f64d43ff0c18 | 131 | //! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. |
mbed_official | 146:f64d43ff0c18 | 132 | #define BF_WDOG_STCTRLH_WDOGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WDOGEN), uint16_t) & BM_WDOG_STCTRLH_WDOGEN) |
mbed_official | 146:f64d43ff0c18 | 133 | |
mbed_official | 146:f64d43ff0c18 | 134 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 135 | //! @brief Set the WDOGEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 136 | #define BW_WDOG_STCTRLH_WDOGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 137 | #endif |
mbed_official | 146:f64d43ff0c18 | 138 | //@} |
mbed_official | 146:f64d43ff0c18 | 139 | |
mbed_official | 146:f64d43ff0c18 | 140 | /*! |
mbed_official | 146:f64d43ff0c18 | 141 | * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 142 | * |
mbed_official | 146:f64d43ff0c18 | 143 | * Selects clock source for the WDOG timer and other internal timing operations. |
mbed_official | 146:f64d43ff0c18 | 144 | * |
mbed_official | 146:f64d43ff0c18 | 145 | * Values: |
mbed_official | 146:f64d43ff0c18 | 146 | * - 0 - WDOG clock sourced from LPO . |
mbed_official | 146:f64d43ff0c18 | 147 | * - 1 - WDOG clock sourced from alternate clock source. |
mbed_official | 146:f64d43ff0c18 | 148 | */ |
mbed_official | 146:f64d43ff0c18 | 149 | //@{ |
mbed_official | 146:f64d43ff0c18 | 150 | #define BP_WDOG_STCTRLH_CLKSRC (1U) //!< Bit position for WDOG_STCTRLH_CLKSRC. |
mbed_official | 146:f64d43ff0c18 | 151 | #define BM_WDOG_STCTRLH_CLKSRC (0x0002U) //!< Bit mask for WDOG_STCTRLH_CLKSRC. |
mbed_official | 146:f64d43ff0c18 | 152 | #define BS_WDOG_STCTRLH_CLKSRC (1U) //!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. |
mbed_official | 146:f64d43ff0c18 | 153 | |
mbed_official | 146:f64d43ff0c18 | 154 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 155 | //! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. |
mbed_official | 146:f64d43ff0c18 | 156 | #define BR_WDOG_STCTRLH_CLKSRC (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC)) |
mbed_official | 146:f64d43ff0c18 | 157 | #endif |
mbed_official | 146:f64d43ff0c18 | 158 | |
mbed_official | 146:f64d43ff0c18 | 159 | //! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. |
mbed_official | 146:f64d43ff0c18 | 160 | #define BF_WDOG_STCTRLH_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_CLKSRC), uint16_t) & BM_WDOG_STCTRLH_CLKSRC) |
mbed_official | 146:f64d43ff0c18 | 161 | |
mbed_official | 146:f64d43ff0c18 | 162 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 163 | //! @brief Set the CLKSRC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 164 | #define BW_WDOG_STCTRLH_CLKSRC(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 165 | #endif |
mbed_official | 146:f64d43ff0c18 | 166 | //@} |
mbed_official | 146:f64d43ff0c18 | 167 | |
mbed_official | 146:f64d43ff0c18 | 168 | /*! |
mbed_official | 146:f64d43ff0c18 | 169 | * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 170 | * |
mbed_official | 146:f64d43ff0c18 | 171 | * Used to enable the debug breadcrumbs feature. A change in this bit is updated |
mbed_official | 146:f64d43ff0c18 | 172 | * immediately, as opposed to updating after WCT. |
mbed_official | 146:f64d43ff0c18 | 173 | * |
mbed_official | 146:f64d43ff0c18 | 174 | * Values: |
mbed_official | 146:f64d43ff0c18 | 175 | * - 0 - WDOG time-out generates reset only. |
mbed_official | 146:f64d43ff0c18 | 176 | * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates |
mbed_official | 146:f64d43ff0c18 | 177 | * a reset. |
mbed_official | 146:f64d43ff0c18 | 178 | */ |
mbed_official | 146:f64d43ff0c18 | 179 | //@{ |
mbed_official | 146:f64d43ff0c18 | 180 | #define BP_WDOG_STCTRLH_IRQRSTEN (2U) //!< Bit position for WDOG_STCTRLH_IRQRSTEN. |
mbed_official | 146:f64d43ff0c18 | 181 | #define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) //!< Bit mask for WDOG_STCTRLH_IRQRSTEN. |
mbed_official | 146:f64d43ff0c18 | 182 | #define BS_WDOG_STCTRLH_IRQRSTEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. |
mbed_official | 146:f64d43ff0c18 | 183 | |
mbed_official | 146:f64d43ff0c18 | 184 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 185 | //! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. |
mbed_official | 146:f64d43ff0c18 | 186 | #define BR_WDOG_STCTRLH_IRQRSTEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN)) |
mbed_official | 146:f64d43ff0c18 | 187 | #endif |
mbed_official | 146:f64d43ff0c18 | 188 | |
mbed_official | 146:f64d43ff0c18 | 189 | //! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. |
mbed_official | 146:f64d43ff0c18 | 190 | #define BF_WDOG_STCTRLH_IRQRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_IRQRSTEN), uint16_t) & BM_WDOG_STCTRLH_IRQRSTEN) |
mbed_official | 146:f64d43ff0c18 | 191 | |
mbed_official | 146:f64d43ff0c18 | 192 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 193 | //! @brief Set the IRQRSTEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 194 | #define BW_WDOG_STCTRLH_IRQRSTEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 195 | #endif |
mbed_official | 146:f64d43ff0c18 | 196 | //@} |
mbed_official | 146:f64d43ff0c18 | 197 | |
mbed_official | 146:f64d43ff0c18 | 198 | /*! |
mbed_official | 146:f64d43ff0c18 | 199 | * @name Register WDOG_STCTRLH, field WINEN[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 200 | * |
mbed_official | 146:f64d43ff0c18 | 201 | * Enables Windowing mode. |
mbed_official | 146:f64d43ff0c18 | 202 | * |
mbed_official | 146:f64d43ff0c18 | 203 | * Values: |
mbed_official | 146:f64d43ff0c18 | 204 | * - 0 - Windowing mode is disabled. |
mbed_official | 146:f64d43ff0c18 | 205 | * - 1 - Windowing mode is enabled. |
mbed_official | 146:f64d43ff0c18 | 206 | */ |
mbed_official | 146:f64d43ff0c18 | 207 | //@{ |
mbed_official | 146:f64d43ff0c18 | 208 | #define BP_WDOG_STCTRLH_WINEN (3U) //!< Bit position for WDOG_STCTRLH_WINEN. |
mbed_official | 146:f64d43ff0c18 | 209 | #define BM_WDOG_STCTRLH_WINEN (0x0008U) //!< Bit mask for WDOG_STCTRLH_WINEN. |
mbed_official | 146:f64d43ff0c18 | 210 | #define BS_WDOG_STCTRLH_WINEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WINEN. |
mbed_official | 146:f64d43ff0c18 | 211 | |
mbed_official | 146:f64d43ff0c18 | 212 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 213 | //! @brief Read current value of the WDOG_STCTRLH_WINEN field. |
mbed_official | 146:f64d43ff0c18 | 214 | #define BR_WDOG_STCTRLH_WINEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN)) |
mbed_official | 146:f64d43ff0c18 | 215 | #endif |
mbed_official | 146:f64d43ff0c18 | 216 | |
mbed_official | 146:f64d43ff0c18 | 217 | //! @brief Format value for bitfield WDOG_STCTRLH_WINEN. |
mbed_official | 146:f64d43ff0c18 | 218 | #define BF_WDOG_STCTRLH_WINEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WINEN), uint16_t) & BM_WDOG_STCTRLH_WINEN) |
mbed_official | 146:f64d43ff0c18 | 219 | |
mbed_official | 146:f64d43ff0c18 | 220 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 221 | //! @brief Set the WINEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 222 | #define BW_WDOG_STCTRLH_WINEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 223 | #endif |
mbed_official | 146:f64d43ff0c18 | 224 | //@} |
mbed_official | 146:f64d43ff0c18 | 225 | |
mbed_official | 146:f64d43ff0c18 | 226 | /*! |
mbed_official | 146:f64d43ff0c18 | 227 | * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 228 | * |
mbed_official | 146:f64d43ff0c18 | 229 | * Enables updates to watchdog write-once registers, after the reset-triggered |
mbed_official | 146:f64d43ff0c18 | 230 | * initial configuration window (WCT) closes, through unlock sequence. |
mbed_official | 146:f64d43ff0c18 | 231 | * |
mbed_official | 146:f64d43ff0c18 | 232 | * Values: |
mbed_official | 146:f64d43ff0c18 | 233 | * - 0 - No further updates allowed to WDOG write-once registers. |
mbed_official | 146:f64d43ff0c18 | 234 | * - 1 - WDOG write-once registers can be unlocked for updating. |
mbed_official | 146:f64d43ff0c18 | 235 | */ |
mbed_official | 146:f64d43ff0c18 | 236 | //@{ |
mbed_official | 146:f64d43ff0c18 | 237 | #define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) //!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. |
mbed_official | 146:f64d43ff0c18 | 238 | #define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) //!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. |
mbed_official | 146:f64d43ff0c18 | 239 | #define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) //!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. |
mbed_official | 146:f64d43ff0c18 | 240 | |
mbed_official | 146:f64d43ff0c18 | 241 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 242 | //! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. |
mbed_official | 146:f64d43ff0c18 | 243 | #define BR_WDOG_STCTRLH_ALLOWUPDATE (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE)) |
mbed_official | 146:f64d43ff0c18 | 244 | #endif |
mbed_official | 146:f64d43ff0c18 | 245 | |
mbed_official | 146:f64d43ff0c18 | 246 | //! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. |
mbed_official | 146:f64d43ff0c18 | 247 | #define BF_WDOG_STCTRLH_ALLOWUPDATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_ALLOWUPDATE), uint16_t) & BM_WDOG_STCTRLH_ALLOWUPDATE) |
mbed_official | 146:f64d43ff0c18 | 248 | |
mbed_official | 146:f64d43ff0c18 | 249 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 250 | //! @brief Set the ALLOWUPDATE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 251 | #define BW_WDOG_STCTRLH_ALLOWUPDATE(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 252 | #endif |
mbed_official | 146:f64d43ff0c18 | 253 | //@} |
mbed_official | 146:f64d43ff0c18 | 254 | |
mbed_official | 146:f64d43ff0c18 | 255 | /*! |
mbed_official | 146:f64d43ff0c18 | 256 | * @name Register WDOG_STCTRLH, field DBGEN[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 257 | * |
mbed_official | 146:f64d43ff0c18 | 258 | * Enables or disables WDOG in Debug mode. |
mbed_official | 146:f64d43ff0c18 | 259 | * |
mbed_official | 146:f64d43ff0c18 | 260 | * Values: |
mbed_official | 146:f64d43ff0c18 | 261 | * - 0 - WDOG is disabled in CPU Debug mode. |
mbed_official | 146:f64d43ff0c18 | 262 | * - 1 - WDOG is enabled in CPU Debug mode. |
mbed_official | 146:f64d43ff0c18 | 263 | */ |
mbed_official | 146:f64d43ff0c18 | 264 | //@{ |
mbed_official | 146:f64d43ff0c18 | 265 | #define BP_WDOG_STCTRLH_DBGEN (5U) //!< Bit position for WDOG_STCTRLH_DBGEN. |
mbed_official | 146:f64d43ff0c18 | 266 | #define BM_WDOG_STCTRLH_DBGEN (0x0020U) //!< Bit mask for WDOG_STCTRLH_DBGEN. |
mbed_official | 146:f64d43ff0c18 | 267 | #define BS_WDOG_STCTRLH_DBGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_DBGEN. |
mbed_official | 146:f64d43ff0c18 | 268 | |
mbed_official | 146:f64d43ff0c18 | 269 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 270 | //! @brief Read current value of the WDOG_STCTRLH_DBGEN field. |
mbed_official | 146:f64d43ff0c18 | 271 | #define BR_WDOG_STCTRLH_DBGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN)) |
mbed_official | 146:f64d43ff0c18 | 272 | #endif |
mbed_official | 146:f64d43ff0c18 | 273 | |
mbed_official | 146:f64d43ff0c18 | 274 | //! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. |
mbed_official | 146:f64d43ff0c18 | 275 | #define BF_WDOG_STCTRLH_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DBGEN), uint16_t) & BM_WDOG_STCTRLH_DBGEN) |
mbed_official | 146:f64d43ff0c18 | 276 | |
mbed_official | 146:f64d43ff0c18 | 277 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 278 | //! @brief Set the DBGEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 279 | #define BW_WDOG_STCTRLH_DBGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 280 | #endif |
mbed_official | 146:f64d43ff0c18 | 281 | //@} |
mbed_official | 146:f64d43ff0c18 | 282 | |
mbed_official | 146:f64d43ff0c18 | 283 | /*! |
mbed_official | 146:f64d43ff0c18 | 284 | * @name Register WDOG_STCTRLH, field STOPEN[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 285 | * |
mbed_official | 146:f64d43ff0c18 | 286 | * Enables or disables WDOG in Stop mode. |
mbed_official | 146:f64d43ff0c18 | 287 | * |
mbed_official | 146:f64d43ff0c18 | 288 | * Values: |
mbed_official | 146:f64d43ff0c18 | 289 | * - 0 - WDOG is disabled in CPU Stop mode. |
mbed_official | 146:f64d43ff0c18 | 290 | * - 1 - WDOG is enabled in CPU Stop mode. |
mbed_official | 146:f64d43ff0c18 | 291 | */ |
mbed_official | 146:f64d43ff0c18 | 292 | //@{ |
mbed_official | 146:f64d43ff0c18 | 293 | #define BP_WDOG_STCTRLH_STOPEN (6U) //!< Bit position for WDOG_STCTRLH_STOPEN. |
mbed_official | 146:f64d43ff0c18 | 294 | #define BM_WDOG_STCTRLH_STOPEN (0x0040U) //!< Bit mask for WDOG_STCTRLH_STOPEN. |
mbed_official | 146:f64d43ff0c18 | 295 | #define BS_WDOG_STCTRLH_STOPEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_STOPEN. |
mbed_official | 146:f64d43ff0c18 | 296 | |
mbed_official | 146:f64d43ff0c18 | 297 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 298 | //! @brief Read current value of the WDOG_STCTRLH_STOPEN field. |
mbed_official | 146:f64d43ff0c18 | 299 | #define BR_WDOG_STCTRLH_STOPEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN)) |
mbed_official | 146:f64d43ff0c18 | 300 | #endif |
mbed_official | 146:f64d43ff0c18 | 301 | |
mbed_official | 146:f64d43ff0c18 | 302 | //! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. |
mbed_official | 146:f64d43ff0c18 | 303 | #define BF_WDOG_STCTRLH_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_STOPEN), uint16_t) & BM_WDOG_STCTRLH_STOPEN) |
mbed_official | 146:f64d43ff0c18 | 304 | |
mbed_official | 146:f64d43ff0c18 | 305 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 306 | //! @brief Set the STOPEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 307 | #define BW_WDOG_STCTRLH_STOPEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 308 | #endif |
mbed_official | 146:f64d43ff0c18 | 309 | //@} |
mbed_official | 146:f64d43ff0c18 | 310 | |
mbed_official | 146:f64d43ff0c18 | 311 | /*! |
mbed_official | 146:f64d43ff0c18 | 312 | * @name Register WDOG_STCTRLH, field WAITEN[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 313 | * |
mbed_official | 146:f64d43ff0c18 | 314 | * Enables or disables WDOG in Wait mode. |
mbed_official | 146:f64d43ff0c18 | 315 | * |
mbed_official | 146:f64d43ff0c18 | 316 | * Values: |
mbed_official | 146:f64d43ff0c18 | 317 | * - 0 - WDOG is disabled in CPU Wait mode. |
mbed_official | 146:f64d43ff0c18 | 318 | * - 1 - WDOG is enabled in CPU Wait mode. |
mbed_official | 146:f64d43ff0c18 | 319 | */ |
mbed_official | 146:f64d43ff0c18 | 320 | //@{ |
mbed_official | 146:f64d43ff0c18 | 321 | #define BP_WDOG_STCTRLH_WAITEN (7U) //!< Bit position for WDOG_STCTRLH_WAITEN. |
mbed_official | 146:f64d43ff0c18 | 322 | #define BM_WDOG_STCTRLH_WAITEN (0x0080U) //!< Bit mask for WDOG_STCTRLH_WAITEN. |
mbed_official | 146:f64d43ff0c18 | 323 | #define BS_WDOG_STCTRLH_WAITEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WAITEN. |
mbed_official | 146:f64d43ff0c18 | 324 | |
mbed_official | 146:f64d43ff0c18 | 325 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 326 | //! @brief Read current value of the WDOG_STCTRLH_WAITEN field. |
mbed_official | 146:f64d43ff0c18 | 327 | #define BR_WDOG_STCTRLH_WAITEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN)) |
mbed_official | 146:f64d43ff0c18 | 328 | #endif |
mbed_official | 146:f64d43ff0c18 | 329 | |
mbed_official | 146:f64d43ff0c18 | 330 | //! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. |
mbed_official | 146:f64d43ff0c18 | 331 | #define BF_WDOG_STCTRLH_WAITEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WAITEN), uint16_t) & BM_WDOG_STCTRLH_WAITEN) |
mbed_official | 146:f64d43ff0c18 | 332 | |
mbed_official | 146:f64d43ff0c18 | 333 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 334 | //! @brief Set the WAITEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 335 | #define BW_WDOG_STCTRLH_WAITEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 336 | #endif |
mbed_official | 146:f64d43ff0c18 | 337 | //@} |
mbed_official | 146:f64d43ff0c18 | 338 | |
mbed_official | 146:f64d43ff0c18 | 339 | /*! |
mbed_official | 146:f64d43ff0c18 | 340 | * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 341 | * |
mbed_official | 146:f64d43ff0c18 | 342 | * Puts the watchdog in the functional test mode. In this mode, the watchdog |
mbed_official | 146:f64d43ff0c18 | 343 | * timer and the associated compare and reset generation logic is tested for correct |
mbed_official | 146:f64d43ff0c18 | 344 | * operation. The clock for the timer is switched from the main watchdog clock |
mbed_official | 146:f64d43ff0c18 | 345 | * to the fast clock input for watchdog functional test. The TESTSEL bit selects |
mbed_official | 146:f64d43ff0c18 | 346 | * the test to be run. |
mbed_official | 146:f64d43ff0c18 | 347 | */ |
mbed_official | 146:f64d43ff0c18 | 348 | //@{ |
mbed_official | 146:f64d43ff0c18 | 349 | #define BP_WDOG_STCTRLH_TESTWDOG (10U) //!< Bit position for WDOG_STCTRLH_TESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 350 | #define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) //!< Bit mask for WDOG_STCTRLH_TESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 351 | #define BS_WDOG_STCTRLH_TESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 352 | |
mbed_official | 146:f64d43ff0c18 | 353 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 354 | //! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. |
mbed_official | 146:f64d43ff0c18 | 355 | #define BR_WDOG_STCTRLH_TESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG)) |
mbed_official | 146:f64d43ff0c18 | 356 | #endif |
mbed_official | 146:f64d43ff0c18 | 357 | |
mbed_official | 146:f64d43ff0c18 | 358 | //! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 359 | #define BF_WDOG_STCTRLH_TESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTWDOG), uint16_t) & BM_WDOG_STCTRLH_TESTWDOG) |
mbed_official | 146:f64d43ff0c18 | 360 | |
mbed_official | 146:f64d43ff0c18 | 361 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 362 | //! @brief Set the TESTWDOG field to a new value. |
mbed_official | 146:f64d43ff0c18 | 363 | #define BW_WDOG_STCTRLH_TESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG) = (v)) |
mbed_official | 146:f64d43ff0c18 | 364 | #endif |
mbed_official | 146:f64d43ff0c18 | 365 | //@} |
mbed_official | 146:f64d43ff0c18 | 366 | |
mbed_official | 146:f64d43ff0c18 | 367 | /*! |
mbed_official | 146:f64d43ff0c18 | 368 | * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW) |
mbed_official | 146:f64d43ff0c18 | 369 | * |
mbed_official | 146:f64d43ff0c18 | 370 | * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog |
mbed_official | 146:f64d43ff0c18 | 371 | * timer. |
mbed_official | 146:f64d43ff0c18 | 372 | * |
mbed_official | 146:f64d43ff0c18 | 373 | * Values: |
mbed_official | 146:f64d43ff0c18 | 374 | * - 0 - Quick test. The timer runs in normal operation. You can load a small |
mbed_official | 146:f64d43ff0c18 | 375 | * time-out value to do a quick test. |
mbed_official | 146:f64d43ff0c18 | 376 | * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes |
mbed_official | 146:f64d43ff0c18 | 377 | * of the timer are enabled for operation and are compared for time-out |
mbed_official | 146:f64d43ff0c18 | 378 | * against the corresponding byte of the programmed time-out value. Select the |
mbed_official | 146:f64d43ff0c18 | 379 | * byte through BYTESEL[1:0] for testing. |
mbed_official | 146:f64d43ff0c18 | 380 | */ |
mbed_official | 146:f64d43ff0c18 | 381 | //@{ |
mbed_official | 146:f64d43ff0c18 | 382 | #define BP_WDOG_STCTRLH_TESTSEL (11U) //!< Bit position for WDOG_STCTRLH_TESTSEL. |
mbed_official | 146:f64d43ff0c18 | 383 | #define BM_WDOG_STCTRLH_TESTSEL (0x0800U) //!< Bit mask for WDOG_STCTRLH_TESTSEL. |
mbed_official | 146:f64d43ff0c18 | 384 | #define BS_WDOG_STCTRLH_TESTSEL (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. |
mbed_official | 146:f64d43ff0c18 | 385 | |
mbed_official | 146:f64d43ff0c18 | 386 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 387 | //! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. |
mbed_official | 146:f64d43ff0c18 | 388 | #define BR_WDOG_STCTRLH_TESTSEL (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL)) |
mbed_official | 146:f64d43ff0c18 | 389 | #endif |
mbed_official | 146:f64d43ff0c18 | 390 | |
mbed_official | 146:f64d43ff0c18 | 391 | //! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. |
mbed_official | 146:f64d43ff0c18 | 392 | #define BF_WDOG_STCTRLH_TESTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTSEL), uint16_t) & BM_WDOG_STCTRLH_TESTSEL) |
mbed_official | 146:f64d43ff0c18 | 393 | |
mbed_official | 146:f64d43ff0c18 | 394 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 395 | //! @brief Set the TESTSEL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 396 | #define BW_WDOG_STCTRLH_TESTSEL(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 397 | #endif |
mbed_official | 146:f64d43ff0c18 | 398 | //@} |
mbed_official | 146:f64d43ff0c18 | 399 | |
mbed_official | 146:f64d43ff0c18 | 400 | /*! |
mbed_official | 146:f64d43ff0c18 | 401 | * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW) |
mbed_official | 146:f64d43ff0c18 | 402 | * |
mbed_official | 146:f64d43ff0c18 | 403 | * This 2-bit field selects the byte to be tested when the watchdog is in the |
mbed_official | 146:f64d43ff0c18 | 404 | * byte test mode. |
mbed_official | 146:f64d43ff0c18 | 405 | * |
mbed_official | 146:f64d43ff0c18 | 406 | * Values: |
mbed_official | 146:f64d43ff0c18 | 407 | * - 00 - Byte 0 selected |
mbed_official | 146:f64d43ff0c18 | 408 | * - 01 - Byte 1 selected |
mbed_official | 146:f64d43ff0c18 | 409 | * - 10 - Byte 2 selected |
mbed_official | 146:f64d43ff0c18 | 410 | * - 11 - Byte 3 selected |
mbed_official | 146:f64d43ff0c18 | 411 | */ |
mbed_official | 146:f64d43ff0c18 | 412 | //@{ |
mbed_official | 146:f64d43ff0c18 | 413 | #define BP_WDOG_STCTRLH_BYTESEL (12U) //!< Bit position for WDOG_STCTRLH_BYTESEL. |
mbed_official | 146:f64d43ff0c18 | 414 | #define BM_WDOG_STCTRLH_BYTESEL (0x3000U) //!< Bit mask for WDOG_STCTRLH_BYTESEL. |
mbed_official | 146:f64d43ff0c18 | 415 | #define BS_WDOG_STCTRLH_BYTESEL (2U) //!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. |
mbed_official | 146:f64d43ff0c18 | 416 | |
mbed_official | 146:f64d43ff0c18 | 417 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 418 | //! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. |
mbed_official | 146:f64d43ff0c18 | 419 | #define BR_WDOG_STCTRLH_BYTESEL (HW_WDOG_STCTRLH.B.BYTESEL) |
mbed_official | 146:f64d43ff0c18 | 420 | #endif |
mbed_official | 146:f64d43ff0c18 | 421 | |
mbed_official | 146:f64d43ff0c18 | 422 | //! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. |
mbed_official | 146:f64d43ff0c18 | 423 | #define BF_WDOG_STCTRLH_BYTESEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_BYTESEL), uint16_t) & BM_WDOG_STCTRLH_BYTESEL) |
mbed_official | 146:f64d43ff0c18 | 424 | |
mbed_official | 146:f64d43ff0c18 | 425 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 426 | //! @brief Set the BYTESEL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 427 | #define BW_WDOG_STCTRLH_BYTESEL(v) (HW_WDOG_STCTRLH_WR((HW_WDOG_STCTRLH_RD() & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v))) |
mbed_official | 146:f64d43ff0c18 | 428 | #endif |
mbed_official | 146:f64d43ff0c18 | 429 | //@} |
mbed_official | 146:f64d43ff0c18 | 430 | |
mbed_official | 146:f64d43ff0c18 | 431 | /*! |
mbed_official | 146:f64d43ff0c18 | 432 | * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 433 | * |
mbed_official | 146:f64d43ff0c18 | 434 | * Allows the WDOG's functional test mode to be disabled permanently. After it |
mbed_official | 146:f64d43ff0c18 | 435 | * is set, it can only be cleared by a reset. It cannot be unlocked for editing |
mbed_official | 146:f64d43ff0c18 | 436 | * after it is set. |
mbed_official | 146:f64d43ff0c18 | 437 | * |
mbed_official | 146:f64d43ff0c18 | 438 | * Values: |
mbed_official | 146:f64d43ff0c18 | 439 | * - 0 - WDOG functional test mode is not disabled. |
mbed_official | 146:f64d43ff0c18 | 440 | * - 1 - WDOG functional test mode is disabled permanently until reset. |
mbed_official | 146:f64d43ff0c18 | 441 | */ |
mbed_official | 146:f64d43ff0c18 | 442 | //@{ |
mbed_official | 146:f64d43ff0c18 | 443 | #define BP_WDOG_STCTRLH_DISTESTWDOG (14U) //!< Bit position for WDOG_STCTRLH_DISTESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 444 | #define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) //!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 445 | #define BS_WDOG_STCTRLH_DISTESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 446 | |
mbed_official | 146:f64d43ff0c18 | 447 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 448 | //! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. |
mbed_official | 146:f64d43ff0c18 | 449 | #define BR_WDOG_STCTRLH_DISTESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG)) |
mbed_official | 146:f64d43ff0c18 | 450 | #endif |
mbed_official | 146:f64d43ff0c18 | 451 | |
mbed_official | 146:f64d43ff0c18 | 452 | //! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. |
mbed_official | 146:f64d43ff0c18 | 453 | #define BF_WDOG_STCTRLH_DISTESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DISTESTWDOG), uint16_t) & BM_WDOG_STCTRLH_DISTESTWDOG) |
mbed_official | 146:f64d43ff0c18 | 454 | |
mbed_official | 146:f64d43ff0c18 | 455 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 456 | //! @brief Set the DISTESTWDOG field to a new value. |
mbed_official | 146:f64d43ff0c18 | 457 | #define BW_WDOG_STCTRLH_DISTESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG) = (v)) |
mbed_official | 146:f64d43ff0c18 | 458 | #endif |
mbed_official | 146:f64d43ff0c18 | 459 | //@} |
mbed_official | 146:f64d43ff0c18 | 460 | |
mbed_official | 146:f64d43ff0c18 | 461 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 462 | // HW_WDOG_STCTRLL - Watchdog Status and Control Register Low |
mbed_official | 146:f64d43ff0c18 | 463 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 464 | |
mbed_official | 146:f64d43ff0c18 | 465 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 466 | /*! |
mbed_official | 146:f64d43ff0c18 | 467 | * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW) |
mbed_official | 146:f64d43ff0c18 | 468 | * |
mbed_official | 146:f64d43ff0c18 | 469 | * Reset value: 0x0001U |
mbed_official | 146:f64d43ff0c18 | 470 | */ |
mbed_official | 146:f64d43ff0c18 | 471 | typedef union _hw_wdog_stctrll |
mbed_official | 146:f64d43ff0c18 | 472 | { |
mbed_official | 146:f64d43ff0c18 | 473 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 474 | struct _hw_wdog_stctrll_bitfields |
mbed_official | 146:f64d43ff0c18 | 475 | { |
mbed_official | 146:f64d43ff0c18 | 476 | uint16_t RESERVED0 : 15; //!< [14:0] |
mbed_official | 146:f64d43ff0c18 | 477 | uint16_t INTFLG : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 478 | } B; |
mbed_official | 146:f64d43ff0c18 | 479 | } hw_wdog_stctrll_t; |
mbed_official | 146:f64d43ff0c18 | 480 | #endif |
mbed_official | 146:f64d43ff0c18 | 481 | |
mbed_official | 146:f64d43ff0c18 | 482 | /*! |
mbed_official | 146:f64d43ff0c18 | 483 | * @name Constants and macros for entire WDOG_STCTRLL register |
mbed_official | 146:f64d43ff0c18 | 484 | */ |
mbed_official | 146:f64d43ff0c18 | 485 | //@{ |
mbed_official | 146:f64d43ff0c18 | 486 | #define HW_WDOG_STCTRLL_ADDR (REGS_WDOG_BASE + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 487 | |
mbed_official | 146:f64d43ff0c18 | 488 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 489 | #define HW_WDOG_STCTRLL (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 490 | #define HW_WDOG_STCTRLL_RD() (HW_WDOG_STCTRLL.U) |
mbed_official | 146:f64d43ff0c18 | 491 | #define HW_WDOG_STCTRLL_WR(v) (HW_WDOG_STCTRLL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 492 | #define HW_WDOG_STCTRLL_SET(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 493 | #define HW_WDOG_STCTRLL_CLR(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 494 | #define HW_WDOG_STCTRLL_TOG(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 495 | #endif |
mbed_official | 146:f64d43ff0c18 | 496 | //@} |
mbed_official | 146:f64d43ff0c18 | 497 | |
mbed_official | 146:f64d43ff0c18 | 498 | /* |
mbed_official | 146:f64d43ff0c18 | 499 | * Constants & macros for individual WDOG_STCTRLL bitfields |
mbed_official | 146:f64d43ff0c18 | 500 | */ |
mbed_official | 146:f64d43ff0c18 | 501 | |
mbed_official | 146:f64d43ff0c18 | 502 | /*! |
mbed_official | 146:f64d43ff0c18 | 503 | * @name Register WDOG_STCTRLL, field INTFLG[15] (RW) |
mbed_official | 146:f64d43ff0c18 | 504 | * |
mbed_official | 146:f64d43ff0c18 | 505 | * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a |
mbed_official | 146:f64d43ff0c18 | 506 | * precondition to set this flag. INTFLG = 1 results in an interrupt being issued |
mbed_official | 146:f64d43ff0c18 | 507 | * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this |
mbed_official | 146:f64d43ff0c18 | 508 | * bit. It also gets cleared on a system reset. |
mbed_official | 146:f64d43ff0c18 | 509 | */ |
mbed_official | 146:f64d43ff0c18 | 510 | //@{ |
mbed_official | 146:f64d43ff0c18 | 511 | #define BP_WDOG_STCTRLL_INTFLG (15U) //!< Bit position for WDOG_STCTRLL_INTFLG. |
mbed_official | 146:f64d43ff0c18 | 512 | #define BM_WDOG_STCTRLL_INTFLG (0x8000U) //!< Bit mask for WDOG_STCTRLL_INTFLG. |
mbed_official | 146:f64d43ff0c18 | 513 | #define BS_WDOG_STCTRLL_INTFLG (1U) //!< Bit field size in bits for WDOG_STCTRLL_INTFLG. |
mbed_official | 146:f64d43ff0c18 | 514 | |
mbed_official | 146:f64d43ff0c18 | 515 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 516 | //! @brief Read current value of the WDOG_STCTRLL_INTFLG field. |
mbed_official | 146:f64d43ff0c18 | 517 | #define BR_WDOG_STCTRLL_INTFLG (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG)) |
mbed_official | 146:f64d43ff0c18 | 518 | #endif |
mbed_official | 146:f64d43ff0c18 | 519 | |
mbed_official | 146:f64d43ff0c18 | 520 | //! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. |
mbed_official | 146:f64d43ff0c18 | 521 | #define BF_WDOG_STCTRLL_INTFLG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLL_INTFLG), uint16_t) & BM_WDOG_STCTRLL_INTFLG) |
mbed_official | 146:f64d43ff0c18 | 522 | |
mbed_official | 146:f64d43ff0c18 | 523 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 524 | //! @brief Set the INTFLG field to a new value. |
mbed_official | 146:f64d43ff0c18 | 525 | #define BW_WDOG_STCTRLL_INTFLG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG) = (v)) |
mbed_official | 146:f64d43ff0c18 | 526 | #endif |
mbed_official | 146:f64d43ff0c18 | 527 | //@} |
mbed_official | 146:f64d43ff0c18 | 528 | |
mbed_official | 146:f64d43ff0c18 | 529 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 530 | // HW_WDOG_TOVALH - Watchdog Time-out Value Register High |
mbed_official | 146:f64d43ff0c18 | 531 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 532 | |
mbed_official | 146:f64d43ff0c18 | 533 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 534 | /*! |
mbed_official | 146:f64d43ff0c18 | 535 | * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW) |
mbed_official | 146:f64d43ff0c18 | 536 | * |
mbed_official | 146:f64d43ff0c18 | 537 | * Reset value: 0x004CU |
mbed_official | 146:f64d43ff0c18 | 538 | */ |
mbed_official | 146:f64d43ff0c18 | 539 | typedef union _hw_wdog_tovalh |
mbed_official | 146:f64d43ff0c18 | 540 | { |
mbed_official | 146:f64d43ff0c18 | 541 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 542 | struct _hw_wdog_tovalh_bitfields |
mbed_official | 146:f64d43ff0c18 | 543 | { |
mbed_official | 146:f64d43ff0c18 | 544 | uint16_t TOVALHIGH : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 545 | } B; |
mbed_official | 146:f64d43ff0c18 | 546 | } hw_wdog_tovalh_t; |
mbed_official | 146:f64d43ff0c18 | 547 | #endif |
mbed_official | 146:f64d43ff0c18 | 548 | |
mbed_official | 146:f64d43ff0c18 | 549 | /*! |
mbed_official | 146:f64d43ff0c18 | 550 | * @name Constants and macros for entire WDOG_TOVALH register |
mbed_official | 146:f64d43ff0c18 | 551 | */ |
mbed_official | 146:f64d43ff0c18 | 552 | //@{ |
mbed_official | 146:f64d43ff0c18 | 553 | #define HW_WDOG_TOVALH_ADDR (REGS_WDOG_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 554 | |
mbed_official | 146:f64d43ff0c18 | 555 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 556 | #define HW_WDOG_TOVALH (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 557 | #define HW_WDOG_TOVALH_RD() (HW_WDOG_TOVALH.U) |
mbed_official | 146:f64d43ff0c18 | 558 | #define HW_WDOG_TOVALH_WR(v) (HW_WDOG_TOVALH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 559 | #define HW_WDOG_TOVALH_SET(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 560 | #define HW_WDOG_TOVALH_CLR(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 561 | #define HW_WDOG_TOVALH_TOG(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 562 | #endif |
mbed_official | 146:f64d43ff0c18 | 563 | //@} |
mbed_official | 146:f64d43ff0c18 | 564 | |
mbed_official | 146:f64d43ff0c18 | 565 | /* |
mbed_official | 146:f64d43ff0c18 | 566 | * Constants & macros for individual WDOG_TOVALH bitfields |
mbed_official | 146:f64d43ff0c18 | 567 | */ |
mbed_official | 146:f64d43ff0c18 | 568 | |
mbed_official | 146:f64d43ff0c18 | 569 | /*! |
mbed_official | 146:f64d43ff0c18 | 570 | * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 571 | * |
mbed_official | 146:f64d43ff0c18 | 572 | * Defines the upper 16 bits of the 32-bit time-out value for the watchdog |
mbed_official | 146:f64d43ff0c18 | 573 | * timer. It is defined in terms of cycles of the watchdog clock. |
mbed_official | 146:f64d43ff0c18 | 574 | */ |
mbed_official | 146:f64d43ff0c18 | 575 | //@{ |
mbed_official | 146:f64d43ff0c18 | 576 | #define BP_WDOG_TOVALH_TOVALHIGH (0U) //!< Bit position for WDOG_TOVALH_TOVALHIGH. |
mbed_official | 146:f64d43ff0c18 | 577 | #define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) //!< Bit mask for WDOG_TOVALH_TOVALHIGH. |
mbed_official | 146:f64d43ff0c18 | 578 | #define BS_WDOG_TOVALH_TOVALHIGH (16U) //!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. |
mbed_official | 146:f64d43ff0c18 | 579 | |
mbed_official | 146:f64d43ff0c18 | 580 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 581 | //! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. |
mbed_official | 146:f64d43ff0c18 | 582 | #define BR_WDOG_TOVALH_TOVALHIGH (HW_WDOG_TOVALH.U) |
mbed_official | 146:f64d43ff0c18 | 583 | #endif |
mbed_official | 146:f64d43ff0c18 | 584 | |
mbed_official | 146:f64d43ff0c18 | 585 | //! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. |
mbed_official | 146:f64d43ff0c18 | 586 | #define BF_WDOG_TOVALH_TOVALHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALH_TOVALHIGH), uint16_t) & BM_WDOG_TOVALH_TOVALHIGH) |
mbed_official | 146:f64d43ff0c18 | 587 | |
mbed_official | 146:f64d43ff0c18 | 588 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 589 | //! @brief Set the TOVALHIGH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 590 | #define BW_WDOG_TOVALH_TOVALHIGH(v) (HW_WDOG_TOVALH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 591 | #endif |
mbed_official | 146:f64d43ff0c18 | 592 | //@} |
mbed_official | 146:f64d43ff0c18 | 593 | |
mbed_official | 146:f64d43ff0c18 | 594 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 595 | // HW_WDOG_TOVALL - Watchdog Time-out Value Register Low |
mbed_official | 146:f64d43ff0c18 | 596 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 597 | |
mbed_official | 146:f64d43ff0c18 | 598 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 599 | /*! |
mbed_official | 146:f64d43ff0c18 | 600 | * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW) |
mbed_official | 146:f64d43ff0c18 | 601 | * |
mbed_official | 146:f64d43ff0c18 | 602 | * Reset value: 0x4B4CU |
mbed_official | 146:f64d43ff0c18 | 603 | * |
mbed_official | 146:f64d43ff0c18 | 604 | * The time-out value of the watchdog must be set to a minimum of four watchdog |
mbed_official | 146:f64d43ff0c18 | 605 | * clock cycles. This is to take into account the delay in new settings taking |
mbed_official | 146:f64d43ff0c18 | 606 | * effect in the watchdog clock domain. |
mbed_official | 146:f64d43ff0c18 | 607 | */ |
mbed_official | 146:f64d43ff0c18 | 608 | typedef union _hw_wdog_tovall |
mbed_official | 146:f64d43ff0c18 | 609 | { |
mbed_official | 146:f64d43ff0c18 | 610 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 611 | struct _hw_wdog_tovall_bitfields |
mbed_official | 146:f64d43ff0c18 | 612 | { |
mbed_official | 146:f64d43ff0c18 | 613 | uint16_t TOVALLOW : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 614 | } B; |
mbed_official | 146:f64d43ff0c18 | 615 | } hw_wdog_tovall_t; |
mbed_official | 146:f64d43ff0c18 | 616 | #endif |
mbed_official | 146:f64d43ff0c18 | 617 | |
mbed_official | 146:f64d43ff0c18 | 618 | /*! |
mbed_official | 146:f64d43ff0c18 | 619 | * @name Constants and macros for entire WDOG_TOVALL register |
mbed_official | 146:f64d43ff0c18 | 620 | */ |
mbed_official | 146:f64d43ff0c18 | 621 | //@{ |
mbed_official | 146:f64d43ff0c18 | 622 | #define HW_WDOG_TOVALL_ADDR (REGS_WDOG_BASE + 0x6U) |
mbed_official | 146:f64d43ff0c18 | 623 | |
mbed_official | 146:f64d43ff0c18 | 624 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 625 | #define HW_WDOG_TOVALL (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 626 | #define HW_WDOG_TOVALL_RD() (HW_WDOG_TOVALL.U) |
mbed_official | 146:f64d43ff0c18 | 627 | #define HW_WDOG_TOVALL_WR(v) (HW_WDOG_TOVALL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 628 | #define HW_WDOG_TOVALL_SET(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 629 | #define HW_WDOG_TOVALL_CLR(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 630 | #define HW_WDOG_TOVALL_TOG(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 631 | #endif |
mbed_official | 146:f64d43ff0c18 | 632 | //@} |
mbed_official | 146:f64d43ff0c18 | 633 | |
mbed_official | 146:f64d43ff0c18 | 634 | /* |
mbed_official | 146:f64d43ff0c18 | 635 | * Constants & macros for individual WDOG_TOVALL bitfields |
mbed_official | 146:f64d43ff0c18 | 636 | */ |
mbed_official | 146:f64d43ff0c18 | 637 | |
mbed_official | 146:f64d43ff0c18 | 638 | /*! |
mbed_official | 146:f64d43ff0c18 | 639 | * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 640 | * |
mbed_official | 146:f64d43ff0c18 | 641 | * Defines the lower 16 bits of the 32-bit time-out value for the watchdog |
mbed_official | 146:f64d43ff0c18 | 642 | * timer. It is defined in terms of cycles of the watchdog clock. |
mbed_official | 146:f64d43ff0c18 | 643 | */ |
mbed_official | 146:f64d43ff0c18 | 644 | //@{ |
mbed_official | 146:f64d43ff0c18 | 645 | #define BP_WDOG_TOVALL_TOVALLOW (0U) //!< Bit position for WDOG_TOVALL_TOVALLOW. |
mbed_official | 146:f64d43ff0c18 | 646 | #define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) //!< Bit mask for WDOG_TOVALL_TOVALLOW. |
mbed_official | 146:f64d43ff0c18 | 647 | #define BS_WDOG_TOVALL_TOVALLOW (16U) //!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. |
mbed_official | 146:f64d43ff0c18 | 648 | |
mbed_official | 146:f64d43ff0c18 | 649 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 650 | //! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. |
mbed_official | 146:f64d43ff0c18 | 651 | #define BR_WDOG_TOVALL_TOVALLOW (HW_WDOG_TOVALL.U) |
mbed_official | 146:f64d43ff0c18 | 652 | #endif |
mbed_official | 146:f64d43ff0c18 | 653 | |
mbed_official | 146:f64d43ff0c18 | 654 | //! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. |
mbed_official | 146:f64d43ff0c18 | 655 | #define BF_WDOG_TOVALL_TOVALLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALL_TOVALLOW), uint16_t) & BM_WDOG_TOVALL_TOVALLOW) |
mbed_official | 146:f64d43ff0c18 | 656 | |
mbed_official | 146:f64d43ff0c18 | 657 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 658 | //! @brief Set the TOVALLOW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 659 | #define BW_WDOG_TOVALL_TOVALLOW(v) (HW_WDOG_TOVALL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 660 | #endif |
mbed_official | 146:f64d43ff0c18 | 661 | //@} |
mbed_official | 146:f64d43ff0c18 | 662 | |
mbed_official | 146:f64d43ff0c18 | 663 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 664 | // HW_WDOG_WINH - Watchdog Window Register High |
mbed_official | 146:f64d43ff0c18 | 665 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 666 | |
mbed_official | 146:f64d43ff0c18 | 667 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 668 | /*! |
mbed_official | 146:f64d43ff0c18 | 669 | * @brief HW_WDOG_WINH - Watchdog Window Register High (RW) |
mbed_official | 146:f64d43ff0c18 | 670 | * |
mbed_official | 146:f64d43ff0c18 | 671 | * Reset value: 0x0000U |
mbed_official | 146:f64d43ff0c18 | 672 | * |
mbed_official | 146:f64d43ff0c18 | 673 | * You must set the Window Register value lower than the Time-out Value Register. |
mbed_official | 146:f64d43ff0c18 | 674 | */ |
mbed_official | 146:f64d43ff0c18 | 675 | typedef union _hw_wdog_winh |
mbed_official | 146:f64d43ff0c18 | 676 | { |
mbed_official | 146:f64d43ff0c18 | 677 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 678 | struct _hw_wdog_winh_bitfields |
mbed_official | 146:f64d43ff0c18 | 679 | { |
mbed_official | 146:f64d43ff0c18 | 680 | uint16_t WINHIGH : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 681 | } B; |
mbed_official | 146:f64d43ff0c18 | 682 | } hw_wdog_winh_t; |
mbed_official | 146:f64d43ff0c18 | 683 | #endif |
mbed_official | 146:f64d43ff0c18 | 684 | |
mbed_official | 146:f64d43ff0c18 | 685 | /*! |
mbed_official | 146:f64d43ff0c18 | 686 | * @name Constants and macros for entire WDOG_WINH register |
mbed_official | 146:f64d43ff0c18 | 687 | */ |
mbed_official | 146:f64d43ff0c18 | 688 | //@{ |
mbed_official | 146:f64d43ff0c18 | 689 | #define HW_WDOG_WINH_ADDR (REGS_WDOG_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 690 | |
mbed_official | 146:f64d43ff0c18 | 691 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 692 | #define HW_WDOG_WINH (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 693 | #define HW_WDOG_WINH_RD() (HW_WDOG_WINH.U) |
mbed_official | 146:f64d43ff0c18 | 694 | #define HW_WDOG_WINH_WR(v) (HW_WDOG_WINH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 695 | #define HW_WDOG_WINH_SET(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 696 | #define HW_WDOG_WINH_CLR(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 697 | #define HW_WDOG_WINH_TOG(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 698 | #endif |
mbed_official | 146:f64d43ff0c18 | 699 | //@} |
mbed_official | 146:f64d43ff0c18 | 700 | |
mbed_official | 146:f64d43ff0c18 | 701 | /* |
mbed_official | 146:f64d43ff0c18 | 702 | * Constants & macros for individual WDOG_WINH bitfields |
mbed_official | 146:f64d43ff0c18 | 703 | */ |
mbed_official | 146:f64d43ff0c18 | 704 | |
mbed_official | 146:f64d43ff0c18 | 705 | /*! |
mbed_official | 146:f64d43ff0c18 | 706 | * @name Register WDOG_WINH, field WINHIGH[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 707 | * |
mbed_official | 146:f64d43ff0c18 | 708 | * Defines the upper 16 bits of the 32-bit window for the windowed mode of |
mbed_official | 146:f64d43ff0c18 | 709 | * operation of the watchdog. It is defined in terms of cycles of the watchdog clock. |
mbed_official | 146:f64d43ff0c18 | 710 | * In this mode, the watchdog can be refreshed only when the timer has reached a |
mbed_official | 146:f64d43ff0c18 | 711 | * value greater than or equal to this window length. A refresh outside this |
mbed_official | 146:f64d43ff0c18 | 712 | * window resets the system or if IRQRSTEN is set, it interrupts and then resets the |
mbed_official | 146:f64d43ff0c18 | 713 | * system. |
mbed_official | 146:f64d43ff0c18 | 714 | */ |
mbed_official | 146:f64d43ff0c18 | 715 | //@{ |
mbed_official | 146:f64d43ff0c18 | 716 | #define BP_WDOG_WINH_WINHIGH (0U) //!< Bit position for WDOG_WINH_WINHIGH. |
mbed_official | 146:f64d43ff0c18 | 717 | #define BM_WDOG_WINH_WINHIGH (0xFFFFU) //!< Bit mask for WDOG_WINH_WINHIGH. |
mbed_official | 146:f64d43ff0c18 | 718 | #define BS_WDOG_WINH_WINHIGH (16U) //!< Bit field size in bits for WDOG_WINH_WINHIGH. |
mbed_official | 146:f64d43ff0c18 | 719 | |
mbed_official | 146:f64d43ff0c18 | 720 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 721 | //! @brief Read current value of the WDOG_WINH_WINHIGH field. |
mbed_official | 146:f64d43ff0c18 | 722 | #define BR_WDOG_WINH_WINHIGH (HW_WDOG_WINH.U) |
mbed_official | 146:f64d43ff0c18 | 723 | #endif |
mbed_official | 146:f64d43ff0c18 | 724 | |
mbed_official | 146:f64d43ff0c18 | 725 | //! @brief Format value for bitfield WDOG_WINH_WINHIGH. |
mbed_official | 146:f64d43ff0c18 | 726 | #define BF_WDOG_WINH_WINHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINH_WINHIGH), uint16_t) & BM_WDOG_WINH_WINHIGH) |
mbed_official | 146:f64d43ff0c18 | 727 | |
mbed_official | 146:f64d43ff0c18 | 728 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 729 | //! @brief Set the WINHIGH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 730 | #define BW_WDOG_WINH_WINHIGH(v) (HW_WDOG_WINH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 731 | #endif |
mbed_official | 146:f64d43ff0c18 | 732 | //@} |
mbed_official | 146:f64d43ff0c18 | 733 | |
mbed_official | 146:f64d43ff0c18 | 734 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 735 | // HW_WDOG_WINL - Watchdog Window Register Low |
mbed_official | 146:f64d43ff0c18 | 736 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 737 | |
mbed_official | 146:f64d43ff0c18 | 738 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 739 | /*! |
mbed_official | 146:f64d43ff0c18 | 740 | * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW) |
mbed_official | 146:f64d43ff0c18 | 741 | * |
mbed_official | 146:f64d43ff0c18 | 742 | * Reset value: 0x0010U |
mbed_official | 146:f64d43ff0c18 | 743 | * |
mbed_official | 146:f64d43ff0c18 | 744 | * You must set the Window Register value lower than the Time-out Value Register. |
mbed_official | 146:f64d43ff0c18 | 745 | */ |
mbed_official | 146:f64d43ff0c18 | 746 | typedef union _hw_wdog_winl |
mbed_official | 146:f64d43ff0c18 | 747 | { |
mbed_official | 146:f64d43ff0c18 | 748 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 749 | struct _hw_wdog_winl_bitfields |
mbed_official | 146:f64d43ff0c18 | 750 | { |
mbed_official | 146:f64d43ff0c18 | 751 | uint16_t WINLOW : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 752 | } B; |
mbed_official | 146:f64d43ff0c18 | 753 | } hw_wdog_winl_t; |
mbed_official | 146:f64d43ff0c18 | 754 | #endif |
mbed_official | 146:f64d43ff0c18 | 755 | |
mbed_official | 146:f64d43ff0c18 | 756 | /*! |
mbed_official | 146:f64d43ff0c18 | 757 | * @name Constants and macros for entire WDOG_WINL register |
mbed_official | 146:f64d43ff0c18 | 758 | */ |
mbed_official | 146:f64d43ff0c18 | 759 | //@{ |
mbed_official | 146:f64d43ff0c18 | 760 | #define HW_WDOG_WINL_ADDR (REGS_WDOG_BASE + 0xAU) |
mbed_official | 146:f64d43ff0c18 | 761 | |
mbed_official | 146:f64d43ff0c18 | 762 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 763 | #define HW_WDOG_WINL (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 764 | #define HW_WDOG_WINL_RD() (HW_WDOG_WINL.U) |
mbed_official | 146:f64d43ff0c18 | 765 | #define HW_WDOG_WINL_WR(v) (HW_WDOG_WINL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 766 | #define HW_WDOG_WINL_SET(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 767 | #define HW_WDOG_WINL_CLR(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 768 | #define HW_WDOG_WINL_TOG(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 769 | #endif |
mbed_official | 146:f64d43ff0c18 | 770 | //@} |
mbed_official | 146:f64d43ff0c18 | 771 | |
mbed_official | 146:f64d43ff0c18 | 772 | /* |
mbed_official | 146:f64d43ff0c18 | 773 | * Constants & macros for individual WDOG_WINL bitfields |
mbed_official | 146:f64d43ff0c18 | 774 | */ |
mbed_official | 146:f64d43ff0c18 | 775 | |
mbed_official | 146:f64d43ff0c18 | 776 | /*! |
mbed_official | 146:f64d43ff0c18 | 777 | * @name Register WDOG_WINL, field WINLOW[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 778 | * |
mbed_official | 146:f64d43ff0c18 | 779 | * Defines the lower 16 bits of the 32-bit window for the windowed mode of |
mbed_official | 146:f64d43ff0c18 | 780 | * operation of the watchdog. It is defined in terms of cycles of the pre-scaled |
mbed_official | 146:f64d43ff0c18 | 781 | * watchdog clock. In this mode, the watchdog can be refreshed only when the timer |
mbed_official | 146:f64d43ff0c18 | 782 | * reaches a value greater than or equal to this window length value. A refresh |
mbed_official | 146:f64d43ff0c18 | 783 | * outside of this window resets the system or if IRQRSTEN is set, it interrupts and |
mbed_official | 146:f64d43ff0c18 | 784 | * then resets the system. |
mbed_official | 146:f64d43ff0c18 | 785 | */ |
mbed_official | 146:f64d43ff0c18 | 786 | //@{ |
mbed_official | 146:f64d43ff0c18 | 787 | #define BP_WDOG_WINL_WINLOW (0U) //!< Bit position for WDOG_WINL_WINLOW. |
mbed_official | 146:f64d43ff0c18 | 788 | #define BM_WDOG_WINL_WINLOW (0xFFFFU) //!< Bit mask for WDOG_WINL_WINLOW. |
mbed_official | 146:f64d43ff0c18 | 789 | #define BS_WDOG_WINL_WINLOW (16U) //!< Bit field size in bits for WDOG_WINL_WINLOW. |
mbed_official | 146:f64d43ff0c18 | 790 | |
mbed_official | 146:f64d43ff0c18 | 791 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 792 | //! @brief Read current value of the WDOG_WINL_WINLOW field. |
mbed_official | 146:f64d43ff0c18 | 793 | #define BR_WDOG_WINL_WINLOW (HW_WDOG_WINL.U) |
mbed_official | 146:f64d43ff0c18 | 794 | #endif |
mbed_official | 146:f64d43ff0c18 | 795 | |
mbed_official | 146:f64d43ff0c18 | 796 | //! @brief Format value for bitfield WDOG_WINL_WINLOW. |
mbed_official | 146:f64d43ff0c18 | 797 | #define BF_WDOG_WINL_WINLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINL_WINLOW), uint16_t) & BM_WDOG_WINL_WINLOW) |
mbed_official | 146:f64d43ff0c18 | 798 | |
mbed_official | 146:f64d43ff0c18 | 799 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 800 | //! @brief Set the WINLOW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 801 | #define BW_WDOG_WINL_WINLOW(v) (HW_WDOG_WINL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 802 | #endif |
mbed_official | 146:f64d43ff0c18 | 803 | //@} |
mbed_official | 146:f64d43ff0c18 | 804 | |
mbed_official | 146:f64d43ff0c18 | 805 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 806 | // HW_WDOG_REFRESH - Watchdog Refresh register |
mbed_official | 146:f64d43ff0c18 | 807 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 808 | |
mbed_official | 146:f64d43ff0c18 | 809 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 810 | /*! |
mbed_official | 146:f64d43ff0c18 | 811 | * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW) |
mbed_official | 146:f64d43ff0c18 | 812 | * |
mbed_official | 146:f64d43ff0c18 | 813 | * Reset value: 0xB480U |
mbed_official | 146:f64d43ff0c18 | 814 | */ |
mbed_official | 146:f64d43ff0c18 | 815 | typedef union _hw_wdog_refresh |
mbed_official | 146:f64d43ff0c18 | 816 | { |
mbed_official | 146:f64d43ff0c18 | 817 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 818 | struct _hw_wdog_refresh_bitfields |
mbed_official | 146:f64d43ff0c18 | 819 | { |
mbed_official | 146:f64d43ff0c18 | 820 | uint16_t WDOGREFRESH : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 821 | } B; |
mbed_official | 146:f64d43ff0c18 | 822 | } hw_wdog_refresh_t; |
mbed_official | 146:f64d43ff0c18 | 823 | #endif |
mbed_official | 146:f64d43ff0c18 | 824 | |
mbed_official | 146:f64d43ff0c18 | 825 | /*! |
mbed_official | 146:f64d43ff0c18 | 826 | * @name Constants and macros for entire WDOG_REFRESH register |
mbed_official | 146:f64d43ff0c18 | 827 | */ |
mbed_official | 146:f64d43ff0c18 | 828 | //@{ |
mbed_official | 146:f64d43ff0c18 | 829 | #define HW_WDOG_REFRESH_ADDR (REGS_WDOG_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 830 | |
mbed_official | 146:f64d43ff0c18 | 831 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 832 | #define HW_WDOG_REFRESH (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 833 | #define HW_WDOG_REFRESH_RD() (HW_WDOG_REFRESH.U) |
mbed_official | 146:f64d43ff0c18 | 834 | #define HW_WDOG_REFRESH_WR(v) (HW_WDOG_REFRESH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 835 | #define HW_WDOG_REFRESH_SET(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 836 | #define HW_WDOG_REFRESH_CLR(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 837 | #define HW_WDOG_REFRESH_TOG(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 838 | #endif |
mbed_official | 146:f64d43ff0c18 | 839 | //@} |
mbed_official | 146:f64d43ff0c18 | 840 | |
mbed_official | 146:f64d43ff0c18 | 841 | /* |
mbed_official | 146:f64d43ff0c18 | 842 | * Constants & macros for individual WDOG_REFRESH bitfields |
mbed_official | 146:f64d43ff0c18 | 843 | */ |
mbed_official | 146:f64d43ff0c18 | 844 | |
mbed_official | 146:f64d43ff0c18 | 845 | /*! |
mbed_official | 146:f64d43ff0c18 | 846 | * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 847 | * |
mbed_official | 146:f64d43ff0c18 | 848 | * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 |
mbed_official | 146:f64d43ff0c18 | 849 | * bus clock cycles written to this register refreshes the WDOG and prevents it |
mbed_official | 146:f64d43ff0c18 | 850 | * from resetting the system. Writing a value other than the above mentioned |
mbed_official | 146:f64d43ff0c18 | 851 | * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if |
mbed_official | 146:f64d43ff0c18 | 852 | * IRQRSTEN is set, it interrupts and then resets the system. |
mbed_official | 146:f64d43ff0c18 | 853 | */ |
mbed_official | 146:f64d43ff0c18 | 854 | //@{ |
mbed_official | 146:f64d43ff0c18 | 855 | #define BP_WDOG_REFRESH_WDOGREFRESH (0U) //!< Bit position for WDOG_REFRESH_WDOGREFRESH. |
mbed_official | 146:f64d43ff0c18 | 856 | #define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) //!< Bit mask for WDOG_REFRESH_WDOGREFRESH. |
mbed_official | 146:f64d43ff0c18 | 857 | #define BS_WDOG_REFRESH_WDOGREFRESH (16U) //!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. |
mbed_official | 146:f64d43ff0c18 | 858 | |
mbed_official | 146:f64d43ff0c18 | 859 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 860 | //! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. |
mbed_official | 146:f64d43ff0c18 | 861 | #define BR_WDOG_REFRESH_WDOGREFRESH (HW_WDOG_REFRESH.U) |
mbed_official | 146:f64d43ff0c18 | 862 | #endif |
mbed_official | 146:f64d43ff0c18 | 863 | |
mbed_official | 146:f64d43ff0c18 | 864 | //! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. |
mbed_official | 146:f64d43ff0c18 | 865 | #define BF_WDOG_REFRESH_WDOGREFRESH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_REFRESH_WDOGREFRESH), uint16_t) & BM_WDOG_REFRESH_WDOGREFRESH) |
mbed_official | 146:f64d43ff0c18 | 866 | |
mbed_official | 146:f64d43ff0c18 | 867 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 868 | //! @brief Set the WDOGREFRESH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 869 | #define BW_WDOG_REFRESH_WDOGREFRESH(v) (HW_WDOG_REFRESH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 870 | #endif |
mbed_official | 146:f64d43ff0c18 | 871 | //@} |
mbed_official | 146:f64d43ff0c18 | 872 | |
mbed_official | 146:f64d43ff0c18 | 873 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 874 | // HW_WDOG_UNLOCK - Watchdog Unlock register |
mbed_official | 146:f64d43ff0c18 | 875 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 876 | |
mbed_official | 146:f64d43ff0c18 | 877 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 878 | /*! |
mbed_official | 146:f64d43ff0c18 | 879 | * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW) |
mbed_official | 146:f64d43ff0c18 | 880 | * |
mbed_official | 146:f64d43ff0c18 | 881 | * Reset value: 0xD928U |
mbed_official | 146:f64d43ff0c18 | 882 | */ |
mbed_official | 146:f64d43ff0c18 | 883 | typedef union _hw_wdog_unlock |
mbed_official | 146:f64d43ff0c18 | 884 | { |
mbed_official | 146:f64d43ff0c18 | 885 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 886 | struct _hw_wdog_unlock_bitfields |
mbed_official | 146:f64d43ff0c18 | 887 | { |
mbed_official | 146:f64d43ff0c18 | 888 | uint16_t WDOGUNLOCK : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 889 | } B; |
mbed_official | 146:f64d43ff0c18 | 890 | } hw_wdog_unlock_t; |
mbed_official | 146:f64d43ff0c18 | 891 | #endif |
mbed_official | 146:f64d43ff0c18 | 892 | |
mbed_official | 146:f64d43ff0c18 | 893 | /*! |
mbed_official | 146:f64d43ff0c18 | 894 | * @name Constants and macros for entire WDOG_UNLOCK register |
mbed_official | 146:f64d43ff0c18 | 895 | */ |
mbed_official | 146:f64d43ff0c18 | 896 | //@{ |
mbed_official | 146:f64d43ff0c18 | 897 | #define HW_WDOG_UNLOCK_ADDR (REGS_WDOG_BASE + 0xEU) |
mbed_official | 146:f64d43ff0c18 | 898 | |
mbed_official | 146:f64d43ff0c18 | 899 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 900 | #define HW_WDOG_UNLOCK (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR) |
mbed_official | 146:f64d43ff0c18 | 901 | #define HW_WDOG_UNLOCK_RD() (HW_WDOG_UNLOCK.U) |
mbed_official | 146:f64d43ff0c18 | 902 | #define HW_WDOG_UNLOCK_WR(v) (HW_WDOG_UNLOCK.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 903 | #define HW_WDOG_UNLOCK_SET(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 904 | #define HW_WDOG_UNLOCK_CLR(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 905 | #define HW_WDOG_UNLOCK_TOG(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 906 | #endif |
mbed_official | 146:f64d43ff0c18 | 907 | //@} |
mbed_official | 146:f64d43ff0c18 | 908 | |
mbed_official | 146:f64d43ff0c18 | 909 | /* |
mbed_official | 146:f64d43ff0c18 | 910 | * Constants & macros for individual WDOG_UNLOCK bitfields |
mbed_official | 146:f64d43ff0c18 | 911 | */ |
mbed_official | 146:f64d43ff0c18 | 912 | |
mbed_official | 146:f64d43ff0c18 | 913 | /*! |
mbed_official | 146:f64d43ff0c18 | 914 | * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 915 | * |
mbed_official | 146:f64d43ff0c18 | 916 | * Writing the unlock sequence values to this register to makes the watchdog |
mbed_official | 146:f64d43ff0c18 | 917 | * write-once registers writable again. The required unlock sequence is 0xC520 |
mbed_official | 146:f64d43ff0c18 | 918 | * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a |
mbed_official | 146:f64d43ff0c18 | 919 | * window equal in length to the WCT within which you can update the registers. |
mbed_official | 146:f64d43ff0c18 | 920 | * Writing a value other than the above mentioned sequence or if the sequence is |
mbed_official | 146:f64d43ff0c18 | 921 | * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts |
mbed_official | 146:f64d43ff0c18 | 922 | * and then resets the system. The unlock sequence is effective only if |
mbed_official | 146:f64d43ff0c18 | 923 | * ALLOWUPDATE is set. |
mbed_official | 146:f64d43ff0c18 | 924 | */ |
mbed_official | 146:f64d43ff0c18 | 925 | //@{ |
mbed_official | 146:f64d43ff0c18 | 926 | #define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) //!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. |
mbed_official | 146:f64d43ff0c18 | 927 | #define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) //!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. |
mbed_official | 146:f64d43ff0c18 | 928 | #define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) //!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. |
mbed_official | 146:f64d43ff0c18 | 929 | |
mbed_official | 146:f64d43ff0c18 | 930 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 931 | //! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. |
mbed_official | 146:f64d43ff0c18 | 932 | #define BR_WDOG_UNLOCK_WDOGUNLOCK (HW_WDOG_UNLOCK.U) |
mbed_official | 146:f64d43ff0c18 | 933 | #endif |
mbed_official | 146:f64d43ff0c18 | 934 | |
mbed_official | 146:f64d43ff0c18 | 935 | //! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. |
mbed_official | 146:f64d43ff0c18 | 936 | #define BF_WDOG_UNLOCK_WDOGUNLOCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_UNLOCK_WDOGUNLOCK), uint16_t) & BM_WDOG_UNLOCK_WDOGUNLOCK) |
mbed_official | 146:f64d43ff0c18 | 937 | |
mbed_official | 146:f64d43ff0c18 | 938 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 939 | //! @brief Set the WDOGUNLOCK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 940 | #define BW_WDOG_UNLOCK_WDOGUNLOCK(v) (HW_WDOG_UNLOCK_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 941 | #endif |
mbed_official | 146:f64d43ff0c18 | 942 | //@} |
mbed_official | 146:f64d43ff0c18 | 943 | |
mbed_official | 146:f64d43ff0c18 | 944 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 945 | // HW_WDOG_TMROUTH - Watchdog Timer Output Register High |
mbed_official | 146:f64d43ff0c18 | 946 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 947 | |
mbed_official | 146:f64d43ff0c18 | 948 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 949 | /*! |
mbed_official | 146:f64d43ff0c18 | 950 | * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW) |
mbed_official | 146:f64d43ff0c18 | 951 | * |
mbed_official | 146:f64d43ff0c18 | 952 | * Reset value: 0x0000U |
mbed_official | 146:f64d43ff0c18 | 953 | */ |
mbed_official | 146:f64d43ff0c18 | 954 | typedef union _hw_wdog_tmrouth |
mbed_official | 146:f64d43ff0c18 | 955 | { |
mbed_official | 146:f64d43ff0c18 | 956 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 957 | struct _hw_wdog_tmrouth_bitfields |
mbed_official | 146:f64d43ff0c18 | 958 | { |
mbed_official | 146:f64d43ff0c18 | 959 | uint16_t TIMEROUTHIGH : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 960 | } B; |
mbed_official | 146:f64d43ff0c18 | 961 | } hw_wdog_tmrouth_t; |
mbed_official | 146:f64d43ff0c18 | 962 | #endif |
mbed_official | 146:f64d43ff0c18 | 963 | |
mbed_official | 146:f64d43ff0c18 | 964 | /*! |
mbed_official | 146:f64d43ff0c18 | 965 | * @name Constants and macros for entire WDOG_TMROUTH register |
mbed_official | 146:f64d43ff0c18 | 966 | */ |
mbed_official | 146:f64d43ff0c18 | 967 | //@{ |
mbed_official | 146:f64d43ff0c18 | 968 | #define HW_WDOG_TMROUTH_ADDR (REGS_WDOG_BASE + 0x10U) |
mbed_official | 146:f64d43ff0c18 | 969 | |
mbed_official | 146:f64d43ff0c18 | 970 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 971 | #define HW_WDOG_TMROUTH (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 972 | #define HW_WDOG_TMROUTH_RD() (HW_WDOG_TMROUTH.U) |
mbed_official | 146:f64d43ff0c18 | 973 | #define HW_WDOG_TMROUTH_WR(v) (HW_WDOG_TMROUTH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 974 | #define HW_WDOG_TMROUTH_SET(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 975 | #define HW_WDOG_TMROUTH_CLR(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 976 | #define HW_WDOG_TMROUTH_TOG(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 977 | #endif |
mbed_official | 146:f64d43ff0c18 | 978 | //@} |
mbed_official | 146:f64d43ff0c18 | 979 | |
mbed_official | 146:f64d43ff0c18 | 980 | /* |
mbed_official | 146:f64d43ff0c18 | 981 | * Constants & macros for individual WDOG_TMROUTH bitfields |
mbed_official | 146:f64d43ff0c18 | 982 | */ |
mbed_official | 146:f64d43ff0c18 | 983 | |
mbed_official | 146:f64d43ff0c18 | 984 | /*! |
mbed_official | 146:f64d43ff0c18 | 985 | * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 986 | * |
mbed_official | 146:f64d43ff0c18 | 987 | * Shows the value of the upper 16 bits of the watchdog timer. |
mbed_official | 146:f64d43ff0c18 | 988 | */ |
mbed_official | 146:f64d43ff0c18 | 989 | //@{ |
mbed_official | 146:f64d43ff0c18 | 990 | #define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) //!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. |
mbed_official | 146:f64d43ff0c18 | 991 | #define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) //!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. |
mbed_official | 146:f64d43ff0c18 | 992 | #define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) //!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. |
mbed_official | 146:f64d43ff0c18 | 993 | |
mbed_official | 146:f64d43ff0c18 | 994 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 995 | //! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. |
mbed_official | 146:f64d43ff0c18 | 996 | #define BR_WDOG_TMROUTH_TIMEROUTHIGH (HW_WDOG_TMROUTH.U) |
mbed_official | 146:f64d43ff0c18 | 997 | #endif |
mbed_official | 146:f64d43ff0c18 | 998 | |
mbed_official | 146:f64d43ff0c18 | 999 | //! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. |
mbed_official | 146:f64d43ff0c18 | 1000 | #define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTH_TIMEROUTHIGH), uint16_t) & BM_WDOG_TMROUTH_TIMEROUTHIGH) |
mbed_official | 146:f64d43ff0c18 | 1001 | |
mbed_official | 146:f64d43ff0c18 | 1002 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1003 | //! @brief Set the TIMEROUTHIGH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1004 | #define BW_WDOG_TMROUTH_TIMEROUTHIGH(v) (HW_WDOG_TMROUTH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1005 | #endif |
mbed_official | 146:f64d43ff0c18 | 1006 | //@} |
mbed_official | 146:f64d43ff0c18 | 1007 | |
mbed_official | 146:f64d43ff0c18 | 1008 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1009 | // HW_WDOG_TMROUTL - Watchdog Timer Output Register Low |
mbed_official | 146:f64d43ff0c18 | 1010 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1011 | |
mbed_official | 146:f64d43ff0c18 | 1012 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1013 | /*! |
mbed_official | 146:f64d43ff0c18 | 1014 | * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW) |
mbed_official | 146:f64d43ff0c18 | 1015 | * |
mbed_official | 146:f64d43ff0c18 | 1016 | * Reset value: 0x0000U |
mbed_official | 146:f64d43ff0c18 | 1017 | * |
mbed_official | 146:f64d43ff0c18 | 1018 | * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of |
mbed_official | 146:f64d43ff0c18 | 1019 | * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK |
mbed_official | 146:f64d43ff0c18 | 1020 | * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following |
mbed_official | 146:f64d43ff0c18 | 1021 | * the watchdog timer. |
mbed_official | 146:f64d43ff0c18 | 1022 | */ |
mbed_official | 146:f64d43ff0c18 | 1023 | typedef union _hw_wdog_tmroutl |
mbed_official | 146:f64d43ff0c18 | 1024 | { |
mbed_official | 146:f64d43ff0c18 | 1025 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 1026 | struct _hw_wdog_tmroutl_bitfields |
mbed_official | 146:f64d43ff0c18 | 1027 | { |
mbed_official | 146:f64d43ff0c18 | 1028 | uint16_t TIMEROUTLOW : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 1029 | } B; |
mbed_official | 146:f64d43ff0c18 | 1030 | } hw_wdog_tmroutl_t; |
mbed_official | 146:f64d43ff0c18 | 1031 | #endif |
mbed_official | 146:f64d43ff0c18 | 1032 | |
mbed_official | 146:f64d43ff0c18 | 1033 | /*! |
mbed_official | 146:f64d43ff0c18 | 1034 | * @name Constants and macros for entire WDOG_TMROUTL register |
mbed_official | 146:f64d43ff0c18 | 1035 | */ |
mbed_official | 146:f64d43ff0c18 | 1036 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1037 | #define HW_WDOG_TMROUTL_ADDR (REGS_WDOG_BASE + 0x12U) |
mbed_official | 146:f64d43ff0c18 | 1038 | |
mbed_official | 146:f64d43ff0c18 | 1039 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1040 | #define HW_WDOG_TMROUTL (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1041 | #define HW_WDOG_TMROUTL_RD() (HW_WDOG_TMROUTL.U) |
mbed_official | 146:f64d43ff0c18 | 1042 | #define HW_WDOG_TMROUTL_WR(v) (HW_WDOG_TMROUTL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1043 | #define HW_WDOG_TMROUTL_SET(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1044 | #define HW_WDOG_TMROUTL_CLR(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1045 | #define HW_WDOG_TMROUTL_TOG(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1046 | #endif |
mbed_official | 146:f64d43ff0c18 | 1047 | //@} |
mbed_official | 146:f64d43ff0c18 | 1048 | |
mbed_official | 146:f64d43ff0c18 | 1049 | /* |
mbed_official | 146:f64d43ff0c18 | 1050 | * Constants & macros for individual WDOG_TMROUTL bitfields |
mbed_official | 146:f64d43ff0c18 | 1051 | */ |
mbed_official | 146:f64d43ff0c18 | 1052 | |
mbed_official | 146:f64d43ff0c18 | 1053 | /*! |
mbed_official | 146:f64d43ff0c18 | 1054 | * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1055 | * |
mbed_official | 146:f64d43ff0c18 | 1056 | * Shows the value of the lower 16 bits of the watchdog timer. |
mbed_official | 146:f64d43ff0c18 | 1057 | */ |
mbed_official | 146:f64d43ff0c18 | 1058 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1059 | #define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) //!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. |
mbed_official | 146:f64d43ff0c18 | 1060 | #define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) //!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. |
mbed_official | 146:f64d43ff0c18 | 1061 | #define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) //!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. |
mbed_official | 146:f64d43ff0c18 | 1062 | |
mbed_official | 146:f64d43ff0c18 | 1063 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1064 | //! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. |
mbed_official | 146:f64d43ff0c18 | 1065 | #define BR_WDOG_TMROUTL_TIMEROUTLOW (HW_WDOG_TMROUTL.U) |
mbed_official | 146:f64d43ff0c18 | 1066 | #endif |
mbed_official | 146:f64d43ff0c18 | 1067 | |
mbed_official | 146:f64d43ff0c18 | 1068 | //! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. |
mbed_official | 146:f64d43ff0c18 | 1069 | #define BF_WDOG_TMROUTL_TIMEROUTLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTL_TIMEROUTLOW), uint16_t) & BM_WDOG_TMROUTL_TIMEROUTLOW) |
mbed_official | 146:f64d43ff0c18 | 1070 | |
mbed_official | 146:f64d43ff0c18 | 1071 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1072 | //! @brief Set the TIMEROUTLOW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1073 | #define BW_WDOG_TMROUTL_TIMEROUTLOW(v) (HW_WDOG_TMROUTL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1074 | #endif |
mbed_official | 146:f64d43ff0c18 | 1075 | //@} |
mbed_official | 146:f64d43ff0c18 | 1076 | |
mbed_official | 146:f64d43ff0c18 | 1077 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1078 | // HW_WDOG_RSTCNT - Watchdog Reset Count register |
mbed_official | 146:f64d43ff0c18 | 1079 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1080 | |
mbed_official | 146:f64d43ff0c18 | 1081 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1082 | /*! |
mbed_official | 146:f64d43ff0c18 | 1083 | * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW) |
mbed_official | 146:f64d43ff0c18 | 1084 | * |
mbed_official | 146:f64d43ff0c18 | 1085 | * Reset value: 0x0000U |
mbed_official | 146:f64d43ff0c18 | 1086 | */ |
mbed_official | 146:f64d43ff0c18 | 1087 | typedef union _hw_wdog_rstcnt |
mbed_official | 146:f64d43ff0c18 | 1088 | { |
mbed_official | 146:f64d43ff0c18 | 1089 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 1090 | struct _hw_wdog_rstcnt_bitfields |
mbed_official | 146:f64d43ff0c18 | 1091 | { |
mbed_official | 146:f64d43ff0c18 | 1092 | uint16_t RSTCNT : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 1093 | } B; |
mbed_official | 146:f64d43ff0c18 | 1094 | } hw_wdog_rstcnt_t; |
mbed_official | 146:f64d43ff0c18 | 1095 | #endif |
mbed_official | 146:f64d43ff0c18 | 1096 | |
mbed_official | 146:f64d43ff0c18 | 1097 | /*! |
mbed_official | 146:f64d43ff0c18 | 1098 | * @name Constants and macros for entire WDOG_RSTCNT register |
mbed_official | 146:f64d43ff0c18 | 1099 | */ |
mbed_official | 146:f64d43ff0c18 | 1100 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1101 | #define HW_WDOG_RSTCNT_ADDR (REGS_WDOG_BASE + 0x14U) |
mbed_official | 146:f64d43ff0c18 | 1102 | |
mbed_official | 146:f64d43ff0c18 | 1103 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1104 | #define HW_WDOG_RSTCNT (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1105 | #define HW_WDOG_RSTCNT_RD() (HW_WDOG_RSTCNT.U) |
mbed_official | 146:f64d43ff0c18 | 1106 | #define HW_WDOG_RSTCNT_WR(v) (HW_WDOG_RSTCNT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1107 | #define HW_WDOG_RSTCNT_SET(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1108 | #define HW_WDOG_RSTCNT_CLR(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1109 | #define HW_WDOG_RSTCNT_TOG(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1110 | #endif |
mbed_official | 146:f64d43ff0c18 | 1111 | //@} |
mbed_official | 146:f64d43ff0c18 | 1112 | |
mbed_official | 146:f64d43ff0c18 | 1113 | /* |
mbed_official | 146:f64d43ff0c18 | 1114 | * Constants & macros for individual WDOG_RSTCNT bitfields |
mbed_official | 146:f64d43ff0c18 | 1115 | */ |
mbed_official | 146:f64d43ff0c18 | 1116 | |
mbed_official | 146:f64d43ff0c18 | 1117 | /*! |
mbed_official | 146:f64d43ff0c18 | 1118 | * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1119 | * |
mbed_official | 146:f64d43ff0c18 | 1120 | * Counts the number of times the watchdog resets the system. This register is |
mbed_official | 146:f64d43ff0c18 | 1121 | * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear |
mbed_official | 146:f64d43ff0c18 | 1122 | * the contents of this register. |
mbed_official | 146:f64d43ff0c18 | 1123 | */ |
mbed_official | 146:f64d43ff0c18 | 1124 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1125 | #define BP_WDOG_RSTCNT_RSTCNT (0U) //!< Bit position for WDOG_RSTCNT_RSTCNT. |
mbed_official | 146:f64d43ff0c18 | 1126 | #define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) //!< Bit mask for WDOG_RSTCNT_RSTCNT. |
mbed_official | 146:f64d43ff0c18 | 1127 | #define BS_WDOG_RSTCNT_RSTCNT (16U) //!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. |
mbed_official | 146:f64d43ff0c18 | 1128 | |
mbed_official | 146:f64d43ff0c18 | 1129 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1130 | //! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. |
mbed_official | 146:f64d43ff0c18 | 1131 | #define BR_WDOG_RSTCNT_RSTCNT (HW_WDOG_RSTCNT.U) |
mbed_official | 146:f64d43ff0c18 | 1132 | #endif |
mbed_official | 146:f64d43ff0c18 | 1133 | |
mbed_official | 146:f64d43ff0c18 | 1134 | //! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. |
mbed_official | 146:f64d43ff0c18 | 1135 | #define BF_WDOG_RSTCNT_RSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_RSTCNT_RSTCNT), uint16_t) & BM_WDOG_RSTCNT_RSTCNT) |
mbed_official | 146:f64d43ff0c18 | 1136 | |
mbed_official | 146:f64d43ff0c18 | 1137 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1138 | //! @brief Set the RSTCNT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1139 | #define BW_WDOG_RSTCNT_RSTCNT(v) (HW_WDOG_RSTCNT_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1140 | #endif |
mbed_official | 146:f64d43ff0c18 | 1141 | //@} |
mbed_official | 146:f64d43ff0c18 | 1142 | |
mbed_official | 146:f64d43ff0c18 | 1143 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1144 | // HW_WDOG_PRESC - Watchdog Prescaler register |
mbed_official | 146:f64d43ff0c18 | 1145 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1146 | |
mbed_official | 146:f64d43ff0c18 | 1147 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1148 | /*! |
mbed_official | 146:f64d43ff0c18 | 1149 | * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW) |
mbed_official | 146:f64d43ff0c18 | 1150 | * |
mbed_official | 146:f64d43ff0c18 | 1151 | * Reset value: 0x0400U |
mbed_official | 146:f64d43ff0c18 | 1152 | */ |
mbed_official | 146:f64d43ff0c18 | 1153 | typedef union _hw_wdog_presc |
mbed_official | 146:f64d43ff0c18 | 1154 | { |
mbed_official | 146:f64d43ff0c18 | 1155 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 1156 | struct _hw_wdog_presc_bitfields |
mbed_official | 146:f64d43ff0c18 | 1157 | { |
mbed_official | 146:f64d43ff0c18 | 1158 | uint16_t RESERVED0 : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1159 | uint16_t PRESCVAL : 3; //!< [10:8] |
mbed_official | 146:f64d43ff0c18 | 1160 | uint16_t RESERVED1 : 5; //!< [15:11] |
mbed_official | 146:f64d43ff0c18 | 1161 | } B; |
mbed_official | 146:f64d43ff0c18 | 1162 | } hw_wdog_presc_t; |
mbed_official | 146:f64d43ff0c18 | 1163 | #endif |
mbed_official | 146:f64d43ff0c18 | 1164 | |
mbed_official | 146:f64d43ff0c18 | 1165 | /*! |
mbed_official | 146:f64d43ff0c18 | 1166 | * @name Constants and macros for entire WDOG_PRESC register |
mbed_official | 146:f64d43ff0c18 | 1167 | */ |
mbed_official | 146:f64d43ff0c18 | 1168 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1169 | #define HW_WDOG_PRESC_ADDR (REGS_WDOG_BASE + 0x16U) |
mbed_official | 146:f64d43ff0c18 | 1170 | |
mbed_official | 146:f64d43ff0c18 | 1171 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1172 | #define HW_WDOG_PRESC (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1173 | #define HW_WDOG_PRESC_RD() (HW_WDOG_PRESC.U) |
mbed_official | 146:f64d43ff0c18 | 1174 | #define HW_WDOG_PRESC_WR(v) (HW_WDOG_PRESC.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1175 | #define HW_WDOG_PRESC_SET(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1176 | #define HW_WDOG_PRESC_CLR(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1177 | #define HW_WDOG_PRESC_TOG(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1178 | #endif |
mbed_official | 146:f64d43ff0c18 | 1179 | //@} |
mbed_official | 146:f64d43ff0c18 | 1180 | |
mbed_official | 146:f64d43ff0c18 | 1181 | /* |
mbed_official | 146:f64d43ff0c18 | 1182 | * Constants & macros for individual WDOG_PRESC bitfields |
mbed_official | 146:f64d43ff0c18 | 1183 | */ |
mbed_official | 146:f64d43ff0c18 | 1184 | |
mbed_official | 146:f64d43ff0c18 | 1185 | /*! |
mbed_official | 146:f64d43ff0c18 | 1186 | * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW) |
mbed_official | 146:f64d43ff0c18 | 1187 | * |
mbed_official | 146:f64d43ff0c18 | 1188 | * 3-bit prescaler for the watchdog clock source. A value of zero indicates no |
mbed_official | 146:f64d43ff0c18 | 1189 | * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + |
mbed_official | 146:f64d43ff0c18 | 1190 | * 1) to provide the prescaled WDOG_CLK. |
mbed_official | 146:f64d43ff0c18 | 1191 | */ |
mbed_official | 146:f64d43ff0c18 | 1192 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1193 | #define BP_WDOG_PRESC_PRESCVAL (8U) //!< Bit position for WDOG_PRESC_PRESCVAL. |
mbed_official | 146:f64d43ff0c18 | 1194 | #define BM_WDOG_PRESC_PRESCVAL (0x0700U) //!< Bit mask for WDOG_PRESC_PRESCVAL. |
mbed_official | 146:f64d43ff0c18 | 1195 | #define BS_WDOG_PRESC_PRESCVAL (3U) //!< Bit field size in bits for WDOG_PRESC_PRESCVAL. |
mbed_official | 146:f64d43ff0c18 | 1196 | |
mbed_official | 146:f64d43ff0c18 | 1197 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1198 | //! @brief Read current value of the WDOG_PRESC_PRESCVAL field. |
mbed_official | 146:f64d43ff0c18 | 1199 | #define BR_WDOG_PRESC_PRESCVAL (HW_WDOG_PRESC.B.PRESCVAL) |
mbed_official | 146:f64d43ff0c18 | 1200 | #endif |
mbed_official | 146:f64d43ff0c18 | 1201 | |
mbed_official | 146:f64d43ff0c18 | 1202 | //! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. |
mbed_official | 146:f64d43ff0c18 | 1203 | #define BF_WDOG_PRESC_PRESCVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_PRESC_PRESCVAL), uint16_t) & BM_WDOG_PRESC_PRESCVAL) |
mbed_official | 146:f64d43ff0c18 | 1204 | |
mbed_official | 146:f64d43ff0c18 | 1205 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1206 | //! @brief Set the PRESCVAL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1207 | #define BW_WDOG_PRESC_PRESCVAL(v) (HW_WDOG_PRESC_WR((HW_WDOG_PRESC_RD() & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v))) |
mbed_official | 146:f64d43ff0c18 | 1208 | #endif |
mbed_official | 146:f64d43ff0c18 | 1209 | //@} |
mbed_official | 146:f64d43ff0c18 | 1210 | |
mbed_official | 146:f64d43ff0c18 | 1211 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1212 | // hw_wdog_t - module struct |
mbed_official | 146:f64d43ff0c18 | 1213 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1214 | /*! |
mbed_official | 146:f64d43ff0c18 | 1215 | * @brief All WDOG module registers. |
mbed_official | 146:f64d43ff0c18 | 1216 | */ |
mbed_official | 146:f64d43ff0c18 | 1217 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1218 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 1219 | typedef struct _hw_wdog |
mbed_official | 146:f64d43ff0c18 | 1220 | { |
mbed_official | 146:f64d43ff0c18 | 1221 | __IO hw_wdog_stctrlh_t STCTRLH; //!< [0x0] Watchdog Status and Control Register High |
mbed_official | 146:f64d43ff0c18 | 1222 | __IO hw_wdog_stctrll_t STCTRLL; //!< [0x2] Watchdog Status and Control Register Low |
mbed_official | 146:f64d43ff0c18 | 1223 | __IO hw_wdog_tovalh_t TOVALH; //!< [0x4] Watchdog Time-out Value Register High |
mbed_official | 146:f64d43ff0c18 | 1224 | __IO hw_wdog_tovall_t TOVALL; //!< [0x6] Watchdog Time-out Value Register Low |
mbed_official | 146:f64d43ff0c18 | 1225 | __IO hw_wdog_winh_t WINH; //!< [0x8] Watchdog Window Register High |
mbed_official | 146:f64d43ff0c18 | 1226 | __IO hw_wdog_winl_t WINL; //!< [0xA] Watchdog Window Register Low |
mbed_official | 146:f64d43ff0c18 | 1227 | __IO hw_wdog_refresh_t REFRESH; //!< [0xC] Watchdog Refresh register |
mbed_official | 146:f64d43ff0c18 | 1228 | __IO hw_wdog_unlock_t UNLOCK; //!< [0xE] Watchdog Unlock register |
mbed_official | 146:f64d43ff0c18 | 1229 | __IO hw_wdog_tmrouth_t TMROUTH; //!< [0x10] Watchdog Timer Output Register High |
mbed_official | 146:f64d43ff0c18 | 1230 | __IO hw_wdog_tmroutl_t TMROUTL; //!< [0x12] Watchdog Timer Output Register Low |
mbed_official | 146:f64d43ff0c18 | 1231 | __IO hw_wdog_rstcnt_t RSTCNT; //!< [0x14] Watchdog Reset Count register |
mbed_official | 146:f64d43ff0c18 | 1232 | __IO hw_wdog_presc_t PRESC; //!< [0x16] Watchdog Prescaler register |
mbed_official | 146:f64d43ff0c18 | 1233 | } hw_wdog_t; |
mbed_official | 146:f64d43ff0c18 | 1234 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 1235 | |
mbed_official | 146:f64d43ff0c18 | 1236 | //! @brief Macro to access all WDOG registers. |
mbed_official | 146:f64d43ff0c18 | 1237 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 1238 | //! use the '&' operator, like <code>&HW_WDOG</code>. |
mbed_official | 146:f64d43ff0c18 | 1239 | #define HW_WDOG (*(hw_wdog_t *) REGS_WDOG_BASE) |
mbed_official | 146:f64d43ff0c18 | 1240 | #endif |
mbed_official | 146:f64d43ff0c18 | 1241 | |
mbed_official | 146:f64d43ff0c18 | 1242 | #endif // __HW_WDOG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 1243 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 1244 | // EOF |