mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcg.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcg.h@146:f64d43ff0c18
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_MCG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_MCG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 MCG |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Multipurpose Clock Generator module |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_MCG_C1 - MCG Control 1 Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_MCG_C2 - MCG Control 2 Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_MCG_C3 - MCG Control 3 Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_MCG_C4 - MCG Control 4 Register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_MCG_C5 - MCG Control 5 Register |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_MCG_C6 - MCG Control 6 Register |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_MCG_S - MCG Status Register |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_MCG_SC - MCG Status and Control Register |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_MCG_C7 - MCG Control 7 Register |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_MCG_C8 - MCG Control 8 Register |
mbed_official | 146:f64d43ff0c18 | 44 | * |
mbed_official | 146:f64d43ff0c18 | 45 | * - hw_mcg_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 46 | */ |
mbed_official | 146:f64d43ff0c18 | 47 | |
mbed_official | 146:f64d43ff0c18 | 48 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 49 | //@{ |
mbed_official | 146:f64d43ff0c18 | 50 | #ifndef REGS_MCG_BASE |
mbed_official | 146:f64d43ff0c18 | 51 | #define HW_MCG_INSTANCE_COUNT (1U) //!< Number of instances of the MCG module. |
mbed_official | 146:f64d43ff0c18 | 52 | #define REGS_MCG_BASE (0x40064000U) //!< Base address for MCG. |
mbed_official | 146:f64d43ff0c18 | 53 | #endif |
mbed_official | 146:f64d43ff0c18 | 54 | //@} |
mbed_official | 146:f64d43ff0c18 | 55 | |
mbed_official | 146:f64d43ff0c18 | 56 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 57 | // HW_MCG_C1 - MCG Control 1 Register |
mbed_official | 146:f64d43ff0c18 | 58 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 59 | |
mbed_official | 146:f64d43ff0c18 | 60 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 61 | /*! |
mbed_official | 146:f64d43ff0c18 | 62 | * @brief HW_MCG_C1 - MCG Control 1 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 63 | * |
mbed_official | 146:f64d43ff0c18 | 64 | * Reset value: 0x04U |
mbed_official | 146:f64d43ff0c18 | 65 | */ |
mbed_official | 146:f64d43ff0c18 | 66 | typedef union _hw_mcg_c1 |
mbed_official | 146:f64d43ff0c18 | 67 | { |
mbed_official | 146:f64d43ff0c18 | 68 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 69 | struct _hw_mcg_c1_bitfields |
mbed_official | 146:f64d43ff0c18 | 70 | { |
mbed_official | 146:f64d43ff0c18 | 71 | uint8_t IREFSTEN : 1; //!< [0] Internal Reference Stop Enable |
mbed_official | 146:f64d43ff0c18 | 72 | uint8_t IRCLKEN : 1; //!< [1] Internal Reference Clock Enable |
mbed_official | 146:f64d43ff0c18 | 73 | uint8_t IREFS : 1; //!< [2] Internal Reference Select |
mbed_official | 146:f64d43ff0c18 | 74 | uint8_t FRDIV : 3; //!< [5:3] FLL External Reference Divider |
mbed_official | 146:f64d43ff0c18 | 75 | uint8_t CLKS : 2; //!< [7:6] Clock Source Select |
mbed_official | 146:f64d43ff0c18 | 76 | } B; |
mbed_official | 146:f64d43ff0c18 | 77 | } hw_mcg_c1_t; |
mbed_official | 146:f64d43ff0c18 | 78 | #endif |
mbed_official | 146:f64d43ff0c18 | 79 | |
mbed_official | 146:f64d43ff0c18 | 80 | /*! |
mbed_official | 146:f64d43ff0c18 | 81 | * @name Constants and macros for entire MCG_C1 register |
mbed_official | 146:f64d43ff0c18 | 82 | */ |
mbed_official | 146:f64d43ff0c18 | 83 | //@{ |
mbed_official | 146:f64d43ff0c18 | 84 | #define HW_MCG_C1_ADDR (REGS_MCG_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 85 | |
mbed_official | 146:f64d43ff0c18 | 86 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 87 | #define HW_MCG_C1 (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR) |
mbed_official | 146:f64d43ff0c18 | 88 | #define HW_MCG_C1_RD() (HW_MCG_C1.U) |
mbed_official | 146:f64d43ff0c18 | 89 | #define HW_MCG_C1_WR(v) (HW_MCG_C1.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 90 | #define HW_MCG_C1_SET(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 91 | #define HW_MCG_C1_CLR(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 92 | #define HW_MCG_C1_TOG(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 93 | #endif |
mbed_official | 146:f64d43ff0c18 | 94 | //@} |
mbed_official | 146:f64d43ff0c18 | 95 | |
mbed_official | 146:f64d43ff0c18 | 96 | /* |
mbed_official | 146:f64d43ff0c18 | 97 | * Constants & macros for individual MCG_C1 bitfields |
mbed_official | 146:f64d43ff0c18 | 98 | */ |
mbed_official | 146:f64d43ff0c18 | 99 | |
mbed_official | 146:f64d43ff0c18 | 100 | /*! |
mbed_official | 146:f64d43ff0c18 | 101 | * @name Register MCG_C1, field IREFSTEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 102 | * |
mbed_official | 146:f64d43ff0c18 | 103 | * Controls whether or not the internal reference clock remains enabled when the |
mbed_official | 146:f64d43ff0c18 | 104 | * MCG enters Stop mode. |
mbed_official | 146:f64d43ff0c18 | 105 | * |
mbed_official | 146:f64d43ff0c18 | 106 | * Values: |
mbed_official | 146:f64d43ff0c18 | 107 | * - 0 - Internal reference clock is disabled in Stop mode. |
mbed_official | 146:f64d43ff0c18 | 108 | * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or |
mbed_official | 146:f64d43ff0c18 | 109 | * if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. |
mbed_official | 146:f64d43ff0c18 | 110 | */ |
mbed_official | 146:f64d43ff0c18 | 111 | //@{ |
mbed_official | 146:f64d43ff0c18 | 112 | #define BP_MCG_C1_IREFSTEN (0U) //!< Bit position for MCG_C1_IREFSTEN. |
mbed_official | 146:f64d43ff0c18 | 113 | #define BM_MCG_C1_IREFSTEN (0x01U) //!< Bit mask for MCG_C1_IREFSTEN. |
mbed_official | 146:f64d43ff0c18 | 114 | #define BS_MCG_C1_IREFSTEN (1U) //!< Bit field size in bits for MCG_C1_IREFSTEN. |
mbed_official | 146:f64d43ff0c18 | 115 | |
mbed_official | 146:f64d43ff0c18 | 116 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 117 | //! @brief Read current value of the MCG_C1_IREFSTEN field. |
mbed_official | 146:f64d43ff0c18 | 118 | #define BR_MCG_C1_IREFSTEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN)) |
mbed_official | 146:f64d43ff0c18 | 119 | #endif |
mbed_official | 146:f64d43ff0c18 | 120 | |
mbed_official | 146:f64d43ff0c18 | 121 | //! @brief Format value for bitfield MCG_C1_IREFSTEN. |
mbed_official | 146:f64d43ff0c18 | 122 | #define BF_MCG_C1_IREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFSTEN), uint8_t) & BM_MCG_C1_IREFSTEN) |
mbed_official | 146:f64d43ff0c18 | 123 | |
mbed_official | 146:f64d43ff0c18 | 124 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 125 | //! @brief Set the IREFSTEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 126 | #define BW_MCG_C1_IREFSTEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 127 | #endif |
mbed_official | 146:f64d43ff0c18 | 128 | //@} |
mbed_official | 146:f64d43ff0c18 | 129 | |
mbed_official | 146:f64d43ff0c18 | 130 | /*! |
mbed_official | 146:f64d43ff0c18 | 131 | * @name Register MCG_C1, field IRCLKEN[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 132 | * |
mbed_official | 146:f64d43ff0c18 | 133 | * Enables the internal reference clock for use as MCGIRCLK. |
mbed_official | 146:f64d43ff0c18 | 134 | * |
mbed_official | 146:f64d43ff0c18 | 135 | * Values: |
mbed_official | 146:f64d43ff0c18 | 136 | * - 0 - MCGIRCLK inactive. |
mbed_official | 146:f64d43ff0c18 | 137 | * - 1 - MCGIRCLK active. |
mbed_official | 146:f64d43ff0c18 | 138 | */ |
mbed_official | 146:f64d43ff0c18 | 139 | //@{ |
mbed_official | 146:f64d43ff0c18 | 140 | #define BP_MCG_C1_IRCLKEN (1U) //!< Bit position for MCG_C1_IRCLKEN. |
mbed_official | 146:f64d43ff0c18 | 141 | #define BM_MCG_C1_IRCLKEN (0x02U) //!< Bit mask for MCG_C1_IRCLKEN. |
mbed_official | 146:f64d43ff0c18 | 142 | #define BS_MCG_C1_IRCLKEN (1U) //!< Bit field size in bits for MCG_C1_IRCLKEN. |
mbed_official | 146:f64d43ff0c18 | 143 | |
mbed_official | 146:f64d43ff0c18 | 144 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 145 | //! @brief Read current value of the MCG_C1_IRCLKEN field. |
mbed_official | 146:f64d43ff0c18 | 146 | #define BR_MCG_C1_IRCLKEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN)) |
mbed_official | 146:f64d43ff0c18 | 147 | #endif |
mbed_official | 146:f64d43ff0c18 | 148 | |
mbed_official | 146:f64d43ff0c18 | 149 | //! @brief Format value for bitfield MCG_C1_IRCLKEN. |
mbed_official | 146:f64d43ff0c18 | 150 | #define BF_MCG_C1_IRCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IRCLKEN), uint8_t) & BM_MCG_C1_IRCLKEN) |
mbed_official | 146:f64d43ff0c18 | 151 | |
mbed_official | 146:f64d43ff0c18 | 152 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 153 | //! @brief Set the IRCLKEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 154 | #define BW_MCG_C1_IRCLKEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 155 | #endif |
mbed_official | 146:f64d43ff0c18 | 156 | //@} |
mbed_official | 146:f64d43ff0c18 | 157 | |
mbed_official | 146:f64d43ff0c18 | 158 | /*! |
mbed_official | 146:f64d43ff0c18 | 159 | * @name Register MCG_C1, field IREFS[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 160 | * |
mbed_official | 146:f64d43ff0c18 | 161 | * Selects the reference clock source for the FLL. |
mbed_official | 146:f64d43ff0c18 | 162 | * |
mbed_official | 146:f64d43ff0c18 | 163 | * Values: |
mbed_official | 146:f64d43ff0c18 | 164 | * - 0 - External reference clock is selected. |
mbed_official | 146:f64d43ff0c18 | 165 | * - 1 - The slow internal reference clock is selected. |
mbed_official | 146:f64d43ff0c18 | 166 | */ |
mbed_official | 146:f64d43ff0c18 | 167 | //@{ |
mbed_official | 146:f64d43ff0c18 | 168 | #define BP_MCG_C1_IREFS (2U) //!< Bit position for MCG_C1_IREFS. |
mbed_official | 146:f64d43ff0c18 | 169 | #define BM_MCG_C1_IREFS (0x04U) //!< Bit mask for MCG_C1_IREFS. |
mbed_official | 146:f64d43ff0c18 | 170 | #define BS_MCG_C1_IREFS (1U) //!< Bit field size in bits for MCG_C1_IREFS. |
mbed_official | 146:f64d43ff0c18 | 171 | |
mbed_official | 146:f64d43ff0c18 | 172 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 173 | //! @brief Read current value of the MCG_C1_IREFS field. |
mbed_official | 146:f64d43ff0c18 | 174 | #define BR_MCG_C1_IREFS (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS)) |
mbed_official | 146:f64d43ff0c18 | 175 | #endif |
mbed_official | 146:f64d43ff0c18 | 176 | |
mbed_official | 146:f64d43ff0c18 | 177 | //! @brief Format value for bitfield MCG_C1_IREFS. |
mbed_official | 146:f64d43ff0c18 | 178 | #define BF_MCG_C1_IREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFS), uint8_t) & BM_MCG_C1_IREFS) |
mbed_official | 146:f64d43ff0c18 | 179 | |
mbed_official | 146:f64d43ff0c18 | 180 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 181 | //! @brief Set the IREFS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 182 | #define BW_MCG_C1_IREFS(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 183 | #endif |
mbed_official | 146:f64d43ff0c18 | 184 | //@} |
mbed_official | 146:f64d43ff0c18 | 185 | |
mbed_official | 146:f64d43ff0c18 | 186 | /*! |
mbed_official | 146:f64d43ff0c18 | 187 | * @name Register MCG_C1, field FRDIV[5:3] (RW) |
mbed_official | 146:f64d43ff0c18 | 188 | * |
mbed_official | 146:f64d43ff0c18 | 189 | * Selects the amount to divide down the external reference clock for the FLL. |
mbed_official | 146:f64d43ff0c18 | 190 | * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is |
mbed_official | 146:f64d43ff0c18 | 191 | * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is |
mbed_official | 146:f64d43ff0c18 | 192 | * not required to meet this range, but it is recommended in the cases when trying |
mbed_official | 146:f64d43ff0c18 | 193 | * to enter a FLL mode from FBE). |
mbed_official | 146:f64d43ff0c18 | 194 | * |
mbed_official | 146:f64d43ff0c18 | 195 | * Values: |
mbed_official | 146:f64d43ff0c18 | 196 | * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 197 | * values, Divide Factor is 32. |
mbed_official | 146:f64d43ff0c18 | 198 | * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 199 | * values, Divide Factor is 64. |
mbed_official | 146:f64d43ff0c18 | 200 | * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 201 | * values, Divide Factor is 128. |
mbed_official | 146:f64d43ff0c18 | 202 | * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 203 | * values, Divide Factor is 256. |
mbed_official | 146:f64d43ff0c18 | 204 | * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 205 | * values, Divide Factor is 512. |
mbed_official | 146:f64d43ff0c18 | 206 | * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 207 | * values, Divide Factor is 1024. |
mbed_official | 146:f64d43ff0c18 | 208 | * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 209 | * values, Divide Factor is 1280 . |
mbed_official | 146:f64d43ff0c18 | 210 | * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE |
mbed_official | 146:f64d43ff0c18 | 211 | * values, Divide Factor is 1536 . |
mbed_official | 146:f64d43ff0c18 | 212 | */ |
mbed_official | 146:f64d43ff0c18 | 213 | //@{ |
mbed_official | 146:f64d43ff0c18 | 214 | #define BP_MCG_C1_FRDIV (3U) //!< Bit position for MCG_C1_FRDIV. |
mbed_official | 146:f64d43ff0c18 | 215 | #define BM_MCG_C1_FRDIV (0x38U) //!< Bit mask for MCG_C1_FRDIV. |
mbed_official | 146:f64d43ff0c18 | 216 | #define BS_MCG_C1_FRDIV (3U) //!< Bit field size in bits for MCG_C1_FRDIV. |
mbed_official | 146:f64d43ff0c18 | 217 | |
mbed_official | 146:f64d43ff0c18 | 218 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 219 | //! @brief Read current value of the MCG_C1_FRDIV field. |
mbed_official | 146:f64d43ff0c18 | 220 | #define BR_MCG_C1_FRDIV (HW_MCG_C1.B.FRDIV) |
mbed_official | 146:f64d43ff0c18 | 221 | #endif |
mbed_official | 146:f64d43ff0c18 | 222 | |
mbed_official | 146:f64d43ff0c18 | 223 | //! @brief Format value for bitfield MCG_C1_FRDIV. |
mbed_official | 146:f64d43ff0c18 | 224 | #define BF_MCG_C1_FRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_FRDIV), uint8_t) & BM_MCG_C1_FRDIV) |
mbed_official | 146:f64d43ff0c18 | 225 | |
mbed_official | 146:f64d43ff0c18 | 226 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 227 | //! @brief Set the FRDIV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 228 | #define BW_MCG_C1_FRDIV(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v))) |
mbed_official | 146:f64d43ff0c18 | 229 | #endif |
mbed_official | 146:f64d43ff0c18 | 230 | //@} |
mbed_official | 146:f64d43ff0c18 | 231 | |
mbed_official | 146:f64d43ff0c18 | 232 | /*! |
mbed_official | 146:f64d43ff0c18 | 233 | * @name Register MCG_C1, field CLKS[7:6] (RW) |
mbed_official | 146:f64d43ff0c18 | 234 | * |
mbed_official | 146:f64d43ff0c18 | 235 | * Selects the clock source for MCGOUTCLK . |
mbed_official | 146:f64d43ff0c18 | 236 | * |
mbed_official | 146:f64d43ff0c18 | 237 | * Values: |
mbed_official | 146:f64d43ff0c18 | 238 | * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control |
mbed_official | 146:f64d43ff0c18 | 239 | * bit). |
mbed_official | 146:f64d43ff0c18 | 240 | * - 01 - Encoding 1 - Internal reference clock is selected. |
mbed_official | 146:f64d43ff0c18 | 241 | * - 10 - Encoding 2 - External reference clock is selected. |
mbed_official | 146:f64d43ff0c18 | 242 | * - 11 - Encoding 3 - Reserved. |
mbed_official | 146:f64d43ff0c18 | 243 | */ |
mbed_official | 146:f64d43ff0c18 | 244 | //@{ |
mbed_official | 146:f64d43ff0c18 | 245 | #define BP_MCG_C1_CLKS (6U) //!< Bit position for MCG_C1_CLKS. |
mbed_official | 146:f64d43ff0c18 | 246 | #define BM_MCG_C1_CLKS (0xC0U) //!< Bit mask for MCG_C1_CLKS. |
mbed_official | 146:f64d43ff0c18 | 247 | #define BS_MCG_C1_CLKS (2U) //!< Bit field size in bits for MCG_C1_CLKS. |
mbed_official | 146:f64d43ff0c18 | 248 | |
mbed_official | 146:f64d43ff0c18 | 249 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 250 | //! @brief Read current value of the MCG_C1_CLKS field. |
mbed_official | 146:f64d43ff0c18 | 251 | #define BR_MCG_C1_CLKS (HW_MCG_C1.B.CLKS) |
mbed_official | 146:f64d43ff0c18 | 252 | #endif |
mbed_official | 146:f64d43ff0c18 | 253 | |
mbed_official | 146:f64d43ff0c18 | 254 | //! @brief Format value for bitfield MCG_C1_CLKS. |
mbed_official | 146:f64d43ff0c18 | 255 | #define BF_MCG_C1_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_CLKS), uint8_t) & BM_MCG_C1_CLKS) |
mbed_official | 146:f64d43ff0c18 | 256 | |
mbed_official | 146:f64d43ff0c18 | 257 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 258 | //! @brief Set the CLKS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 259 | #define BW_MCG_C1_CLKS(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v))) |
mbed_official | 146:f64d43ff0c18 | 260 | #endif |
mbed_official | 146:f64d43ff0c18 | 261 | //@} |
mbed_official | 146:f64d43ff0c18 | 262 | |
mbed_official | 146:f64d43ff0c18 | 263 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 264 | // HW_MCG_C2 - MCG Control 2 Register |
mbed_official | 146:f64d43ff0c18 | 265 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 266 | |
mbed_official | 146:f64d43ff0c18 | 267 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 268 | /*! |
mbed_official | 146:f64d43ff0c18 | 269 | * @brief HW_MCG_C2 - MCG Control 2 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 270 | * |
mbed_official | 146:f64d43ff0c18 | 271 | * Reset value: 0x80U |
mbed_official | 146:f64d43ff0c18 | 272 | */ |
mbed_official | 146:f64d43ff0c18 | 273 | typedef union _hw_mcg_c2 |
mbed_official | 146:f64d43ff0c18 | 274 | { |
mbed_official | 146:f64d43ff0c18 | 275 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 276 | struct _hw_mcg_c2_bitfields |
mbed_official | 146:f64d43ff0c18 | 277 | { |
mbed_official | 146:f64d43ff0c18 | 278 | uint8_t IRCS : 1; //!< [0] Internal Reference Clock Select |
mbed_official | 146:f64d43ff0c18 | 279 | uint8_t LP : 1; //!< [1] Low Power Select |
mbed_official | 146:f64d43ff0c18 | 280 | uint8_t EREFS : 1; //!< [2] External Reference Select |
mbed_official | 146:f64d43ff0c18 | 281 | uint8_t HGO : 1; //!< [3] High Gain Oscillator Select |
mbed_official | 146:f64d43ff0c18 | 282 | uint8_t RANGE : 2; //!< [5:4] Frequency Range Select |
mbed_official | 146:f64d43ff0c18 | 283 | uint8_t FCFTRIM : 1; //!< [6] Fast Internal Reference Clock Fine Trim |
mbed_official | 146:f64d43ff0c18 | 284 | uint8_t LOCRE0 : 1; //!< [7] Loss of Clock Reset Enable |
mbed_official | 146:f64d43ff0c18 | 285 | } B; |
mbed_official | 146:f64d43ff0c18 | 286 | } hw_mcg_c2_t; |
mbed_official | 146:f64d43ff0c18 | 287 | #endif |
mbed_official | 146:f64d43ff0c18 | 288 | |
mbed_official | 146:f64d43ff0c18 | 289 | /*! |
mbed_official | 146:f64d43ff0c18 | 290 | * @name Constants and macros for entire MCG_C2 register |
mbed_official | 146:f64d43ff0c18 | 291 | */ |
mbed_official | 146:f64d43ff0c18 | 292 | //@{ |
mbed_official | 146:f64d43ff0c18 | 293 | #define HW_MCG_C2_ADDR (REGS_MCG_BASE + 0x1U) |
mbed_official | 146:f64d43ff0c18 | 294 | |
mbed_official | 146:f64d43ff0c18 | 295 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 296 | #define HW_MCG_C2 (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR) |
mbed_official | 146:f64d43ff0c18 | 297 | #define HW_MCG_C2_RD() (HW_MCG_C2.U) |
mbed_official | 146:f64d43ff0c18 | 298 | #define HW_MCG_C2_WR(v) (HW_MCG_C2.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 299 | #define HW_MCG_C2_SET(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 300 | #define HW_MCG_C2_CLR(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 301 | #define HW_MCG_C2_TOG(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 302 | #endif |
mbed_official | 146:f64d43ff0c18 | 303 | //@} |
mbed_official | 146:f64d43ff0c18 | 304 | |
mbed_official | 146:f64d43ff0c18 | 305 | /* |
mbed_official | 146:f64d43ff0c18 | 306 | * Constants & macros for individual MCG_C2 bitfields |
mbed_official | 146:f64d43ff0c18 | 307 | */ |
mbed_official | 146:f64d43ff0c18 | 308 | |
mbed_official | 146:f64d43ff0c18 | 309 | /*! |
mbed_official | 146:f64d43ff0c18 | 310 | * @name Register MCG_C2, field IRCS[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 311 | * |
mbed_official | 146:f64d43ff0c18 | 312 | * Selects between the fast or slow internal reference clock source. |
mbed_official | 146:f64d43ff0c18 | 313 | * |
mbed_official | 146:f64d43ff0c18 | 314 | * Values: |
mbed_official | 146:f64d43ff0c18 | 315 | * - 0 - Slow internal reference clock selected. |
mbed_official | 146:f64d43ff0c18 | 316 | * - 1 - Fast internal reference clock selected. |
mbed_official | 146:f64d43ff0c18 | 317 | */ |
mbed_official | 146:f64d43ff0c18 | 318 | //@{ |
mbed_official | 146:f64d43ff0c18 | 319 | #define BP_MCG_C2_IRCS (0U) //!< Bit position for MCG_C2_IRCS. |
mbed_official | 146:f64d43ff0c18 | 320 | #define BM_MCG_C2_IRCS (0x01U) //!< Bit mask for MCG_C2_IRCS. |
mbed_official | 146:f64d43ff0c18 | 321 | #define BS_MCG_C2_IRCS (1U) //!< Bit field size in bits for MCG_C2_IRCS. |
mbed_official | 146:f64d43ff0c18 | 322 | |
mbed_official | 146:f64d43ff0c18 | 323 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 324 | //! @brief Read current value of the MCG_C2_IRCS field. |
mbed_official | 146:f64d43ff0c18 | 325 | #define BR_MCG_C2_IRCS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS)) |
mbed_official | 146:f64d43ff0c18 | 326 | #endif |
mbed_official | 146:f64d43ff0c18 | 327 | |
mbed_official | 146:f64d43ff0c18 | 328 | //! @brief Format value for bitfield MCG_C2_IRCS. |
mbed_official | 146:f64d43ff0c18 | 329 | #define BF_MCG_C2_IRCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_IRCS), uint8_t) & BM_MCG_C2_IRCS) |
mbed_official | 146:f64d43ff0c18 | 330 | |
mbed_official | 146:f64d43ff0c18 | 331 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 332 | //! @brief Set the IRCS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 333 | #define BW_MCG_C2_IRCS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 334 | #endif |
mbed_official | 146:f64d43ff0c18 | 335 | //@} |
mbed_official | 146:f64d43ff0c18 | 336 | |
mbed_official | 146:f64d43ff0c18 | 337 | /*! |
mbed_official | 146:f64d43ff0c18 | 338 | * @name Register MCG_C2, field LP[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 339 | * |
mbed_official | 146:f64d43ff0c18 | 340 | * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or |
mbed_official | 146:f64d43ff0c18 | 341 | * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in |
mbed_official | 146:f64d43ff0c18 | 342 | * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any |
mbed_official | 146:f64d43ff0c18 | 343 | * other MCG mode, LP bit has no affect. |
mbed_official | 146:f64d43ff0c18 | 344 | * |
mbed_official | 146:f64d43ff0c18 | 345 | * Values: |
mbed_official | 146:f64d43ff0c18 | 346 | * - 0 - FLL or PLL is not disabled in bypass modes. |
mbed_official | 146:f64d43ff0c18 | 347 | * - 1 - FLL or PLL is disabled in bypass modes (lower power) |
mbed_official | 146:f64d43ff0c18 | 348 | */ |
mbed_official | 146:f64d43ff0c18 | 349 | //@{ |
mbed_official | 146:f64d43ff0c18 | 350 | #define BP_MCG_C2_LP (1U) //!< Bit position for MCG_C2_LP. |
mbed_official | 146:f64d43ff0c18 | 351 | #define BM_MCG_C2_LP (0x02U) //!< Bit mask for MCG_C2_LP. |
mbed_official | 146:f64d43ff0c18 | 352 | #define BS_MCG_C2_LP (1U) //!< Bit field size in bits for MCG_C2_LP. |
mbed_official | 146:f64d43ff0c18 | 353 | |
mbed_official | 146:f64d43ff0c18 | 354 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 355 | //! @brief Read current value of the MCG_C2_LP field. |
mbed_official | 146:f64d43ff0c18 | 356 | #define BR_MCG_C2_LP (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP)) |
mbed_official | 146:f64d43ff0c18 | 357 | #endif |
mbed_official | 146:f64d43ff0c18 | 358 | |
mbed_official | 146:f64d43ff0c18 | 359 | //! @brief Format value for bitfield MCG_C2_LP. |
mbed_official | 146:f64d43ff0c18 | 360 | #define BF_MCG_C2_LP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LP), uint8_t) & BM_MCG_C2_LP) |
mbed_official | 146:f64d43ff0c18 | 361 | |
mbed_official | 146:f64d43ff0c18 | 362 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 363 | //! @brief Set the LP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 364 | #define BW_MCG_C2_LP(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP) = (v)) |
mbed_official | 146:f64d43ff0c18 | 365 | #endif |
mbed_official | 146:f64d43ff0c18 | 366 | //@} |
mbed_official | 146:f64d43ff0c18 | 367 | |
mbed_official | 146:f64d43ff0c18 | 368 | /*! |
mbed_official | 146:f64d43ff0c18 | 369 | * @name Register MCG_C2, field EREFS[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 370 | * |
mbed_official | 146:f64d43ff0c18 | 371 | * Selects the source for the external reference clock. See the Oscillator (OSC) |
mbed_official | 146:f64d43ff0c18 | 372 | * chapter for more details. |
mbed_official | 146:f64d43ff0c18 | 373 | * |
mbed_official | 146:f64d43ff0c18 | 374 | * Values: |
mbed_official | 146:f64d43ff0c18 | 375 | * - 0 - External reference clock requested. |
mbed_official | 146:f64d43ff0c18 | 376 | * - 1 - Oscillator requested. |
mbed_official | 146:f64d43ff0c18 | 377 | */ |
mbed_official | 146:f64d43ff0c18 | 378 | //@{ |
mbed_official | 146:f64d43ff0c18 | 379 | #define BP_MCG_C2_EREFS (2U) //!< Bit position for MCG_C2_EREFS. |
mbed_official | 146:f64d43ff0c18 | 380 | #define BM_MCG_C2_EREFS (0x04U) //!< Bit mask for MCG_C2_EREFS. |
mbed_official | 146:f64d43ff0c18 | 381 | #define BS_MCG_C2_EREFS (1U) //!< Bit field size in bits for MCG_C2_EREFS. |
mbed_official | 146:f64d43ff0c18 | 382 | |
mbed_official | 146:f64d43ff0c18 | 383 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 384 | //! @brief Read current value of the MCG_C2_EREFS field. |
mbed_official | 146:f64d43ff0c18 | 385 | #define BR_MCG_C2_EREFS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS)) |
mbed_official | 146:f64d43ff0c18 | 386 | #endif |
mbed_official | 146:f64d43ff0c18 | 387 | |
mbed_official | 146:f64d43ff0c18 | 388 | //! @brief Format value for bitfield MCG_C2_EREFS. |
mbed_official | 146:f64d43ff0c18 | 389 | #define BF_MCG_C2_EREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_EREFS), uint8_t) & BM_MCG_C2_EREFS) |
mbed_official | 146:f64d43ff0c18 | 390 | |
mbed_official | 146:f64d43ff0c18 | 391 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 392 | //! @brief Set the EREFS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 393 | #define BW_MCG_C2_EREFS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 394 | #endif |
mbed_official | 146:f64d43ff0c18 | 395 | //@} |
mbed_official | 146:f64d43ff0c18 | 396 | |
mbed_official | 146:f64d43ff0c18 | 397 | /*! |
mbed_official | 146:f64d43ff0c18 | 398 | * @name Register MCG_C2, field HGO[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 399 | * |
mbed_official | 146:f64d43ff0c18 | 400 | * Controls the crystal oscillator mode of operation. See the Oscillator (OSC) |
mbed_official | 146:f64d43ff0c18 | 401 | * chapter for more details. |
mbed_official | 146:f64d43ff0c18 | 402 | * |
mbed_official | 146:f64d43ff0c18 | 403 | * Values: |
mbed_official | 146:f64d43ff0c18 | 404 | * - 0 - Configure crystal oscillator for low-power operation. |
mbed_official | 146:f64d43ff0c18 | 405 | * - 1 - Configure crystal oscillator for high-gain operation. |
mbed_official | 146:f64d43ff0c18 | 406 | */ |
mbed_official | 146:f64d43ff0c18 | 407 | //@{ |
mbed_official | 146:f64d43ff0c18 | 408 | #define BP_MCG_C2_HGO (3U) //!< Bit position for MCG_C2_HGO. |
mbed_official | 146:f64d43ff0c18 | 409 | #define BM_MCG_C2_HGO (0x08U) //!< Bit mask for MCG_C2_HGO. |
mbed_official | 146:f64d43ff0c18 | 410 | #define BS_MCG_C2_HGO (1U) //!< Bit field size in bits for MCG_C2_HGO. |
mbed_official | 146:f64d43ff0c18 | 411 | |
mbed_official | 146:f64d43ff0c18 | 412 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 413 | //! @brief Read current value of the MCG_C2_HGO field. |
mbed_official | 146:f64d43ff0c18 | 414 | #define BR_MCG_C2_HGO (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO)) |
mbed_official | 146:f64d43ff0c18 | 415 | #endif |
mbed_official | 146:f64d43ff0c18 | 416 | |
mbed_official | 146:f64d43ff0c18 | 417 | //! @brief Format value for bitfield MCG_C2_HGO. |
mbed_official | 146:f64d43ff0c18 | 418 | #define BF_MCG_C2_HGO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_HGO), uint8_t) & BM_MCG_C2_HGO) |
mbed_official | 146:f64d43ff0c18 | 419 | |
mbed_official | 146:f64d43ff0c18 | 420 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 421 | //! @brief Set the HGO field to a new value. |
mbed_official | 146:f64d43ff0c18 | 422 | #define BW_MCG_C2_HGO(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO) = (v)) |
mbed_official | 146:f64d43ff0c18 | 423 | #endif |
mbed_official | 146:f64d43ff0c18 | 424 | //@} |
mbed_official | 146:f64d43ff0c18 | 425 | |
mbed_official | 146:f64d43ff0c18 | 426 | /*! |
mbed_official | 146:f64d43ff0c18 | 427 | * @name Register MCG_C2, field RANGE[5:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 428 | * |
mbed_official | 146:f64d43ff0c18 | 429 | * Selects the frequency range for the crystal oscillator or external clock |
mbed_official | 146:f64d43ff0c18 | 430 | * source. See the Oscillator (OSC) chapter for more details and the device data |
mbed_official | 146:f64d43ff0c18 | 431 | * sheet for the frequency ranges used. |
mbed_official | 146:f64d43ff0c18 | 432 | * |
mbed_official | 146:f64d43ff0c18 | 433 | * Values: |
mbed_official | 146:f64d43ff0c18 | 434 | * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator . |
mbed_official | 146:f64d43ff0c18 | 435 | * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator . |
mbed_official | 146:f64d43ff0c18 | 436 | */ |
mbed_official | 146:f64d43ff0c18 | 437 | //@{ |
mbed_official | 146:f64d43ff0c18 | 438 | #define BP_MCG_C2_RANGE (4U) //!< Bit position for MCG_C2_RANGE. |
mbed_official | 146:f64d43ff0c18 | 439 | #define BM_MCG_C2_RANGE (0x30U) //!< Bit mask for MCG_C2_RANGE. |
mbed_official | 146:f64d43ff0c18 | 440 | #define BS_MCG_C2_RANGE (2U) //!< Bit field size in bits for MCG_C2_RANGE. |
mbed_official | 146:f64d43ff0c18 | 441 | |
mbed_official | 146:f64d43ff0c18 | 442 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 443 | //! @brief Read current value of the MCG_C2_RANGE field. |
mbed_official | 146:f64d43ff0c18 | 444 | #define BR_MCG_C2_RANGE (HW_MCG_C2.B.RANGE) |
mbed_official | 146:f64d43ff0c18 | 445 | #endif |
mbed_official | 146:f64d43ff0c18 | 446 | |
mbed_official | 146:f64d43ff0c18 | 447 | //! @brief Format value for bitfield MCG_C2_RANGE. |
mbed_official | 146:f64d43ff0c18 | 448 | #define BF_MCG_C2_RANGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_RANGE), uint8_t) & BM_MCG_C2_RANGE) |
mbed_official | 146:f64d43ff0c18 | 449 | |
mbed_official | 146:f64d43ff0c18 | 450 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 451 | //! @brief Set the RANGE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 452 | #define BW_MCG_C2_RANGE(v) (HW_MCG_C2_WR((HW_MCG_C2_RD() & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v))) |
mbed_official | 146:f64d43ff0c18 | 453 | #endif |
mbed_official | 146:f64d43ff0c18 | 454 | //@} |
mbed_official | 146:f64d43ff0c18 | 455 | |
mbed_official | 146:f64d43ff0c18 | 456 | /*! |
mbed_official | 146:f64d43ff0c18 | 457 | * @name Register MCG_C2, field FCFTRIM[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 458 | * |
mbed_official | 146:f64d43ff0c18 | 459 | * FCFTRIM controls the smallest adjustment of the fast internal reference clock |
mbed_official | 146:f64d43ff0c18 | 460 | * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM |
mbed_official | 146:f64d43ff0c18 | 461 | * decreases the period by the smallest amount possible. If an FCFTRIM value stored in |
mbed_official | 146:f64d43ff0c18 | 462 | * nonvolatile memory is to be used, it is your responsibility to copy that value |
mbed_official | 146:f64d43ff0c18 | 463 | * from the nonvolatile memory location to this bit. |
mbed_official | 146:f64d43ff0c18 | 464 | */ |
mbed_official | 146:f64d43ff0c18 | 465 | //@{ |
mbed_official | 146:f64d43ff0c18 | 466 | #define BP_MCG_C2_FCFTRIM (6U) //!< Bit position for MCG_C2_FCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 467 | #define BM_MCG_C2_FCFTRIM (0x40U) //!< Bit mask for MCG_C2_FCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 468 | #define BS_MCG_C2_FCFTRIM (1U) //!< Bit field size in bits for MCG_C2_FCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 469 | |
mbed_official | 146:f64d43ff0c18 | 470 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 471 | //! @brief Read current value of the MCG_C2_FCFTRIM field. |
mbed_official | 146:f64d43ff0c18 | 472 | #define BR_MCG_C2_FCFTRIM (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM)) |
mbed_official | 146:f64d43ff0c18 | 473 | #endif |
mbed_official | 146:f64d43ff0c18 | 474 | |
mbed_official | 146:f64d43ff0c18 | 475 | //! @brief Format value for bitfield MCG_C2_FCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 476 | #define BF_MCG_C2_FCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_FCFTRIM), uint8_t) & BM_MCG_C2_FCFTRIM) |
mbed_official | 146:f64d43ff0c18 | 477 | |
mbed_official | 146:f64d43ff0c18 | 478 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 479 | //! @brief Set the FCFTRIM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 480 | #define BW_MCG_C2_FCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM) = (v)) |
mbed_official | 146:f64d43ff0c18 | 481 | #endif |
mbed_official | 146:f64d43ff0c18 | 482 | //@} |
mbed_official | 146:f64d43ff0c18 | 483 | |
mbed_official | 146:f64d43ff0c18 | 484 | /*! |
mbed_official | 146:f64d43ff0c18 | 485 | * @name Register MCG_C2, field LOCRE0[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 486 | * |
mbed_official | 146:f64d43ff0c18 | 487 | * Determines whether an interrupt or a reset request is made following a loss |
mbed_official | 146:f64d43ff0c18 | 488 | * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is |
mbed_official | 146:f64d43ff0c18 | 489 | * set. |
mbed_official | 146:f64d43ff0c18 | 490 | * |
mbed_official | 146:f64d43ff0c18 | 491 | * Values: |
mbed_official | 146:f64d43ff0c18 | 492 | * - 0 - Interrupt request is generated on a loss of OSC0 external reference |
mbed_official | 146:f64d43ff0c18 | 493 | * clock. |
mbed_official | 146:f64d43ff0c18 | 494 | * - 1 - Generate a reset request on a loss of OSC0 external reference clock. |
mbed_official | 146:f64d43ff0c18 | 495 | */ |
mbed_official | 146:f64d43ff0c18 | 496 | //@{ |
mbed_official | 146:f64d43ff0c18 | 497 | #define BP_MCG_C2_LOCRE0 (7U) //!< Bit position for MCG_C2_LOCRE0. |
mbed_official | 146:f64d43ff0c18 | 498 | #define BM_MCG_C2_LOCRE0 (0x80U) //!< Bit mask for MCG_C2_LOCRE0. |
mbed_official | 146:f64d43ff0c18 | 499 | #define BS_MCG_C2_LOCRE0 (1U) //!< Bit field size in bits for MCG_C2_LOCRE0. |
mbed_official | 146:f64d43ff0c18 | 500 | |
mbed_official | 146:f64d43ff0c18 | 501 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 502 | //! @brief Read current value of the MCG_C2_LOCRE0 field. |
mbed_official | 146:f64d43ff0c18 | 503 | #define BR_MCG_C2_LOCRE0 (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0)) |
mbed_official | 146:f64d43ff0c18 | 504 | #endif |
mbed_official | 146:f64d43ff0c18 | 505 | |
mbed_official | 146:f64d43ff0c18 | 506 | //! @brief Format value for bitfield MCG_C2_LOCRE0. |
mbed_official | 146:f64d43ff0c18 | 507 | #define BF_MCG_C2_LOCRE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LOCRE0), uint8_t) & BM_MCG_C2_LOCRE0) |
mbed_official | 146:f64d43ff0c18 | 508 | |
mbed_official | 146:f64d43ff0c18 | 509 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 510 | //! @brief Set the LOCRE0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 511 | #define BW_MCG_C2_LOCRE0(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 512 | #endif |
mbed_official | 146:f64d43ff0c18 | 513 | //@} |
mbed_official | 146:f64d43ff0c18 | 514 | |
mbed_official | 146:f64d43ff0c18 | 515 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 516 | // HW_MCG_C3 - MCG Control 3 Register |
mbed_official | 146:f64d43ff0c18 | 517 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 518 | |
mbed_official | 146:f64d43ff0c18 | 519 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 520 | /*! |
mbed_official | 146:f64d43ff0c18 | 521 | * @brief HW_MCG_C3 - MCG Control 3 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 522 | * |
mbed_official | 146:f64d43ff0c18 | 523 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 524 | */ |
mbed_official | 146:f64d43ff0c18 | 525 | typedef union _hw_mcg_c3 |
mbed_official | 146:f64d43ff0c18 | 526 | { |
mbed_official | 146:f64d43ff0c18 | 527 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 528 | struct _hw_mcg_c3_bitfields |
mbed_official | 146:f64d43ff0c18 | 529 | { |
mbed_official | 146:f64d43ff0c18 | 530 | uint8_t SCTRIM : 8; //!< [7:0] Slow Internal Reference Clock Trim |
mbed_official | 146:f64d43ff0c18 | 531 | //! Setting |
mbed_official | 146:f64d43ff0c18 | 532 | } B; |
mbed_official | 146:f64d43ff0c18 | 533 | } hw_mcg_c3_t; |
mbed_official | 146:f64d43ff0c18 | 534 | #endif |
mbed_official | 146:f64d43ff0c18 | 535 | |
mbed_official | 146:f64d43ff0c18 | 536 | /*! |
mbed_official | 146:f64d43ff0c18 | 537 | * @name Constants and macros for entire MCG_C3 register |
mbed_official | 146:f64d43ff0c18 | 538 | */ |
mbed_official | 146:f64d43ff0c18 | 539 | //@{ |
mbed_official | 146:f64d43ff0c18 | 540 | #define HW_MCG_C3_ADDR (REGS_MCG_BASE + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 541 | |
mbed_official | 146:f64d43ff0c18 | 542 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 543 | #define HW_MCG_C3 (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR) |
mbed_official | 146:f64d43ff0c18 | 544 | #define HW_MCG_C3_RD() (HW_MCG_C3.U) |
mbed_official | 146:f64d43ff0c18 | 545 | #define HW_MCG_C3_WR(v) (HW_MCG_C3.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 546 | #define HW_MCG_C3_SET(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 547 | #define HW_MCG_C3_CLR(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 548 | #define HW_MCG_C3_TOG(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 549 | #endif |
mbed_official | 146:f64d43ff0c18 | 550 | //@} |
mbed_official | 146:f64d43ff0c18 | 551 | |
mbed_official | 146:f64d43ff0c18 | 552 | /* |
mbed_official | 146:f64d43ff0c18 | 553 | * Constants & macros for individual MCG_C3 bitfields |
mbed_official | 146:f64d43ff0c18 | 554 | */ |
mbed_official | 146:f64d43ff0c18 | 555 | |
mbed_official | 146:f64d43ff0c18 | 556 | /*! |
mbed_official | 146:f64d43ff0c18 | 557 | * @name Register MCG_C3, field SCTRIM[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 558 | * |
mbed_official | 146:f64d43ff0c18 | 559 | * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed |
mbed_official | 146:f64d43ff0c18 | 560 | * location. controls the slow internal reference clock frequency by controlling |
mbed_official | 146:f64d43ff0c18 | 561 | * the slow internal reference clock period. The SCTRIM bits are binary weighted, |
mbed_official | 146:f64d43ff0c18 | 562 | * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value |
mbed_official | 146:f64d43ff0c18 | 563 | * increases the period, and decreasing the value decreases the period. An additional |
mbed_official | 146:f64d43ff0c18 | 564 | * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, |
mbed_official | 146:f64d43ff0c18 | 565 | * this value is loaded with a factory trim value. If an SCTRIM value stored in |
mbed_official | 146:f64d43ff0c18 | 566 | * nonvolatile memory is to be used, it is your responsibility to copy that value |
mbed_official | 146:f64d43ff0c18 | 567 | * from the nonvolatile memory location to this register. |
mbed_official | 146:f64d43ff0c18 | 568 | */ |
mbed_official | 146:f64d43ff0c18 | 569 | //@{ |
mbed_official | 146:f64d43ff0c18 | 570 | #define BP_MCG_C3_SCTRIM (0U) //!< Bit position for MCG_C3_SCTRIM. |
mbed_official | 146:f64d43ff0c18 | 571 | #define BM_MCG_C3_SCTRIM (0xFFU) //!< Bit mask for MCG_C3_SCTRIM. |
mbed_official | 146:f64d43ff0c18 | 572 | #define BS_MCG_C3_SCTRIM (8U) //!< Bit field size in bits for MCG_C3_SCTRIM. |
mbed_official | 146:f64d43ff0c18 | 573 | |
mbed_official | 146:f64d43ff0c18 | 574 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 575 | //! @brief Read current value of the MCG_C3_SCTRIM field. |
mbed_official | 146:f64d43ff0c18 | 576 | #define BR_MCG_C3_SCTRIM (HW_MCG_C3.U) |
mbed_official | 146:f64d43ff0c18 | 577 | #endif |
mbed_official | 146:f64d43ff0c18 | 578 | |
mbed_official | 146:f64d43ff0c18 | 579 | //! @brief Format value for bitfield MCG_C3_SCTRIM. |
mbed_official | 146:f64d43ff0c18 | 580 | #define BF_MCG_C3_SCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C3_SCTRIM), uint8_t) & BM_MCG_C3_SCTRIM) |
mbed_official | 146:f64d43ff0c18 | 581 | |
mbed_official | 146:f64d43ff0c18 | 582 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 583 | //! @brief Set the SCTRIM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 584 | #define BW_MCG_C3_SCTRIM(v) (HW_MCG_C3_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 585 | #endif |
mbed_official | 146:f64d43ff0c18 | 586 | //@} |
mbed_official | 146:f64d43ff0c18 | 587 | |
mbed_official | 146:f64d43ff0c18 | 588 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 589 | // HW_MCG_C4 - MCG Control 4 Register |
mbed_official | 146:f64d43ff0c18 | 590 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 591 | |
mbed_official | 146:f64d43ff0c18 | 592 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 593 | /*! |
mbed_official | 146:f64d43ff0c18 | 594 | * @brief HW_MCG_C4 - MCG Control 4 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 595 | * |
mbed_official | 146:f64d43ff0c18 | 596 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 597 | * |
mbed_official | 146:f64d43ff0c18 | 598 | * Reset values for DRST and DMX32 bits are 0. |
mbed_official | 146:f64d43ff0c18 | 599 | */ |
mbed_official | 146:f64d43ff0c18 | 600 | typedef union _hw_mcg_c4 |
mbed_official | 146:f64d43ff0c18 | 601 | { |
mbed_official | 146:f64d43ff0c18 | 602 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 603 | struct _hw_mcg_c4_bitfields |
mbed_official | 146:f64d43ff0c18 | 604 | { |
mbed_official | 146:f64d43ff0c18 | 605 | uint8_t SCFTRIM : 1; //!< [0] Slow Internal Reference Clock Fine Trim |
mbed_official | 146:f64d43ff0c18 | 606 | uint8_t FCTRIM : 4; //!< [4:1] Fast Internal Reference Clock Trim |
mbed_official | 146:f64d43ff0c18 | 607 | //! Setting |
mbed_official | 146:f64d43ff0c18 | 608 | uint8_t DRST_DRS : 2; //!< [6:5] DCO Range Select |
mbed_official | 146:f64d43ff0c18 | 609 | uint8_t DMX32 : 1; //!< [7] DCO Maximum Frequency with 32.768 kHz |
mbed_official | 146:f64d43ff0c18 | 610 | //! Reference |
mbed_official | 146:f64d43ff0c18 | 611 | } B; |
mbed_official | 146:f64d43ff0c18 | 612 | } hw_mcg_c4_t; |
mbed_official | 146:f64d43ff0c18 | 613 | #endif |
mbed_official | 146:f64d43ff0c18 | 614 | |
mbed_official | 146:f64d43ff0c18 | 615 | /*! |
mbed_official | 146:f64d43ff0c18 | 616 | * @name Constants and macros for entire MCG_C4 register |
mbed_official | 146:f64d43ff0c18 | 617 | */ |
mbed_official | 146:f64d43ff0c18 | 618 | //@{ |
mbed_official | 146:f64d43ff0c18 | 619 | #define HW_MCG_C4_ADDR (REGS_MCG_BASE + 0x3U) |
mbed_official | 146:f64d43ff0c18 | 620 | |
mbed_official | 146:f64d43ff0c18 | 621 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 622 | #define HW_MCG_C4 (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR) |
mbed_official | 146:f64d43ff0c18 | 623 | #define HW_MCG_C4_RD() (HW_MCG_C4.U) |
mbed_official | 146:f64d43ff0c18 | 624 | #define HW_MCG_C4_WR(v) (HW_MCG_C4.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 625 | #define HW_MCG_C4_SET(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 626 | #define HW_MCG_C4_CLR(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 627 | #define HW_MCG_C4_TOG(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 628 | #endif |
mbed_official | 146:f64d43ff0c18 | 629 | //@} |
mbed_official | 146:f64d43ff0c18 | 630 | |
mbed_official | 146:f64d43ff0c18 | 631 | /* |
mbed_official | 146:f64d43ff0c18 | 632 | * Constants & macros for individual MCG_C4 bitfields |
mbed_official | 146:f64d43ff0c18 | 633 | */ |
mbed_official | 146:f64d43ff0c18 | 634 | |
mbed_official | 146:f64d43ff0c18 | 635 | /*! |
mbed_official | 146:f64d43ff0c18 | 636 | * @name Register MCG_C4, field SCFTRIM[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 637 | * |
mbed_official | 146:f64d43ff0c18 | 638 | * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed |
mbed_official | 146:f64d43ff0c18 | 639 | * location . controls the smallest adjustment of the slow internal reference |
mbed_official | 146:f64d43ff0c18 | 640 | * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM |
mbed_official | 146:f64d43ff0c18 | 641 | * decreases the period by the smallest amount possible. If an SCFTRIM value stored in |
mbed_official | 146:f64d43ff0c18 | 642 | * nonvolatile memory is to be used, it is your responsibility to copy that value |
mbed_official | 146:f64d43ff0c18 | 643 | * from the nonvolatile memory location to this bit. |
mbed_official | 146:f64d43ff0c18 | 644 | */ |
mbed_official | 146:f64d43ff0c18 | 645 | //@{ |
mbed_official | 146:f64d43ff0c18 | 646 | #define BP_MCG_C4_SCFTRIM (0U) //!< Bit position for MCG_C4_SCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 647 | #define BM_MCG_C4_SCFTRIM (0x01U) //!< Bit mask for MCG_C4_SCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 648 | #define BS_MCG_C4_SCFTRIM (1U) //!< Bit field size in bits for MCG_C4_SCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 649 | |
mbed_official | 146:f64d43ff0c18 | 650 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 651 | //! @brief Read current value of the MCG_C4_SCFTRIM field. |
mbed_official | 146:f64d43ff0c18 | 652 | #define BR_MCG_C4_SCFTRIM (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM)) |
mbed_official | 146:f64d43ff0c18 | 653 | #endif |
mbed_official | 146:f64d43ff0c18 | 654 | |
mbed_official | 146:f64d43ff0c18 | 655 | //! @brief Format value for bitfield MCG_C4_SCFTRIM. |
mbed_official | 146:f64d43ff0c18 | 656 | #define BF_MCG_C4_SCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_SCFTRIM), uint8_t) & BM_MCG_C4_SCFTRIM) |
mbed_official | 146:f64d43ff0c18 | 657 | |
mbed_official | 146:f64d43ff0c18 | 658 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 659 | //! @brief Set the SCFTRIM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 660 | #define BW_MCG_C4_SCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM) = (v)) |
mbed_official | 146:f64d43ff0c18 | 661 | #endif |
mbed_official | 146:f64d43ff0c18 | 662 | //@} |
mbed_official | 146:f64d43ff0c18 | 663 | |
mbed_official | 146:f64d43ff0c18 | 664 | /*! |
mbed_official | 146:f64d43ff0c18 | 665 | * @name Register MCG_C4, field FCTRIM[4:1] (RW) |
mbed_official | 146:f64d43ff0c18 | 666 | * |
mbed_official | 146:f64d43ff0c18 | 667 | * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed |
mbed_official | 146:f64d43ff0c18 | 668 | * location. controls the fast internal reference clock frequency by controlling |
mbed_official | 146:f64d43ff0c18 | 669 | * the fast internal reference clock period. The FCTRIM bits are binary weighted, |
mbed_official | 146:f64d43ff0c18 | 670 | * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value |
mbed_official | 146:f64d43ff0c18 | 671 | * increases the period, and decreasing the value decreases the period. If an |
mbed_official | 146:f64d43ff0c18 | 672 | * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your |
mbed_official | 146:f64d43ff0c18 | 673 | * responsibility to copy that value from the nonvolatile memory location to this register. |
mbed_official | 146:f64d43ff0c18 | 674 | */ |
mbed_official | 146:f64d43ff0c18 | 675 | //@{ |
mbed_official | 146:f64d43ff0c18 | 676 | #define BP_MCG_C4_FCTRIM (1U) //!< Bit position for MCG_C4_FCTRIM. |
mbed_official | 146:f64d43ff0c18 | 677 | #define BM_MCG_C4_FCTRIM (0x1EU) //!< Bit mask for MCG_C4_FCTRIM. |
mbed_official | 146:f64d43ff0c18 | 678 | #define BS_MCG_C4_FCTRIM (4U) //!< Bit field size in bits for MCG_C4_FCTRIM. |
mbed_official | 146:f64d43ff0c18 | 679 | |
mbed_official | 146:f64d43ff0c18 | 680 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 681 | //! @brief Read current value of the MCG_C4_FCTRIM field. |
mbed_official | 146:f64d43ff0c18 | 682 | #define BR_MCG_C4_FCTRIM (HW_MCG_C4.B.FCTRIM) |
mbed_official | 146:f64d43ff0c18 | 683 | #endif |
mbed_official | 146:f64d43ff0c18 | 684 | |
mbed_official | 146:f64d43ff0c18 | 685 | //! @brief Format value for bitfield MCG_C4_FCTRIM. |
mbed_official | 146:f64d43ff0c18 | 686 | #define BF_MCG_C4_FCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_FCTRIM), uint8_t) & BM_MCG_C4_FCTRIM) |
mbed_official | 146:f64d43ff0c18 | 687 | |
mbed_official | 146:f64d43ff0c18 | 688 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 689 | //! @brief Set the FCTRIM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 690 | #define BW_MCG_C4_FCTRIM(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v))) |
mbed_official | 146:f64d43ff0c18 | 691 | #endif |
mbed_official | 146:f64d43ff0c18 | 692 | //@} |
mbed_official | 146:f64d43ff0c18 | 693 | |
mbed_official | 146:f64d43ff0c18 | 694 | /*! |
mbed_official | 146:f64d43ff0c18 | 695 | * @name Register MCG_C4, field DRST_DRS[6:5] (RW) |
mbed_official | 146:f64d43ff0c18 | 696 | * |
mbed_official | 146:f64d43ff0c18 | 697 | * The DRS bits select the frequency range for the FLL output, DCOOUT. When the |
mbed_official | 146:f64d43ff0c18 | 698 | * LP bit is set, writes to the DRS bits are ignored. The DRST read field |
mbed_official | 146:f64d43ff0c18 | 699 | * indicates the current frequency range for DCOOUT. The DRST field does not update |
mbed_official | 146:f64d43ff0c18 | 700 | * immediately after a write to the DRS field due to internal synchronization between |
mbed_official | 146:f64d43ff0c18 | 701 | * clock domains. See the DCO Frequency Range table for more details. |
mbed_official | 146:f64d43ff0c18 | 702 | * |
mbed_official | 146:f64d43ff0c18 | 703 | * Values: |
mbed_official | 146:f64d43ff0c18 | 704 | * - 00 - Encoding 0 - Low range (reset default). |
mbed_official | 146:f64d43ff0c18 | 705 | * - 01 - Encoding 1 - Mid range. |
mbed_official | 146:f64d43ff0c18 | 706 | * - 10 - Encoding 2 - Mid-high range. |
mbed_official | 146:f64d43ff0c18 | 707 | * - 11 - Encoding 3 - High range. |
mbed_official | 146:f64d43ff0c18 | 708 | */ |
mbed_official | 146:f64d43ff0c18 | 709 | //@{ |
mbed_official | 146:f64d43ff0c18 | 710 | #define BP_MCG_C4_DRST_DRS (5U) //!< Bit position for MCG_C4_DRST_DRS. |
mbed_official | 146:f64d43ff0c18 | 711 | #define BM_MCG_C4_DRST_DRS (0x60U) //!< Bit mask for MCG_C4_DRST_DRS. |
mbed_official | 146:f64d43ff0c18 | 712 | #define BS_MCG_C4_DRST_DRS (2U) //!< Bit field size in bits for MCG_C4_DRST_DRS. |
mbed_official | 146:f64d43ff0c18 | 713 | |
mbed_official | 146:f64d43ff0c18 | 714 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 715 | //! @brief Read current value of the MCG_C4_DRST_DRS field. |
mbed_official | 146:f64d43ff0c18 | 716 | #define BR_MCG_C4_DRST_DRS (HW_MCG_C4.B.DRST_DRS) |
mbed_official | 146:f64d43ff0c18 | 717 | #endif |
mbed_official | 146:f64d43ff0c18 | 718 | |
mbed_official | 146:f64d43ff0c18 | 719 | //! @brief Format value for bitfield MCG_C4_DRST_DRS. |
mbed_official | 146:f64d43ff0c18 | 720 | #define BF_MCG_C4_DRST_DRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DRST_DRS), uint8_t) & BM_MCG_C4_DRST_DRS) |
mbed_official | 146:f64d43ff0c18 | 721 | |
mbed_official | 146:f64d43ff0c18 | 722 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 723 | //! @brief Set the DRST_DRS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 724 | #define BW_MCG_C4_DRST_DRS(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v))) |
mbed_official | 146:f64d43ff0c18 | 725 | #endif |
mbed_official | 146:f64d43ff0c18 | 726 | //@} |
mbed_official | 146:f64d43ff0c18 | 727 | |
mbed_official | 146:f64d43ff0c18 | 728 | /*! |
mbed_official | 146:f64d43ff0c18 | 729 | * @name Register MCG_C4, field DMX32[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 730 | * |
mbed_official | 146:f64d43ff0c18 | 731 | * The DMX32 bit controls whether the DCO frequency range is narrowed to its |
mbed_official | 146:f64d43ff0c18 | 732 | * maximum frequency with a 32.768 kHz reference. The following table identifies |
mbed_official | 146:f64d43ff0c18 | 733 | * settings for the DCO frequency range. The system clocks derived from this source |
mbed_official | 146:f64d43ff0c18 | 734 | * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL |
mbed_official | 146:f64d43ff0c18 | 735 | * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz |
mbed_official | 146:f64d43ff0c18 | 736 | * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0 |
mbed_official | 146:f64d43ff0c18 | 737 | * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560 |
mbed_official | 146:f64d43ff0c18 | 738 | * 80-100 MHz 1 32.768 kHz 2929 96 MHz |
mbed_official | 146:f64d43ff0c18 | 739 | * |
mbed_official | 146:f64d43ff0c18 | 740 | * Values: |
mbed_official | 146:f64d43ff0c18 | 741 | * - 0 - DCO has a default range of 25%. |
mbed_official | 146:f64d43ff0c18 | 742 | * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference. |
mbed_official | 146:f64d43ff0c18 | 743 | */ |
mbed_official | 146:f64d43ff0c18 | 744 | //@{ |
mbed_official | 146:f64d43ff0c18 | 745 | #define BP_MCG_C4_DMX32 (7U) //!< Bit position for MCG_C4_DMX32. |
mbed_official | 146:f64d43ff0c18 | 746 | #define BM_MCG_C4_DMX32 (0x80U) //!< Bit mask for MCG_C4_DMX32. |
mbed_official | 146:f64d43ff0c18 | 747 | #define BS_MCG_C4_DMX32 (1U) //!< Bit field size in bits for MCG_C4_DMX32. |
mbed_official | 146:f64d43ff0c18 | 748 | |
mbed_official | 146:f64d43ff0c18 | 749 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 750 | //! @brief Read current value of the MCG_C4_DMX32 field. |
mbed_official | 146:f64d43ff0c18 | 751 | #define BR_MCG_C4_DMX32 (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32)) |
mbed_official | 146:f64d43ff0c18 | 752 | #endif |
mbed_official | 146:f64d43ff0c18 | 753 | |
mbed_official | 146:f64d43ff0c18 | 754 | //! @brief Format value for bitfield MCG_C4_DMX32. |
mbed_official | 146:f64d43ff0c18 | 755 | #define BF_MCG_C4_DMX32(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DMX32), uint8_t) & BM_MCG_C4_DMX32) |
mbed_official | 146:f64d43ff0c18 | 756 | |
mbed_official | 146:f64d43ff0c18 | 757 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 758 | //! @brief Set the DMX32 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 759 | #define BW_MCG_C4_DMX32(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32) = (v)) |
mbed_official | 146:f64d43ff0c18 | 760 | #endif |
mbed_official | 146:f64d43ff0c18 | 761 | //@} |
mbed_official | 146:f64d43ff0c18 | 762 | |
mbed_official | 146:f64d43ff0c18 | 763 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 764 | // HW_MCG_C5 - MCG Control 5 Register |
mbed_official | 146:f64d43ff0c18 | 765 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 766 | |
mbed_official | 146:f64d43ff0c18 | 767 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 768 | /*! |
mbed_official | 146:f64d43ff0c18 | 769 | * @brief HW_MCG_C5 - MCG Control 5 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 770 | * |
mbed_official | 146:f64d43ff0c18 | 771 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 772 | */ |
mbed_official | 146:f64d43ff0c18 | 773 | typedef union _hw_mcg_c5 |
mbed_official | 146:f64d43ff0c18 | 774 | { |
mbed_official | 146:f64d43ff0c18 | 775 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 776 | struct _hw_mcg_c5_bitfields |
mbed_official | 146:f64d43ff0c18 | 777 | { |
mbed_official | 146:f64d43ff0c18 | 778 | uint8_t PRDIV0 : 5; //!< [4:0] PLL External Reference Divider |
mbed_official | 146:f64d43ff0c18 | 779 | uint8_t PLLSTEN0 : 1; //!< [5] PLL Stop Enable |
mbed_official | 146:f64d43ff0c18 | 780 | uint8_t PLLCLKEN0 : 1; //!< [6] PLL Clock Enable |
mbed_official | 146:f64d43ff0c18 | 781 | uint8_t RESERVED0 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 782 | } B; |
mbed_official | 146:f64d43ff0c18 | 783 | } hw_mcg_c5_t; |
mbed_official | 146:f64d43ff0c18 | 784 | #endif |
mbed_official | 146:f64d43ff0c18 | 785 | |
mbed_official | 146:f64d43ff0c18 | 786 | /*! |
mbed_official | 146:f64d43ff0c18 | 787 | * @name Constants and macros for entire MCG_C5 register |
mbed_official | 146:f64d43ff0c18 | 788 | */ |
mbed_official | 146:f64d43ff0c18 | 789 | //@{ |
mbed_official | 146:f64d43ff0c18 | 790 | #define HW_MCG_C5_ADDR (REGS_MCG_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 791 | |
mbed_official | 146:f64d43ff0c18 | 792 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 793 | #define HW_MCG_C5 (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR) |
mbed_official | 146:f64d43ff0c18 | 794 | #define HW_MCG_C5_RD() (HW_MCG_C5.U) |
mbed_official | 146:f64d43ff0c18 | 795 | #define HW_MCG_C5_WR(v) (HW_MCG_C5.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 796 | #define HW_MCG_C5_SET(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 797 | #define HW_MCG_C5_CLR(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 798 | #define HW_MCG_C5_TOG(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 799 | #endif |
mbed_official | 146:f64d43ff0c18 | 800 | //@} |
mbed_official | 146:f64d43ff0c18 | 801 | |
mbed_official | 146:f64d43ff0c18 | 802 | /* |
mbed_official | 146:f64d43ff0c18 | 803 | * Constants & macros for individual MCG_C5 bitfields |
mbed_official | 146:f64d43ff0c18 | 804 | */ |
mbed_official | 146:f64d43ff0c18 | 805 | |
mbed_official | 146:f64d43ff0c18 | 806 | /*! |
mbed_official | 146:f64d43ff0c18 | 807 | * @name Register MCG_C5, field PRDIV0[4:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 808 | * |
mbed_official | 146:f64d43ff0c18 | 809 | * Selects the amount to divide down the external reference clock for the PLL. |
mbed_official | 146:f64d43ff0c18 | 810 | * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL |
mbed_official | 146:f64d43ff0c18 | 811 | * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not |
mbed_official | 146:f64d43ff0c18 | 812 | * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0 |
mbed_official | 146:f64d43ff0c18 | 813 | * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor |
mbed_official | 146:f64d43ff0c18 | 814 | * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved |
mbed_official | 146:f64d43ff0c18 | 815 | * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved |
mbed_official | 146:f64d43ff0c18 | 816 | * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101 |
mbed_official | 146:f64d43ff0c18 | 817 | * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111 |
mbed_official | 146:f64d43ff0c18 | 818 | * Reserved |
mbed_official | 146:f64d43ff0c18 | 819 | */ |
mbed_official | 146:f64d43ff0c18 | 820 | //@{ |
mbed_official | 146:f64d43ff0c18 | 821 | #define BP_MCG_C5_PRDIV0 (0U) //!< Bit position for MCG_C5_PRDIV0. |
mbed_official | 146:f64d43ff0c18 | 822 | #define BM_MCG_C5_PRDIV0 (0x1FU) //!< Bit mask for MCG_C5_PRDIV0. |
mbed_official | 146:f64d43ff0c18 | 823 | #define BS_MCG_C5_PRDIV0 (5U) //!< Bit field size in bits for MCG_C5_PRDIV0. |
mbed_official | 146:f64d43ff0c18 | 824 | |
mbed_official | 146:f64d43ff0c18 | 825 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 826 | //! @brief Read current value of the MCG_C5_PRDIV0 field. |
mbed_official | 146:f64d43ff0c18 | 827 | #define BR_MCG_C5_PRDIV0 (HW_MCG_C5.B.PRDIV0) |
mbed_official | 146:f64d43ff0c18 | 828 | #endif |
mbed_official | 146:f64d43ff0c18 | 829 | |
mbed_official | 146:f64d43ff0c18 | 830 | //! @brief Format value for bitfield MCG_C5_PRDIV0. |
mbed_official | 146:f64d43ff0c18 | 831 | #define BF_MCG_C5_PRDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PRDIV0), uint8_t) & BM_MCG_C5_PRDIV0) |
mbed_official | 146:f64d43ff0c18 | 832 | |
mbed_official | 146:f64d43ff0c18 | 833 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 834 | //! @brief Set the PRDIV0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 835 | #define BW_MCG_C5_PRDIV0(v) (HW_MCG_C5_WR((HW_MCG_C5_RD() & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v))) |
mbed_official | 146:f64d43ff0c18 | 836 | #endif |
mbed_official | 146:f64d43ff0c18 | 837 | //@} |
mbed_official | 146:f64d43ff0c18 | 838 | |
mbed_official | 146:f64d43ff0c18 | 839 | /*! |
mbed_official | 146:f64d43ff0c18 | 840 | * @name Register MCG_C5, field PLLSTEN0[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 841 | * |
mbed_official | 146:f64d43ff0c18 | 842 | * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL |
mbed_official | 146:f64d43ff0c18 | 843 | * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit |
mbed_official | 146:f64d43ff0c18 | 844 | * has no affect and does not enable the PLL Clock to run if it is written to 1. |
mbed_official | 146:f64d43ff0c18 | 845 | * |
mbed_official | 146:f64d43ff0c18 | 846 | * Values: |
mbed_official | 146:f64d43ff0c18 | 847 | * - 0 - MCGPLLCLK is disabled in any of the Stop modes. |
mbed_official | 146:f64d43ff0c18 | 848 | * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode. |
mbed_official | 146:f64d43ff0c18 | 849 | */ |
mbed_official | 146:f64d43ff0c18 | 850 | //@{ |
mbed_official | 146:f64d43ff0c18 | 851 | #define BP_MCG_C5_PLLSTEN0 (5U) //!< Bit position for MCG_C5_PLLSTEN0. |
mbed_official | 146:f64d43ff0c18 | 852 | #define BM_MCG_C5_PLLSTEN0 (0x20U) //!< Bit mask for MCG_C5_PLLSTEN0. |
mbed_official | 146:f64d43ff0c18 | 853 | #define BS_MCG_C5_PLLSTEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLSTEN0. |
mbed_official | 146:f64d43ff0c18 | 854 | |
mbed_official | 146:f64d43ff0c18 | 855 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 856 | //! @brief Read current value of the MCG_C5_PLLSTEN0 field. |
mbed_official | 146:f64d43ff0c18 | 857 | #define BR_MCG_C5_PLLSTEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0)) |
mbed_official | 146:f64d43ff0c18 | 858 | #endif |
mbed_official | 146:f64d43ff0c18 | 859 | |
mbed_official | 146:f64d43ff0c18 | 860 | //! @brief Format value for bitfield MCG_C5_PLLSTEN0. |
mbed_official | 146:f64d43ff0c18 | 861 | #define BF_MCG_C5_PLLSTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLSTEN0), uint8_t) & BM_MCG_C5_PLLSTEN0) |
mbed_official | 146:f64d43ff0c18 | 862 | |
mbed_official | 146:f64d43ff0c18 | 863 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 864 | //! @brief Set the PLLSTEN0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 865 | #define BW_MCG_C5_PLLSTEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 866 | #endif |
mbed_official | 146:f64d43ff0c18 | 867 | //@} |
mbed_official | 146:f64d43ff0c18 | 868 | |
mbed_official | 146:f64d43ff0c18 | 869 | /*! |
mbed_official | 146:f64d43ff0c18 | 870 | * @name Register MCG_C5, field PLLCLKEN0[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 871 | * |
mbed_official | 146:f64d43ff0c18 | 872 | * Enables the PLL independent of PLLS and enables the PLL clock for use as |
mbed_official | 146:f64d43ff0c18 | 873 | * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a |
mbed_official | 146:f64d43ff0c18 | 874 | * PLL reference clock in the range of 2 - 4 MHz range prior to setting the |
mbed_official | 146:f64d43ff0c18 | 875 | * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not |
mbed_official | 146:f64d43ff0c18 | 876 | * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, |
mbed_official | 146:f64d43ff0c18 | 877 | * and the external oscillator is being used as the reference clock, the OSCINIT 0 |
mbed_official | 146:f64d43ff0c18 | 878 | * bit should be checked to make sure it is set. |
mbed_official | 146:f64d43ff0c18 | 879 | * |
mbed_official | 146:f64d43ff0c18 | 880 | * Values: |
mbed_official | 146:f64d43ff0c18 | 881 | * - 0 - MCGPLLCLK is inactive. |
mbed_official | 146:f64d43ff0c18 | 882 | * - 1 - MCGPLLCLK is active. |
mbed_official | 146:f64d43ff0c18 | 883 | */ |
mbed_official | 146:f64d43ff0c18 | 884 | //@{ |
mbed_official | 146:f64d43ff0c18 | 885 | #define BP_MCG_C5_PLLCLKEN0 (6U) //!< Bit position for MCG_C5_PLLCLKEN0. |
mbed_official | 146:f64d43ff0c18 | 886 | #define BM_MCG_C5_PLLCLKEN0 (0x40U) //!< Bit mask for MCG_C5_PLLCLKEN0. |
mbed_official | 146:f64d43ff0c18 | 887 | #define BS_MCG_C5_PLLCLKEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLCLKEN0. |
mbed_official | 146:f64d43ff0c18 | 888 | |
mbed_official | 146:f64d43ff0c18 | 889 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 890 | //! @brief Read current value of the MCG_C5_PLLCLKEN0 field. |
mbed_official | 146:f64d43ff0c18 | 891 | #define BR_MCG_C5_PLLCLKEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0)) |
mbed_official | 146:f64d43ff0c18 | 892 | #endif |
mbed_official | 146:f64d43ff0c18 | 893 | |
mbed_official | 146:f64d43ff0c18 | 894 | //! @brief Format value for bitfield MCG_C5_PLLCLKEN0. |
mbed_official | 146:f64d43ff0c18 | 895 | #define BF_MCG_C5_PLLCLKEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLCLKEN0), uint8_t) & BM_MCG_C5_PLLCLKEN0) |
mbed_official | 146:f64d43ff0c18 | 896 | |
mbed_official | 146:f64d43ff0c18 | 897 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 898 | //! @brief Set the PLLCLKEN0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 899 | #define BW_MCG_C5_PLLCLKEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 900 | #endif |
mbed_official | 146:f64d43ff0c18 | 901 | //@} |
mbed_official | 146:f64d43ff0c18 | 902 | |
mbed_official | 146:f64d43ff0c18 | 903 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 904 | // HW_MCG_C6 - MCG Control 6 Register |
mbed_official | 146:f64d43ff0c18 | 905 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 906 | |
mbed_official | 146:f64d43ff0c18 | 907 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 908 | /*! |
mbed_official | 146:f64d43ff0c18 | 909 | * @brief HW_MCG_C6 - MCG Control 6 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 910 | * |
mbed_official | 146:f64d43ff0c18 | 911 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 912 | */ |
mbed_official | 146:f64d43ff0c18 | 913 | typedef union _hw_mcg_c6 |
mbed_official | 146:f64d43ff0c18 | 914 | { |
mbed_official | 146:f64d43ff0c18 | 915 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 916 | struct _hw_mcg_c6_bitfields |
mbed_official | 146:f64d43ff0c18 | 917 | { |
mbed_official | 146:f64d43ff0c18 | 918 | uint8_t VDIV0 : 5; //!< [4:0] VCO 0 Divider |
mbed_official | 146:f64d43ff0c18 | 919 | uint8_t CME0 : 1; //!< [5] Clock Monitor Enable |
mbed_official | 146:f64d43ff0c18 | 920 | uint8_t PLLS : 1; //!< [6] PLL Select |
mbed_official | 146:f64d43ff0c18 | 921 | uint8_t LOLIE0 : 1; //!< [7] Loss of Lock Interrrupt Enable |
mbed_official | 146:f64d43ff0c18 | 922 | } B; |
mbed_official | 146:f64d43ff0c18 | 923 | } hw_mcg_c6_t; |
mbed_official | 146:f64d43ff0c18 | 924 | #endif |
mbed_official | 146:f64d43ff0c18 | 925 | |
mbed_official | 146:f64d43ff0c18 | 926 | /*! |
mbed_official | 146:f64d43ff0c18 | 927 | * @name Constants and macros for entire MCG_C6 register |
mbed_official | 146:f64d43ff0c18 | 928 | */ |
mbed_official | 146:f64d43ff0c18 | 929 | //@{ |
mbed_official | 146:f64d43ff0c18 | 930 | #define HW_MCG_C6_ADDR (REGS_MCG_BASE + 0x5U) |
mbed_official | 146:f64d43ff0c18 | 931 | |
mbed_official | 146:f64d43ff0c18 | 932 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 933 | #define HW_MCG_C6 (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR) |
mbed_official | 146:f64d43ff0c18 | 934 | #define HW_MCG_C6_RD() (HW_MCG_C6.U) |
mbed_official | 146:f64d43ff0c18 | 935 | #define HW_MCG_C6_WR(v) (HW_MCG_C6.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 936 | #define HW_MCG_C6_SET(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 937 | #define HW_MCG_C6_CLR(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 938 | #define HW_MCG_C6_TOG(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 939 | #endif |
mbed_official | 146:f64d43ff0c18 | 940 | //@} |
mbed_official | 146:f64d43ff0c18 | 941 | |
mbed_official | 146:f64d43ff0c18 | 942 | /* |
mbed_official | 146:f64d43ff0c18 | 943 | * Constants & macros for individual MCG_C6 bitfields |
mbed_official | 146:f64d43ff0c18 | 944 | */ |
mbed_official | 146:f64d43ff0c18 | 945 | |
mbed_official | 146:f64d43ff0c18 | 946 | /*! |
mbed_official | 146:f64d43ff0c18 | 947 | * @name Register MCG_C6, field VDIV0[4:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 948 | * |
mbed_official | 146:f64d43ff0c18 | 949 | * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits |
mbed_official | 146:f64d43ff0c18 | 950 | * establish the multiplication factor (M) applied to the reference clock frequency. |
mbed_official | 146:f64d43ff0c18 | 951 | * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0 |
mbed_official | 146:f64d43ff0c18 | 952 | * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0 |
mbed_official | 146:f64d43ff0c18 | 953 | * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply |
mbed_official | 146:f64d43ff0c18 | 954 | * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49 |
mbed_official | 146:f64d43ff0c18 | 955 | * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 |
mbed_official | 146:f64d43ff0c18 | 956 | * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 |
mbed_official | 146:f64d43ff0c18 | 957 | * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 |
mbed_official | 146:f64d43ff0c18 | 958 | */ |
mbed_official | 146:f64d43ff0c18 | 959 | //@{ |
mbed_official | 146:f64d43ff0c18 | 960 | #define BP_MCG_C6_VDIV0 (0U) //!< Bit position for MCG_C6_VDIV0. |
mbed_official | 146:f64d43ff0c18 | 961 | #define BM_MCG_C6_VDIV0 (0x1FU) //!< Bit mask for MCG_C6_VDIV0. |
mbed_official | 146:f64d43ff0c18 | 962 | #define BS_MCG_C6_VDIV0 (5U) //!< Bit field size in bits for MCG_C6_VDIV0. |
mbed_official | 146:f64d43ff0c18 | 963 | |
mbed_official | 146:f64d43ff0c18 | 964 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 965 | //! @brief Read current value of the MCG_C6_VDIV0 field. |
mbed_official | 146:f64d43ff0c18 | 966 | #define BR_MCG_C6_VDIV0 (HW_MCG_C6.B.VDIV0) |
mbed_official | 146:f64d43ff0c18 | 967 | #endif |
mbed_official | 146:f64d43ff0c18 | 968 | |
mbed_official | 146:f64d43ff0c18 | 969 | //! @brief Format value for bitfield MCG_C6_VDIV0. |
mbed_official | 146:f64d43ff0c18 | 970 | #define BF_MCG_C6_VDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_VDIV0), uint8_t) & BM_MCG_C6_VDIV0) |
mbed_official | 146:f64d43ff0c18 | 971 | |
mbed_official | 146:f64d43ff0c18 | 972 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 973 | //! @brief Set the VDIV0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 974 | #define BW_MCG_C6_VDIV0(v) (HW_MCG_C6_WR((HW_MCG_C6_RD() & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v))) |
mbed_official | 146:f64d43ff0c18 | 975 | #endif |
mbed_official | 146:f64d43ff0c18 | 976 | //@} |
mbed_official | 146:f64d43ff0c18 | 977 | |
mbed_official | 146:f64d43ff0c18 | 978 | /*! |
mbed_official | 146:f64d43ff0c18 | 979 | * @name Register MCG_C6, field CME0[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 980 | * |
mbed_official | 146:f64d43ff0c18 | 981 | * Enables the loss of clock monitoring circuit for the OSC0 external reference |
mbed_official | 146:f64d43ff0c18 | 982 | * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is |
mbed_official | 146:f64d43ff0c18 | 983 | * generated following a loss of OSC0 indication. The CME0 bit must only be set |
mbed_official | 146:f64d43ff0c18 | 984 | * to a logic 1 when the MCG is in an operational mode that uses the external |
mbed_official | 146:f64d43ff0c18 | 985 | * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, |
mbed_official | 146:f64d43ff0c18 | 986 | * the value of the RANGE0 bits in the C2 register should not be changed. CME0 |
mbed_official | 146:f64d43ff0c18 | 987 | * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a |
mbed_official | 146:f64d43ff0c18 | 988 | * reset request may occur while in Stop mode. CME0 should also be set to a |
mbed_official | 146:f64d43ff0c18 | 989 | * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. |
mbed_official | 146:f64d43ff0c18 | 990 | * |
mbed_official | 146:f64d43ff0c18 | 991 | * Values: |
mbed_official | 146:f64d43ff0c18 | 992 | * - 0 - External clock monitor is disabled for OSC0. |
mbed_official | 146:f64d43ff0c18 | 993 | * - 1 - External clock monitor is enabled for OSC0. |
mbed_official | 146:f64d43ff0c18 | 994 | */ |
mbed_official | 146:f64d43ff0c18 | 995 | //@{ |
mbed_official | 146:f64d43ff0c18 | 996 | #define BP_MCG_C6_CME0 (5U) //!< Bit position for MCG_C6_CME0. |
mbed_official | 146:f64d43ff0c18 | 997 | #define BM_MCG_C6_CME0 (0x20U) //!< Bit mask for MCG_C6_CME0. |
mbed_official | 146:f64d43ff0c18 | 998 | #define BS_MCG_C6_CME0 (1U) //!< Bit field size in bits for MCG_C6_CME0. |
mbed_official | 146:f64d43ff0c18 | 999 | |
mbed_official | 146:f64d43ff0c18 | 1000 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1001 | //! @brief Read current value of the MCG_C6_CME0 field. |
mbed_official | 146:f64d43ff0c18 | 1002 | #define BR_MCG_C6_CME0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0)) |
mbed_official | 146:f64d43ff0c18 | 1003 | #endif |
mbed_official | 146:f64d43ff0c18 | 1004 | |
mbed_official | 146:f64d43ff0c18 | 1005 | //! @brief Format value for bitfield MCG_C6_CME0. |
mbed_official | 146:f64d43ff0c18 | 1006 | #define BF_MCG_C6_CME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_CME0), uint8_t) & BM_MCG_C6_CME0) |
mbed_official | 146:f64d43ff0c18 | 1007 | |
mbed_official | 146:f64d43ff0c18 | 1008 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1009 | //! @brief Set the CME0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1010 | #define BW_MCG_C6_CME0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1011 | #endif |
mbed_official | 146:f64d43ff0c18 | 1012 | //@} |
mbed_official | 146:f64d43ff0c18 | 1013 | |
mbed_official | 146:f64d43ff0c18 | 1014 | /*! |
mbed_official | 146:f64d43ff0c18 | 1015 | * @name Register MCG_C6, field PLLS[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1016 | * |
mbed_official | 146:f64d43ff0c18 | 1017 | * Controls whether the PLL or FLL output is selected as the MCG source when |
mbed_official | 146:f64d43ff0c18 | 1018 | * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is |
mbed_official | 146:f64d43ff0c18 | 1019 | * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. |
mbed_official | 146:f64d43ff0c18 | 1020 | * |
mbed_official | 146:f64d43ff0c18 | 1021 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1022 | * - 0 - FLL is selected. |
mbed_official | 146:f64d43ff0c18 | 1023 | * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider |
mbed_official | 146:f64d43ff0c18 | 1024 | * to generate a PLL reference clock in the range of 2-4 MHz prior to setting |
mbed_official | 146:f64d43ff0c18 | 1025 | * the PLLS bit). |
mbed_official | 146:f64d43ff0c18 | 1026 | */ |
mbed_official | 146:f64d43ff0c18 | 1027 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1028 | #define BP_MCG_C6_PLLS (6U) //!< Bit position for MCG_C6_PLLS. |
mbed_official | 146:f64d43ff0c18 | 1029 | #define BM_MCG_C6_PLLS (0x40U) //!< Bit mask for MCG_C6_PLLS. |
mbed_official | 146:f64d43ff0c18 | 1030 | #define BS_MCG_C6_PLLS (1U) //!< Bit field size in bits for MCG_C6_PLLS. |
mbed_official | 146:f64d43ff0c18 | 1031 | |
mbed_official | 146:f64d43ff0c18 | 1032 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1033 | //! @brief Read current value of the MCG_C6_PLLS field. |
mbed_official | 146:f64d43ff0c18 | 1034 | #define BR_MCG_C6_PLLS (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS)) |
mbed_official | 146:f64d43ff0c18 | 1035 | #endif |
mbed_official | 146:f64d43ff0c18 | 1036 | |
mbed_official | 146:f64d43ff0c18 | 1037 | //! @brief Format value for bitfield MCG_C6_PLLS. |
mbed_official | 146:f64d43ff0c18 | 1038 | #define BF_MCG_C6_PLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_PLLS), uint8_t) & BM_MCG_C6_PLLS) |
mbed_official | 146:f64d43ff0c18 | 1039 | |
mbed_official | 146:f64d43ff0c18 | 1040 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1041 | //! @brief Set the PLLS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1042 | #define BW_MCG_C6_PLLS(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1043 | #endif |
mbed_official | 146:f64d43ff0c18 | 1044 | //@} |
mbed_official | 146:f64d43ff0c18 | 1045 | |
mbed_official | 146:f64d43ff0c18 | 1046 | /*! |
mbed_official | 146:f64d43ff0c18 | 1047 | * @name Register MCG_C6, field LOLIE0[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1048 | * |
mbed_official | 146:f64d43ff0c18 | 1049 | * Determines if an interrupt request is made following a loss of lock |
mbed_official | 146:f64d43ff0c18 | 1050 | * indication. This bit only has an effect when LOLS 0 is set. |
mbed_official | 146:f64d43ff0c18 | 1051 | * |
mbed_official | 146:f64d43ff0c18 | 1052 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1053 | * - 0 - No interrupt request is generated on loss of lock. |
mbed_official | 146:f64d43ff0c18 | 1054 | * - 1 - Generate an interrupt request on loss of lock. |
mbed_official | 146:f64d43ff0c18 | 1055 | */ |
mbed_official | 146:f64d43ff0c18 | 1056 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1057 | #define BP_MCG_C6_LOLIE0 (7U) //!< Bit position for MCG_C6_LOLIE0. |
mbed_official | 146:f64d43ff0c18 | 1058 | #define BM_MCG_C6_LOLIE0 (0x80U) //!< Bit mask for MCG_C6_LOLIE0. |
mbed_official | 146:f64d43ff0c18 | 1059 | #define BS_MCG_C6_LOLIE0 (1U) //!< Bit field size in bits for MCG_C6_LOLIE0. |
mbed_official | 146:f64d43ff0c18 | 1060 | |
mbed_official | 146:f64d43ff0c18 | 1061 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1062 | //! @brief Read current value of the MCG_C6_LOLIE0 field. |
mbed_official | 146:f64d43ff0c18 | 1063 | #define BR_MCG_C6_LOLIE0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0)) |
mbed_official | 146:f64d43ff0c18 | 1064 | #endif |
mbed_official | 146:f64d43ff0c18 | 1065 | |
mbed_official | 146:f64d43ff0c18 | 1066 | //! @brief Format value for bitfield MCG_C6_LOLIE0. |
mbed_official | 146:f64d43ff0c18 | 1067 | #define BF_MCG_C6_LOLIE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_LOLIE0), uint8_t) & BM_MCG_C6_LOLIE0) |
mbed_official | 146:f64d43ff0c18 | 1068 | |
mbed_official | 146:f64d43ff0c18 | 1069 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1070 | //! @brief Set the LOLIE0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1071 | #define BW_MCG_C6_LOLIE0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1072 | #endif |
mbed_official | 146:f64d43ff0c18 | 1073 | //@} |
mbed_official | 146:f64d43ff0c18 | 1074 | |
mbed_official | 146:f64d43ff0c18 | 1075 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1076 | // HW_MCG_S - MCG Status Register |
mbed_official | 146:f64d43ff0c18 | 1077 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1078 | |
mbed_official | 146:f64d43ff0c18 | 1079 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1080 | /*! |
mbed_official | 146:f64d43ff0c18 | 1081 | * @brief HW_MCG_S - MCG Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1082 | * |
mbed_official | 146:f64d43ff0c18 | 1083 | * Reset value: 0x10U |
mbed_official | 146:f64d43ff0c18 | 1084 | */ |
mbed_official | 146:f64d43ff0c18 | 1085 | typedef union _hw_mcg_s |
mbed_official | 146:f64d43ff0c18 | 1086 | { |
mbed_official | 146:f64d43ff0c18 | 1087 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1088 | struct _hw_mcg_s_bitfields |
mbed_official | 146:f64d43ff0c18 | 1089 | { |
mbed_official | 146:f64d43ff0c18 | 1090 | uint8_t IRCST : 1; //!< [0] Internal Reference Clock Status |
mbed_official | 146:f64d43ff0c18 | 1091 | uint8_t OSCINIT0 : 1; //!< [1] OSC Initialization |
mbed_official | 146:f64d43ff0c18 | 1092 | uint8_t CLKST : 2; //!< [3:2] Clock Mode Status |
mbed_official | 146:f64d43ff0c18 | 1093 | uint8_t IREFST : 1; //!< [4] Internal Reference Status |
mbed_official | 146:f64d43ff0c18 | 1094 | uint8_t PLLST : 1; //!< [5] PLL Select Status |
mbed_official | 146:f64d43ff0c18 | 1095 | uint8_t LOCK0 : 1; //!< [6] Lock Status |
mbed_official | 146:f64d43ff0c18 | 1096 | uint8_t LOLS0 : 1; //!< [7] Loss of Lock Status |
mbed_official | 146:f64d43ff0c18 | 1097 | } B; |
mbed_official | 146:f64d43ff0c18 | 1098 | } hw_mcg_s_t; |
mbed_official | 146:f64d43ff0c18 | 1099 | #endif |
mbed_official | 146:f64d43ff0c18 | 1100 | |
mbed_official | 146:f64d43ff0c18 | 1101 | /*! |
mbed_official | 146:f64d43ff0c18 | 1102 | * @name Constants and macros for entire MCG_S register |
mbed_official | 146:f64d43ff0c18 | 1103 | */ |
mbed_official | 146:f64d43ff0c18 | 1104 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1105 | #define HW_MCG_S_ADDR (REGS_MCG_BASE + 0x6U) |
mbed_official | 146:f64d43ff0c18 | 1106 | |
mbed_official | 146:f64d43ff0c18 | 1107 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1108 | #define HW_MCG_S (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1109 | #define HW_MCG_S_RD() (HW_MCG_S.U) |
mbed_official | 146:f64d43ff0c18 | 1110 | #define HW_MCG_S_WR(v) (HW_MCG_S.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1111 | #define HW_MCG_S_SET(v) (HW_MCG_S_WR(HW_MCG_S_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1112 | #define HW_MCG_S_CLR(v) (HW_MCG_S_WR(HW_MCG_S_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1113 | #define HW_MCG_S_TOG(v) (HW_MCG_S_WR(HW_MCG_S_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1114 | #endif |
mbed_official | 146:f64d43ff0c18 | 1115 | //@} |
mbed_official | 146:f64d43ff0c18 | 1116 | |
mbed_official | 146:f64d43ff0c18 | 1117 | /* |
mbed_official | 146:f64d43ff0c18 | 1118 | * Constants & macros for individual MCG_S bitfields |
mbed_official | 146:f64d43ff0c18 | 1119 | */ |
mbed_official | 146:f64d43ff0c18 | 1120 | |
mbed_official | 146:f64d43ff0c18 | 1121 | /*! |
mbed_official | 146:f64d43ff0c18 | 1122 | * @name Register MCG_S, field IRCST[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 1123 | * |
mbed_official | 146:f64d43ff0c18 | 1124 | * The IRCST bit indicates the current source for the internal reference clock |
mbed_official | 146:f64d43ff0c18 | 1125 | * select clock (IRCSCLK). The IRCST bit does not update immediately after a write |
mbed_official | 146:f64d43ff0c18 | 1126 | * to the IRCS bit due to internal synchronization between clock domains. The |
mbed_official | 146:f64d43ff0c18 | 1127 | * IRCST bit will only be updated if the internal reference clock is enabled, |
mbed_official | 146:f64d43ff0c18 | 1128 | * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] |
mbed_official | 146:f64d43ff0c18 | 1129 | * bit . |
mbed_official | 146:f64d43ff0c18 | 1130 | * |
mbed_official | 146:f64d43ff0c18 | 1131 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1132 | * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC). |
mbed_official | 146:f64d43ff0c18 | 1133 | * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC). |
mbed_official | 146:f64d43ff0c18 | 1134 | */ |
mbed_official | 146:f64d43ff0c18 | 1135 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1136 | #define BP_MCG_S_IRCST (0U) //!< Bit position for MCG_S_IRCST. |
mbed_official | 146:f64d43ff0c18 | 1137 | #define BM_MCG_S_IRCST (0x01U) //!< Bit mask for MCG_S_IRCST. |
mbed_official | 146:f64d43ff0c18 | 1138 | #define BS_MCG_S_IRCST (1U) //!< Bit field size in bits for MCG_S_IRCST. |
mbed_official | 146:f64d43ff0c18 | 1139 | |
mbed_official | 146:f64d43ff0c18 | 1140 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1141 | //! @brief Read current value of the MCG_S_IRCST field. |
mbed_official | 146:f64d43ff0c18 | 1142 | #define BR_MCG_S_IRCST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IRCST)) |
mbed_official | 146:f64d43ff0c18 | 1143 | #endif |
mbed_official | 146:f64d43ff0c18 | 1144 | //@} |
mbed_official | 146:f64d43ff0c18 | 1145 | |
mbed_official | 146:f64d43ff0c18 | 1146 | /*! |
mbed_official | 146:f64d43ff0c18 | 1147 | * @name Register MCG_S, field OSCINIT0[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 1148 | * |
mbed_official | 146:f64d43ff0c18 | 1149 | * This bit, which resets to 0, is set to 1 after the initialization cycles of |
mbed_official | 146:f64d43ff0c18 | 1150 | * the crystal oscillator clock have completed. After being set, the bit is |
mbed_official | 146:f64d43ff0c18 | 1151 | * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed |
mbed_official | 146:f64d43ff0c18 | 1152 | * description for more information. |
mbed_official | 146:f64d43ff0c18 | 1153 | */ |
mbed_official | 146:f64d43ff0c18 | 1154 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1155 | #define BP_MCG_S_OSCINIT0 (1U) //!< Bit position for MCG_S_OSCINIT0. |
mbed_official | 146:f64d43ff0c18 | 1156 | #define BM_MCG_S_OSCINIT0 (0x02U) //!< Bit mask for MCG_S_OSCINIT0. |
mbed_official | 146:f64d43ff0c18 | 1157 | #define BS_MCG_S_OSCINIT0 (1U) //!< Bit field size in bits for MCG_S_OSCINIT0. |
mbed_official | 146:f64d43ff0c18 | 1158 | |
mbed_official | 146:f64d43ff0c18 | 1159 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1160 | //! @brief Read current value of the MCG_S_OSCINIT0 field. |
mbed_official | 146:f64d43ff0c18 | 1161 | #define BR_MCG_S_OSCINIT0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_OSCINIT0)) |
mbed_official | 146:f64d43ff0c18 | 1162 | #endif |
mbed_official | 146:f64d43ff0c18 | 1163 | //@} |
mbed_official | 146:f64d43ff0c18 | 1164 | |
mbed_official | 146:f64d43ff0c18 | 1165 | /*! |
mbed_official | 146:f64d43ff0c18 | 1166 | * @name Register MCG_S, field CLKST[3:2] (RO) |
mbed_official | 146:f64d43ff0c18 | 1167 | * |
mbed_official | 146:f64d43ff0c18 | 1168 | * These bits indicate the current clock mode. The CLKST bits do not update |
mbed_official | 146:f64d43ff0c18 | 1169 | * immediately after a write to the CLKS bits due to internal synchronization between |
mbed_official | 146:f64d43ff0c18 | 1170 | * clock domains. |
mbed_official | 146:f64d43ff0c18 | 1171 | * |
mbed_official | 146:f64d43ff0c18 | 1172 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1173 | * - 00 - Encoding 0 - Output of the FLL is selected (reset default). |
mbed_official | 146:f64d43ff0c18 | 1174 | * - 01 - Encoding 1 - Internal reference clock is selected. |
mbed_official | 146:f64d43ff0c18 | 1175 | * - 10 - Encoding 2 - External reference clock is selected. |
mbed_official | 146:f64d43ff0c18 | 1176 | * - 11 - Encoding 3 - Output of the PLL is selected. |
mbed_official | 146:f64d43ff0c18 | 1177 | */ |
mbed_official | 146:f64d43ff0c18 | 1178 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1179 | #define BP_MCG_S_CLKST (2U) //!< Bit position for MCG_S_CLKST. |
mbed_official | 146:f64d43ff0c18 | 1180 | #define BM_MCG_S_CLKST (0x0CU) //!< Bit mask for MCG_S_CLKST. |
mbed_official | 146:f64d43ff0c18 | 1181 | #define BS_MCG_S_CLKST (2U) //!< Bit field size in bits for MCG_S_CLKST. |
mbed_official | 146:f64d43ff0c18 | 1182 | |
mbed_official | 146:f64d43ff0c18 | 1183 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1184 | //! @brief Read current value of the MCG_S_CLKST field. |
mbed_official | 146:f64d43ff0c18 | 1185 | #define BR_MCG_S_CLKST (HW_MCG_S.B.CLKST) |
mbed_official | 146:f64d43ff0c18 | 1186 | #endif |
mbed_official | 146:f64d43ff0c18 | 1187 | //@} |
mbed_official | 146:f64d43ff0c18 | 1188 | |
mbed_official | 146:f64d43ff0c18 | 1189 | /*! |
mbed_official | 146:f64d43ff0c18 | 1190 | * @name Register MCG_S, field IREFST[4] (RO) |
mbed_official | 146:f64d43ff0c18 | 1191 | * |
mbed_official | 146:f64d43ff0c18 | 1192 | * This bit indicates the current source for the FLL reference clock. The IREFST |
mbed_official | 146:f64d43ff0c18 | 1193 | * bit does not update immediately after a write to the IREFS bit due to |
mbed_official | 146:f64d43ff0c18 | 1194 | * internal synchronization between clock domains. |
mbed_official | 146:f64d43ff0c18 | 1195 | * |
mbed_official | 146:f64d43ff0c18 | 1196 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1197 | * - 0 - Source of FLL reference clock is the external reference clock. |
mbed_official | 146:f64d43ff0c18 | 1198 | * - 1 - Source of FLL reference clock is the internal reference clock. |
mbed_official | 146:f64d43ff0c18 | 1199 | */ |
mbed_official | 146:f64d43ff0c18 | 1200 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1201 | #define BP_MCG_S_IREFST (4U) //!< Bit position for MCG_S_IREFST. |
mbed_official | 146:f64d43ff0c18 | 1202 | #define BM_MCG_S_IREFST (0x10U) //!< Bit mask for MCG_S_IREFST. |
mbed_official | 146:f64d43ff0c18 | 1203 | #define BS_MCG_S_IREFST (1U) //!< Bit field size in bits for MCG_S_IREFST. |
mbed_official | 146:f64d43ff0c18 | 1204 | |
mbed_official | 146:f64d43ff0c18 | 1205 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1206 | //! @brief Read current value of the MCG_S_IREFST field. |
mbed_official | 146:f64d43ff0c18 | 1207 | #define BR_MCG_S_IREFST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IREFST)) |
mbed_official | 146:f64d43ff0c18 | 1208 | #endif |
mbed_official | 146:f64d43ff0c18 | 1209 | //@} |
mbed_official | 146:f64d43ff0c18 | 1210 | |
mbed_official | 146:f64d43ff0c18 | 1211 | /*! |
mbed_official | 146:f64d43ff0c18 | 1212 | * @name Register MCG_S, field PLLST[5] (RO) |
mbed_official | 146:f64d43ff0c18 | 1213 | * |
mbed_official | 146:f64d43ff0c18 | 1214 | * This bit indicates the clock source selected by PLLS . The PLLST bit does not |
mbed_official | 146:f64d43ff0c18 | 1215 | * update immediately after a write to the PLLS bit due to internal |
mbed_official | 146:f64d43ff0c18 | 1216 | * synchronization between clock domains. |
mbed_official | 146:f64d43ff0c18 | 1217 | * |
mbed_official | 146:f64d43ff0c18 | 1218 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1219 | * - 0 - Source of PLLS clock is FLL clock. |
mbed_official | 146:f64d43ff0c18 | 1220 | * - 1 - Source of PLLS clock is PLL output clock. |
mbed_official | 146:f64d43ff0c18 | 1221 | */ |
mbed_official | 146:f64d43ff0c18 | 1222 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1223 | #define BP_MCG_S_PLLST (5U) //!< Bit position for MCG_S_PLLST. |
mbed_official | 146:f64d43ff0c18 | 1224 | #define BM_MCG_S_PLLST (0x20U) //!< Bit mask for MCG_S_PLLST. |
mbed_official | 146:f64d43ff0c18 | 1225 | #define BS_MCG_S_PLLST (1U) //!< Bit field size in bits for MCG_S_PLLST. |
mbed_official | 146:f64d43ff0c18 | 1226 | |
mbed_official | 146:f64d43ff0c18 | 1227 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1228 | //! @brief Read current value of the MCG_S_PLLST field. |
mbed_official | 146:f64d43ff0c18 | 1229 | #define BR_MCG_S_PLLST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_PLLST)) |
mbed_official | 146:f64d43ff0c18 | 1230 | #endif |
mbed_official | 146:f64d43ff0c18 | 1231 | //@} |
mbed_official | 146:f64d43ff0c18 | 1232 | |
mbed_official | 146:f64d43ff0c18 | 1233 | /*! |
mbed_official | 146:f64d43ff0c18 | 1234 | * @name Register MCG_S, field LOCK0[6] (RO) |
mbed_official | 146:f64d43ff0c18 | 1235 | * |
mbed_official | 146:f64d43ff0c18 | 1236 | * This bit indicates whether the PLL has acquired lock. Lock detection is only |
mbed_official | 146:f64d43ff0c18 | 1237 | * enabled when the PLL is enabled (either through clock mode selection or |
mbed_official | 146:f64d43ff0c18 | 1238 | * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the |
mbed_official | 146:f64d43ff0c18 | 1239 | * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. |
mbed_official | 146:f64d43ff0c18 | 1240 | * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in |
mbed_official | 146:f64d43ff0c18 | 1241 | * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock |
mbed_official | 146:f64d43ff0c18 | 1242 | * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL |
mbed_official | 146:f64d43ff0c18 | 1243 | * reference clock will also cause the LOCK0 bit to clear until the PLL has |
mbed_official | 146:f64d43ff0c18 | 1244 | * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes |
mbed_official | 146:f64d43ff0c18 | 1245 | * the lock status bit to clear and stay cleared until the Stop mode is exited |
mbed_official | 146:f64d43ff0c18 | 1246 | * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit |
mbed_official | 146:f64d43ff0c18 | 1247 | * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted |
mbed_official | 146:f64d43ff0c18 | 1248 | * again. |
mbed_official | 146:f64d43ff0c18 | 1249 | * |
mbed_official | 146:f64d43ff0c18 | 1250 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1251 | * - 0 - PLL is currently unlocked. |
mbed_official | 146:f64d43ff0c18 | 1252 | * - 1 - PLL is currently locked. |
mbed_official | 146:f64d43ff0c18 | 1253 | */ |
mbed_official | 146:f64d43ff0c18 | 1254 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1255 | #define BP_MCG_S_LOCK0 (6U) //!< Bit position for MCG_S_LOCK0. |
mbed_official | 146:f64d43ff0c18 | 1256 | #define BM_MCG_S_LOCK0 (0x40U) //!< Bit mask for MCG_S_LOCK0. |
mbed_official | 146:f64d43ff0c18 | 1257 | #define BS_MCG_S_LOCK0 (1U) //!< Bit field size in bits for MCG_S_LOCK0. |
mbed_official | 146:f64d43ff0c18 | 1258 | |
mbed_official | 146:f64d43ff0c18 | 1259 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1260 | //! @brief Read current value of the MCG_S_LOCK0 field. |
mbed_official | 146:f64d43ff0c18 | 1261 | #define BR_MCG_S_LOCK0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOCK0)) |
mbed_official | 146:f64d43ff0c18 | 1262 | #endif |
mbed_official | 146:f64d43ff0c18 | 1263 | //@} |
mbed_official | 146:f64d43ff0c18 | 1264 | |
mbed_official | 146:f64d43ff0c18 | 1265 | /*! |
mbed_official | 146:f64d43ff0c18 | 1266 | * @name Register MCG_S, field LOLS0[7] (W1C) |
mbed_official | 146:f64d43ff0c18 | 1267 | * |
mbed_official | 146:f64d43ff0c18 | 1268 | * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set |
mbed_official | 146:f64d43ff0c18 | 1269 | * if after acquiring lock, the PLL output frequency has fallen outside the lock |
mbed_official | 146:f64d43ff0c18 | 1270 | * exit frequency tolerance, D unl . LOLIE determines whether an interrupt |
mbed_official | 146:f64d43ff0c18 | 1271 | * request is made when LOLS is set. LOLRE determines whether a reset request is made |
mbed_official | 146:f64d43ff0c18 | 1272 | * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it |
mbed_official | 146:f64d43ff0c18 | 1273 | * when set. Writing a logic 0 to this bit has no effect. |
mbed_official | 146:f64d43ff0c18 | 1274 | * |
mbed_official | 146:f64d43ff0c18 | 1275 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1276 | * - 0 - PLL has not lost lock since LOLS 0 was last cleared. |
mbed_official | 146:f64d43ff0c18 | 1277 | * - 1 - PLL has lost lock since LOLS 0 was last cleared. |
mbed_official | 146:f64d43ff0c18 | 1278 | */ |
mbed_official | 146:f64d43ff0c18 | 1279 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1280 | #define BP_MCG_S_LOLS0 (7U) //!< Bit position for MCG_S_LOLS0. |
mbed_official | 146:f64d43ff0c18 | 1281 | #define BM_MCG_S_LOLS0 (0x80U) //!< Bit mask for MCG_S_LOLS0. |
mbed_official | 146:f64d43ff0c18 | 1282 | #define BS_MCG_S_LOLS0 (1U) //!< Bit field size in bits for MCG_S_LOLS0. |
mbed_official | 146:f64d43ff0c18 | 1283 | |
mbed_official | 146:f64d43ff0c18 | 1284 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1285 | //! @brief Read current value of the MCG_S_LOLS0 field. |
mbed_official | 146:f64d43ff0c18 | 1286 | #define BR_MCG_S_LOLS0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0)) |
mbed_official | 146:f64d43ff0c18 | 1287 | #endif |
mbed_official | 146:f64d43ff0c18 | 1288 | |
mbed_official | 146:f64d43ff0c18 | 1289 | //! @brief Format value for bitfield MCG_S_LOLS0. |
mbed_official | 146:f64d43ff0c18 | 1290 | #define BF_MCG_S_LOLS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_S_LOLS0), uint8_t) & BM_MCG_S_LOLS0) |
mbed_official | 146:f64d43ff0c18 | 1291 | |
mbed_official | 146:f64d43ff0c18 | 1292 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1293 | //! @brief Set the LOLS0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1294 | #define BW_MCG_S_LOLS0(v) (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1295 | #endif |
mbed_official | 146:f64d43ff0c18 | 1296 | //@} |
mbed_official | 146:f64d43ff0c18 | 1297 | |
mbed_official | 146:f64d43ff0c18 | 1298 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1299 | // HW_MCG_SC - MCG Status and Control Register |
mbed_official | 146:f64d43ff0c18 | 1300 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1301 | |
mbed_official | 146:f64d43ff0c18 | 1302 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1303 | /*! |
mbed_official | 146:f64d43ff0c18 | 1304 | * @brief HW_MCG_SC - MCG Status and Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1305 | * |
mbed_official | 146:f64d43ff0c18 | 1306 | * Reset value: 0x02U |
mbed_official | 146:f64d43ff0c18 | 1307 | */ |
mbed_official | 146:f64d43ff0c18 | 1308 | typedef union _hw_mcg_sc |
mbed_official | 146:f64d43ff0c18 | 1309 | { |
mbed_official | 146:f64d43ff0c18 | 1310 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1311 | struct _hw_mcg_sc_bitfields |
mbed_official | 146:f64d43ff0c18 | 1312 | { |
mbed_official | 146:f64d43ff0c18 | 1313 | uint8_t LOCS0 : 1; //!< [0] OSC0 Loss of Clock Status |
mbed_official | 146:f64d43ff0c18 | 1314 | uint8_t FCRDIV : 3; //!< [3:1] Fast Clock Internal Reference Divider |
mbed_official | 146:f64d43ff0c18 | 1315 | uint8_t FLTPRSRV : 1; //!< [4] FLL Filter Preserve Enable |
mbed_official | 146:f64d43ff0c18 | 1316 | uint8_t ATMF : 1; //!< [5] Automatic Trim Machine Fail Flag |
mbed_official | 146:f64d43ff0c18 | 1317 | uint8_t ATMS : 1; //!< [6] Automatic Trim Machine Select |
mbed_official | 146:f64d43ff0c18 | 1318 | uint8_t ATME : 1; //!< [7] Automatic Trim Machine Enable |
mbed_official | 146:f64d43ff0c18 | 1319 | } B; |
mbed_official | 146:f64d43ff0c18 | 1320 | } hw_mcg_sc_t; |
mbed_official | 146:f64d43ff0c18 | 1321 | #endif |
mbed_official | 146:f64d43ff0c18 | 1322 | |
mbed_official | 146:f64d43ff0c18 | 1323 | /*! |
mbed_official | 146:f64d43ff0c18 | 1324 | * @name Constants and macros for entire MCG_SC register |
mbed_official | 146:f64d43ff0c18 | 1325 | */ |
mbed_official | 146:f64d43ff0c18 | 1326 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1327 | #define HW_MCG_SC_ADDR (REGS_MCG_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 1328 | |
mbed_official | 146:f64d43ff0c18 | 1329 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1330 | #define HW_MCG_SC (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1331 | #define HW_MCG_SC_RD() (HW_MCG_SC.U) |
mbed_official | 146:f64d43ff0c18 | 1332 | #define HW_MCG_SC_WR(v) (HW_MCG_SC.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1333 | #define HW_MCG_SC_SET(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1334 | #define HW_MCG_SC_CLR(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1335 | #define HW_MCG_SC_TOG(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1336 | #endif |
mbed_official | 146:f64d43ff0c18 | 1337 | //@} |
mbed_official | 146:f64d43ff0c18 | 1338 | |
mbed_official | 146:f64d43ff0c18 | 1339 | /* |
mbed_official | 146:f64d43ff0c18 | 1340 | * Constants & macros for individual MCG_SC bitfields |
mbed_official | 146:f64d43ff0c18 | 1341 | */ |
mbed_official | 146:f64d43ff0c18 | 1342 | |
mbed_official | 146:f64d43ff0c18 | 1343 | /*! |
mbed_official | 146:f64d43ff0c18 | 1344 | * @name Register MCG_SC, field LOCS0[0] (W1C) |
mbed_official | 146:f64d43ff0c18 | 1345 | * |
mbed_official | 146:f64d43ff0c18 | 1346 | * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The |
mbed_official | 146:f64d43ff0c18 | 1347 | * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a |
mbed_official | 146:f64d43ff0c18 | 1348 | * logic 1 to it when set. |
mbed_official | 146:f64d43ff0c18 | 1349 | * |
mbed_official | 146:f64d43ff0c18 | 1350 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1351 | * - 0 - Loss of OSC0 has not occurred. |
mbed_official | 146:f64d43ff0c18 | 1352 | * - 1 - Loss of OSC0 has occurred. |
mbed_official | 146:f64d43ff0c18 | 1353 | */ |
mbed_official | 146:f64d43ff0c18 | 1354 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1355 | #define BP_MCG_SC_LOCS0 (0U) //!< Bit position for MCG_SC_LOCS0. |
mbed_official | 146:f64d43ff0c18 | 1356 | #define BM_MCG_SC_LOCS0 (0x01U) //!< Bit mask for MCG_SC_LOCS0. |
mbed_official | 146:f64d43ff0c18 | 1357 | #define BS_MCG_SC_LOCS0 (1U) //!< Bit field size in bits for MCG_SC_LOCS0. |
mbed_official | 146:f64d43ff0c18 | 1358 | |
mbed_official | 146:f64d43ff0c18 | 1359 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1360 | //! @brief Read current value of the MCG_SC_LOCS0 field. |
mbed_official | 146:f64d43ff0c18 | 1361 | #define BR_MCG_SC_LOCS0 (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0)) |
mbed_official | 146:f64d43ff0c18 | 1362 | #endif |
mbed_official | 146:f64d43ff0c18 | 1363 | |
mbed_official | 146:f64d43ff0c18 | 1364 | //! @brief Format value for bitfield MCG_SC_LOCS0. |
mbed_official | 146:f64d43ff0c18 | 1365 | #define BF_MCG_SC_LOCS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_LOCS0), uint8_t) & BM_MCG_SC_LOCS0) |
mbed_official | 146:f64d43ff0c18 | 1366 | |
mbed_official | 146:f64d43ff0c18 | 1367 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1368 | //! @brief Set the LOCS0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1369 | #define BW_MCG_SC_LOCS0(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1370 | #endif |
mbed_official | 146:f64d43ff0c18 | 1371 | //@} |
mbed_official | 146:f64d43ff0c18 | 1372 | |
mbed_official | 146:f64d43ff0c18 | 1373 | /*! |
mbed_official | 146:f64d43ff0c18 | 1374 | * @name Register MCG_SC, field FCRDIV[3:1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1375 | * |
mbed_official | 146:f64d43ff0c18 | 1376 | * Selects the amount to divide down the fast internal reference clock. The |
mbed_official | 146:f64d43ff0c18 | 1377 | * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the |
mbed_official | 146:f64d43ff0c18 | 1378 | * divider when the Fast IRC is enabled is not supported). |
mbed_official | 146:f64d43ff0c18 | 1379 | * |
mbed_official | 146:f64d43ff0c18 | 1380 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1381 | * - 000 - Divide Factor is 1 |
mbed_official | 146:f64d43ff0c18 | 1382 | * - 001 - Divide Factor is 2. |
mbed_official | 146:f64d43ff0c18 | 1383 | * - 010 - Divide Factor is 4. |
mbed_official | 146:f64d43ff0c18 | 1384 | * - 011 - Divide Factor is 8. |
mbed_official | 146:f64d43ff0c18 | 1385 | * - 100 - Divide Factor is 16 |
mbed_official | 146:f64d43ff0c18 | 1386 | * - 101 - Divide Factor is 32 |
mbed_official | 146:f64d43ff0c18 | 1387 | * - 110 - Divide Factor is 64 |
mbed_official | 146:f64d43ff0c18 | 1388 | * - 111 - Divide Factor is 128. |
mbed_official | 146:f64d43ff0c18 | 1389 | */ |
mbed_official | 146:f64d43ff0c18 | 1390 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1391 | #define BP_MCG_SC_FCRDIV (1U) //!< Bit position for MCG_SC_FCRDIV. |
mbed_official | 146:f64d43ff0c18 | 1392 | #define BM_MCG_SC_FCRDIV (0x0EU) //!< Bit mask for MCG_SC_FCRDIV. |
mbed_official | 146:f64d43ff0c18 | 1393 | #define BS_MCG_SC_FCRDIV (3U) //!< Bit field size in bits for MCG_SC_FCRDIV. |
mbed_official | 146:f64d43ff0c18 | 1394 | |
mbed_official | 146:f64d43ff0c18 | 1395 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1396 | //! @brief Read current value of the MCG_SC_FCRDIV field. |
mbed_official | 146:f64d43ff0c18 | 1397 | #define BR_MCG_SC_FCRDIV (HW_MCG_SC.B.FCRDIV) |
mbed_official | 146:f64d43ff0c18 | 1398 | #endif |
mbed_official | 146:f64d43ff0c18 | 1399 | |
mbed_official | 146:f64d43ff0c18 | 1400 | //! @brief Format value for bitfield MCG_SC_FCRDIV. |
mbed_official | 146:f64d43ff0c18 | 1401 | #define BF_MCG_SC_FCRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FCRDIV), uint8_t) & BM_MCG_SC_FCRDIV) |
mbed_official | 146:f64d43ff0c18 | 1402 | |
mbed_official | 146:f64d43ff0c18 | 1403 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1404 | //! @brief Set the FCRDIV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1405 | #define BW_MCG_SC_FCRDIV(v) (HW_MCG_SC_WR((HW_MCG_SC_RD() & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v))) |
mbed_official | 146:f64d43ff0c18 | 1406 | #endif |
mbed_official | 146:f64d43ff0c18 | 1407 | //@} |
mbed_official | 146:f64d43ff0c18 | 1408 | |
mbed_official | 146:f64d43ff0c18 | 1409 | /*! |
mbed_official | 146:f64d43ff0c18 | 1410 | * @name Register MCG_SC, field FLTPRSRV[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1411 | * |
mbed_official | 146:f64d43ff0c18 | 1412 | * This bit will prevent the FLL filter values from resetting allowing the FLL |
mbed_official | 146:f64d43ff0c18 | 1413 | * output frequency to remain the same during clock mode changes where the FLL/DCO |
mbed_official | 146:f64d43ff0c18 | 1414 | * output is still valid. (Note: This requires that the FLL reference frequency |
mbed_official | 146:f64d43ff0c18 | 1415 | * to remain the same as what it was prior to the new clock mode switch. |
mbed_official | 146:f64d43ff0c18 | 1416 | * Otherwise FLL filter and frequency values will change.) |
mbed_official | 146:f64d43ff0c18 | 1417 | * |
mbed_official | 146:f64d43ff0c18 | 1418 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1419 | * - 0 - FLL filter and FLL frequency will reset on changes to currect clock |
mbed_official | 146:f64d43ff0c18 | 1420 | * mode. |
mbed_official | 146:f64d43ff0c18 | 1421 | * - 1 - Fll filter and FLL frequency retain their previous values during new |
mbed_official | 146:f64d43ff0c18 | 1422 | * clock mode change. |
mbed_official | 146:f64d43ff0c18 | 1423 | */ |
mbed_official | 146:f64d43ff0c18 | 1424 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1425 | #define BP_MCG_SC_FLTPRSRV (4U) //!< Bit position for MCG_SC_FLTPRSRV. |
mbed_official | 146:f64d43ff0c18 | 1426 | #define BM_MCG_SC_FLTPRSRV (0x10U) //!< Bit mask for MCG_SC_FLTPRSRV. |
mbed_official | 146:f64d43ff0c18 | 1427 | #define BS_MCG_SC_FLTPRSRV (1U) //!< Bit field size in bits for MCG_SC_FLTPRSRV. |
mbed_official | 146:f64d43ff0c18 | 1428 | |
mbed_official | 146:f64d43ff0c18 | 1429 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1430 | //! @brief Read current value of the MCG_SC_FLTPRSRV field. |
mbed_official | 146:f64d43ff0c18 | 1431 | #define BR_MCG_SC_FLTPRSRV (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV)) |
mbed_official | 146:f64d43ff0c18 | 1432 | #endif |
mbed_official | 146:f64d43ff0c18 | 1433 | |
mbed_official | 146:f64d43ff0c18 | 1434 | //! @brief Format value for bitfield MCG_SC_FLTPRSRV. |
mbed_official | 146:f64d43ff0c18 | 1435 | #define BF_MCG_SC_FLTPRSRV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FLTPRSRV), uint8_t) & BM_MCG_SC_FLTPRSRV) |
mbed_official | 146:f64d43ff0c18 | 1436 | |
mbed_official | 146:f64d43ff0c18 | 1437 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1438 | //! @brief Set the FLTPRSRV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1439 | #define BW_MCG_SC_FLTPRSRV(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1440 | #endif |
mbed_official | 146:f64d43ff0c18 | 1441 | //@} |
mbed_official | 146:f64d43ff0c18 | 1442 | |
mbed_official | 146:f64d43ff0c18 | 1443 | /*! |
mbed_official | 146:f64d43ff0c18 | 1444 | * @name Register MCG_SC, field ATMF[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1445 | * |
mbed_official | 146:f64d43ff0c18 | 1446 | * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the |
mbed_official | 146:f64d43ff0c18 | 1447 | * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC |
mbed_official | 146:f64d43ff0c18 | 1448 | * registers is detected or the MCG enters into any Stop mode. A write to ATMF |
mbed_official | 146:f64d43ff0c18 | 1449 | * clears the flag. |
mbed_official | 146:f64d43ff0c18 | 1450 | * |
mbed_official | 146:f64d43ff0c18 | 1451 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1452 | * - 0 - Automatic Trim Machine completed normally. |
mbed_official | 146:f64d43ff0c18 | 1453 | * - 1 - Automatic Trim Machine failed. |
mbed_official | 146:f64d43ff0c18 | 1454 | */ |
mbed_official | 146:f64d43ff0c18 | 1455 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1456 | #define BP_MCG_SC_ATMF (5U) //!< Bit position for MCG_SC_ATMF. |
mbed_official | 146:f64d43ff0c18 | 1457 | #define BM_MCG_SC_ATMF (0x20U) //!< Bit mask for MCG_SC_ATMF. |
mbed_official | 146:f64d43ff0c18 | 1458 | #define BS_MCG_SC_ATMF (1U) //!< Bit field size in bits for MCG_SC_ATMF. |
mbed_official | 146:f64d43ff0c18 | 1459 | |
mbed_official | 146:f64d43ff0c18 | 1460 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1461 | //! @brief Read current value of the MCG_SC_ATMF field. |
mbed_official | 146:f64d43ff0c18 | 1462 | #define BR_MCG_SC_ATMF (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF)) |
mbed_official | 146:f64d43ff0c18 | 1463 | #endif |
mbed_official | 146:f64d43ff0c18 | 1464 | |
mbed_official | 146:f64d43ff0c18 | 1465 | //! @brief Format value for bitfield MCG_SC_ATMF. |
mbed_official | 146:f64d43ff0c18 | 1466 | #define BF_MCG_SC_ATMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMF), uint8_t) & BM_MCG_SC_ATMF) |
mbed_official | 146:f64d43ff0c18 | 1467 | |
mbed_official | 146:f64d43ff0c18 | 1468 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1469 | //! @brief Set the ATMF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1470 | #define BW_MCG_SC_ATMF(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1471 | #endif |
mbed_official | 146:f64d43ff0c18 | 1472 | //@} |
mbed_official | 146:f64d43ff0c18 | 1473 | |
mbed_official | 146:f64d43ff0c18 | 1474 | /*! |
mbed_official | 146:f64d43ff0c18 | 1475 | * @name Register MCG_SC, field ATMS[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1476 | * |
mbed_official | 146:f64d43ff0c18 | 1477 | * Selects the IRCS clock for Auto Trim Test. |
mbed_official | 146:f64d43ff0c18 | 1478 | * |
mbed_official | 146:f64d43ff0c18 | 1479 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1480 | * - 0 - 32 kHz Internal Reference Clock selected. |
mbed_official | 146:f64d43ff0c18 | 1481 | * - 1 - 4 MHz Internal Reference Clock selected. |
mbed_official | 146:f64d43ff0c18 | 1482 | */ |
mbed_official | 146:f64d43ff0c18 | 1483 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1484 | #define BP_MCG_SC_ATMS (6U) //!< Bit position for MCG_SC_ATMS. |
mbed_official | 146:f64d43ff0c18 | 1485 | #define BM_MCG_SC_ATMS (0x40U) //!< Bit mask for MCG_SC_ATMS. |
mbed_official | 146:f64d43ff0c18 | 1486 | #define BS_MCG_SC_ATMS (1U) //!< Bit field size in bits for MCG_SC_ATMS. |
mbed_official | 146:f64d43ff0c18 | 1487 | |
mbed_official | 146:f64d43ff0c18 | 1488 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1489 | //! @brief Read current value of the MCG_SC_ATMS field. |
mbed_official | 146:f64d43ff0c18 | 1490 | #define BR_MCG_SC_ATMS (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS)) |
mbed_official | 146:f64d43ff0c18 | 1491 | #endif |
mbed_official | 146:f64d43ff0c18 | 1492 | |
mbed_official | 146:f64d43ff0c18 | 1493 | //! @brief Format value for bitfield MCG_SC_ATMS. |
mbed_official | 146:f64d43ff0c18 | 1494 | #define BF_MCG_SC_ATMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMS), uint8_t) & BM_MCG_SC_ATMS) |
mbed_official | 146:f64d43ff0c18 | 1495 | |
mbed_official | 146:f64d43ff0c18 | 1496 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1497 | //! @brief Set the ATMS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1498 | #define BW_MCG_SC_ATMS(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1499 | #endif |
mbed_official | 146:f64d43ff0c18 | 1500 | //@} |
mbed_official | 146:f64d43ff0c18 | 1501 | |
mbed_official | 146:f64d43ff0c18 | 1502 | /*! |
mbed_official | 146:f64d43ff0c18 | 1503 | * @name Register MCG_SC, field ATME[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1504 | * |
mbed_official | 146:f64d43ff0c18 | 1505 | * Enables the Auto Trim Machine to start automatically trimming the selected |
mbed_official | 146:f64d43ff0c18 | 1506 | * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has |
mbed_official | 146:f64d43ff0c18 | 1507 | * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing |
mbed_official | 146:f64d43ff0c18 | 1508 | * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim |
mbed_official | 146:f64d43ff0c18 | 1509 | * operation and clears this bit. |
mbed_official | 146:f64d43ff0c18 | 1510 | * |
mbed_official | 146:f64d43ff0c18 | 1511 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1512 | * - 0 - Auto Trim Machine disabled. |
mbed_official | 146:f64d43ff0c18 | 1513 | * - 1 - Auto Trim Machine enabled. |
mbed_official | 146:f64d43ff0c18 | 1514 | */ |
mbed_official | 146:f64d43ff0c18 | 1515 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1516 | #define BP_MCG_SC_ATME (7U) //!< Bit position for MCG_SC_ATME. |
mbed_official | 146:f64d43ff0c18 | 1517 | #define BM_MCG_SC_ATME (0x80U) //!< Bit mask for MCG_SC_ATME. |
mbed_official | 146:f64d43ff0c18 | 1518 | #define BS_MCG_SC_ATME (1U) //!< Bit field size in bits for MCG_SC_ATME. |
mbed_official | 146:f64d43ff0c18 | 1519 | |
mbed_official | 146:f64d43ff0c18 | 1520 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1521 | //! @brief Read current value of the MCG_SC_ATME field. |
mbed_official | 146:f64d43ff0c18 | 1522 | #define BR_MCG_SC_ATME (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME)) |
mbed_official | 146:f64d43ff0c18 | 1523 | #endif |
mbed_official | 146:f64d43ff0c18 | 1524 | |
mbed_official | 146:f64d43ff0c18 | 1525 | //! @brief Format value for bitfield MCG_SC_ATME. |
mbed_official | 146:f64d43ff0c18 | 1526 | #define BF_MCG_SC_ATME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATME), uint8_t) & BM_MCG_SC_ATME) |
mbed_official | 146:f64d43ff0c18 | 1527 | |
mbed_official | 146:f64d43ff0c18 | 1528 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1529 | //! @brief Set the ATME field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1530 | #define BW_MCG_SC_ATME(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1531 | #endif |
mbed_official | 146:f64d43ff0c18 | 1532 | //@} |
mbed_official | 146:f64d43ff0c18 | 1533 | |
mbed_official | 146:f64d43ff0c18 | 1534 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1535 | // HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register |
mbed_official | 146:f64d43ff0c18 | 1536 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1537 | |
mbed_official | 146:f64d43ff0c18 | 1538 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1539 | /*! |
mbed_official | 146:f64d43ff0c18 | 1540 | * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1541 | * |
mbed_official | 146:f64d43ff0c18 | 1542 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1543 | */ |
mbed_official | 146:f64d43ff0c18 | 1544 | typedef union _hw_mcg_atcvh |
mbed_official | 146:f64d43ff0c18 | 1545 | { |
mbed_official | 146:f64d43ff0c18 | 1546 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1547 | struct _hw_mcg_atcvh_bitfields |
mbed_official | 146:f64d43ff0c18 | 1548 | { |
mbed_official | 146:f64d43ff0c18 | 1549 | uint8_t ATCVH : 8; //!< [7:0] ATM Compare Value High |
mbed_official | 146:f64d43ff0c18 | 1550 | } B; |
mbed_official | 146:f64d43ff0c18 | 1551 | } hw_mcg_atcvh_t; |
mbed_official | 146:f64d43ff0c18 | 1552 | #endif |
mbed_official | 146:f64d43ff0c18 | 1553 | |
mbed_official | 146:f64d43ff0c18 | 1554 | /*! |
mbed_official | 146:f64d43ff0c18 | 1555 | * @name Constants and macros for entire MCG_ATCVH register |
mbed_official | 146:f64d43ff0c18 | 1556 | */ |
mbed_official | 146:f64d43ff0c18 | 1557 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1558 | #define HW_MCG_ATCVH_ADDR (REGS_MCG_BASE + 0xAU) |
mbed_official | 146:f64d43ff0c18 | 1559 | |
mbed_official | 146:f64d43ff0c18 | 1560 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1561 | #define HW_MCG_ATCVH (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1562 | #define HW_MCG_ATCVH_RD() (HW_MCG_ATCVH.U) |
mbed_official | 146:f64d43ff0c18 | 1563 | #define HW_MCG_ATCVH_WR(v) (HW_MCG_ATCVH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1564 | #define HW_MCG_ATCVH_SET(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1565 | #define HW_MCG_ATCVH_CLR(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1566 | #define HW_MCG_ATCVH_TOG(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1567 | #endif |
mbed_official | 146:f64d43ff0c18 | 1568 | //@} |
mbed_official | 146:f64d43ff0c18 | 1569 | |
mbed_official | 146:f64d43ff0c18 | 1570 | /* |
mbed_official | 146:f64d43ff0c18 | 1571 | * Constants & macros for individual MCG_ATCVH bitfields |
mbed_official | 146:f64d43ff0c18 | 1572 | */ |
mbed_official | 146:f64d43ff0c18 | 1573 | |
mbed_official | 146:f64d43ff0c18 | 1574 | /*! |
mbed_official | 146:f64d43ff0c18 | 1575 | * @name Register MCG_ATCVH, field ATCVH[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1576 | * |
mbed_official | 146:f64d43ff0c18 | 1577 | * Values are used by Auto Trim Machine to compare and adjust Internal Reference |
mbed_official | 146:f64d43ff0c18 | 1578 | * trim values during ATM SAR conversion. |
mbed_official | 146:f64d43ff0c18 | 1579 | */ |
mbed_official | 146:f64d43ff0c18 | 1580 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1581 | #define BP_MCG_ATCVH_ATCVH (0U) //!< Bit position for MCG_ATCVH_ATCVH. |
mbed_official | 146:f64d43ff0c18 | 1582 | #define BM_MCG_ATCVH_ATCVH (0xFFU) //!< Bit mask for MCG_ATCVH_ATCVH. |
mbed_official | 146:f64d43ff0c18 | 1583 | #define BS_MCG_ATCVH_ATCVH (8U) //!< Bit field size in bits for MCG_ATCVH_ATCVH. |
mbed_official | 146:f64d43ff0c18 | 1584 | |
mbed_official | 146:f64d43ff0c18 | 1585 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1586 | //! @brief Read current value of the MCG_ATCVH_ATCVH field. |
mbed_official | 146:f64d43ff0c18 | 1587 | #define BR_MCG_ATCVH_ATCVH (HW_MCG_ATCVH.U) |
mbed_official | 146:f64d43ff0c18 | 1588 | #endif |
mbed_official | 146:f64d43ff0c18 | 1589 | |
mbed_official | 146:f64d43ff0c18 | 1590 | //! @brief Format value for bitfield MCG_ATCVH_ATCVH. |
mbed_official | 146:f64d43ff0c18 | 1591 | #define BF_MCG_ATCVH_ATCVH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVH_ATCVH), uint8_t) & BM_MCG_ATCVH_ATCVH) |
mbed_official | 146:f64d43ff0c18 | 1592 | |
mbed_official | 146:f64d43ff0c18 | 1593 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1594 | //! @brief Set the ATCVH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1595 | #define BW_MCG_ATCVH_ATCVH(v) (HW_MCG_ATCVH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1596 | #endif |
mbed_official | 146:f64d43ff0c18 | 1597 | //@} |
mbed_official | 146:f64d43ff0c18 | 1598 | |
mbed_official | 146:f64d43ff0c18 | 1599 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1600 | // HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register |
mbed_official | 146:f64d43ff0c18 | 1601 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1602 | |
mbed_official | 146:f64d43ff0c18 | 1603 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1604 | /*! |
mbed_official | 146:f64d43ff0c18 | 1605 | * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1606 | * |
mbed_official | 146:f64d43ff0c18 | 1607 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1608 | */ |
mbed_official | 146:f64d43ff0c18 | 1609 | typedef union _hw_mcg_atcvl |
mbed_official | 146:f64d43ff0c18 | 1610 | { |
mbed_official | 146:f64d43ff0c18 | 1611 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1612 | struct _hw_mcg_atcvl_bitfields |
mbed_official | 146:f64d43ff0c18 | 1613 | { |
mbed_official | 146:f64d43ff0c18 | 1614 | uint8_t ATCVL : 8; //!< [7:0] ATM Compare Value Low |
mbed_official | 146:f64d43ff0c18 | 1615 | } B; |
mbed_official | 146:f64d43ff0c18 | 1616 | } hw_mcg_atcvl_t; |
mbed_official | 146:f64d43ff0c18 | 1617 | #endif |
mbed_official | 146:f64d43ff0c18 | 1618 | |
mbed_official | 146:f64d43ff0c18 | 1619 | /*! |
mbed_official | 146:f64d43ff0c18 | 1620 | * @name Constants and macros for entire MCG_ATCVL register |
mbed_official | 146:f64d43ff0c18 | 1621 | */ |
mbed_official | 146:f64d43ff0c18 | 1622 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1623 | #define HW_MCG_ATCVL_ADDR (REGS_MCG_BASE + 0xBU) |
mbed_official | 146:f64d43ff0c18 | 1624 | |
mbed_official | 146:f64d43ff0c18 | 1625 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1626 | #define HW_MCG_ATCVL (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1627 | #define HW_MCG_ATCVL_RD() (HW_MCG_ATCVL.U) |
mbed_official | 146:f64d43ff0c18 | 1628 | #define HW_MCG_ATCVL_WR(v) (HW_MCG_ATCVL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1629 | #define HW_MCG_ATCVL_SET(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1630 | #define HW_MCG_ATCVL_CLR(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1631 | #define HW_MCG_ATCVL_TOG(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1632 | #endif |
mbed_official | 146:f64d43ff0c18 | 1633 | //@} |
mbed_official | 146:f64d43ff0c18 | 1634 | |
mbed_official | 146:f64d43ff0c18 | 1635 | /* |
mbed_official | 146:f64d43ff0c18 | 1636 | * Constants & macros for individual MCG_ATCVL bitfields |
mbed_official | 146:f64d43ff0c18 | 1637 | */ |
mbed_official | 146:f64d43ff0c18 | 1638 | |
mbed_official | 146:f64d43ff0c18 | 1639 | /*! |
mbed_official | 146:f64d43ff0c18 | 1640 | * @name Register MCG_ATCVL, field ATCVL[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1641 | * |
mbed_official | 146:f64d43ff0c18 | 1642 | * Values are used by Auto Trim Machine to compare and adjust Internal Reference |
mbed_official | 146:f64d43ff0c18 | 1643 | * trim values during ATM SAR conversion. |
mbed_official | 146:f64d43ff0c18 | 1644 | */ |
mbed_official | 146:f64d43ff0c18 | 1645 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1646 | #define BP_MCG_ATCVL_ATCVL (0U) //!< Bit position for MCG_ATCVL_ATCVL. |
mbed_official | 146:f64d43ff0c18 | 1647 | #define BM_MCG_ATCVL_ATCVL (0xFFU) //!< Bit mask for MCG_ATCVL_ATCVL. |
mbed_official | 146:f64d43ff0c18 | 1648 | #define BS_MCG_ATCVL_ATCVL (8U) //!< Bit field size in bits for MCG_ATCVL_ATCVL. |
mbed_official | 146:f64d43ff0c18 | 1649 | |
mbed_official | 146:f64d43ff0c18 | 1650 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1651 | //! @brief Read current value of the MCG_ATCVL_ATCVL field. |
mbed_official | 146:f64d43ff0c18 | 1652 | #define BR_MCG_ATCVL_ATCVL (HW_MCG_ATCVL.U) |
mbed_official | 146:f64d43ff0c18 | 1653 | #endif |
mbed_official | 146:f64d43ff0c18 | 1654 | |
mbed_official | 146:f64d43ff0c18 | 1655 | //! @brief Format value for bitfield MCG_ATCVL_ATCVL. |
mbed_official | 146:f64d43ff0c18 | 1656 | #define BF_MCG_ATCVL_ATCVL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVL_ATCVL), uint8_t) & BM_MCG_ATCVL_ATCVL) |
mbed_official | 146:f64d43ff0c18 | 1657 | |
mbed_official | 146:f64d43ff0c18 | 1658 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1659 | //! @brief Set the ATCVL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1660 | #define BW_MCG_ATCVL_ATCVL(v) (HW_MCG_ATCVL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1661 | #endif |
mbed_official | 146:f64d43ff0c18 | 1662 | //@} |
mbed_official | 146:f64d43ff0c18 | 1663 | |
mbed_official | 146:f64d43ff0c18 | 1664 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1665 | // HW_MCG_C7 - MCG Control 7 Register |
mbed_official | 146:f64d43ff0c18 | 1666 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1667 | |
mbed_official | 146:f64d43ff0c18 | 1668 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1669 | /*! |
mbed_official | 146:f64d43ff0c18 | 1670 | * @brief HW_MCG_C7 - MCG Control 7 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1671 | * |
mbed_official | 146:f64d43ff0c18 | 1672 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1673 | */ |
mbed_official | 146:f64d43ff0c18 | 1674 | typedef union _hw_mcg_c7 |
mbed_official | 146:f64d43ff0c18 | 1675 | { |
mbed_official | 146:f64d43ff0c18 | 1676 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1677 | struct _hw_mcg_c7_bitfields |
mbed_official | 146:f64d43ff0c18 | 1678 | { |
mbed_official | 146:f64d43ff0c18 | 1679 | uint8_t OSCSEL : 2; //!< [1:0] MCG OSC Clock Select |
mbed_official | 146:f64d43ff0c18 | 1680 | uint8_t RESERVED0 : 6; //!< [7:2] |
mbed_official | 146:f64d43ff0c18 | 1681 | } B; |
mbed_official | 146:f64d43ff0c18 | 1682 | } hw_mcg_c7_t; |
mbed_official | 146:f64d43ff0c18 | 1683 | #endif |
mbed_official | 146:f64d43ff0c18 | 1684 | |
mbed_official | 146:f64d43ff0c18 | 1685 | /*! |
mbed_official | 146:f64d43ff0c18 | 1686 | * @name Constants and macros for entire MCG_C7 register |
mbed_official | 146:f64d43ff0c18 | 1687 | */ |
mbed_official | 146:f64d43ff0c18 | 1688 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1689 | #define HW_MCG_C7_ADDR (REGS_MCG_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 1690 | |
mbed_official | 146:f64d43ff0c18 | 1691 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1692 | #define HW_MCG_C7 (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1693 | #define HW_MCG_C7_RD() (HW_MCG_C7.U) |
mbed_official | 146:f64d43ff0c18 | 1694 | #define HW_MCG_C7_WR(v) (HW_MCG_C7.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1695 | #define HW_MCG_C7_SET(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1696 | #define HW_MCG_C7_CLR(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1697 | #define HW_MCG_C7_TOG(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1698 | #endif |
mbed_official | 146:f64d43ff0c18 | 1699 | //@} |
mbed_official | 146:f64d43ff0c18 | 1700 | |
mbed_official | 146:f64d43ff0c18 | 1701 | /* |
mbed_official | 146:f64d43ff0c18 | 1702 | * Constants & macros for individual MCG_C7 bitfields |
mbed_official | 146:f64d43ff0c18 | 1703 | */ |
mbed_official | 146:f64d43ff0c18 | 1704 | |
mbed_official | 146:f64d43ff0c18 | 1705 | /*! |
mbed_official | 146:f64d43ff0c18 | 1706 | * @name Register MCG_C7, field OSCSEL[1:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1707 | * |
mbed_official | 146:f64d43ff0c18 | 1708 | * Selects the MCG FLL external reference clock |
mbed_official | 146:f64d43ff0c18 | 1709 | * |
mbed_official | 146:f64d43ff0c18 | 1710 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1711 | * - 00 - Selects Oscillator (OSCCLK0). |
mbed_official | 146:f64d43ff0c18 | 1712 | * - 01 - Selects 32 kHz RTC Oscillator. |
mbed_official | 146:f64d43ff0c18 | 1713 | * - 10 - Selects Oscillator (OSCCLK1). |
mbed_official | 146:f64d43ff0c18 | 1714 | * - 11 - RESERVED |
mbed_official | 146:f64d43ff0c18 | 1715 | */ |
mbed_official | 146:f64d43ff0c18 | 1716 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1717 | #define BP_MCG_C7_OSCSEL (0U) //!< Bit position for MCG_C7_OSCSEL. |
mbed_official | 146:f64d43ff0c18 | 1718 | #define BM_MCG_C7_OSCSEL (0x03U) //!< Bit mask for MCG_C7_OSCSEL. |
mbed_official | 146:f64d43ff0c18 | 1719 | #define BS_MCG_C7_OSCSEL (2U) //!< Bit field size in bits for MCG_C7_OSCSEL. |
mbed_official | 146:f64d43ff0c18 | 1720 | |
mbed_official | 146:f64d43ff0c18 | 1721 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1722 | //! @brief Read current value of the MCG_C7_OSCSEL field. |
mbed_official | 146:f64d43ff0c18 | 1723 | #define BR_MCG_C7_OSCSEL (HW_MCG_C7.B.OSCSEL) |
mbed_official | 146:f64d43ff0c18 | 1724 | #endif |
mbed_official | 146:f64d43ff0c18 | 1725 | |
mbed_official | 146:f64d43ff0c18 | 1726 | //! @brief Format value for bitfield MCG_C7_OSCSEL. |
mbed_official | 146:f64d43ff0c18 | 1727 | #define BF_MCG_C7_OSCSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C7_OSCSEL), uint8_t) & BM_MCG_C7_OSCSEL) |
mbed_official | 146:f64d43ff0c18 | 1728 | |
mbed_official | 146:f64d43ff0c18 | 1729 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1730 | //! @brief Set the OSCSEL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1731 | #define BW_MCG_C7_OSCSEL(v) (HW_MCG_C7_WR((HW_MCG_C7_RD() & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v))) |
mbed_official | 146:f64d43ff0c18 | 1732 | #endif |
mbed_official | 146:f64d43ff0c18 | 1733 | //@} |
mbed_official | 146:f64d43ff0c18 | 1734 | |
mbed_official | 146:f64d43ff0c18 | 1735 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1736 | // HW_MCG_C8 - MCG Control 8 Register |
mbed_official | 146:f64d43ff0c18 | 1737 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1738 | |
mbed_official | 146:f64d43ff0c18 | 1739 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1740 | /*! |
mbed_official | 146:f64d43ff0c18 | 1741 | * @brief HW_MCG_C8 - MCG Control 8 Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1742 | * |
mbed_official | 146:f64d43ff0c18 | 1743 | * Reset value: 0x80U |
mbed_official | 146:f64d43ff0c18 | 1744 | */ |
mbed_official | 146:f64d43ff0c18 | 1745 | typedef union _hw_mcg_c8 |
mbed_official | 146:f64d43ff0c18 | 1746 | { |
mbed_official | 146:f64d43ff0c18 | 1747 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1748 | struct _hw_mcg_c8_bitfields |
mbed_official | 146:f64d43ff0c18 | 1749 | { |
mbed_official | 146:f64d43ff0c18 | 1750 | uint8_t LOCS1 : 1; //!< [0] RTC Loss of Clock Status |
mbed_official | 146:f64d43ff0c18 | 1751 | uint8_t RESERVED0 : 4; //!< [4:1] |
mbed_official | 146:f64d43ff0c18 | 1752 | uint8_t CME1 : 1; //!< [5] Clock Monitor Enable1 |
mbed_official | 146:f64d43ff0c18 | 1753 | uint8_t LOLRE : 1; //!< [6] PLL Loss of Lock Reset Enable |
mbed_official | 146:f64d43ff0c18 | 1754 | uint8_t LOCRE1 : 1; //!< [7] Loss of Clock Reset Enable |
mbed_official | 146:f64d43ff0c18 | 1755 | } B; |
mbed_official | 146:f64d43ff0c18 | 1756 | } hw_mcg_c8_t; |
mbed_official | 146:f64d43ff0c18 | 1757 | #endif |
mbed_official | 146:f64d43ff0c18 | 1758 | |
mbed_official | 146:f64d43ff0c18 | 1759 | /*! |
mbed_official | 146:f64d43ff0c18 | 1760 | * @name Constants and macros for entire MCG_C8 register |
mbed_official | 146:f64d43ff0c18 | 1761 | */ |
mbed_official | 146:f64d43ff0c18 | 1762 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1763 | #define HW_MCG_C8_ADDR (REGS_MCG_BASE + 0xDU) |
mbed_official | 146:f64d43ff0c18 | 1764 | |
mbed_official | 146:f64d43ff0c18 | 1765 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1766 | #define HW_MCG_C8 (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1767 | #define HW_MCG_C8_RD() (HW_MCG_C8.U) |
mbed_official | 146:f64d43ff0c18 | 1768 | #define HW_MCG_C8_WR(v) (HW_MCG_C8.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1769 | #define HW_MCG_C8_SET(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1770 | #define HW_MCG_C8_CLR(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1771 | #define HW_MCG_C8_TOG(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1772 | #endif |
mbed_official | 146:f64d43ff0c18 | 1773 | //@} |
mbed_official | 146:f64d43ff0c18 | 1774 | |
mbed_official | 146:f64d43ff0c18 | 1775 | /* |
mbed_official | 146:f64d43ff0c18 | 1776 | * Constants & macros for individual MCG_C8 bitfields |
mbed_official | 146:f64d43ff0c18 | 1777 | */ |
mbed_official | 146:f64d43ff0c18 | 1778 | |
mbed_official | 146:f64d43ff0c18 | 1779 | /*! |
mbed_official | 146:f64d43ff0c18 | 1780 | * @name Register MCG_C8, field LOCS1[0] (W1C) |
mbed_official | 146:f64d43ff0c18 | 1781 | * |
mbed_official | 146:f64d43ff0c18 | 1782 | * This bit indicates when a loss of clock has occurred. This bit is cleared by |
mbed_official | 146:f64d43ff0c18 | 1783 | * writing a logic 1 to it when set. |
mbed_official | 146:f64d43ff0c18 | 1784 | * |
mbed_official | 146:f64d43ff0c18 | 1785 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1786 | * - 0 - Loss of RTC has not occur. |
mbed_official | 146:f64d43ff0c18 | 1787 | * - 1 - Loss of RTC has occur |
mbed_official | 146:f64d43ff0c18 | 1788 | */ |
mbed_official | 146:f64d43ff0c18 | 1789 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1790 | #define BP_MCG_C8_LOCS1 (0U) //!< Bit position for MCG_C8_LOCS1. |
mbed_official | 146:f64d43ff0c18 | 1791 | #define BM_MCG_C8_LOCS1 (0x01U) //!< Bit mask for MCG_C8_LOCS1. |
mbed_official | 146:f64d43ff0c18 | 1792 | #define BS_MCG_C8_LOCS1 (1U) //!< Bit field size in bits for MCG_C8_LOCS1. |
mbed_official | 146:f64d43ff0c18 | 1793 | |
mbed_official | 146:f64d43ff0c18 | 1794 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1795 | //! @brief Read current value of the MCG_C8_LOCS1 field. |
mbed_official | 146:f64d43ff0c18 | 1796 | #define BR_MCG_C8_LOCS1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1)) |
mbed_official | 146:f64d43ff0c18 | 1797 | #endif |
mbed_official | 146:f64d43ff0c18 | 1798 | |
mbed_official | 146:f64d43ff0c18 | 1799 | //! @brief Format value for bitfield MCG_C8_LOCS1. |
mbed_official | 146:f64d43ff0c18 | 1800 | #define BF_MCG_C8_LOCS1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCS1), uint8_t) & BM_MCG_C8_LOCS1) |
mbed_official | 146:f64d43ff0c18 | 1801 | |
mbed_official | 146:f64d43ff0c18 | 1802 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1803 | //! @brief Set the LOCS1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1804 | #define BW_MCG_C8_LOCS1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1805 | #endif |
mbed_official | 146:f64d43ff0c18 | 1806 | //@} |
mbed_official | 146:f64d43ff0c18 | 1807 | |
mbed_official | 146:f64d43ff0c18 | 1808 | /*! |
mbed_official | 146:f64d43ff0c18 | 1809 | * @name Register MCG_C8, field CME1[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1810 | * |
mbed_official | 146:f64d43ff0c18 | 1811 | * Enables the loss of clock monitoring circuit for the output of the RTC |
mbed_official | 146:f64d43ff0c18 | 1812 | * external reference clock. The LOCRE1 bit will determine whether an interrupt or a |
mbed_official | 146:f64d43ff0c18 | 1813 | * reset request is generated following a loss of RTC clock indication. The CME1 |
mbed_official | 146:f64d43ff0c18 | 1814 | * bit should be set to a logic 1 when the MCG is in an operational mode that uses |
mbed_official | 146:f64d43ff0c18 | 1815 | * the RTC as its external reference clock or if the RTC is operational. CME1 bit |
mbed_official | 146:f64d43ff0c18 | 1816 | * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a |
mbed_official | 146:f64d43ff0c18 | 1817 | * reset request may occur when in Stop mode. CME1 should also be set to a logic 0 |
mbed_official | 146:f64d43ff0c18 | 1818 | * before entering VLPR or VLPW power modes. |
mbed_official | 146:f64d43ff0c18 | 1819 | * |
mbed_official | 146:f64d43ff0c18 | 1820 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1821 | * - 0 - External clock monitor is disabled for RTC clock. |
mbed_official | 146:f64d43ff0c18 | 1822 | * - 1 - External clock monitor is enabled for RTC clock. |
mbed_official | 146:f64d43ff0c18 | 1823 | */ |
mbed_official | 146:f64d43ff0c18 | 1824 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1825 | #define BP_MCG_C8_CME1 (5U) //!< Bit position for MCG_C8_CME1. |
mbed_official | 146:f64d43ff0c18 | 1826 | #define BM_MCG_C8_CME1 (0x20U) //!< Bit mask for MCG_C8_CME1. |
mbed_official | 146:f64d43ff0c18 | 1827 | #define BS_MCG_C8_CME1 (1U) //!< Bit field size in bits for MCG_C8_CME1. |
mbed_official | 146:f64d43ff0c18 | 1828 | |
mbed_official | 146:f64d43ff0c18 | 1829 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1830 | //! @brief Read current value of the MCG_C8_CME1 field. |
mbed_official | 146:f64d43ff0c18 | 1831 | #define BR_MCG_C8_CME1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1)) |
mbed_official | 146:f64d43ff0c18 | 1832 | #endif |
mbed_official | 146:f64d43ff0c18 | 1833 | |
mbed_official | 146:f64d43ff0c18 | 1834 | //! @brief Format value for bitfield MCG_C8_CME1. |
mbed_official | 146:f64d43ff0c18 | 1835 | #define BF_MCG_C8_CME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_CME1), uint8_t) & BM_MCG_C8_CME1) |
mbed_official | 146:f64d43ff0c18 | 1836 | |
mbed_official | 146:f64d43ff0c18 | 1837 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1838 | //! @brief Set the CME1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1839 | #define BW_MCG_C8_CME1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1840 | #endif |
mbed_official | 146:f64d43ff0c18 | 1841 | //@} |
mbed_official | 146:f64d43ff0c18 | 1842 | |
mbed_official | 146:f64d43ff0c18 | 1843 | /*! |
mbed_official | 146:f64d43ff0c18 | 1844 | * @name Register MCG_C8, field LOLRE[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1845 | * |
mbed_official | 146:f64d43ff0c18 | 1846 | * Determines if an interrupt or a reset request is made following a PLL loss of |
mbed_official | 146:f64d43ff0c18 | 1847 | * lock. |
mbed_official | 146:f64d43ff0c18 | 1848 | * |
mbed_official | 146:f64d43ff0c18 | 1849 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1850 | * - 0 - Interrupt request is generated on a PLL loss of lock indication. The |
mbed_official | 146:f64d43ff0c18 | 1851 | * PLL loss of lock interrupt enable bit must also be set to generate the |
mbed_official | 146:f64d43ff0c18 | 1852 | * interrupt request. |
mbed_official | 146:f64d43ff0c18 | 1853 | * - 1 - Generate a reset request on a PLL loss of lock indication. |
mbed_official | 146:f64d43ff0c18 | 1854 | */ |
mbed_official | 146:f64d43ff0c18 | 1855 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1856 | #define BP_MCG_C8_LOLRE (6U) //!< Bit position for MCG_C8_LOLRE. |
mbed_official | 146:f64d43ff0c18 | 1857 | #define BM_MCG_C8_LOLRE (0x40U) //!< Bit mask for MCG_C8_LOLRE. |
mbed_official | 146:f64d43ff0c18 | 1858 | #define BS_MCG_C8_LOLRE (1U) //!< Bit field size in bits for MCG_C8_LOLRE. |
mbed_official | 146:f64d43ff0c18 | 1859 | |
mbed_official | 146:f64d43ff0c18 | 1860 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1861 | //! @brief Read current value of the MCG_C8_LOLRE field. |
mbed_official | 146:f64d43ff0c18 | 1862 | #define BR_MCG_C8_LOLRE (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE)) |
mbed_official | 146:f64d43ff0c18 | 1863 | #endif |
mbed_official | 146:f64d43ff0c18 | 1864 | |
mbed_official | 146:f64d43ff0c18 | 1865 | //! @brief Format value for bitfield MCG_C8_LOLRE. |
mbed_official | 146:f64d43ff0c18 | 1866 | #define BF_MCG_C8_LOLRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOLRE), uint8_t) & BM_MCG_C8_LOLRE) |
mbed_official | 146:f64d43ff0c18 | 1867 | |
mbed_official | 146:f64d43ff0c18 | 1868 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1869 | //! @brief Set the LOLRE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1870 | #define BW_MCG_C8_LOLRE(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1871 | #endif |
mbed_official | 146:f64d43ff0c18 | 1872 | //@} |
mbed_official | 146:f64d43ff0c18 | 1873 | |
mbed_official | 146:f64d43ff0c18 | 1874 | /*! |
mbed_official | 146:f64d43ff0c18 | 1875 | * @name Register MCG_C8, field LOCRE1[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 1876 | * |
mbed_official | 146:f64d43ff0c18 | 1877 | * Determines if a interrupt or a reset request is made following a loss of RTC |
mbed_official | 146:f64d43ff0c18 | 1878 | * external reference clock. The LOCRE1 only has an affect when CME1 is set. |
mbed_official | 146:f64d43ff0c18 | 1879 | * |
mbed_official | 146:f64d43ff0c18 | 1880 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1881 | * - 0 - Interrupt request is generated on a loss of RTC external reference |
mbed_official | 146:f64d43ff0c18 | 1882 | * clock. |
mbed_official | 146:f64d43ff0c18 | 1883 | * - 1 - Generate a reset request on a loss of RTC external reference clock |
mbed_official | 146:f64d43ff0c18 | 1884 | */ |
mbed_official | 146:f64d43ff0c18 | 1885 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1886 | #define BP_MCG_C8_LOCRE1 (7U) //!< Bit position for MCG_C8_LOCRE1. |
mbed_official | 146:f64d43ff0c18 | 1887 | #define BM_MCG_C8_LOCRE1 (0x80U) //!< Bit mask for MCG_C8_LOCRE1. |
mbed_official | 146:f64d43ff0c18 | 1888 | #define BS_MCG_C8_LOCRE1 (1U) //!< Bit field size in bits for MCG_C8_LOCRE1. |
mbed_official | 146:f64d43ff0c18 | 1889 | |
mbed_official | 146:f64d43ff0c18 | 1890 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1891 | //! @brief Read current value of the MCG_C8_LOCRE1 field. |
mbed_official | 146:f64d43ff0c18 | 1892 | #define BR_MCG_C8_LOCRE1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1)) |
mbed_official | 146:f64d43ff0c18 | 1893 | #endif |
mbed_official | 146:f64d43ff0c18 | 1894 | |
mbed_official | 146:f64d43ff0c18 | 1895 | //! @brief Format value for bitfield MCG_C8_LOCRE1. |
mbed_official | 146:f64d43ff0c18 | 1896 | #define BF_MCG_C8_LOCRE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCRE1), uint8_t) & BM_MCG_C8_LOCRE1) |
mbed_official | 146:f64d43ff0c18 | 1897 | |
mbed_official | 146:f64d43ff0c18 | 1898 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1899 | //! @brief Set the LOCRE1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1900 | #define BW_MCG_C8_LOCRE1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1901 | #endif |
mbed_official | 146:f64d43ff0c18 | 1902 | //@} |
mbed_official | 146:f64d43ff0c18 | 1903 | |
mbed_official | 146:f64d43ff0c18 | 1904 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1905 | // hw_mcg_t - module struct |
mbed_official | 146:f64d43ff0c18 | 1906 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1907 | /*! |
mbed_official | 146:f64d43ff0c18 | 1908 | * @brief All MCG module registers. |
mbed_official | 146:f64d43ff0c18 | 1909 | */ |
mbed_official | 146:f64d43ff0c18 | 1910 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1911 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 1912 | typedef struct _hw_mcg |
mbed_official | 146:f64d43ff0c18 | 1913 | { |
mbed_official | 146:f64d43ff0c18 | 1914 | __IO hw_mcg_c1_t C1; //!< [0x0] MCG Control 1 Register |
mbed_official | 146:f64d43ff0c18 | 1915 | __IO hw_mcg_c2_t C2; //!< [0x1] MCG Control 2 Register |
mbed_official | 146:f64d43ff0c18 | 1916 | __IO hw_mcg_c3_t C3; //!< [0x2] MCG Control 3 Register |
mbed_official | 146:f64d43ff0c18 | 1917 | __IO hw_mcg_c4_t C4; //!< [0x3] MCG Control 4 Register |
mbed_official | 146:f64d43ff0c18 | 1918 | __IO hw_mcg_c5_t C5; //!< [0x4] MCG Control 5 Register |
mbed_official | 146:f64d43ff0c18 | 1919 | __IO hw_mcg_c6_t C6; //!< [0x5] MCG Control 6 Register |
mbed_official | 146:f64d43ff0c18 | 1920 | __IO hw_mcg_s_t S; //!< [0x6] MCG Status Register |
mbed_official | 146:f64d43ff0c18 | 1921 | uint8_t _reserved0[1]; |
mbed_official | 146:f64d43ff0c18 | 1922 | __IO hw_mcg_sc_t SC; //!< [0x8] MCG Status and Control Register |
mbed_official | 146:f64d43ff0c18 | 1923 | uint8_t _reserved1[1]; |
mbed_official | 146:f64d43ff0c18 | 1924 | __IO hw_mcg_atcvh_t ATCVH; //!< [0xA] MCG Auto Trim Compare Value High Register |
mbed_official | 146:f64d43ff0c18 | 1925 | __IO hw_mcg_atcvl_t ATCVL; //!< [0xB] MCG Auto Trim Compare Value Low Register |
mbed_official | 146:f64d43ff0c18 | 1926 | __IO hw_mcg_c7_t C7; //!< [0xC] MCG Control 7 Register |
mbed_official | 146:f64d43ff0c18 | 1927 | __IO hw_mcg_c8_t C8; //!< [0xD] MCG Control 8 Register |
mbed_official | 146:f64d43ff0c18 | 1928 | } hw_mcg_t; |
mbed_official | 146:f64d43ff0c18 | 1929 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 1930 | |
mbed_official | 146:f64d43ff0c18 | 1931 | //! @brief Macro to access all MCG registers. |
mbed_official | 146:f64d43ff0c18 | 1932 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 1933 | //! use the '&' operator, like <code>&HW_MCG</code>. |
mbed_official | 146:f64d43ff0c18 | 1934 | #define HW_MCG (*(hw_mcg_t *) REGS_MCG_BASE) |
mbed_official | 146:f64d43ff0c18 | 1935 | #endif |
mbed_official | 146:f64d43ff0c18 | 1936 | |
mbed_official | 146:f64d43ff0c18 | 1937 | #endif // __HW_MCG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 1938 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 1939 | // EOF |