mbed-src-kl05 - mbed library sources

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mbed library sources

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dma.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:: mbed_official
Date:: Thu Apr 03 11:45:06 2014 +0100
Revision:: 149:1fb5f62b92bd
Parent:: targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dma.h@146:f64d43ff0c18

Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	146:f64d43ff0c18	1	/*
mbed_official	146:f64d43ff0c18	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official	146:f64d43ff0c18	3	* All rights reserved.
mbed_official	146:f64d43ff0c18	4	*
mbed_official	146:f64d43ff0c18	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	146:f64d43ff0c18	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	146:f64d43ff0c18	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official	146:f64d43ff0c18	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official	146:f64d43ff0c18	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official	146:f64d43ff0c18	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	146:f64d43ff0c18	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	146:f64d43ff0c18	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official	146:f64d43ff0c18	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official	146:f64d43ff0c18	14	* OF SUCH DAMAGE.
mbed_official	146:f64d43ff0c18	15	*/
mbed_official	146:f64d43ff0c18	16	/*
mbed_official	146:f64d43ff0c18	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	146:f64d43ff0c18	18	*
mbed_official	146:f64d43ff0c18	19	* This file was generated automatically and any changes may be lost.
mbed_official	146:f64d43ff0c18	20	*/
mbed_official	146:f64d43ff0c18	21	#ifndef __HW_DMA_REGISTERS_H__
mbed_official	146:f64d43ff0c18	22	#define __HW_DMA_REGISTERS_H__
mbed_official	146:f64d43ff0c18	23
mbed_official	146:f64d43ff0c18	24	#include "regs.h"
mbed_official	146:f64d43ff0c18	25
mbed_official	146:f64d43ff0c18	26	/*
mbed_official	146:f64d43ff0c18	27	* MK64F12 DMA
mbed_official	146:f64d43ff0c18	28	*
mbed_official	146:f64d43ff0c18	29	* Enhanced direct memory access controller
mbed_official	146:f64d43ff0c18	30	*
mbed_official	146:f64d43ff0c18	31	* Registers defined in this header file:
mbed_official	146:f64d43ff0c18	32	* - HW_DMA_CR - Control Register
mbed_official	146:f64d43ff0c18	33	* - HW_DMA_ES - Error Status Register
mbed_official	146:f64d43ff0c18	34	* - HW_DMA_ERQ - Enable Request Register
mbed_official	146:f64d43ff0c18	35	* - HW_DMA_EEI - Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	36	* - HW_DMA_CEEI - Clear Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	37	* - HW_DMA_SEEI - Set Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	38	* - HW_DMA_CERQ - Clear Enable Request Register
mbed_official	146:f64d43ff0c18	39	* - HW_DMA_SERQ - Set Enable Request Register
mbed_official	146:f64d43ff0c18	40	* - HW_DMA_CDNE - Clear DONE Status Bit Register
mbed_official	146:f64d43ff0c18	41	* - HW_DMA_SSRT - Set START Bit Register
mbed_official	146:f64d43ff0c18	42	* - HW_DMA_CERR - Clear Error Register
mbed_official	146:f64d43ff0c18	43	* - HW_DMA_CINT - Clear Interrupt Request Register
mbed_official	146:f64d43ff0c18	44	* - HW_DMA_INT - Interrupt Request Register
mbed_official	146:f64d43ff0c18	45	* - HW_DMA_ERR - Error Register
mbed_official	146:f64d43ff0c18	46	* - HW_DMA_HRS - Hardware Request Status Register
mbed_official	146:f64d43ff0c18	47	* - HW_DMA_DCHPRIn - Channel n Priority Register
mbed_official	146:f64d43ff0c18	48	* - HW_DMA_TCDn_SADDR - TCD Source Address
mbed_official	146:f64d43ff0c18	49	* - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
mbed_official	146:f64d43ff0c18	50	* - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
mbed_official	146:f64d43ff0c18	51	* - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
mbed_official	146:f64d43ff0c18	52	* - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
mbed_official	146:f64d43ff0c18	53	* - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
mbed_official	146:f64d43ff0c18	54	* - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
mbed_official	146:f64d43ff0c18	55	* - HW_DMA_TCDn_DADDR - TCD Destination Address
mbed_official	146:f64d43ff0c18	56	* - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
mbed_official	146:f64d43ff0c18	57	* - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official	146:f64d43ff0c18	58	* - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official	146:f64d43ff0c18	59	* - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
mbed_official	146:f64d43ff0c18	60	* - HW_DMA_TCDn_CSR - TCD Control and Status
mbed_official	146:f64d43ff0c18	61	* - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official	146:f64d43ff0c18	62	* - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official	146:f64d43ff0c18	63	*
mbed_official	146:f64d43ff0c18	64	* - hw_dma_t - Struct containing all module registers.
mbed_official	146:f64d43ff0c18	65	*/
mbed_official	146:f64d43ff0c18	66
mbed_official	146:f64d43ff0c18	67	//! @name Module base addresses
mbed_official	146:f64d43ff0c18	68	//@{
mbed_official	146:f64d43ff0c18	69	#ifndef REGS_DMA_BASE
mbed_official	146:f64d43ff0c18	70	#define HW_DMA_INSTANCE_COUNT (1U) //!< Number of instances of the DMA module.
mbed_official	146:f64d43ff0c18	71	#define HW_DMA0 (0U) //!< Instance number for DMA.
mbed_official	146:f64d43ff0c18	72	#define REGS_DMA0_BASE (0x40008000U) //!< Base address for DMA.
mbed_official	146:f64d43ff0c18	73
mbed_official	146:f64d43ff0c18	74	//! @brief Table of base addresses for DMA instances.
mbed_official	146:f64d43ff0c18	75	static const uint32_t __g_regs_DMA_base_addresses[] = {
mbed_official	146:f64d43ff0c18	76	REGS_DMA0_BASE,
mbed_official	146:f64d43ff0c18	77	};
mbed_official	146:f64d43ff0c18	78
mbed_official	146:f64d43ff0c18	79	//! @brief Get the base address of DMA by instance number.
mbed_official	146:f64d43ff0c18	80	//! @param x DMA instance number, from 0 through 0.
mbed_official	146:f64d43ff0c18	81	#define REGS_DMA_BASE(x) (__g_regs_DMA_base_addresses[(x)])
mbed_official	146:f64d43ff0c18	82
mbed_official	146:f64d43ff0c18	83	//! @brief Get the instance number given a base address.
mbed_official	146:f64d43ff0c18	84	//! @param b Base address for an instance of DMA.
mbed_official	146:f64d43ff0c18	85	#define REGS_DMA_INSTANCE(b) ((b) == REGS_DMA0_BASE ? HW_DMA0 : 0)
mbed_official	146:f64d43ff0c18	86	#endif
mbed_official	146:f64d43ff0c18	87	//@}
mbed_official	146:f64d43ff0c18	88
mbed_official	146:f64d43ff0c18	89	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	90	// HW_DMA_CR - Control Register
mbed_official	146:f64d43ff0c18	91	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	92
mbed_official	146:f64d43ff0c18	93	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	94	/*!
mbed_official	146:f64d43ff0c18	95	* @brief HW_DMA_CR - Control Register (RW)
mbed_official	146:f64d43ff0c18	96	*
mbed_official	146:f64d43ff0c18	97	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	98	*
mbed_official	146:f64d43ff0c18	99	* The CR defines the basic operating configuration of the DMA. Arbitration can
mbed_official	146:f64d43ff0c18	100	* be configured to use either a fixed-priority or a round-robin scheme. For
mbed_official	146:f64d43ff0c18	101	* fixed-priority arbitration, the highest priority channel requesting service is
mbed_official	146:f64d43ff0c18	102	* selected to execute. The channel priority registers assign the priorities; see
mbed_official	146:f64d43ff0c18	103	* the DCHPRIn registers. For round-robin arbitration, the channel priorities are
mbed_official	146:f64d43ff0c18	104	* ignored and channels are cycled through (from high to low channel number)
mbed_official	146:f64d43ff0c18	105	* without regard to priority. For correct operation, writes to the CR register must
mbed_official	146:f64d43ff0c18	106	* be performed only when the DMA channels are inactive; that is, when
mbed_official	146:f64d43ff0c18	107	* TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
mbed_official	146:f64d43ff0c18	108	* the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
mbed_official	146:f64d43ff0c18	109	* minor loop completion. When minor loop offsets are enabled, the minor loop
mbed_official	146:f64d43ff0c18	110	* offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
mbed_official	146:f64d43ff0c18	111	* destination address (TCDn_DADDR), or to both prior to the addresses being
mbed_official	146:f64d43ff0c18	112	* written back into the TCD. If the major loop is complete, the minor loop offset is
mbed_official	146:f64d43ff0c18	113	* ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
mbed_official	146:f64d43ff0c18	114	* used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
mbed_official	146:f64d43ff0c18	115	* mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
mbed_official	146:f64d43ff0c18	116	* is used to specify multiple fields: a source enable bit (SMLOE) to specify
mbed_official	146:f64d43ff0c18	117	* the minor loop offset should be applied to the source address (TCDn_SADDR) upon
mbed_official	146:f64d43ff0c18	118	* minor loop completion, a destination enable bit (DMLOE) to specify the minor
mbed_official	146:f64d43ff0c18	119	* loop offset should be applied to the destination address (TCDn_DADDR) upon
mbed_official	146:f64d43ff0c18	120	* minor loop completion, and the sign extended minor loop offset value (MLOFF). The
mbed_official	146:f64d43ff0c18	121	* same offset value (MLOFF) is used for both source and destination minor loop
mbed_official	146:f64d43ff0c18	122	* offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
mbed_official	146:f64d43ff0c18	123	* NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
mbed_official	146:f64d43ff0c18	124	* (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
mbed_official	146:f64d43ff0c18	125	* minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
mbed_official	146:f64d43ff0c18	126	* assigned to the NBYTES field.
mbed_official	146:f64d43ff0c18	127	*/
mbed_official	146:f64d43ff0c18	128	typedef union _hw_dma_cr
mbed_official	146:f64d43ff0c18	129	{
mbed_official	146:f64d43ff0c18	130	uint32_t U;
mbed_official	146:f64d43ff0c18	131	struct _hw_dma_cr_bitfields
mbed_official	146:f64d43ff0c18	132	{
mbed_official	146:f64d43ff0c18	133	uint32_t RESERVED0 : 1; //!< [0] Reserved.
mbed_official	146:f64d43ff0c18	134	uint32_t EDBG : 1; //!< [1] Enable Debug
mbed_official	146:f64d43ff0c18	135	uint32_t ERCA : 1; //!< [2] Enable Round Robin Channel Arbitration
mbed_official	146:f64d43ff0c18	136	uint32_t RESERVED1 : 1; //!< [3] Reserved.
mbed_official	146:f64d43ff0c18	137	uint32_t HOE : 1; //!< [4] Halt On Error
mbed_official	146:f64d43ff0c18	138	uint32_t HALT : 1; //!< [5] Halt DMA Operations
mbed_official	146:f64d43ff0c18	139	uint32_t CLM : 1; //!< [6] Continuous Link Mode
mbed_official	146:f64d43ff0c18	140	uint32_t EMLM : 1; //!< [7] Enable Minor Loop Mapping
mbed_official	146:f64d43ff0c18	141	uint32_t RESERVED2 : 8; //!< [15:8]
mbed_official	146:f64d43ff0c18	142	uint32_t ECX : 1; //!< [16] Error Cancel Transfer
mbed_official	146:f64d43ff0c18	143	uint32_t CX : 1; //!< [17] Cancel Transfer
mbed_official	146:f64d43ff0c18	144	uint32_t RESERVED3 : 14; //!< [31:18]
mbed_official	146:f64d43ff0c18	145	} B;
mbed_official	146:f64d43ff0c18	146	} hw_dma_cr_t;
mbed_official	146:f64d43ff0c18	147	#endif
mbed_official	146:f64d43ff0c18	148
mbed_official	146:f64d43ff0c18	149	/*!
mbed_official	146:f64d43ff0c18	150	* @name Constants and macros for entire DMA_CR register
mbed_official	146:f64d43ff0c18	151	*/
mbed_official	146:f64d43ff0c18	152	//@{
mbed_official	146:f64d43ff0c18	153	#define HW_DMA_CR_ADDR(x) (REGS_DMA_BASE(x) + 0x0U)
mbed_official	146:f64d43ff0c18	154
mbed_official	146:f64d43ff0c18	155	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	156	#define HW_DMA_CR(x) ((__IO hw_dma_cr_t ) HW_DMA_CR_ADDR(x))
mbed_official	146:f64d43ff0c18	157	#define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
mbed_official	146:f64d43ff0c18	158	#define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
mbed_official	146:f64d43ff0c18	159	#define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	160	#define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	161	#define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	162	#endif
mbed_official	146:f64d43ff0c18	163	//@}
mbed_official	146:f64d43ff0c18	164
mbed_official	146:f64d43ff0c18	165	/*
mbed_official	146:f64d43ff0c18	166	* Constants & macros for individual DMA_CR bitfields
mbed_official	146:f64d43ff0c18	167	*/
mbed_official	146:f64d43ff0c18	168
mbed_official	146:f64d43ff0c18	169	/*!
mbed_official	146:f64d43ff0c18	170	* @name Register DMA_CR, field EDBG[1] (RW)
mbed_official	146:f64d43ff0c18	171	*
mbed_official	146:f64d43ff0c18	172	* Values:
mbed_official	146:f64d43ff0c18	173	* - 0 - When in debug mode, the DMA continues to operate.
mbed_official	146:f64d43ff0c18	174	* - 1 - When in debug mode, the DMA stalls the start of a new channel.
mbed_official	146:f64d43ff0c18	175	* Executing channels are allowed to complete. Channel execution resumes when the
mbed_official	146:f64d43ff0c18	176	* system exits debug mode or the EDBG bit is cleared.
mbed_official	146:f64d43ff0c18	177	*/
mbed_official	146:f64d43ff0c18	178	//@{
mbed_official	146:f64d43ff0c18	179	#define BP_DMA_CR_EDBG (1U) //!< Bit position for DMA_CR_EDBG.
mbed_official	146:f64d43ff0c18	180	#define BM_DMA_CR_EDBG (0x00000002U) //!< Bit mask for DMA_CR_EDBG.
mbed_official	146:f64d43ff0c18	181	#define BS_DMA_CR_EDBG (1U) //!< Bit field size in bits for DMA_CR_EDBG.
mbed_official	146:f64d43ff0c18	182
mbed_official	146:f64d43ff0c18	183	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	184	//! @brief Read current value of the DMA_CR_EDBG field.
mbed_official	146:f64d43ff0c18	185	#define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
mbed_official	146:f64d43ff0c18	186	#endif
mbed_official	146:f64d43ff0c18	187
mbed_official	146:f64d43ff0c18	188	//! @brief Format value for bitfield DMA_CR_EDBG.
mbed_official	146:f64d43ff0c18	189	#define BF_DMA_CR_EDBG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EDBG), uint32_t) & BM_DMA_CR_EDBG)
mbed_official	146:f64d43ff0c18	190
mbed_official	146:f64d43ff0c18	191	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	192	//! @brief Set the EDBG field to a new value.
mbed_official	146:f64d43ff0c18	193	#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
mbed_official	146:f64d43ff0c18	194	#endif
mbed_official	146:f64d43ff0c18	195	//@}
mbed_official	146:f64d43ff0c18	196
mbed_official	146:f64d43ff0c18	197	/*!
mbed_official	146:f64d43ff0c18	198	* @name Register DMA_CR, field ERCA[2] (RW)
mbed_official	146:f64d43ff0c18	199	*
mbed_official	146:f64d43ff0c18	200	* Values:
mbed_official	146:f64d43ff0c18	201	* - 0 - Fixed priority arbitration is used for channel selection .
mbed_official	146:f64d43ff0c18	202	* - 1 - Round robin arbitration is used for channel selection .
mbed_official	146:f64d43ff0c18	203	*/
mbed_official	146:f64d43ff0c18	204	//@{
mbed_official	146:f64d43ff0c18	205	#define BP_DMA_CR_ERCA (2U) //!< Bit position for DMA_CR_ERCA.
mbed_official	146:f64d43ff0c18	206	#define BM_DMA_CR_ERCA (0x00000004U) //!< Bit mask for DMA_CR_ERCA.
mbed_official	146:f64d43ff0c18	207	#define BS_DMA_CR_ERCA (1U) //!< Bit field size in bits for DMA_CR_ERCA.
mbed_official	146:f64d43ff0c18	208
mbed_official	146:f64d43ff0c18	209	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	210	//! @brief Read current value of the DMA_CR_ERCA field.
mbed_official	146:f64d43ff0c18	211	#define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
mbed_official	146:f64d43ff0c18	212	#endif
mbed_official	146:f64d43ff0c18	213
mbed_official	146:f64d43ff0c18	214	//! @brief Format value for bitfield DMA_CR_ERCA.
mbed_official	146:f64d43ff0c18	215	#define BF_DMA_CR_ERCA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ERCA), uint32_t) & BM_DMA_CR_ERCA)
mbed_official	146:f64d43ff0c18	216
mbed_official	146:f64d43ff0c18	217	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	218	//! @brief Set the ERCA field to a new value.
mbed_official	146:f64d43ff0c18	219	#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
mbed_official	146:f64d43ff0c18	220	#endif
mbed_official	146:f64d43ff0c18	221	//@}
mbed_official	146:f64d43ff0c18	222
mbed_official	146:f64d43ff0c18	223	/*!
mbed_official	146:f64d43ff0c18	224	* @name Register DMA_CR, field HOE[4] (RW)
mbed_official	146:f64d43ff0c18	225	*
mbed_official	146:f64d43ff0c18	226	* Values:
mbed_official	146:f64d43ff0c18	227	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	228	* - 1 - Any error causes the HALT bit to set. Subsequently, all service
mbed_official	146:f64d43ff0c18	229	* requests are ignored until the HALT bit is cleared.
mbed_official	146:f64d43ff0c18	230	*/
mbed_official	146:f64d43ff0c18	231	//@{
mbed_official	146:f64d43ff0c18	232	#define BP_DMA_CR_HOE (4U) //!< Bit position for DMA_CR_HOE.
mbed_official	146:f64d43ff0c18	233	#define BM_DMA_CR_HOE (0x00000010U) //!< Bit mask for DMA_CR_HOE.
mbed_official	146:f64d43ff0c18	234	#define BS_DMA_CR_HOE (1U) //!< Bit field size in bits for DMA_CR_HOE.
mbed_official	146:f64d43ff0c18	235
mbed_official	146:f64d43ff0c18	236	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	237	//! @brief Read current value of the DMA_CR_HOE field.
mbed_official	146:f64d43ff0c18	238	#define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
mbed_official	146:f64d43ff0c18	239	#endif
mbed_official	146:f64d43ff0c18	240
mbed_official	146:f64d43ff0c18	241	//! @brief Format value for bitfield DMA_CR_HOE.
mbed_official	146:f64d43ff0c18	242	#define BF_DMA_CR_HOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HOE), uint32_t) & BM_DMA_CR_HOE)
mbed_official	146:f64d43ff0c18	243
mbed_official	146:f64d43ff0c18	244	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	245	//! @brief Set the HOE field to a new value.
mbed_official	146:f64d43ff0c18	246	#define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
mbed_official	146:f64d43ff0c18	247	#endif
mbed_official	146:f64d43ff0c18	248	//@}
mbed_official	146:f64d43ff0c18	249
mbed_official	146:f64d43ff0c18	250	/*!
mbed_official	146:f64d43ff0c18	251	* @name Register DMA_CR, field HALT[5] (RW)
mbed_official	146:f64d43ff0c18	252	*
mbed_official	146:f64d43ff0c18	253	* Values:
mbed_official	146:f64d43ff0c18	254	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	255	* - 1 - Stall the start of any new channels. Executing channels are allowed to
mbed_official	146:f64d43ff0c18	256	* complete. Channel execution resumes when this bit is cleared.
mbed_official	146:f64d43ff0c18	257	*/
mbed_official	146:f64d43ff0c18	258	//@{
mbed_official	146:f64d43ff0c18	259	#define BP_DMA_CR_HALT (5U) //!< Bit position for DMA_CR_HALT.
mbed_official	146:f64d43ff0c18	260	#define BM_DMA_CR_HALT (0x00000020U) //!< Bit mask for DMA_CR_HALT.
mbed_official	146:f64d43ff0c18	261	#define BS_DMA_CR_HALT (1U) //!< Bit field size in bits for DMA_CR_HALT.
mbed_official	146:f64d43ff0c18	262
mbed_official	146:f64d43ff0c18	263	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	264	//! @brief Read current value of the DMA_CR_HALT field.
mbed_official	146:f64d43ff0c18	265	#define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
mbed_official	146:f64d43ff0c18	266	#endif
mbed_official	146:f64d43ff0c18	267
mbed_official	146:f64d43ff0c18	268	//! @brief Format value for bitfield DMA_CR_HALT.
mbed_official	146:f64d43ff0c18	269	#define BF_DMA_CR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HALT), uint32_t) & BM_DMA_CR_HALT)
mbed_official	146:f64d43ff0c18	270
mbed_official	146:f64d43ff0c18	271	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	272	//! @brief Set the HALT field to a new value.
mbed_official	146:f64d43ff0c18	273	#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
mbed_official	146:f64d43ff0c18	274	#endif
mbed_official	146:f64d43ff0c18	275	//@}
mbed_official	146:f64d43ff0c18	276
mbed_official	146:f64d43ff0c18	277	/*!
mbed_official	146:f64d43ff0c18	278	* @name Register DMA_CR, field CLM[6] (RW)
mbed_official	146:f64d43ff0c18	279	*
mbed_official	146:f64d43ff0c18	280	* Values:
mbed_official	146:f64d43ff0c18	281	* - 0 - A minor loop channel link made to itself goes through channel
mbed_official	146:f64d43ff0c18	282	* arbitration before being activated again.
mbed_official	146:f64d43ff0c18	283	* - 1 - A minor loop channel link made to itself does not go through channel
mbed_official	146:f64d43ff0c18	284	* arbitration before being activated again. Upon minor loop completion, the
mbed_official	146:f64d43ff0c18	285	* channel activates again if that channel has a minor loop channel link
mbed_official	146:f64d43ff0c18	286	* enabled and the link channel is itself. This effectively applies the minor loop
mbed_official	146:f64d43ff0c18	287	* offsets and restarts the next minor loop.
mbed_official	146:f64d43ff0c18	288	*/
mbed_official	146:f64d43ff0c18	289	//@{
mbed_official	146:f64d43ff0c18	290	#define BP_DMA_CR_CLM (6U) //!< Bit position for DMA_CR_CLM.
mbed_official	146:f64d43ff0c18	291	#define BM_DMA_CR_CLM (0x00000040U) //!< Bit mask for DMA_CR_CLM.
mbed_official	146:f64d43ff0c18	292	#define BS_DMA_CR_CLM (1U) //!< Bit field size in bits for DMA_CR_CLM.
mbed_official	146:f64d43ff0c18	293
mbed_official	146:f64d43ff0c18	294	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	295	//! @brief Read current value of the DMA_CR_CLM field.
mbed_official	146:f64d43ff0c18	296	#define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
mbed_official	146:f64d43ff0c18	297	#endif
mbed_official	146:f64d43ff0c18	298
mbed_official	146:f64d43ff0c18	299	//! @brief Format value for bitfield DMA_CR_CLM.
mbed_official	146:f64d43ff0c18	300	#define BF_DMA_CR_CLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CLM), uint32_t) & BM_DMA_CR_CLM)
mbed_official	146:f64d43ff0c18	301
mbed_official	146:f64d43ff0c18	302	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	303	//! @brief Set the CLM field to a new value.
mbed_official	146:f64d43ff0c18	304	#define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
mbed_official	146:f64d43ff0c18	305	#endif
mbed_official	146:f64d43ff0c18	306	//@}
mbed_official	146:f64d43ff0c18	307
mbed_official	146:f64d43ff0c18	308	/*!
mbed_official	146:f64d43ff0c18	309	* @name Register DMA_CR, field EMLM[7] (RW)
mbed_official	146:f64d43ff0c18	310	*
mbed_official	146:f64d43ff0c18	311	* Values:
mbed_official	146:f64d43ff0c18	312	* - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
mbed_official	146:f64d43ff0c18	313	* - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
mbed_official	146:f64d43ff0c18	314	* an offset field, and the NBYTES field. The individual enable fields allow
mbed_official	146:f64d43ff0c18	315	* the minor loop offset to be applied to the source address, the destination
mbed_official	146:f64d43ff0c18	316	* address, or both. The NBYTES field is reduced when either offset is
mbed_official	146:f64d43ff0c18	317	* enabled.
mbed_official	146:f64d43ff0c18	318	*/
mbed_official	146:f64d43ff0c18	319	//@{
mbed_official	146:f64d43ff0c18	320	#define BP_DMA_CR_EMLM (7U) //!< Bit position for DMA_CR_EMLM.
mbed_official	146:f64d43ff0c18	321	#define BM_DMA_CR_EMLM (0x00000080U) //!< Bit mask for DMA_CR_EMLM.
mbed_official	146:f64d43ff0c18	322	#define BS_DMA_CR_EMLM (1U) //!< Bit field size in bits for DMA_CR_EMLM.
mbed_official	146:f64d43ff0c18	323
mbed_official	146:f64d43ff0c18	324	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	325	//! @brief Read current value of the DMA_CR_EMLM field.
mbed_official	146:f64d43ff0c18	326	#define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
mbed_official	146:f64d43ff0c18	327	#endif
mbed_official	146:f64d43ff0c18	328
mbed_official	146:f64d43ff0c18	329	//! @brief Format value for bitfield DMA_CR_EMLM.
mbed_official	146:f64d43ff0c18	330	#define BF_DMA_CR_EMLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EMLM), uint32_t) & BM_DMA_CR_EMLM)
mbed_official	146:f64d43ff0c18	331
mbed_official	146:f64d43ff0c18	332	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	333	//! @brief Set the EMLM field to a new value.
mbed_official	146:f64d43ff0c18	334	#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
mbed_official	146:f64d43ff0c18	335	#endif
mbed_official	146:f64d43ff0c18	336	//@}
mbed_official	146:f64d43ff0c18	337
mbed_official	146:f64d43ff0c18	338	/*!
mbed_official	146:f64d43ff0c18	339	* @name Register DMA_CR, field ECX[16] (RW)
mbed_official	146:f64d43ff0c18	340	*
mbed_official	146:f64d43ff0c18	341	* Values:
mbed_official	146:f64d43ff0c18	342	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	343	* - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
mbed_official	146:f64d43ff0c18	344	* Stop the executing channel and force the minor loop to finish. The cancel
mbed_official	146:f64d43ff0c18	345	* takes effect after the last write of the current read/write sequence. The
mbed_official	146:f64d43ff0c18	346	* ECX bit clears itself after the cancel is honored. In addition to
mbed_official	146:f64d43ff0c18	347	* cancelling the transfer, ECX treats the cancel as an error condition, thus updating
mbed_official	146:f64d43ff0c18	348	* the Error Status register (DMAx_ES) and generating an optional error
mbed_official	146:f64d43ff0c18	349	* interrupt.
mbed_official	146:f64d43ff0c18	350	*/
mbed_official	146:f64d43ff0c18	351	//@{
mbed_official	146:f64d43ff0c18	352	#define BP_DMA_CR_ECX (16U) //!< Bit position for DMA_CR_ECX.
mbed_official	146:f64d43ff0c18	353	#define BM_DMA_CR_ECX (0x00010000U) //!< Bit mask for DMA_CR_ECX.
mbed_official	146:f64d43ff0c18	354	#define BS_DMA_CR_ECX (1U) //!< Bit field size in bits for DMA_CR_ECX.
mbed_official	146:f64d43ff0c18	355
mbed_official	146:f64d43ff0c18	356	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	357	//! @brief Read current value of the DMA_CR_ECX field.
mbed_official	146:f64d43ff0c18	358	#define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
mbed_official	146:f64d43ff0c18	359	#endif
mbed_official	146:f64d43ff0c18	360
mbed_official	146:f64d43ff0c18	361	//! @brief Format value for bitfield DMA_CR_ECX.
mbed_official	146:f64d43ff0c18	362	#define BF_DMA_CR_ECX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ECX), uint32_t) & BM_DMA_CR_ECX)
mbed_official	146:f64d43ff0c18	363
mbed_official	146:f64d43ff0c18	364	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	365	//! @brief Set the ECX field to a new value.
mbed_official	146:f64d43ff0c18	366	#define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
mbed_official	146:f64d43ff0c18	367	#endif
mbed_official	146:f64d43ff0c18	368	//@}
mbed_official	146:f64d43ff0c18	369
mbed_official	146:f64d43ff0c18	370	/*!
mbed_official	146:f64d43ff0c18	371	* @name Register DMA_CR, field CX[17] (RW)
mbed_official	146:f64d43ff0c18	372	*
mbed_official	146:f64d43ff0c18	373	* Values:
mbed_official	146:f64d43ff0c18	374	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	375	* - 1 - Cancel the remaining data transfer. Stop the executing channel and
mbed_official	146:f64d43ff0c18	376	* force the minor loop to finish. The cancel takes effect after the last write
mbed_official	146:f64d43ff0c18	377	* of the current read/write sequence. The CX bit clears itself after the
mbed_official	146:f64d43ff0c18	378	* cancel has been honored. This cancel retires the channel normally as if the
mbed_official	146:f64d43ff0c18	379	* minor loop was completed.
mbed_official	146:f64d43ff0c18	380	*/
mbed_official	146:f64d43ff0c18	381	//@{
mbed_official	146:f64d43ff0c18	382	#define BP_DMA_CR_CX (17U) //!< Bit position for DMA_CR_CX.
mbed_official	146:f64d43ff0c18	383	#define BM_DMA_CR_CX (0x00020000U) //!< Bit mask for DMA_CR_CX.
mbed_official	146:f64d43ff0c18	384	#define BS_DMA_CR_CX (1U) //!< Bit field size in bits for DMA_CR_CX.
mbed_official	146:f64d43ff0c18	385
mbed_official	146:f64d43ff0c18	386	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	387	//! @brief Read current value of the DMA_CR_CX field.
mbed_official	146:f64d43ff0c18	388	#define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
mbed_official	146:f64d43ff0c18	389	#endif
mbed_official	146:f64d43ff0c18	390
mbed_official	146:f64d43ff0c18	391	//! @brief Format value for bitfield DMA_CR_CX.
mbed_official	146:f64d43ff0c18	392	#define BF_DMA_CR_CX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CX), uint32_t) & BM_DMA_CR_CX)
mbed_official	146:f64d43ff0c18	393
mbed_official	146:f64d43ff0c18	394	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	395	//! @brief Set the CX field to a new value.
mbed_official	146:f64d43ff0c18	396	#define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
mbed_official	146:f64d43ff0c18	397	#endif
mbed_official	146:f64d43ff0c18	398	//@}
mbed_official	146:f64d43ff0c18	399
mbed_official	146:f64d43ff0c18	400	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	401	// HW_DMA_ES - Error Status Register
mbed_official	146:f64d43ff0c18	402	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	403
mbed_official	146:f64d43ff0c18	404	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	405	/*!
mbed_official	146:f64d43ff0c18	406	* @brief HW_DMA_ES - Error Status Register (RO)
mbed_official	146:f64d43ff0c18	407	*
mbed_official	146:f64d43ff0c18	408	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	409	*
mbed_official	146:f64d43ff0c18	410	* The ES provides information concerning the last recorded channel error.
mbed_official	146:f64d43ff0c18	411	* Channel errors can be caused by: A configuration error, that is: An illegal setting
mbed_official	146:f64d43ff0c18	412	* in the transfer-control descriptor, or An illegal priority register setting
mbed_official	146:f64d43ff0c18	413	* in fixed-arbitration An error termination to a bus master read or write cycle
mbed_official	146:f64d43ff0c18	414	* See the Error Reporting and Handling section for more details.
mbed_official	146:f64d43ff0c18	415	*/
mbed_official	146:f64d43ff0c18	416	typedef union _hw_dma_es
mbed_official	146:f64d43ff0c18	417	{
mbed_official	146:f64d43ff0c18	418	uint32_t U;
mbed_official	146:f64d43ff0c18	419	struct _hw_dma_es_bitfields
mbed_official	146:f64d43ff0c18	420	{
mbed_official	146:f64d43ff0c18	421	uint32_t DBE : 1; //!< [0] Destination Bus Error
mbed_official	146:f64d43ff0c18	422	uint32_t SBE : 1; //!< [1] Source Bus Error
mbed_official	146:f64d43ff0c18	423	uint32_t SGE : 1; //!< [2] Scatter/Gather Configuration Error
mbed_official	146:f64d43ff0c18	424	uint32_t NCE : 1; //!< [3] NBYTES/CITER Configuration Error
mbed_official	146:f64d43ff0c18	425	uint32_t DOE : 1; //!< [4] Destination Offset Error
mbed_official	146:f64d43ff0c18	426	uint32_t DAE : 1; //!< [5] Destination Address Error
mbed_official	146:f64d43ff0c18	427	uint32_t SOE : 1; //!< [6] Source Offset Error
mbed_official	146:f64d43ff0c18	428	uint32_t SAE : 1; //!< [7] Source Address Error
mbed_official	146:f64d43ff0c18	429	uint32_t ERRCHN : 4; //!< [11:8] Error Channel Number or Canceled
mbed_official	146:f64d43ff0c18	430	//! Channel Number
mbed_official	146:f64d43ff0c18	431	uint32_t RESERVED0 : 2; //!< [13:12]
mbed_official	146:f64d43ff0c18	432	uint32_t CPE : 1; //!< [14] Channel Priority Error
mbed_official	146:f64d43ff0c18	433	uint32_t RESERVED1 : 1; //!< [15]
mbed_official	146:f64d43ff0c18	434	uint32_t ECX : 1; //!< [16] Transfer Canceled
mbed_official	146:f64d43ff0c18	435	uint32_t RESERVED2 : 14; //!< [30:17]
mbed_official	146:f64d43ff0c18	436	uint32_t VLD : 1; //!< [31]
mbed_official	146:f64d43ff0c18	437	} B;
mbed_official	146:f64d43ff0c18	438	} hw_dma_es_t;
mbed_official	146:f64d43ff0c18	439	#endif
mbed_official	146:f64d43ff0c18	440
mbed_official	146:f64d43ff0c18	441	/*!
mbed_official	146:f64d43ff0c18	442	* @name Constants and macros for entire DMA_ES register
mbed_official	146:f64d43ff0c18	443	*/
mbed_official	146:f64d43ff0c18	444	//@{
mbed_official	146:f64d43ff0c18	445	#define HW_DMA_ES_ADDR(x) (REGS_DMA_BASE(x) + 0x4U)
mbed_official	146:f64d43ff0c18	446
mbed_official	146:f64d43ff0c18	447	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	448	#define HW_DMA_ES(x) ((__I hw_dma_es_t ) HW_DMA_ES_ADDR(x))
mbed_official	146:f64d43ff0c18	449	#define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
mbed_official	146:f64d43ff0c18	450	#endif
mbed_official	146:f64d43ff0c18	451	//@}
mbed_official	146:f64d43ff0c18	452
mbed_official	146:f64d43ff0c18	453	/*
mbed_official	146:f64d43ff0c18	454	* Constants & macros for individual DMA_ES bitfields
mbed_official	146:f64d43ff0c18	455	*/
mbed_official	146:f64d43ff0c18	456
mbed_official	146:f64d43ff0c18	457	/*!
mbed_official	146:f64d43ff0c18	458	* @name Register DMA_ES, field DBE[0] (RO)
mbed_official	146:f64d43ff0c18	459	*
mbed_official	146:f64d43ff0c18	460	* Values:
mbed_official	146:f64d43ff0c18	461	* - 0 - No destination bus error
mbed_official	146:f64d43ff0c18	462	* - 1 - The last recorded error was a bus error on a destination write
mbed_official	146:f64d43ff0c18	463	*/
mbed_official	146:f64d43ff0c18	464	//@{
mbed_official	146:f64d43ff0c18	465	#define BP_DMA_ES_DBE (0U) //!< Bit position for DMA_ES_DBE.
mbed_official	146:f64d43ff0c18	466	#define BM_DMA_ES_DBE (0x00000001U) //!< Bit mask for DMA_ES_DBE.
mbed_official	146:f64d43ff0c18	467	#define BS_DMA_ES_DBE (1U) //!< Bit field size in bits for DMA_ES_DBE.
mbed_official	146:f64d43ff0c18	468
mbed_official	146:f64d43ff0c18	469	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	470	//! @brief Read current value of the DMA_ES_DBE field.
mbed_official	146:f64d43ff0c18	471	#define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
mbed_official	146:f64d43ff0c18	472	#endif
mbed_official	146:f64d43ff0c18	473	//@}
mbed_official	146:f64d43ff0c18	474
mbed_official	146:f64d43ff0c18	475	/*!
mbed_official	146:f64d43ff0c18	476	* @name Register DMA_ES, field SBE[1] (RO)
mbed_official	146:f64d43ff0c18	477	*
mbed_official	146:f64d43ff0c18	478	* Values:
mbed_official	146:f64d43ff0c18	479	* - 0 - No source bus error
mbed_official	146:f64d43ff0c18	480	* - 1 - The last recorded error was a bus error on a source read
mbed_official	146:f64d43ff0c18	481	*/
mbed_official	146:f64d43ff0c18	482	//@{
mbed_official	146:f64d43ff0c18	483	#define BP_DMA_ES_SBE (1U) //!< Bit position for DMA_ES_SBE.
mbed_official	146:f64d43ff0c18	484	#define BM_DMA_ES_SBE (0x00000002U) //!< Bit mask for DMA_ES_SBE.
mbed_official	146:f64d43ff0c18	485	#define BS_DMA_ES_SBE (1U) //!< Bit field size in bits for DMA_ES_SBE.
mbed_official	146:f64d43ff0c18	486
mbed_official	146:f64d43ff0c18	487	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	488	//! @brief Read current value of the DMA_ES_SBE field.
mbed_official	146:f64d43ff0c18	489	#define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
mbed_official	146:f64d43ff0c18	490	#endif
mbed_official	146:f64d43ff0c18	491	//@}
mbed_official	146:f64d43ff0c18	492
mbed_official	146:f64d43ff0c18	493	/*!
mbed_official	146:f64d43ff0c18	494	* @name Register DMA_ES, field SGE[2] (RO)
mbed_official	146:f64d43ff0c18	495	*
mbed_official	146:f64d43ff0c18	496	* Values:
mbed_official	146:f64d43ff0c18	497	* - 0 - No scatter/gather configuration error
mbed_official	146:f64d43ff0c18	498	* - 1 - The last recorded error was a configuration error detected in the
mbed_official	146:f64d43ff0c18	499	* TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
mbed_official	146:f64d43ff0c18	500	* operation after major loop completion if TCDn_CSR[ESG] is enabled.
mbed_official	146:f64d43ff0c18	501	* TCDn_DLASTSGA is not on a 32 byte boundary.
mbed_official	146:f64d43ff0c18	502	*/
mbed_official	146:f64d43ff0c18	503	//@{
mbed_official	146:f64d43ff0c18	504	#define BP_DMA_ES_SGE (2U) //!< Bit position for DMA_ES_SGE.
mbed_official	146:f64d43ff0c18	505	#define BM_DMA_ES_SGE (0x00000004U) //!< Bit mask for DMA_ES_SGE.
mbed_official	146:f64d43ff0c18	506	#define BS_DMA_ES_SGE (1U) //!< Bit field size in bits for DMA_ES_SGE.
mbed_official	146:f64d43ff0c18	507
mbed_official	146:f64d43ff0c18	508	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	509	//! @brief Read current value of the DMA_ES_SGE field.
mbed_official	146:f64d43ff0c18	510	#define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
mbed_official	146:f64d43ff0c18	511	#endif
mbed_official	146:f64d43ff0c18	512	//@}
mbed_official	146:f64d43ff0c18	513
mbed_official	146:f64d43ff0c18	514	/*!
mbed_official	146:f64d43ff0c18	515	* @name Register DMA_ES, field NCE[3] (RO)
mbed_official	146:f64d43ff0c18	516	*
mbed_official	146:f64d43ff0c18	517	* Values:
mbed_official	146:f64d43ff0c18	518	* - 0 - No NBYTES/CITER configuration error
mbed_official	146:f64d43ff0c18	519	* - 1 - The last recorded error was a configuration error detected in the
mbed_official	146:f64d43ff0c18	520	* TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
mbed_official	146:f64d43ff0c18	521	* TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
mbed_official	146:f64d43ff0c18	522	* TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
mbed_official	146:f64d43ff0c18	523	*/
mbed_official	146:f64d43ff0c18	524	//@{
mbed_official	146:f64d43ff0c18	525	#define BP_DMA_ES_NCE (3U) //!< Bit position for DMA_ES_NCE.
mbed_official	146:f64d43ff0c18	526	#define BM_DMA_ES_NCE (0x00000008U) //!< Bit mask for DMA_ES_NCE.
mbed_official	146:f64d43ff0c18	527	#define BS_DMA_ES_NCE (1U) //!< Bit field size in bits for DMA_ES_NCE.
mbed_official	146:f64d43ff0c18	528
mbed_official	146:f64d43ff0c18	529	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	530	//! @brief Read current value of the DMA_ES_NCE field.
mbed_official	146:f64d43ff0c18	531	#define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
mbed_official	146:f64d43ff0c18	532	#endif
mbed_official	146:f64d43ff0c18	533	//@}
mbed_official	146:f64d43ff0c18	534
mbed_official	146:f64d43ff0c18	535	/*!
mbed_official	146:f64d43ff0c18	536	* @name Register DMA_ES, field DOE[4] (RO)
mbed_official	146:f64d43ff0c18	537	*
mbed_official	146:f64d43ff0c18	538	* Values:
mbed_official	146:f64d43ff0c18	539	* - 0 - No destination offset configuration error
mbed_official	146:f64d43ff0c18	540	* - 1 - The last recorded error was a configuration error detected in the
mbed_official	146:f64d43ff0c18	541	* TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
mbed_official	146:f64d43ff0c18	542	*/
mbed_official	146:f64d43ff0c18	543	//@{
mbed_official	146:f64d43ff0c18	544	#define BP_DMA_ES_DOE (4U) //!< Bit position for DMA_ES_DOE.
mbed_official	146:f64d43ff0c18	545	#define BM_DMA_ES_DOE (0x00000010U) //!< Bit mask for DMA_ES_DOE.
mbed_official	146:f64d43ff0c18	546	#define BS_DMA_ES_DOE (1U) //!< Bit field size in bits for DMA_ES_DOE.
mbed_official	146:f64d43ff0c18	547
mbed_official	146:f64d43ff0c18	548	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	549	//! @brief Read current value of the DMA_ES_DOE field.
mbed_official	146:f64d43ff0c18	550	#define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
mbed_official	146:f64d43ff0c18	551	#endif
mbed_official	146:f64d43ff0c18	552	//@}
mbed_official	146:f64d43ff0c18	553
mbed_official	146:f64d43ff0c18	554	/*!
mbed_official	146:f64d43ff0c18	555	* @name Register DMA_ES, field DAE[5] (RO)
mbed_official	146:f64d43ff0c18	556	*
mbed_official	146:f64d43ff0c18	557	* Values:
mbed_official	146:f64d43ff0c18	558	* - 0 - No destination address configuration error
mbed_official	146:f64d43ff0c18	559	* - 1 - The last recorded error was a configuration error detected in the
mbed_official	146:f64d43ff0c18	560	* TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
mbed_official	146:f64d43ff0c18	561	*/
mbed_official	146:f64d43ff0c18	562	//@{
mbed_official	146:f64d43ff0c18	563	#define BP_DMA_ES_DAE (5U) //!< Bit position for DMA_ES_DAE.
mbed_official	146:f64d43ff0c18	564	#define BM_DMA_ES_DAE (0x00000020U) //!< Bit mask for DMA_ES_DAE.
mbed_official	146:f64d43ff0c18	565	#define BS_DMA_ES_DAE (1U) //!< Bit field size in bits for DMA_ES_DAE.
mbed_official	146:f64d43ff0c18	566
mbed_official	146:f64d43ff0c18	567	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	568	//! @brief Read current value of the DMA_ES_DAE field.
mbed_official	146:f64d43ff0c18	569	#define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
mbed_official	146:f64d43ff0c18	570	#endif
mbed_official	146:f64d43ff0c18	571	//@}
mbed_official	146:f64d43ff0c18	572
mbed_official	146:f64d43ff0c18	573	/*!
mbed_official	146:f64d43ff0c18	574	* @name Register DMA_ES, field SOE[6] (RO)
mbed_official	146:f64d43ff0c18	575	*
mbed_official	146:f64d43ff0c18	576	* Values:
mbed_official	146:f64d43ff0c18	577	* - 0 - No source offset configuration error
mbed_official	146:f64d43ff0c18	578	* - 1 - The last recorded error was a configuration error detected in the
mbed_official	146:f64d43ff0c18	579	* TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
mbed_official	146:f64d43ff0c18	580	*/
mbed_official	146:f64d43ff0c18	581	//@{
mbed_official	146:f64d43ff0c18	582	#define BP_DMA_ES_SOE (6U) //!< Bit position for DMA_ES_SOE.
mbed_official	146:f64d43ff0c18	583	#define BM_DMA_ES_SOE (0x00000040U) //!< Bit mask for DMA_ES_SOE.
mbed_official	146:f64d43ff0c18	584	#define BS_DMA_ES_SOE (1U) //!< Bit field size in bits for DMA_ES_SOE.
mbed_official	146:f64d43ff0c18	585
mbed_official	146:f64d43ff0c18	586	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	587	//! @brief Read current value of the DMA_ES_SOE field.
mbed_official	146:f64d43ff0c18	588	#define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
mbed_official	146:f64d43ff0c18	589	#endif
mbed_official	146:f64d43ff0c18	590	//@}
mbed_official	146:f64d43ff0c18	591
mbed_official	146:f64d43ff0c18	592	/*!
mbed_official	146:f64d43ff0c18	593	* @name Register DMA_ES, field SAE[7] (RO)
mbed_official	146:f64d43ff0c18	594	*
mbed_official	146:f64d43ff0c18	595	* Values:
mbed_official	146:f64d43ff0c18	596	* - 0 - No source address configuration error.
mbed_official	146:f64d43ff0c18	597	* - 1 - The last recorded error was a configuration error detected in the
mbed_official	146:f64d43ff0c18	598	* TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
mbed_official	146:f64d43ff0c18	599	*/
mbed_official	146:f64d43ff0c18	600	//@{
mbed_official	146:f64d43ff0c18	601	#define BP_DMA_ES_SAE (7U) //!< Bit position for DMA_ES_SAE.
mbed_official	146:f64d43ff0c18	602	#define BM_DMA_ES_SAE (0x00000080U) //!< Bit mask for DMA_ES_SAE.
mbed_official	146:f64d43ff0c18	603	#define BS_DMA_ES_SAE (1U) //!< Bit field size in bits for DMA_ES_SAE.
mbed_official	146:f64d43ff0c18	604
mbed_official	146:f64d43ff0c18	605	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	606	//! @brief Read current value of the DMA_ES_SAE field.
mbed_official	146:f64d43ff0c18	607	#define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
mbed_official	146:f64d43ff0c18	608	#endif
mbed_official	146:f64d43ff0c18	609	//@}
mbed_official	146:f64d43ff0c18	610
mbed_official	146:f64d43ff0c18	611	/*!
mbed_official	146:f64d43ff0c18	612	* @name Register DMA_ES, field ERRCHN[11:8] (RO)
mbed_official	146:f64d43ff0c18	613	*
mbed_official	146:f64d43ff0c18	614	* The channel number of the last recorded error (excluding CPE errors) or last
mbed_official	146:f64d43ff0c18	615	* recorded error canceled transfer.
mbed_official	146:f64d43ff0c18	616	*/
mbed_official	146:f64d43ff0c18	617	//@{
mbed_official	146:f64d43ff0c18	618	#define BP_DMA_ES_ERRCHN (8U) //!< Bit position for DMA_ES_ERRCHN.
mbed_official	146:f64d43ff0c18	619	#define BM_DMA_ES_ERRCHN (0x00000F00U) //!< Bit mask for DMA_ES_ERRCHN.
mbed_official	146:f64d43ff0c18	620	#define BS_DMA_ES_ERRCHN (4U) //!< Bit field size in bits for DMA_ES_ERRCHN.
mbed_official	146:f64d43ff0c18	621
mbed_official	146:f64d43ff0c18	622	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	623	//! @brief Read current value of the DMA_ES_ERRCHN field.
mbed_official	146:f64d43ff0c18	624	#define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
mbed_official	146:f64d43ff0c18	625	#endif
mbed_official	146:f64d43ff0c18	626	//@}
mbed_official	146:f64d43ff0c18	627
mbed_official	146:f64d43ff0c18	628	/*!
mbed_official	146:f64d43ff0c18	629	* @name Register DMA_ES, field CPE[14] (RO)
mbed_official	146:f64d43ff0c18	630	*
mbed_official	146:f64d43ff0c18	631	* Values:
mbed_official	146:f64d43ff0c18	632	* - 0 - No channel priority error
mbed_official	146:f64d43ff0c18	633	* - 1 - The last recorded error was a configuration error in the channel
mbed_official	146:f64d43ff0c18	634	* priorities . Channel priorities are not unique.
mbed_official	146:f64d43ff0c18	635	*/
mbed_official	146:f64d43ff0c18	636	//@{
mbed_official	146:f64d43ff0c18	637	#define BP_DMA_ES_CPE (14U) //!< Bit position for DMA_ES_CPE.
mbed_official	146:f64d43ff0c18	638	#define BM_DMA_ES_CPE (0x00004000U) //!< Bit mask for DMA_ES_CPE.
mbed_official	146:f64d43ff0c18	639	#define BS_DMA_ES_CPE (1U) //!< Bit field size in bits for DMA_ES_CPE.
mbed_official	146:f64d43ff0c18	640
mbed_official	146:f64d43ff0c18	641	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	642	//! @brief Read current value of the DMA_ES_CPE field.
mbed_official	146:f64d43ff0c18	643	#define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
mbed_official	146:f64d43ff0c18	644	#endif
mbed_official	146:f64d43ff0c18	645	//@}
mbed_official	146:f64d43ff0c18	646
mbed_official	146:f64d43ff0c18	647	/*!
mbed_official	146:f64d43ff0c18	648	* @name Register DMA_ES, field ECX[16] (RO)
mbed_official	146:f64d43ff0c18	649	*
mbed_official	146:f64d43ff0c18	650	* Values:
mbed_official	146:f64d43ff0c18	651	* - 0 - No canceled transfers
mbed_official	146:f64d43ff0c18	652	* - 1 - The last recorded entry was a canceled transfer by the error cancel
mbed_official	146:f64d43ff0c18	653	* transfer input
mbed_official	146:f64d43ff0c18	654	*/
mbed_official	146:f64d43ff0c18	655	//@{
mbed_official	146:f64d43ff0c18	656	#define BP_DMA_ES_ECX (16U) //!< Bit position for DMA_ES_ECX.
mbed_official	146:f64d43ff0c18	657	#define BM_DMA_ES_ECX (0x00010000U) //!< Bit mask for DMA_ES_ECX.
mbed_official	146:f64d43ff0c18	658	#define BS_DMA_ES_ECX (1U) //!< Bit field size in bits for DMA_ES_ECX.
mbed_official	146:f64d43ff0c18	659
mbed_official	146:f64d43ff0c18	660	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	661	//! @brief Read current value of the DMA_ES_ECX field.
mbed_official	146:f64d43ff0c18	662	#define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
mbed_official	146:f64d43ff0c18	663	#endif
mbed_official	146:f64d43ff0c18	664	//@}
mbed_official	146:f64d43ff0c18	665
mbed_official	146:f64d43ff0c18	666	/*!
mbed_official	146:f64d43ff0c18	667	* @name Register DMA_ES, field VLD[31] (RO)
mbed_official	146:f64d43ff0c18	668	*
mbed_official	146:f64d43ff0c18	669	* Logical OR of all ERR status bits
mbed_official	146:f64d43ff0c18	670	*
mbed_official	146:f64d43ff0c18	671	* Values:
mbed_official	146:f64d43ff0c18	672	* - 0 - No ERR bits are set
mbed_official	146:f64d43ff0c18	673	* - 1 - At least one ERR bit is set indicating a valid error exists that has
mbed_official	146:f64d43ff0c18	674	* not been cleared
mbed_official	146:f64d43ff0c18	675	*/
mbed_official	146:f64d43ff0c18	676	//@{
mbed_official	146:f64d43ff0c18	677	#define BP_DMA_ES_VLD (31U) //!< Bit position for DMA_ES_VLD.
mbed_official	146:f64d43ff0c18	678	#define BM_DMA_ES_VLD (0x80000000U) //!< Bit mask for DMA_ES_VLD.
mbed_official	146:f64d43ff0c18	679	#define BS_DMA_ES_VLD (1U) //!< Bit field size in bits for DMA_ES_VLD.
mbed_official	146:f64d43ff0c18	680
mbed_official	146:f64d43ff0c18	681	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	682	//! @brief Read current value of the DMA_ES_VLD field.
mbed_official	146:f64d43ff0c18	683	#define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
mbed_official	146:f64d43ff0c18	684	#endif
mbed_official	146:f64d43ff0c18	685	//@}
mbed_official	146:f64d43ff0c18	686
mbed_official	146:f64d43ff0c18	687	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	688	// HW_DMA_ERQ - Enable Request Register
mbed_official	146:f64d43ff0c18	689	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	690
mbed_official	146:f64d43ff0c18	691	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	692	/*!
mbed_official	146:f64d43ff0c18	693	* @brief HW_DMA_ERQ - Enable Request Register (RW)
mbed_official	146:f64d43ff0c18	694	*
mbed_official	146:f64d43ff0c18	695	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	696	*
mbed_official	146:f64d43ff0c18	697	* The ERQ register provides a bit map for the 16 implemented channels to enable
mbed_official	146:f64d43ff0c18	698	* the request signal for each channel. The state of any given channel enable is
mbed_official	146:f64d43ff0c18	699	* directly affected by writes to this register; it is also affected by writes
mbed_official	146:f64d43ff0c18	700	* to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
mbed_official	146:f64d43ff0c18	701	* for a single channel can easily be modified without needing to perform a
mbed_official	146:f64d43ff0c18	702	* read-modify-write sequence to the ERQ. DMA request input signals and this enable
mbed_official	146:f64d43ff0c18	703	* request flag must be asserted before a channel's hardware service request is
mbed_official	146:f64d43ff0c18	704	* accepted. The state of the DMA enable request flag does not affect a channel
mbed_official	146:f64d43ff0c18	705	* service request made explicitly through software or a linked channel request.
mbed_official	146:f64d43ff0c18	706	*/
mbed_official	146:f64d43ff0c18	707	typedef union _hw_dma_erq
mbed_official	146:f64d43ff0c18	708	{
mbed_official	146:f64d43ff0c18	709	uint32_t U;
mbed_official	146:f64d43ff0c18	710	struct _hw_dma_erq_bitfields
mbed_official	146:f64d43ff0c18	711	{
mbed_official	146:f64d43ff0c18	712	uint32_t ERQ0 : 1; //!< [0] Enable DMA Request 0
mbed_official	146:f64d43ff0c18	713	uint32_t ERQ1 : 1; //!< [1] Enable DMA Request 1
mbed_official	146:f64d43ff0c18	714	uint32_t ERQ2 : 1; //!< [2] Enable DMA Request 2
mbed_official	146:f64d43ff0c18	715	uint32_t ERQ3 : 1; //!< [3] Enable DMA Request 3
mbed_official	146:f64d43ff0c18	716	uint32_t ERQ4 : 1; //!< [4] Enable DMA Request 4
mbed_official	146:f64d43ff0c18	717	uint32_t ERQ5 : 1; //!< [5] Enable DMA Request 5
mbed_official	146:f64d43ff0c18	718	uint32_t ERQ6 : 1; //!< [6] Enable DMA Request 6
mbed_official	146:f64d43ff0c18	719	uint32_t ERQ7 : 1; //!< [7] Enable DMA Request 7
mbed_official	146:f64d43ff0c18	720	uint32_t ERQ8 : 1; //!< [8] Enable DMA Request 8
mbed_official	146:f64d43ff0c18	721	uint32_t ERQ9 : 1; //!< [9] Enable DMA Request 9
mbed_official	146:f64d43ff0c18	722	uint32_t ERQ10 : 1; //!< [10] Enable DMA Request 10
mbed_official	146:f64d43ff0c18	723	uint32_t ERQ11 : 1; //!< [11] Enable DMA Request 11
mbed_official	146:f64d43ff0c18	724	uint32_t ERQ12 : 1; //!< [12] Enable DMA Request 12
mbed_official	146:f64d43ff0c18	725	uint32_t ERQ13 : 1; //!< [13] Enable DMA Request 13
mbed_official	146:f64d43ff0c18	726	uint32_t ERQ14 : 1; //!< [14] Enable DMA Request 14
mbed_official	146:f64d43ff0c18	727	uint32_t ERQ15 : 1; //!< [15] Enable DMA Request 15
mbed_official	146:f64d43ff0c18	728	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	729	} B;
mbed_official	146:f64d43ff0c18	730	} hw_dma_erq_t;
mbed_official	146:f64d43ff0c18	731	#endif
mbed_official	146:f64d43ff0c18	732
mbed_official	146:f64d43ff0c18	733	/*!
mbed_official	146:f64d43ff0c18	734	* @name Constants and macros for entire DMA_ERQ register
mbed_official	146:f64d43ff0c18	735	*/
mbed_official	146:f64d43ff0c18	736	//@{
mbed_official	146:f64d43ff0c18	737	#define HW_DMA_ERQ_ADDR(x) (REGS_DMA_BASE(x) + 0xCU)
mbed_official	146:f64d43ff0c18	738
mbed_official	146:f64d43ff0c18	739	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	740	#define HW_DMA_ERQ(x) ((__IO hw_dma_erq_t ) HW_DMA_ERQ_ADDR(x))
mbed_official	146:f64d43ff0c18	741	#define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
mbed_official	146:f64d43ff0c18	742	#define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
mbed_official	146:f64d43ff0c18	743	#define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	744	#define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	745	#define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	746	#endif
mbed_official	146:f64d43ff0c18	747	//@}
mbed_official	146:f64d43ff0c18	748
mbed_official	146:f64d43ff0c18	749	/*
mbed_official	146:f64d43ff0c18	750	* Constants & macros for individual DMA_ERQ bitfields
mbed_official	146:f64d43ff0c18	751	*/
mbed_official	146:f64d43ff0c18	752
mbed_official	146:f64d43ff0c18	753	/*!
mbed_official	146:f64d43ff0c18	754	* @name Register DMA_ERQ, field ERQ0[0] (RW)
mbed_official	146:f64d43ff0c18	755	*
mbed_official	146:f64d43ff0c18	756	* Values:
mbed_official	146:f64d43ff0c18	757	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	758	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	759	*/
mbed_official	146:f64d43ff0c18	760	//@{
mbed_official	146:f64d43ff0c18	761	#define BP_DMA_ERQ_ERQ0 (0U) //!< Bit position for DMA_ERQ_ERQ0.
mbed_official	146:f64d43ff0c18	762	#define BM_DMA_ERQ_ERQ0 (0x00000001U) //!< Bit mask for DMA_ERQ_ERQ0.
mbed_official	146:f64d43ff0c18	763	#define BS_DMA_ERQ_ERQ0 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ0.
mbed_official	146:f64d43ff0c18	764
mbed_official	146:f64d43ff0c18	765	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	766	//! @brief Read current value of the DMA_ERQ_ERQ0 field.
mbed_official	146:f64d43ff0c18	767	#define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
mbed_official	146:f64d43ff0c18	768	#endif
mbed_official	146:f64d43ff0c18	769
mbed_official	146:f64d43ff0c18	770	//! @brief Format value for bitfield DMA_ERQ_ERQ0.
mbed_official	146:f64d43ff0c18	771	#define BF_DMA_ERQ_ERQ0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ0), uint32_t) & BM_DMA_ERQ_ERQ0)
mbed_official	146:f64d43ff0c18	772
mbed_official	146:f64d43ff0c18	773	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	774	//! @brief Set the ERQ0 field to a new value.
mbed_official	146:f64d43ff0c18	775	#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
mbed_official	146:f64d43ff0c18	776	#endif
mbed_official	146:f64d43ff0c18	777	//@}
mbed_official	146:f64d43ff0c18	778
mbed_official	146:f64d43ff0c18	779	/*!
mbed_official	146:f64d43ff0c18	780	* @name Register DMA_ERQ, field ERQ1[1] (RW)
mbed_official	146:f64d43ff0c18	781	*
mbed_official	146:f64d43ff0c18	782	* Values:
mbed_official	146:f64d43ff0c18	783	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	784	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	785	*/
mbed_official	146:f64d43ff0c18	786	//@{
mbed_official	146:f64d43ff0c18	787	#define BP_DMA_ERQ_ERQ1 (1U) //!< Bit position for DMA_ERQ_ERQ1.
mbed_official	146:f64d43ff0c18	788	#define BM_DMA_ERQ_ERQ1 (0x00000002U) //!< Bit mask for DMA_ERQ_ERQ1.
mbed_official	146:f64d43ff0c18	789	#define BS_DMA_ERQ_ERQ1 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ1.
mbed_official	146:f64d43ff0c18	790
mbed_official	146:f64d43ff0c18	791	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	792	//! @brief Read current value of the DMA_ERQ_ERQ1 field.
mbed_official	146:f64d43ff0c18	793	#define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
mbed_official	146:f64d43ff0c18	794	#endif
mbed_official	146:f64d43ff0c18	795
mbed_official	146:f64d43ff0c18	796	//! @brief Format value for bitfield DMA_ERQ_ERQ1.
mbed_official	146:f64d43ff0c18	797	#define BF_DMA_ERQ_ERQ1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ1), uint32_t) & BM_DMA_ERQ_ERQ1)
mbed_official	146:f64d43ff0c18	798
mbed_official	146:f64d43ff0c18	799	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	800	//! @brief Set the ERQ1 field to a new value.
mbed_official	146:f64d43ff0c18	801	#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
mbed_official	146:f64d43ff0c18	802	#endif
mbed_official	146:f64d43ff0c18	803	//@}
mbed_official	146:f64d43ff0c18	804
mbed_official	146:f64d43ff0c18	805	/*!
mbed_official	146:f64d43ff0c18	806	* @name Register DMA_ERQ, field ERQ2[2] (RW)
mbed_official	146:f64d43ff0c18	807	*
mbed_official	146:f64d43ff0c18	808	* Values:
mbed_official	146:f64d43ff0c18	809	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	810	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	811	*/
mbed_official	146:f64d43ff0c18	812	//@{
mbed_official	146:f64d43ff0c18	813	#define BP_DMA_ERQ_ERQ2 (2U) //!< Bit position for DMA_ERQ_ERQ2.
mbed_official	146:f64d43ff0c18	814	#define BM_DMA_ERQ_ERQ2 (0x00000004U) //!< Bit mask for DMA_ERQ_ERQ2.
mbed_official	146:f64d43ff0c18	815	#define BS_DMA_ERQ_ERQ2 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ2.
mbed_official	146:f64d43ff0c18	816
mbed_official	146:f64d43ff0c18	817	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	818	//! @brief Read current value of the DMA_ERQ_ERQ2 field.
mbed_official	146:f64d43ff0c18	819	#define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
mbed_official	146:f64d43ff0c18	820	#endif
mbed_official	146:f64d43ff0c18	821
mbed_official	146:f64d43ff0c18	822	//! @brief Format value for bitfield DMA_ERQ_ERQ2.
mbed_official	146:f64d43ff0c18	823	#define BF_DMA_ERQ_ERQ2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ2), uint32_t) & BM_DMA_ERQ_ERQ2)
mbed_official	146:f64d43ff0c18	824
mbed_official	146:f64d43ff0c18	825	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	826	//! @brief Set the ERQ2 field to a new value.
mbed_official	146:f64d43ff0c18	827	#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
mbed_official	146:f64d43ff0c18	828	#endif
mbed_official	146:f64d43ff0c18	829	//@}
mbed_official	146:f64d43ff0c18	830
mbed_official	146:f64d43ff0c18	831	/*!
mbed_official	146:f64d43ff0c18	832	* @name Register DMA_ERQ, field ERQ3[3] (RW)
mbed_official	146:f64d43ff0c18	833	*
mbed_official	146:f64d43ff0c18	834	* Values:
mbed_official	146:f64d43ff0c18	835	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	836	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	837	*/
mbed_official	146:f64d43ff0c18	838	//@{
mbed_official	146:f64d43ff0c18	839	#define BP_DMA_ERQ_ERQ3 (3U) //!< Bit position for DMA_ERQ_ERQ3.
mbed_official	146:f64d43ff0c18	840	#define BM_DMA_ERQ_ERQ3 (0x00000008U) //!< Bit mask for DMA_ERQ_ERQ3.
mbed_official	146:f64d43ff0c18	841	#define BS_DMA_ERQ_ERQ3 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ3.
mbed_official	146:f64d43ff0c18	842
mbed_official	146:f64d43ff0c18	843	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	844	//! @brief Read current value of the DMA_ERQ_ERQ3 field.
mbed_official	146:f64d43ff0c18	845	#define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
mbed_official	146:f64d43ff0c18	846	#endif
mbed_official	146:f64d43ff0c18	847
mbed_official	146:f64d43ff0c18	848	//! @brief Format value for bitfield DMA_ERQ_ERQ3.
mbed_official	146:f64d43ff0c18	849	#define BF_DMA_ERQ_ERQ3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ3), uint32_t) & BM_DMA_ERQ_ERQ3)
mbed_official	146:f64d43ff0c18	850
mbed_official	146:f64d43ff0c18	851	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	852	//! @brief Set the ERQ3 field to a new value.
mbed_official	146:f64d43ff0c18	853	#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
mbed_official	146:f64d43ff0c18	854	#endif
mbed_official	146:f64d43ff0c18	855	//@}
mbed_official	146:f64d43ff0c18	856
mbed_official	146:f64d43ff0c18	857	/*!
mbed_official	146:f64d43ff0c18	858	* @name Register DMA_ERQ, field ERQ4[4] (RW)
mbed_official	146:f64d43ff0c18	859	*
mbed_official	146:f64d43ff0c18	860	* Values:
mbed_official	146:f64d43ff0c18	861	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	862	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	863	*/
mbed_official	146:f64d43ff0c18	864	//@{
mbed_official	146:f64d43ff0c18	865	#define BP_DMA_ERQ_ERQ4 (4U) //!< Bit position for DMA_ERQ_ERQ4.
mbed_official	146:f64d43ff0c18	866	#define BM_DMA_ERQ_ERQ4 (0x00000010U) //!< Bit mask for DMA_ERQ_ERQ4.
mbed_official	146:f64d43ff0c18	867	#define BS_DMA_ERQ_ERQ4 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ4.
mbed_official	146:f64d43ff0c18	868
mbed_official	146:f64d43ff0c18	869	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	870	//! @brief Read current value of the DMA_ERQ_ERQ4 field.
mbed_official	146:f64d43ff0c18	871	#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
mbed_official	146:f64d43ff0c18	872	#endif
mbed_official	146:f64d43ff0c18	873
mbed_official	146:f64d43ff0c18	874	//! @brief Format value for bitfield DMA_ERQ_ERQ4.
mbed_official	146:f64d43ff0c18	875	#define BF_DMA_ERQ_ERQ4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ4), uint32_t) & BM_DMA_ERQ_ERQ4)
mbed_official	146:f64d43ff0c18	876
mbed_official	146:f64d43ff0c18	877	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	878	//! @brief Set the ERQ4 field to a new value.
mbed_official	146:f64d43ff0c18	879	#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
mbed_official	146:f64d43ff0c18	880	#endif
mbed_official	146:f64d43ff0c18	881	//@}
mbed_official	146:f64d43ff0c18	882
mbed_official	146:f64d43ff0c18	883	/*!
mbed_official	146:f64d43ff0c18	884	* @name Register DMA_ERQ, field ERQ5[5] (RW)
mbed_official	146:f64d43ff0c18	885	*
mbed_official	146:f64d43ff0c18	886	* Values:
mbed_official	146:f64d43ff0c18	887	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	888	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	889	*/
mbed_official	146:f64d43ff0c18	890	//@{
mbed_official	146:f64d43ff0c18	891	#define BP_DMA_ERQ_ERQ5 (5U) //!< Bit position for DMA_ERQ_ERQ5.
mbed_official	146:f64d43ff0c18	892	#define BM_DMA_ERQ_ERQ5 (0x00000020U) //!< Bit mask for DMA_ERQ_ERQ5.
mbed_official	146:f64d43ff0c18	893	#define BS_DMA_ERQ_ERQ5 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ5.
mbed_official	146:f64d43ff0c18	894
mbed_official	146:f64d43ff0c18	895	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	896	//! @brief Read current value of the DMA_ERQ_ERQ5 field.
mbed_official	146:f64d43ff0c18	897	#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
mbed_official	146:f64d43ff0c18	898	#endif
mbed_official	146:f64d43ff0c18	899
mbed_official	146:f64d43ff0c18	900	//! @brief Format value for bitfield DMA_ERQ_ERQ5.
mbed_official	146:f64d43ff0c18	901	#define BF_DMA_ERQ_ERQ5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ5), uint32_t) & BM_DMA_ERQ_ERQ5)
mbed_official	146:f64d43ff0c18	902
mbed_official	146:f64d43ff0c18	903	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	904	//! @brief Set the ERQ5 field to a new value.
mbed_official	146:f64d43ff0c18	905	#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
mbed_official	146:f64d43ff0c18	906	#endif
mbed_official	146:f64d43ff0c18	907	//@}
mbed_official	146:f64d43ff0c18	908
mbed_official	146:f64d43ff0c18	909	/*!
mbed_official	146:f64d43ff0c18	910	* @name Register DMA_ERQ, field ERQ6[6] (RW)
mbed_official	146:f64d43ff0c18	911	*
mbed_official	146:f64d43ff0c18	912	* Values:
mbed_official	146:f64d43ff0c18	913	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	914	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	915	*/
mbed_official	146:f64d43ff0c18	916	//@{
mbed_official	146:f64d43ff0c18	917	#define BP_DMA_ERQ_ERQ6 (6U) //!< Bit position for DMA_ERQ_ERQ6.
mbed_official	146:f64d43ff0c18	918	#define BM_DMA_ERQ_ERQ6 (0x00000040U) //!< Bit mask for DMA_ERQ_ERQ6.
mbed_official	146:f64d43ff0c18	919	#define BS_DMA_ERQ_ERQ6 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ6.
mbed_official	146:f64d43ff0c18	920
mbed_official	146:f64d43ff0c18	921	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	922	//! @brief Read current value of the DMA_ERQ_ERQ6 field.
mbed_official	146:f64d43ff0c18	923	#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
mbed_official	146:f64d43ff0c18	924	#endif
mbed_official	146:f64d43ff0c18	925
mbed_official	146:f64d43ff0c18	926	//! @brief Format value for bitfield DMA_ERQ_ERQ6.
mbed_official	146:f64d43ff0c18	927	#define BF_DMA_ERQ_ERQ6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ6), uint32_t) & BM_DMA_ERQ_ERQ6)
mbed_official	146:f64d43ff0c18	928
mbed_official	146:f64d43ff0c18	929	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	930	//! @brief Set the ERQ6 field to a new value.
mbed_official	146:f64d43ff0c18	931	#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
mbed_official	146:f64d43ff0c18	932	#endif
mbed_official	146:f64d43ff0c18	933	//@}
mbed_official	146:f64d43ff0c18	934
mbed_official	146:f64d43ff0c18	935	/*!
mbed_official	146:f64d43ff0c18	936	* @name Register DMA_ERQ, field ERQ7[7] (RW)
mbed_official	146:f64d43ff0c18	937	*
mbed_official	146:f64d43ff0c18	938	* Values:
mbed_official	146:f64d43ff0c18	939	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	940	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	941	*/
mbed_official	146:f64d43ff0c18	942	//@{
mbed_official	146:f64d43ff0c18	943	#define BP_DMA_ERQ_ERQ7 (7U) //!< Bit position for DMA_ERQ_ERQ7.
mbed_official	146:f64d43ff0c18	944	#define BM_DMA_ERQ_ERQ7 (0x00000080U) //!< Bit mask for DMA_ERQ_ERQ7.
mbed_official	146:f64d43ff0c18	945	#define BS_DMA_ERQ_ERQ7 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ7.
mbed_official	146:f64d43ff0c18	946
mbed_official	146:f64d43ff0c18	947	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	948	//! @brief Read current value of the DMA_ERQ_ERQ7 field.
mbed_official	146:f64d43ff0c18	949	#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
mbed_official	146:f64d43ff0c18	950	#endif
mbed_official	146:f64d43ff0c18	951
mbed_official	146:f64d43ff0c18	952	//! @brief Format value for bitfield DMA_ERQ_ERQ7.
mbed_official	146:f64d43ff0c18	953	#define BF_DMA_ERQ_ERQ7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ7), uint32_t) & BM_DMA_ERQ_ERQ7)
mbed_official	146:f64d43ff0c18	954
mbed_official	146:f64d43ff0c18	955	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	956	//! @brief Set the ERQ7 field to a new value.
mbed_official	146:f64d43ff0c18	957	#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
mbed_official	146:f64d43ff0c18	958	#endif
mbed_official	146:f64d43ff0c18	959	//@}
mbed_official	146:f64d43ff0c18	960
mbed_official	146:f64d43ff0c18	961	/*!
mbed_official	146:f64d43ff0c18	962	* @name Register DMA_ERQ, field ERQ8[8] (RW)
mbed_official	146:f64d43ff0c18	963	*
mbed_official	146:f64d43ff0c18	964	* Values:
mbed_official	146:f64d43ff0c18	965	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	966	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	967	*/
mbed_official	146:f64d43ff0c18	968	//@{
mbed_official	146:f64d43ff0c18	969	#define BP_DMA_ERQ_ERQ8 (8U) //!< Bit position for DMA_ERQ_ERQ8.
mbed_official	146:f64d43ff0c18	970	#define BM_DMA_ERQ_ERQ8 (0x00000100U) //!< Bit mask for DMA_ERQ_ERQ8.
mbed_official	146:f64d43ff0c18	971	#define BS_DMA_ERQ_ERQ8 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ8.
mbed_official	146:f64d43ff0c18	972
mbed_official	146:f64d43ff0c18	973	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	974	//! @brief Read current value of the DMA_ERQ_ERQ8 field.
mbed_official	146:f64d43ff0c18	975	#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
mbed_official	146:f64d43ff0c18	976	#endif
mbed_official	146:f64d43ff0c18	977
mbed_official	146:f64d43ff0c18	978	//! @brief Format value for bitfield DMA_ERQ_ERQ8.
mbed_official	146:f64d43ff0c18	979	#define BF_DMA_ERQ_ERQ8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ8), uint32_t) & BM_DMA_ERQ_ERQ8)
mbed_official	146:f64d43ff0c18	980
mbed_official	146:f64d43ff0c18	981	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	982	//! @brief Set the ERQ8 field to a new value.
mbed_official	146:f64d43ff0c18	983	#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
mbed_official	146:f64d43ff0c18	984	#endif
mbed_official	146:f64d43ff0c18	985	//@}
mbed_official	146:f64d43ff0c18	986
mbed_official	146:f64d43ff0c18	987	/*!
mbed_official	146:f64d43ff0c18	988	* @name Register DMA_ERQ, field ERQ9[9] (RW)
mbed_official	146:f64d43ff0c18	989	*
mbed_official	146:f64d43ff0c18	990	* Values:
mbed_official	146:f64d43ff0c18	991	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	992	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	993	*/
mbed_official	146:f64d43ff0c18	994	//@{
mbed_official	146:f64d43ff0c18	995	#define BP_DMA_ERQ_ERQ9 (9U) //!< Bit position for DMA_ERQ_ERQ9.
mbed_official	146:f64d43ff0c18	996	#define BM_DMA_ERQ_ERQ9 (0x00000200U) //!< Bit mask for DMA_ERQ_ERQ9.
mbed_official	146:f64d43ff0c18	997	#define BS_DMA_ERQ_ERQ9 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ9.
mbed_official	146:f64d43ff0c18	998
mbed_official	146:f64d43ff0c18	999	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1000	//! @brief Read current value of the DMA_ERQ_ERQ9 field.
mbed_official	146:f64d43ff0c18	1001	#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
mbed_official	146:f64d43ff0c18	1002	#endif
mbed_official	146:f64d43ff0c18	1003
mbed_official	146:f64d43ff0c18	1004	//! @brief Format value for bitfield DMA_ERQ_ERQ9.
mbed_official	146:f64d43ff0c18	1005	#define BF_DMA_ERQ_ERQ9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ9), uint32_t) & BM_DMA_ERQ_ERQ9)
mbed_official	146:f64d43ff0c18	1006
mbed_official	146:f64d43ff0c18	1007	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1008	//! @brief Set the ERQ9 field to a new value.
mbed_official	146:f64d43ff0c18	1009	#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
mbed_official	146:f64d43ff0c18	1010	#endif
mbed_official	146:f64d43ff0c18	1011	//@}
mbed_official	146:f64d43ff0c18	1012
mbed_official	146:f64d43ff0c18	1013	/*!
mbed_official	146:f64d43ff0c18	1014	* @name Register DMA_ERQ, field ERQ10[10] (RW)
mbed_official	146:f64d43ff0c18	1015	*
mbed_official	146:f64d43ff0c18	1016	* Values:
mbed_official	146:f64d43ff0c18	1017	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	1018	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	1019	*/
mbed_official	146:f64d43ff0c18	1020	//@{
mbed_official	146:f64d43ff0c18	1021	#define BP_DMA_ERQ_ERQ10 (10U) //!< Bit position for DMA_ERQ_ERQ10.
mbed_official	146:f64d43ff0c18	1022	#define BM_DMA_ERQ_ERQ10 (0x00000400U) //!< Bit mask for DMA_ERQ_ERQ10.
mbed_official	146:f64d43ff0c18	1023	#define BS_DMA_ERQ_ERQ10 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ10.
mbed_official	146:f64d43ff0c18	1024
mbed_official	146:f64d43ff0c18	1025	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1026	//! @brief Read current value of the DMA_ERQ_ERQ10 field.
mbed_official	146:f64d43ff0c18	1027	#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
mbed_official	146:f64d43ff0c18	1028	#endif
mbed_official	146:f64d43ff0c18	1029
mbed_official	146:f64d43ff0c18	1030	//! @brief Format value for bitfield DMA_ERQ_ERQ10.
mbed_official	146:f64d43ff0c18	1031	#define BF_DMA_ERQ_ERQ10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ10), uint32_t) & BM_DMA_ERQ_ERQ10)
mbed_official	146:f64d43ff0c18	1032
mbed_official	146:f64d43ff0c18	1033	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1034	//! @brief Set the ERQ10 field to a new value.
mbed_official	146:f64d43ff0c18	1035	#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
mbed_official	146:f64d43ff0c18	1036	#endif
mbed_official	146:f64d43ff0c18	1037	//@}
mbed_official	146:f64d43ff0c18	1038
mbed_official	146:f64d43ff0c18	1039	/*!
mbed_official	146:f64d43ff0c18	1040	* @name Register DMA_ERQ, field ERQ11[11] (RW)
mbed_official	146:f64d43ff0c18	1041	*
mbed_official	146:f64d43ff0c18	1042	* Values:
mbed_official	146:f64d43ff0c18	1043	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	1044	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	1045	*/
mbed_official	146:f64d43ff0c18	1046	//@{
mbed_official	146:f64d43ff0c18	1047	#define BP_DMA_ERQ_ERQ11 (11U) //!< Bit position for DMA_ERQ_ERQ11.
mbed_official	146:f64d43ff0c18	1048	#define BM_DMA_ERQ_ERQ11 (0x00000800U) //!< Bit mask for DMA_ERQ_ERQ11.
mbed_official	146:f64d43ff0c18	1049	#define BS_DMA_ERQ_ERQ11 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ11.
mbed_official	146:f64d43ff0c18	1050
mbed_official	146:f64d43ff0c18	1051	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1052	//! @brief Read current value of the DMA_ERQ_ERQ11 field.
mbed_official	146:f64d43ff0c18	1053	#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
mbed_official	146:f64d43ff0c18	1054	#endif
mbed_official	146:f64d43ff0c18	1055
mbed_official	146:f64d43ff0c18	1056	//! @brief Format value for bitfield DMA_ERQ_ERQ11.
mbed_official	146:f64d43ff0c18	1057	#define BF_DMA_ERQ_ERQ11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ11), uint32_t) & BM_DMA_ERQ_ERQ11)
mbed_official	146:f64d43ff0c18	1058
mbed_official	146:f64d43ff0c18	1059	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1060	//! @brief Set the ERQ11 field to a new value.
mbed_official	146:f64d43ff0c18	1061	#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
mbed_official	146:f64d43ff0c18	1062	#endif
mbed_official	146:f64d43ff0c18	1063	//@}
mbed_official	146:f64d43ff0c18	1064
mbed_official	146:f64d43ff0c18	1065	/*!
mbed_official	146:f64d43ff0c18	1066	* @name Register DMA_ERQ, field ERQ12[12] (RW)
mbed_official	146:f64d43ff0c18	1067	*
mbed_official	146:f64d43ff0c18	1068	* Values:
mbed_official	146:f64d43ff0c18	1069	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	1070	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	1071	*/
mbed_official	146:f64d43ff0c18	1072	//@{
mbed_official	146:f64d43ff0c18	1073	#define BP_DMA_ERQ_ERQ12 (12U) //!< Bit position for DMA_ERQ_ERQ12.
mbed_official	146:f64d43ff0c18	1074	#define BM_DMA_ERQ_ERQ12 (0x00001000U) //!< Bit mask for DMA_ERQ_ERQ12.
mbed_official	146:f64d43ff0c18	1075	#define BS_DMA_ERQ_ERQ12 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ12.
mbed_official	146:f64d43ff0c18	1076
mbed_official	146:f64d43ff0c18	1077	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1078	//! @brief Read current value of the DMA_ERQ_ERQ12 field.
mbed_official	146:f64d43ff0c18	1079	#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
mbed_official	146:f64d43ff0c18	1080	#endif
mbed_official	146:f64d43ff0c18	1081
mbed_official	146:f64d43ff0c18	1082	//! @brief Format value for bitfield DMA_ERQ_ERQ12.
mbed_official	146:f64d43ff0c18	1083	#define BF_DMA_ERQ_ERQ12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ12), uint32_t) & BM_DMA_ERQ_ERQ12)
mbed_official	146:f64d43ff0c18	1084
mbed_official	146:f64d43ff0c18	1085	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1086	//! @brief Set the ERQ12 field to a new value.
mbed_official	146:f64d43ff0c18	1087	#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
mbed_official	146:f64d43ff0c18	1088	#endif
mbed_official	146:f64d43ff0c18	1089	//@}
mbed_official	146:f64d43ff0c18	1090
mbed_official	146:f64d43ff0c18	1091	/*!
mbed_official	146:f64d43ff0c18	1092	* @name Register DMA_ERQ, field ERQ13[13] (RW)
mbed_official	146:f64d43ff0c18	1093	*
mbed_official	146:f64d43ff0c18	1094	* Values:
mbed_official	146:f64d43ff0c18	1095	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	1096	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	1097	*/
mbed_official	146:f64d43ff0c18	1098	//@{
mbed_official	146:f64d43ff0c18	1099	#define BP_DMA_ERQ_ERQ13 (13U) //!< Bit position for DMA_ERQ_ERQ13.
mbed_official	146:f64d43ff0c18	1100	#define BM_DMA_ERQ_ERQ13 (0x00002000U) //!< Bit mask for DMA_ERQ_ERQ13.
mbed_official	146:f64d43ff0c18	1101	#define BS_DMA_ERQ_ERQ13 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ13.
mbed_official	146:f64d43ff0c18	1102
mbed_official	146:f64d43ff0c18	1103	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1104	//! @brief Read current value of the DMA_ERQ_ERQ13 field.
mbed_official	146:f64d43ff0c18	1105	#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
mbed_official	146:f64d43ff0c18	1106	#endif
mbed_official	146:f64d43ff0c18	1107
mbed_official	146:f64d43ff0c18	1108	//! @brief Format value for bitfield DMA_ERQ_ERQ13.
mbed_official	146:f64d43ff0c18	1109	#define BF_DMA_ERQ_ERQ13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ13), uint32_t) & BM_DMA_ERQ_ERQ13)
mbed_official	146:f64d43ff0c18	1110
mbed_official	146:f64d43ff0c18	1111	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1112	//! @brief Set the ERQ13 field to a new value.
mbed_official	146:f64d43ff0c18	1113	#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
mbed_official	146:f64d43ff0c18	1114	#endif
mbed_official	146:f64d43ff0c18	1115	//@}
mbed_official	146:f64d43ff0c18	1116
mbed_official	146:f64d43ff0c18	1117	/*!
mbed_official	146:f64d43ff0c18	1118	* @name Register DMA_ERQ, field ERQ14[14] (RW)
mbed_official	146:f64d43ff0c18	1119	*
mbed_official	146:f64d43ff0c18	1120	* Values:
mbed_official	146:f64d43ff0c18	1121	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	1122	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	1123	*/
mbed_official	146:f64d43ff0c18	1124	//@{
mbed_official	146:f64d43ff0c18	1125	#define BP_DMA_ERQ_ERQ14 (14U) //!< Bit position for DMA_ERQ_ERQ14.
mbed_official	146:f64d43ff0c18	1126	#define BM_DMA_ERQ_ERQ14 (0x00004000U) //!< Bit mask for DMA_ERQ_ERQ14.
mbed_official	146:f64d43ff0c18	1127	#define BS_DMA_ERQ_ERQ14 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ14.
mbed_official	146:f64d43ff0c18	1128
mbed_official	146:f64d43ff0c18	1129	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1130	//! @brief Read current value of the DMA_ERQ_ERQ14 field.
mbed_official	146:f64d43ff0c18	1131	#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
mbed_official	146:f64d43ff0c18	1132	#endif
mbed_official	146:f64d43ff0c18	1133
mbed_official	146:f64d43ff0c18	1134	//! @brief Format value for bitfield DMA_ERQ_ERQ14.
mbed_official	146:f64d43ff0c18	1135	#define BF_DMA_ERQ_ERQ14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ14), uint32_t) & BM_DMA_ERQ_ERQ14)
mbed_official	146:f64d43ff0c18	1136
mbed_official	146:f64d43ff0c18	1137	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1138	//! @brief Set the ERQ14 field to a new value.
mbed_official	146:f64d43ff0c18	1139	#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
mbed_official	146:f64d43ff0c18	1140	#endif
mbed_official	146:f64d43ff0c18	1141	//@}
mbed_official	146:f64d43ff0c18	1142
mbed_official	146:f64d43ff0c18	1143	/*!
mbed_official	146:f64d43ff0c18	1144	* @name Register DMA_ERQ, field ERQ15[15] (RW)
mbed_official	146:f64d43ff0c18	1145	*
mbed_official	146:f64d43ff0c18	1146	* Values:
mbed_official	146:f64d43ff0c18	1147	* - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official	146:f64d43ff0c18	1148	* - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official	146:f64d43ff0c18	1149	*/
mbed_official	146:f64d43ff0c18	1150	//@{
mbed_official	146:f64d43ff0c18	1151	#define BP_DMA_ERQ_ERQ15 (15U) //!< Bit position for DMA_ERQ_ERQ15.
mbed_official	146:f64d43ff0c18	1152	#define BM_DMA_ERQ_ERQ15 (0x00008000U) //!< Bit mask for DMA_ERQ_ERQ15.
mbed_official	146:f64d43ff0c18	1153	#define BS_DMA_ERQ_ERQ15 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ15.
mbed_official	146:f64d43ff0c18	1154
mbed_official	146:f64d43ff0c18	1155	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1156	//! @brief Read current value of the DMA_ERQ_ERQ15 field.
mbed_official	146:f64d43ff0c18	1157	#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
mbed_official	146:f64d43ff0c18	1158	#endif
mbed_official	146:f64d43ff0c18	1159
mbed_official	146:f64d43ff0c18	1160	//! @brief Format value for bitfield DMA_ERQ_ERQ15.
mbed_official	146:f64d43ff0c18	1161	#define BF_DMA_ERQ_ERQ15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ15), uint32_t) & BM_DMA_ERQ_ERQ15)
mbed_official	146:f64d43ff0c18	1162
mbed_official	146:f64d43ff0c18	1163	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1164	//! @brief Set the ERQ15 field to a new value.
mbed_official	146:f64d43ff0c18	1165	#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
mbed_official	146:f64d43ff0c18	1166	#endif
mbed_official	146:f64d43ff0c18	1167	//@}
mbed_official	146:f64d43ff0c18	1168
mbed_official	146:f64d43ff0c18	1169	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1170	// HW_DMA_EEI - Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	1171	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1172
mbed_official	146:f64d43ff0c18	1173	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1174	/*!
mbed_official	146:f64d43ff0c18	1175	* @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
mbed_official	146:f64d43ff0c18	1176	*
mbed_official	146:f64d43ff0c18	1177	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1178	*
mbed_official	146:f64d43ff0c18	1179	* The EEI register provides a bit map for the 16 channels to enable the error
mbed_official	146:f64d43ff0c18	1180	* interrupt signal for each channel. The state of any given channel's error
mbed_official	146:f64d43ff0c18	1181	* interrupt enable is directly affected by writes to this register; it is also
mbed_official	146:f64d43ff0c18	1182	* affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
mbed_official	146:f64d43ff0c18	1183	* interrupt enable for a single channel can easily be modified without the need to
mbed_official	146:f64d43ff0c18	1184	* perform a read-modify-write sequence to the EEI register. The DMA error
mbed_official	146:f64d43ff0c18	1185	* indicator and the error interrupt enable flag must be asserted before an error
mbed_official	146:f64d43ff0c18	1186	* interrupt request for a given channel is asserted to the interrupt controller.
mbed_official	146:f64d43ff0c18	1187	*/
mbed_official	146:f64d43ff0c18	1188	typedef union _hw_dma_eei
mbed_official	146:f64d43ff0c18	1189	{
mbed_official	146:f64d43ff0c18	1190	uint32_t U;
mbed_official	146:f64d43ff0c18	1191	struct _hw_dma_eei_bitfields
mbed_official	146:f64d43ff0c18	1192	{
mbed_official	146:f64d43ff0c18	1193	uint32_t EEI0 : 1; //!< [0] Enable Error Interrupt 0
mbed_official	146:f64d43ff0c18	1194	uint32_t EEI1 : 1; //!< [1] Enable Error Interrupt 1
mbed_official	146:f64d43ff0c18	1195	uint32_t EEI2 : 1; //!< [2] Enable Error Interrupt 2
mbed_official	146:f64d43ff0c18	1196	uint32_t EEI3 : 1; //!< [3] Enable Error Interrupt 3
mbed_official	146:f64d43ff0c18	1197	uint32_t EEI4 : 1; //!< [4] Enable Error Interrupt 4
mbed_official	146:f64d43ff0c18	1198	uint32_t EEI5 : 1; //!< [5] Enable Error Interrupt 5
mbed_official	146:f64d43ff0c18	1199	uint32_t EEI6 : 1; //!< [6] Enable Error Interrupt 6
mbed_official	146:f64d43ff0c18	1200	uint32_t EEI7 : 1; //!< [7] Enable Error Interrupt 7
mbed_official	146:f64d43ff0c18	1201	uint32_t EEI8 : 1; //!< [8] Enable Error Interrupt 8
mbed_official	146:f64d43ff0c18	1202	uint32_t EEI9 : 1; //!< [9] Enable Error Interrupt 9
mbed_official	146:f64d43ff0c18	1203	uint32_t EEI10 : 1; //!< [10] Enable Error Interrupt 10
mbed_official	146:f64d43ff0c18	1204	uint32_t EEI11 : 1; //!< [11] Enable Error Interrupt 11
mbed_official	146:f64d43ff0c18	1205	uint32_t EEI12 : 1; //!< [12] Enable Error Interrupt 12
mbed_official	146:f64d43ff0c18	1206	uint32_t EEI13 : 1; //!< [13] Enable Error Interrupt 13
mbed_official	146:f64d43ff0c18	1207	uint32_t EEI14 : 1; //!< [14] Enable Error Interrupt 14
mbed_official	146:f64d43ff0c18	1208	uint32_t EEI15 : 1; //!< [15] Enable Error Interrupt 15
mbed_official	146:f64d43ff0c18	1209	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	1210	} B;
mbed_official	146:f64d43ff0c18	1211	} hw_dma_eei_t;
mbed_official	146:f64d43ff0c18	1212	#endif
mbed_official	146:f64d43ff0c18	1213
mbed_official	146:f64d43ff0c18	1214	/*!
mbed_official	146:f64d43ff0c18	1215	* @name Constants and macros for entire DMA_EEI register
mbed_official	146:f64d43ff0c18	1216	*/
mbed_official	146:f64d43ff0c18	1217	//@{
mbed_official	146:f64d43ff0c18	1218	#define HW_DMA_EEI_ADDR(x) (REGS_DMA_BASE(x) + 0x14U)
mbed_official	146:f64d43ff0c18	1219
mbed_official	146:f64d43ff0c18	1220	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1221	#define HW_DMA_EEI(x) ((__IO hw_dma_eei_t ) HW_DMA_EEI_ADDR(x))
mbed_official	146:f64d43ff0c18	1222	#define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
mbed_official	146:f64d43ff0c18	1223	#define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
mbed_official	146:f64d43ff0c18	1224	#define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1225	#define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1226	#define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1227	#endif
mbed_official	146:f64d43ff0c18	1228	//@}
mbed_official	146:f64d43ff0c18	1229
mbed_official	146:f64d43ff0c18	1230	/*
mbed_official	146:f64d43ff0c18	1231	* Constants & macros for individual DMA_EEI bitfields
mbed_official	146:f64d43ff0c18	1232	*/
mbed_official	146:f64d43ff0c18	1233
mbed_official	146:f64d43ff0c18	1234	/*!
mbed_official	146:f64d43ff0c18	1235	* @name Register DMA_EEI, field EEI0[0] (RW)
mbed_official	146:f64d43ff0c18	1236	*
mbed_official	146:f64d43ff0c18	1237	* Values:
mbed_official	146:f64d43ff0c18	1238	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1239	* interrupt
mbed_official	146:f64d43ff0c18	1240	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1241	* an error interrupt request
mbed_official	146:f64d43ff0c18	1242	*/
mbed_official	146:f64d43ff0c18	1243	//@{
mbed_official	146:f64d43ff0c18	1244	#define BP_DMA_EEI_EEI0 (0U) //!< Bit position for DMA_EEI_EEI0.
mbed_official	146:f64d43ff0c18	1245	#define BM_DMA_EEI_EEI0 (0x00000001U) //!< Bit mask for DMA_EEI_EEI0.
mbed_official	146:f64d43ff0c18	1246	#define BS_DMA_EEI_EEI0 (1U) //!< Bit field size in bits for DMA_EEI_EEI0.
mbed_official	146:f64d43ff0c18	1247
mbed_official	146:f64d43ff0c18	1248	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1249	//! @brief Read current value of the DMA_EEI_EEI0 field.
mbed_official	146:f64d43ff0c18	1250	#define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
mbed_official	146:f64d43ff0c18	1251	#endif
mbed_official	146:f64d43ff0c18	1252
mbed_official	146:f64d43ff0c18	1253	//! @brief Format value for bitfield DMA_EEI_EEI0.
mbed_official	146:f64d43ff0c18	1254	#define BF_DMA_EEI_EEI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI0), uint32_t) & BM_DMA_EEI_EEI0)
mbed_official	146:f64d43ff0c18	1255
mbed_official	146:f64d43ff0c18	1256	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1257	//! @brief Set the EEI0 field to a new value.
mbed_official	146:f64d43ff0c18	1258	#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
mbed_official	146:f64d43ff0c18	1259	#endif
mbed_official	146:f64d43ff0c18	1260	//@}
mbed_official	146:f64d43ff0c18	1261
mbed_official	146:f64d43ff0c18	1262	/*!
mbed_official	146:f64d43ff0c18	1263	* @name Register DMA_EEI, field EEI1[1] (RW)
mbed_official	146:f64d43ff0c18	1264	*
mbed_official	146:f64d43ff0c18	1265	* Values:
mbed_official	146:f64d43ff0c18	1266	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1267	* interrupt
mbed_official	146:f64d43ff0c18	1268	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1269	* an error interrupt request
mbed_official	146:f64d43ff0c18	1270	*/
mbed_official	146:f64d43ff0c18	1271	//@{
mbed_official	146:f64d43ff0c18	1272	#define BP_DMA_EEI_EEI1 (1U) //!< Bit position for DMA_EEI_EEI1.
mbed_official	146:f64d43ff0c18	1273	#define BM_DMA_EEI_EEI1 (0x00000002U) //!< Bit mask for DMA_EEI_EEI1.
mbed_official	146:f64d43ff0c18	1274	#define BS_DMA_EEI_EEI1 (1U) //!< Bit field size in bits for DMA_EEI_EEI1.
mbed_official	146:f64d43ff0c18	1275
mbed_official	146:f64d43ff0c18	1276	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1277	//! @brief Read current value of the DMA_EEI_EEI1 field.
mbed_official	146:f64d43ff0c18	1278	#define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
mbed_official	146:f64d43ff0c18	1279	#endif
mbed_official	146:f64d43ff0c18	1280
mbed_official	146:f64d43ff0c18	1281	//! @brief Format value for bitfield DMA_EEI_EEI1.
mbed_official	146:f64d43ff0c18	1282	#define BF_DMA_EEI_EEI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI1), uint32_t) & BM_DMA_EEI_EEI1)
mbed_official	146:f64d43ff0c18	1283
mbed_official	146:f64d43ff0c18	1284	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1285	//! @brief Set the EEI1 field to a new value.
mbed_official	146:f64d43ff0c18	1286	#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
mbed_official	146:f64d43ff0c18	1287	#endif
mbed_official	146:f64d43ff0c18	1288	//@}
mbed_official	146:f64d43ff0c18	1289
mbed_official	146:f64d43ff0c18	1290	/*!
mbed_official	146:f64d43ff0c18	1291	* @name Register DMA_EEI, field EEI2[2] (RW)
mbed_official	146:f64d43ff0c18	1292	*
mbed_official	146:f64d43ff0c18	1293	* Values:
mbed_official	146:f64d43ff0c18	1294	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1295	* interrupt
mbed_official	146:f64d43ff0c18	1296	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1297	* an error interrupt request
mbed_official	146:f64d43ff0c18	1298	*/
mbed_official	146:f64d43ff0c18	1299	//@{
mbed_official	146:f64d43ff0c18	1300	#define BP_DMA_EEI_EEI2 (2U) //!< Bit position for DMA_EEI_EEI2.
mbed_official	146:f64d43ff0c18	1301	#define BM_DMA_EEI_EEI2 (0x00000004U) //!< Bit mask for DMA_EEI_EEI2.
mbed_official	146:f64d43ff0c18	1302	#define BS_DMA_EEI_EEI2 (1U) //!< Bit field size in bits for DMA_EEI_EEI2.
mbed_official	146:f64d43ff0c18	1303
mbed_official	146:f64d43ff0c18	1304	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1305	//! @brief Read current value of the DMA_EEI_EEI2 field.
mbed_official	146:f64d43ff0c18	1306	#define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
mbed_official	146:f64d43ff0c18	1307	#endif
mbed_official	146:f64d43ff0c18	1308
mbed_official	146:f64d43ff0c18	1309	//! @brief Format value for bitfield DMA_EEI_EEI2.
mbed_official	146:f64d43ff0c18	1310	#define BF_DMA_EEI_EEI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI2), uint32_t) & BM_DMA_EEI_EEI2)
mbed_official	146:f64d43ff0c18	1311
mbed_official	146:f64d43ff0c18	1312	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1313	//! @brief Set the EEI2 field to a new value.
mbed_official	146:f64d43ff0c18	1314	#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
mbed_official	146:f64d43ff0c18	1315	#endif
mbed_official	146:f64d43ff0c18	1316	//@}
mbed_official	146:f64d43ff0c18	1317
mbed_official	146:f64d43ff0c18	1318	/*!
mbed_official	146:f64d43ff0c18	1319	* @name Register DMA_EEI, field EEI3[3] (RW)
mbed_official	146:f64d43ff0c18	1320	*
mbed_official	146:f64d43ff0c18	1321	* Values:
mbed_official	146:f64d43ff0c18	1322	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1323	* interrupt
mbed_official	146:f64d43ff0c18	1324	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1325	* an error interrupt request
mbed_official	146:f64d43ff0c18	1326	*/
mbed_official	146:f64d43ff0c18	1327	//@{
mbed_official	146:f64d43ff0c18	1328	#define BP_DMA_EEI_EEI3 (3U) //!< Bit position for DMA_EEI_EEI3.
mbed_official	146:f64d43ff0c18	1329	#define BM_DMA_EEI_EEI3 (0x00000008U) //!< Bit mask for DMA_EEI_EEI3.
mbed_official	146:f64d43ff0c18	1330	#define BS_DMA_EEI_EEI3 (1U) //!< Bit field size in bits for DMA_EEI_EEI3.
mbed_official	146:f64d43ff0c18	1331
mbed_official	146:f64d43ff0c18	1332	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1333	//! @brief Read current value of the DMA_EEI_EEI3 field.
mbed_official	146:f64d43ff0c18	1334	#define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
mbed_official	146:f64d43ff0c18	1335	#endif
mbed_official	146:f64d43ff0c18	1336
mbed_official	146:f64d43ff0c18	1337	//! @brief Format value for bitfield DMA_EEI_EEI3.
mbed_official	146:f64d43ff0c18	1338	#define BF_DMA_EEI_EEI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI3), uint32_t) & BM_DMA_EEI_EEI3)
mbed_official	146:f64d43ff0c18	1339
mbed_official	146:f64d43ff0c18	1340	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1341	//! @brief Set the EEI3 field to a new value.
mbed_official	146:f64d43ff0c18	1342	#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
mbed_official	146:f64d43ff0c18	1343	#endif
mbed_official	146:f64d43ff0c18	1344	//@}
mbed_official	146:f64d43ff0c18	1345
mbed_official	146:f64d43ff0c18	1346	/*!
mbed_official	146:f64d43ff0c18	1347	* @name Register DMA_EEI, field EEI4[4] (RW)
mbed_official	146:f64d43ff0c18	1348	*
mbed_official	146:f64d43ff0c18	1349	* Values:
mbed_official	146:f64d43ff0c18	1350	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1351	* interrupt
mbed_official	146:f64d43ff0c18	1352	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1353	* an error interrupt request
mbed_official	146:f64d43ff0c18	1354	*/
mbed_official	146:f64d43ff0c18	1355	//@{
mbed_official	146:f64d43ff0c18	1356	#define BP_DMA_EEI_EEI4 (4U) //!< Bit position for DMA_EEI_EEI4.
mbed_official	146:f64d43ff0c18	1357	#define BM_DMA_EEI_EEI4 (0x00000010U) //!< Bit mask for DMA_EEI_EEI4.
mbed_official	146:f64d43ff0c18	1358	#define BS_DMA_EEI_EEI4 (1U) //!< Bit field size in bits for DMA_EEI_EEI4.
mbed_official	146:f64d43ff0c18	1359
mbed_official	146:f64d43ff0c18	1360	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1361	//! @brief Read current value of the DMA_EEI_EEI4 field.
mbed_official	146:f64d43ff0c18	1362	#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
mbed_official	146:f64d43ff0c18	1363	#endif
mbed_official	146:f64d43ff0c18	1364
mbed_official	146:f64d43ff0c18	1365	//! @brief Format value for bitfield DMA_EEI_EEI4.
mbed_official	146:f64d43ff0c18	1366	#define BF_DMA_EEI_EEI4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI4), uint32_t) & BM_DMA_EEI_EEI4)
mbed_official	146:f64d43ff0c18	1367
mbed_official	146:f64d43ff0c18	1368	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1369	//! @brief Set the EEI4 field to a new value.
mbed_official	146:f64d43ff0c18	1370	#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
mbed_official	146:f64d43ff0c18	1371	#endif
mbed_official	146:f64d43ff0c18	1372	//@}
mbed_official	146:f64d43ff0c18	1373
mbed_official	146:f64d43ff0c18	1374	/*!
mbed_official	146:f64d43ff0c18	1375	* @name Register DMA_EEI, field EEI5[5] (RW)
mbed_official	146:f64d43ff0c18	1376	*
mbed_official	146:f64d43ff0c18	1377	* Values:
mbed_official	146:f64d43ff0c18	1378	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1379	* interrupt
mbed_official	146:f64d43ff0c18	1380	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1381	* an error interrupt request
mbed_official	146:f64d43ff0c18	1382	*/
mbed_official	146:f64d43ff0c18	1383	//@{
mbed_official	146:f64d43ff0c18	1384	#define BP_DMA_EEI_EEI5 (5U) //!< Bit position for DMA_EEI_EEI5.
mbed_official	146:f64d43ff0c18	1385	#define BM_DMA_EEI_EEI5 (0x00000020U) //!< Bit mask for DMA_EEI_EEI5.
mbed_official	146:f64d43ff0c18	1386	#define BS_DMA_EEI_EEI5 (1U) //!< Bit field size in bits for DMA_EEI_EEI5.
mbed_official	146:f64d43ff0c18	1387
mbed_official	146:f64d43ff0c18	1388	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1389	//! @brief Read current value of the DMA_EEI_EEI5 field.
mbed_official	146:f64d43ff0c18	1390	#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
mbed_official	146:f64d43ff0c18	1391	#endif
mbed_official	146:f64d43ff0c18	1392
mbed_official	146:f64d43ff0c18	1393	//! @brief Format value for bitfield DMA_EEI_EEI5.
mbed_official	146:f64d43ff0c18	1394	#define BF_DMA_EEI_EEI5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI5), uint32_t) & BM_DMA_EEI_EEI5)
mbed_official	146:f64d43ff0c18	1395
mbed_official	146:f64d43ff0c18	1396	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1397	//! @brief Set the EEI5 field to a new value.
mbed_official	146:f64d43ff0c18	1398	#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
mbed_official	146:f64d43ff0c18	1399	#endif
mbed_official	146:f64d43ff0c18	1400	//@}
mbed_official	146:f64d43ff0c18	1401
mbed_official	146:f64d43ff0c18	1402	/*!
mbed_official	146:f64d43ff0c18	1403	* @name Register DMA_EEI, field EEI6[6] (RW)
mbed_official	146:f64d43ff0c18	1404	*
mbed_official	146:f64d43ff0c18	1405	* Values:
mbed_official	146:f64d43ff0c18	1406	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1407	* interrupt
mbed_official	146:f64d43ff0c18	1408	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1409	* an error interrupt request
mbed_official	146:f64d43ff0c18	1410	*/
mbed_official	146:f64d43ff0c18	1411	//@{
mbed_official	146:f64d43ff0c18	1412	#define BP_DMA_EEI_EEI6 (6U) //!< Bit position for DMA_EEI_EEI6.
mbed_official	146:f64d43ff0c18	1413	#define BM_DMA_EEI_EEI6 (0x00000040U) //!< Bit mask for DMA_EEI_EEI6.
mbed_official	146:f64d43ff0c18	1414	#define BS_DMA_EEI_EEI6 (1U) //!< Bit field size in bits for DMA_EEI_EEI6.
mbed_official	146:f64d43ff0c18	1415
mbed_official	146:f64d43ff0c18	1416	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1417	//! @brief Read current value of the DMA_EEI_EEI6 field.
mbed_official	146:f64d43ff0c18	1418	#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
mbed_official	146:f64d43ff0c18	1419	#endif
mbed_official	146:f64d43ff0c18	1420
mbed_official	146:f64d43ff0c18	1421	//! @brief Format value for bitfield DMA_EEI_EEI6.
mbed_official	146:f64d43ff0c18	1422	#define BF_DMA_EEI_EEI6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI6), uint32_t) & BM_DMA_EEI_EEI6)
mbed_official	146:f64d43ff0c18	1423
mbed_official	146:f64d43ff0c18	1424	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1425	//! @brief Set the EEI6 field to a new value.
mbed_official	146:f64d43ff0c18	1426	#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
mbed_official	146:f64d43ff0c18	1427	#endif
mbed_official	146:f64d43ff0c18	1428	//@}
mbed_official	146:f64d43ff0c18	1429
mbed_official	146:f64d43ff0c18	1430	/*!
mbed_official	146:f64d43ff0c18	1431	* @name Register DMA_EEI, field EEI7[7] (RW)
mbed_official	146:f64d43ff0c18	1432	*
mbed_official	146:f64d43ff0c18	1433	* Values:
mbed_official	146:f64d43ff0c18	1434	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1435	* interrupt
mbed_official	146:f64d43ff0c18	1436	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1437	* an error interrupt request
mbed_official	146:f64d43ff0c18	1438	*/
mbed_official	146:f64d43ff0c18	1439	//@{
mbed_official	146:f64d43ff0c18	1440	#define BP_DMA_EEI_EEI7 (7U) //!< Bit position for DMA_EEI_EEI7.
mbed_official	146:f64d43ff0c18	1441	#define BM_DMA_EEI_EEI7 (0x00000080U) //!< Bit mask for DMA_EEI_EEI7.
mbed_official	146:f64d43ff0c18	1442	#define BS_DMA_EEI_EEI7 (1U) //!< Bit field size in bits for DMA_EEI_EEI7.
mbed_official	146:f64d43ff0c18	1443
mbed_official	146:f64d43ff0c18	1444	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1445	//! @brief Read current value of the DMA_EEI_EEI7 field.
mbed_official	146:f64d43ff0c18	1446	#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
mbed_official	146:f64d43ff0c18	1447	#endif
mbed_official	146:f64d43ff0c18	1448
mbed_official	146:f64d43ff0c18	1449	//! @brief Format value for bitfield DMA_EEI_EEI7.
mbed_official	146:f64d43ff0c18	1450	#define BF_DMA_EEI_EEI7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI7), uint32_t) & BM_DMA_EEI_EEI7)
mbed_official	146:f64d43ff0c18	1451
mbed_official	146:f64d43ff0c18	1452	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1453	//! @brief Set the EEI7 field to a new value.
mbed_official	146:f64d43ff0c18	1454	#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
mbed_official	146:f64d43ff0c18	1455	#endif
mbed_official	146:f64d43ff0c18	1456	//@}
mbed_official	146:f64d43ff0c18	1457
mbed_official	146:f64d43ff0c18	1458	/*!
mbed_official	146:f64d43ff0c18	1459	* @name Register DMA_EEI, field EEI8[8] (RW)
mbed_official	146:f64d43ff0c18	1460	*
mbed_official	146:f64d43ff0c18	1461	* Values:
mbed_official	146:f64d43ff0c18	1462	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1463	* interrupt
mbed_official	146:f64d43ff0c18	1464	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1465	* an error interrupt request
mbed_official	146:f64d43ff0c18	1466	*/
mbed_official	146:f64d43ff0c18	1467	//@{
mbed_official	146:f64d43ff0c18	1468	#define BP_DMA_EEI_EEI8 (8U) //!< Bit position for DMA_EEI_EEI8.
mbed_official	146:f64d43ff0c18	1469	#define BM_DMA_EEI_EEI8 (0x00000100U) //!< Bit mask for DMA_EEI_EEI8.
mbed_official	146:f64d43ff0c18	1470	#define BS_DMA_EEI_EEI8 (1U) //!< Bit field size in bits for DMA_EEI_EEI8.
mbed_official	146:f64d43ff0c18	1471
mbed_official	146:f64d43ff0c18	1472	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1473	//! @brief Read current value of the DMA_EEI_EEI8 field.
mbed_official	146:f64d43ff0c18	1474	#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
mbed_official	146:f64d43ff0c18	1475	#endif
mbed_official	146:f64d43ff0c18	1476
mbed_official	146:f64d43ff0c18	1477	//! @brief Format value for bitfield DMA_EEI_EEI8.
mbed_official	146:f64d43ff0c18	1478	#define BF_DMA_EEI_EEI8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI8), uint32_t) & BM_DMA_EEI_EEI8)
mbed_official	146:f64d43ff0c18	1479
mbed_official	146:f64d43ff0c18	1480	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1481	//! @brief Set the EEI8 field to a new value.
mbed_official	146:f64d43ff0c18	1482	#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
mbed_official	146:f64d43ff0c18	1483	#endif
mbed_official	146:f64d43ff0c18	1484	//@}
mbed_official	146:f64d43ff0c18	1485
mbed_official	146:f64d43ff0c18	1486	/*!
mbed_official	146:f64d43ff0c18	1487	* @name Register DMA_EEI, field EEI9[9] (RW)
mbed_official	146:f64d43ff0c18	1488	*
mbed_official	146:f64d43ff0c18	1489	* Values:
mbed_official	146:f64d43ff0c18	1490	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1491	* interrupt
mbed_official	146:f64d43ff0c18	1492	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1493	* an error interrupt request
mbed_official	146:f64d43ff0c18	1494	*/
mbed_official	146:f64d43ff0c18	1495	//@{
mbed_official	146:f64d43ff0c18	1496	#define BP_DMA_EEI_EEI9 (9U) //!< Bit position for DMA_EEI_EEI9.
mbed_official	146:f64d43ff0c18	1497	#define BM_DMA_EEI_EEI9 (0x00000200U) //!< Bit mask for DMA_EEI_EEI9.
mbed_official	146:f64d43ff0c18	1498	#define BS_DMA_EEI_EEI9 (1U) //!< Bit field size in bits for DMA_EEI_EEI9.
mbed_official	146:f64d43ff0c18	1499
mbed_official	146:f64d43ff0c18	1500	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1501	//! @brief Read current value of the DMA_EEI_EEI9 field.
mbed_official	146:f64d43ff0c18	1502	#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
mbed_official	146:f64d43ff0c18	1503	#endif
mbed_official	146:f64d43ff0c18	1504
mbed_official	146:f64d43ff0c18	1505	//! @brief Format value for bitfield DMA_EEI_EEI9.
mbed_official	146:f64d43ff0c18	1506	#define BF_DMA_EEI_EEI9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI9), uint32_t) & BM_DMA_EEI_EEI9)
mbed_official	146:f64d43ff0c18	1507
mbed_official	146:f64d43ff0c18	1508	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1509	//! @brief Set the EEI9 field to a new value.
mbed_official	146:f64d43ff0c18	1510	#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
mbed_official	146:f64d43ff0c18	1511	#endif
mbed_official	146:f64d43ff0c18	1512	//@}
mbed_official	146:f64d43ff0c18	1513
mbed_official	146:f64d43ff0c18	1514	/*!
mbed_official	146:f64d43ff0c18	1515	* @name Register DMA_EEI, field EEI10[10] (RW)
mbed_official	146:f64d43ff0c18	1516	*
mbed_official	146:f64d43ff0c18	1517	* Values:
mbed_official	146:f64d43ff0c18	1518	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1519	* interrupt
mbed_official	146:f64d43ff0c18	1520	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1521	* an error interrupt request
mbed_official	146:f64d43ff0c18	1522	*/
mbed_official	146:f64d43ff0c18	1523	//@{
mbed_official	146:f64d43ff0c18	1524	#define BP_DMA_EEI_EEI10 (10U) //!< Bit position for DMA_EEI_EEI10.
mbed_official	146:f64d43ff0c18	1525	#define BM_DMA_EEI_EEI10 (0x00000400U) //!< Bit mask for DMA_EEI_EEI10.
mbed_official	146:f64d43ff0c18	1526	#define BS_DMA_EEI_EEI10 (1U) //!< Bit field size in bits for DMA_EEI_EEI10.
mbed_official	146:f64d43ff0c18	1527
mbed_official	146:f64d43ff0c18	1528	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1529	//! @brief Read current value of the DMA_EEI_EEI10 field.
mbed_official	146:f64d43ff0c18	1530	#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
mbed_official	146:f64d43ff0c18	1531	#endif
mbed_official	146:f64d43ff0c18	1532
mbed_official	146:f64d43ff0c18	1533	//! @brief Format value for bitfield DMA_EEI_EEI10.
mbed_official	146:f64d43ff0c18	1534	#define BF_DMA_EEI_EEI10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI10), uint32_t) & BM_DMA_EEI_EEI10)
mbed_official	146:f64d43ff0c18	1535
mbed_official	146:f64d43ff0c18	1536	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1537	//! @brief Set the EEI10 field to a new value.
mbed_official	146:f64d43ff0c18	1538	#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
mbed_official	146:f64d43ff0c18	1539	#endif
mbed_official	146:f64d43ff0c18	1540	//@}
mbed_official	146:f64d43ff0c18	1541
mbed_official	146:f64d43ff0c18	1542	/*!
mbed_official	146:f64d43ff0c18	1543	* @name Register DMA_EEI, field EEI11[11] (RW)
mbed_official	146:f64d43ff0c18	1544	*
mbed_official	146:f64d43ff0c18	1545	* Values:
mbed_official	146:f64d43ff0c18	1546	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1547	* interrupt
mbed_official	146:f64d43ff0c18	1548	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1549	* an error interrupt request
mbed_official	146:f64d43ff0c18	1550	*/
mbed_official	146:f64d43ff0c18	1551	//@{
mbed_official	146:f64d43ff0c18	1552	#define BP_DMA_EEI_EEI11 (11U) //!< Bit position for DMA_EEI_EEI11.
mbed_official	146:f64d43ff0c18	1553	#define BM_DMA_EEI_EEI11 (0x00000800U) //!< Bit mask for DMA_EEI_EEI11.
mbed_official	146:f64d43ff0c18	1554	#define BS_DMA_EEI_EEI11 (1U) //!< Bit field size in bits for DMA_EEI_EEI11.
mbed_official	146:f64d43ff0c18	1555
mbed_official	146:f64d43ff0c18	1556	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1557	//! @brief Read current value of the DMA_EEI_EEI11 field.
mbed_official	146:f64d43ff0c18	1558	#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
mbed_official	146:f64d43ff0c18	1559	#endif
mbed_official	146:f64d43ff0c18	1560
mbed_official	146:f64d43ff0c18	1561	//! @brief Format value for bitfield DMA_EEI_EEI11.
mbed_official	146:f64d43ff0c18	1562	#define BF_DMA_EEI_EEI11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI11), uint32_t) & BM_DMA_EEI_EEI11)
mbed_official	146:f64d43ff0c18	1563
mbed_official	146:f64d43ff0c18	1564	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1565	//! @brief Set the EEI11 field to a new value.
mbed_official	146:f64d43ff0c18	1566	#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
mbed_official	146:f64d43ff0c18	1567	#endif
mbed_official	146:f64d43ff0c18	1568	//@}
mbed_official	146:f64d43ff0c18	1569
mbed_official	146:f64d43ff0c18	1570	/*!
mbed_official	146:f64d43ff0c18	1571	* @name Register DMA_EEI, field EEI12[12] (RW)
mbed_official	146:f64d43ff0c18	1572	*
mbed_official	146:f64d43ff0c18	1573	* Values:
mbed_official	146:f64d43ff0c18	1574	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1575	* interrupt
mbed_official	146:f64d43ff0c18	1576	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1577	* an error interrupt request
mbed_official	146:f64d43ff0c18	1578	*/
mbed_official	146:f64d43ff0c18	1579	//@{
mbed_official	146:f64d43ff0c18	1580	#define BP_DMA_EEI_EEI12 (12U) //!< Bit position for DMA_EEI_EEI12.
mbed_official	146:f64d43ff0c18	1581	#define BM_DMA_EEI_EEI12 (0x00001000U) //!< Bit mask for DMA_EEI_EEI12.
mbed_official	146:f64d43ff0c18	1582	#define BS_DMA_EEI_EEI12 (1U) //!< Bit field size in bits for DMA_EEI_EEI12.
mbed_official	146:f64d43ff0c18	1583
mbed_official	146:f64d43ff0c18	1584	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1585	//! @brief Read current value of the DMA_EEI_EEI12 field.
mbed_official	146:f64d43ff0c18	1586	#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
mbed_official	146:f64d43ff0c18	1587	#endif
mbed_official	146:f64d43ff0c18	1588
mbed_official	146:f64d43ff0c18	1589	//! @brief Format value for bitfield DMA_EEI_EEI12.
mbed_official	146:f64d43ff0c18	1590	#define BF_DMA_EEI_EEI12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI12), uint32_t) & BM_DMA_EEI_EEI12)
mbed_official	146:f64d43ff0c18	1591
mbed_official	146:f64d43ff0c18	1592	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1593	//! @brief Set the EEI12 field to a new value.
mbed_official	146:f64d43ff0c18	1594	#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
mbed_official	146:f64d43ff0c18	1595	#endif
mbed_official	146:f64d43ff0c18	1596	//@}
mbed_official	146:f64d43ff0c18	1597
mbed_official	146:f64d43ff0c18	1598	/*!
mbed_official	146:f64d43ff0c18	1599	* @name Register DMA_EEI, field EEI13[13] (RW)
mbed_official	146:f64d43ff0c18	1600	*
mbed_official	146:f64d43ff0c18	1601	* Values:
mbed_official	146:f64d43ff0c18	1602	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1603	* interrupt
mbed_official	146:f64d43ff0c18	1604	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1605	* an error interrupt request
mbed_official	146:f64d43ff0c18	1606	*/
mbed_official	146:f64d43ff0c18	1607	//@{
mbed_official	146:f64d43ff0c18	1608	#define BP_DMA_EEI_EEI13 (13U) //!< Bit position for DMA_EEI_EEI13.
mbed_official	146:f64d43ff0c18	1609	#define BM_DMA_EEI_EEI13 (0x00002000U) //!< Bit mask for DMA_EEI_EEI13.
mbed_official	146:f64d43ff0c18	1610	#define BS_DMA_EEI_EEI13 (1U) //!< Bit field size in bits for DMA_EEI_EEI13.
mbed_official	146:f64d43ff0c18	1611
mbed_official	146:f64d43ff0c18	1612	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1613	//! @brief Read current value of the DMA_EEI_EEI13 field.
mbed_official	146:f64d43ff0c18	1614	#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
mbed_official	146:f64d43ff0c18	1615	#endif
mbed_official	146:f64d43ff0c18	1616
mbed_official	146:f64d43ff0c18	1617	//! @brief Format value for bitfield DMA_EEI_EEI13.
mbed_official	146:f64d43ff0c18	1618	#define BF_DMA_EEI_EEI13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI13), uint32_t) & BM_DMA_EEI_EEI13)
mbed_official	146:f64d43ff0c18	1619
mbed_official	146:f64d43ff0c18	1620	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1621	//! @brief Set the EEI13 field to a new value.
mbed_official	146:f64d43ff0c18	1622	#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
mbed_official	146:f64d43ff0c18	1623	#endif
mbed_official	146:f64d43ff0c18	1624	//@}
mbed_official	146:f64d43ff0c18	1625
mbed_official	146:f64d43ff0c18	1626	/*!
mbed_official	146:f64d43ff0c18	1627	* @name Register DMA_EEI, field EEI14[14] (RW)
mbed_official	146:f64d43ff0c18	1628	*
mbed_official	146:f64d43ff0c18	1629	* Values:
mbed_official	146:f64d43ff0c18	1630	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1631	* interrupt
mbed_official	146:f64d43ff0c18	1632	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1633	* an error interrupt request
mbed_official	146:f64d43ff0c18	1634	*/
mbed_official	146:f64d43ff0c18	1635	//@{
mbed_official	146:f64d43ff0c18	1636	#define BP_DMA_EEI_EEI14 (14U) //!< Bit position for DMA_EEI_EEI14.
mbed_official	146:f64d43ff0c18	1637	#define BM_DMA_EEI_EEI14 (0x00004000U) //!< Bit mask for DMA_EEI_EEI14.
mbed_official	146:f64d43ff0c18	1638	#define BS_DMA_EEI_EEI14 (1U) //!< Bit field size in bits for DMA_EEI_EEI14.
mbed_official	146:f64d43ff0c18	1639
mbed_official	146:f64d43ff0c18	1640	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1641	//! @brief Read current value of the DMA_EEI_EEI14 field.
mbed_official	146:f64d43ff0c18	1642	#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
mbed_official	146:f64d43ff0c18	1643	#endif
mbed_official	146:f64d43ff0c18	1644
mbed_official	146:f64d43ff0c18	1645	//! @brief Format value for bitfield DMA_EEI_EEI14.
mbed_official	146:f64d43ff0c18	1646	#define BF_DMA_EEI_EEI14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI14), uint32_t) & BM_DMA_EEI_EEI14)
mbed_official	146:f64d43ff0c18	1647
mbed_official	146:f64d43ff0c18	1648	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1649	//! @brief Set the EEI14 field to a new value.
mbed_official	146:f64d43ff0c18	1650	#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
mbed_official	146:f64d43ff0c18	1651	#endif
mbed_official	146:f64d43ff0c18	1652	//@}
mbed_official	146:f64d43ff0c18	1653
mbed_official	146:f64d43ff0c18	1654	/*!
mbed_official	146:f64d43ff0c18	1655	* @name Register DMA_EEI, field EEI15[15] (RW)
mbed_official	146:f64d43ff0c18	1656	*
mbed_official	146:f64d43ff0c18	1657	* Values:
mbed_official	146:f64d43ff0c18	1658	* - 0 - The error signal for corresponding channel does not generate an error
mbed_official	146:f64d43ff0c18	1659	* interrupt
mbed_official	146:f64d43ff0c18	1660	* - 1 - The assertion of the error signal for corresponding channel generates
mbed_official	146:f64d43ff0c18	1661	* an error interrupt request
mbed_official	146:f64d43ff0c18	1662	*/
mbed_official	146:f64d43ff0c18	1663	//@{
mbed_official	146:f64d43ff0c18	1664	#define BP_DMA_EEI_EEI15 (15U) //!< Bit position for DMA_EEI_EEI15.
mbed_official	146:f64d43ff0c18	1665	#define BM_DMA_EEI_EEI15 (0x00008000U) //!< Bit mask for DMA_EEI_EEI15.
mbed_official	146:f64d43ff0c18	1666	#define BS_DMA_EEI_EEI15 (1U) //!< Bit field size in bits for DMA_EEI_EEI15.
mbed_official	146:f64d43ff0c18	1667
mbed_official	146:f64d43ff0c18	1668	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1669	//! @brief Read current value of the DMA_EEI_EEI15 field.
mbed_official	146:f64d43ff0c18	1670	#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
mbed_official	146:f64d43ff0c18	1671	#endif
mbed_official	146:f64d43ff0c18	1672
mbed_official	146:f64d43ff0c18	1673	//! @brief Format value for bitfield DMA_EEI_EEI15.
mbed_official	146:f64d43ff0c18	1674	#define BF_DMA_EEI_EEI15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI15), uint32_t) & BM_DMA_EEI_EEI15)
mbed_official	146:f64d43ff0c18	1675
mbed_official	146:f64d43ff0c18	1676	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1677	//! @brief Set the EEI15 field to a new value.
mbed_official	146:f64d43ff0c18	1678	#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
mbed_official	146:f64d43ff0c18	1679	#endif
mbed_official	146:f64d43ff0c18	1680	//@}
mbed_official	146:f64d43ff0c18	1681
mbed_official	146:f64d43ff0c18	1682	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1683	// HW_DMA_CEEI - Clear Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	1684	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1685
mbed_official	146:f64d43ff0c18	1686	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1687	/*!
mbed_official	146:f64d43ff0c18	1688	* @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
mbed_official	146:f64d43ff0c18	1689	*
mbed_official	146:f64d43ff0c18	1690	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1691	*
mbed_official	146:f64d43ff0c18	1692	* The CEEI provides a simple memory-mapped mechanism to clear a given bit in
mbed_official	146:f64d43ff0c18	1693	* the EEI to disable the error interrupt for a given channel. The data value on a
mbed_official	146:f64d43ff0c18	1694	* register write causes the corresponding bit in the EEI to be cleared. Setting
mbed_official	146:f64d43ff0c18	1695	* the CAEE bit provides a global clear function, forcing the EEI contents to be
mbed_official	146:f64d43ff0c18	1696	* cleared, disabling all DMA request inputs. If the NOP bit is set, the command
mbed_official	146:f64d43ff0c18	1697	* is ignored. This allows you to write multiple-byte registers as a 32-bit word.
mbed_official	146:f64d43ff0c18	1698	* Reads of this register return all zeroes.
mbed_official	146:f64d43ff0c18	1699	*/
mbed_official	146:f64d43ff0c18	1700	typedef union _hw_dma_ceei
mbed_official	146:f64d43ff0c18	1701	{
mbed_official	146:f64d43ff0c18	1702	uint8_t U;
mbed_official	146:f64d43ff0c18	1703	struct _hw_dma_ceei_bitfields
mbed_official	146:f64d43ff0c18	1704	{
mbed_official	146:f64d43ff0c18	1705	uint8_t CEEI : 4; //!< [3:0] Clear Enable Error Interrupt
mbed_official	146:f64d43ff0c18	1706	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	1707	uint8_t CAEE : 1; //!< [6] Clear All Enable Error Interrupts
mbed_official	146:f64d43ff0c18	1708	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	1709	} B;
mbed_official	146:f64d43ff0c18	1710	} hw_dma_ceei_t;
mbed_official	146:f64d43ff0c18	1711	#endif
mbed_official	146:f64d43ff0c18	1712
mbed_official	146:f64d43ff0c18	1713	/*!
mbed_official	146:f64d43ff0c18	1714	* @name Constants and macros for entire DMA_CEEI register
mbed_official	146:f64d43ff0c18	1715	*/
mbed_official	146:f64d43ff0c18	1716	//@{
mbed_official	146:f64d43ff0c18	1717	#define HW_DMA_CEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x18U)
mbed_official	146:f64d43ff0c18	1718
mbed_official	146:f64d43ff0c18	1719	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1720	#define HW_DMA_CEEI(x) ((__O hw_dma_ceei_t ) HW_DMA_CEEI_ADDR(x))
mbed_official	146:f64d43ff0c18	1721	#define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
mbed_official	146:f64d43ff0c18	1722	#define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
mbed_official	146:f64d43ff0c18	1723	#endif
mbed_official	146:f64d43ff0c18	1724	//@}
mbed_official	146:f64d43ff0c18	1725
mbed_official	146:f64d43ff0c18	1726	/*
mbed_official	146:f64d43ff0c18	1727	* Constants & macros for individual DMA_CEEI bitfields
mbed_official	146:f64d43ff0c18	1728	*/
mbed_official	146:f64d43ff0c18	1729
mbed_official	146:f64d43ff0c18	1730	/*!
mbed_official	146:f64d43ff0c18	1731	* @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	1732	*
mbed_official	146:f64d43ff0c18	1733	* Clears the corresponding bit in EEI
mbed_official	146:f64d43ff0c18	1734	*/
mbed_official	146:f64d43ff0c18	1735	//@{
mbed_official	146:f64d43ff0c18	1736	#define BP_DMA_CEEI_CEEI (0U) //!< Bit position for DMA_CEEI_CEEI.
mbed_official	146:f64d43ff0c18	1737	#define BM_DMA_CEEI_CEEI (0x0FU) //!< Bit mask for DMA_CEEI_CEEI.
mbed_official	146:f64d43ff0c18	1738	#define BS_DMA_CEEI_CEEI (4U) //!< Bit field size in bits for DMA_CEEI_CEEI.
mbed_official	146:f64d43ff0c18	1739
mbed_official	146:f64d43ff0c18	1740	//! @brief Format value for bitfield DMA_CEEI_CEEI.
mbed_official	146:f64d43ff0c18	1741	#define BF_DMA_CEEI_CEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CEEI), uint8_t) & BM_DMA_CEEI_CEEI)
mbed_official	146:f64d43ff0c18	1742
mbed_official	146:f64d43ff0c18	1743	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1744	//! @brief Set the CEEI field to a new value.
mbed_official	146:f64d43ff0c18	1745	#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) \| BF_DMA_CEEI_CEEI(v)))
mbed_official	146:f64d43ff0c18	1746	#endif
mbed_official	146:f64d43ff0c18	1747	//@}
mbed_official	146:f64d43ff0c18	1748
mbed_official	146:f64d43ff0c18	1749	/*!
mbed_official	146:f64d43ff0c18	1750	* @name Register DMA_CEEI, field CAEE[6] (WORZ)
mbed_official	146:f64d43ff0c18	1751	*
mbed_official	146:f64d43ff0c18	1752	* Values:
mbed_official	146:f64d43ff0c18	1753	* - 0 - Clear only the EEI bit specified in the CEEI field
mbed_official	146:f64d43ff0c18	1754	* - 1 - Clear all bits in EEI
mbed_official	146:f64d43ff0c18	1755	*/
mbed_official	146:f64d43ff0c18	1756	//@{
mbed_official	146:f64d43ff0c18	1757	#define BP_DMA_CEEI_CAEE (6U) //!< Bit position for DMA_CEEI_CAEE.
mbed_official	146:f64d43ff0c18	1758	#define BM_DMA_CEEI_CAEE (0x40U) //!< Bit mask for DMA_CEEI_CAEE.
mbed_official	146:f64d43ff0c18	1759	#define BS_DMA_CEEI_CAEE (1U) //!< Bit field size in bits for DMA_CEEI_CAEE.
mbed_official	146:f64d43ff0c18	1760
mbed_official	146:f64d43ff0c18	1761	//! @brief Format value for bitfield DMA_CEEI_CAEE.
mbed_official	146:f64d43ff0c18	1762	#define BF_DMA_CEEI_CAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CAEE), uint8_t) & BM_DMA_CEEI_CAEE)
mbed_official	146:f64d43ff0c18	1763
mbed_official	146:f64d43ff0c18	1764	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1765	//! @brief Set the CAEE field to a new value.
mbed_official	146:f64d43ff0c18	1766	#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
mbed_official	146:f64d43ff0c18	1767	#endif
mbed_official	146:f64d43ff0c18	1768	//@}
mbed_official	146:f64d43ff0c18	1769
mbed_official	146:f64d43ff0c18	1770	/*!
mbed_official	146:f64d43ff0c18	1771	* @name Register DMA_CEEI, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	1772	*
mbed_official	146:f64d43ff0c18	1773	* Values:
mbed_official	146:f64d43ff0c18	1774	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	1775	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	1776	*/
mbed_official	146:f64d43ff0c18	1777	//@{
mbed_official	146:f64d43ff0c18	1778	#define BP_DMA_CEEI_NOP (7U) //!< Bit position for DMA_CEEI_NOP.
mbed_official	146:f64d43ff0c18	1779	#define BM_DMA_CEEI_NOP (0x80U) //!< Bit mask for DMA_CEEI_NOP.
mbed_official	146:f64d43ff0c18	1780	#define BS_DMA_CEEI_NOP (1U) //!< Bit field size in bits for DMA_CEEI_NOP.
mbed_official	146:f64d43ff0c18	1781
mbed_official	146:f64d43ff0c18	1782	//! @brief Format value for bitfield DMA_CEEI_NOP.
mbed_official	146:f64d43ff0c18	1783	#define BF_DMA_CEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_NOP), uint8_t) & BM_DMA_CEEI_NOP)
mbed_official	146:f64d43ff0c18	1784
mbed_official	146:f64d43ff0c18	1785	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1786	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	1787	#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
mbed_official	146:f64d43ff0c18	1788	#endif
mbed_official	146:f64d43ff0c18	1789	//@}
mbed_official	146:f64d43ff0c18	1790
mbed_official	146:f64d43ff0c18	1791	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1792	// HW_DMA_SEEI - Set Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	1793	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1794
mbed_official	146:f64d43ff0c18	1795	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1796	/*!
mbed_official	146:f64d43ff0c18	1797	* @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
mbed_official	146:f64d43ff0c18	1798	*
mbed_official	146:f64d43ff0c18	1799	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1800	*
mbed_official	146:f64d43ff0c18	1801	* The SEEI provides a simple memory-mapped mechanism to set a given bit in the
mbed_official	146:f64d43ff0c18	1802	* EEI to enable the error interrupt for a given channel. The data value on a
mbed_official	146:f64d43ff0c18	1803	* register write causes the corresponding bit in the EEI to be set. Setting the
mbed_official	146:f64d43ff0c18	1804	* SAEE bit provides a global set function, forcing the entire EEI contents to be
mbed_official	146:f64d43ff0c18	1805	* set. If the NOP bit is set, the command is ignored. This allows you to write
mbed_official	146:f64d43ff0c18	1806	* multiple-byte registers as a 32-bit word. Reads of this register return all
mbed_official	146:f64d43ff0c18	1807	* zeroes.
mbed_official	146:f64d43ff0c18	1808	*/
mbed_official	146:f64d43ff0c18	1809	typedef union _hw_dma_seei
mbed_official	146:f64d43ff0c18	1810	{
mbed_official	146:f64d43ff0c18	1811	uint8_t U;
mbed_official	146:f64d43ff0c18	1812	struct _hw_dma_seei_bitfields
mbed_official	146:f64d43ff0c18	1813	{
mbed_official	146:f64d43ff0c18	1814	uint8_t SEEI : 4; //!< [3:0] Set Enable Error Interrupt
mbed_official	146:f64d43ff0c18	1815	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	1816	uint8_t SAEE : 1; //!< [6] Sets All Enable Error Interrupts
mbed_official	146:f64d43ff0c18	1817	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	1818	} B;
mbed_official	146:f64d43ff0c18	1819	} hw_dma_seei_t;
mbed_official	146:f64d43ff0c18	1820	#endif
mbed_official	146:f64d43ff0c18	1821
mbed_official	146:f64d43ff0c18	1822	/*!
mbed_official	146:f64d43ff0c18	1823	* @name Constants and macros for entire DMA_SEEI register
mbed_official	146:f64d43ff0c18	1824	*/
mbed_official	146:f64d43ff0c18	1825	//@{
mbed_official	146:f64d43ff0c18	1826	#define HW_DMA_SEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x19U)
mbed_official	146:f64d43ff0c18	1827
mbed_official	146:f64d43ff0c18	1828	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1829	#define HW_DMA_SEEI(x) ((__O hw_dma_seei_t ) HW_DMA_SEEI_ADDR(x))
mbed_official	146:f64d43ff0c18	1830	#define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
mbed_official	146:f64d43ff0c18	1831	#define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
mbed_official	146:f64d43ff0c18	1832	#endif
mbed_official	146:f64d43ff0c18	1833	//@}
mbed_official	146:f64d43ff0c18	1834
mbed_official	146:f64d43ff0c18	1835	/*
mbed_official	146:f64d43ff0c18	1836	* Constants & macros for individual DMA_SEEI bitfields
mbed_official	146:f64d43ff0c18	1837	*/
mbed_official	146:f64d43ff0c18	1838
mbed_official	146:f64d43ff0c18	1839	/*!
mbed_official	146:f64d43ff0c18	1840	* @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	1841	*
mbed_official	146:f64d43ff0c18	1842	* Sets the corresponding bit in EEI
mbed_official	146:f64d43ff0c18	1843	*/
mbed_official	146:f64d43ff0c18	1844	//@{
mbed_official	146:f64d43ff0c18	1845	#define BP_DMA_SEEI_SEEI (0U) //!< Bit position for DMA_SEEI_SEEI.
mbed_official	146:f64d43ff0c18	1846	#define BM_DMA_SEEI_SEEI (0x0FU) //!< Bit mask for DMA_SEEI_SEEI.
mbed_official	146:f64d43ff0c18	1847	#define BS_DMA_SEEI_SEEI (4U) //!< Bit field size in bits for DMA_SEEI_SEEI.
mbed_official	146:f64d43ff0c18	1848
mbed_official	146:f64d43ff0c18	1849	//! @brief Format value for bitfield DMA_SEEI_SEEI.
mbed_official	146:f64d43ff0c18	1850	#define BF_DMA_SEEI_SEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SEEI), uint8_t) & BM_DMA_SEEI_SEEI)
mbed_official	146:f64d43ff0c18	1851
mbed_official	146:f64d43ff0c18	1852	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1853	//! @brief Set the SEEI field to a new value.
mbed_official	146:f64d43ff0c18	1854	#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) \| BF_DMA_SEEI_SEEI(v)))
mbed_official	146:f64d43ff0c18	1855	#endif
mbed_official	146:f64d43ff0c18	1856	//@}
mbed_official	146:f64d43ff0c18	1857
mbed_official	146:f64d43ff0c18	1858	/*!
mbed_official	146:f64d43ff0c18	1859	* @name Register DMA_SEEI, field SAEE[6] (WORZ)
mbed_official	146:f64d43ff0c18	1860	*
mbed_official	146:f64d43ff0c18	1861	* Values:
mbed_official	146:f64d43ff0c18	1862	* - 0 - Set only the EEI bit specified in the SEEI field.
mbed_official	146:f64d43ff0c18	1863	* - 1 - Sets all bits in EEI
mbed_official	146:f64d43ff0c18	1864	*/
mbed_official	146:f64d43ff0c18	1865	//@{
mbed_official	146:f64d43ff0c18	1866	#define BP_DMA_SEEI_SAEE (6U) //!< Bit position for DMA_SEEI_SAEE.
mbed_official	146:f64d43ff0c18	1867	#define BM_DMA_SEEI_SAEE (0x40U) //!< Bit mask for DMA_SEEI_SAEE.
mbed_official	146:f64d43ff0c18	1868	#define BS_DMA_SEEI_SAEE (1U) //!< Bit field size in bits for DMA_SEEI_SAEE.
mbed_official	146:f64d43ff0c18	1869
mbed_official	146:f64d43ff0c18	1870	//! @brief Format value for bitfield DMA_SEEI_SAEE.
mbed_official	146:f64d43ff0c18	1871	#define BF_DMA_SEEI_SAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SAEE), uint8_t) & BM_DMA_SEEI_SAEE)
mbed_official	146:f64d43ff0c18	1872
mbed_official	146:f64d43ff0c18	1873	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1874	//! @brief Set the SAEE field to a new value.
mbed_official	146:f64d43ff0c18	1875	#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
mbed_official	146:f64d43ff0c18	1876	#endif
mbed_official	146:f64d43ff0c18	1877	//@}
mbed_official	146:f64d43ff0c18	1878
mbed_official	146:f64d43ff0c18	1879	/*!
mbed_official	146:f64d43ff0c18	1880	* @name Register DMA_SEEI, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	1881	*
mbed_official	146:f64d43ff0c18	1882	* Values:
mbed_official	146:f64d43ff0c18	1883	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	1884	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	1885	*/
mbed_official	146:f64d43ff0c18	1886	//@{
mbed_official	146:f64d43ff0c18	1887	#define BP_DMA_SEEI_NOP (7U) //!< Bit position for DMA_SEEI_NOP.
mbed_official	146:f64d43ff0c18	1888	#define BM_DMA_SEEI_NOP (0x80U) //!< Bit mask for DMA_SEEI_NOP.
mbed_official	146:f64d43ff0c18	1889	#define BS_DMA_SEEI_NOP (1U) //!< Bit field size in bits for DMA_SEEI_NOP.
mbed_official	146:f64d43ff0c18	1890
mbed_official	146:f64d43ff0c18	1891	//! @brief Format value for bitfield DMA_SEEI_NOP.
mbed_official	146:f64d43ff0c18	1892	#define BF_DMA_SEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_NOP), uint8_t) & BM_DMA_SEEI_NOP)
mbed_official	146:f64d43ff0c18	1893
mbed_official	146:f64d43ff0c18	1894	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1895	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	1896	#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
mbed_official	146:f64d43ff0c18	1897	#endif
mbed_official	146:f64d43ff0c18	1898	//@}
mbed_official	146:f64d43ff0c18	1899
mbed_official	146:f64d43ff0c18	1900	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1901	// HW_DMA_CERQ - Clear Enable Request Register
mbed_official	146:f64d43ff0c18	1902	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1903
mbed_official	146:f64d43ff0c18	1904	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1905	/*!
mbed_official	146:f64d43ff0c18	1906	* @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
mbed_official	146:f64d43ff0c18	1907	*
mbed_official	146:f64d43ff0c18	1908	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1909	*
mbed_official	146:f64d43ff0c18	1910	* The CERQ provides a simple memory-mapped mechanism to clear a given bit in
mbed_official	146:f64d43ff0c18	1911	* the ERQ to disable the DMA request for a given channel. The data value on a
mbed_official	146:f64d43ff0c18	1912	* register write causes the corresponding bit in the ERQ to be cleared. Setting the
mbed_official	146:f64d43ff0c18	1913	* CAER bit provides a global clear function, forcing the entire contents of the
mbed_official	146:f64d43ff0c18	1914	* ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
mbed_official	146:f64d43ff0c18	1915	* command is ignored. This allows you to write multiple-byte registers as a 32-bit
mbed_official	146:f64d43ff0c18	1916	* word. Reads of this register return all zeroes.
mbed_official	146:f64d43ff0c18	1917	*/
mbed_official	146:f64d43ff0c18	1918	typedef union _hw_dma_cerq
mbed_official	146:f64d43ff0c18	1919	{
mbed_official	146:f64d43ff0c18	1920	uint8_t U;
mbed_official	146:f64d43ff0c18	1921	struct _hw_dma_cerq_bitfields
mbed_official	146:f64d43ff0c18	1922	{
mbed_official	146:f64d43ff0c18	1923	uint8_t CERQ : 4; //!< [3:0] Clear Enable Request
mbed_official	146:f64d43ff0c18	1924	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	1925	uint8_t CAER : 1; //!< [6] Clear All Enable Requests
mbed_official	146:f64d43ff0c18	1926	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	1927	} B;
mbed_official	146:f64d43ff0c18	1928	} hw_dma_cerq_t;
mbed_official	146:f64d43ff0c18	1929	#endif
mbed_official	146:f64d43ff0c18	1930
mbed_official	146:f64d43ff0c18	1931	/*!
mbed_official	146:f64d43ff0c18	1932	* @name Constants and macros for entire DMA_CERQ register
mbed_official	146:f64d43ff0c18	1933	*/
mbed_official	146:f64d43ff0c18	1934	//@{
mbed_official	146:f64d43ff0c18	1935	#define HW_DMA_CERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1AU)
mbed_official	146:f64d43ff0c18	1936
mbed_official	146:f64d43ff0c18	1937	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1938	#define HW_DMA_CERQ(x) ((__O hw_dma_cerq_t ) HW_DMA_CERQ_ADDR(x))
mbed_official	146:f64d43ff0c18	1939	#define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
mbed_official	146:f64d43ff0c18	1940	#define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
mbed_official	146:f64d43ff0c18	1941	#endif
mbed_official	146:f64d43ff0c18	1942	//@}
mbed_official	146:f64d43ff0c18	1943
mbed_official	146:f64d43ff0c18	1944	/*
mbed_official	146:f64d43ff0c18	1945	* Constants & macros for individual DMA_CERQ bitfields
mbed_official	146:f64d43ff0c18	1946	*/
mbed_official	146:f64d43ff0c18	1947
mbed_official	146:f64d43ff0c18	1948	/*!
mbed_official	146:f64d43ff0c18	1949	* @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	1950	*
mbed_official	146:f64d43ff0c18	1951	* Clears the corresponding bit in ERQ
mbed_official	146:f64d43ff0c18	1952	*/
mbed_official	146:f64d43ff0c18	1953	//@{
mbed_official	146:f64d43ff0c18	1954	#define BP_DMA_CERQ_CERQ (0U) //!< Bit position for DMA_CERQ_CERQ.
mbed_official	146:f64d43ff0c18	1955	#define BM_DMA_CERQ_CERQ (0x0FU) //!< Bit mask for DMA_CERQ_CERQ.
mbed_official	146:f64d43ff0c18	1956	#define BS_DMA_CERQ_CERQ (4U) //!< Bit field size in bits for DMA_CERQ_CERQ.
mbed_official	146:f64d43ff0c18	1957
mbed_official	146:f64d43ff0c18	1958	//! @brief Format value for bitfield DMA_CERQ_CERQ.
mbed_official	146:f64d43ff0c18	1959	#define BF_DMA_CERQ_CERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CERQ), uint8_t) & BM_DMA_CERQ_CERQ)
mbed_official	146:f64d43ff0c18	1960
mbed_official	146:f64d43ff0c18	1961	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1962	//! @brief Set the CERQ field to a new value.
mbed_official	146:f64d43ff0c18	1963	#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) \| BF_DMA_CERQ_CERQ(v)))
mbed_official	146:f64d43ff0c18	1964	#endif
mbed_official	146:f64d43ff0c18	1965	//@}
mbed_official	146:f64d43ff0c18	1966
mbed_official	146:f64d43ff0c18	1967	/*!
mbed_official	146:f64d43ff0c18	1968	* @name Register DMA_CERQ, field CAER[6] (WORZ)
mbed_official	146:f64d43ff0c18	1969	*
mbed_official	146:f64d43ff0c18	1970	* Values:
mbed_official	146:f64d43ff0c18	1971	* - 0 - Clear only the ERQ bit specified in the CERQ field
mbed_official	146:f64d43ff0c18	1972	* - 1 - Clear all bits in ERQ
mbed_official	146:f64d43ff0c18	1973	*/
mbed_official	146:f64d43ff0c18	1974	//@{
mbed_official	146:f64d43ff0c18	1975	#define BP_DMA_CERQ_CAER (6U) //!< Bit position for DMA_CERQ_CAER.
mbed_official	146:f64d43ff0c18	1976	#define BM_DMA_CERQ_CAER (0x40U) //!< Bit mask for DMA_CERQ_CAER.
mbed_official	146:f64d43ff0c18	1977	#define BS_DMA_CERQ_CAER (1U) //!< Bit field size in bits for DMA_CERQ_CAER.
mbed_official	146:f64d43ff0c18	1978
mbed_official	146:f64d43ff0c18	1979	//! @brief Format value for bitfield DMA_CERQ_CAER.
mbed_official	146:f64d43ff0c18	1980	#define BF_DMA_CERQ_CAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CAER), uint8_t) & BM_DMA_CERQ_CAER)
mbed_official	146:f64d43ff0c18	1981
mbed_official	146:f64d43ff0c18	1982	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1983	//! @brief Set the CAER field to a new value.
mbed_official	146:f64d43ff0c18	1984	#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
mbed_official	146:f64d43ff0c18	1985	#endif
mbed_official	146:f64d43ff0c18	1986	//@}
mbed_official	146:f64d43ff0c18	1987
mbed_official	146:f64d43ff0c18	1988	/*!
mbed_official	146:f64d43ff0c18	1989	* @name Register DMA_CERQ, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	1990	*
mbed_official	146:f64d43ff0c18	1991	* Values:
mbed_official	146:f64d43ff0c18	1992	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	1993	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	1994	*/
mbed_official	146:f64d43ff0c18	1995	//@{
mbed_official	146:f64d43ff0c18	1996	#define BP_DMA_CERQ_NOP (7U) //!< Bit position for DMA_CERQ_NOP.
mbed_official	146:f64d43ff0c18	1997	#define BM_DMA_CERQ_NOP (0x80U) //!< Bit mask for DMA_CERQ_NOP.
mbed_official	146:f64d43ff0c18	1998	#define BS_DMA_CERQ_NOP (1U) //!< Bit field size in bits for DMA_CERQ_NOP.
mbed_official	146:f64d43ff0c18	1999
mbed_official	146:f64d43ff0c18	2000	//! @brief Format value for bitfield DMA_CERQ_NOP.
mbed_official	146:f64d43ff0c18	2001	#define BF_DMA_CERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_NOP), uint8_t) & BM_DMA_CERQ_NOP)
mbed_official	146:f64d43ff0c18	2002
mbed_official	146:f64d43ff0c18	2003	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2004	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	2005	#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
mbed_official	146:f64d43ff0c18	2006	#endif
mbed_official	146:f64d43ff0c18	2007	//@}
mbed_official	146:f64d43ff0c18	2008
mbed_official	146:f64d43ff0c18	2009	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2010	// HW_DMA_SERQ - Set Enable Request Register
mbed_official	146:f64d43ff0c18	2011	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2012
mbed_official	146:f64d43ff0c18	2013	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2014	/*!
mbed_official	146:f64d43ff0c18	2015	* @brief HW_DMA_SERQ - Set Enable Request Register (WO)
mbed_official	146:f64d43ff0c18	2016	*
mbed_official	146:f64d43ff0c18	2017	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	2018	*
mbed_official	146:f64d43ff0c18	2019	* The SERQ provides a simple memory-mapped mechanism to set a given bit in the
mbed_official	146:f64d43ff0c18	2020	* ERQ to enable the DMA request for a given channel. The data value on a
mbed_official	146:f64d43ff0c18	2021	* register write causes the corresponding bit in the ERQ to be set. Setting the SAER
mbed_official	146:f64d43ff0c18	2022	* bit provides a global set function, forcing the entire contents of ERQ to be
mbed_official	146:f64d43ff0c18	2023	* set. If the NOP bit is set, the command is ignored. This allows you to write
mbed_official	146:f64d43ff0c18	2024	* multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
mbed_official	146:f64d43ff0c18	2025	*/
mbed_official	146:f64d43ff0c18	2026	typedef union _hw_dma_serq
mbed_official	146:f64d43ff0c18	2027	{
mbed_official	146:f64d43ff0c18	2028	uint8_t U;
mbed_official	146:f64d43ff0c18	2029	struct _hw_dma_serq_bitfields
mbed_official	146:f64d43ff0c18	2030	{
mbed_official	146:f64d43ff0c18	2031	uint8_t SERQ : 4; //!< [3:0] Set enable request
mbed_official	146:f64d43ff0c18	2032	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	2033	uint8_t SAER : 1; //!< [6] Set All Enable Requests
mbed_official	146:f64d43ff0c18	2034	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	2035	} B;
mbed_official	146:f64d43ff0c18	2036	} hw_dma_serq_t;
mbed_official	146:f64d43ff0c18	2037	#endif
mbed_official	146:f64d43ff0c18	2038
mbed_official	146:f64d43ff0c18	2039	/*!
mbed_official	146:f64d43ff0c18	2040	* @name Constants and macros for entire DMA_SERQ register
mbed_official	146:f64d43ff0c18	2041	*/
mbed_official	146:f64d43ff0c18	2042	//@{
mbed_official	146:f64d43ff0c18	2043	#define HW_DMA_SERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1BU)
mbed_official	146:f64d43ff0c18	2044
mbed_official	146:f64d43ff0c18	2045	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2046	#define HW_DMA_SERQ(x) ((__O hw_dma_serq_t ) HW_DMA_SERQ_ADDR(x))
mbed_official	146:f64d43ff0c18	2047	#define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
mbed_official	146:f64d43ff0c18	2048	#define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
mbed_official	146:f64d43ff0c18	2049	#endif
mbed_official	146:f64d43ff0c18	2050	//@}
mbed_official	146:f64d43ff0c18	2051
mbed_official	146:f64d43ff0c18	2052	/*
mbed_official	146:f64d43ff0c18	2053	* Constants & macros for individual DMA_SERQ bitfields
mbed_official	146:f64d43ff0c18	2054	*/
mbed_official	146:f64d43ff0c18	2055
mbed_official	146:f64d43ff0c18	2056	/*!
mbed_official	146:f64d43ff0c18	2057	* @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	2058	*
mbed_official	146:f64d43ff0c18	2059	* Sets the corresponding bit in ERQ
mbed_official	146:f64d43ff0c18	2060	*/
mbed_official	146:f64d43ff0c18	2061	//@{
mbed_official	146:f64d43ff0c18	2062	#define BP_DMA_SERQ_SERQ (0U) //!< Bit position for DMA_SERQ_SERQ.
mbed_official	146:f64d43ff0c18	2063	#define BM_DMA_SERQ_SERQ (0x0FU) //!< Bit mask for DMA_SERQ_SERQ.
mbed_official	146:f64d43ff0c18	2064	#define BS_DMA_SERQ_SERQ (4U) //!< Bit field size in bits for DMA_SERQ_SERQ.
mbed_official	146:f64d43ff0c18	2065
mbed_official	146:f64d43ff0c18	2066	//! @brief Format value for bitfield DMA_SERQ_SERQ.
mbed_official	146:f64d43ff0c18	2067	#define BF_DMA_SERQ_SERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SERQ), uint8_t) & BM_DMA_SERQ_SERQ)
mbed_official	146:f64d43ff0c18	2068
mbed_official	146:f64d43ff0c18	2069	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2070	//! @brief Set the SERQ field to a new value.
mbed_official	146:f64d43ff0c18	2071	#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) \| BF_DMA_SERQ_SERQ(v)))
mbed_official	146:f64d43ff0c18	2072	#endif
mbed_official	146:f64d43ff0c18	2073	//@}
mbed_official	146:f64d43ff0c18	2074
mbed_official	146:f64d43ff0c18	2075	/*!
mbed_official	146:f64d43ff0c18	2076	* @name Register DMA_SERQ, field SAER[6] (WORZ)
mbed_official	146:f64d43ff0c18	2077	*
mbed_official	146:f64d43ff0c18	2078	* Values:
mbed_official	146:f64d43ff0c18	2079	* - 0 - Set only the ERQ bit specified in the SERQ field
mbed_official	146:f64d43ff0c18	2080	* - 1 - Set all bits in ERQ
mbed_official	146:f64d43ff0c18	2081	*/
mbed_official	146:f64d43ff0c18	2082	//@{
mbed_official	146:f64d43ff0c18	2083	#define BP_DMA_SERQ_SAER (6U) //!< Bit position for DMA_SERQ_SAER.
mbed_official	146:f64d43ff0c18	2084	#define BM_DMA_SERQ_SAER (0x40U) //!< Bit mask for DMA_SERQ_SAER.
mbed_official	146:f64d43ff0c18	2085	#define BS_DMA_SERQ_SAER (1U) //!< Bit field size in bits for DMA_SERQ_SAER.
mbed_official	146:f64d43ff0c18	2086
mbed_official	146:f64d43ff0c18	2087	//! @brief Format value for bitfield DMA_SERQ_SAER.
mbed_official	146:f64d43ff0c18	2088	#define BF_DMA_SERQ_SAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SAER), uint8_t) & BM_DMA_SERQ_SAER)
mbed_official	146:f64d43ff0c18	2089
mbed_official	146:f64d43ff0c18	2090	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2091	//! @brief Set the SAER field to a new value.
mbed_official	146:f64d43ff0c18	2092	#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
mbed_official	146:f64d43ff0c18	2093	#endif
mbed_official	146:f64d43ff0c18	2094	//@}
mbed_official	146:f64d43ff0c18	2095
mbed_official	146:f64d43ff0c18	2096	/*!
mbed_official	146:f64d43ff0c18	2097	* @name Register DMA_SERQ, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	2098	*
mbed_official	146:f64d43ff0c18	2099	* Values:
mbed_official	146:f64d43ff0c18	2100	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	2101	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	2102	*/
mbed_official	146:f64d43ff0c18	2103	//@{
mbed_official	146:f64d43ff0c18	2104	#define BP_DMA_SERQ_NOP (7U) //!< Bit position for DMA_SERQ_NOP.
mbed_official	146:f64d43ff0c18	2105	#define BM_DMA_SERQ_NOP (0x80U) //!< Bit mask for DMA_SERQ_NOP.
mbed_official	146:f64d43ff0c18	2106	#define BS_DMA_SERQ_NOP (1U) //!< Bit field size in bits for DMA_SERQ_NOP.
mbed_official	146:f64d43ff0c18	2107
mbed_official	146:f64d43ff0c18	2108	//! @brief Format value for bitfield DMA_SERQ_NOP.
mbed_official	146:f64d43ff0c18	2109	#define BF_DMA_SERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_NOP), uint8_t) & BM_DMA_SERQ_NOP)
mbed_official	146:f64d43ff0c18	2110
mbed_official	146:f64d43ff0c18	2111	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2112	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	2113	#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
mbed_official	146:f64d43ff0c18	2114	#endif
mbed_official	146:f64d43ff0c18	2115	//@}
mbed_official	146:f64d43ff0c18	2116
mbed_official	146:f64d43ff0c18	2117	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2118	// HW_DMA_CDNE - Clear DONE Status Bit Register
mbed_official	146:f64d43ff0c18	2119	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2120
mbed_official	146:f64d43ff0c18	2121	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2122	/*!
mbed_official	146:f64d43ff0c18	2123	* @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
mbed_official	146:f64d43ff0c18	2124	*
mbed_official	146:f64d43ff0c18	2125	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	2126	*
mbed_official	146:f64d43ff0c18	2127	* The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
mbed_official	146:f64d43ff0c18	2128	* the TCD of the given channel. The data value on a register write causes the
mbed_official	146:f64d43ff0c18	2129	* DONE bit in the corresponding transfer control descriptor to be cleared. Setting
mbed_official	146:f64d43ff0c18	2130	* the CADN bit provides a global clear function, forcing all DONE bits to be
mbed_official	146:f64d43ff0c18	2131	* cleared. If the NOP bit is set, the command is ignored. This allows you to write
mbed_official	146:f64d43ff0c18	2132	* multiple-byte registers as a 32-bit word. Reads of this register return all
mbed_official	146:f64d43ff0c18	2133	* zeroes.
mbed_official	146:f64d43ff0c18	2134	*/
mbed_official	146:f64d43ff0c18	2135	typedef union _hw_dma_cdne
mbed_official	146:f64d43ff0c18	2136	{
mbed_official	146:f64d43ff0c18	2137	uint8_t U;
mbed_official	146:f64d43ff0c18	2138	struct _hw_dma_cdne_bitfields
mbed_official	146:f64d43ff0c18	2139	{
mbed_official	146:f64d43ff0c18	2140	uint8_t CDNE : 4; //!< [3:0] Clear DONE Bit
mbed_official	146:f64d43ff0c18	2141	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	2142	uint8_t CADN : 1; //!< [6] Clears All DONE Bits
mbed_official	146:f64d43ff0c18	2143	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	2144	} B;
mbed_official	146:f64d43ff0c18	2145	} hw_dma_cdne_t;
mbed_official	146:f64d43ff0c18	2146	#endif
mbed_official	146:f64d43ff0c18	2147
mbed_official	146:f64d43ff0c18	2148	/*!
mbed_official	146:f64d43ff0c18	2149	* @name Constants and macros for entire DMA_CDNE register
mbed_official	146:f64d43ff0c18	2150	*/
mbed_official	146:f64d43ff0c18	2151	//@{
mbed_official	146:f64d43ff0c18	2152	#define HW_DMA_CDNE_ADDR(x) (REGS_DMA_BASE(x) + 0x1CU)
mbed_official	146:f64d43ff0c18	2153
mbed_official	146:f64d43ff0c18	2154	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2155	#define HW_DMA_CDNE(x) ((__O hw_dma_cdne_t ) HW_DMA_CDNE_ADDR(x))
mbed_official	146:f64d43ff0c18	2156	#define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
mbed_official	146:f64d43ff0c18	2157	#define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
mbed_official	146:f64d43ff0c18	2158	#endif
mbed_official	146:f64d43ff0c18	2159	//@}
mbed_official	146:f64d43ff0c18	2160
mbed_official	146:f64d43ff0c18	2161	/*
mbed_official	146:f64d43ff0c18	2162	* Constants & macros for individual DMA_CDNE bitfields
mbed_official	146:f64d43ff0c18	2163	*/
mbed_official	146:f64d43ff0c18	2164
mbed_official	146:f64d43ff0c18	2165	/*!
mbed_official	146:f64d43ff0c18	2166	* @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	2167	*
mbed_official	146:f64d43ff0c18	2168	* Clears the corresponding bit in TCDn_CSR[DONE]
mbed_official	146:f64d43ff0c18	2169	*/
mbed_official	146:f64d43ff0c18	2170	//@{
mbed_official	146:f64d43ff0c18	2171	#define BP_DMA_CDNE_CDNE (0U) //!< Bit position for DMA_CDNE_CDNE.
mbed_official	146:f64d43ff0c18	2172	#define BM_DMA_CDNE_CDNE (0x0FU) //!< Bit mask for DMA_CDNE_CDNE.
mbed_official	146:f64d43ff0c18	2173	#define BS_DMA_CDNE_CDNE (4U) //!< Bit field size in bits for DMA_CDNE_CDNE.
mbed_official	146:f64d43ff0c18	2174
mbed_official	146:f64d43ff0c18	2175	//! @brief Format value for bitfield DMA_CDNE_CDNE.
mbed_official	146:f64d43ff0c18	2176	#define BF_DMA_CDNE_CDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CDNE), uint8_t) & BM_DMA_CDNE_CDNE)
mbed_official	146:f64d43ff0c18	2177
mbed_official	146:f64d43ff0c18	2178	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2179	//! @brief Set the CDNE field to a new value.
mbed_official	146:f64d43ff0c18	2180	#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) \| BF_DMA_CDNE_CDNE(v)))
mbed_official	146:f64d43ff0c18	2181	#endif
mbed_official	146:f64d43ff0c18	2182	//@}
mbed_official	146:f64d43ff0c18	2183
mbed_official	146:f64d43ff0c18	2184	/*!
mbed_official	146:f64d43ff0c18	2185	* @name Register DMA_CDNE, field CADN[6] (WORZ)
mbed_official	146:f64d43ff0c18	2186	*
mbed_official	146:f64d43ff0c18	2187	* Values:
mbed_official	146:f64d43ff0c18	2188	* - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
mbed_official	146:f64d43ff0c18	2189	* - 1 - Clears all bits in TCDn_CSR[DONE]
mbed_official	146:f64d43ff0c18	2190	*/
mbed_official	146:f64d43ff0c18	2191	//@{
mbed_official	146:f64d43ff0c18	2192	#define BP_DMA_CDNE_CADN (6U) //!< Bit position for DMA_CDNE_CADN.
mbed_official	146:f64d43ff0c18	2193	#define BM_DMA_CDNE_CADN (0x40U) //!< Bit mask for DMA_CDNE_CADN.
mbed_official	146:f64d43ff0c18	2194	#define BS_DMA_CDNE_CADN (1U) //!< Bit field size in bits for DMA_CDNE_CADN.
mbed_official	146:f64d43ff0c18	2195
mbed_official	146:f64d43ff0c18	2196	//! @brief Format value for bitfield DMA_CDNE_CADN.
mbed_official	146:f64d43ff0c18	2197	#define BF_DMA_CDNE_CADN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CADN), uint8_t) & BM_DMA_CDNE_CADN)
mbed_official	146:f64d43ff0c18	2198
mbed_official	146:f64d43ff0c18	2199	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2200	//! @brief Set the CADN field to a new value.
mbed_official	146:f64d43ff0c18	2201	#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
mbed_official	146:f64d43ff0c18	2202	#endif
mbed_official	146:f64d43ff0c18	2203	//@}
mbed_official	146:f64d43ff0c18	2204
mbed_official	146:f64d43ff0c18	2205	/*!
mbed_official	146:f64d43ff0c18	2206	* @name Register DMA_CDNE, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	2207	*
mbed_official	146:f64d43ff0c18	2208	* Values:
mbed_official	146:f64d43ff0c18	2209	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	2210	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	2211	*/
mbed_official	146:f64d43ff0c18	2212	//@{
mbed_official	146:f64d43ff0c18	2213	#define BP_DMA_CDNE_NOP (7U) //!< Bit position for DMA_CDNE_NOP.
mbed_official	146:f64d43ff0c18	2214	#define BM_DMA_CDNE_NOP (0x80U) //!< Bit mask for DMA_CDNE_NOP.
mbed_official	146:f64d43ff0c18	2215	#define BS_DMA_CDNE_NOP (1U) //!< Bit field size in bits for DMA_CDNE_NOP.
mbed_official	146:f64d43ff0c18	2216
mbed_official	146:f64d43ff0c18	2217	//! @brief Format value for bitfield DMA_CDNE_NOP.
mbed_official	146:f64d43ff0c18	2218	#define BF_DMA_CDNE_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_NOP), uint8_t) & BM_DMA_CDNE_NOP)
mbed_official	146:f64d43ff0c18	2219
mbed_official	146:f64d43ff0c18	2220	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2221	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	2222	#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
mbed_official	146:f64d43ff0c18	2223	#endif
mbed_official	146:f64d43ff0c18	2224	//@}
mbed_official	146:f64d43ff0c18	2225
mbed_official	146:f64d43ff0c18	2226	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2227	// HW_DMA_SSRT - Set START Bit Register
mbed_official	146:f64d43ff0c18	2228	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2229
mbed_official	146:f64d43ff0c18	2230	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2231	/*!
mbed_official	146:f64d43ff0c18	2232	* @brief HW_DMA_SSRT - Set START Bit Register (WO)
mbed_official	146:f64d43ff0c18	2233	*
mbed_official	146:f64d43ff0c18	2234	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	2235	*
mbed_official	146:f64d43ff0c18	2236	* The SSRT provides a simple memory-mapped mechanism to set the START bit in
mbed_official	146:f64d43ff0c18	2237	* the TCD of the given channel. The data value on a register write causes the
mbed_official	146:f64d43ff0c18	2238	* START bit in the corresponding transfer control descriptor to be set. Setting the
mbed_official	146:f64d43ff0c18	2239	* SAST bit provides a global set function, forcing all START bits to be set. If
mbed_official	146:f64d43ff0c18	2240	* the NOP bit is set, the command is ignored. This allows you to write
mbed_official	146:f64d43ff0c18	2241	* multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
mbed_official	146:f64d43ff0c18	2242	*/
mbed_official	146:f64d43ff0c18	2243	typedef union _hw_dma_ssrt
mbed_official	146:f64d43ff0c18	2244	{
mbed_official	146:f64d43ff0c18	2245	uint8_t U;
mbed_official	146:f64d43ff0c18	2246	struct _hw_dma_ssrt_bitfields
mbed_official	146:f64d43ff0c18	2247	{
mbed_official	146:f64d43ff0c18	2248	uint8_t SSRT : 4; //!< [3:0] Set START Bit
mbed_official	146:f64d43ff0c18	2249	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	2250	uint8_t SAST : 1; //!< [6] Set All START Bits (activates all channels)
mbed_official	146:f64d43ff0c18	2251	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	2252	} B;
mbed_official	146:f64d43ff0c18	2253	} hw_dma_ssrt_t;
mbed_official	146:f64d43ff0c18	2254	#endif
mbed_official	146:f64d43ff0c18	2255
mbed_official	146:f64d43ff0c18	2256	/*!
mbed_official	146:f64d43ff0c18	2257	* @name Constants and macros for entire DMA_SSRT register
mbed_official	146:f64d43ff0c18	2258	*/
mbed_official	146:f64d43ff0c18	2259	//@{
mbed_official	146:f64d43ff0c18	2260	#define HW_DMA_SSRT_ADDR(x) (REGS_DMA_BASE(x) + 0x1DU)
mbed_official	146:f64d43ff0c18	2261
mbed_official	146:f64d43ff0c18	2262	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2263	#define HW_DMA_SSRT(x) ((__O hw_dma_ssrt_t ) HW_DMA_SSRT_ADDR(x))
mbed_official	146:f64d43ff0c18	2264	#define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
mbed_official	146:f64d43ff0c18	2265	#define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
mbed_official	146:f64d43ff0c18	2266	#endif
mbed_official	146:f64d43ff0c18	2267	//@}
mbed_official	146:f64d43ff0c18	2268
mbed_official	146:f64d43ff0c18	2269	/*
mbed_official	146:f64d43ff0c18	2270	* Constants & macros for individual DMA_SSRT bitfields
mbed_official	146:f64d43ff0c18	2271	*/
mbed_official	146:f64d43ff0c18	2272
mbed_official	146:f64d43ff0c18	2273	/*!
mbed_official	146:f64d43ff0c18	2274	* @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	2275	*
mbed_official	146:f64d43ff0c18	2276	* Sets the corresponding bit in TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	2277	*/
mbed_official	146:f64d43ff0c18	2278	//@{
mbed_official	146:f64d43ff0c18	2279	#define BP_DMA_SSRT_SSRT (0U) //!< Bit position for DMA_SSRT_SSRT.
mbed_official	146:f64d43ff0c18	2280	#define BM_DMA_SSRT_SSRT (0x0FU) //!< Bit mask for DMA_SSRT_SSRT.
mbed_official	146:f64d43ff0c18	2281	#define BS_DMA_SSRT_SSRT (4U) //!< Bit field size in bits for DMA_SSRT_SSRT.
mbed_official	146:f64d43ff0c18	2282
mbed_official	146:f64d43ff0c18	2283	//! @brief Format value for bitfield DMA_SSRT_SSRT.
mbed_official	146:f64d43ff0c18	2284	#define BF_DMA_SSRT_SSRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SSRT), uint8_t) & BM_DMA_SSRT_SSRT)
mbed_official	146:f64d43ff0c18	2285
mbed_official	146:f64d43ff0c18	2286	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2287	//! @brief Set the SSRT field to a new value.
mbed_official	146:f64d43ff0c18	2288	#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) \| BF_DMA_SSRT_SSRT(v)))
mbed_official	146:f64d43ff0c18	2289	#endif
mbed_official	146:f64d43ff0c18	2290	//@}
mbed_official	146:f64d43ff0c18	2291
mbed_official	146:f64d43ff0c18	2292	/*!
mbed_official	146:f64d43ff0c18	2293	* @name Register DMA_SSRT, field SAST[6] (WORZ)
mbed_official	146:f64d43ff0c18	2294	*
mbed_official	146:f64d43ff0c18	2295	* Values:
mbed_official	146:f64d43ff0c18	2296	* - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
mbed_official	146:f64d43ff0c18	2297	* - 1 - Set all bits in TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	2298	*/
mbed_official	146:f64d43ff0c18	2299	//@{
mbed_official	146:f64d43ff0c18	2300	#define BP_DMA_SSRT_SAST (6U) //!< Bit position for DMA_SSRT_SAST.
mbed_official	146:f64d43ff0c18	2301	#define BM_DMA_SSRT_SAST (0x40U) //!< Bit mask for DMA_SSRT_SAST.
mbed_official	146:f64d43ff0c18	2302	#define BS_DMA_SSRT_SAST (1U) //!< Bit field size in bits for DMA_SSRT_SAST.
mbed_official	146:f64d43ff0c18	2303
mbed_official	146:f64d43ff0c18	2304	//! @brief Format value for bitfield DMA_SSRT_SAST.
mbed_official	146:f64d43ff0c18	2305	#define BF_DMA_SSRT_SAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SAST), uint8_t) & BM_DMA_SSRT_SAST)
mbed_official	146:f64d43ff0c18	2306
mbed_official	146:f64d43ff0c18	2307	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2308	//! @brief Set the SAST field to a new value.
mbed_official	146:f64d43ff0c18	2309	#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
mbed_official	146:f64d43ff0c18	2310	#endif
mbed_official	146:f64d43ff0c18	2311	//@}
mbed_official	146:f64d43ff0c18	2312
mbed_official	146:f64d43ff0c18	2313	/*!
mbed_official	146:f64d43ff0c18	2314	* @name Register DMA_SSRT, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	2315	*
mbed_official	146:f64d43ff0c18	2316	* Values:
mbed_official	146:f64d43ff0c18	2317	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	2318	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	2319	*/
mbed_official	146:f64d43ff0c18	2320	//@{
mbed_official	146:f64d43ff0c18	2321	#define BP_DMA_SSRT_NOP (7U) //!< Bit position for DMA_SSRT_NOP.
mbed_official	146:f64d43ff0c18	2322	#define BM_DMA_SSRT_NOP (0x80U) //!< Bit mask for DMA_SSRT_NOP.
mbed_official	146:f64d43ff0c18	2323	#define BS_DMA_SSRT_NOP (1U) //!< Bit field size in bits for DMA_SSRT_NOP.
mbed_official	146:f64d43ff0c18	2324
mbed_official	146:f64d43ff0c18	2325	//! @brief Format value for bitfield DMA_SSRT_NOP.
mbed_official	146:f64d43ff0c18	2326	#define BF_DMA_SSRT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_NOP), uint8_t) & BM_DMA_SSRT_NOP)
mbed_official	146:f64d43ff0c18	2327
mbed_official	146:f64d43ff0c18	2328	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2329	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	2330	#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
mbed_official	146:f64d43ff0c18	2331	#endif
mbed_official	146:f64d43ff0c18	2332	//@}
mbed_official	146:f64d43ff0c18	2333
mbed_official	146:f64d43ff0c18	2334	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2335	// HW_DMA_CERR - Clear Error Register
mbed_official	146:f64d43ff0c18	2336	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2337
mbed_official	146:f64d43ff0c18	2338	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2339	/*!
mbed_official	146:f64d43ff0c18	2340	* @brief HW_DMA_CERR - Clear Error Register (WO)
mbed_official	146:f64d43ff0c18	2341	*
mbed_official	146:f64d43ff0c18	2342	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	2343	*
mbed_official	146:f64d43ff0c18	2344	* The CERR provides a simple memory-mapped mechanism to clear a given bit in
mbed_official	146:f64d43ff0c18	2345	* the ERR to disable the error condition flag for a given channel. The given value
mbed_official	146:f64d43ff0c18	2346	* on a register write causes the corresponding bit in the ERR to be cleared.
mbed_official	146:f64d43ff0c18	2347	* Setting the CAEI bit provides a global clear function, forcing the ERR contents
mbed_official	146:f64d43ff0c18	2348	* to be cleared, clearing all channel error indicators. If the NOP bit is set,
mbed_official	146:f64d43ff0c18	2349	* the command is ignored. This allows you to write multiple-byte registers as a
mbed_official	146:f64d43ff0c18	2350	* 32-bit word. Reads of this register return all zeroes.
mbed_official	146:f64d43ff0c18	2351	*/
mbed_official	146:f64d43ff0c18	2352	typedef union _hw_dma_cerr
mbed_official	146:f64d43ff0c18	2353	{
mbed_official	146:f64d43ff0c18	2354	uint8_t U;
mbed_official	146:f64d43ff0c18	2355	struct _hw_dma_cerr_bitfields
mbed_official	146:f64d43ff0c18	2356	{
mbed_official	146:f64d43ff0c18	2357	uint8_t CERR : 4; //!< [3:0] Clear Error Indicator
mbed_official	146:f64d43ff0c18	2358	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	2359	uint8_t CAEI : 1; //!< [6] Clear All Error Indicators
mbed_official	146:f64d43ff0c18	2360	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	2361	} B;
mbed_official	146:f64d43ff0c18	2362	} hw_dma_cerr_t;
mbed_official	146:f64d43ff0c18	2363	#endif
mbed_official	146:f64d43ff0c18	2364
mbed_official	146:f64d43ff0c18	2365	/*!
mbed_official	146:f64d43ff0c18	2366	* @name Constants and macros for entire DMA_CERR register
mbed_official	146:f64d43ff0c18	2367	*/
mbed_official	146:f64d43ff0c18	2368	//@{
mbed_official	146:f64d43ff0c18	2369	#define HW_DMA_CERR_ADDR(x) (REGS_DMA_BASE(x) + 0x1EU)
mbed_official	146:f64d43ff0c18	2370
mbed_official	146:f64d43ff0c18	2371	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2372	#define HW_DMA_CERR(x) ((__O hw_dma_cerr_t ) HW_DMA_CERR_ADDR(x))
mbed_official	146:f64d43ff0c18	2373	#define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
mbed_official	146:f64d43ff0c18	2374	#define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
mbed_official	146:f64d43ff0c18	2375	#endif
mbed_official	146:f64d43ff0c18	2376	//@}
mbed_official	146:f64d43ff0c18	2377
mbed_official	146:f64d43ff0c18	2378	/*
mbed_official	146:f64d43ff0c18	2379	* Constants & macros for individual DMA_CERR bitfields
mbed_official	146:f64d43ff0c18	2380	*/
mbed_official	146:f64d43ff0c18	2381
mbed_official	146:f64d43ff0c18	2382	/*!
mbed_official	146:f64d43ff0c18	2383	* @name Register DMA_CERR, field CERR[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	2384	*
mbed_official	146:f64d43ff0c18	2385	* Clears the corresponding bit in ERR
mbed_official	146:f64d43ff0c18	2386	*/
mbed_official	146:f64d43ff0c18	2387	//@{
mbed_official	146:f64d43ff0c18	2388	#define BP_DMA_CERR_CERR (0U) //!< Bit position for DMA_CERR_CERR.
mbed_official	146:f64d43ff0c18	2389	#define BM_DMA_CERR_CERR (0x0FU) //!< Bit mask for DMA_CERR_CERR.
mbed_official	146:f64d43ff0c18	2390	#define BS_DMA_CERR_CERR (4U) //!< Bit field size in bits for DMA_CERR_CERR.
mbed_official	146:f64d43ff0c18	2391
mbed_official	146:f64d43ff0c18	2392	//! @brief Format value for bitfield DMA_CERR_CERR.
mbed_official	146:f64d43ff0c18	2393	#define BF_DMA_CERR_CERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CERR), uint8_t) & BM_DMA_CERR_CERR)
mbed_official	146:f64d43ff0c18	2394
mbed_official	146:f64d43ff0c18	2395	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2396	//! @brief Set the CERR field to a new value.
mbed_official	146:f64d43ff0c18	2397	#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) \| BF_DMA_CERR_CERR(v)))
mbed_official	146:f64d43ff0c18	2398	#endif
mbed_official	146:f64d43ff0c18	2399	//@}
mbed_official	146:f64d43ff0c18	2400
mbed_official	146:f64d43ff0c18	2401	/*!
mbed_official	146:f64d43ff0c18	2402	* @name Register DMA_CERR, field CAEI[6] (WORZ)
mbed_official	146:f64d43ff0c18	2403	*
mbed_official	146:f64d43ff0c18	2404	* Values:
mbed_official	146:f64d43ff0c18	2405	* - 0 - Clear only the ERR bit specified in the CERR field
mbed_official	146:f64d43ff0c18	2406	* - 1 - Clear all bits in ERR
mbed_official	146:f64d43ff0c18	2407	*/
mbed_official	146:f64d43ff0c18	2408	//@{
mbed_official	146:f64d43ff0c18	2409	#define BP_DMA_CERR_CAEI (6U) //!< Bit position for DMA_CERR_CAEI.
mbed_official	146:f64d43ff0c18	2410	#define BM_DMA_CERR_CAEI (0x40U) //!< Bit mask for DMA_CERR_CAEI.
mbed_official	146:f64d43ff0c18	2411	#define BS_DMA_CERR_CAEI (1U) //!< Bit field size in bits for DMA_CERR_CAEI.
mbed_official	146:f64d43ff0c18	2412
mbed_official	146:f64d43ff0c18	2413	//! @brief Format value for bitfield DMA_CERR_CAEI.
mbed_official	146:f64d43ff0c18	2414	#define BF_DMA_CERR_CAEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CAEI), uint8_t) & BM_DMA_CERR_CAEI)
mbed_official	146:f64d43ff0c18	2415
mbed_official	146:f64d43ff0c18	2416	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2417	//! @brief Set the CAEI field to a new value.
mbed_official	146:f64d43ff0c18	2418	#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
mbed_official	146:f64d43ff0c18	2419	#endif
mbed_official	146:f64d43ff0c18	2420	//@}
mbed_official	146:f64d43ff0c18	2421
mbed_official	146:f64d43ff0c18	2422	/*!
mbed_official	146:f64d43ff0c18	2423	* @name Register DMA_CERR, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	2424	*
mbed_official	146:f64d43ff0c18	2425	* Values:
mbed_official	146:f64d43ff0c18	2426	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	2427	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	2428	*/
mbed_official	146:f64d43ff0c18	2429	//@{
mbed_official	146:f64d43ff0c18	2430	#define BP_DMA_CERR_NOP (7U) //!< Bit position for DMA_CERR_NOP.
mbed_official	146:f64d43ff0c18	2431	#define BM_DMA_CERR_NOP (0x80U) //!< Bit mask for DMA_CERR_NOP.
mbed_official	146:f64d43ff0c18	2432	#define BS_DMA_CERR_NOP (1U) //!< Bit field size in bits for DMA_CERR_NOP.
mbed_official	146:f64d43ff0c18	2433
mbed_official	146:f64d43ff0c18	2434	//! @brief Format value for bitfield DMA_CERR_NOP.
mbed_official	146:f64d43ff0c18	2435	#define BF_DMA_CERR_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_NOP), uint8_t) & BM_DMA_CERR_NOP)
mbed_official	146:f64d43ff0c18	2436
mbed_official	146:f64d43ff0c18	2437	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2438	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	2439	#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
mbed_official	146:f64d43ff0c18	2440	#endif
mbed_official	146:f64d43ff0c18	2441	//@}
mbed_official	146:f64d43ff0c18	2442
mbed_official	146:f64d43ff0c18	2443	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2444	// HW_DMA_CINT - Clear Interrupt Request Register
mbed_official	146:f64d43ff0c18	2445	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2446
mbed_official	146:f64d43ff0c18	2447	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2448	/*!
mbed_official	146:f64d43ff0c18	2449	* @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
mbed_official	146:f64d43ff0c18	2450	*
mbed_official	146:f64d43ff0c18	2451	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	2452	*
mbed_official	146:f64d43ff0c18	2453	* The CINT provides a simple, memory-mapped mechanism to clear a given bit in
mbed_official	146:f64d43ff0c18	2454	* the INT to disable the interrupt request for a given channel. The given value
mbed_official	146:f64d43ff0c18	2455	* on a register write causes the corresponding bit in the INT to be cleared.
mbed_official	146:f64d43ff0c18	2456	* Setting the CAIR bit provides a global clear function, forcing the entire contents
mbed_official	146:f64d43ff0c18	2457	* of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
mbed_official	146:f64d43ff0c18	2458	* bit is set, the command is ignored. This allows you to write multiple-byte
mbed_official	146:f64d43ff0c18	2459	* registers as a 32-bit word. Reads of this register return all zeroes.
mbed_official	146:f64d43ff0c18	2460	*/
mbed_official	146:f64d43ff0c18	2461	typedef union _hw_dma_cint
mbed_official	146:f64d43ff0c18	2462	{
mbed_official	146:f64d43ff0c18	2463	uint8_t U;
mbed_official	146:f64d43ff0c18	2464	struct _hw_dma_cint_bitfields
mbed_official	146:f64d43ff0c18	2465	{
mbed_official	146:f64d43ff0c18	2466	uint8_t CINT : 4; //!< [3:0] Clear Interrupt Request
mbed_official	146:f64d43ff0c18	2467	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	2468	uint8_t CAIR : 1; //!< [6] Clear All Interrupt Requests
mbed_official	146:f64d43ff0c18	2469	uint8_t NOP : 1; //!< [7] No Op enable
mbed_official	146:f64d43ff0c18	2470	} B;
mbed_official	146:f64d43ff0c18	2471	} hw_dma_cint_t;
mbed_official	146:f64d43ff0c18	2472	#endif
mbed_official	146:f64d43ff0c18	2473
mbed_official	146:f64d43ff0c18	2474	/*!
mbed_official	146:f64d43ff0c18	2475	* @name Constants and macros for entire DMA_CINT register
mbed_official	146:f64d43ff0c18	2476	*/
mbed_official	146:f64d43ff0c18	2477	//@{
mbed_official	146:f64d43ff0c18	2478	#define HW_DMA_CINT_ADDR(x) (REGS_DMA_BASE(x) + 0x1FU)
mbed_official	146:f64d43ff0c18	2479
mbed_official	146:f64d43ff0c18	2480	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2481	#define HW_DMA_CINT(x) ((__O hw_dma_cint_t ) HW_DMA_CINT_ADDR(x))
mbed_official	146:f64d43ff0c18	2482	#define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
mbed_official	146:f64d43ff0c18	2483	#define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
mbed_official	146:f64d43ff0c18	2484	#endif
mbed_official	146:f64d43ff0c18	2485	//@}
mbed_official	146:f64d43ff0c18	2486
mbed_official	146:f64d43ff0c18	2487	/*
mbed_official	146:f64d43ff0c18	2488	* Constants & macros for individual DMA_CINT bitfields
mbed_official	146:f64d43ff0c18	2489	*/
mbed_official	146:f64d43ff0c18	2490
mbed_official	146:f64d43ff0c18	2491	/*!
mbed_official	146:f64d43ff0c18	2492	* @name Register DMA_CINT, field CINT[3:0] (WORZ)
mbed_official	146:f64d43ff0c18	2493	*
mbed_official	146:f64d43ff0c18	2494	* Clears the corresponding bit in INT
mbed_official	146:f64d43ff0c18	2495	*/
mbed_official	146:f64d43ff0c18	2496	//@{
mbed_official	146:f64d43ff0c18	2497	#define BP_DMA_CINT_CINT (0U) //!< Bit position for DMA_CINT_CINT.
mbed_official	146:f64d43ff0c18	2498	#define BM_DMA_CINT_CINT (0x0FU) //!< Bit mask for DMA_CINT_CINT.
mbed_official	146:f64d43ff0c18	2499	#define BS_DMA_CINT_CINT (4U) //!< Bit field size in bits for DMA_CINT_CINT.
mbed_official	146:f64d43ff0c18	2500
mbed_official	146:f64d43ff0c18	2501	//! @brief Format value for bitfield DMA_CINT_CINT.
mbed_official	146:f64d43ff0c18	2502	#define BF_DMA_CINT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CINT), uint8_t) & BM_DMA_CINT_CINT)
mbed_official	146:f64d43ff0c18	2503
mbed_official	146:f64d43ff0c18	2504	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2505	//! @brief Set the CINT field to a new value.
mbed_official	146:f64d43ff0c18	2506	#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) \| BF_DMA_CINT_CINT(v)))
mbed_official	146:f64d43ff0c18	2507	#endif
mbed_official	146:f64d43ff0c18	2508	//@}
mbed_official	146:f64d43ff0c18	2509
mbed_official	146:f64d43ff0c18	2510	/*!
mbed_official	146:f64d43ff0c18	2511	* @name Register DMA_CINT, field CAIR[6] (WORZ)
mbed_official	146:f64d43ff0c18	2512	*
mbed_official	146:f64d43ff0c18	2513	* Values:
mbed_official	146:f64d43ff0c18	2514	* - 0 - Clear only the INT bit specified in the CINT field
mbed_official	146:f64d43ff0c18	2515	* - 1 - Clear all bits in INT
mbed_official	146:f64d43ff0c18	2516	*/
mbed_official	146:f64d43ff0c18	2517	//@{
mbed_official	146:f64d43ff0c18	2518	#define BP_DMA_CINT_CAIR (6U) //!< Bit position for DMA_CINT_CAIR.
mbed_official	146:f64d43ff0c18	2519	#define BM_DMA_CINT_CAIR (0x40U) //!< Bit mask for DMA_CINT_CAIR.
mbed_official	146:f64d43ff0c18	2520	#define BS_DMA_CINT_CAIR (1U) //!< Bit field size in bits for DMA_CINT_CAIR.
mbed_official	146:f64d43ff0c18	2521
mbed_official	146:f64d43ff0c18	2522	//! @brief Format value for bitfield DMA_CINT_CAIR.
mbed_official	146:f64d43ff0c18	2523	#define BF_DMA_CINT_CAIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CAIR), uint8_t) & BM_DMA_CINT_CAIR)
mbed_official	146:f64d43ff0c18	2524
mbed_official	146:f64d43ff0c18	2525	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2526	//! @brief Set the CAIR field to a new value.
mbed_official	146:f64d43ff0c18	2527	#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
mbed_official	146:f64d43ff0c18	2528	#endif
mbed_official	146:f64d43ff0c18	2529	//@}
mbed_official	146:f64d43ff0c18	2530
mbed_official	146:f64d43ff0c18	2531	/*!
mbed_official	146:f64d43ff0c18	2532	* @name Register DMA_CINT, field NOP[7] (WORZ)
mbed_official	146:f64d43ff0c18	2533	*
mbed_official	146:f64d43ff0c18	2534	* Values:
mbed_official	146:f64d43ff0c18	2535	* - 0 - Normal operation
mbed_official	146:f64d43ff0c18	2536	* - 1 - No operation, ignore the other bits in this register
mbed_official	146:f64d43ff0c18	2537	*/
mbed_official	146:f64d43ff0c18	2538	//@{
mbed_official	146:f64d43ff0c18	2539	#define BP_DMA_CINT_NOP (7U) //!< Bit position for DMA_CINT_NOP.
mbed_official	146:f64d43ff0c18	2540	#define BM_DMA_CINT_NOP (0x80U) //!< Bit mask for DMA_CINT_NOP.
mbed_official	146:f64d43ff0c18	2541	#define BS_DMA_CINT_NOP (1U) //!< Bit field size in bits for DMA_CINT_NOP.
mbed_official	146:f64d43ff0c18	2542
mbed_official	146:f64d43ff0c18	2543	//! @brief Format value for bitfield DMA_CINT_NOP.
mbed_official	146:f64d43ff0c18	2544	#define BF_DMA_CINT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_NOP), uint8_t) & BM_DMA_CINT_NOP)
mbed_official	146:f64d43ff0c18	2545
mbed_official	146:f64d43ff0c18	2546	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2547	//! @brief Set the NOP field to a new value.
mbed_official	146:f64d43ff0c18	2548	#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
mbed_official	146:f64d43ff0c18	2549	#endif
mbed_official	146:f64d43ff0c18	2550	//@}
mbed_official	146:f64d43ff0c18	2551
mbed_official	146:f64d43ff0c18	2552	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2553	// HW_DMA_INT - Interrupt Request Register
mbed_official	146:f64d43ff0c18	2554	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2555
mbed_official	146:f64d43ff0c18	2556	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2557	/*!
mbed_official	146:f64d43ff0c18	2558	* @brief HW_DMA_INT - Interrupt Request Register (RW)
mbed_official	146:f64d43ff0c18	2559	*
mbed_official	146:f64d43ff0c18	2560	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2561	*
mbed_official	146:f64d43ff0c18	2562	* The INT register provides a bit map for the 16 channels signaling the
mbed_official	146:f64d43ff0c18	2563	* presence of an interrupt request for each channel. Depending on the appropriate bit
mbed_official	146:f64d43ff0c18	2564	* setting in the transfer-control descriptors, the eDMA engine generates an
mbed_official	146:f64d43ff0c18	2565	* interrupt on data transfer completion. The outputs of this register are directly
mbed_official	146:f64d43ff0c18	2566	* routed to the interrupt controller (INTC). During the interrupt-service routine
mbed_official	146:f64d43ff0c18	2567	* associated with any given channel, it is the software's responsibility to
mbed_official	146:f64d43ff0c18	2568	* clear the appropriate bit, negating the interrupt request. Typically, a write to
mbed_official	146:f64d43ff0c18	2569	* the CINT register in the interrupt service routine is used for this purpose.
mbed_official	146:f64d43ff0c18	2570	* The state of any given channel's interrupt request is directly affected by
mbed_official	146:f64d43ff0c18	2571	* writes to this register; it is also affected by writes to the CINT register. On
mbed_official	146:f64d43ff0c18	2572	* writes to INT, a 1 in any bit position clears the corresponding channel's
mbed_official	146:f64d43ff0c18	2573	* interrupt request. A zero in any bit position has no affect on the corresponding
mbed_official	146:f64d43ff0c18	2574	* channel's current interrupt status. The CINT register is provided so the interrupt
mbed_official	146:f64d43ff0c18	2575	* request for a single channel can easily be cleared without the need to
mbed_official	146:f64d43ff0c18	2576	* perform a read-modify-write sequence to the INT register.
mbed_official	146:f64d43ff0c18	2577	*/
mbed_official	146:f64d43ff0c18	2578	typedef union _hw_dma_int
mbed_official	146:f64d43ff0c18	2579	{
mbed_official	146:f64d43ff0c18	2580	uint32_t U;
mbed_official	146:f64d43ff0c18	2581	struct _hw_dma_int_bitfields
mbed_official	146:f64d43ff0c18	2582	{
mbed_official	146:f64d43ff0c18	2583	uint32_t INT0 : 1; //!< [0] Interrupt Request 0
mbed_official	146:f64d43ff0c18	2584	uint32_t INT1 : 1; //!< [1] Interrupt Request 1
mbed_official	146:f64d43ff0c18	2585	uint32_t INT2 : 1; //!< [2] Interrupt Request 2
mbed_official	146:f64d43ff0c18	2586	uint32_t INT3 : 1; //!< [3] Interrupt Request 3
mbed_official	146:f64d43ff0c18	2587	uint32_t INT4 : 1; //!< [4] Interrupt Request 4
mbed_official	146:f64d43ff0c18	2588	uint32_t INT5 : 1; //!< [5] Interrupt Request 5
mbed_official	146:f64d43ff0c18	2589	uint32_t INT6 : 1; //!< [6] Interrupt Request 6
mbed_official	146:f64d43ff0c18	2590	uint32_t INT7 : 1; //!< [7] Interrupt Request 7
mbed_official	146:f64d43ff0c18	2591	uint32_t INT8 : 1; //!< [8] Interrupt Request 8
mbed_official	146:f64d43ff0c18	2592	uint32_t INT9 : 1; //!< [9] Interrupt Request 9
mbed_official	146:f64d43ff0c18	2593	uint32_t INT10 : 1; //!< [10] Interrupt Request 10
mbed_official	146:f64d43ff0c18	2594	uint32_t INT11 : 1; //!< [11] Interrupt Request 11
mbed_official	146:f64d43ff0c18	2595	uint32_t INT12 : 1; //!< [12] Interrupt Request 12
mbed_official	146:f64d43ff0c18	2596	uint32_t INT13 : 1; //!< [13] Interrupt Request 13
mbed_official	146:f64d43ff0c18	2597	uint32_t INT14 : 1; //!< [14] Interrupt Request 14
mbed_official	146:f64d43ff0c18	2598	uint32_t INT15 : 1; //!< [15] Interrupt Request 15
mbed_official	146:f64d43ff0c18	2599	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	2600	} B;
mbed_official	146:f64d43ff0c18	2601	} hw_dma_int_t;
mbed_official	146:f64d43ff0c18	2602	#endif
mbed_official	146:f64d43ff0c18	2603
mbed_official	146:f64d43ff0c18	2604	/*!
mbed_official	146:f64d43ff0c18	2605	* @name Constants and macros for entire DMA_INT register
mbed_official	146:f64d43ff0c18	2606	*/
mbed_official	146:f64d43ff0c18	2607	//@{
mbed_official	146:f64d43ff0c18	2608	#define HW_DMA_INT_ADDR(x) (REGS_DMA_BASE(x) + 0x24U)
mbed_official	146:f64d43ff0c18	2609
mbed_official	146:f64d43ff0c18	2610	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2611	#define HW_DMA_INT(x) ((__IO hw_dma_int_t ) HW_DMA_INT_ADDR(x))
mbed_official	146:f64d43ff0c18	2612	#define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
mbed_official	146:f64d43ff0c18	2613	#define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
mbed_official	146:f64d43ff0c18	2614	#define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2615	#define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2616	#define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2617	#endif
mbed_official	146:f64d43ff0c18	2618	//@}
mbed_official	146:f64d43ff0c18	2619
mbed_official	146:f64d43ff0c18	2620	/*
mbed_official	146:f64d43ff0c18	2621	* Constants & macros for individual DMA_INT bitfields
mbed_official	146:f64d43ff0c18	2622	*/
mbed_official	146:f64d43ff0c18	2623
mbed_official	146:f64d43ff0c18	2624	/*!
mbed_official	146:f64d43ff0c18	2625	* @name Register DMA_INT, field INT0[0] (W1C)
mbed_official	146:f64d43ff0c18	2626	*
mbed_official	146:f64d43ff0c18	2627	* Values:
mbed_official	146:f64d43ff0c18	2628	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2629	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2630	*/
mbed_official	146:f64d43ff0c18	2631	//@{
mbed_official	146:f64d43ff0c18	2632	#define BP_DMA_INT_INT0 (0U) //!< Bit position for DMA_INT_INT0.
mbed_official	146:f64d43ff0c18	2633	#define BM_DMA_INT_INT0 (0x00000001U) //!< Bit mask for DMA_INT_INT0.
mbed_official	146:f64d43ff0c18	2634	#define BS_DMA_INT_INT0 (1U) //!< Bit field size in bits for DMA_INT_INT0.
mbed_official	146:f64d43ff0c18	2635
mbed_official	146:f64d43ff0c18	2636	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2637	//! @brief Read current value of the DMA_INT_INT0 field.
mbed_official	146:f64d43ff0c18	2638	#define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
mbed_official	146:f64d43ff0c18	2639	#endif
mbed_official	146:f64d43ff0c18	2640
mbed_official	146:f64d43ff0c18	2641	//! @brief Format value for bitfield DMA_INT_INT0.
mbed_official	146:f64d43ff0c18	2642	#define BF_DMA_INT_INT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT0), uint32_t) & BM_DMA_INT_INT0)
mbed_official	146:f64d43ff0c18	2643
mbed_official	146:f64d43ff0c18	2644	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2645	//! @brief Set the INT0 field to a new value.
mbed_official	146:f64d43ff0c18	2646	#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
mbed_official	146:f64d43ff0c18	2647	#endif
mbed_official	146:f64d43ff0c18	2648	//@}
mbed_official	146:f64d43ff0c18	2649
mbed_official	146:f64d43ff0c18	2650	/*!
mbed_official	146:f64d43ff0c18	2651	* @name Register DMA_INT, field INT1[1] (W1C)
mbed_official	146:f64d43ff0c18	2652	*
mbed_official	146:f64d43ff0c18	2653	* Values:
mbed_official	146:f64d43ff0c18	2654	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2655	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2656	*/
mbed_official	146:f64d43ff0c18	2657	//@{
mbed_official	146:f64d43ff0c18	2658	#define BP_DMA_INT_INT1 (1U) //!< Bit position for DMA_INT_INT1.
mbed_official	146:f64d43ff0c18	2659	#define BM_DMA_INT_INT1 (0x00000002U) //!< Bit mask for DMA_INT_INT1.
mbed_official	146:f64d43ff0c18	2660	#define BS_DMA_INT_INT1 (1U) //!< Bit field size in bits for DMA_INT_INT1.
mbed_official	146:f64d43ff0c18	2661
mbed_official	146:f64d43ff0c18	2662	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2663	//! @brief Read current value of the DMA_INT_INT1 field.
mbed_official	146:f64d43ff0c18	2664	#define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
mbed_official	146:f64d43ff0c18	2665	#endif
mbed_official	146:f64d43ff0c18	2666
mbed_official	146:f64d43ff0c18	2667	//! @brief Format value for bitfield DMA_INT_INT1.
mbed_official	146:f64d43ff0c18	2668	#define BF_DMA_INT_INT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT1), uint32_t) & BM_DMA_INT_INT1)
mbed_official	146:f64d43ff0c18	2669
mbed_official	146:f64d43ff0c18	2670	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2671	//! @brief Set the INT1 field to a new value.
mbed_official	146:f64d43ff0c18	2672	#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
mbed_official	146:f64d43ff0c18	2673	#endif
mbed_official	146:f64d43ff0c18	2674	//@}
mbed_official	146:f64d43ff0c18	2675
mbed_official	146:f64d43ff0c18	2676	/*!
mbed_official	146:f64d43ff0c18	2677	* @name Register DMA_INT, field INT2[2] (W1C)
mbed_official	146:f64d43ff0c18	2678	*
mbed_official	146:f64d43ff0c18	2679	* Values:
mbed_official	146:f64d43ff0c18	2680	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2681	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2682	*/
mbed_official	146:f64d43ff0c18	2683	//@{
mbed_official	146:f64d43ff0c18	2684	#define BP_DMA_INT_INT2 (2U) //!< Bit position for DMA_INT_INT2.
mbed_official	146:f64d43ff0c18	2685	#define BM_DMA_INT_INT2 (0x00000004U) //!< Bit mask for DMA_INT_INT2.
mbed_official	146:f64d43ff0c18	2686	#define BS_DMA_INT_INT2 (1U) //!< Bit field size in bits for DMA_INT_INT2.
mbed_official	146:f64d43ff0c18	2687
mbed_official	146:f64d43ff0c18	2688	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2689	//! @brief Read current value of the DMA_INT_INT2 field.
mbed_official	146:f64d43ff0c18	2690	#define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
mbed_official	146:f64d43ff0c18	2691	#endif
mbed_official	146:f64d43ff0c18	2692
mbed_official	146:f64d43ff0c18	2693	//! @brief Format value for bitfield DMA_INT_INT2.
mbed_official	146:f64d43ff0c18	2694	#define BF_DMA_INT_INT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT2), uint32_t) & BM_DMA_INT_INT2)
mbed_official	146:f64d43ff0c18	2695
mbed_official	146:f64d43ff0c18	2696	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2697	//! @brief Set the INT2 field to a new value.
mbed_official	146:f64d43ff0c18	2698	#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
mbed_official	146:f64d43ff0c18	2699	#endif
mbed_official	146:f64d43ff0c18	2700	//@}
mbed_official	146:f64d43ff0c18	2701
mbed_official	146:f64d43ff0c18	2702	/*!
mbed_official	146:f64d43ff0c18	2703	* @name Register DMA_INT, field INT3[3] (W1C)
mbed_official	146:f64d43ff0c18	2704	*
mbed_official	146:f64d43ff0c18	2705	* Values:
mbed_official	146:f64d43ff0c18	2706	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2707	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2708	*/
mbed_official	146:f64d43ff0c18	2709	//@{
mbed_official	146:f64d43ff0c18	2710	#define BP_DMA_INT_INT3 (3U) //!< Bit position for DMA_INT_INT3.
mbed_official	146:f64d43ff0c18	2711	#define BM_DMA_INT_INT3 (0x00000008U) //!< Bit mask for DMA_INT_INT3.
mbed_official	146:f64d43ff0c18	2712	#define BS_DMA_INT_INT3 (1U) //!< Bit field size in bits for DMA_INT_INT3.
mbed_official	146:f64d43ff0c18	2713
mbed_official	146:f64d43ff0c18	2714	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2715	//! @brief Read current value of the DMA_INT_INT3 field.
mbed_official	146:f64d43ff0c18	2716	#define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
mbed_official	146:f64d43ff0c18	2717	#endif
mbed_official	146:f64d43ff0c18	2718
mbed_official	146:f64d43ff0c18	2719	//! @brief Format value for bitfield DMA_INT_INT3.
mbed_official	146:f64d43ff0c18	2720	#define BF_DMA_INT_INT3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT3), uint32_t) & BM_DMA_INT_INT3)
mbed_official	146:f64d43ff0c18	2721
mbed_official	146:f64d43ff0c18	2722	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2723	//! @brief Set the INT3 field to a new value.
mbed_official	146:f64d43ff0c18	2724	#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
mbed_official	146:f64d43ff0c18	2725	#endif
mbed_official	146:f64d43ff0c18	2726	//@}
mbed_official	146:f64d43ff0c18	2727
mbed_official	146:f64d43ff0c18	2728	/*!
mbed_official	146:f64d43ff0c18	2729	* @name Register DMA_INT, field INT4[4] (W1C)
mbed_official	146:f64d43ff0c18	2730	*
mbed_official	146:f64d43ff0c18	2731	* Values:
mbed_official	146:f64d43ff0c18	2732	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2733	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2734	*/
mbed_official	146:f64d43ff0c18	2735	//@{
mbed_official	146:f64d43ff0c18	2736	#define BP_DMA_INT_INT4 (4U) //!< Bit position for DMA_INT_INT4.
mbed_official	146:f64d43ff0c18	2737	#define BM_DMA_INT_INT4 (0x00000010U) //!< Bit mask for DMA_INT_INT4.
mbed_official	146:f64d43ff0c18	2738	#define BS_DMA_INT_INT4 (1U) //!< Bit field size in bits for DMA_INT_INT4.
mbed_official	146:f64d43ff0c18	2739
mbed_official	146:f64d43ff0c18	2740	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2741	//! @brief Read current value of the DMA_INT_INT4 field.
mbed_official	146:f64d43ff0c18	2742	#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
mbed_official	146:f64d43ff0c18	2743	#endif
mbed_official	146:f64d43ff0c18	2744
mbed_official	146:f64d43ff0c18	2745	//! @brief Format value for bitfield DMA_INT_INT4.
mbed_official	146:f64d43ff0c18	2746	#define BF_DMA_INT_INT4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT4), uint32_t) & BM_DMA_INT_INT4)
mbed_official	146:f64d43ff0c18	2747
mbed_official	146:f64d43ff0c18	2748	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2749	//! @brief Set the INT4 field to a new value.
mbed_official	146:f64d43ff0c18	2750	#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
mbed_official	146:f64d43ff0c18	2751	#endif
mbed_official	146:f64d43ff0c18	2752	//@}
mbed_official	146:f64d43ff0c18	2753
mbed_official	146:f64d43ff0c18	2754	/*!
mbed_official	146:f64d43ff0c18	2755	* @name Register DMA_INT, field INT5[5] (W1C)
mbed_official	146:f64d43ff0c18	2756	*
mbed_official	146:f64d43ff0c18	2757	* Values:
mbed_official	146:f64d43ff0c18	2758	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2759	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2760	*/
mbed_official	146:f64d43ff0c18	2761	//@{
mbed_official	146:f64d43ff0c18	2762	#define BP_DMA_INT_INT5 (5U) //!< Bit position for DMA_INT_INT5.
mbed_official	146:f64d43ff0c18	2763	#define BM_DMA_INT_INT5 (0x00000020U) //!< Bit mask for DMA_INT_INT5.
mbed_official	146:f64d43ff0c18	2764	#define BS_DMA_INT_INT5 (1U) //!< Bit field size in bits for DMA_INT_INT5.
mbed_official	146:f64d43ff0c18	2765
mbed_official	146:f64d43ff0c18	2766	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2767	//! @brief Read current value of the DMA_INT_INT5 field.
mbed_official	146:f64d43ff0c18	2768	#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
mbed_official	146:f64d43ff0c18	2769	#endif
mbed_official	146:f64d43ff0c18	2770
mbed_official	146:f64d43ff0c18	2771	//! @brief Format value for bitfield DMA_INT_INT5.
mbed_official	146:f64d43ff0c18	2772	#define BF_DMA_INT_INT5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT5), uint32_t) & BM_DMA_INT_INT5)
mbed_official	146:f64d43ff0c18	2773
mbed_official	146:f64d43ff0c18	2774	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2775	//! @brief Set the INT5 field to a new value.
mbed_official	146:f64d43ff0c18	2776	#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
mbed_official	146:f64d43ff0c18	2777	#endif
mbed_official	146:f64d43ff0c18	2778	//@}
mbed_official	146:f64d43ff0c18	2779
mbed_official	146:f64d43ff0c18	2780	/*!
mbed_official	146:f64d43ff0c18	2781	* @name Register DMA_INT, field INT6[6] (W1C)
mbed_official	146:f64d43ff0c18	2782	*
mbed_official	146:f64d43ff0c18	2783	* Values:
mbed_official	146:f64d43ff0c18	2784	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2785	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2786	*/
mbed_official	146:f64d43ff0c18	2787	//@{
mbed_official	146:f64d43ff0c18	2788	#define BP_DMA_INT_INT6 (6U) //!< Bit position for DMA_INT_INT6.
mbed_official	146:f64d43ff0c18	2789	#define BM_DMA_INT_INT6 (0x00000040U) //!< Bit mask for DMA_INT_INT6.
mbed_official	146:f64d43ff0c18	2790	#define BS_DMA_INT_INT6 (1U) //!< Bit field size in bits for DMA_INT_INT6.
mbed_official	146:f64d43ff0c18	2791
mbed_official	146:f64d43ff0c18	2792	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2793	//! @brief Read current value of the DMA_INT_INT6 field.
mbed_official	146:f64d43ff0c18	2794	#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
mbed_official	146:f64d43ff0c18	2795	#endif
mbed_official	146:f64d43ff0c18	2796
mbed_official	146:f64d43ff0c18	2797	//! @brief Format value for bitfield DMA_INT_INT6.
mbed_official	146:f64d43ff0c18	2798	#define BF_DMA_INT_INT6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT6), uint32_t) & BM_DMA_INT_INT6)
mbed_official	146:f64d43ff0c18	2799
mbed_official	146:f64d43ff0c18	2800	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2801	//! @brief Set the INT6 field to a new value.
mbed_official	146:f64d43ff0c18	2802	#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
mbed_official	146:f64d43ff0c18	2803	#endif
mbed_official	146:f64d43ff0c18	2804	//@}
mbed_official	146:f64d43ff0c18	2805
mbed_official	146:f64d43ff0c18	2806	/*!
mbed_official	146:f64d43ff0c18	2807	* @name Register DMA_INT, field INT7[7] (W1C)
mbed_official	146:f64d43ff0c18	2808	*
mbed_official	146:f64d43ff0c18	2809	* Values:
mbed_official	146:f64d43ff0c18	2810	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2811	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2812	*/
mbed_official	146:f64d43ff0c18	2813	//@{
mbed_official	146:f64d43ff0c18	2814	#define BP_DMA_INT_INT7 (7U) //!< Bit position for DMA_INT_INT7.
mbed_official	146:f64d43ff0c18	2815	#define BM_DMA_INT_INT7 (0x00000080U) //!< Bit mask for DMA_INT_INT7.
mbed_official	146:f64d43ff0c18	2816	#define BS_DMA_INT_INT7 (1U) //!< Bit field size in bits for DMA_INT_INT7.
mbed_official	146:f64d43ff0c18	2817
mbed_official	146:f64d43ff0c18	2818	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2819	//! @brief Read current value of the DMA_INT_INT7 field.
mbed_official	146:f64d43ff0c18	2820	#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
mbed_official	146:f64d43ff0c18	2821	#endif
mbed_official	146:f64d43ff0c18	2822
mbed_official	146:f64d43ff0c18	2823	//! @brief Format value for bitfield DMA_INT_INT7.
mbed_official	146:f64d43ff0c18	2824	#define BF_DMA_INT_INT7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT7), uint32_t) & BM_DMA_INT_INT7)
mbed_official	146:f64d43ff0c18	2825
mbed_official	146:f64d43ff0c18	2826	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2827	//! @brief Set the INT7 field to a new value.
mbed_official	146:f64d43ff0c18	2828	#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
mbed_official	146:f64d43ff0c18	2829	#endif
mbed_official	146:f64d43ff0c18	2830	//@}
mbed_official	146:f64d43ff0c18	2831
mbed_official	146:f64d43ff0c18	2832	/*!
mbed_official	146:f64d43ff0c18	2833	* @name Register DMA_INT, field INT8[8] (W1C)
mbed_official	146:f64d43ff0c18	2834	*
mbed_official	146:f64d43ff0c18	2835	* Values:
mbed_official	146:f64d43ff0c18	2836	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2837	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2838	*/
mbed_official	146:f64d43ff0c18	2839	//@{
mbed_official	146:f64d43ff0c18	2840	#define BP_DMA_INT_INT8 (8U) //!< Bit position for DMA_INT_INT8.
mbed_official	146:f64d43ff0c18	2841	#define BM_DMA_INT_INT8 (0x00000100U) //!< Bit mask for DMA_INT_INT8.
mbed_official	146:f64d43ff0c18	2842	#define BS_DMA_INT_INT8 (1U) //!< Bit field size in bits for DMA_INT_INT8.
mbed_official	146:f64d43ff0c18	2843
mbed_official	146:f64d43ff0c18	2844	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2845	//! @brief Read current value of the DMA_INT_INT8 field.
mbed_official	146:f64d43ff0c18	2846	#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
mbed_official	146:f64d43ff0c18	2847	#endif
mbed_official	146:f64d43ff0c18	2848
mbed_official	146:f64d43ff0c18	2849	//! @brief Format value for bitfield DMA_INT_INT8.
mbed_official	146:f64d43ff0c18	2850	#define BF_DMA_INT_INT8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT8), uint32_t) & BM_DMA_INT_INT8)
mbed_official	146:f64d43ff0c18	2851
mbed_official	146:f64d43ff0c18	2852	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2853	//! @brief Set the INT8 field to a new value.
mbed_official	146:f64d43ff0c18	2854	#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
mbed_official	146:f64d43ff0c18	2855	#endif
mbed_official	146:f64d43ff0c18	2856	//@}
mbed_official	146:f64d43ff0c18	2857
mbed_official	146:f64d43ff0c18	2858	/*!
mbed_official	146:f64d43ff0c18	2859	* @name Register DMA_INT, field INT9[9] (W1C)
mbed_official	146:f64d43ff0c18	2860	*
mbed_official	146:f64d43ff0c18	2861	* Values:
mbed_official	146:f64d43ff0c18	2862	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2863	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2864	*/
mbed_official	146:f64d43ff0c18	2865	//@{
mbed_official	146:f64d43ff0c18	2866	#define BP_DMA_INT_INT9 (9U) //!< Bit position for DMA_INT_INT9.
mbed_official	146:f64d43ff0c18	2867	#define BM_DMA_INT_INT9 (0x00000200U) //!< Bit mask for DMA_INT_INT9.
mbed_official	146:f64d43ff0c18	2868	#define BS_DMA_INT_INT9 (1U) //!< Bit field size in bits for DMA_INT_INT9.
mbed_official	146:f64d43ff0c18	2869
mbed_official	146:f64d43ff0c18	2870	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2871	//! @brief Read current value of the DMA_INT_INT9 field.
mbed_official	146:f64d43ff0c18	2872	#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
mbed_official	146:f64d43ff0c18	2873	#endif
mbed_official	146:f64d43ff0c18	2874
mbed_official	146:f64d43ff0c18	2875	//! @brief Format value for bitfield DMA_INT_INT9.
mbed_official	146:f64d43ff0c18	2876	#define BF_DMA_INT_INT9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT9), uint32_t) & BM_DMA_INT_INT9)
mbed_official	146:f64d43ff0c18	2877
mbed_official	146:f64d43ff0c18	2878	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2879	//! @brief Set the INT9 field to a new value.
mbed_official	146:f64d43ff0c18	2880	#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
mbed_official	146:f64d43ff0c18	2881	#endif
mbed_official	146:f64d43ff0c18	2882	//@}
mbed_official	146:f64d43ff0c18	2883
mbed_official	146:f64d43ff0c18	2884	/*!
mbed_official	146:f64d43ff0c18	2885	* @name Register DMA_INT, field INT10[10] (W1C)
mbed_official	146:f64d43ff0c18	2886	*
mbed_official	146:f64d43ff0c18	2887	* Values:
mbed_official	146:f64d43ff0c18	2888	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2889	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2890	*/
mbed_official	146:f64d43ff0c18	2891	//@{
mbed_official	146:f64d43ff0c18	2892	#define BP_DMA_INT_INT10 (10U) //!< Bit position for DMA_INT_INT10.
mbed_official	146:f64d43ff0c18	2893	#define BM_DMA_INT_INT10 (0x00000400U) //!< Bit mask for DMA_INT_INT10.
mbed_official	146:f64d43ff0c18	2894	#define BS_DMA_INT_INT10 (1U) //!< Bit field size in bits for DMA_INT_INT10.
mbed_official	146:f64d43ff0c18	2895
mbed_official	146:f64d43ff0c18	2896	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2897	//! @brief Read current value of the DMA_INT_INT10 field.
mbed_official	146:f64d43ff0c18	2898	#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
mbed_official	146:f64d43ff0c18	2899	#endif
mbed_official	146:f64d43ff0c18	2900
mbed_official	146:f64d43ff0c18	2901	//! @brief Format value for bitfield DMA_INT_INT10.
mbed_official	146:f64d43ff0c18	2902	#define BF_DMA_INT_INT10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT10), uint32_t) & BM_DMA_INT_INT10)
mbed_official	146:f64d43ff0c18	2903
mbed_official	146:f64d43ff0c18	2904	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2905	//! @brief Set the INT10 field to a new value.
mbed_official	146:f64d43ff0c18	2906	#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
mbed_official	146:f64d43ff0c18	2907	#endif
mbed_official	146:f64d43ff0c18	2908	//@}
mbed_official	146:f64d43ff0c18	2909
mbed_official	146:f64d43ff0c18	2910	/*!
mbed_official	146:f64d43ff0c18	2911	* @name Register DMA_INT, field INT11[11] (W1C)
mbed_official	146:f64d43ff0c18	2912	*
mbed_official	146:f64d43ff0c18	2913	* Values:
mbed_official	146:f64d43ff0c18	2914	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2915	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2916	*/
mbed_official	146:f64d43ff0c18	2917	//@{
mbed_official	146:f64d43ff0c18	2918	#define BP_DMA_INT_INT11 (11U) //!< Bit position for DMA_INT_INT11.
mbed_official	146:f64d43ff0c18	2919	#define BM_DMA_INT_INT11 (0x00000800U) //!< Bit mask for DMA_INT_INT11.
mbed_official	146:f64d43ff0c18	2920	#define BS_DMA_INT_INT11 (1U) //!< Bit field size in bits for DMA_INT_INT11.
mbed_official	146:f64d43ff0c18	2921
mbed_official	146:f64d43ff0c18	2922	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2923	//! @brief Read current value of the DMA_INT_INT11 field.
mbed_official	146:f64d43ff0c18	2924	#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
mbed_official	146:f64d43ff0c18	2925	#endif
mbed_official	146:f64d43ff0c18	2926
mbed_official	146:f64d43ff0c18	2927	//! @brief Format value for bitfield DMA_INT_INT11.
mbed_official	146:f64d43ff0c18	2928	#define BF_DMA_INT_INT11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT11), uint32_t) & BM_DMA_INT_INT11)
mbed_official	146:f64d43ff0c18	2929
mbed_official	146:f64d43ff0c18	2930	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2931	//! @brief Set the INT11 field to a new value.
mbed_official	146:f64d43ff0c18	2932	#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
mbed_official	146:f64d43ff0c18	2933	#endif
mbed_official	146:f64d43ff0c18	2934	//@}
mbed_official	146:f64d43ff0c18	2935
mbed_official	146:f64d43ff0c18	2936	/*!
mbed_official	146:f64d43ff0c18	2937	* @name Register DMA_INT, field INT12[12] (W1C)
mbed_official	146:f64d43ff0c18	2938	*
mbed_official	146:f64d43ff0c18	2939	* Values:
mbed_official	146:f64d43ff0c18	2940	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2941	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2942	*/
mbed_official	146:f64d43ff0c18	2943	//@{
mbed_official	146:f64d43ff0c18	2944	#define BP_DMA_INT_INT12 (12U) //!< Bit position for DMA_INT_INT12.
mbed_official	146:f64d43ff0c18	2945	#define BM_DMA_INT_INT12 (0x00001000U) //!< Bit mask for DMA_INT_INT12.
mbed_official	146:f64d43ff0c18	2946	#define BS_DMA_INT_INT12 (1U) //!< Bit field size in bits for DMA_INT_INT12.
mbed_official	146:f64d43ff0c18	2947
mbed_official	146:f64d43ff0c18	2948	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2949	//! @brief Read current value of the DMA_INT_INT12 field.
mbed_official	146:f64d43ff0c18	2950	#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
mbed_official	146:f64d43ff0c18	2951	#endif
mbed_official	146:f64d43ff0c18	2952
mbed_official	146:f64d43ff0c18	2953	//! @brief Format value for bitfield DMA_INT_INT12.
mbed_official	146:f64d43ff0c18	2954	#define BF_DMA_INT_INT12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT12), uint32_t) & BM_DMA_INT_INT12)
mbed_official	146:f64d43ff0c18	2955
mbed_official	146:f64d43ff0c18	2956	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2957	//! @brief Set the INT12 field to a new value.
mbed_official	146:f64d43ff0c18	2958	#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
mbed_official	146:f64d43ff0c18	2959	#endif
mbed_official	146:f64d43ff0c18	2960	//@}
mbed_official	146:f64d43ff0c18	2961
mbed_official	146:f64d43ff0c18	2962	/*!
mbed_official	146:f64d43ff0c18	2963	* @name Register DMA_INT, field INT13[13] (W1C)
mbed_official	146:f64d43ff0c18	2964	*
mbed_official	146:f64d43ff0c18	2965	* Values:
mbed_official	146:f64d43ff0c18	2966	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2967	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2968	*/
mbed_official	146:f64d43ff0c18	2969	//@{
mbed_official	146:f64d43ff0c18	2970	#define BP_DMA_INT_INT13 (13U) //!< Bit position for DMA_INT_INT13.
mbed_official	146:f64d43ff0c18	2971	#define BM_DMA_INT_INT13 (0x00002000U) //!< Bit mask for DMA_INT_INT13.
mbed_official	146:f64d43ff0c18	2972	#define BS_DMA_INT_INT13 (1U) //!< Bit field size in bits for DMA_INT_INT13.
mbed_official	146:f64d43ff0c18	2973
mbed_official	146:f64d43ff0c18	2974	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2975	//! @brief Read current value of the DMA_INT_INT13 field.
mbed_official	146:f64d43ff0c18	2976	#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
mbed_official	146:f64d43ff0c18	2977	#endif
mbed_official	146:f64d43ff0c18	2978
mbed_official	146:f64d43ff0c18	2979	//! @brief Format value for bitfield DMA_INT_INT13.
mbed_official	146:f64d43ff0c18	2980	#define BF_DMA_INT_INT13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT13), uint32_t) & BM_DMA_INT_INT13)
mbed_official	146:f64d43ff0c18	2981
mbed_official	146:f64d43ff0c18	2982	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2983	//! @brief Set the INT13 field to a new value.
mbed_official	146:f64d43ff0c18	2984	#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
mbed_official	146:f64d43ff0c18	2985	#endif
mbed_official	146:f64d43ff0c18	2986	//@}
mbed_official	146:f64d43ff0c18	2987
mbed_official	146:f64d43ff0c18	2988	/*!
mbed_official	146:f64d43ff0c18	2989	* @name Register DMA_INT, field INT14[14] (W1C)
mbed_official	146:f64d43ff0c18	2990	*
mbed_official	146:f64d43ff0c18	2991	* Values:
mbed_official	146:f64d43ff0c18	2992	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	2993	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	2994	*/
mbed_official	146:f64d43ff0c18	2995	//@{
mbed_official	146:f64d43ff0c18	2996	#define BP_DMA_INT_INT14 (14U) //!< Bit position for DMA_INT_INT14.
mbed_official	146:f64d43ff0c18	2997	#define BM_DMA_INT_INT14 (0x00004000U) //!< Bit mask for DMA_INT_INT14.
mbed_official	146:f64d43ff0c18	2998	#define BS_DMA_INT_INT14 (1U) //!< Bit field size in bits for DMA_INT_INT14.
mbed_official	146:f64d43ff0c18	2999
mbed_official	146:f64d43ff0c18	3000	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3001	//! @brief Read current value of the DMA_INT_INT14 field.
mbed_official	146:f64d43ff0c18	3002	#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
mbed_official	146:f64d43ff0c18	3003	#endif
mbed_official	146:f64d43ff0c18	3004
mbed_official	146:f64d43ff0c18	3005	//! @brief Format value for bitfield DMA_INT_INT14.
mbed_official	146:f64d43ff0c18	3006	#define BF_DMA_INT_INT14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT14), uint32_t) & BM_DMA_INT_INT14)
mbed_official	146:f64d43ff0c18	3007
mbed_official	146:f64d43ff0c18	3008	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3009	//! @brief Set the INT14 field to a new value.
mbed_official	146:f64d43ff0c18	3010	#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
mbed_official	146:f64d43ff0c18	3011	#endif
mbed_official	146:f64d43ff0c18	3012	//@}
mbed_official	146:f64d43ff0c18	3013
mbed_official	146:f64d43ff0c18	3014	/*!
mbed_official	146:f64d43ff0c18	3015	* @name Register DMA_INT, field INT15[15] (W1C)
mbed_official	146:f64d43ff0c18	3016	*
mbed_official	146:f64d43ff0c18	3017	* Values:
mbed_official	146:f64d43ff0c18	3018	* - 0 - The interrupt request for corresponding channel is cleared
mbed_official	146:f64d43ff0c18	3019	* - 1 - The interrupt request for corresponding channel is active
mbed_official	146:f64d43ff0c18	3020	*/
mbed_official	146:f64d43ff0c18	3021	//@{
mbed_official	146:f64d43ff0c18	3022	#define BP_DMA_INT_INT15 (15U) //!< Bit position for DMA_INT_INT15.
mbed_official	146:f64d43ff0c18	3023	#define BM_DMA_INT_INT15 (0x00008000U) //!< Bit mask for DMA_INT_INT15.
mbed_official	146:f64d43ff0c18	3024	#define BS_DMA_INT_INT15 (1U) //!< Bit field size in bits for DMA_INT_INT15.
mbed_official	146:f64d43ff0c18	3025
mbed_official	146:f64d43ff0c18	3026	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3027	//! @brief Read current value of the DMA_INT_INT15 field.
mbed_official	146:f64d43ff0c18	3028	#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
mbed_official	146:f64d43ff0c18	3029	#endif
mbed_official	146:f64d43ff0c18	3030
mbed_official	146:f64d43ff0c18	3031	//! @brief Format value for bitfield DMA_INT_INT15.
mbed_official	146:f64d43ff0c18	3032	#define BF_DMA_INT_INT15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT15), uint32_t) & BM_DMA_INT_INT15)
mbed_official	146:f64d43ff0c18	3033
mbed_official	146:f64d43ff0c18	3034	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3035	//! @brief Set the INT15 field to a new value.
mbed_official	146:f64d43ff0c18	3036	#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
mbed_official	146:f64d43ff0c18	3037	#endif
mbed_official	146:f64d43ff0c18	3038	//@}
mbed_official	146:f64d43ff0c18	3039
mbed_official	146:f64d43ff0c18	3040	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3041	// HW_DMA_ERR - Error Register
mbed_official	146:f64d43ff0c18	3042	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3043
mbed_official	146:f64d43ff0c18	3044	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3045	/*!
mbed_official	146:f64d43ff0c18	3046	* @brief HW_DMA_ERR - Error Register (RW)
mbed_official	146:f64d43ff0c18	3047	*
mbed_official	146:f64d43ff0c18	3048	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3049	*
mbed_official	146:f64d43ff0c18	3050	* The ERR provides a bit map for the 16 channels, signaling the presence of an
mbed_official	146:f64d43ff0c18	3051	* error for each channel. The eDMA engine signals the occurrence of an error
mbed_official	146:f64d43ff0c18	3052	* condition by setting the appropriate bit in this register. The outputs of this
mbed_official	146:f64d43ff0c18	3053	* register are enabled by the contents of the EEI, and then routed to the
mbed_official	146:f64d43ff0c18	3054	* interrupt controller. During the execution of the interrupt-service routine associated
mbed_official	146:f64d43ff0c18	3055	* with any DMA errors, it is software's responsibility to clear the appropriate
mbed_official	146:f64d43ff0c18	3056	* bit, negating the error-interrupt request. Typically, a write to the CERR in
mbed_official	146:f64d43ff0c18	3057	* the interrupt-service routine is used for this purpose. The normal DMA channel
mbed_official	146:f64d43ff0c18	3058	* completion indicators (setting the transfer control descriptor DONE flag and
mbed_official	146:f64d43ff0c18	3059	* the possible assertion of an interrupt request) are not affected when an error
mbed_official	146:f64d43ff0c18	3060	* is detected. The contents of this register can also be polled because a
mbed_official	146:f64d43ff0c18	3061	* non-zero value indicates the presence of a channel error regardless of the state of
mbed_official	146:f64d43ff0c18	3062	* the EEI. The state of any given channel's error indicators is affected by
mbed_official	146:f64d43ff0c18	3063	* writes to this register; it is also affected by writes to the CERR. On writes to
mbed_official	146:f64d43ff0c18	3064	* the ERR, a one in any bit position clears the corresponding channel's error
mbed_official	146:f64d43ff0c18	3065	* status. A zero in any bit position has no affect on the corresponding channel's
mbed_official	146:f64d43ff0c18	3066	* current error status. The CERR is provided so the error indicator for a single
mbed_official	146:f64d43ff0c18	3067	* channel can easily be cleared.
mbed_official	146:f64d43ff0c18	3068	*/
mbed_official	146:f64d43ff0c18	3069	typedef union _hw_dma_err
mbed_official	146:f64d43ff0c18	3070	{
mbed_official	146:f64d43ff0c18	3071	uint32_t U;
mbed_official	146:f64d43ff0c18	3072	struct _hw_dma_err_bitfields
mbed_official	146:f64d43ff0c18	3073	{
mbed_official	146:f64d43ff0c18	3074	uint32_t ERR0 : 1; //!< [0] Error In Channel 0
mbed_official	146:f64d43ff0c18	3075	uint32_t ERR1 : 1; //!< [1] Error In Channel 1
mbed_official	146:f64d43ff0c18	3076	uint32_t ERR2 : 1; //!< [2] Error In Channel 2
mbed_official	146:f64d43ff0c18	3077	uint32_t ERR3 : 1; //!< [3] Error In Channel 3
mbed_official	146:f64d43ff0c18	3078	uint32_t ERR4 : 1; //!< [4] Error In Channel 4
mbed_official	146:f64d43ff0c18	3079	uint32_t ERR5 : 1; //!< [5] Error In Channel 5
mbed_official	146:f64d43ff0c18	3080	uint32_t ERR6 : 1; //!< [6] Error In Channel 6
mbed_official	146:f64d43ff0c18	3081	uint32_t ERR7 : 1; //!< [7] Error In Channel 7
mbed_official	146:f64d43ff0c18	3082	uint32_t ERR8 : 1; //!< [8] Error In Channel 8
mbed_official	146:f64d43ff0c18	3083	uint32_t ERR9 : 1; //!< [9] Error In Channel 9
mbed_official	146:f64d43ff0c18	3084	uint32_t ERR10 : 1; //!< [10] Error In Channel 10
mbed_official	146:f64d43ff0c18	3085	uint32_t ERR11 : 1; //!< [11] Error In Channel 11
mbed_official	146:f64d43ff0c18	3086	uint32_t ERR12 : 1; //!< [12] Error In Channel 12
mbed_official	146:f64d43ff0c18	3087	uint32_t ERR13 : 1; //!< [13] Error In Channel 13
mbed_official	146:f64d43ff0c18	3088	uint32_t ERR14 : 1; //!< [14] Error In Channel 14
mbed_official	146:f64d43ff0c18	3089	uint32_t ERR15 : 1; //!< [15] Error In Channel 15
mbed_official	146:f64d43ff0c18	3090	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	3091	} B;
mbed_official	146:f64d43ff0c18	3092	} hw_dma_err_t;
mbed_official	146:f64d43ff0c18	3093	#endif
mbed_official	146:f64d43ff0c18	3094
mbed_official	146:f64d43ff0c18	3095	/*!
mbed_official	146:f64d43ff0c18	3096	* @name Constants and macros for entire DMA_ERR register
mbed_official	146:f64d43ff0c18	3097	*/
mbed_official	146:f64d43ff0c18	3098	//@{
mbed_official	146:f64d43ff0c18	3099	#define HW_DMA_ERR_ADDR(x) (REGS_DMA_BASE(x) + 0x2CU)
mbed_official	146:f64d43ff0c18	3100
mbed_official	146:f64d43ff0c18	3101	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3102	#define HW_DMA_ERR(x) ((__IO hw_dma_err_t ) HW_DMA_ERR_ADDR(x))
mbed_official	146:f64d43ff0c18	3103	#define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
mbed_official	146:f64d43ff0c18	3104	#define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
mbed_official	146:f64d43ff0c18	3105	#define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3106	#define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3107	#define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3108	#endif
mbed_official	146:f64d43ff0c18	3109	//@}
mbed_official	146:f64d43ff0c18	3110
mbed_official	146:f64d43ff0c18	3111	/*
mbed_official	146:f64d43ff0c18	3112	* Constants & macros for individual DMA_ERR bitfields
mbed_official	146:f64d43ff0c18	3113	*/
mbed_official	146:f64d43ff0c18	3114
mbed_official	146:f64d43ff0c18	3115	/*!
mbed_official	146:f64d43ff0c18	3116	* @name Register DMA_ERR, field ERR0[0] (W1C)
mbed_official	146:f64d43ff0c18	3117	*
mbed_official	146:f64d43ff0c18	3118	* Values:
mbed_official	146:f64d43ff0c18	3119	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3120	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3121	*/
mbed_official	146:f64d43ff0c18	3122	//@{
mbed_official	146:f64d43ff0c18	3123	#define BP_DMA_ERR_ERR0 (0U) //!< Bit position for DMA_ERR_ERR0.
mbed_official	146:f64d43ff0c18	3124	#define BM_DMA_ERR_ERR0 (0x00000001U) //!< Bit mask for DMA_ERR_ERR0.
mbed_official	146:f64d43ff0c18	3125	#define BS_DMA_ERR_ERR0 (1U) //!< Bit field size in bits for DMA_ERR_ERR0.
mbed_official	146:f64d43ff0c18	3126
mbed_official	146:f64d43ff0c18	3127	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3128	//! @brief Read current value of the DMA_ERR_ERR0 field.
mbed_official	146:f64d43ff0c18	3129	#define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
mbed_official	146:f64d43ff0c18	3130	#endif
mbed_official	146:f64d43ff0c18	3131
mbed_official	146:f64d43ff0c18	3132	//! @brief Format value for bitfield DMA_ERR_ERR0.
mbed_official	146:f64d43ff0c18	3133	#define BF_DMA_ERR_ERR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR0), uint32_t) & BM_DMA_ERR_ERR0)
mbed_official	146:f64d43ff0c18	3134
mbed_official	146:f64d43ff0c18	3135	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3136	//! @brief Set the ERR0 field to a new value.
mbed_official	146:f64d43ff0c18	3137	#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
mbed_official	146:f64d43ff0c18	3138	#endif
mbed_official	146:f64d43ff0c18	3139	//@}
mbed_official	146:f64d43ff0c18	3140
mbed_official	146:f64d43ff0c18	3141	/*!
mbed_official	146:f64d43ff0c18	3142	* @name Register DMA_ERR, field ERR1[1] (W1C)
mbed_official	146:f64d43ff0c18	3143	*
mbed_official	146:f64d43ff0c18	3144	* Values:
mbed_official	146:f64d43ff0c18	3145	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3146	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3147	*/
mbed_official	146:f64d43ff0c18	3148	//@{
mbed_official	146:f64d43ff0c18	3149	#define BP_DMA_ERR_ERR1 (1U) //!< Bit position for DMA_ERR_ERR1.
mbed_official	146:f64d43ff0c18	3150	#define BM_DMA_ERR_ERR1 (0x00000002U) //!< Bit mask for DMA_ERR_ERR1.
mbed_official	146:f64d43ff0c18	3151	#define BS_DMA_ERR_ERR1 (1U) //!< Bit field size in bits for DMA_ERR_ERR1.
mbed_official	146:f64d43ff0c18	3152
mbed_official	146:f64d43ff0c18	3153	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3154	//! @brief Read current value of the DMA_ERR_ERR1 field.
mbed_official	146:f64d43ff0c18	3155	#define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
mbed_official	146:f64d43ff0c18	3156	#endif
mbed_official	146:f64d43ff0c18	3157
mbed_official	146:f64d43ff0c18	3158	//! @brief Format value for bitfield DMA_ERR_ERR1.
mbed_official	146:f64d43ff0c18	3159	#define BF_DMA_ERR_ERR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR1), uint32_t) & BM_DMA_ERR_ERR1)
mbed_official	146:f64d43ff0c18	3160
mbed_official	146:f64d43ff0c18	3161	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3162	//! @brief Set the ERR1 field to a new value.
mbed_official	146:f64d43ff0c18	3163	#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
mbed_official	146:f64d43ff0c18	3164	#endif
mbed_official	146:f64d43ff0c18	3165	//@}
mbed_official	146:f64d43ff0c18	3166
mbed_official	146:f64d43ff0c18	3167	/*!
mbed_official	146:f64d43ff0c18	3168	* @name Register DMA_ERR, field ERR2[2] (W1C)
mbed_official	146:f64d43ff0c18	3169	*
mbed_official	146:f64d43ff0c18	3170	* Values:
mbed_official	146:f64d43ff0c18	3171	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3172	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3173	*/
mbed_official	146:f64d43ff0c18	3174	//@{
mbed_official	146:f64d43ff0c18	3175	#define BP_DMA_ERR_ERR2 (2U) //!< Bit position for DMA_ERR_ERR2.
mbed_official	146:f64d43ff0c18	3176	#define BM_DMA_ERR_ERR2 (0x00000004U) //!< Bit mask for DMA_ERR_ERR2.
mbed_official	146:f64d43ff0c18	3177	#define BS_DMA_ERR_ERR2 (1U) //!< Bit field size in bits for DMA_ERR_ERR2.
mbed_official	146:f64d43ff0c18	3178
mbed_official	146:f64d43ff0c18	3179	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3180	//! @brief Read current value of the DMA_ERR_ERR2 field.
mbed_official	146:f64d43ff0c18	3181	#define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
mbed_official	146:f64d43ff0c18	3182	#endif
mbed_official	146:f64d43ff0c18	3183
mbed_official	146:f64d43ff0c18	3184	//! @brief Format value for bitfield DMA_ERR_ERR2.
mbed_official	146:f64d43ff0c18	3185	#define BF_DMA_ERR_ERR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR2), uint32_t) & BM_DMA_ERR_ERR2)
mbed_official	146:f64d43ff0c18	3186
mbed_official	146:f64d43ff0c18	3187	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3188	//! @brief Set the ERR2 field to a new value.
mbed_official	146:f64d43ff0c18	3189	#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
mbed_official	146:f64d43ff0c18	3190	#endif
mbed_official	146:f64d43ff0c18	3191	//@}
mbed_official	146:f64d43ff0c18	3192
mbed_official	146:f64d43ff0c18	3193	/*!
mbed_official	146:f64d43ff0c18	3194	* @name Register DMA_ERR, field ERR3[3] (W1C)
mbed_official	146:f64d43ff0c18	3195	*
mbed_official	146:f64d43ff0c18	3196	* Values:
mbed_official	146:f64d43ff0c18	3197	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3198	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3199	*/
mbed_official	146:f64d43ff0c18	3200	//@{
mbed_official	146:f64d43ff0c18	3201	#define BP_DMA_ERR_ERR3 (3U) //!< Bit position for DMA_ERR_ERR3.
mbed_official	146:f64d43ff0c18	3202	#define BM_DMA_ERR_ERR3 (0x00000008U) //!< Bit mask for DMA_ERR_ERR3.
mbed_official	146:f64d43ff0c18	3203	#define BS_DMA_ERR_ERR3 (1U) //!< Bit field size in bits for DMA_ERR_ERR3.
mbed_official	146:f64d43ff0c18	3204
mbed_official	146:f64d43ff0c18	3205	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3206	//! @brief Read current value of the DMA_ERR_ERR3 field.
mbed_official	146:f64d43ff0c18	3207	#define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
mbed_official	146:f64d43ff0c18	3208	#endif
mbed_official	146:f64d43ff0c18	3209
mbed_official	146:f64d43ff0c18	3210	//! @brief Format value for bitfield DMA_ERR_ERR3.
mbed_official	146:f64d43ff0c18	3211	#define BF_DMA_ERR_ERR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR3), uint32_t) & BM_DMA_ERR_ERR3)
mbed_official	146:f64d43ff0c18	3212
mbed_official	146:f64d43ff0c18	3213	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3214	//! @brief Set the ERR3 field to a new value.
mbed_official	146:f64d43ff0c18	3215	#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
mbed_official	146:f64d43ff0c18	3216	#endif
mbed_official	146:f64d43ff0c18	3217	//@}
mbed_official	146:f64d43ff0c18	3218
mbed_official	146:f64d43ff0c18	3219	/*!
mbed_official	146:f64d43ff0c18	3220	* @name Register DMA_ERR, field ERR4[4] (W1C)
mbed_official	146:f64d43ff0c18	3221	*
mbed_official	146:f64d43ff0c18	3222	* Values:
mbed_official	146:f64d43ff0c18	3223	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3224	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3225	*/
mbed_official	146:f64d43ff0c18	3226	//@{
mbed_official	146:f64d43ff0c18	3227	#define BP_DMA_ERR_ERR4 (4U) //!< Bit position for DMA_ERR_ERR4.
mbed_official	146:f64d43ff0c18	3228	#define BM_DMA_ERR_ERR4 (0x00000010U) //!< Bit mask for DMA_ERR_ERR4.
mbed_official	146:f64d43ff0c18	3229	#define BS_DMA_ERR_ERR4 (1U) //!< Bit field size in bits for DMA_ERR_ERR4.
mbed_official	146:f64d43ff0c18	3230
mbed_official	146:f64d43ff0c18	3231	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3232	//! @brief Read current value of the DMA_ERR_ERR4 field.
mbed_official	146:f64d43ff0c18	3233	#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
mbed_official	146:f64d43ff0c18	3234	#endif
mbed_official	146:f64d43ff0c18	3235
mbed_official	146:f64d43ff0c18	3236	//! @brief Format value for bitfield DMA_ERR_ERR4.
mbed_official	146:f64d43ff0c18	3237	#define BF_DMA_ERR_ERR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR4), uint32_t) & BM_DMA_ERR_ERR4)
mbed_official	146:f64d43ff0c18	3238
mbed_official	146:f64d43ff0c18	3239	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3240	//! @brief Set the ERR4 field to a new value.
mbed_official	146:f64d43ff0c18	3241	#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
mbed_official	146:f64d43ff0c18	3242	#endif
mbed_official	146:f64d43ff0c18	3243	//@}
mbed_official	146:f64d43ff0c18	3244
mbed_official	146:f64d43ff0c18	3245	/*!
mbed_official	146:f64d43ff0c18	3246	* @name Register DMA_ERR, field ERR5[5] (W1C)
mbed_official	146:f64d43ff0c18	3247	*
mbed_official	146:f64d43ff0c18	3248	* Values:
mbed_official	146:f64d43ff0c18	3249	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3250	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3251	*/
mbed_official	146:f64d43ff0c18	3252	//@{
mbed_official	146:f64d43ff0c18	3253	#define BP_DMA_ERR_ERR5 (5U) //!< Bit position for DMA_ERR_ERR5.
mbed_official	146:f64d43ff0c18	3254	#define BM_DMA_ERR_ERR5 (0x00000020U) //!< Bit mask for DMA_ERR_ERR5.
mbed_official	146:f64d43ff0c18	3255	#define BS_DMA_ERR_ERR5 (1U) //!< Bit field size in bits for DMA_ERR_ERR5.
mbed_official	146:f64d43ff0c18	3256
mbed_official	146:f64d43ff0c18	3257	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3258	//! @brief Read current value of the DMA_ERR_ERR5 field.
mbed_official	146:f64d43ff0c18	3259	#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
mbed_official	146:f64d43ff0c18	3260	#endif
mbed_official	146:f64d43ff0c18	3261
mbed_official	146:f64d43ff0c18	3262	//! @brief Format value for bitfield DMA_ERR_ERR5.
mbed_official	146:f64d43ff0c18	3263	#define BF_DMA_ERR_ERR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR5), uint32_t) & BM_DMA_ERR_ERR5)
mbed_official	146:f64d43ff0c18	3264
mbed_official	146:f64d43ff0c18	3265	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3266	//! @brief Set the ERR5 field to a new value.
mbed_official	146:f64d43ff0c18	3267	#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
mbed_official	146:f64d43ff0c18	3268	#endif
mbed_official	146:f64d43ff0c18	3269	//@}
mbed_official	146:f64d43ff0c18	3270
mbed_official	146:f64d43ff0c18	3271	/*!
mbed_official	146:f64d43ff0c18	3272	* @name Register DMA_ERR, field ERR6[6] (W1C)
mbed_official	146:f64d43ff0c18	3273	*
mbed_official	146:f64d43ff0c18	3274	* Values:
mbed_official	146:f64d43ff0c18	3275	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3276	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3277	*/
mbed_official	146:f64d43ff0c18	3278	//@{
mbed_official	146:f64d43ff0c18	3279	#define BP_DMA_ERR_ERR6 (6U) //!< Bit position for DMA_ERR_ERR6.
mbed_official	146:f64d43ff0c18	3280	#define BM_DMA_ERR_ERR6 (0x00000040U) //!< Bit mask for DMA_ERR_ERR6.
mbed_official	146:f64d43ff0c18	3281	#define BS_DMA_ERR_ERR6 (1U) //!< Bit field size in bits for DMA_ERR_ERR6.
mbed_official	146:f64d43ff0c18	3282
mbed_official	146:f64d43ff0c18	3283	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3284	//! @brief Read current value of the DMA_ERR_ERR6 field.
mbed_official	146:f64d43ff0c18	3285	#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
mbed_official	146:f64d43ff0c18	3286	#endif
mbed_official	146:f64d43ff0c18	3287
mbed_official	146:f64d43ff0c18	3288	//! @brief Format value for bitfield DMA_ERR_ERR6.
mbed_official	146:f64d43ff0c18	3289	#define BF_DMA_ERR_ERR6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR6), uint32_t) & BM_DMA_ERR_ERR6)
mbed_official	146:f64d43ff0c18	3290
mbed_official	146:f64d43ff0c18	3291	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3292	//! @brief Set the ERR6 field to a new value.
mbed_official	146:f64d43ff0c18	3293	#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
mbed_official	146:f64d43ff0c18	3294	#endif
mbed_official	146:f64d43ff0c18	3295	//@}
mbed_official	146:f64d43ff0c18	3296
mbed_official	146:f64d43ff0c18	3297	/*!
mbed_official	146:f64d43ff0c18	3298	* @name Register DMA_ERR, field ERR7[7] (W1C)
mbed_official	146:f64d43ff0c18	3299	*
mbed_official	146:f64d43ff0c18	3300	* Values:
mbed_official	146:f64d43ff0c18	3301	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3302	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3303	*/
mbed_official	146:f64d43ff0c18	3304	//@{
mbed_official	146:f64d43ff0c18	3305	#define BP_DMA_ERR_ERR7 (7U) //!< Bit position for DMA_ERR_ERR7.
mbed_official	146:f64d43ff0c18	3306	#define BM_DMA_ERR_ERR7 (0x00000080U) //!< Bit mask for DMA_ERR_ERR7.
mbed_official	146:f64d43ff0c18	3307	#define BS_DMA_ERR_ERR7 (1U) //!< Bit field size in bits for DMA_ERR_ERR7.
mbed_official	146:f64d43ff0c18	3308
mbed_official	146:f64d43ff0c18	3309	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3310	//! @brief Read current value of the DMA_ERR_ERR7 field.
mbed_official	146:f64d43ff0c18	3311	#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
mbed_official	146:f64d43ff0c18	3312	#endif
mbed_official	146:f64d43ff0c18	3313
mbed_official	146:f64d43ff0c18	3314	//! @brief Format value for bitfield DMA_ERR_ERR7.
mbed_official	146:f64d43ff0c18	3315	#define BF_DMA_ERR_ERR7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR7), uint32_t) & BM_DMA_ERR_ERR7)
mbed_official	146:f64d43ff0c18	3316
mbed_official	146:f64d43ff0c18	3317	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3318	//! @brief Set the ERR7 field to a new value.
mbed_official	146:f64d43ff0c18	3319	#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
mbed_official	146:f64d43ff0c18	3320	#endif
mbed_official	146:f64d43ff0c18	3321	//@}
mbed_official	146:f64d43ff0c18	3322
mbed_official	146:f64d43ff0c18	3323	/*!
mbed_official	146:f64d43ff0c18	3324	* @name Register DMA_ERR, field ERR8[8] (W1C)
mbed_official	146:f64d43ff0c18	3325	*
mbed_official	146:f64d43ff0c18	3326	* Values:
mbed_official	146:f64d43ff0c18	3327	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3328	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3329	*/
mbed_official	146:f64d43ff0c18	3330	//@{
mbed_official	146:f64d43ff0c18	3331	#define BP_DMA_ERR_ERR8 (8U) //!< Bit position for DMA_ERR_ERR8.
mbed_official	146:f64d43ff0c18	3332	#define BM_DMA_ERR_ERR8 (0x00000100U) //!< Bit mask for DMA_ERR_ERR8.
mbed_official	146:f64d43ff0c18	3333	#define BS_DMA_ERR_ERR8 (1U) //!< Bit field size in bits for DMA_ERR_ERR8.
mbed_official	146:f64d43ff0c18	3334
mbed_official	146:f64d43ff0c18	3335	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3336	//! @brief Read current value of the DMA_ERR_ERR8 field.
mbed_official	146:f64d43ff0c18	3337	#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
mbed_official	146:f64d43ff0c18	3338	#endif
mbed_official	146:f64d43ff0c18	3339
mbed_official	146:f64d43ff0c18	3340	//! @brief Format value for bitfield DMA_ERR_ERR8.
mbed_official	146:f64d43ff0c18	3341	#define BF_DMA_ERR_ERR8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR8), uint32_t) & BM_DMA_ERR_ERR8)
mbed_official	146:f64d43ff0c18	3342
mbed_official	146:f64d43ff0c18	3343	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3344	//! @brief Set the ERR8 field to a new value.
mbed_official	146:f64d43ff0c18	3345	#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
mbed_official	146:f64d43ff0c18	3346	#endif
mbed_official	146:f64d43ff0c18	3347	//@}
mbed_official	146:f64d43ff0c18	3348
mbed_official	146:f64d43ff0c18	3349	/*!
mbed_official	146:f64d43ff0c18	3350	* @name Register DMA_ERR, field ERR9[9] (W1C)
mbed_official	146:f64d43ff0c18	3351	*
mbed_official	146:f64d43ff0c18	3352	* Values:
mbed_official	146:f64d43ff0c18	3353	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3354	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3355	*/
mbed_official	146:f64d43ff0c18	3356	//@{
mbed_official	146:f64d43ff0c18	3357	#define BP_DMA_ERR_ERR9 (9U) //!< Bit position for DMA_ERR_ERR9.
mbed_official	146:f64d43ff0c18	3358	#define BM_DMA_ERR_ERR9 (0x00000200U) //!< Bit mask for DMA_ERR_ERR9.
mbed_official	146:f64d43ff0c18	3359	#define BS_DMA_ERR_ERR9 (1U) //!< Bit field size in bits for DMA_ERR_ERR9.
mbed_official	146:f64d43ff0c18	3360
mbed_official	146:f64d43ff0c18	3361	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3362	//! @brief Read current value of the DMA_ERR_ERR9 field.
mbed_official	146:f64d43ff0c18	3363	#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
mbed_official	146:f64d43ff0c18	3364	#endif
mbed_official	146:f64d43ff0c18	3365
mbed_official	146:f64d43ff0c18	3366	//! @brief Format value for bitfield DMA_ERR_ERR9.
mbed_official	146:f64d43ff0c18	3367	#define BF_DMA_ERR_ERR9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR9), uint32_t) & BM_DMA_ERR_ERR9)
mbed_official	146:f64d43ff0c18	3368
mbed_official	146:f64d43ff0c18	3369	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3370	//! @brief Set the ERR9 field to a new value.
mbed_official	146:f64d43ff0c18	3371	#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
mbed_official	146:f64d43ff0c18	3372	#endif
mbed_official	146:f64d43ff0c18	3373	//@}
mbed_official	146:f64d43ff0c18	3374
mbed_official	146:f64d43ff0c18	3375	/*!
mbed_official	146:f64d43ff0c18	3376	* @name Register DMA_ERR, field ERR10[10] (W1C)
mbed_official	146:f64d43ff0c18	3377	*
mbed_official	146:f64d43ff0c18	3378	* Values:
mbed_official	146:f64d43ff0c18	3379	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3380	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3381	*/
mbed_official	146:f64d43ff0c18	3382	//@{
mbed_official	146:f64d43ff0c18	3383	#define BP_DMA_ERR_ERR10 (10U) //!< Bit position for DMA_ERR_ERR10.
mbed_official	146:f64d43ff0c18	3384	#define BM_DMA_ERR_ERR10 (0x00000400U) //!< Bit mask for DMA_ERR_ERR10.
mbed_official	146:f64d43ff0c18	3385	#define BS_DMA_ERR_ERR10 (1U) //!< Bit field size in bits for DMA_ERR_ERR10.
mbed_official	146:f64d43ff0c18	3386
mbed_official	146:f64d43ff0c18	3387	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3388	//! @brief Read current value of the DMA_ERR_ERR10 field.
mbed_official	146:f64d43ff0c18	3389	#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
mbed_official	146:f64d43ff0c18	3390	#endif
mbed_official	146:f64d43ff0c18	3391
mbed_official	146:f64d43ff0c18	3392	//! @brief Format value for bitfield DMA_ERR_ERR10.
mbed_official	146:f64d43ff0c18	3393	#define BF_DMA_ERR_ERR10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR10), uint32_t) & BM_DMA_ERR_ERR10)
mbed_official	146:f64d43ff0c18	3394
mbed_official	146:f64d43ff0c18	3395	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3396	//! @brief Set the ERR10 field to a new value.
mbed_official	146:f64d43ff0c18	3397	#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
mbed_official	146:f64d43ff0c18	3398	#endif
mbed_official	146:f64d43ff0c18	3399	//@}
mbed_official	146:f64d43ff0c18	3400
mbed_official	146:f64d43ff0c18	3401	/*!
mbed_official	146:f64d43ff0c18	3402	* @name Register DMA_ERR, field ERR11[11] (W1C)
mbed_official	146:f64d43ff0c18	3403	*
mbed_official	146:f64d43ff0c18	3404	* Values:
mbed_official	146:f64d43ff0c18	3405	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3406	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3407	*/
mbed_official	146:f64d43ff0c18	3408	//@{
mbed_official	146:f64d43ff0c18	3409	#define BP_DMA_ERR_ERR11 (11U) //!< Bit position for DMA_ERR_ERR11.
mbed_official	146:f64d43ff0c18	3410	#define BM_DMA_ERR_ERR11 (0x00000800U) //!< Bit mask for DMA_ERR_ERR11.
mbed_official	146:f64d43ff0c18	3411	#define BS_DMA_ERR_ERR11 (1U) //!< Bit field size in bits for DMA_ERR_ERR11.
mbed_official	146:f64d43ff0c18	3412
mbed_official	146:f64d43ff0c18	3413	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3414	//! @brief Read current value of the DMA_ERR_ERR11 field.
mbed_official	146:f64d43ff0c18	3415	#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
mbed_official	146:f64d43ff0c18	3416	#endif
mbed_official	146:f64d43ff0c18	3417
mbed_official	146:f64d43ff0c18	3418	//! @brief Format value for bitfield DMA_ERR_ERR11.
mbed_official	146:f64d43ff0c18	3419	#define BF_DMA_ERR_ERR11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR11), uint32_t) & BM_DMA_ERR_ERR11)
mbed_official	146:f64d43ff0c18	3420
mbed_official	146:f64d43ff0c18	3421	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3422	//! @brief Set the ERR11 field to a new value.
mbed_official	146:f64d43ff0c18	3423	#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
mbed_official	146:f64d43ff0c18	3424	#endif
mbed_official	146:f64d43ff0c18	3425	//@}
mbed_official	146:f64d43ff0c18	3426
mbed_official	146:f64d43ff0c18	3427	/*!
mbed_official	146:f64d43ff0c18	3428	* @name Register DMA_ERR, field ERR12[12] (W1C)
mbed_official	146:f64d43ff0c18	3429	*
mbed_official	146:f64d43ff0c18	3430	* Values:
mbed_official	146:f64d43ff0c18	3431	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3432	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3433	*/
mbed_official	146:f64d43ff0c18	3434	//@{
mbed_official	146:f64d43ff0c18	3435	#define BP_DMA_ERR_ERR12 (12U) //!< Bit position for DMA_ERR_ERR12.
mbed_official	146:f64d43ff0c18	3436	#define BM_DMA_ERR_ERR12 (0x00001000U) //!< Bit mask for DMA_ERR_ERR12.
mbed_official	146:f64d43ff0c18	3437	#define BS_DMA_ERR_ERR12 (1U) //!< Bit field size in bits for DMA_ERR_ERR12.
mbed_official	146:f64d43ff0c18	3438
mbed_official	146:f64d43ff0c18	3439	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3440	//! @brief Read current value of the DMA_ERR_ERR12 field.
mbed_official	146:f64d43ff0c18	3441	#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
mbed_official	146:f64d43ff0c18	3442	#endif
mbed_official	146:f64d43ff0c18	3443
mbed_official	146:f64d43ff0c18	3444	//! @brief Format value for bitfield DMA_ERR_ERR12.
mbed_official	146:f64d43ff0c18	3445	#define BF_DMA_ERR_ERR12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR12), uint32_t) & BM_DMA_ERR_ERR12)
mbed_official	146:f64d43ff0c18	3446
mbed_official	146:f64d43ff0c18	3447	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3448	//! @brief Set the ERR12 field to a new value.
mbed_official	146:f64d43ff0c18	3449	#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
mbed_official	146:f64d43ff0c18	3450	#endif
mbed_official	146:f64d43ff0c18	3451	//@}
mbed_official	146:f64d43ff0c18	3452
mbed_official	146:f64d43ff0c18	3453	/*!
mbed_official	146:f64d43ff0c18	3454	* @name Register DMA_ERR, field ERR13[13] (W1C)
mbed_official	146:f64d43ff0c18	3455	*
mbed_official	146:f64d43ff0c18	3456	* Values:
mbed_official	146:f64d43ff0c18	3457	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3458	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3459	*/
mbed_official	146:f64d43ff0c18	3460	//@{
mbed_official	146:f64d43ff0c18	3461	#define BP_DMA_ERR_ERR13 (13U) //!< Bit position for DMA_ERR_ERR13.
mbed_official	146:f64d43ff0c18	3462	#define BM_DMA_ERR_ERR13 (0x00002000U) //!< Bit mask for DMA_ERR_ERR13.
mbed_official	146:f64d43ff0c18	3463	#define BS_DMA_ERR_ERR13 (1U) //!< Bit field size in bits for DMA_ERR_ERR13.
mbed_official	146:f64d43ff0c18	3464
mbed_official	146:f64d43ff0c18	3465	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3466	//! @brief Read current value of the DMA_ERR_ERR13 field.
mbed_official	146:f64d43ff0c18	3467	#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
mbed_official	146:f64d43ff0c18	3468	#endif
mbed_official	146:f64d43ff0c18	3469
mbed_official	146:f64d43ff0c18	3470	//! @brief Format value for bitfield DMA_ERR_ERR13.
mbed_official	146:f64d43ff0c18	3471	#define BF_DMA_ERR_ERR13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR13), uint32_t) & BM_DMA_ERR_ERR13)
mbed_official	146:f64d43ff0c18	3472
mbed_official	146:f64d43ff0c18	3473	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3474	//! @brief Set the ERR13 field to a new value.
mbed_official	146:f64d43ff0c18	3475	#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
mbed_official	146:f64d43ff0c18	3476	#endif
mbed_official	146:f64d43ff0c18	3477	//@}
mbed_official	146:f64d43ff0c18	3478
mbed_official	146:f64d43ff0c18	3479	/*!
mbed_official	146:f64d43ff0c18	3480	* @name Register DMA_ERR, field ERR14[14] (W1C)
mbed_official	146:f64d43ff0c18	3481	*
mbed_official	146:f64d43ff0c18	3482	* Values:
mbed_official	146:f64d43ff0c18	3483	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3484	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3485	*/
mbed_official	146:f64d43ff0c18	3486	//@{
mbed_official	146:f64d43ff0c18	3487	#define BP_DMA_ERR_ERR14 (14U) //!< Bit position for DMA_ERR_ERR14.
mbed_official	146:f64d43ff0c18	3488	#define BM_DMA_ERR_ERR14 (0x00004000U) //!< Bit mask for DMA_ERR_ERR14.
mbed_official	146:f64d43ff0c18	3489	#define BS_DMA_ERR_ERR14 (1U) //!< Bit field size in bits for DMA_ERR_ERR14.
mbed_official	146:f64d43ff0c18	3490
mbed_official	146:f64d43ff0c18	3491	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3492	//! @brief Read current value of the DMA_ERR_ERR14 field.
mbed_official	146:f64d43ff0c18	3493	#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
mbed_official	146:f64d43ff0c18	3494	#endif
mbed_official	146:f64d43ff0c18	3495
mbed_official	146:f64d43ff0c18	3496	//! @brief Format value for bitfield DMA_ERR_ERR14.
mbed_official	146:f64d43ff0c18	3497	#define BF_DMA_ERR_ERR14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR14), uint32_t) & BM_DMA_ERR_ERR14)
mbed_official	146:f64d43ff0c18	3498
mbed_official	146:f64d43ff0c18	3499	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3500	//! @brief Set the ERR14 field to a new value.
mbed_official	146:f64d43ff0c18	3501	#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
mbed_official	146:f64d43ff0c18	3502	#endif
mbed_official	146:f64d43ff0c18	3503	//@}
mbed_official	146:f64d43ff0c18	3504
mbed_official	146:f64d43ff0c18	3505	/*!
mbed_official	146:f64d43ff0c18	3506	* @name Register DMA_ERR, field ERR15[15] (W1C)
mbed_official	146:f64d43ff0c18	3507	*
mbed_official	146:f64d43ff0c18	3508	* Values:
mbed_official	146:f64d43ff0c18	3509	* - 0 - An error in the corresponding channel has not occurred
mbed_official	146:f64d43ff0c18	3510	* - 1 - An error in the corresponding channel has occurred
mbed_official	146:f64d43ff0c18	3511	*/
mbed_official	146:f64d43ff0c18	3512	//@{
mbed_official	146:f64d43ff0c18	3513	#define BP_DMA_ERR_ERR15 (15U) //!< Bit position for DMA_ERR_ERR15.
mbed_official	146:f64d43ff0c18	3514	#define BM_DMA_ERR_ERR15 (0x00008000U) //!< Bit mask for DMA_ERR_ERR15.
mbed_official	146:f64d43ff0c18	3515	#define BS_DMA_ERR_ERR15 (1U) //!< Bit field size in bits for DMA_ERR_ERR15.
mbed_official	146:f64d43ff0c18	3516
mbed_official	146:f64d43ff0c18	3517	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3518	//! @brief Read current value of the DMA_ERR_ERR15 field.
mbed_official	146:f64d43ff0c18	3519	#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
mbed_official	146:f64d43ff0c18	3520	#endif
mbed_official	146:f64d43ff0c18	3521
mbed_official	146:f64d43ff0c18	3522	//! @brief Format value for bitfield DMA_ERR_ERR15.
mbed_official	146:f64d43ff0c18	3523	#define BF_DMA_ERR_ERR15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR15), uint32_t) & BM_DMA_ERR_ERR15)
mbed_official	146:f64d43ff0c18	3524
mbed_official	146:f64d43ff0c18	3525	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3526	//! @brief Set the ERR15 field to a new value.
mbed_official	146:f64d43ff0c18	3527	#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
mbed_official	146:f64d43ff0c18	3528	#endif
mbed_official	146:f64d43ff0c18	3529	//@}
mbed_official	146:f64d43ff0c18	3530
mbed_official	146:f64d43ff0c18	3531	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3532	// HW_DMA_HRS - Hardware Request Status Register
mbed_official	146:f64d43ff0c18	3533	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3534
mbed_official	146:f64d43ff0c18	3535	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3536	/*!
mbed_official	146:f64d43ff0c18	3537	* @brief HW_DMA_HRS - Hardware Request Status Register (RO)
mbed_official	146:f64d43ff0c18	3538	*
mbed_official	146:f64d43ff0c18	3539	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3540	*
mbed_official	146:f64d43ff0c18	3541	* The HRS register provides a bit map for the DMA channels, signaling the
mbed_official	146:f64d43ff0c18	3542	* presence of a hardware request for each channel. The hardware request status bits
mbed_official	146:f64d43ff0c18	3543	* reflect the current state of the register and qualified (via the ERQ fields)
mbed_official	146:f64d43ff0c18	3544	* DMA request signals as seen by the DMA's arbitration logic. This view into the
mbed_official	146:f64d43ff0c18	3545	* hardware request signals may be used for debug purposes. These bits reflect the
mbed_official	146:f64d43ff0c18	3546	* state of the request as seen by the arbitration logic. Therefore, this status
mbed_official	146:f64d43ff0c18	3547	* is affected by the ERQ bits.
mbed_official	146:f64d43ff0c18	3548	*/
mbed_official	146:f64d43ff0c18	3549	typedef union _hw_dma_hrs
mbed_official	146:f64d43ff0c18	3550	{
mbed_official	146:f64d43ff0c18	3551	uint32_t U;
mbed_official	146:f64d43ff0c18	3552	struct _hw_dma_hrs_bitfields
mbed_official	146:f64d43ff0c18	3553	{
mbed_official	146:f64d43ff0c18	3554	uint32_t HRS0 : 1; //!< [0] Hardware Request Status Channel 0
mbed_official	146:f64d43ff0c18	3555	uint32_t HRS1 : 1; //!< [1] Hardware Request Status Channel 1
mbed_official	146:f64d43ff0c18	3556	uint32_t HRS2 : 1; //!< [2] Hardware Request Status Channel 2
mbed_official	146:f64d43ff0c18	3557	uint32_t HRS3 : 1; //!< [3] Hardware Request Status Channel 3
mbed_official	146:f64d43ff0c18	3558	uint32_t HRS4 : 1; //!< [4] Hardware Request Status Channel 4
mbed_official	146:f64d43ff0c18	3559	uint32_t HRS5 : 1; //!< [5] Hardware Request Status Channel 5
mbed_official	146:f64d43ff0c18	3560	uint32_t HRS6 : 1; //!< [6] Hardware Request Status Channel 6
mbed_official	146:f64d43ff0c18	3561	uint32_t HRS7 : 1; //!< [7] Hardware Request Status Channel 7
mbed_official	146:f64d43ff0c18	3562	uint32_t HRS8 : 1; //!< [8] Hardware Request Status Channel 8
mbed_official	146:f64d43ff0c18	3563	uint32_t HRS9 : 1; //!< [9] Hardware Request Status Channel 9
mbed_official	146:f64d43ff0c18	3564	uint32_t HRS10 : 1; //!< [10] Hardware Request Status Channel 10
mbed_official	146:f64d43ff0c18	3565	uint32_t HRS11 : 1; //!< [11] Hardware Request Status Channel 11
mbed_official	146:f64d43ff0c18	3566	uint32_t HRS12 : 1; //!< [12] Hardware Request Status Channel 12
mbed_official	146:f64d43ff0c18	3567	uint32_t HRS13 : 1; //!< [13] Hardware Request Status Channel 13
mbed_official	146:f64d43ff0c18	3568	uint32_t HRS14 : 1; //!< [14] Hardware Request Status Channel 14
mbed_official	146:f64d43ff0c18	3569	uint32_t HRS15 : 1; //!< [15] Hardware Request Status Channel 15
mbed_official	146:f64d43ff0c18	3570	uint32_t RESERVED0 : 16; //!< [31:16] Reserved
mbed_official	146:f64d43ff0c18	3571	} B;
mbed_official	146:f64d43ff0c18	3572	} hw_dma_hrs_t;
mbed_official	146:f64d43ff0c18	3573	#endif
mbed_official	146:f64d43ff0c18	3574
mbed_official	146:f64d43ff0c18	3575	/*!
mbed_official	146:f64d43ff0c18	3576	* @name Constants and macros for entire DMA_HRS register
mbed_official	146:f64d43ff0c18	3577	*/
mbed_official	146:f64d43ff0c18	3578	//@{
mbed_official	146:f64d43ff0c18	3579	#define HW_DMA_HRS_ADDR(x) (REGS_DMA_BASE(x) + 0x34U)
mbed_official	146:f64d43ff0c18	3580
mbed_official	146:f64d43ff0c18	3581	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3582	#define HW_DMA_HRS(x) ((__I hw_dma_hrs_t ) HW_DMA_HRS_ADDR(x))
mbed_official	146:f64d43ff0c18	3583	#define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
mbed_official	146:f64d43ff0c18	3584	#endif
mbed_official	146:f64d43ff0c18	3585	//@}
mbed_official	146:f64d43ff0c18	3586
mbed_official	146:f64d43ff0c18	3587	/*
mbed_official	146:f64d43ff0c18	3588	* Constants & macros for individual DMA_HRS bitfields
mbed_official	146:f64d43ff0c18	3589	*/
mbed_official	146:f64d43ff0c18	3590
mbed_official	146:f64d43ff0c18	3591	/*!
mbed_official	146:f64d43ff0c18	3592	* @name Register DMA_HRS, field HRS0[0] (RO)
mbed_official	146:f64d43ff0c18	3593	*
mbed_official	146:f64d43ff0c18	3594	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3595	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3596	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3597	*
mbed_official	146:f64d43ff0c18	3598	* Values:
mbed_official	146:f64d43ff0c18	3599	* - 0 - A hardware service request for channel 0 is not present
mbed_official	146:f64d43ff0c18	3600	* - 1 - A hardware service request for channel 0 is present
mbed_official	146:f64d43ff0c18	3601	*/
mbed_official	146:f64d43ff0c18	3602	//@{
mbed_official	146:f64d43ff0c18	3603	#define BP_DMA_HRS_HRS0 (0U) //!< Bit position for DMA_HRS_HRS0.
mbed_official	146:f64d43ff0c18	3604	#define BM_DMA_HRS_HRS0 (0x00000001U) //!< Bit mask for DMA_HRS_HRS0.
mbed_official	146:f64d43ff0c18	3605	#define BS_DMA_HRS_HRS0 (1U) //!< Bit field size in bits for DMA_HRS_HRS0.
mbed_official	146:f64d43ff0c18	3606
mbed_official	146:f64d43ff0c18	3607	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3608	//! @brief Read current value of the DMA_HRS_HRS0 field.
mbed_official	146:f64d43ff0c18	3609	#define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
mbed_official	146:f64d43ff0c18	3610	#endif
mbed_official	146:f64d43ff0c18	3611	//@}
mbed_official	146:f64d43ff0c18	3612
mbed_official	146:f64d43ff0c18	3613	/*!
mbed_official	146:f64d43ff0c18	3614	* @name Register DMA_HRS, field HRS1[1] (RO)
mbed_official	146:f64d43ff0c18	3615	*
mbed_official	146:f64d43ff0c18	3616	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3617	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3618	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3619	*
mbed_official	146:f64d43ff0c18	3620	* Values:
mbed_official	146:f64d43ff0c18	3621	* - 0 - A hardware service request for channel 1 is not present
mbed_official	146:f64d43ff0c18	3622	* - 1 - A hardware service request for channel 1 is present
mbed_official	146:f64d43ff0c18	3623	*/
mbed_official	146:f64d43ff0c18	3624	//@{
mbed_official	146:f64d43ff0c18	3625	#define BP_DMA_HRS_HRS1 (1U) //!< Bit position for DMA_HRS_HRS1.
mbed_official	146:f64d43ff0c18	3626	#define BM_DMA_HRS_HRS1 (0x00000002U) //!< Bit mask for DMA_HRS_HRS1.
mbed_official	146:f64d43ff0c18	3627	#define BS_DMA_HRS_HRS1 (1U) //!< Bit field size in bits for DMA_HRS_HRS1.
mbed_official	146:f64d43ff0c18	3628
mbed_official	146:f64d43ff0c18	3629	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3630	//! @brief Read current value of the DMA_HRS_HRS1 field.
mbed_official	146:f64d43ff0c18	3631	#define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
mbed_official	146:f64d43ff0c18	3632	#endif
mbed_official	146:f64d43ff0c18	3633	//@}
mbed_official	146:f64d43ff0c18	3634
mbed_official	146:f64d43ff0c18	3635	/*!
mbed_official	146:f64d43ff0c18	3636	* @name Register DMA_HRS, field HRS2[2] (RO)
mbed_official	146:f64d43ff0c18	3637	*
mbed_official	146:f64d43ff0c18	3638	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3639	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3640	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3641	*
mbed_official	146:f64d43ff0c18	3642	* Values:
mbed_official	146:f64d43ff0c18	3643	* - 0 - A hardware service request for channel 2 is not present
mbed_official	146:f64d43ff0c18	3644	* - 1 - A hardware service request for channel 2 is present
mbed_official	146:f64d43ff0c18	3645	*/
mbed_official	146:f64d43ff0c18	3646	//@{
mbed_official	146:f64d43ff0c18	3647	#define BP_DMA_HRS_HRS2 (2U) //!< Bit position for DMA_HRS_HRS2.
mbed_official	146:f64d43ff0c18	3648	#define BM_DMA_HRS_HRS2 (0x00000004U) //!< Bit mask for DMA_HRS_HRS2.
mbed_official	146:f64d43ff0c18	3649	#define BS_DMA_HRS_HRS2 (1U) //!< Bit field size in bits for DMA_HRS_HRS2.
mbed_official	146:f64d43ff0c18	3650
mbed_official	146:f64d43ff0c18	3651	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3652	//! @brief Read current value of the DMA_HRS_HRS2 field.
mbed_official	146:f64d43ff0c18	3653	#define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
mbed_official	146:f64d43ff0c18	3654	#endif
mbed_official	146:f64d43ff0c18	3655	//@}
mbed_official	146:f64d43ff0c18	3656
mbed_official	146:f64d43ff0c18	3657	/*!
mbed_official	146:f64d43ff0c18	3658	* @name Register DMA_HRS, field HRS3[3] (RO)
mbed_official	146:f64d43ff0c18	3659	*
mbed_official	146:f64d43ff0c18	3660	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3661	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3662	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3663	*
mbed_official	146:f64d43ff0c18	3664	* Values:
mbed_official	146:f64d43ff0c18	3665	* - 0 - A hardware service request for channel 3 is not present
mbed_official	146:f64d43ff0c18	3666	* - 1 - A hardware service request for channel 3 is present
mbed_official	146:f64d43ff0c18	3667	*/
mbed_official	146:f64d43ff0c18	3668	//@{
mbed_official	146:f64d43ff0c18	3669	#define BP_DMA_HRS_HRS3 (3U) //!< Bit position for DMA_HRS_HRS3.
mbed_official	146:f64d43ff0c18	3670	#define BM_DMA_HRS_HRS3 (0x00000008U) //!< Bit mask for DMA_HRS_HRS3.
mbed_official	146:f64d43ff0c18	3671	#define BS_DMA_HRS_HRS3 (1U) //!< Bit field size in bits for DMA_HRS_HRS3.
mbed_official	146:f64d43ff0c18	3672
mbed_official	146:f64d43ff0c18	3673	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3674	//! @brief Read current value of the DMA_HRS_HRS3 field.
mbed_official	146:f64d43ff0c18	3675	#define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
mbed_official	146:f64d43ff0c18	3676	#endif
mbed_official	146:f64d43ff0c18	3677	//@}
mbed_official	146:f64d43ff0c18	3678
mbed_official	146:f64d43ff0c18	3679	/*!
mbed_official	146:f64d43ff0c18	3680	* @name Register DMA_HRS, field HRS4[4] (RO)
mbed_official	146:f64d43ff0c18	3681	*
mbed_official	146:f64d43ff0c18	3682	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3683	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3684	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3685	*
mbed_official	146:f64d43ff0c18	3686	* Values:
mbed_official	146:f64d43ff0c18	3687	* - 0 - A hardware service request for channel 4 is not present
mbed_official	146:f64d43ff0c18	3688	* - 1 - A hardware service request for channel 4 is present
mbed_official	146:f64d43ff0c18	3689	*/
mbed_official	146:f64d43ff0c18	3690	//@{
mbed_official	146:f64d43ff0c18	3691	#define BP_DMA_HRS_HRS4 (4U) //!< Bit position for DMA_HRS_HRS4.
mbed_official	146:f64d43ff0c18	3692	#define BM_DMA_HRS_HRS4 (0x00000010U) //!< Bit mask for DMA_HRS_HRS4.
mbed_official	146:f64d43ff0c18	3693	#define BS_DMA_HRS_HRS4 (1U) //!< Bit field size in bits for DMA_HRS_HRS4.
mbed_official	146:f64d43ff0c18	3694
mbed_official	146:f64d43ff0c18	3695	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3696	//! @brief Read current value of the DMA_HRS_HRS4 field.
mbed_official	146:f64d43ff0c18	3697	#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
mbed_official	146:f64d43ff0c18	3698	#endif
mbed_official	146:f64d43ff0c18	3699	//@}
mbed_official	146:f64d43ff0c18	3700
mbed_official	146:f64d43ff0c18	3701	/*!
mbed_official	146:f64d43ff0c18	3702	* @name Register DMA_HRS, field HRS5[5] (RO)
mbed_official	146:f64d43ff0c18	3703	*
mbed_official	146:f64d43ff0c18	3704	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3705	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3706	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3707	*
mbed_official	146:f64d43ff0c18	3708	* Values:
mbed_official	146:f64d43ff0c18	3709	* - 0 - A hardware service request for channel 5 is not present
mbed_official	146:f64d43ff0c18	3710	* - 1 - A hardware service request for channel 5 is present
mbed_official	146:f64d43ff0c18	3711	*/
mbed_official	146:f64d43ff0c18	3712	//@{
mbed_official	146:f64d43ff0c18	3713	#define BP_DMA_HRS_HRS5 (5U) //!< Bit position for DMA_HRS_HRS5.
mbed_official	146:f64d43ff0c18	3714	#define BM_DMA_HRS_HRS5 (0x00000020U) //!< Bit mask for DMA_HRS_HRS5.
mbed_official	146:f64d43ff0c18	3715	#define BS_DMA_HRS_HRS5 (1U) //!< Bit field size in bits for DMA_HRS_HRS5.
mbed_official	146:f64d43ff0c18	3716
mbed_official	146:f64d43ff0c18	3717	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3718	//! @brief Read current value of the DMA_HRS_HRS5 field.
mbed_official	146:f64d43ff0c18	3719	#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
mbed_official	146:f64d43ff0c18	3720	#endif
mbed_official	146:f64d43ff0c18	3721	//@}
mbed_official	146:f64d43ff0c18	3722
mbed_official	146:f64d43ff0c18	3723	/*!
mbed_official	146:f64d43ff0c18	3724	* @name Register DMA_HRS, field HRS6[6] (RO)
mbed_official	146:f64d43ff0c18	3725	*
mbed_official	146:f64d43ff0c18	3726	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3727	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3728	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3729	*
mbed_official	146:f64d43ff0c18	3730	* Values:
mbed_official	146:f64d43ff0c18	3731	* - 0 - A hardware service request for channel 6 is not present
mbed_official	146:f64d43ff0c18	3732	* - 1 - A hardware service request for channel 6 is present
mbed_official	146:f64d43ff0c18	3733	*/
mbed_official	146:f64d43ff0c18	3734	//@{
mbed_official	146:f64d43ff0c18	3735	#define BP_DMA_HRS_HRS6 (6U) //!< Bit position for DMA_HRS_HRS6.
mbed_official	146:f64d43ff0c18	3736	#define BM_DMA_HRS_HRS6 (0x00000040U) //!< Bit mask for DMA_HRS_HRS6.
mbed_official	146:f64d43ff0c18	3737	#define BS_DMA_HRS_HRS6 (1U) //!< Bit field size in bits for DMA_HRS_HRS6.
mbed_official	146:f64d43ff0c18	3738
mbed_official	146:f64d43ff0c18	3739	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3740	//! @brief Read current value of the DMA_HRS_HRS6 field.
mbed_official	146:f64d43ff0c18	3741	#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
mbed_official	146:f64d43ff0c18	3742	#endif
mbed_official	146:f64d43ff0c18	3743	//@}
mbed_official	146:f64d43ff0c18	3744
mbed_official	146:f64d43ff0c18	3745	/*!
mbed_official	146:f64d43ff0c18	3746	* @name Register DMA_HRS, field HRS7[7] (RO)
mbed_official	146:f64d43ff0c18	3747	*
mbed_official	146:f64d43ff0c18	3748	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3749	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3750	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3751	*
mbed_official	146:f64d43ff0c18	3752	* Values:
mbed_official	146:f64d43ff0c18	3753	* - 0 - A hardware service request for channel 7 is not present
mbed_official	146:f64d43ff0c18	3754	* - 1 - A hardware service request for channel 7 is present
mbed_official	146:f64d43ff0c18	3755	*/
mbed_official	146:f64d43ff0c18	3756	//@{
mbed_official	146:f64d43ff0c18	3757	#define BP_DMA_HRS_HRS7 (7U) //!< Bit position for DMA_HRS_HRS7.
mbed_official	146:f64d43ff0c18	3758	#define BM_DMA_HRS_HRS7 (0x00000080U) //!< Bit mask for DMA_HRS_HRS7.
mbed_official	146:f64d43ff0c18	3759	#define BS_DMA_HRS_HRS7 (1U) //!< Bit field size in bits for DMA_HRS_HRS7.
mbed_official	146:f64d43ff0c18	3760
mbed_official	146:f64d43ff0c18	3761	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3762	//! @brief Read current value of the DMA_HRS_HRS7 field.
mbed_official	146:f64d43ff0c18	3763	#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
mbed_official	146:f64d43ff0c18	3764	#endif
mbed_official	146:f64d43ff0c18	3765	//@}
mbed_official	146:f64d43ff0c18	3766
mbed_official	146:f64d43ff0c18	3767	/*!
mbed_official	146:f64d43ff0c18	3768	* @name Register DMA_HRS, field HRS8[8] (RO)
mbed_official	146:f64d43ff0c18	3769	*
mbed_official	146:f64d43ff0c18	3770	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3771	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3772	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3773	*
mbed_official	146:f64d43ff0c18	3774	* Values:
mbed_official	146:f64d43ff0c18	3775	* - 0 - A hardware service request for channel 8 is not present
mbed_official	146:f64d43ff0c18	3776	* - 1 - A hardware service request for channel 8 is present
mbed_official	146:f64d43ff0c18	3777	*/
mbed_official	146:f64d43ff0c18	3778	//@{
mbed_official	146:f64d43ff0c18	3779	#define BP_DMA_HRS_HRS8 (8U) //!< Bit position for DMA_HRS_HRS8.
mbed_official	146:f64d43ff0c18	3780	#define BM_DMA_HRS_HRS8 (0x00000100U) //!< Bit mask for DMA_HRS_HRS8.
mbed_official	146:f64d43ff0c18	3781	#define BS_DMA_HRS_HRS8 (1U) //!< Bit field size in bits for DMA_HRS_HRS8.
mbed_official	146:f64d43ff0c18	3782
mbed_official	146:f64d43ff0c18	3783	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3784	//! @brief Read current value of the DMA_HRS_HRS8 field.
mbed_official	146:f64d43ff0c18	3785	#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
mbed_official	146:f64d43ff0c18	3786	#endif
mbed_official	146:f64d43ff0c18	3787	//@}
mbed_official	146:f64d43ff0c18	3788
mbed_official	146:f64d43ff0c18	3789	/*!
mbed_official	146:f64d43ff0c18	3790	* @name Register DMA_HRS, field HRS9[9] (RO)
mbed_official	146:f64d43ff0c18	3791	*
mbed_official	146:f64d43ff0c18	3792	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3793	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3794	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3795	*
mbed_official	146:f64d43ff0c18	3796	* Values:
mbed_official	146:f64d43ff0c18	3797	* - 0 - A hardware service request for channel 9 is not present
mbed_official	146:f64d43ff0c18	3798	* - 1 - A hardware service request for channel 9 is present
mbed_official	146:f64d43ff0c18	3799	*/
mbed_official	146:f64d43ff0c18	3800	//@{
mbed_official	146:f64d43ff0c18	3801	#define BP_DMA_HRS_HRS9 (9U) //!< Bit position for DMA_HRS_HRS9.
mbed_official	146:f64d43ff0c18	3802	#define BM_DMA_HRS_HRS9 (0x00000200U) //!< Bit mask for DMA_HRS_HRS9.
mbed_official	146:f64d43ff0c18	3803	#define BS_DMA_HRS_HRS9 (1U) //!< Bit field size in bits for DMA_HRS_HRS9.
mbed_official	146:f64d43ff0c18	3804
mbed_official	146:f64d43ff0c18	3805	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3806	//! @brief Read current value of the DMA_HRS_HRS9 field.
mbed_official	146:f64d43ff0c18	3807	#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
mbed_official	146:f64d43ff0c18	3808	#endif
mbed_official	146:f64d43ff0c18	3809	//@}
mbed_official	146:f64d43ff0c18	3810
mbed_official	146:f64d43ff0c18	3811	/*!
mbed_official	146:f64d43ff0c18	3812	* @name Register DMA_HRS, field HRS10[10] (RO)
mbed_official	146:f64d43ff0c18	3813	*
mbed_official	146:f64d43ff0c18	3814	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3815	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3816	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3817	*
mbed_official	146:f64d43ff0c18	3818	* Values:
mbed_official	146:f64d43ff0c18	3819	* - 0 - A hardware service request for channel 10 is not present
mbed_official	146:f64d43ff0c18	3820	* - 1 - A hardware service request for channel 10 is present
mbed_official	146:f64d43ff0c18	3821	*/
mbed_official	146:f64d43ff0c18	3822	//@{
mbed_official	146:f64d43ff0c18	3823	#define BP_DMA_HRS_HRS10 (10U) //!< Bit position for DMA_HRS_HRS10.
mbed_official	146:f64d43ff0c18	3824	#define BM_DMA_HRS_HRS10 (0x00000400U) //!< Bit mask for DMA_HRS_HRS10.
mbed_official	146:f64d43ff0c18	3825	#define BS_DMA_HRS_HRS10 (1U) //!< Bit field size in bits for DMA_HRS_HRS10.
mbed_official	146:f64d43ff0c18	3826
mbed_official	146:f64d43ff0c18	3827	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3828	//! @brief Read current value of the DMA_HRS_HRS10 field.
mbed_official	146:f64d43ff0c18	3829	#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
mbed_official	146:f64d43ff0c18	3830	#endif
mbed_official	146:f64d43ff0c18	3831	//@}
mbed_official	146:f64d43ff0c18	3832
mbed_official	146:f64d43ff0c18	3833	/*!
mbed_official	146:f64d43ff0c18	3834	* @name Register DMA_HRS, field HRS11[11] (RO)
mbed_official	146:f64d43ff0c18	3835	*
mbed_official	146:f64d43ff0c18	3836	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3837	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3838	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3839	*
mbed_official	146:f64d43ff0c18	3840	* Values:
mbed_official	146:f64d43ff0c18	3841	* - 0 - A hardware service request for channel 11 is not present
mbed_official	146:f64d43ff0c18	3842	* - 1 - A hardware service request for channel 11 is present
mbed_official	146:f64d43ff0c18	3843	*/
mbed_official	146:f64d43ff0c18	3844	//@{
mbed_official	146:f64d43ff0c18	3845	#define BP_DMA_HRS_HRS11 (11U) //!< Bit position for DMA_HRS_HRS11.
mbed_official	146:f64d43ff0c18	3846	#define BM_DMA_HRS_HRS11 (0x00000800U) //!< Bit mask for DMA_HRS_HRS11.
mbed_official	146:f64d43ff0c18	3847	#define BS_DMA_HRS_HRS11 (1U) //!< Bit field size in bits for DMA_HRS_HRS11.
mbed_official	146:f64d43ff0c18	3848
mbed_official	146:f64d43ff0c18	3849	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3850	//! @brief Read current value of the DMA_HRS_HRS11 field.
mbed_official	146:f64d43ff0c18	3851	#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
mbed_official	146:f64d43ff0c18	3852	#endif
mbed_official	146:f64d43ff0c18	3853	//@}
mbed_official	146:f64d43ff0c18	3854
mbed_official	146:f64d43ff0c18	3855	/*!
mbed_official	146:f64d43ff0c18	3856	* @name Register DMA_HRS, field HRS12[12] (RO)
mbed_official	146:f64d43ff0c18	3857	*
mbed_official	146:f64d43ff0c18	3858	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3859	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3860	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3861	*
mbed_official	146:f64d43ff0c18	3862	* Values:
mbed_official	146:f64d43ff0c18	3863	* - 0 - A hardware service request for channel 12 is not present
mbed_official	146:f64d43ff0c18	3864	* - 1 - A hardware service request for channel 12 is present
mbed_official	146:f64d43ff0c18	3865	*/
mbed_official	146:f64d43ff0c18	3866	//@{
mbed_official	146:f64d43ff0c18	3867	#define BP_DMA_HRS_HRS12 (12U) //!< Bit position for DMA_HRS_HRS12.
mbed_official	146:f64d43ff0c18	3868	#define BM_DMA_HRS_HRS12 (0x00001000U) //!< Bit mask for DMA_HRS_HRS12.
mbed_official	146:f64d43ff0c18	3869	#define BS_DMA_HRS_HRS12 (1U) //!< Bit field size in bits for DMA_HRS_HRS12.
mbed_official	146:f64d43ff0c18	3870
mbed_official	146:f64d43ff0c18	3871	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3872	//! @brief Read current value of the DMA_HRS_HRS12 field.
mbed_official	146:f64d43ff0c18	3873	#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
mbed_official	146:f64d43ff0c18	3874	#endif
mbed_official	146:f64d43ff0c18	3875	//@}
mbed_official	146:f64d43ff0c18	3876
mbed_official	146:f64d43ff0c18	3877	/*!
mbed_official	146:f64d43ff0c18	3878	* @name Register DMA_HRS, field HRS13[13] (RO)
mbed_official	146:f64d43ff0c18	3879	*
mbed_official	146:f64d43ff0c18	3880	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3881	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3882	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3883	*
mbed_official	146:f64d43ff0c18	3884	* Values:
mbed_official	146:f64d43ff0c18	3885	* - 0 - A hardware service request for channel 13 is not present
mbed_official	146:f64d43ff0c18	3886	* - 1 - A hardware service request for channel 13 is present
mbed_official	146:f64d43ff0c18	3887	*/
mbed_official	146:f64d43ff0c18	3888	//@{
mbed_official	146:f64d43ff0c18	3889	#define BP_DMA_HRS_HRS13 (13U) //!< Bit position for DMA_HRS_HRS13.
mbed_official	146:f64d43ff0c18	3890	#define BM_DMA_HRS_HRS13 (0x00002000U) //!< Bit mask for DMA_HRS_HRS13.
mbed_official	146:f64d43ff0c18	3891	#define BS_DMA_HRS_HRS13 (1U) //!< Bit field size in bits for DMA_HRS_HRS13.
mbed_official	146:f64d43ff0c18	3892
mbed_official	146:f64d43ff0c18	3893	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3894	//! @brief Read current value of the DMA_HRS_HRS13 field.
mbed_official	146:f64d43ff0c18	3895	#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
mbed_official	146:f64d43ff0c18	3896	#endif
mbed_official	146:f64d43ff0c18	3897	//@}
mbed_official	146:f64d43ff0c18	3898
mbed_official	146:f64d43ff0c18	3899	/*!
mbed_official	146:f64d43ff0c18	3900	* @name Register DMA_HRS, field HRS14[14] (RO)
mbed_official	146:f64d43ff0c18	3901	*
mbed_official	146:f64d43ff0c18	3902	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3903	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3904	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3905	*
mbed_official	146:f64d43ff0c18	3906	* Values:
mbed_official	146:f64d43ff0c18	3907	* - 0 - A hardware service request for channel 14 is not present
mbed_official	146:f64d43ff0c18	3908	* - 1 - A hardware service request for channel 14 is present
mbed_official	146:f64d43ff0c18	3909	*/
mbed_official	146:f64d43ff0c18	3910	//@{
mbed_official	146:f64d43ff0c18	3911	#define BP_DMA_HRS_HRS14 (14U) //!< Bit position for DMA_HRS_HRS14.
mbed_official	146:f64d43ff0c18	3912	#define BM_DMA_HRS_HRS14 (0x00004000U) //!< Bit mask for DMA_HRS_HRS14.
mbed_official	146:f64d43ff0c18	3913	#define BS_DMA_HRS_HRS14 (1U) //!< Bit field size in bits for DMA_HRS_HRS14.
mbed_official	146:f64d43ff0c18	3914
mbed_official	146:f64d43ff0c18	3915	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3916	//! @brief Read current value of the DMA_HRS_HRS14 field.
mbed_official	146:f64d43ff0c18	3917	#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
mbed_official	146:f64d43ff0c18	3918	#endif
mbed_official	146:f64d43ff0c18	3919	//@}
mbed_official	146:f64d43ff0c18	3920
mbed_official	146:f64d43ff0c18	3921	/*!
mbed_official	146:f64d43ff0c18	3922	* @name Register DMA_HRS, field HRS15[15] (RO)
mbed_official	146:f64d43ff0c18	3923	*
mbed_official	146:f64d43ff0c18	3924	* The HRS bit for its respective channel remains asserted for the period when a
mbed_official	146:f64d43ff0c18	3925	* Hardware Request is Present on the Channel. After the Request is completed
mbed_official	146:f64d43ff0c18	3926	* and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official	146:f64d43ff0c18	3927	*
mbed_official	146:f64d43ff0c18	3928	* Values:
mbed_official	146:f64d43ff0c18	3929	* - 0 - A hardware service request for channel 15 is not present
mbed_official	146:f64d43ff0c18	3930	* - 1 - A hardware service request for channel 15 is present
mbed_official	146:f64d43ff0c18	3931	*/
mbed_official	146:f64d43ff0c18	3932	//@{
mbed_official	146:f64d43ff0c18	3933	#define BP_DMA_HRS_HRS15 (15U) //!< Bit position for DMA_HRS_HRS15.
mbed_official	146:f64d43ff0c18	3934	#define BM_DMA_HRS_HRS15 (0x00008000U) //!< Bit mask for DMA_HRS_HRS15.
mbed_official	146:f64d43ff0c18	3935	#define BS_DMA_HRS_HRS15 (1U) //!< Bit field size in bits for DMA_HRS_HRS15.
mbed_official	146:f64d43ff0c18	3936
mbed_official	146:f64d43ff0c18	3937	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3938	//! @brief Read current value of the DMA_HRS_HRS15 field.
mbed_official	146:f64d43ff0c18	3939	#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
mbed_official	146:f64d43ff0c18	3940	#endif
mbed_official	146:f64d43ff0c18	3941	//@}
mbed_official	146:f64d43ff0c18	3942
mbed_official	146:f64d43ff0c18	3943	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3944	// HW_DMA_DCHPRIn - Channel n Priority Register
mbed_official	146:f64d43ff0c18	3945	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3946
mbed_official	146:f64d43ff0c18	3947	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3948	/*!
mbed_official	146:f64d43ff0c18	3949	* @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
mbed_official	146:f64d43ff0c18	3950	*
mbed_official	146:f64d43ff0c18	3951	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	3952	*
mbed_official	146:f64d43ff0c18	3953	* When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
mbed_official	146:f64d43ff0c18	3954	* contents of these registers define the unique priorities associated with each
mbed_official	146:f64d43ff0c18	3955	* channel . The channel priorities are evaluated by numeric value; for example, 0 is
mbed_official	146:f64d43ff0c18	3956	* the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
mbed_official	146:f64d43ff0c18	3957	* program the channel priorities with unique values; otherwise, a configuration
mbed_official	146:f64d43ff0c18	3958	* error is reported. The range of the priority value is limited to the values of 0
mbed_official	146:f64d43ff0c18	3959	* through 15.
mbed_official	146:f64d43ff0c18	3960	*/
mbed_official	146:f64d43ff0c18	3961	typedef union _hw_dma_dchprin
mbed_official	146:f64d43ff0c18	3962	{
mbed_official	146:f64d43ff0c18	3963	uint8_t U;
mbed_official	146:f64d43ff0c18	3964	struct _hw_dma_dchprin_bitfields
mbed_official	146:f64d43ff0c18	3965	{
mbed_official	146:f64d43ff0c18	3966	uint8_t CHPRI : 4; //!< [3:0] Channel n Arbitration Priority
mbed_official	146:f64d43ff0c18	3967	uint8_t RESERVED0 : 2; //!< [5:4]
mbed_official	146:f64d43ff0c18	3968	uint8_t DPA : 1; //!< [6] Disable Preempt Ability
mbed_official	146:f64d43ff0c18	3969	uint8_t ECP : 1; //!< [7] Enable Channel Preemption
mbed_official	146:f64d43ff0c18	3970	} B;
mbed_official	146:f64d43ff0c18	3971	} hw_dma_dchprin_t;
mbed_official	146:f64d43ff0c18	3972	#endif
mbed_official	146:f64d43ff0c18	3973
mbed_official	146:f64d43ff0c18	3974	/*!
mbed_official	146:f64d43ff0c18	3975	* @name Constants and macros for entire DMA_DCHPRIn register
mbed_official	146:f64d43ff0c18	3976	*/
mbed_official	146:f64d43ff0c18	3977	//@{
mbed_official	146:f64d43ff0c18	3978	#define HW_DMA_DCHPRIn_COUNT (16U)
mbed_official	146:f64d43ff0c18	3979
mbed_official	146:f64d43ff0c18	3980	#define HW_DMA_DCHPRIn_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100U + (0x1U * n))
mbed_official	146:f64d43ff0c18	3981
mbed_official	146:f64d43ff0c18	3982	/* DMA channel index to DMA channel priority register array index conversion macro */
mbed_official	146:f64d43ff0c18	3983	#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) \| (3 - ((n) & 0x03U)))
mbed_official	146:f64d43ff0c18	3984
mbed_official	146:f64d43ff0c18	3985	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3986	#define HW_DMA_DCHPRIn(x, n) ((__IO hw_dma_dchprin_t ) HW_DMA_DCHPRIn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	3987	#define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
mbed_official	146:f64d43ff0c18	3988	#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
mbed_official	146:f64d43ff0c18	3989	#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	3990	#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	3991	#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	3992	#endif
mbed_official	146:f64d43ff0c18	3993	//@}
mbed_official	146:f64d43ff0c18	3994
mbed_official	146:f64d43ff0c18	3995	/*
mbed_official	146:f64d43ff0c18	3996	* Constants & macros for individual DMA_DCHPRIn bitfields
mbed_official	146:f64d43ff0c18	3997	*/
mbed_official	146:f64d43ff0c18	3998
mbed_official	146:f64d43ff0c18	3999	/*!
mbed_official	146:f64d43ff0c18	4000	* @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
mbed_official	146:f64d43ff0c18	4001	*
mbed_official	146:f64d43ff0c18	4002	* Channel priority when fixed-priority arbitration is enabled Reset value for
mbed_official	146:f64d43ff0c18	4003	* the channel priority fields, CHPRI, is equal to the corresponding channel
mbed_official	146:f64d43ff0c18	4004	* number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
mbed_official	146:f64d43ff0c18	4005	*/
mbed_official	146:f64d43ff0c18	4006	//@{
mbed_official	146:f64d43ff0c18	4007	#define BP_DMA_DCHPRIn_CHPRI (0U) //!< Bit position for DMA_DCHPRIn_CHPRI.
mbed_official	146:f64d43ff0c18	4008	#define BM_DMA_DCHPRIn_CHPRI (0x0FU) //!< Bit mask for DMA_DCHPRIn_CHPRI.
mbed_official	146:f64d43ff0c18	4009	#define BS_DMA_DCHPRIn_CHPRI (4U) //!< Bit field size in bits for DMA_DCHPRIn_CHPRI.
mbed_official	146:f64d43ff0c18	4010
mbed_official	146:f64d43ff0c18	4011	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4012	//! @brief Read current value of the DMA_DCHPRIn_CHPRI field.
mbed_official	146:f64d43ff0c18	4013	#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
mbed_official	146:f64d43ff0c18	4014	#endif
mbed_official	146:f64d43ff0c18	4015
mbed_official	146:f64d43ff0c18	4016	//! @brief Format value for bitfield DMA_DCHPRIn_CHPRI.
mbed_official	146:f64d43ff0c18	4017	#define BF_DMA_DCHPRIn_CHPRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_CHPRI), uint8_t) & BM_DMA_DCHPRIn_CHPRI)
mbed_official	146:f64d43ff0c18	4018
mbed_official	146:f64d43ff0c18	4019	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4020	//! @brief Set the CHPRI field to a new value.
mbed_official	146:f64d43ff0c18	4021	#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) \| BF_DMA_DCHPRIn_CHPRI(v)))
mbed_official	146:f64d43ff0c18	4022	#endif
mbed_official	146:f64d43ff0c18	4023	//@}
mbed_official	146:f64d43ff0c18	4024
mbed_official	146:f64d43ff0c18	4025	/*!
mbed_official	146:f64d43ff0c18	4026	* @name Register DMA_DCHPRIn, field DPA[6] (RW)
mbed_official	146:f64d43ff0c18	4027	*
mbed_official	146:f64d43ff0c18	4028	* Values:
mbed_official	146:f64d43ff0c18	4029	* - 0 - Channel n can suspend a lower priority channel
mbed_official	146:f64d43ff0c18	4030	* - 1 - Channel n cannot suspend any channel, regardless of channel priority
mbed_official	146:f64d43ff0c18	4031	*/
mbed_official	146:f64d43ff0c18	4032	//@{
mbed_official	146:f64d43ff0c18	4033	#define BP_DMA_DCHPRIn_DPA (6U) //!< Bit position for DMA_DCHPRIn_DPA.
mbed_official	146:f64d43ff0c18	4034	#define BM_DMA_DCHPRIn_DPA (0x40U) //!< Bit mask for DMA_DCHPRIn_DPA.
mbed_official	146:f64d43ff0c18	4035	#define BS_DMA_DCHPRIn_DPA (1U) //!< Bit field size in bits for DMA_DCHPRIn_DPA.
mbed_official	146:f64d43ff0c18	4036
mbed_official	146:f64d43ff0c18	4037	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4038	//! @brief Read current value of the DMA_DCHPRIn_DPA field.
mbed_official	146:f64d43ff0c18	4039	#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
mbed_official	146:f64d43ff0c18	4040	#endif
mbed_official	146:f64d43ff0c18	4041
mbed_official	146:f64d43ff0c18	4042	//! @brief Format value for bitfield DMA_DCHPRIn_DPA.
mbed_official	146:f64d43ff0c18	4043	#define BF_DMA_DCHPRIn_DPA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_DPA), uint8_t) & BM_DMA_DCHPRIn_DPA)
mbed_official	146:f64d43ff0c18	4044
mbed_official	146:f64d43ff0c18	4045	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4046	//! @brief Set the DPA field to a new value.
mbed_official	146:f64d43ff0c18	4047	#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
mbed_official	146:f64d43ff0c18	4048	#endif
mbed_official	146:f64d43ff0c18	4049	//@}
mbed_official	146:f64d43ff0c18	4050
mbed_official	146:f64d43ff0c18	4051	/*!
mbed_official	146:f64d43ff0c18	4052	* @name Register DMA_DCHPRIn, field ECP[7] (RW)
mbed_official	146:f64d43ff0c18	4053	*
mbed_official	146:f64d43ff0c18	4054	* Values:
mbed_official	146:f64d43ff0c18	4055	* - 0 - Channel n cannot be suspended by a higher priority channel's service
mbed_official	146:f64d43ff0c18	4056	* request
mbed_official	146:f64d43ff0c18	4057	* - 1 - Channel n can be temporarily suspended by the service request of a
mbed_official	146:f64d43ff0c18	4058	* higher priority channel
mbed_official	146:f64d43ff0c18	4059	*/
mbed_official	146:f64d43ff0c18	4060	//@{
mbed_official	146:f64d43ff0c18	4061	#define BP_DMA_DCHPRIn_ECP (7U) //!< Bit position for DMA_DCHPRIn_ECP.
mbed_official	146:f64d43ff0c18	4062	#define BM_DMA_DCHPRIn_ECP (0x80U) //!< Bit mask for DMA_DCHPRIn_ECP.
mbed_official	146:f64d43ff0c18	4063	#define BS_DMA_DCHPRIn_ECP (1U) //!< Bit field size in bits for DMA_DCHPRIn_ECP.
mbed_official	146:f64d43ff0c18	4064
mbed_official	146:f64d43ff0c18	4065	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4066	//! @brief Read current value of the DMA_DCHPRIn_ECP field.
mbed_official	146:f64d43ff0c18	4067	#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
mbed_official	146:f64d43ff0c18	4068	#endif
mbed_official	146:f64d43ff0c18	4069
mbed_official	146:f64d43ff0c18	4070	//! @brief Format value for bitfield DMA_DCHPRIn_ECP.
mbed_official	146:f64d43ff0c18	4071	#define BF_DMA_DCHPRIn_ECP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_ECP), uint8_t) & BM_DMA_DCHPRIn_ECP)
mbed_official	146:f64d43ff0c18	4072
mbed_official	146:f64d43ff0c18	4073	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4074	//! @brief Set the ECP field to a new value.
mbed_official	146:f64d43ff0c18	4075	#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
mbed_official	146:f64d43ff0c18	4076	#endif
mbed_official	146:f64d43ff0c18	4077	//@}
mbed_official	146:f64d43ff0c18	4078
mbed_official	146:f64d43ff0c18	4079	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4080	// HW_DMA_TCDn_SADDR - TCD Source Address
mbed_official	146:f64d43ff0c18	4081	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4082
mbed_official	146:f64d43ff0c18	4083	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4084	/*!
mbed_official	146:f64d43ff0c18	4085	* @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
mbed_official	146:f64d43ff0c18	4086	*
mbed_official	146:f64d43ff0c18	4087	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4088	*/
mbed_official	146:f64d43ff0c18	4089	typedef union _hw_dma_tcdn_saddr
mbed_official	146:f64d43ff0c18	4090	{
mbed_official	146:f64d43ff0c18	4091	uint32_t U;
mbed_official	146:f64d43ff0c18	4092	struct _hw_dma_tcdn_saddr_bitfields
mbed_official	146:f64d43ff0c18	4093	{
mbed_official	146:f64d43ff0c18	4094	uint32_t SADDR : 32; //!< [31:0] Source Address
mbed_official	146:f64d43ff0c18	4095	} B;
mbed_official	146:f64d43ff0c18	4096	} hw_dma_tcdn_saddr_t;
mbed_official	146:f64d43ff0c18	4097	#endif
mbed_official	146:f64d43ff0c18	4098
mbed_official	146:f64d43ff0c18	4099	/*!
mbed_official	146:f64d43ff0c18	4100	* @name Constants and macros for entire DMA_TCDn_SADDR register
mbed_official	146:f64d43ff0c18	4101	*/
mbed_official	146:f64d43ff0c18	4102	//@{
mbed_official	146:f64d43ff0c18	4103	#define HW_DMA_TCDn_SADDR_COUNT (16U)
mbed_official	146:f64d43ff0c18	4104
mbed_official	146:f64d43ff0c18	4105	#define HW_DMA_TCDn_SADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1000U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4106
mbed_official	146:f64d43ff0c18	4107	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4108	#define HW_DMA_TCDn_SADDR(x, n) ((__IO hw_dma_tcdn_saddr_t ) HW_DMA_TCDn_SADDR_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4109	#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
mbed_official	146:f64d43ff0c18	4110	#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4111	#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4112	#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4113	#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4114	#endif
mbed_official	146:f64d43ff0c18	4115	//@}
mbed_official	146:f64d43ff0c18	4116
mbed_official	146:f64d43ff0c18	4117	/*
mbed_official	146:f64d43ff0c18	4118	* Constants & macros for individual DMA_TCDn_SADDR bitfields
mbed_official	146:f64d43ff0c18	4119	*/
mbed_official	146:f64d43ff0c18	4120
mbed_official	146:f64d43ff0c18	4121	/*!
mbed_official	146:f64d43ff0c18	4122	* @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
mbed_official	146:f64d43ff0c18	4123	*
mbed_official	146:f64d43ff0c18	4124	* Memory address pointing to the source data.
mbed_official	146:f64d43ff0c18	4125	*/
mbed_official	146:f64d43ff0c18	4126	//@{
mbed_official	146:f64d43ff0c18	4127	#define BP_DMA_TCDn_SADDR_SADDR (0U) //!< Bit position for DMA_TCDn_SADDR_SADDR.
mbed_official	146:f64d43ff0c18	4128	#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SADDR_SADDR.
mbed_official	146:f64d43ff0c18	4129	#define BS_DMA_TCDn_SADDR_SADDR (32U) //!< Bit field size in bits for DMA_TCDn_SADDR_SADDR.
mbed_official	146:f64d43ff0c18	4130
mbed_official	146:f64d43ff0c18	4131	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4132	//! @brief Read current value of the DMA_TCDn_SADDR_SADDR field.
mbed_official	146:f64d43ff0c18	4133	#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
mbed_official	146:f64d43ff0c18	4134	#endif
mbed_official	146:f64d43ff0c18	4135
mbed_official	146:f64d43ff0c18	4136	//! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR.
mbed_official	146:f64d43ff0c18	4137	#define BF_DMA_TCDn_SADDR_SADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SADDR_SADDR), uint32_t) & BM_DMA_TCDn_SADDR_SADDR)
mbed_official	146:f64d43ff0c18	4138
mbed_official	146:f64d43ff0c18	4139	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4140	//! @brief Set the SADDR field to a new value.
mbed_official	146:f64d43ff0c18	4141	#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
mbed_official	146:f64d43ff0c18	4142	#endif
mbed_official	146:f64d43ff0c18	4143	//@}
mbed_official	146:f64d43ff0c18	4144	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4145	// HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
mbed_official	146:f64d43ff0c18	4146	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4147
mbed_official	146:f64d43ff0c18	4148	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4149	/*!
mbed_official	146:f64d43ff0c18	4150	* @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
mbed_official	146:f64d43ff0c18	4151	*
mbed_official	146:f64d43ff0c18	4152	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	4153	*/
mbed_official	146:f64d43ff0c18	4154	typedef union _hw_dma_tcdn_soff
mbed_official	146:f64d43ff0c18	4155	{
mbed_official	146:f64d43ff0c18	4156	uint16_t U;
mbed_official	146:f64d43ff0c18	4157	struct _hw_dma_tcdn_soff_bitfields
mbed_official	146:f64d43ff0c18	4158	{
mbed_official	146:f64d43ff0c18	4159	uint16_t SOFF : 16; //!< [15:0] Source address signed offset
mbed_official	146:f64d43ff0c18	4160	} B;
mbed_official	146:f64d43ff0c18	4161	} hw_dma_tcdn_soff_t;
mbed_official	146:f64d43ff0c18	4162	#endif
mbed_official	146:f64d43ff0c18	4163
mbed_official	146:f64d43ff0c18	4164	/*!
mbed_official	146:f64d43ff0c18	4165	* @name Constants and macros for entire DMA_TCDn_SOFF register
mbed_official	146:f64d43ff0c18	4166	*/
mbed_official	146:f64d43ff0c18	4167	//@{
mbed_official	146:f64d43ff0c18	4168	#define HW_DMA_TCDn_SOFF_COUNT (16U)
mbed_official	146:f64d43ff0c18	4169
mbed_official	146:f64d43ff0c18	4170	#define HW_DMA_TCDn_SOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1004U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4171
mbed_official	146:f64d43ff0c18	4172	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4173	#define HW_DMA_TCDn_SOFF(x, n) ((__IO hw_dma_tcdn_soff_t ) HW_DMA_TCDn_SOFF_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4174	#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
mbed_official	146:f64d43ff0c18	4175	#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4176	#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4177	#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4178	#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4179	#endif
mbed_official	146:f64d43ff0c18	4180	//@}
mbed_official	146:f64d43ff0c18	4181
mbed_official	146:f64d43ff0c18	4182	/*
mbed_official	146:f64d43ff0c18	4183	* Constants & macros for individual DMA_TCDn_SOFF bitfields
mbed_official	146:f64d43ff0c18	4184	*/
mbed_official	146:f64d43ff0c18	4185
mbed_official	146:f64d43ff0c18	4186	/*!
mbed_official	146:f64d43ff0c18	4187	* @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
mbed_official	146:f64d43ff0c18	4188	*
mbed_official	146:f64d43ff0c18	4189	* Sign-extended offset applied to the current source address to form the
mbed_official	146:f64d43ff0c18	4190	* next-state value as each source read is completed.
mbed_official	146:f64d43ff0c18	4191	*/
mbed_official	146:f64d43ff0c18	4192	//@{
mbed_official	146:f64d43ff0c18	4193	#define BP_DMA_TCDn_SOFF_SOFF (0U) //!< Bit position for DMA_TCDn_SOFF_SOFF.
mbed_official	146:f64d43ff0c18	4194	#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_SOFF_SOFF.
mbed_official	146:f64d43ff0c18	4195	#define BS_DMA_TCDn_SOFF_SOFF (16U) //!< Bit field size in bits for DMA_TCDn_SOFF_SOFF.
mbed_official	146:f64d43ff0c18	4196
mbed_official	146:f64d43ff0c18	4197	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4198	//! @brief Read current value of the DMA_TCDn_SOFF_SOFF field.
mbed_official	146:f64d43ff0c18	4199	#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
mbed_official	146:f64d43ff0c18	4200	#endif
mbed_official	146:f64d43ff0c18	4201
mbed_official	146:f64d43ff0c18	4202	//! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF.
mbed_official	146:f64d43ff0c18	4203	#define BF_DMA_TCDn_SOFF_SOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_SOFF_SOFF), uint16_t) & BM_DMA_TCDn_SOFF_SOFF)
mbed_official	146:f64d43ff0c18	4204
mbed_official	146:f64d43ff0c18	4205	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4206	//! @brief Set the SOFF field to a new value.
mbed_official	146:f64d43ff0c18	4207	#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
mbed_official	146:f64d43ff0c18	4208	#endif
mbed_official	146:f64d43ff0c18	4209	//@}
mbed_official	146:f64d43ff0c18	4210	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4211	// HW_DMA_TCDn_ATTR - TCD Transfer Attributes
mbed_official	146:f64d43ff0c18	4212	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4213
mbed_official	146:f64d43ff0c18	4214	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4215	/*!
mbed_official	146:f64d43ff0c18	4216	* @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
mbed_official	146:f64d43ff0c18	4217	*
mbed_official	146:f64d43ff0c18	4218	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	4219	*/
mbed_official	146:f64d43ff0c18	4220	typedef union _hw_dma_tcdn_attr
mbed_official	146:f64d43ff0c18	4221	{
mbed_official	146:f64d43ff0c18	4222	uint16_t U;
mbed_official	146:f64d43ff0c18	4223	struct _hw_dma_tcdn_attr_bitfields
mbed_official	146:f64d43ff0c18	4224	{
mbed_official	146:f64d43ff0c18	4225	uint16_t DSIZE : 3; //!< [2:0] Destination Data Transfer Size
mbed_official	146:f64d43ff0c18	4226	uint16_t DMOD : 5; //!< [7:3] Destination Address Modulo
mbed_official	146:f64d43ff0c18	4227	uint16_t SSIZE : 3; //!< [10:8] Source data transfer size
mbed_official	146:f64d43ff0c18	4228	uint16_t SMOD : 5; //!< [15:11] Source Address Modulo.
mbed_official	146:f64d43ff0c18	4229	} B;
mbed_official	146:f64d43ff0c18	4230	} hw_dma_tcdn_attr_t;
mbed_official	146:f64d43ff0c18	4231	#endif
mbed_official	146:f64d43ff0c18	4232
mbed_official	146:f64d43ff0c18	4233	/*!
mbed_official	146:f64d43ff0c18	4234	* @name Constants and macros for entire DMA_TCDn_ATTR register
mbed_official	146:f64d43ff0c18	4235	*/
mbed_official	146:f64d43ff0c18	4236	//@{
mbed_official	146:f64d43ff0c18	4237	#define HW_DMA_TCDn_ATTR_COUNT (16U)
mbed_official	146:f64d43ff0c18	4238
mbed_official	146:f64d43ff0c18	4239	#define HW_DMA_TCDn_ATTR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1006U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4240
mbed_official	146:f64d43ff0c18	4241	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4242	#define HW_DMA_TCDn_ATTR(x, n) ((__IO hw_dma_tcdn_attr_t ) HW_DMA_TCDn_ATTR_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4243	#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
mbed_official	146:f64d43ff0c18	4244	#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4245	#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4246	#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4247	#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4248	#endif
mbed_official	146:f64d43ff0c18	4249	//@}
mbed_official	146:f64d43ff0c18	4250
mbed_official	146:f64d43ff0c18	4251	/*
mbed_official	146:f64d43ff0c18	4252	* Constants & macros for individual DMA_TCDn_ATTR bitfields
mbed_official	146:f64d43ff0c18	4253	*/
mbed_official	146:f64d43ff0c18	4254
mbed_official	146:f64d43ff0c18	4255	/*!
mbed_official	146:f64d43ff0c18	4256	* @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
mbed_official	146:f64d43ff0c18	4257	*
mbed_official	146:f64d43ff0c18	4258	* See the SSIZE definition
mbed_official	146:f64d43ff0c18	4259	*/
mbed_official	146:f64d43ff0c18	4260	//@{
mbed_official	146:f64d43ff0c18	4261	#define BP_DMA_TCDn_ATTR_DSIZE (0U) //!< Bit position for DMA_TCDn_ATTR_DSIZE.
mbed_official	146:f64d43ff0c18	4262	#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) //!< Bit mask for DMA_TCDn_ATTR_DSIZE.
mbed_official	146:f64d43ff0c18	4263	#define BS_DMA_TCDn_ATTR_DSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE.
mbed_official	146:f64d43ff0c18	4264
mbed_official	146:f64d43ff0c18	4265	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4266	//! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field.
mbed_official	146:f64d43ff0c18	4267	#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
mbed_official	146:f64d43ff0c18	4268	#endif
mbed_official	146:f64d43ff0c18	4269
mbed_official	146:f64d43ff0c18	4270	//! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE.
mbed_official	146:f64d43ff0c18	4271	#define BF_DMA_TCDn_ATTR_DSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DSIZE), uint16_t) & BM_DMA_TCDn_ATTR_DSIZE)
mbed_official	146:f64d43ff0c18	4272
mbed_official	146:f64d43ff0c18	4273	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4274	//! @brief Set the DSIZE field to a new value.
mbed_official	146:f64d43ff0c18	4275	#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) \| BF_DMA_TCDn_ATTR_DSIZE(v)))
mbed_official	146:f64d43ff0c18	4276	#endif
mbed_official	146:f64d43ff0c18	4277	//@}
mbed_official	146:f64d43ff0c18	4278
mbed_official	146:f64d43ff0c18	4279	/*!
mbed_official	146:f64d43ff0c18	4280	* @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
mbed_official	146:f64d43ff0c18	4281	*
mbed_official	146:f64d43ff0c18	4282	* See the SMOD definition
mbed_official	146:f64d43ff0c18	4283	*/
mbed_official	146:f64d43ff0c18	4284	//@{
mbed_official	146:f64d43ff0c18	4285	#define BP_DMA_TCDn_ATTR_DMOD (3U) //!< Bit position for DMA_TCDn_ATTR_DMOD.
mbed_official	146:f64d43ff0c18	4286	#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) //!< Bit mask for DMA_TCDn_ATTR_DMOD.
mbed_official	146:f64d43ff0c18	4287	#define BS_DMA_TCDn_ATTR_DMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_DMOD.
mbed_official	146:f64d43ff0c18	4288
mbed_official	146:f64d43ff0c18	4289	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4290	//! @brief Read current value of the DMA_TCDn_ATTR_DMOD field.
mbed_official	146:f64d43ff0c18	4291	#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
mbed_official	146:f64d43ff0c18	4292	#endif
mbed_official	146:f64d43ff0c18	4293
mbed_official	146:f64d43ff0c18	4294	//! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD.
mbed_official	146:f64d43ff0c18	4295	#define BF_DMA_TCDn_ATTR_DMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DMOD), uint16_t) & BM_DMA_TCDn_ATTR_DMOD)
mbed_official	146:f64d43ff0c18	4296
mbed_official	146:f64d43ff0c18	4297	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4298	//! @brief Set the DMOD field to a new value.
mbed_official	146:f64d43ff0c18	4299	#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) \| BF_DMA_TCDn_ATTR_DMOD(v)))
mbed_official	146:f64d43ff0c18	4300	#endif
mbed_official	146:f64d43ff0c18	4301	//@}
mbed_official	146:f64d43ff0c18	4302
mbed_official	146:f64d43ff0c18	4303	/*!
mbed_official	146:f64d43ff0c18	4304	* @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
mbed_official	146:f64d43ff0c18	4305	*
mbed_official	146:f64d43ff0c18	4306	* The attempted use of a Reserved encoding causes a configuration error.
mbed_official	146:f64d43ff0c18	4307	*
mbed_official	146:f64d43ff0c18	4308	* Values:
mbed_official	146:f64d43ff0c18	4309	* - 000 - 8-bit
mbed_official	146:f64d43ff0c18	4310	* - 001 - 16-bit
mbed_official	146:f64d43ff0c18	4311	* - 010 - 32-bit
mbed_official	146:f64d43ff0c18	4312	* - 011 - Reserved
mbed_official	146:f64d43ff0c18	4313	* - 100 - 16-byte
mbed_official	146:f64d43ff0c18	4314	* - 101 - 32-byte
mbed_official	146:f64d43ff0c18	4315	* - 110 - Reserved
mbed_official	146:f64d43ff0c18	4316	* - 111 - Reserved
mbed_official	146:f64d43ff0c18	4317	*/
mbed_official	146:f64d43ff0c18	4318	//@{
mbed_official	146:f64d43ff0c18	4319	#define BP_DMA_TCDn_ATTR_SSIZE (8U) //!< Bit position for DMA_TCDn_ATTR_SSIZE.
mbed_official	146:f64d43ff0c18	4320	#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) //!< Bit mask for DMA_TCDn_ATTR_SSIZE.
mbed_official	146:f64d43ff0c18	4321	#define BS_DMA_TCDn_ATTR_SSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE.
mbed_official	146:f64d43ff0c18	4322
mbed_official	146:f64d43ff0c18	4323	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4324	//! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field.
mbed_official	146:f64d43ff0c18	4325	#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
mbed_official	146:f64d43ff0c18	4326	#endif
mbed_official	146:f64d43ff0c18	4327
mbed_official	146:f64d43ff0c18	4328	//! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE.
mbed_official	146:f64d43ff0c18	4329	#define BF_DMA_TCDn_ATTR_SSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SSIZE), uint16_t) & BM_DMA_TCDn_ATTR_SSIZE)
mbed_official	146:f64d43ff0c18	4330
mbed_official	146:f64d43ff0c18	4331	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4332	//! @brief Set the SSIZE field to a new value.
mbed_official	146:f64d43ff0c18	4333	#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) \| BF_DMA_TCDn_ATTR_SSIZE(v)))
mbed_official	146:f64d43ff0c18	4334	#endif
mbed_official	146:f64d43ff0c18	4335	//@}
mbed_official	146:f64d43ff0c18	4336
mbed_official	146:f64d43ff0c18	4337	/*!
mbed_official	146:f64d43ff0c18	4338	* @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
mbed_official	146:f64d43ff0c18	4339	*
mbed_official	146:f64d43ff0c18	4340	* Values:
mbed_official	146:f64d43ff0c18	4341	* - 0 - Source address modulo feature is disabled
mbed_official	146:f64d43ff0c18	4342	*/
mbed_official	146:f64d43ff0c18	4343	//@{
mbed_official	146:f64d43ff0c18	4344	#define BP_DMA_TCDn_ATTR_SMOD (11U) //!< Bit position for DMA_TCDn_ATTR_SMOD.
mbed_official	146:f64d43ff0c18	4345	#define BM_DMA_TCDn_ATTR_SMOD (0xF800U) //!< Bit mask for DMA_TCDn_ATTR_SMOD.
mbed_official	146:f64d43ff0c18	4346	#define BS_DMA_TCDn_ATTR_SMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_SMOD.
mbed_official	146:f64d43ff0c18	4347
mbed_official	146:f64d43ff0c18	4348	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4349	//! @brief Read current value of the DMA_TCDn_ATTR_SMOD field.
mbed_official	146:f64d43ff0c18	4350	#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
mbed_official	146:f64d43ff0c18	4351	#endif
mbed_official	146:f64d43ff0c18	4352
mbed_official	146:f64d43ff0c18	4353	//! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD.
mbed_official	146:f64d43ff0c18	4354	#define BF_DMA_TCDn_ATTR_SMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SMOD), uint16_t) & BM_DMA_TCDn_ATTR_SMOD)
mbed_official	146:f64d43ff0c18	4355
mbed_official	146:f64d43ff0c18	4356	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4357	//! @brief Set the SMOD field to a new value.
mbed_official	146:f64d43ff0c18	4358	#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) \| BF_DMA_TCDn_ATTR_SMOD(v)))
mbed_official	146:f64d43ff0c18	4359	#endif
mbed_official	146:f64d43ff0c18	4360	//@}
mbed_official	146:f64d43ff0c18	4361	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4362	// HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
mbed_official	146:f64d43ff0c18	4363	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4364
mbed_official	146:f64d43ff0c18	4365	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4366	/*!
mbed_official	146:f64d43ff0c18	4367	* @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
mbed_official	146:f64d43ff0c18	4368	*
mbed_official	146:f64d43ff0c18	4369	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4370	*
mbed_official	146:f64d43ff0c18	4371	* This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
mbed_official	146:f64d43ff0c18	4372	* TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
mbed_official	146:f64d43ff0c18	4373	* register to use depends on whether minor loop mapping is disabled, enabled but not
mbed_official	146:f64d43ff0c18	4374	* used for this channel, or enabled and used. TCD word 2 is defined as follows
mbed_official	146:f64d43ff0c18	4375	* if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
mbed_official	146:f64d43ff0c18	4376	* enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
mbed_official	146:f64d43ff0c18	4377	* for TCD word 2's definition.
mbed_official	146:f64d43ff0c18	4378	*/
mbed_official	146:f64d43ff0c18	4379	typedef union _hw_dma_tcdn_nbytes_mlno
mbed_official	146:f64d43ff0c18	4380	{
mbed_official	146:f64d43ff0c18	4381	uint32_t U;
mbed_official	146:f64d43ff0c18	4382	struct _hw_dma_tcdn_nbytes_mlno_bitfields
mbed_official	146:f64d43ff0c18	4383	{
mbed_official	146:f64d43ff0c18	4384	uint32_t NBYTES : 32; //!< [31:0] Minor Byte Transfer Count
mbed_official	146:f64d43ff0c18	4385	} B;
mbed_official	146:f64d43ff0c18	4386	} hw_dma_tcdn_nbytes_mlno_t;
mbed_official	146:f64d43ff0c18	4387	#endif
mbed_official	146:f64d43ff0c18	4388
mbed_official	146:f64d43ff0c18	4389	/*!
mbed_official	146:f64d43ff0c18	4390	* @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
mbed_official	146:f64d43ff0c18	4391	*/
mbed_official	146:f64d43ff0c18	4392	//@{
mbed_official	146:f64d43ff0c18	4393	#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
mbed_official	146:f64d43ff0c18	4394
mbed_official	146:f64d43ff0c18	4395	#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4396
mbed_official	146:f64d43ff0c18	4397	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4398	#define HW_DMA_TCDn_NBYTES_MLNO(x, n) ((__IO hw_dma_tcdn_nbytes_mlno_t ) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4399	#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
mbed_official	146:f64d43ff0c18	4400	#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4401	#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4402	#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4403	#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4404	#endif
mbed_official	146:f64d43ff0c18	4405	//@}
mbed_official	146:f64d43ff0c18	4406
mbed_official	146:f64d43ff0c18	4407	/*
mbed_official	146:f64d43ff0c18	4408	* Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
mbed_official	146:f64d43ff0c18	4409	*/
mbed_official	146:f64d43ff0c18	4410
mbed_official	146:f64d43ff0c18	4411	/*!
mbed_official	146:f64d43ff0c18	4412	* @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
mbed_official	146:f64d43ff0c18	4413	*
mbed_official	146:f64d43ff0c18	4414	* Number of bytes to be transferred in each service request of the channel. As
mbed_official	146:f64d43ff0c18	4415	* a channel activates, the appropriate TCD contents load into the eDMA engine,
mbed_official	146:f64d43ff0c18	4416	* and the appropriate reads and writes perform until the minor byte transfer
mbed_official	146:f64d43ff0c18	4417	* count has transferred. This is an indivisible operation and cannot be halted.
mbed_official	146:f64d43ff0c18	4418	* (Although, it may be stalled by using the bandwidth control field, or via
mbed_official	146:f64d43ff0c18	4419	* preemption.) After the minor count is exhausted, the SADDR and DADDR values are
mbed_official	146:f64d43ff0c18	4420	* written back into the TCD memory, the major iteration count is decremented and
mbed_official	146:f64d43ff0c18	4421	* restored to the TCD memory. If the major iteration count is completed, additional
mbed_official	146:f64d43ff0c18	4422	* processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
mbed_official	146:f64d43ff0c18	4423	* GB transfer.
mbed_official	146:f64d43ff0c18	4424	*/
mbed_official	146:f64d43ff0c18	4425	//@{
mbed_official	146:f64d43ff0c18	4426	#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES.
mbed_official	146:f64d43ff0c18	4427	#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES.
mbed_official	146:f64d43ff0c18	4428	#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES.
mbed_official	146:f64d43ff0c18	4429
mbed_official	146:f64d43ff0c18	4430	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4431	//! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field.
mbed_official	146:f64d43ff0c18	4432	#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
mbed_official	146:f64d43ff0c18	4433	#endif
mbed_official	146:f64d43ff0c18	4434
mbed_official	146:f64d43ff0c18	4435	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES.
mbed_official	146:f64d43ff0c18	4436	#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
mbed_official	146:f64d43ff0c18	4437
mbed_official	146:f64d43ff0c18	4438	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4439	//! @brief Set the NBYTES field to a new value.
mbed_official	146:f64d43ff0c18	4440	#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
mbed_official	146:f64d43ff0c18	4441	#endif
mbed_official	146:f64d43ff0c18	4442	//@}
mbed_official	146:f64d43ff0c18	4443	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4444	// HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
mbed_official	146:f64d43ff0c18	4445	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4446
mbed_official	146:f64d43ff0c18	4447	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4448	/*!
mbed_official	146:f64d43ff0c18	4449	* @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
mbed_official	146:f64d43ff0c18	4450	*
mbed_official	146:f64d43ff0c18	4451	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4452	*
mbed_official	146:f64d43ff0c18	4453	* One of three registers (this register, TCD_NBYTES_MLNO, or
mbed_official	146:f64d43ff0c18	4454	* TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
mbed_official	146:f64d43ff0c18	4455	* depends on whether minor loop mapping is disabled, enabled but not used for
mbed_official	146:f64d43ff0c18	4456	* this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
mbed_official	146:f64d43ff0c18	4457	* loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
mbed_official	146:f64d43ff0c18	4458	* loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
mbed_official	146:f64d43ff0c18	4459	* TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
mbed_official	146:f64d43ff0c18	4460	* the TCD_NBYTES_MLNO register description.
mbed_official	146:f64d43ff0c18	4461	*/
mbed_official	146:f64d43ff0c18	4462	typedef union _hw_dma_tcdn_nbytes_mloffno
mbed_official	146:f64d43ff0c18	4463	{
mbed_official	146:f64d43ff0c18	4464	uint32_t U;
mbed_official	146:f64d43ff0c18	4465	struct _hw_dma_tcdn_nbytes_mloffno_bitfields
mbed_official	146:f64d43ff0c18	4466	{
mbed_official	146:f64d43ff0c18	4467	uint32_t NBYTES : 30; //!< [29:0] Minor Byte Transfer Count
mbed_official	146:f64d43ff0c18	4468	uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
mbed_official	146:f64d43ff0c18	4469	uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
mbed_official	146:f64d43ff0c18	4470	} B;
mbed_official	146:f64d43ff0c18	4471	} hw_dma_tcdn_nbytes_mloffno_t;
mbed_official	146:f64d43ff0c18	4472	#endif
mbed_official	146:f64d43ff0c18	4473
mbed_official	146:f64d43ff0c18	4474	/*!
mbed_official	146:f64d43ff0c18	4475	* @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
mbed_official	146:f64d43ff0c18	4476	*/
mbed_official	146:f64d43ff0c18	4477	//@{
mbed_official	146:f64d43ff0c18	4478	#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
mbed_official	146:f64d43ff0c18	4479
mbed_official	146:f64d43ff0c18	4480	#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4481
mbed_official	146:f64d43ff0c18	4482	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4483	#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) ((__IO hw_dma_tcdn_nbytes_mloffno_t ) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4484	#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
mbed_official	146:f64d43ff0c18	4485	#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4486	#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4487	#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4488	#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4489	#endif
mbed_official	146:f64d43ff0c18	4490	//@}
mbed_official	146:f64d43ff0c18	4491
mbed_official	146:f64d43ff0c18	4492	/*
mbed_official	146:f64d43ff0c18	4493	* Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
mbed_official	146:f64d43ff0c18	4494	*/
mbed_official	146:f64d43ff0c18	4495
mbed_official	146:f64d43ff0c18	4496	/*!
mbed_official	146:f64d43ff0c18	4497	* @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
mbed_official	146:f64d43ff0c18	4498	*
mbed_official	146:f64d43ff0c18	4499	* Number of bytes to be transferred in each service request of the channel. As
mbed_official	146:f64d43ff0c18	4500	* a channel activates, the appropriate TCD contents load into the eDMA engine,
mbed_official	146:f64d43ff0c18	4501	* and the appropriate reads and writes perform until the minor byte transfer
mbed_official	146:f64d43ff0c18	4502	* count has transferred. This is an indivisible operation and cannot be halted;
mbed_official	146:f64d43ff0c18	4503	* although, it may be stalled by using the bandwidth control field, or via
mbed_official	146:f64d43ff0c18	4504	* preemption. After the minor count is exhausted, the SADDR and DADDR values are written
mbed_official	146:f64d43ff0c18	4505	* back into the TCD memory, the major iteration count is decremented and
mbed_official	146:f64d43ff0c18	4506	* restored to the TCD memory. If the major iteration count is completed, additional
mbed_official	146:f64d43ff0c18	4507	* processing is performed.
mbed_official	146:f64d43ff0c18	4508	*/
mbed_official	146:f64d43ff0c18	4509	//@{
mbed_official	146:f64d43ff0c18	4510	#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
mbed_official	146:f64d43ff0c18	4511	#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
mbed_official	146:f64d43ff0c18	4512	#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
mbed_official	146:f64d43ff0c18	4513
mbed_official	146:f64d43ff0c18	4514	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4515	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field.
mbed_official	146:f64d43ff0c18	4516	#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
mbed_official	146:f64d43ff0c18	4517	#endif
mbed_official	146:f64d43ff0c18	4518
mbed_official	146:f64d43ff0c18	4519	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
mbed_official	146:f64d43ff0c18	4520	#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
mbed_official	146:f64d43ff0c18	4521
mbed_official	146:f64d43ff0c18	4522	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4523	//! @brief Set the NBYTES field to a new value.
mbed_official	146:f64d43ff0c18	4524	#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) \| BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
mbed_official	146:f64d43ff0c18	4525	#endif
mbed_official	146:f64d43ff0c18	4526	//@}
mbed_official	146:f64d43ff0c18	4527
mbed_official	146:f64d43ff0c18	4528	/*!
mbed_official	146:f64d43ff0c18	4529	* @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
mbed_official	146:f64d43ff0c18	4530	*
mbed_official	146:f64d43ff0c18	4531	* Selects whether the minor loop offset is applied to the destination address
mbed_official	146:f64d43ff0c18	4532	* upon minor loop completion.
mbed_official	146:f64d43ff0c18	4533	*
mbed_official	146:f64d43ff0c18	4534	* Values:
mbed_official	146:f64d43ff0c18	4535	* - 0 - The minor loop offset is not applied to the DADDR
mbed_official	146:f64d43ff0c18	4536	* - 1 - The minor loop offset is applied to the DADDR
mbed_official	146:f64d43ff0c18	4537	*/
mbed_official	146:f64d43ff0c18	4538	//@{
mbed_official	146:f64d43ff0c18	4539	#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
mbed_official	146:f64d43ff0c18	4540	#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
mbed_official	146:f64d43ff0c18	4541	#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
mbed_official	146:f64d43ff0c18	4542
mbed_official	146:f64d43ff0c18	4543	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4544	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field.
mbed_official	146:f64d43ff0c18	4545	#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
mbed_official	146:f64d43ff0c18	4546	#endif
mbed_official	146:f64d43ff0c18	4547
mbed_official	146:f64d43ff0c18	4548	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
mbed_official	146:f64d43ff0c18	4549	#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
mbed_official	146:f64d43ff0c18	4550
mbed_official	146:f64d43ff0c18	4551	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4552	//! @brief Set the DMLOE field to a new value.
mbed_official	146:f64d43ff0c18	4553	#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
mbed_official	146:f64d43ff0c18	4554	#endif
mbed_official	146:f64d43ff0c18	4555	//@}
mbed_official	146:f64d43ff0c18	4556
mbed_official	146:f64d43ff0c18	4557	/*!
mbed_official	146:f64d43ff0c18	4558	* @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
mbed_official	146:f64d43ff0c18	4559	*
mbed_official	146:f64d43ff0c18	4560	* Selects whether the minor loop offset is applied to the source address upon
mbed_official	146:f64d43ff0c18	4561	* minor loop completion.
mbed_official	146:f64d43ff0c18	4562	*
mbed_official	146:f64d43ff0c18	4563	* Values:
mbed_official	146:f64d43ff0c18	4564	* - 0 - The minor loop offset is not applied to the SADDR
mbed_official	146:f64d43ff0c18	4565	* - 1 - The minor loop offset is applied to the SADDR
mbed_official	146:f64d43ff0c18	4566	*/
mbed_official	146:f64d43ff0c18	4567	//@{
mbed_official	146:f64d43ff0c18	4568	#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
mbed_official	146:f64d43ff0c18	4569	#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
mbed_official	146:f64d43ff0c18	4570	#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
mbed_official	146:f64d43ff0c18	4571
mbed_official	146:f64d43ff0c18	4572	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4573	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field.
mbed_official	146:f64d43ff0c18	4574	#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
mbed_official	146:f64d43ff0c18	4575	#endif
mbed_official	146:f64d43ff0c18	4576
mbed_official	146:f64d43ff0c18	4577	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
mbed_official	146:f64d43ff0c18	4578	#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
mbed_official	146:f64d43ff0c18	4579
mbed_official	146:f64d43ff0c18	4580	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4581	//! @brief Set the SMLOE field to a new value.
mbed_official	146:f64d43ff0c18	4582	#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
mbed_official	146:f64d43ff0c18	4583	#endif
mbed_official	146:f64d43ff0c18	4584	//@}
mbed_official	146:f64d43ff0c18	4585	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4586	// HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
mbed_official	146:f64d43ff0c18	4587	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4588
mbed_official	146:f64d43ff0c18	4589	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4590	/*!
mbed_official	146:f64d43ff0c18	4591	* @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
mbed_official	146:f64d43ff0c18	4592	*
mbed_official	146:f64d43ff0c18	4593	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4594	*
mbed_official	146:f64d43ff0c18	4595	* One of three registers (this register, TCD_NBYTES_MLNO, or
mbed_official	146:f64d43ff0c18	4596	* TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
mbed_official	146:f64d43ff0c18	4597	* depends on whether minor loop mapping is disabled, enabled but not used for
mbed_official	146:f64d43ff0c18	4598	* this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
mbed_official	146:f64d43ff0c18	4599	* loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
mbed_official	146:f64d43ff0c18	4600	* or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
mbed_official	146:f64d43ff0c18	4601	* then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
mbed_official	146:f64d43ff0c18	4602	* mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
mbed_official	146:f64d43ff0c18	4603	*/
mbed_official	146:f64d43ff0c18	4604	typedef union _hw_dma_tcdn_nbytes_mloffyes
mbed_official	146:f64d43ff0c18	4605	{
mbed_official	146:f64d43ff0c18	4606	uint32_t U;
mbed_official	146:f64d43ff0c18	4607	struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
mbed_official	146:f64d43ff0c18	4608	{
mbed_official	146:f64d43ff0c18	4609	uint32_t NBYTES : 10; //!< [9:0] Minor Byte Transfer Count
mbed_official	146:f64d43ff0c18	4610	uint32_t MLOFF : 20; //!< [29:10] If SMLOE or DMLOE is set, this
mbed_official	146:f64d43ff0c18	4611	//! field represents a sign-extended offset applied to the source or
mbed_official	146:f64d43ff0c18	4612	//! destination address to form the next-state value after the minor loop completes.
mbed_official	146:f64d43ff0c18	4613	uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
mbed_official	146:f64d43ff0c18	4614	uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
mbed_official	146:f64d43ff0c18	4615	} B;
mbed_official	146:f64d43ff0c18	4616	} hw_dma_tcdn_nbytes_mloffyes_t;
mbed_official	146:f64d43ff0c18	4617	#endif
mbed_official	146:f64d43ff0c18	4618
mbed_official	146:f64d43ff0c18	4619	/*!
mbed_official	146:f64d43ff0c18	4620	* @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
mbed_official	146:f64d43ff0c18	4621	*/
mbed_official	146:f64d43ff0c18	4622	//@{
mbed_official	146:f64d43ff0c18	4623	#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
mbed_official	146:f64d43ff0c18	4624
mbed_official	146:f64d43ff0c18	4625	#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4626
mbed_official	146:f64d43ff0c18	4627	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4628	#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) ((__IO hw_dma_tcdn_nbytes_mloffyes_t ) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4629	#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
mbed_official	146:f64d43ff0c18	4630	#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4631	#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4632	#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4633	#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4634	#endif
mbed_official	146:f64d43ff0c18	4635	//@}
mbed_official	146:f64d43ff0c18	4636
mbed_official	146:f64d43ff0c18	4637	/*
mbed_official	146:f64d43ff0c18	4638	* Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
mbed_official	146:f64d43ff0c18	4639	*/
mbed_official	146:f64d43ff0c18	4640
mbed_official	146:f64d43ff0c18	4641	/*!
mbed_official	146:f64d43ff0c18	4642	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
mbed_official	146:f64d43ff0c18	4643	*
mbed_official	146:f64d43ff0c18	4644	* Number of bytes to be transferred in each service request of the channel. As
mbed_official	146:f64d43ff0c18	4645	* a channel activates, the appropriate TCD contents load into the eDMA engine,
mbed_official	146:f64d43ff0c18	4646	* and the appropriate reads and writes perform until the minor byte transfer
mbed_official	146:f64d43ff0c18	4647	* count has transferred. This is an indivisible operation and cannot be halted.
mbed_official	146:f64d43ff0c18	4648	* (Although, it may be stalled by using the bandwidth control field, or via
mbed_official	146:f64d43ff0c18	4649	* preemption.) After the minor count is exhausted, the SADDR and DADDR values are
mbed_official	146:f64d43ff0c18	4650	* written back into the TCD memory, the major iteration count is decremented and
mbed_official	146:f64d43ff0c18	4651	* restored to the TCD memory. If the major iteration count is completed, additional
mbed_official	146:f64d43ff0c18	4652	* processing is performed.
mbed_official	146:f64d43ff0c18	4653	*/
mbed_official	146:f64d43ff0c18	4654	//@{
mbed_official	146:f64d43ff0c18	4655	#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
mbed_official	146:f64d43ff0c18	4656	#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
mbed_official	146:f64d43ff0c18	4657	#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
mbed_official	146:f64d43ff0c18	4658
mbed_official	146:f64d43ff0c18	4659	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4660	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field.
mbed_official	146:f64d43ff0c18	4661	#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
mbed_official	146:f64d43ff0c18	4662	#endif
mbed_official	146:f64d43ff0c18	4663
mbed_official	146:f64d43ff0c18	4664	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
mbed_official	146:f64d43ff0c18	4665	#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
mbed_official	146:f64d43ff0c18	4666
mbed_official	146:f64d43ff0c18	4667	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4668	//! @brief Set the NBYTES field to a new value.
mbed_official	146:f64d43ff0c18	4669	#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) \| BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
mbed_official	146:f64d43ff0c18	4670	#endif
mbed_official	146:f64d43ff0c18	4671	//@}
mbed_official	146:f64d43ff0c18	4672
mbed_official	146:f64d43ff0c18	4673	/*!
mbed_official	146:f64d43ff0c18	4674	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
mbed_official	146:f64d43ff0c18	4675	*/
mbed_official	146:f64d43ff0c18	4676	//@{
mbed_official	146:f64d43ff0c18	4677	#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
mbed_official	146:f64d43ff0c18	4678	#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
mbed_official	146:f64d43ff0c18	4679	#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
mbed_official	146:f64d43ff0c18	4680
mbed_official	146:f64d43ff0c18	4681	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4682	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field.
mbed_official	146:f64d43ff0c18	4683	#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
mbed_official	146:f64d43ff0c18	4684	#endif
mbed_official	146:f64d43ff0c18	4685
mbed_official	146:f64d43ff0c18	4686	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
mbed_official	146:f64d43ff0c18	4687	#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
mbed_official	146:f64d43ff0c18	4688
mbed_official	146:f64d43ff0c18	4689	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4690	//! @brief Set the MLOFF field to a new value.
mbed_official	146:f64d43ff0c18	4691	#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) \| BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
mbed_official	146:f64d43ff0c18	4692	#endif
mbed_official	146:f64d43ff0c18	4693	//@}
mbed_official	146:f64d43ff0c18	4694
mbed_official	146:f64d43ff0c18	4695	/*!
mbed_official	146:f64d43ff0c18	4696	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
mbed_official	146:f64d43ff0c18	4697	*
mbed_official	146:f64d43ff0c18	4698	* Selects whether the minor loop offset is applied to the destination address
mbed_official	146:f64d43ff0c18	4699	* upon minor loop completion.
mbed_official	146:f64d43ff0c18	4700	*
mbed_official	146:f64d43ff0c18	4701	* Values:
mbed_official	146:f64d43ff0c18	4702	* - 0 - The minor loop offset is not applied to the DADDR
mbed_official	146:f64d43ff0c18	4703	* - 1 - The minor loop offset is applied to the DADDR
mbed_official	146:f64d43ff0c18	4704	*/
mbed_official	146:f64d43ff0c18	4705	//@{
mbed_official	146:f64d43ff0c18	4706	#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
mbed_official	146:f64d43ff0c18	4707	#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
mbed_official	146:f64d43ff0c18	4708	#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
mbed_official	146:f64d43ff0c18	4709
mbed_official	146:f64d43ff0c18	4710	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4711	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field.
mbed_official	146:f64d43ff0c18	4712	#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
mbed_official	146:f64d43ff0c18	4713	#endif
mbed_official	146:f64d43ff0c18	4714
mbed_official	146:f64d43ff0c18	4715	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
mbed_official	146:f64d43ff0c18	4716	#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
mbed_official	146:f64d43ff0c18	4717
mbed_official	146:f64d43ff0c18	4718	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4719	//! @brief Set the DMLOE field to a new value.
mbed_official	146:f64d43ff0c18	4720	#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
mbed_official	146:f64d43ff0c18	4721	#endif
mbed_official	146:f64d43ff0c18	4722	//@}
mbed_official	146:f64d43ff0c18	4723
mbed_official	146:f64d43ff0c18	4724	/*!
mbed_official	146:f64d43ff0c18	4725	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
mbed_official	146:f64d43ff0c18	4726	*
mbed_official	146:f64d43ff0c18	4727	* Selects whether the minor loop offset is applied to the source address upon
mbed_official	146:f64d43ff0c18	4728	* minor loop completion.
mbed_official	146:f64d43ff0c18	4729	*
mbed_official	146:f64d43ff0c18	4730	* Values:
mbed_official	146:f64d43ff0c18	4731	* - 0 - The minor loop offset is not applied to the SADDR
mbed_official	146:f64d43ff0c18	4732	* - 1 - The minor loop offset is applied to the SADDR
mbed_official	146:f64d43ff0c18	4733	*/
mbed_official	146:f64d43ff0c18	4734	//@{
mbed_official	146:f64d43ff0c18	4735	#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
mbed_official	146:f64d43ff0c18	4736	#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
mbed_official	146:f64d43ff0c18	4737	#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
mbed_official	146:f64d43ff0c18	4738
mbed_official	146:f64d43ff0c18	4739	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4740	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field.
mbed_official	146:f64d43ff0c18	4741	#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
mbed_official	146:f64d43ff0c18	4742	#endif
mbed_official	146:f64d43ff0c18	4743
mbed_official	146:f64d43ff0c18	4744	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
mbed_official	146:f64d43ff0c18	4745	#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
mbed_official	146:f64d43ff0c18	4746
mbed_official	146:f64d43ff0c18	4747	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4748	//! @brief Set the SMLOE field to a new value.
mbed_official	146:f64d43ff0c18	4749	#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
mbed_official	146:f64d43ff0c18	4750	#endif
mbed_official	146:f64d43ff0c18	4751	//@}
mbed_official	146:f64d43ff0c18	4752	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4753	// HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
mbed_official	146:f64d43ff0c18	4754	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4755
mbed_official	146:f64d43ff0c18	4756	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4757	/*!
mbed_official	146:f64d43ff0c18	4758	* @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
mbed_official	146:f64d43ff0c18	4759	*
mbed_official	146:f64d43ff0c18	4760	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4761	*/
mbed_official	146:f64d43ff0c18	4762	typedef union _hw_dma_tcdn_slast
mbed_official	146:f64d43ff0c18	4763	{
mbed_official	146:f64d43ff0c18	4764	uint32_t U;
mbed_official	146:f64d43ff0c18	4765	struct _hw_dma_tcdn_slast_bitfields
mbed_official	146:f64d43ff0c18	4766	{
mbed_official	146:f64d43ff0c18	4767	uint32_t SLAST : 32; //!< [31:0] Last source Address Adjustment
mbed_official	146:f64d43ff0c18	4768	} B;
mbed_official	146:f64d43ff0c18	4769	} hw_dma_tcdn_slast_t;
mbed_official	146:f64d43ff0c18	4770	#endif
mbed_official	146:f64d43ff0c18	4771
mbed_official	146:f64d43ff0c18	4772	/*!
mbed_official	146:f64d43ff0c18	4773	* @name Constants and macros for entire DMA_TCDn_SLAST register
mbed_official	146:f64d43ff0c18	4774	*/
mbed_official	146:f64d43ff0c18	4775	//@{
mbed_official	146:f64d43ff0c18	4776	#define HW_DMA_TCDn_SLAST_COUNT (16U)
mbed_official	146:f64d43ff0c18	4777
mbed_official	146:f64d43ff0c18	4778	#define HW_DMA_TCDn_SLAST_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100CU + (0x20U * n))
mbed_official	146:f64d43ff0c18	4779
mbed_official	146:f64d43ff0c18	4780	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4781	#define HW_DMA_TCDn_SLAST(x, n) ((__IO hw_dma_tcdn_slast_t ) HW_DMA_TCDn_SLAST_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4782	#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
mbed_official	146:f64d43ff0c18	4783	#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4784	#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4785	#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4786	#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4787	#endif
mbed_official	146:f64d43ff0c18	4788	//@}
mbed_official	146:f64d43ff0c18	4789
mbed_official	146:f64d43ff0c18	4790	/*
mbed_official	146:f64d43ff0c18	4791	* Constants & macros for individual DMA_TCDn_SLAST bitfields
mbed_official	146:f64d43ff0c18	4792	*/
mbed_official	146:f64d43ff0c18	4793
mbed_official	146:f64d43ff0c18	4794	/*!
mbed_official	146:f64d43ff0c18	4795	* @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
mbed_official	146:f64d43ff0c18	4796	*
mbed_official	146:f64d43ff0c18	4797	* Adjustment value added to the source address at the completion of the major
mbed_official	146:f64d43ff0c18	4798	* iteration count. This value can be applied to restore the source address to the
mbed_official	146:f64d43ff0c18	4799	* initial value, or adjust the address to reference the next data structure.
mbed_official	146:f64d43ff0c18	4800	* This register uses two's complement notation; the overflow bit is discarded.
mbed_official	146:f64d43ff0c18	4801	*/
mbed_official	146:f64d43ff0c18	4802	//@{
mbed_official	146:f64d43ff0c18	4803	#define BP_DMA_TCDn_SLAST_SLAST (0U) //!< Bit position for DMA_TCDn_SLAST_SLAST.
mbed_official	146:f64d43ff0c18	4804	#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SLAST_SLAST.
mbed_official	146:f64d43ff0c18	4805	#define BS_DMA_TCDn_SLAST_SLAST (32U) //!< Bit field size in bits for DMA_TCDn_SLAST_SLAST.
mbed_official	146:f64d43ff0c18	4806
mbed_official	146:f64d43ff0c18	4807	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4808	//! @brief Read current value of the DMA_TCDn_SLAST_SLAST field.
mbed_official	146:f64d43ff0c18	4809	#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
mbed_official	146:f64d43ff0c18	4810	#endif
mbed_official	146:f64d43ff0c18	4811
mbed_official	146:f64d43ff0c18	4812	//! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST.
mbed_official	146:f64d43ff0c18	4813	#define BF_DMA_TCDn_SLAST_SLAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SLAST_SLAST), uint32_t) & BM_DMA_TCDn_SLAST_SLAST)
mbed_official	146:f64d43ff0c18	4814
mbed_official	146:f64d43ff0c18	4815	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4816	//! @brief Set the SLAST field to a new value.
mbed_official	146:f64d43ff0c18	4817	#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
mbed_official	146:f64d43ff0c18	4818	#endif
mbed_official	146:f64d43ff0c18	4819	//@}
mbed_official	146:f64d43ff0c18	4820	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4821	// HW_DMA_TCDn_DADDR - TCD Destination Address
mbed_official	146:f64d43ff0c18	4822	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4823
mbed_official	146:f64d43ff0c18	4824	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4825	/*!
mbed_official	146:f64d43ff0c18	4826	* @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
mbed_official	146:f64d43ff0c18	4827	*
mbed_official	146:f64d43ff0c18	4828	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4829	*/
mbed_official	146:f64d43ff0c18	4830	typedef union _hw_dma_tcdn_daddr
mbed_official	146:f64d43ff0c18	4831	{
mbed_official	146:f64d43ff0c18	4832	uint32_t U;
mbed_official	146:f64d43ff0c18	4833	struct _hw_dma_tcdn_daddr_bitfields
mbed_official	146:f64d43ff0c18	4834	{
mbed_official	146:f64d43ff0c18	4835	uint32_t DADDR : 32; //!< [31:0] Destination Address
mbed_official	146:f64d43ff0c18	4836	} B;
mbed_official	146:f64d43ff0c18	4837	} hw_dma_tcdn_daddr_t;
mbed_official	146:f64d43ff0c18	4838	#endif
mbed_official	146:f64d43ff0c18	4839
mbed_official	146:f64d43ff0c18	4840	/*!
mbed_official	146:f64d43ff0c18	4841	* @name Constants and macros for entire DMA_TCDn_DADDR register
mbed_official	146:f64d43ff0c18	4842	*/
mbed_official	146:f64d43ff0c18	4843	//@{
mbed_official	146:f64d43ff0c18	4844	#define HW_DMA_TCDn_DADDR_COUNT (16U)
mbed_official	146:f64d43ff0c18	4845
mbed_official	146:f64d43ff0c18	4846	#define HW_DMA_TCDn_DADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1010U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4847
mbed_official	146:f64d43ff0c18	4848	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4849	#define HW_DMA_TCDn_DADDR(x, n) ((__IO hw_dma_tcdn_daddr_t ) HW_DMA_TCDn_DADDR_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4850	#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
mbed_official	146:f64d43ff0c18	4851	#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4852	#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4853	#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4854	#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4855	#endif
mbed_official	146:f64d43ff0c18	4856	//@}
mbed_official	146:f64d43ff0c18	4857
mbed_official	146:f64d43ff0c18	4858	/*
mbed_official	146:f64d43ff0c18	4859	* Constants & macros for individual DMA_TCDn_DADDR bitfields
mbed_official	146:f64d43ff0c18	4860	*/
mbed_official	146:f64d43ff0c18	4861
mbed_official	146:f64d43ff0c18	4862	/*!
mbed_official	146:f64d43ff0c18	4863	* @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
mbed_official	146:f64d43ff0c18	4864	*
mbed_official	146:f64d43ff0c18	4865	* Memory address pointing to the destination data.
mbed_official	146:f64d43ff0c18	4866	*/
mbed_official	146:f64d43ff0c18	4867	//@{
mbed_official	146:f64d43ff0c18	4868	#define BP_DMA_TCDn_DADDR_DADDR (0U) //!< Bit position for DMA_TCDn_DADDR_DADDR.
mbed_official	146:f64d43ff0c18	4869	#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DADDR_DADDR.
mbed_official	146:f64d43ff0c18	4870	#define BS_DMA_TCDn_DADDR_DADDR (32U) //!< Bit field size in bits for DMA_TCDn_DADDR_DADDR.
mbed_official	146:f64d43ff0c18	4871
mbed_official	146:f64d43ff0c18	4872	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4873	//! @brief Read current value of the DMA_TCDn_DADDR_DADDR field.
mbed_official	146:f64d43ff0c18	4874	#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
mbed_official	146:f64d43ff0c18	4875	#endif
mbed_official	146:f64d43ff0c18	4876
mbed_official	146:f64d43ff0c18	4877	//! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR.
mbed_official	146:f64d43ff0c18	4878	#define BF_DMA_TCDn_DADDR_DADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DADDR_DADDR), uint32_t) & BM_DMA_TCDn_DADDR_DADDR)
mbed_official	146:f64d43ff0c18	4879
mbed_official	146:f64d43ff0c18	4880	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4881	//! @brief Set the DADDR field to a new value.
mbed_official	146:f64d43ff0c18	4882	#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
mbed_official	146:f64d43ff0c18	4883	#endif
mbed_official	146:f64d43ff0c18	4884	//@}
mbed_official	146:f64d43ff0c18	4885	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4886	// HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
mbed_official	146:f64d43ff0c18	4887	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4888
mbed_official	146:f64d43ff0c18	4889	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4890	/*!
mbed_official	146:f64d43ff0c18	4891	* @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
mbed_official	146:f64d43ff0c18	4892	*
mbed_official	146:f64d43ff0c18	4893	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	4894	*/
mbed_official	146:f64d43ff0c18	4895	typedef union _hw_dma_tcdn_doff
mbed_official	146:f64d43ff0c18	4896	{
mbed_official	146:f64d43ff0c18	4897	uint16_t U;
mbed_official	146:f64d43ff0c18	4898	struct _hw_dma_tcdn_doff_bitfields
mbed_official	146:f64d43ff0c18	4899	{
mbed_official	146:f64d43ff0c18	4900	uint16_t DOFF : 16; //!< [15:0] Destination Address Signed offset
mbed_official	146:f64d43ff0c18	4901	} B;
mbed_official	146:f64d43ff0c18	4902	} hw_dma_tcdn_doff_t;
mbed_official	146:f64d43ff0c18	4903	#endif
mbed_official	146:f64d43ff0c18	4904
mbed_official	146:f64d43ff0c18	4905	/*!
mbed_official	146:f64d43ff0c18	4906	* @name Constants and macros for entire DMA_TCDn_DOFF register
mbed_official	146:f64d43ff0c18	4907	*/
mbed_official	146:f64d43ff0c18	4908	//@{
mbed_official	146:f64d43ff0c18	4909	#define HW_DMA_TCDn_DOFF_COUNT (16U)
mbed_official	146:f64d43ff0c18	4910
mbed_official	146:f64d43ff0c18	4911	#define HW_DMA_TCDn_DOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1014U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4912
mbed_official	146:f64d43ff0c18	4913	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4914	#define HW_DMA_TCDn_DOFF(x, n) ((__IO hw_dma_tcdn_doff_t ) HW_DMA_TCDn_DOFF_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4915	#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
mbed_official	146:f64d43ff0c18	4916	#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4917	#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4918	#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4919	#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4920	#endif
mbed_official	146:f64d43ff0c18	4921	//@}
mbed_official	146:f64d43ff0c18	4922
mbed_official	146:f64d43ff0c18	4923	/*
mbed_official	146:f64d43ff0c18	4924	* Constants & macros for individual DMA_TCDn_DOFF bitfields
mbed_official	146:f64d43ff0c18	4925	*/
mbed_official	146:f64d43ff0c18	4926
mbed_official	146:f64d43ff0c18	4927	/*!
mbed_official	146:f64d43ff0c18	4928	* @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
mbed_official	146:f64d43ff0c18	4929	*
mbed_official	146:f64d43ff0c18	4930	* Sign-extended offset applied to the current destination address to form the
mbed_official	146:f64d43ff0c18	4931	* next-state value as each destination write is completed.
mbed_official	146:f64d43ff0c18	4932	*/
mbed_official	146:f64d43ff0c18	4933	//@{
mbed_official	146:f64d43ff0c18	4934	#define BP_DMA_TCDn_DOFF_DOFF (0U) //!< Bit position for DMA_TCDn_DOFF_DOFF.
mbed_official	146:f64d43ff0c18	4935	#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_DOFF_DOFF.
mbed_official	146:f64d43ff0c18	4936	#define BS_DMA_TCDn_DOFF_DOFF (16U) //!< Bit field size in bits for DMA_TCDn_DOFF_DOFF.
mbed_official	146:f64d43ff0c18	4937
mbed_official	146:f64d43ff0c18	4938	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4939	//! @brief Read current value of the DMA_TCDn_DOFF_DOFF field.
mbed_official	146:f64d43ff0c18	4940	#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
mbed_official	146:f64d43ff0c18	4941	#endif
mbed_official	146:f64d43ff0c18	4942
mbed_official	146:f64d43ff0c18	4943	//! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF.
mbed_official	146:f64d43ff0c18	4944	#define BF_DMA_TCDn_DOFF_DOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_DOFF_DOFF), uint16_t) & BM_DMA_TCDn_DOFF_DOFF)
mbed_official	146:f64d43ff0c18	4945
mbed_official	146:f64d43ff0c18	4946	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4947	//! @brief Set the DOFF field to a new value.
mbed_official	146:f64d43ff0c18	4948	#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
mbed_official	146:f64d43ff0c18	4949	#endif
mbed_official	146:f64d43ff0c18	4950	//@}
mbed_official	146:f64d43ff0c18	4951	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4952	// HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official	146:f64d43ff0c18	4953	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4954
mbed_official	146:f64d43ff0c18	4955	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4956	/*!
mbed_official	146:f64d43ff0c18	4957	* @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
mbed_official	146:f64d43ff0c18	4958	*
mbed_official	146:f64d43ff0c18	4959	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	4960	*
mbed_official	146:f64d43ff0c18	4961	* If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
mbed_official	146:f64d43ff0c18	4962	* follows.
mbed_official	146:f64d43ff0c18	4963	*/
mbed_official	146:f64d43ff0c18	4964	typedef union _hw_dma_tcdn_citer_elinkno
mbed_official	146:f64d43ff0c18	4965	{
mbed_official	146:f64d43ff0c18	4966	uint16_t U;
mbed_official	146:f64d43ff0c18	4967	struct _hw_dma_tcdn_citer_elinkno_bitfields
mbed_official	146:f64d43ff0c18	4968	{
mbed_official	146:f64d43ff0c18	4969	uint16_t CITER : 15; //!< [14:0] Current Major Iteration Count
mbed_official	146:f64d43ff0c18	4970	uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
mbed_official	146:f64d43ff0c18	4971	//! minor-loop complete
mbed_official	146:f64d43ff0c18	4972	} B;
mbed_official	146:f64d43ff0c18	4973	} hw_dma_tcdn_citer_elinkno_t;
mbed_official	146:f64d43ff0c18	4974	#endif
mbed_official	146:f64d43ff0c18	4975
mbed_official	146:f64d43ff0c18	4976	/*!
mbed_official	146:f64d43ff0c18	4977	* @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
mbed_official	146:f64d43ff0c18	4978	*/
mbed_official	146:f64d43ff0c18	4979	//@{
mbed_official	146:f64d43ff0c18	4980	#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
mbed_official	146:f64d43ff0c18	4981
mbed_official	146:f64d43ff0c18	4982	#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
mbed_official	146:f64d43ff0c18	4983
mbed_official	146:f64d43ff0c18	4984	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4985	#define HW_DMA_TCDn_CITER_ELINKNO(x, n) ((__IO hw_dma_tcdn_citer_elinkno_t ) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
mbed_official	146:f64d43ff0c18	4986	#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
mbed_official	146:f64d43ff0c18	4987	#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
mbed_official	146:f64d43ff0c18	4988	#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	4989	#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	4990	#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	4991	#endif
mbed_official	146:f64d43ff0c18	4992	//@}
mbed_official	146:f64d43ff0c18	4993
mbed_official	146:f64d43ff0c18	4994	/*
mbed_official	146:f64d43ff0c18	4995	* Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
mbed_official	146:f64d43ff0c18	4996	*/
mbed_official	146:f64d43ff0c18	4997
mbed_official	146:f64d43ff0c18	4998	/*!
mbed_official	146:f64d43ff0c18	4999	* @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
mbed_official	146:f64d43ff0c18	5000	*
mbed_official	146:f64d43ff0c18	5001	* This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
mbed_official	146:f64d43ff0c18	5002	* major loop count for the channel. It is decremented each time the minor loop is
mbed_official	146:f64d43ff0c18	5003	* completed and updated in the transfer control descriptor memory. After the
mbed_official	146:f64d43ff0c18	5004	* major iteration count is exhausted, the channel performs a number of operations
mbed_official	146:f64d43ff0c18	5005	* (e.g., final source and destination address calculations), optionally generating
mbed_official	146:f64d43ff0c18	5006	* an interrupt to signal channel completion before reloading the CITER field
mbed_official	146:f64d43ff0c18	5007	* from the beginning iteration count (BITER) field. When the CITER field is
mbed_official	146:f64d43ff0c18	5008	* initially loaded by software, it must be set to the same value as that contained in
mbed_official	146:f64d43ff0c18	5009	* the BITER field. If the channel is configured to execute a single service
mbed_official	146:f64d43ff0c18	5010	* request, the initial values of BITER and CITER should be 0x0001.
mbed_official	146:f64d43ff0c18	5011	*/
mbed_official	146:f64d43ff0c18	5012	//@{
mbed_official	146:f64d43ff0c18	5013	#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER.
mbed_official	146:f64d43ff0c18	5014	#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER.
mbed_official	146:f64d43ff0c18	5015	#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER.
mbed_official	146:f64d43ff0c18	5016
mbed_official	146:f64d43ff0c18	5017	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5018	//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field.
mbed_official	146:f64d43ff0c18	5019	#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
mbed_official	146:f64d43ff0c18	5020	#endif
mbed_official	146:f64d43ff0c18	5021
mbed_official	146:f64d43ff0c18	5022	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER.
mbed_official	146:f64d43ff0c18	5023	#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
mbed_official	146:f64d43ff0c18	5024
mbed_official	146:f64d43ff0c18	5025	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5026	//! @brief Set the CITER field to a new value.
mbed_official	146:f64d43ff0c18	5027	#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) \| BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
mbed_official	146:f64d43ff0c18	5028	#endif
mbed_official	146:f64d43ff0c18	5029	//@}
mbed_official	146:f64d43ff0c18	5030
mbed_official	146:f64d43ff0c18	5031	/*!
mbed_official	146:f64d43ff0c18	5032	* @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
mbed_official	146:f64d43ff0c18	5033	*
mbed_official	146:f64d43ff0c18	5034	* As the channel completes the minor loop, this flag enables linking to another
mbed_official	146:f64d43ff0c18	5035	* channel, defined by the LINKCH field. The link target channel initiates a
mbed_official	146:f64d43ff0c18	5036	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	5037	* bit of the specified channel. If channel linking is disabled, the CITER value
mbed_official	146:f64d43ff0c18	5038	* is extended to 15 bits in place of a link channel number. If the major loop is
mbed_official	146:f64d43ff0c18	5039	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK
mbed_official	146:f64d43ff0c18	5040	* channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
mbed_official	146:f64d43ff0c18	5041	* configuration error is reported.
mbed_official	146:f64d43ff0c18	5042	*
mbed_official	146:f64d43ff0c18	5043	* Values:
mbed_official	146:f64d43ff0c18	5044	* - 0 - The channel-to-channel linking is disabled
mbed_official	146:f64d43ff0c18	5045	* - 1 - The channel-to-channel linking is enabled
mbed_official	146:f64d43ff0c18	5046	*/
mbed_official	146:f64d43ff0c18	5047	//@{
mbed_official	146:f64d43ff0c18	5048	#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5049	#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5050	#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5051
mbed_official	146:f64d43ff0c18	5052	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5053	//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field.
mbed_official	146:f64d43ff0c18	5054	#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
mbed_official	146:f64d43ff0c18	5055	#endif
mbed_official	146:f64d43ff0c18	5056
mbed_official	146:f64d43ff0c18	5057	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5058	#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
mbed_official	146:f64d43ff0c18	5059
mbed_official	146:f64d43ff0c18	5060	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5061	//! @brief Set the ELINK field to a new value.
mbed_official	146:f64d43ff0c18	5062	#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
mbed_official	146:f64d43ff0c18	5063	#endif
mbed_official	146:f64d43ff0c18	5064	//@}
mbed_official	146:f64d43ff0c18	5065	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5066	// HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official	146:f64d43ff0c18	5067	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5068
mbed_official	146:f64d43ff0c18	5069	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5070	/*!
mbed_official	146:f64d43ff0c18	5071	* @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
mbed_official	146:f64d43ff0c18	5072	*
mbed_official	146:f64d43ff0c18	5073	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	5074	*
mbed_official	146:f64d43ff0c18	5075	* If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
mbed_official	146:f64d43ff0c18	5076	*/
mbed_official	146:f64d43ff0c18	5077	typedef union _hw_dma_tcdn_citer_elinkyes
mbed_official	146:f64d43ff0c18	5078	{
mbed_official	146:f64d43ff0c18	5079	uint16_t U;
mbed_official	146:f64d43ff0c18	5080	struct _hw_dma_tcdn_citer_elinkyes_bitfields
mbed_official	146:f64d43ff0c18	5081	{
mbed_official	146:f64d43ff0c18	5082	uint16_t CITER : 9; //!< [8:0] Current Major Iteration Count
mbed_official	146:f64d43ff0c18	5083	uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
mbed_official	146:f64d43ff0c18	5084	uint16_t RESERVED0 : 2; //!< [14:13]
mbed_official	146:f64d43ff0c18	5085	uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
mbed_official	146:f64d43ff0c18	5086	//! minor-loop complete
mbed_official	146:f64d43ff0c18	5087	} B;
mbed_official	146:f64d43ff0c18	5088	} hw_dma_tcdn_citer_elinkyes_t;
mbed_official	146:f64d43ff0c18	5089	#endif
mbed_official	146:f64d43ff0c18	5090
mbed_official	146:f64d43ff0c18	5091	/*!
mbed_official	146:f64d43ff0c18	5092	* @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
mbed_official	146:f64d43ff0c18	5093	*/
mbed_official	146:f64d43ff0c18	5094	//@{
mbed_official	146:f64d43ff0c18	5095	#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
mbed_official	146:f64d43ff0c18	5096
mbed_official	146:f64d43ff0c18	5097	#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
mbed_official	146:f64d43ff0c18	5098
mbed_official	146:f64d43ff0c18	5099	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5100	#define HW_DMA_TCDn_CITER_ELINKYES(x, n) ((__IO hw_dma_tcdn_citer_elinkyes_t ) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
mbed_official	146:f64d43ff0c18	5101	#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
mbed_official	146:f64d43ff0c18	5102	#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
mbed_official	146:f64d43ff0c18	5103	#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	5104	#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	5105	#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	5106	#endif
mbed_official	146:f64d43ff0c18	5107	//@}
mbed_official	146:f64d43ff0c18	5108
mbed_official	146:f64d43ff0c18	5109	/*
mbed_official	146:f64d43ff0c18	5110	* Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
mbed_official	146:f64d43ff0c18	5111	*/
mbed_official	146:f64d43ff0c18	5112
mbed_official	146:f64d43ff0c18	5113	/*!
mbed_official	146:f64d43ff0c18	5114	* @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
mbed_official	146:f64d43ff0c18	5115	*
mbed_official	146:f64d43ff0c18	5116	* This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
mbed_official	146:f64d43ff0c18	5117	* major loop count for the channel. It is decremented each time the minor loop is
mbed_official	146:f64d43ff0c18	5118	* completed and updated in the transfer control descriptor memory. After the
mbed_official	146:f64d43ff0c18	5119	* major iteration count is exhausted, the channel performs a number of operations
mbed_official	146:f64d43ff0c18	5120	* (e.g., final source and destination address calculations), optionally generating
mbed_official	146:f64d43ff0c18	5121	* an interrupt to signal channel completion before reloading the CITER field
mbed_official	146:f64d43ff0c18	5122	* from the beginning iteration count (BITER) field. When the CITER field is
mbed_official	146:f64d43ff0c18	5123	* initially loaded by software, it must be set to the same value as that contained in
mbed_official	146:f64d43ff0c18	5124	* the BITER field. If the channel is configured to execute a single service
mbed_official	146:f64d43ff0c18	5125	* request, the initial values of BITER and CITER should be 0x0001.
mbed_official	146:f64d43ff0c18	5126	*/
mbed_official	146:f64d43ff0c18	5127	//@{
mbed_official	146:f64d43ff0c18	5128	#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER.
mbed_official	146:f64d43ff0c18	5129	#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER.
mbed_official	146:f64d43ff0c18	5130	#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER.
mbed_official	146:f64d43ff0c18	5131
mbed_official	146:f64d43ff0c18	5132	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5133	//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field.
mbed_official	146:f64d43ff0c18	5134	#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
mbed_official	146:f64d43ff0c18	5135	#endif
mbed_official	146:f64d43ff0c18	5136
mbed_official	146:f64d43ff0c18	5137	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER.
mbed_official	146:f64d43ff0c18	5138	#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
mbed_official	146:f64d43ff0c18	5139
mbed_official	146:f64d43ff0c18	5140	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5141	//! @brief Set the CITER field to a new value.
mbed_official	146:f64d43ff0c18	5142	#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) \| BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
mbed_official	146:f64d43ff0c18	5143	#endif
mbed_official	146:f64d43ff0c18	5144	//@}
mbed_official	146:f64d43ff0c18	5145
mbed_official	146:f64d43ff0c18	5146	/*!
mbed_official	146:f64d43ff0c18	5147	* @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
mbed_official	146:f64d43ff0c18	5148	*
mbed_official	146:f64d43ff0c18	5149	* If channel-to-channel linking is enabled (ELINK = 1), then after the minor
mbed_official	146:f64d43ff0c18	5150	* loop is exhausted, the eDMA engine initiates a channel service request to the
mbed_official	146:f64d43ff0c18	5151	* channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
mbed_official	146:f64d43ff0c18	5152	*/
mbed_official	146:f64d43ff0c18	5153	//@{
mbed_official	146:f64d43ff0c18	5154	#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5155	#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5156	#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5157
mbed_official	146:f64d43ff0c18	5158	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5159	//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field.
mbed_official	146:f64d43ff0c18	5160	#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
mbed_official	146:f64d43ff0c18	5161	#endif
mbed_official	146:f64d43ff0c18	5162
mbed_official	146:f64d43ff0c18	5163	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5164	#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
mbed_official	146:f64d43ff0c18	5165
mbed_official	146:f64d43ff0c18	5166	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5167	//! @brief Set the LINKCH field to a new value.
mbed_official	146:f64d43ff0c18	5168	#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) \| BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
mbed_official	146:f64d43ff0c18	5169	#endif
mbed_official	146:f64d43ff0c18	5170	//@}
mbed_official	146:f64d43ff0c18	5171
mbed_official	146:f64d43ff0c18	5172	/*!
mbed_official	146:f64d43ff0c18	5173	* @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
mbed_official	146:f64d43ff0c18	5174	*
mbed_official	146:f64d43ff0c18	5175	* As the channel completes the minor loop, this flag enables linking to another
mbed_official	146:f64d43ff0c18	5176	* channel, defined by the LINKCH field. The link target channel initiates a
mbed_official	146:f64d43ff0c18	5177	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	5178	* bit of the specified channel. If channel linking is disabled, the CITER value
mbed_official	146:f64d43ff0c18	5179	* is extended to 15 bits in place of a link channel number. If the major loop is
mbed_official	146:f64d43ff0c18	5180	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK
mbed_official	146:f64d43ff0c18	5181	* channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
mbed_official	146:f64d43ff0c18	5182	* configuration error is reported.
mbed_official	146:f64d43ff0c18	5183	*
mbed_official	146:f64d43ff0c18	5184	* Values:
mbed_official	146:f64d43ff0c18	5185	* - 0 - The channel-to-channel linking is disabled
mbed_official	146:f64d43ff0c18	5186	* - 1 - The channel-to-channel linking is enabled
mbed_official	146:f64d43ff0c18	5187	*/
mbed_official	146:f64d43ff0c18	5188	//@{
mbed_official	146:f64d43ff0c18	5189	#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5190	#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5191	#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5192
mbed_official	146:f64d43ff0c18	5193	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5194	//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field.
mbed_official	146:f64d43ff0c18	5195	#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
mbed_official	146:f64d43ff0c18	5196	#endif
mbed_official	146:f64d43ff0c18	5197
mbed_official	146:f64d43ff0c18	5198	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5199	#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
mbed_official	146:f64d43ff0c18	5200
mbed_official	146:f64d43ff0c18	5201	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5202	//! @brief Set the ELINK field to a new value.
mbed_official	146:f64d43ff0c18	5203	#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
mbed_official	146:f64d43ff0c18	5204	#endif
mbed_official	146:f64d43ff0c18	5205	//@}
mbed_official	146:f64d43ff0c18	5206	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5207	// HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
mbed_official	146:f64d43ff0c18	5208	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5209
mbed_official	146:f64d43ff0c18	5210	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5211	/*!
mbed_official	146:f64d43ff0c18	5212	* @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
mbed_official	146:f64d43ff0c18	5213	*
mbed_official	146:f64d43ff0c18	5214	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	5215	*/
mbed_official	146:f64d43ff0c18	5216	typedef union _hw_dma_tcdn_dlastsga
mbed_official	146:f64d43ff0c18	5217	{
mbed_official	146:f64d43ff0c18	5218	uint32_t U;
mbed_official	146:f64d43ff0c18	5219	struct _hw_dma_tcdn_dlastsga_bitfields
mbed_official	146:f64d43ff0c18	5220	{
mbed_official	146:f64d43ff0c18	5221	uint32_t DLASTSGA : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	5222	} B;
mbed_official	146:f64d43ff0c18	5223	} hw_dma_tcdn_dlastsga_t;
mbed_official	146:f64d43ff0c18	5224	#endif
mbed_official	146:f64d43ff0c18	5225
mbed_official	146:f64d43ff0c18	5226	/*!
mbed_official	146:f64d43ff0c18	5227	* @name Constants and macros for entire DMA_TCDn_DLASTSGA register
mbed_official	146:f64d43ff0c18	5228	*/
mbed_official	146:f64d43ff0c18	5229	//@{
mbed_official	146:f64d43ff0c18	5230	#define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
mbed_official	146:f64d43ff0c18	5231
mbed_official	146:f64d43ff0c18	5232	#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1018U + (0x20U * n))
mbed_official	146:f64d43ff0c18	5233
mbed_official	146:f64d43ff0c18	5234	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5235	#define HW_DMA_TCDn_DLASTSGA(x, n) ((__IO hw_dma_tcdn_dlastsga_t ) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
mbed_official	146:f64d43ff0c18	5236	#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
mbed_official	146:f64d43ff0c18	5237	#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
mbed_official	146:f64d43ff0c18	5238	#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	5239	#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	5240	#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	5241	#endif
mbed_official	146:f64d43ff0c18	5242	//@}
mbed_official	146:f64d43ff0c18	5243
mbed_official	146:f64d43ff0c18	5244	/*
mbed_official	146:f64d43ff0c18	5245	* Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
mbed_official	146:f64d43ff0c18	5246	*/
mbed_official	146:f64d43ff0c18	5247
mbed_official	146:f64d43ff0c18	5248	/*!
mbed_official	146:f64d43ff0c18	5249	* @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
mbed_official	146:f64d43ff0c18	5250	*
mbed_official	146:f64d43ff0c18	5251	* Destination last address adjustment or the memory address for the next
mbed_official	146:f64d43ff0c18	5252	* transfer control descriptor to be loaded into this channel (scatter/gather). If
mbed_official	146:f64d43ff0c18	5253	* (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
mbed_official	146:f64d43ff0c18	5254	* the completion of the major iteration count. This value can apply to restore the
mbed_official	146:f64d43ff0c18	5255	* destination address to the initial value or adjust the address to reference
mbed_official	146:f64d43ff0c18	5256	* the next data structure. This field uses two's complement notation for the
mbed_official	146:f64d43ff0c18	5257	* final destination address adjustment. Otherwise: This address points to the
mbed_official	146:f64d43ff0c18	5258	* beginning of a 0-modulo-32-byte region containing the next transfer control
mbed_official	146:f64d43ff0c18	5259	* descriptor to be loaded into this channel. This channel reload is performed as the
mbed_official	146:f64d43ff0c18	5260	* major iteration count completes. The scatter/gather address must be
mbed_official	146:f64d43ff0c18	5261	* 0-modulo-32-byte, else a configuration error is reported.
mbed_official	146:f64d43ff0c18	5262	*/
mbed_official	146:f64d43ff0c18	5263	//@{
mbed_official	146:f64d43ff0c18	5264	#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) //!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA.
mbed_official	146:f64d43ff0c18	5265	#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA.
mbed_official	146:f64d43ff0c18	5266	#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) //!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA.
mbed_official	146:f64d43ff0c18	5267
mbed_official	146:f64d43ff0c18	5268	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5269	//! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field.
mbed_official	146:f64d43ff0c18	5270	#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
mbed_official	146:f64d43ff0c18	5271	#endif
mbed_official	146:f64d43ff0c18	5272
mbed_official	146:f64d43ff0c18	5273	//! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA.
mbed_official	146:f64d43ff0c18	5274	#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DLASTSGA_DLASTSGA), uint32_t) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
mbed_official	146:f64d43ff0c18	5275
mbed_official	146:f64d43ff0c18	5276	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5277	//! @brief Set the DLASTSGA field to a new value.
mbed_official	146:f64d43ff0c18	5278	#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
mbed_official	146:f64d43ff0c18	5279	#endif
mbed_official	146:f64d43ff0c18	5280	//@}
mbed_official	146:f64d43ff0c18	5281	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5282	// HW_DMA_TCDn_CSR - TCD Control and Status
mbed_official	146:f64d43ff0c18	5283	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5284
mbed_official	146:f64d43ff0c18	5285	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5286	/*!
mbed_official	146:f64d43ff0c18	5287	* @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
mbed_official	146:f64d43ff0c18	5288	*
mbed_official	146:f64d43ff0c18	5289	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	5290	*/
mbed_official	146:f64d43ff0c18	5291	typedef union _hw_dma_tcdn_csr
mbed_official	146:f64d43ff0c18	5292	{
mbed_official	146:f64d43ff0c18	5293	uint16_t U;
mbed_official	146:f64d43ff0c18	5294	struct _hw_dma_tcdn_csr_bitfields
mbed_official	146:f64d43ff0c18	5295	{
mbed_official	146:f64d43ff0c18	5296	uint16_t START : 1; //!< [0] Channel Start
mbed_official	146:f64d43ff0c18	5297	uint16_t INTMAJOR : 1; //!< [1] Enable an interrupt when major
mbed_official	146:f64d43ff0c18	5298	//! iteration count completes
mbed_official	146:f64d43ff0c18	5299	uint16_t INTHALF : 1; //!< [2] Enable an interrupt when major counter
mbed_official	146:f64d43ff0c18	5300	//! is half complete.
mbed_official	146:f64d43ff0c18	5301	uint16_t DREQ : 1; //!< [3] Disable Request
mbed_official	146:f64d43ff0c18	5302	uint16_t ESG : 1; //!< [4] Enable Scatter/Gather Processing
mbed_official	146:f64d43ff0c18	5303	uint16_t MAJORELINK : 1; //!< [5] Enable channel-to-channel linking
mbed_official	146:f64d43ff0c18	5304	//! on major loop complete
mbed_official	146:f64d43ff0c18	5305	uint16_t ACTIVE : 1; //!< [6] Channel Active
mbed_official	146:f64d43ff0c18	5306	uint16_t DONE : 1; //!< [7] Channel Done
mbed_official	146:f64d43ff0c18	5307	uint16_t MAJORLINKCH : 4; //!< [11:8] Link Channel Number
mbed_official	146:f64d43ff0c18	5308	uint16_t RESERVED0 : 2; //!< [13:12]
mbed_official	146:f64d43ff0c18	5309	uint16_t BWC : 2; //!< [15:14] Bandwidth Control
mbed_official	146:f64d43ff0c18	5310	} B;
mbed_official	146:f64d43ff0c18	5311	} hw_dma_tcdn_csr_t;
mbed_official	146:f64d43ff0c18	5312	#endif
mbed_official	146:f64d43ff0c18	5313
mbed_official	146:f64d43ff0c18	5314	/*!
mbed_official	146:f64d43ff0c18	5315	* @name Constants and macros for entire DMA_TCDn_CSR register
mbed_official	146:f64d43ff0c18	5316	*/
mbed_official	146:f64d43ff0c18	5317	//@{
mbed_official	146:f64d43ff0c18	5318	#define HW_DMA_TCDn_CSR_COUNT (16U)
mbed_official	146:f64d43ff0c18	5319
mbed_official	146:f64d43ff0c18	5320	#define HW_DMA_TCDn_CSR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101CU + (0x20U * n))
mbed_official	146:f64d43ff0c18	5321
mbed_official	146:f64d43ff0c18	5322	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5323	#define HW_DMA_TCDn_CSR(x, n) ((__IO hw_dma_tcdn_csr_t ) HW_DMA_TCDn_CSR_ADDR(x, n))
mbed_official	146:f64d43ff0c18	5324	#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
mbed_official	146:f64d43ff0c18	5325	#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
mbed_official	146:f64d43ff0c18	5326	#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	5327	#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	5328	#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	5329	#endif
mbed_official	146:f64d43ff0c18	5330	//@}
mbed_official	146:f64d43ff0c18	5331
mbed_official	146:f64d43ff0c18	5332	/*
mbed_official	146:f64d43ff0c18	5333	* Constants & macros for individual DMA_TCDn_CSR bitfields
mbed_official	146:f64d43ff0c18	5334	*/
mbed_official	146:f64d43ff0c18	5335
mbed_official	146:f64d43ff0c18	5336	/*!
mbed_official	146:f64d43ff0c18	5337	* @name Register DMA_TCDn_CSR, field START[0] (RW)
mbed_official	146:f64d43ff0c18	5338	*
mbed_official	146:f64d43ff0c18	5339	* If this flag is set, the channel is requesting service. The eDMA hardware
mbed_official	146:f64d43ff0c18	5340	* automatically clears this flag after the channel begins execution.
mbed_official	146:f64d43ff0c18	5341	*
mbed_official	146:f64d43ff0c18	5342	* Values:
mbed_official	146:f64d43ff0c18	5343	* - 0 - The channel is not explicitly started
mbed_official	146:f64d43ff0c18	5344	* - 1 - The channel is explicitly started via a software initiated service
mbed_official	146:f64d43ff0c18	5345	* request
mbed_official	146:f64d43ff0c18	5346	*/
mbed_official	146:f64d43ff0c18	5347	//@{
mbed_official	146:f64d43ff0c18	5348	#define BP_DMA_TCDn_CSR_START (0U) //!< Bit position for DMA_TCDn_CSR_START.
mbed_official	146:f64d43ff0c18	5349	#define BM_DMA_TCDn_CSR_START (0x0001U) //!< Bit mask for DMA_TCDn_CSR_START.
mbed_official	146:f64d43ff0c18	5350	#define BS_DMA_TCDn_CSR_START (1U) //!< Bit field size in bits for DMA_TCDn_CSR_START.
mbed_official	146:f64d43ff0c18	5351
mbed_official	146:f64d43ff0c18	5352	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5353	//! @brief Read current value of the DMA_TCDn_CSR_START field.
mbed_official	146:f64d43ff0c18	5354	#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
mbed_official	146:f64d43ff0c18	5355	#endif
mbed_official	146:f64d43ff0c18	5356
mbed_official	146:f64d43ff0c18	5357	//! @brief Format value for bitfield DMA_TCDn_CSR_START.
mbed_official	146:f64d43ff0c18	5358	#define BF_DMA_TCDn_CSR_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_START), uint16_t) & BM_DMA_TCDn_CSR_START)
mbed_official	146:f64d43ff0c18	5359
mbed_official	146:f64d43ff0c18	5360	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5361	//! @brief Set the START field to a new value.
mbed_official	146:f64d43ff0c18	5362	#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
mbed_official	146:f64d43ff0c18	5363	#endif
mbed_official	146:f64d43ff0c18	5364	//@}
mbed_official	146:f64d43ff0c18	5365
mbed_official	146:f64d43ff0c18	5366	/*!
mbed_official	146:f64d43ff0c18	5367	* @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
mbed_official	146:f64d43ff0c18	5368	*
mbed_official	146:f64d43ff0c18	5369	* If this flag is set, the channel generates an interrupt request by setting
mbed_official	146:f64d43ff0c18	5370	* the appropriate bit in the INT when the current major iteration count reaches
mbed_official	146:f64d43ff0c18	5371	* zero.
mbed_official	146:f64d43ff0c18	5372	*
mbed_official	146:f64d43ff0c18	5373	* Values:
mbed_official	146:f64d43ff0c18	5374	* - 0 - The end-of-major loop interrupt is disabled
mbed_official	146:f64d43ff0c18	5375	* - 1 - The end-of-major loop interrupt is enabled
mbed_official	146:f64d43ff0c18	5376	*/
mbed_official	146:f64d43ff0c18	5377	//@{
mbed_official	146:f64d43ff0c18	5378	#define BP_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit position for DMA_TCDn_CSR_INTMAJOR.
mbed_official	146:f64d43ff0c18	5379	#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) //!< Bit mask for DMA_TCDn_CSR_INTMAJOR.
mbed_official	146:f64d43ff0c18	5380	#define BS_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR.
mbed_official	146:f64d43ff0c18	5381
mbed_official	146:f64d43ff0c18	5382	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5383	//! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field.
mbed_official	146:f64d43ff0c18	5384	#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
mbed_official	146:f64d43ff0c18	5385	#endif
mbed_official	146:f64d43ff0c18	5386
mbed_official	146:f64d43ff0c18	5387	//! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR.
mbed_official	146:f64d43ff0c18	5388	#define BF_DMA_TCDn_CSR_INTMAJOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTMAJOR), uint16_t) & BM_DMA_TCDn_CSR_INTMAJOR)
mbed_official	146:f64d43ff0c18	5389
mbed_official	146:f64d43ff0c18	5390	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5391	//! @brief Set the INTMAJOR field to a new value.
mbed_official	146:f64d43ff0c18	5392	#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
mbed_official	146:f64d43ff0c18	5393	#endif
mbed_official	146:f64d43ff0c18	5394	//@}
mbed_official	146:f64d43ff0c18	5395
mbed_official	146:f64d43ff0c18	5396	/*!
mbed_official	146:f64d43ff0c18	5397	* @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
mbed_official	146:f64d43ff0c18	5398	*
mbed_official	146:f64d43ff0c18	5399	* If this flag is set, the channel generates an interrupt request by setting
mbed_official	146:f64d43ff0c18	5400	* the appropriate bit in the INT register when the current major iteration count
mbed_official	146:f64d43ff0c18	5401	* reaches the halfway point. Specifically, the comparison performed by the eDMA
mbed_official	146:f64d43ff0c18	5402	* engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
mbed_official	146:f64d43ff0c18	5403	* provided to support double-buffered (aka ping-pong) schemes or other types of data
mbed_official	146:f64d43ff0c18	5404	* movement where the processor needs an early indication of the transfer's
mbed_official	146:f64d43ff0c18	5405	* progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
mbed_official	146:f64d43ff0c18	5406	*
mbed_official	146:f64d43ff0c18	5407	* Values:
mbed_official	146:f64d43ff0c18	5408	* - 0 - The half-point interrupt is disabled
mbed_official	146:f64d43ff0c18	5409	* - 1 - The half-point interrupt is enabled
mbed_official	146:f64d43ff0c18	5410	*/
mbed_official	146:f64d43ff0c18	5411	//@{
mbed_official	146:f64d43ff0c18	5412	#define BP_DMA_TCDn_CSR_INTHALF (2U) //!< Bit position for DMA_TCDn_CSR_INTHALF.
mbed_official	146:f64d43ff0c18	5413	#define BM_DMA_TCDn_CSR_INTHALF (0x0004U) //!< Bit mask for DMA_TCDn_CSR_INTHALF.
mbed_official	146:f64d43ff0c18	5414	#define BS_DMA_TCDn_CSR_INTHALF (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTHALF.
mbed_official	146:f64d43ff0c18	5415
mbed_official	146:f64d43ff0c18	5416	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5417	//! @brief Read current value of the DMA_TCDn_CSR_INTHALF field.
mbed_official	146:f64d43ff0c18	5418	#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
mbed_official	146:f64d43ff0c18	5419	#endif
mbed_official	146:f64d43ff0c18	5420
mbed_official	146:f64d43ff0c18	5421	//! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF.
mbed_official	146:f64d43ff0c18	5422	#define BF_DMA_TCDn_CSR_INTHALF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTHALF), uint16_t) & BM_DMA_TCDn_CSR_INTHALF)
mbed_official	146:f64d43ff0c18	5423
mbed_official	146:f64d43ff0c18	5424	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5425	//! @brief Set the INTHALF field to a new value.
mbed_official	146:f64d43ff0c18	5426	#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
mbed_official	146:f64d43ff0c18	5427	#endif
mbed_official	146:f64d43ff0c18	5428	//@}
mbed_official	146:f64d43ff0c18	5429
mbed_official	146:f64d43ff0c18	5430	/*!
mbed_official	146:f64d43ff0c18	5431	* @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
mbed_official	146:f64d43ff0c18	5432	*
mbed_official	146:f64d43ff0c18	5433	* If this flag is set, the eDMA hardware automatically clears the corresponding
mbed_official	146:f64d43ff0c18	5434	* ERQ bit when the current major iteration count reaches zero.
mbed_official	146:f64d43ff0c18	5435	*
mbed_official	146:f64d43ff0c18	5436	* Values:
mbed_official	146:f64d43ff0c18	5437	* - 0 - The channel's ERQ bit is not affected
mbed_official	146:f64d43ff0c18	5438	* - 1 - The channel's ERQ bit is cleared when the major loop is complete
mbed_official	146:f64d43ff0c18	5439	*/
mbed_official	146:f64d43ff0c18	5440	//@{
mbed_official	146:f64d43ff0c18	5441	#define BP_DMA_TCDn_CSR_DREQ (3U) //!< Bit position for DMA_TCDn_CSR_DREQ.
mbed_official	146:f64d43ff0c18	5442	#define BM_DMA_TCDn_CSR_DREQ (0x0008U) //!< Bit mask for DMA_TCDn_CSR_DREQ.
mbed_official	146:f64d43ff0c18	5443	#define BS_DMA_TCDn_CSR_DREQ (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DREQ.
mbed_official	146:f64d43ff0c18	5444
mbed_official	146:f64d43ff0c18	5445	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5446	//! @brief Read current value of the DMA_TCDn_CSR_DREQ field.
mbed_official	146:f64d43ff0c18	5447	#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
mbed_official	146:f64d43ff0c18	5448	#endif
mbed_official	146:f64d43ff0c18	5449
mbed_official	146:f64d43ff0c18	5450	//! @brief Format value for bitfield DMA_TCDn_CSR_DREQ.
mbed_official	146:f64d43ff0c18	5451	#define BF_DMA_TCDn_CSR_DREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DREQ), uint16_t) & BM_DMA_TCDn_CSR_DREQ)
mbed_official	146:f64d43ff0c18	5452
mbed_official	146:f64d43ff0c18	5453	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5454	//! @brief Set the DREQ field to a new value.
mbed_official	146:f64d43ff0c18	5455	#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
mbed_official	146:f64d43ff0c18	5456	#endif
mbed_official	146:f64d43ff0c18	5457	//@}
mbed_official	146:f64d43ff0c18	5458
mbed_official	146:f64d43ff0c18	5459	/*!
mbed_official	146:f64d43ff0c18	5460	* @name Register DMA_TCDn_CSR, field ESG[4] (RW)
mbed_official	146:f64d43ff0c18	5461	*
mbed_official	146:f64d43ff0c18	5462	* As the channel completes the major loop, this flag enables scatter/gather
mbed_official	146:f64d43ff0c18	5463	* processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
mbed_official	146:f64d43ff0c18	5464	* memory pointer to a 0-modulo-32 address containing a 32-byte data structure
mbed_official	146:f64d43ff0c18	5465	* loaded as the transfer control descriptor into the local memory. To support the
mbed_official	146:f64d43ff0c18	5466	* dynamic scatter/gather coherency model, this field is forced to zero when
mbed_official	146:f64d43ff0c18	5467	* written to while the TCDn_CSR[DONE] bit is set.
mbed_official	146:f64d43ff0c18	5468	*
mbed_official	146:f64d43ff0c18	5469	* Values:
mbed_official	146:f64d43ff0c18	5470	* - 0 - The current channel's TCD is normal format.
mbed_official	146:f64d43ff0c18	5471	* - 1 - The current channel's TCD specifies a scatter gather format. The
mbed_official	146:f64d43ff0c18	5472	* DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
mbed_official	146:f64d43ff0c18	5473	* channel after the major loop completes its execution.
mbed_official	146:f64d43ff0c18	5474	*/
mbed_official	146:f64d43ff0c18	5475	//@{
mbed_official	146:f64d43ff0c18	5476	#define BP_DMA_TCDn_CSR_ESG (4U) //!< Bit position for DMA_TCDn_CSR_ESG.
mbed_official	146:f64d43ff0c18	5477	#define BM_DMA_TCDn_CSR_ESG (0x0010U) //!< Bit mask for DMA_TCDn_CSR_ESG.
mbed_official	146:f64d43ff0c18	5478	#define BS_DMA_TCDn_CSR_ESG (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ESG.
mbed_official	146:f64d43ff0c18	5479
mbed_official	146:f64d43ff0c18	5480	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5481	//! @brief Read current value of the DMA_TCDn_CSR_ESG field.
mbed_official	146:f64d43ff0c18	5482	#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
mbed_official	146:f64d43ff0c18	5483	#endif
mbed_official	146:f64d43ff0c18	5484
mbed_official	146:f64d43ff0c18	5485	//! @brief Format value for bitfield DMA_TCDn_CSR_ESG.
mbed_official	146:f64d43ff0c18	5486	#define BF_DMA_TCDn_CSR_ESG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ESG), uint16_t) & BM_DMA_TCDn_CSR_ESG)
mbed_official	146:f64d43ff0c18	5487
mbed_official	146:f64d43ff0c18	5488	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5489	//! @brief Set the ESG field to a new value.
mbed_official	146:f64d43ff0c18	5490	#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
mbed_official	146:f64d43ff0c18	5491	#endif
mbed_official	146:f64d43ff0c18	5492	//@}
mbed_official	146:f64d43ff0c18	5493
mbed_official	146:f64d43ff0c18	5494	/*!
mbed_official	146:f64d43ff0c18	5495	* @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
mbed_official	146:f64d43ff0c18	5496	*
mbed_official	146:f64d43ff0c18	5497	* As the channel completes the major loop, this flag enables the linking to
mbed_official	146:f64d43ff0c18	5498	* another channel, defined by MAJORLINKCH. The link target channel initiates a
mbed_official	146:f64d43ff0c18	5499	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	5500	* bit of the specified channel. To support the dynamic linking coherency model,
mbed_official	146:f64d43ff0c18	5501	* this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
mbed_official	146:f64d43ff0c18	5502	*
mbed_official	146:f64d43ff0c18	5503	* Values:
mbed_official	146:f64d43ff0c18	5504	* - 0 - The channel-to-channel linking is disabled
mbed_official	146:f64d43ff0c18	5505	* - 1 - The channel-to-channel linking is enabled
mbed_official	146:f64d43ff0c18	5506	*/
mbed_official	146:f64d43ff0c18	5507	//@{
mbed_official	146:f64d43ff0c18	5508	#define BP_DMA_TCDn_CSR_MAJORELINK (5U) //!< Bit position for DMA_TCDn_CSR_MAJORELINK.
mbed_official	146:f64d43ff0c18	5509	#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) //!< Bit mask for DMA_TCDn_CSR_MAJORELINK.
mbed_official	146:f64d43ff0c18	5510	#define BS_DMA_TCDn_CSR_MAJORELINK (1U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK.
mbed_official	146:f64d43ff0c18	5511
mbed_official	146:f64d43ff0c18	5512	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5513	//! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field.
mbed_official	146:f64d43ff0c18	5514	#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
mbed_official	146:f64d43ff0c18	5515	#endif
mbed_official	146:f64d43ff0c18	5516
mbed_official	146:f64d43ff0c18	5517	//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK.
mbed_official	146:f64d43ff0c18	5518	#define BF_DMA_TCDn_CSR_MAJORELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORELINK), uint16_t) & BM_DMA_TCDn_CSR_MAJORELINK)
mbed_official	146:f64d43ff0c18	5519
mbed_official	146:f64d43ff0c18	5520	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5521	//! @brief Set the MAJORELINK field to a new value.
mbed_official	146:f64d43ff0c18	5522	#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
mbed_official	146:f64d43ff0c18	5523	#endif
mbed_official	146:f64d43ff0c18	5524	//@}
mbed_official	146:f64d43ff0c18	5525
mbed_official	146:f64d43ff0c18	5526	/*!
mbed_official	146:f64d43ff0c18	5527	* @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
mbed_official	146:f64d43ff0c18	5528	*
mbed_official	146:f64d43ff0c18	5529	* This flag signals the channel is currently in execution. It is set when
mbed_official	146:f64d43ff0c18	5530	* channel service begins, and the eDMA clears it as the minor loop completes or if
mbed_official	146:f64d43ff0c18	5531	* any error condition is detected. This bit resets to zero.
mbed_official	146:f64d43ff0c18	5532	*/
mbed_official	146:f64d43ff0c18	5533	//@{
mbed_official	146:f64d43ff0c18	5534	#define BP_DMA_TCDn_CSR_ACTIVE (6U) //!< Bit position for DMA_TCDn_CSR_ACTIVE.
mbed_official	146:f64d43ff0c18	5535	#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) //!< Bit mask for DMA_TCDn_CSR_ACTIVE.
mbed_official	146:f64d43ff0c18	5536	#define BS_DMA_TCDn_CSR_ACTIVE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE.
mbed_official	146:f64d43ff0c18	5537
mbed_official	146:f64d43ff0c18	5538	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5539	//! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field.
mbed_official	146:f64d43ff0c18	5540	#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
mbed_official	146:f64d43ff0c18	5541	#endif
mbed_official	146:f64d43ff0c18	5542
mbed_official	146:f64d43ff0c18	5543	//! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE.
mbed_official	146:f64d43ff0c18	5544	#define BF_DMA_TCDn_CSR_ACTIVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ACTIVE), uint16_t) & BM_DMA_TCDn_CSR_ACTIVE)
mbed_official	146:f64d43ff0c18	5545
mbed_official	146:f64d43ff0c18	5546	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5547	//! @brief Set the ACTIVE field to a new value.
mbed_official	146:f64d43ff0c18	5548	#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
mbed_official	146:f64d43ff0c18	5549	#endif
mbed_official	146:f64d43ff0c18	5550	//@}
mbed_official	146:f64d43ff0c18	5551
mbed_official	146:f64d43ff0c18	5552	/*!
mbed_official	146:f64d43ff0c18	5553	* @name Register DMA_TCDn_CSR, field DONE[7] (RW)
mbed_official	146:f64d43ff0c18	5554	*
mbed_official	146:f64d43ff0c18	5555	* This flag indicates the eDMA has completed the major loop. The eDMA engine
mbed_official	146:f64d43ff0c18	5556	* sets it as the CITER count reaches zero; The software clears it, or the hardware
mbed_official	146:f64d43ff0c18	5557	* when the channel is activated. This bit must be cleared to write the
mbed_official	146:f64d43ff0c18	5558	* MAJORELINK or ESG bits.
mbed_official	146:f64d43ff0c18	5559	*/
mbed_official	146:f64d43ff0c18	5560	//@{
mbed_official	146:f64d43ff0c18	5561	#define BP_DMA_TCDn_CSR_DONE (7U) //!< Bit position for DMA_TCDn_CSR_DONE.
mbed_official	146:f64d43ff0c18	5562	#define BM_DMA_TCDn_CSR_DONE (0x0080U) //!< Bit mask for DMA_TCDn_CSR_DONE.
mbed_official	146:f64d43ff0c18	5563	#define BS_DMA_TCDn_CSR_DONE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DONE.
mbed_official	146:f64d43ff0c18	5564
mbed_official	146:f64d43ff0c18	5565	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5566	//! @brief Read current value of the DMA_TCDn_CSR_DONE field.
mbed_official	146:f64d43ff0c18	5567	#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
mbed_official	146:f64d43ff0c18	5568	#endif
mbed_official	146:f64d43ff0c18	5569
mbed_official	146:f64d43ff0c18	5570	//! @brief Format value for bitfield DMA_TCDn_CSR_DONE.
mbed_official	146:f64d43ff0c18	5571	#define BF_DMA_TCDn_CSR_DONE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DONE), uint16_t) & BM_DMA_TCDn_CSR_DONE)
mbed_official	146:f64d43ff0c18	5572
mbed_official	146:f64d43ff0c18	5573	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5574	//! @brief Set the DONE field to a new value.
mbed_official	146:f64d43ff0c18	5575	#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
mbed_official	146:f64d43ff0c18	5576	#endif
mbed_official	146:f64d43ff0c18	5577	//@}
mbed_official	146:f64d43ff0c18	5578
mbed_official	146:f64d43ff0c18	5579	/*!
mbed_official	146:f64d43ff0c18	5580	* @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
mbed_official	146:f64d43ff0c18	5581	*
mbed_official	146:f64d43ff0c18	5582	* If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
mbed_official	146:f64d43ff0c18	5583	* performed after the major loop counter is exhausted. else After the major loop
mbed_official	146:f64d43ff0c18	5584	* counter is exhausted, the eDMA engine initiates a channel service request at the
mbed_official	146:f64d43ff0c18	5585	* channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
mbed_official	146:f64d43ff0c18	5586	*/
mbed_official	146:f64d43ff0c18	5587	//@{
mbed_official	146:f64d43ff0c18	5588	#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) //!< Bit position for DMA_TCDn_CSR_MAJORLINKCH.
mbed_official	146:f64d43ff0c18	5589	#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) //!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH.
mbed_official	146:f64d43ff0c18	5590	#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH.
mbed_official	146:f64d43ff0c18	5591
mbed_official	146:f64d43ff0c18	5592	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5593	//! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field.
mbed_official	146:f64d43ff0c18	5594	#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
mbed_official	146:f64d43ff0c18	5595	#endif
mbed_official	146:f64d43ff0c18	5596
mbed_official	146:f64d43ff0c18	5597	//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH.
mbed_official	146:f64d43ff0c18	5598	#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORLINKCH), uint16_t) & BM_DMA_TCDn_CSR_MAJORLINKCH)
mbed_official	146:f64d43ff0c18	5599
mbed_official	146:f64d43ff0c18	5600	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5601	//! @brief Set the MAJORLINKCH field to a new value.
mbed_official	146:f64d43ff0c18	5602	#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) \| BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
mbed_official	146:f64d43ff0c18	5603	#endif
mbed_official	146:f64d43ff0c18	5604	//@}
mbed_official	146:f64d43ff0c18	5605
mbed_official	146:f64d43ff0c18	5606	/*!
mbed_official	146:f64d43ff0c18	5607	* @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
mbed_official	146:f64d43ff0c18	5608	*
mbed_official	146:f64d43ff0c18	5609	* Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
mbed_official	146:f64d43ff0c18	5610	* the eDMA processes the minor loop, it continuously generates read/write
mbed_official	146:f64d43ff0c18	5611	* sequences until the minor count is exhausted. This field forces the eDMA to stall
mbed_official	146:f64d43ff0c18	5612	* after the completion of each read/write access to control the bus request
mbed_official	146:f64d43ff0c18	5613	* bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
mbed_official	146:f64d43ff0c18	5614	* this field is ignored between the first and second transfers and after the
mbed_official	146:f64d43ff0c18	5615	* last write of each minor loop. This behavior is a side effect of reducing
mbed_official	146:f64d43ff0c18	5616	* start-up latency.
mbed_official	146:f64d43ff0c18	5617	*
mbed_official	146:f64d43ff0c18	5618	* Values:
mbed_official	146:f64d43ff0c18	5619	* - 00 - No eDMA engine stalls
mbed_official	146:f64d43ff0c18	5620	* - 01 - Reserved
mbed_official	146:f64d43ff0c18	5621	* - 10 - eDMA engine stalls for 4 cycles after each r/w
mbed_official	146:f64d43ff0c18	5622	* - 11 - eDMA engine stalls for 8 cycles after each r/w
mbed_official	146:f64d43ff0c18	5623	*/
mbed_official	146:f64d43ff0c18	5624	//@{
mbed_official	146:f64d43ff0c18	5625	#define BP_DMA_TCDn_CSR_BWC (14U) //!< Bit position for DMA_TCDn_CSR_BWC.
mbed_official	146:f64d43ff0c18	5626	#define BM_DMA_TCDn_CSR_BWC (0xC000U) //!< Bit mask for DMA_TCDn_CSR_BWC.
mbed_official	146:f64d43ff0c18	5627	#define BS_DMA_TCDn_CSR_BWC (2U) //!< Bit field size in bits for DMA_TCDn_CSR_BWC.
mbed_official	146:f64d43ff0c18	5628
mbed_official	146:f64d43ff0c18	5629	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5630	//! @brief Read current value of the DMA_TCDn_CSR_BWC field.
mbed_official	146:f64d43ff0c18	5631	#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
mbed_official	146:f64d43ff0c18	5632	#endif
mbed_official	146:f64d43ff0c18	5633
mbed_official	146:f64d43ff0c18	5634	//! @brief Format value for bitfield DMA_TCDn_CSR_BWC.
mbed_official	146:f64d43ff0c18	5635	#define BF_DMA_TCDn_CSR_BWC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_BWC), uint16_t) & BM_DMA_TCDn_CSR_BWC)
mbed_official	146:f64d43ff0c18	5636
mbed_official	146:f64d43ff0c18	5637	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5638	//! @brief Set the BWC field to a new value.
mbed_official	146:f64d43ff0c18	5639	#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) \| BF_DMA_TCDn_CSR_BWC(v)))
mbed_official	146:f64d43ff0c18	5640	#endif
mbed_official	146:f64d43ff0c18	5641	//@}
mbed_official	146:f64d43ff0c18	5642	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5643	// HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official	146:f64d43ff0c18	5644	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5645
mbed_official	146:f64d43ff0c18	5646	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5647	/*!
mbed_official	146:f64d43ff0c18	5648	* @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
mbed_official	146:f64d43ff0c18	5649	*
mbed_official	146:f64d43ff0c18	5650	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	5651	*
mbed_official	146:f64d43ff0c18	5652	* If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
mbed_official	146:f64d43ff0c18	5653	* as follows.
mbed_official	146:f64d43ff0c18	5654	*/
mbed_official	146:f64d43ff0c18	5655	typedef union _hw_dma_tcdn_biter_elinkno
mbed_official	146:f64d43ff0c18	5656	{
mbed_official	146:f64d43ff0c18	5657	uint16_t U;
mbed_official	146:f64d43ff0c18	5658	struct _hw_dma_tcdn_biter_elinkno_bitfields
mbed_official	146:f64d43ff0c18	5659	{
mbed_official	146:f64d43ff0c18	5660	uint16_t BITER : 15; //!< [14:0] Starting Major Iteration Count
mbed_official	146:f64d43ff0c18	5661	uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
mbed_official	146:f64d43ff0c18	5662	//! minor loop complete
mbed_official	146:f64d43ff0c18	5663	} B;
mbed_official	146:f64d43ff0c18	5664	} hw_dma_tcdn_biter_elinkno_t;
mbed_official	146:f64d43ff0c18	5665	#endif
mbed_official	146:f64d43ff0c18	5666
mbed_official	146:f64d43ff0c18	5667	/*!
mbed_official	146:f64d43ff0c18	5668	* @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
mbed_official	146:f64d43ff0c18	5669	*/
mbed_official	146:f64d43ff0c18	5670	//@{
mbed_official	146:f64d43ff0c18	5671	#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
mbed_official	146:f64d43ff0c18	5672
mbed_official	146:f64d43ff0c18	5673	#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
mbed_official	146:f64d43ff0c18	5674
mbed_official	146:f64d43ff0c18	5675	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5676	#define HW_DMA_TCDn_BITER_ELINKNO(x, n) ((__IO hw_dma_tcdn_biter_elinkno_t ) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
mbed_official	146:f64d43ff0c18	5677	#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
mbed_official	146:f64d43ff0c18	5678	#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
mbed_official	146:f64d43ff0c18	5679	#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	5680	#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	5681	#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	5682	#endif
mbed_official	146:f64d43ff0c18	5683	//@}
mbed_official	146:f64d43ff0c18	5684
mbed_official	146:f64d43ff0c18	5685	/*
mbed_official	146:f64d43ff0c18	5686	* Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
mbed_official	146:f64d43ff0c18	5687	*/
mbed_official	146:f64d43ff0c18	5688
mbed_official	146:f64d43ff0c18	5689	/*!
mbed_official	146:f64d43ff0c18	5690	* @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
mbed_official	146:f64d43ff0c18	5691	*
mbed_official	146:f64d43ff0c18	5692	* As the transfer control descriptor is first loaded by software, this 9-bit
mbed_official	146:f64d43ff0c18	5693	* (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
mbed_official	146:f64d43ff0c18	5694	* field. As the major iteration count is exhausted, the contents of this field
mbed_official	146:f64d43ff0c18	5695	* are reloaded into the CITER field. When the software loads the TCD, this field
mbed_official	146:f64d43ff0c18	5696	* must be set equal to the corresponding CITER field; otherwise, a configuration
mbed_official	146:f64d43ff0c18	5697	* error is reported. As the major iteration count is exhausted, the contents of
mbed_official	146:f64d43ff0c18	5698	* this field is reloaded into the CITER field. If the channel is configured to
mbed_official	146:f64d43ff0c18	5699	* execute a single service request, the initial values of BITER and CITER should
mbed_official	146:f64d43ff0c18	5700	* be 0x0001.
mbed_official	146:f64d43ff0c18	5701	*/
mbed_official	146:f64d43ff0c18	5702	//@{
mbed_official	146:f64d43ff0c18	5703	#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER.
mbed_official	146:f64d43ff0c18	5704	#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER.
mbed_official	146:f64d43ff0c18	5705	#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER.
mbed_official	146:f64d43ff0c18	5706
mbed_official	146:f64d43ff0c18	5707	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5708	//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field.
mbed_official	146:f64d43ff0c18	5709	#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
mbed_official	146:f64d43ff0c18	5710	#endif
mbed_official	146:f64d43ff0c18	5711
mbed_official	146:f64d43ff0c18	5712	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER.
mbed_official	146:f64d43ff0c18	5713	#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
mbed_official	146:f64d43ff0c18	5714
mbed_official	146:f64d43ff0c18	5715	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5716	//! @brief Set the BITER field to a new value.
mbed_official	146:f64d43ff0c18	5717	#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) \| BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
mbed_official	146:f64d43ff0c18	5718	#endif
mbed_official	146:f64d43ff0c18	5719	//@}
mbed_official	146:f64d43ff0c18	5720
mbed_official	146:f64d43ff0c18	5721	/*!
mbed_official	146:f64d43ff0c18	5722	* @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
mbed_official	146:f64d43ff0c18	5723	*
mbed_official	146:f64d43ff0c18	5724	* As the channel completes the minor loop, this flag enables the linking to
mbed_official	146:f64d43ff0c18	5725	* another channel, defined by BITER[LINKCH]. The link target channel initiates a
mbed_official	146:f64d43ff0c18	5726	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	5727	* bit of the specified channel. If channel linking is disabled, the BITER value
mbed_official	146:f64d43ff0c18	5728	* extends to 15 bits in place of a link channel number. If the major loop is
mbed_official	146:f64d43ff0c18	5729	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
mbed_official	146:f64d43ff0c18	5730	* linking. When the software loads the TCD, this field must be set equal to the
mbed_official	146:f64d43ff0c18	5731	* corresponding CITER field; otherwise, a configuration error is reported. As the
mbed_official	146:f64d43ff0c18	5732	* major iteration count is exhausted, the contents of this field is reloaded
mbed_official	146:f64d43ff0c18	5733	* into the CITER field.
mbed_official	146:f64d43ff0c18	5734	*
mbed_official	146:f64d43ff0c18	5735	* Values:
mbed_official	146:f64d43ff0c18	5736	* - 0 - The channel-to-channel linking is disabled
mbed_official	146:f64d43ff0c18	5737	* - 1 - The channel-to-channel linking is enabled
mbed_official	146:f64d43ff0c18	5738	*/
mbed_official	146:f64d43ff0c18	5739	//@{
mbed_official	146:f64d43ff0c18	5740	#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5741	#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5742	#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5743
mbed_official	146:f64d43ff0c18	5744	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5745	//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field.
mbed_official	146:f64d43ff0c18	5746	#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
mbed_official	146:f64d43ff0c18	5747	#endif
mbed_official	146:f64d43ff0c18	5748
mbed_official	146:f64d43ff0c18	5749	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK.
mbed_official	146:f64d43ff0c18	5750	#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
mbed_official	146:f64d43ff0c18	5751
mbed_official	146:f64d43ff0c18	5752	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5753	//! @brief Set the ELINK field to a new value.
mbed_official	146:f64d43ff0c18	5754	#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
mbed_official	146:f64d43ff0c18	5755	#endif
mbed_official	146:f64d43ff0c18	5756	//@}
mbed_official	146:f64d43ff0c18	5757	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5758	// HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official	146:f64d43ff0c18	5759	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5760
mbed_official	146:f64d43ff0c18	5761	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5762	/*!
mbed_official	146:f64d43ff0c18	5763	* @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
mbed_official	146:f64d43ff0c18	5764	*
mbed_official	146:f64d43ff0c18	5765	* Reset value: 0x0000U
mbed_official	146:f64d43ff0c18	5766	*
mbed_official	146:f64d43ff0c18	5767	* If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
mbed_official	146:f64d43ff0c18	5768	* follows.
mbed_official	146:f64d43ff0c18	5769	*/
mbed_official	146:f64d43ff0c18	5770	typedef union _hw_dma_tcdn_biter_elinkyes
mbed_official	146:f64d43ff0c18	5771	{
mbed_official	146:f64d43ff0c18	5772	uint16_t U;
mbed_official	146:f64d43ff0c18	5773	struct _hw_dma_tcdn_biter_elinkyes_bitfields
mbed_official	146:f64d43ff0c18	5774	{
mbed_official	146:f64d43ff0c18	5775	uint16_t BITER : 9; //!< [8:0] Starting Major Iteration Count
mbed_official	146:f64d43ff0c18	5776	uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
mbed_official	146:f64d43ff0c18	5777	uint16_t RESERVED0 : 2; //!< [14:13]
mbed_official	146:f64d43ff0c18	5778	uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
mbed_official	146:f64d43ff0c18	5779	//! minor loop complete
mbed_official	146:f64d43ff0c18	5780	} B;
mbed_official	146:f64d43ff0c18	5781	} hw_dma_tcdn_biter_elinkyes_t;
mbed_official	146:f64d43ff0c18	5782	#endif
mbed_official	146:f64d43ff0c18	5783
mbed_official	146:f64d43ff0c18	5784	/*!
mbed_official	146:f64d43ff0c18	5785	* @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
mbed_official	146:f64d43ff0c18	5786	*/
mbed_official	146:f64d43ff0c18	5787	//@{
mbed_official	146:f64d43ff0c18	5788	#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
mbed_official	146:f64d43ff0c18	5789
mbed_official	146:f64d43ff0c18	5790	#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
mbed_official	146:f64d43ff0c18	5791
mbed_official	146:f64d43ff0c18	5792	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5793	#define HW_DMA_TCDn_BITER_ELINKYES(x, n) ((__IO hw_dma_tcdn_biter_elinkyes_t ) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
mbed_official	146:f64d43ff0c18	5794	#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
mbed_official	146:f64d43ff0c18	5795	#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
mbed_official	146:f64d43ff0c18	5796	#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	5797	#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	5798	#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	5799	#endif
mbed_official	146:f64d43ff0c18	5800	//@}
mbed_official	146:f64d43ff0c18	5801
mbed_official	146:f64d43ff0c18	5802	/*
mbed_official	146:f64d43ff0c18	5803	* Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
mbed_official	146:f64d43ff0c18	5804	*/
mbed_official	146:f64d43ff0c18	5805
mbed_official	146:f64d43ff0c18	5806	/*!
mbed_official	146:f64d43ff0c18	5807	* @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
mbed_official	146:f64d43ff0c18	5808	*
mbed_official	146:f64d43ff0c18	5809	* As the transfer control descriptor is first loaded by software, this 9-bit
mbed_official	146:f64d43ff0c18	5810	* (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
mbed_official	146:f64d43ff0c18	5811	* field. As the major iteration count is exhausted, the contents of this field
mbed_official	146:f64d43ff0c18	5812	* are reloaded into the CITER field. When the software loads the TCD, this field
mbed_official	146:f64d43ff0c18	5813	* must be set equal to the corresponding CITER field; otherwise, a configuration
mbed_official	146:f64d43ff0c18	5814	* error is reported. As the major iteration count is exhausted, the contents of
mbed_official	146:f64d43ff0c18	5815	* this field is reloaded into the CITER field. If the channel is configured to
mbed_official	146:f64d43ff0c18	5816	* execute a single service request, the initial values of BITER and CITER should
mbed_official	146:f64d43ff0c18	5817	* be 0x0001.
mbed_official	146:f64d43ff0c18	5818	*/
mbed_official	146:f64d43ff0c18	5819	//@{
mbed_official	146:f64d43ff0c18	5820	#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER.
mbed_official	146:f64d43ff0c18	5821	#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER.
mbed_official	146:f64d43ff0c18	5822	#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER.
mbed_official	146:f64d43ff0c18	5823
mbed_official	146:f64d43ff0c18	5824	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5825	//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field.
mbed_official	146:f64d43ff0c18	5826	#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
mbed_official	146:f64d43ff0c18	5827	#endif
mbed_official	146:f64d43ff0c18	5828
mbed_official	146:f64d43ff0c18	5829	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER.
mbed_official	146:f64d43ff0c18	5830	#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
mbed_official	146:f64d43ff0c18	5831
mbed_official	146:f64d43ff0c18	5832	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5833	//! @brief Set the BITER field to a new value.
mbed_official	146:f64d43ff0c18	5834	#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) \| BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
mbed_official	146:f64d43ff0c18	5835	#endif
mbed_official	146:f64d43ff0c18	5836	//@}
mbed_official	146:f64d43ff0c18	5837
mbed_official	146:f64d43ff0c18	5838	/*!
mbed_official	146:f64d43ff0c18	5839	* @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
mbed_official	146:f64d43ff0c18	5840	*
mbed_official	146:f64d43ff0c18	5841	* If channel-to-channel linking is enabled (ELINK = 1), then after the minor
mbed_official	146:f64d43ff0c18	5842	* loop is exhausted, the eDMA engine initiates a channel service request at the
mbed_official	146:f64d43ff0c18	5843	* channel defined by these four bits by setting that channel's TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	5844	* bit. When the software loads the TCD, this field must be set equal to the
mbed_official	146:f64d43ff0c18	5845	* corresponding CITER field; otherwise, a configuration error is reported. As the major
mbed_official	146:f64d43ff0c18	5846	* iteration count is exhausted, the contents of this field is reloaded into the
mbed_official	146:f64d43ff0c18	5847	* CITER field.
mbed_official	146:f64d43ff0c18	5848	*/
mbed_official	146:f64d43ff0c18	5849	//@{
mbed_official	146:f64d43ff0c18	5850	#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5851	#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5852	#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5853
mbed_official	146:f64d43ff0c18	5854	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5855	//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field.
mbed_official	146:f64d43ff0c18	5856	#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
mbed_official	146:f64d43ff0c18	5857	#endif
mbed_official	146:f64d43ff0c18	5858
mbed_official	146:f64d43ff0c18	5859	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH.
mbed_official	146:f64d43ff0c18	5860	#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
mbed_official	146:f64d43ff0c18	5861
mbed_official	146:f64d43ff0c18	5862	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5863	//! @brief Set the LINKCH field to a new value.
mbed_official	146:f64d43ff0c18	5864	#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) \| BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
mbed_official	146:f64d43ff0c18	5865	#endif
mbed_official	146:f64d43ff0c18	5866	//@}
mbed_official	146:f64d43ff0c18	5867
mbed_official	146:f64d43ff0c18	5868	/*!
mbed_official	146:f64d43ff0c18	5869	* @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
mbed_official	146:f64d43ff0c18	5870	*
mbed_official	146:f64d43ff0c18	5871	* As the channel completes the minor loop, this flag enables the linking to
mbed_official	146:f64d43ff0c18	5872	* another channel, defined by BITER[LINKCH]. The link target channel initiates a
mbed_official	146:f64d43ff0c18	5873	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official	146:f64d43ff0c18	5874	* bit of the specified channel. If channel linking disables, the BITER value
mbed_official	146:f64d43ff0c18	5875	* extends to 15 bits in place of a link channel number. If the major loop is
mbed_official	146:f64d43ff0c18	5876	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
mbed_official	146:f64d43ff0c18	5877	* linking. When the software loads the TCD, this field must be set equal to the
mbed_official	146:f64d43ff0c18	5878	* corresponding CITER field; otherwise, a configuration error is reported. As the
mbed_official	146:f64d43ff0c18	5879	* major iteration count is exhausted, the contents of this field is reloaded into
mbed_official	146:f64d43ff0c18	5880	* the CITER field.
mbed_official	146:f64d43ff0c18	5881	*
mbed_official	146:f64d43ff0c18	5882	* Values:
mbed_official	146:f64d43ff0c18	5883	* - 0 - The channel-to-channel linking is disabled
mbed_official	146:f64d43ff0c18	5884	* - 1 - The channel-to-channel linking is enabled
mbed_official	146:f64d43ff0c18	5885	*/
mbed_official	146:f64d43ff0c18	5886	//@{
mbed_official	146:f64d43ff0c18	5887	#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5888	#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5889	#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5890
mbed_official	146:f64d43ff0c18	5891	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5892	//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field.
mbed_official	146:f64d43ff0c18	5893	#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
mbed_official	146:f64d43ff0c18	5894	#endif
mbed_official	146:f64d43ff0c18	5895
mbed_official	146:f64d43ff0c18	5896	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK.
mbed_official	146:f64d43ff0c18	5897	#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
mbed_official	146:f64d43ff0c18	5898
mbed_official	146:f64d43ff0c18	5899	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5900	//! @brief Set the ELINK field to a new value.
mbed_official	146:f64d43ff0c18	5901	#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
mbed_official	146:f64d43ff0c18	5902	#endif
mbed_official	146:f64d43ff0c18	5903	//@}
mbed_official	146:f64d43ff0c18	5904
mbed_official	146:f64d43ff0c18	5905	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5906	// hw_dma_t - module struct
mbed_official	146:f64d43ff0c18	5907	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5908	/*!
mbed_official	146:f64d43ff0c18	5909	* @brief All DMA module registers.
mbed_official	146:f64d43ff0c18	5910	*/
mbed_official	146:f64d43ff0c18	5911	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5912	#pragma pack(1)
mbed_official	146:f64d43ff0c18	5913	typedef struct _hw_dma
mbed_official	146:f64d43ff0c18	5914	{
mbed_official	146:f64d43ff0c18	5915	__IO hw_dma_cr_t CR; //!< [0x0] Control Register
mbed_official	146:f64d43ff0c18	5916	__I hw_dma_es_t ES; //!< [0x4] Error Status Register
mbed_official	146:f64d43ff0c18	5917	uint8_t _reserved0[4];
mbed_official	146:f64d43ff0c18	5918	__IO hw_dma_erq_t ERQ; //!< [0xC] Enable Request Register
mbed_official	146:f64d43ff0c18	5919	uint8_t _reserved1[4];
mbed_official	146:f64d43ff0c18	5920	__IO hw_dma_eei_t EEI; //!< [0x14] Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	5921	__O hw_dma_ceei_t CEEI; //!< [0x18] Clear Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	5922	__O hw_dma_seei_t SEEI; //!< [0x19] Set Enable Error Interrupt Register
mbed_official	146:f64d43ff0c18	5923	__O hw_dma_cerq_t CERQ; //!< [0x1A] Clear Enable Request Register
mbed_official	146:f64d43ff0c18	5924	__O hw_dma_serq_t SERQ; //!< [0x1B] Set Enable Request Register
mbed_official	146:f64d43ff0c18	5925	__O hw_dma_cdne_t CDNE; //!< [0x1C] Clear DONE Status Bit Register
mbed_official	146:f64d43ff0c18	5926	__O hw_dma_ssrt_t SSRT; //!< [0x1D] Set START Bit Register
mbed_official	146:f64d43ff0c18	5927	__O hw_dma_cerr_t CERR; //!< [0x1E] Clear Error Register
mbed_official	146:f64d43ff0c18	5928	__O hw_dma_cint_t CINT; //!< [0x1F] Clear Interrupt Request Register
mbed_official	146:f64d43ff0c18	5929	uint8_t _reserved2[4];
mbed_official	146:f64d43ff0c18	5930	__IO hw_dma_int_t INT; //!< [0x24] Interrupt Request Register
mbed_official	146:f64d43ff0c18	5931	uint8_t _reserved3[4];
mbed_official	146:f64d43ff0c18	5932	__IO hw_dma_err_t ERR; //!< [0x2C] Error Register
mbed_official	146:f64d43ff0c18	5933	uint8_t _reserved4[4];
mbed_official	146:f64d43ff0c18	5934	__I hw_dma_hrs_t HRS; //!< [0x34] Hardware Request Status Register
mbed_official	146:f64d43ff0c18	5935	uint8_t _reserved5[200];
mbed_official	146:f64d43ff0c18	5936	__IO hw_dma_dchprin_t DCHPRIn[16]; //!< [0x100] Channel n Priority Register
mbed_official	146:f64d43ff0c18	5937	uint8_t _reserved6[3824];
mbed_official	146:f64d43ff0c18	5938	struct {
mbed_official	146:f64d43ff0c18	5939	__IO hw_dma_tcdn_saddr_t TCDn_SADDR; //!< [0x1000] TCD Source Address
mbed_official	146:f64d43ff0c18	5940	__IO hw_dma_tcdn_soff_t TCDn_SOFF; //!< [0x1004] TCD Signed Source Address Offset
mbed_official	146:f64d43ff0c18	5941	__IO hw_dma_tcdn_attr_t TCDn_ATTR; //!< [0x1006] TCD Transfer Attributes
mbed_official	146:f64d43ff0c18	5942	union {
mbed_official	146:f64d43ff0c18	5943	__IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; //!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled)
mbed_official	146:f64d43ff0c18	5944	__IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
mbed_official	146:f64d43ff0c18	5945	__IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
mbed_official	146:f64d43ff0c18	5946	};
mbed_official	146:f64d43ff0c18	5947	__IO hw_dma_tcdn_slast_t TCDn_SLAST; //!< [0x100C] TCD Last Source Address Adjustment
mbed_official	146:f64d43ff0c18	5948	__IO hw_dma_tcdn_daddr_t TCDn_DADDR; //!< [0x1010] TCD Destination Address
mbed_official	146:f64d43ff0c18	5949	__IO hw_dma_tcdn_doff_t TCDn_DOFF; //!< [0x1014] TCD Signed Destination Address Offset
mbed_official	146:f64d43ff0c18	5950	union {
mbed_official	146:f64d43ff0c18	5951	__IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official	146:f64d43ff0c18	5952	__IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official	146:f64d43ff0c18	5953	};
mbed_official	146:f64d43ff0c18	5954	__IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; //!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address
mbed_official	146:f64d43ff0c18	5955	__IO hw_dma_tcdn_csr_t TCDn_CSR; //!< [0x101C] TCD Control and Status
mbed_official	146:f64d43ff0c18	5956	union {
mbed_official	146:f64d43ff0c18	5957	__IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official	146:f64d43ff0c18	5958	__IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official	146:f64d43ff0c18	5959	};
mbed_official	146:f64d43ff0c18	5960	} TCD[16];
mbed_official	146:f64d43ff0c18	5961	} hw_dma_t;
mbed_official	146:f64d43ff0c18	5962	#pragma pack()
mbed_official	146:f64d43ff0c18	5963
mbed_official	146:f64d43ff0c18	5964	//! @brief Macro to access all DMA registers.
mbed_official	146:f64d43ff0c18	5965	//! @param x DMA instance number.
mbed_official	146:f64d43ff0c18	5966	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	146:f64d43ff0c18	5967	//! use the '&' operator, like <code>&HW_DMA(0)</code>.
mbed_official	146:f64d43ff0c18	5968	#define HW_DMA(x) ((hw_dma_t ) REGS_DMA_BASE(x))
mbed_official	146:f64d43ff0c18	5969	#endif
mbed_official	146:f64d43ff0c18	5970
mbed_official	146:f64d43ff0c18	5971	#endif // __HW_DMA_REGISTERS_H__
mbed_official	146:f64d43ff0c18	5972	// v22/130726/0.9
mbed_official	146:f64d43ff0c18	5973	// EOF

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dma.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

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