mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_aips.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_aips.h@146:f64d43ff0c18
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_AIPS_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_AIPS_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 AIPS |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * AIPS-Lite Bridge |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_AIPS_MPRA - Master Privilege Register A |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_AIPS_PACRA - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_AIPS_PACRB - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_AIPS_PACRC - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_AIPS_PACRD - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_AIPS_PACRE - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_AIPS_PACRF - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_AIPS_PACRG - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_AIPS_PACRH - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_AIPS_PACRI - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_AIPS_PACRJ - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_AIPS_PACRK - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 44 | * - HW_AIPS_PACRL - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 45 | * - HW_AIPS_PACRM - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 46 | * - HW_AIPS_PACRN - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 47 | * - HW_AIPS_PACRO - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 48 | * - HW_AIPS_PACRP - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 49 | * - HW_AIPS_PACRU - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 50 | * |
mbed_official | 146:f64d43ff0c18 | 51 | * - hw_aips_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 52 | */ |
mbed_official | 146:f64d43ff0c18 | 53 | |
mbed_official | 146:f64d43ff0c18 | 54 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 55 | //@{ |
mbed_official | 146:f64d43ff0c18 | 56 | #ifndef REGS_AIPS_BASE |
mbed_official | 146:f64d43ff0c18 | 57 | #define HW_AIPS_INSTANCE_COUNT (2U) //!< Number of instances of the AIPS module. |
mbed_official | 146:f64d43ff0c18 | 58 | #define HW_AIPS0 (0U) //!< Instance number for AIPS0. |
mbed_official | 146:f64d43ff0c18 | 59 | #define HW_AIPS1 (1U) //!< Instance number for AIPS1. |
mbed_official | 146:f64d43ff0c18 | 60 | #define REGS_AIPS0_BASE (0x40000000U) //!< Base address for AIPS0. |
mbed_official | 146:f64d43ff0c18 | 61 | #define REGS_AIPS1_BASE (0x40080000U) //!< Base address for AIPS1. |
mbed_official | 146:f64d43ff0c18 | 62 | |
mbed_official | 146:f64d43ff0c18 | 63 | //! @brief Table of base addresses for AIPS instances. |
mbed_official | 146:f64d43ff0c18 | 64 | static const uint32_t __g_regs_AIPS_base_addresses[] = { |
mbed_official | 146:f64d43ff0c18 | 65 | REGS_AIPS0_BASE, |
mbed_official | 146:f64d43ff0c18 | 66 | REGS_AIPS1_BASE, |
mbed_official | 146:f64d43ff0c18 | 67 | }; |
mbed_official | 146:f64d43ff0c18 | 68 | |
mbed_official | 146:f64d43ff0c18 | 69 | //! @brief Get the base address of AIPS by instance number. |
mbed_official | 146:f64d43ff0c18 | 70 | //! @param x AIPS instance number, from 0 through 1. |
mbed_official | 146:f64d43ff0c18 | 71 | #define REGS_AIPS_BASE(x) (__g_regs_AIPS_base_addresses[(x)]) |
mbed_official | 146:f64d43ff0c18 | 72 | |
mbed_official | 146:f64d43ff0c18 | 73 | //! @brief Get the instance number given a base address. |
mbed_official | 146:f64d43ff0c18 | 74 | //! @param b Base address for an instance of AIPS. |
mbed_official | 146:f64d43ff0c18 | 75 | #define REGS_AIPS_INSTANCE(b) ((b) == REGS_AIPS0_BASE ? HW_AIPS0 : (b) == REGS_AIPS1_BASE ? HW_AIPS1 : 0) |
mbed_official | 146:f64d43ff0c18 | 76 | #endif |
mbed_official | 146:f64d43ff0c18 | 77 | //@} |
mbed_official | 146:f64d43ff0c18 | 78 | |
mbed_official | 146:f64d43ff0c18 | 79 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 80 | // HW_AIPS_MPRA - Master Privilege Register A |
mbed_official | 146:f64d43ff0c18 | 81 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 82 | |
mbed_official | 146:f64d43ff0c18 | 83 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 84 | /*! |
mbed_official | 146:f64d43ff0c18 | 85 | * @brief HW_AIPS_MPRA - Master Privilege Register A (RW) |
mbed_official | 146:f64d43ff0c18 | 86 | * |
mbed_official | 146:f64d43ff0c18 | 87 | * Reset value: 0x77700000U |
mbed_official | 146:f64d43ff0c18 | 88 | * |
mbed_official | 146:f64d43ff0c18 | 89 | * The MPRA specifies identical 4-bit fields defining the access-privilege level |
mbed_official | 146:f64d43ff0c18 | 90 | * associated with a bus master to various peripherals on the chip. The register |
mbed_official | 146:f64d43ff0c18 | 91 | * provides one field per bus master. At reset, the default value loaded into |
mbed_official | 146:f64d43ff0c18 | 92 | * the MPRA fields is chip-specific. See the chip configuration details for the |
mbed_official | 146:f64d43ff0c18 | 93 | * value of a particular device. A register field that maps to an unimplemented |
mbed_official | 146:f64d43ff0c18 | 94 | * master or peripheral behaves as read-only-zero. Each master is assigned a logical |
mbed_official | 146:f64d43ff0c18 | 95 | * ID from 0 to 15. See the master logical ID assignment table in the |
mbed_official | 146:f64d43ff0c18 | 96 | * chip-specific AIPS information. |
mbed_official | 146:f64d43ff0c18 | 97 | */ |
mbed_official | 146:f64d43ff0c18 | 98 | typedef union _hw_aips_mpra |
mbed_official | 146:f64d43ff0c18 | 99 | { |
mbed_official | 146:f64d43ff0c18 | 100 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 101 | struct _hw_aips_mpra_bitfields |
mbed_official | 146:f64d43ff0c18 | 102 | { |
mbed_official | 146:f64d43ff0c18 | 103 | uint32_t RESERVED0 : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 104 | uint32_t MPL5 : 1; //!< [8] Master 5 Privilege Level |
mbed_official | 146:f64d43ff0c18 | 105 | uint32_t MTW5 : 1; //!< [9] Master 5 Trusted For Writes |
mbed_official | 146:f64d43ff0c18 | 106 | uint32_t MTR5 : 1; //!< [10] Master 5 Trusted For Read |
mbed_official | 146:f64d43ff0c18 | 107 | uint32_t RESERVED1 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 108 | uint32_t MPL4 : 1; //!< [12] Master 4 Privilege Level |
mbed_official | 146:f64d43ff0c18 | 109 | uint32_t MTW4 : 1; //!< [13] Master 4 Trusted For Writes |
mbed_official | 146:f64d43ff0c18 | 110 | uint32_t MTR4 : 1; //!< [14] Master 4 Trusted For Read |
mbed_official | 146:f64d43ff0c18 | 111 | uint32_t RESERVED2 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 112 | uint32_t MPL3 : 1; //!< [16] Master 3 Privilege Level |
mbed_official | 146:f64d43ff0c18 | 113 | uint32_t MTW3 : 1; //!< [17] Master 3 Trusted For Writes |
mbed_official | 146:f64d43ff0c18 | 114 | uint32_t MTR3 : 1; //!< [18] Master 3 Trusted For Read |
mbed_official | 146:f64d43ff0c18 | 115 | uint32_t RESERVED3 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 116 | uint32_t MPL2 : 1; //!< [20] Master 2 Privilege Level |
mbed_official | 146:f64d43ff0c18 | 117 | uint32_t MTW2 : 1; //!< [21] Master 2 Trusted For Writes |
mbed_official | 146:f64d43ff0c18 | 118 | uint32_t MTR2 : 1; //!< [22] Master 2 Trusted For Read |
mbed_official | 146:f64d43ff0c18 | 119 | uint32_t RESERVED4 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 120 | uint32_t MPL1 : 1; //!< [24] Master 1 Privilege Level |
mbed_official | 146:f64d43ff0c18 | 121 | uint32_t MTW1 : 1; //!< [25] Master 1 Trusted for Writes |
mbed_official | 146:f64d43ff0c18 | 122 | uint32_t MTR1 : 1; //!< [26] Master 1 Trusted for Read |
mbed_official | 146:f64d43ff0c18 | 123 | uint32_t RESERVED5 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 124 | uint32_t MPL0 : 1; //!< [28] Master 0 Privilege Level |
mbed_official | 146:f64d43ff0c18 | 125 | uint32_t MTW0 : 1; //!< [29] Master 0 Trusted For Writes |
mbed_official | 146:f64d43ff0c18 | 126 | uint32_t MTR0 : 1; //!< [30] Master 0 Trusted For Read |
mbed_official | 146:f64d43ff0c18 | 127 | uint32_t RESERVED6 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 128 | } B; |
mbed_official | 146:f64d43ff0c18 | 129 | } hw_aips_mpra_t; |
mbed_official | 146:f64d43ff0c18 | 130 | #endif |
mbed_official | 146:f64d43ff0c18 | 131 | |
mbed_official | 146:f64d43ff0c18 | 132 | /*! |
mbed_official | 146:f64d43ff0c18 | 133 | * @name Constants and macros for entire AIPS_MPRA register |
mbed_official | 146:f64d43ff0c18 | 134 | */ |
mbed_official | 146:f64d43ff0c18 | 135 | //@{ |
mbed_official | 146:f64d43ff0c18 | 136 | #define HW_AIPS_MPRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 137 | |
mbed_official | 146:f64d43ff0c18 | 138 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 139 | #define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 140 | #define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U) |
mbed_official | 146:f64d43ff0c18 | 141 | #define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 142 | #define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 143 | #define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 144 | #define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 145 | #endif |
mbed_official | 146:f64d43ff0c18 | 146 | //@} |
mbed_official | 146:f64d43ff0c18 | 147 | |
mbed_official | 146:f64d43ff0c18 | 148 | /* |
mbed_official | 146:f64d43ff0c18 | 149 | * Constants & macros for individual AIPS_MPRA bitfields |
mbed_official | 146:f64d43ff0c18 | 150 | */ |
mbed_official | 146:f64d43ff0c18 | 151 | |
mbed_official | 146:f64d43ff0c18 | 152 | /*! |
mbed_official | 146:f64d43ff0c18 | 153 | * @name Register AIPS_MPRA, field MPL5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 154 | * |
mbed_official | 146:f64d43ff0c18 | 155 | * Specifies how the privilege level of the master is determined. |
mbed_official | 146:f64d43ff0c18 | 156 | * |
mbed_official | 146:f64d43ff0c18 | 157 | * Values: |
mbed_official | 146:f64d43ff0c18 | 158 | * - 0 - Accesses from this master are forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 159 | * - 1 - Accesses from this master are not forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 160 | */ |
mbed_official | 146:f64d43ff0c18 | 161 | //@{ |
mbed_official | 146:f64d43ff0c18 | 162 | #define BP_AIPS_MPRA_MPL5 (8U) //!< Bit position for AIPS_MPRA_MPL5. |
mbed_official | 146:f64d43ff0c18 | 163 | #define BM_AIPS_MPRA_MPL5 (0x00000100U) //!< Bit mask for AIPS_MPRA_MPL5. |
mbed_official | 146:f64d43ff0c18 | 164 | #define BS_AIPS_MPRA_MPL5 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL5. |
mbed_official | 146:f64d43ff0c18 | 165 | |
mbed_official | 146:f64d43ff0c18 | 166 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 167 | //! @brief Read current value of the AIPS_MPRA_MPL5 field. |
mbed_official | 146:f64d43ff0c18 | 168 | #define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5)) |
mbed_official | 146:f64d43ff0c18 | 169 | #endif |
mbed_official | 146:f64d43ff0c18 | 170 | |
mbed_official | 146:f64d43ff0c18 | 171 | //! @brief Format value for bitfield AIPS_MPRA_MPL5. |
mbed_official | 146:f64d43ff0c18 | 172 | #define BF_AIPS_MPRA_MPL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL5), uint32_t) & BM_AIPS_MPRA_MPL5) |
mbed_official | 146:f64d43ff0c18 | 173 | |
mbed_official | 146:f64d43ff0c18 | 174 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 175 | //! @brief Set the MPL5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 176 | #define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 177 | #endif |
mbed_official | 146:f64d43ff0c18 | 178 | //@} |
mbed_official | 146:f64d43ff0c18 | 179 | |
mbed_official | 146:f64d43ff0c18 | 180 | /*! |
mbed_official | 146:f64d43ff0c18 | 181 | * @name Register AIPS_MPRA, field MTW5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 182 | * |
mbed_official | 146:f64d43ff0c18 | 183 | * Determines whether the master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 184 | * |
mbed_official | 146:f64d43ff0c18 | 185 | * Values: |
mbed_official | 146:f64d43ff0c18 | 186 | * - 0 - This master is not trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 187 | * - 1 - This master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 188 | */ |
mbed_official | 146:f64d43ff0c18 | 189 | //@{ |
mbed_official | 146:f64d43ff0c18 | 190 | #define BP_AIPS_MPRA_MTW5 (9U) //!< Bit position for AIPS_MPRA_MTW5. |
mbed_official | 146:f64d43ff0c18 | 191 | #define BM_AIPS_MPRA_MTW5 (0x00000200U) //!< Bit mask for AIPS_MPRA_MTW5. |
mbed_official | 146:f64d43ff0c18 | 192 | #define BS_AIPS_MPRA_MTW5 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW5. |
mbed_official | 146:f64d43ff0c18 | 193 | |
mbed_official | 146:f64d43ff0c18 | 194 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 195 | //! @brief Read current value of the AIPS_MPRA_MTW5 field. |
mbed_official | 146:f64d43ff0c18 | 196 | #define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5)) |
mbed_official | 146:f64d43ff0c18 | 197 | #endif |
mbed_official | 146:f64d43ff0c18 | 198 | |
mbed_official | 146:f64d43ff0c18 | 199 | //! @brief Format value for bitfield AIPS_MPRA_MTW5. |
mbed_official | 146:f64d43ff0c18 | 200 | #define BF_AIPS_MPRA_MTW5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW5), uint32_t) & BM_AIPS_MPRA_MTW5) |
mbed_official | 146:f64d43ff0c18 | 201 | |
mbed_official | 146:f64d43ff0c18 | 202 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 203 | //! @brief Set the MTW5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 204 | #define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 205 | #endif |
mbed_official | 146:f64d43ff0c18 | 206 | //@} |
mbed_official | 146:f64d43ff0c18 | 207 | |
mbed_official | 146:f64d43ff0c18 | 208 | /*! |
mbed_official | 146:f64d43ff0c18 | 209 | * @name Register AIPS_MPRA, field MTR5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 210 | * |
mbed_official | 146:f64d43ff0c18 | 211 | * Determines whether the master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 212 | * |
mbed_official | 146:f64d43ff0c18 | 213 | * Values: |
mbed_official | 146:f64d43ff0c18 | 214 | * - 0 - This master is not trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 215 | * - 1 - This master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 216 | */ |
mbed_official | 146:f64d43ff0c18 | 217 | //@{ |
mbed_official | 146:f64d43ff0c18 | 218 | #define BP_AIPS_MPRA_MTR5 (10U) //!< Bit position for AIPS_MPRA_MTR5. |
mbed_official | 146:f64d43ff0c18 | 219 | #define BM_AIPS_MPRA_MTR5 (0x00000400U) //!< Bit mask for AIPS_MPRA_MTR5. |
mbed_official | 146:f64d43ff0c18 | 220 | #define BS_AIPS_MPRA_MTR5 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR5. |
mbed_official | 146:f64d43ff0c18 | 221 | |
mbed_official | 146:f64d43ff0c18 | 222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 223 | //! @brief Read current value of the AIPS_MPRA_MTR5 field. |
mbed_official | 146:f64d43ff0c18 | 224 | #define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5)) |
mbed_official | 146:f64d43ff0c18 | 225 | #endif |
mbed_official | 146:f64d43ff0c18 | 226 | |
mbed_official | 146:f64d43ff0c18 | 227 | //! @brief Format value for bitfield AIPS_MPRA_MTR5. |
mbed_official | 146:f64d43ff0c18 | 228 | #define BF_AIPS_MPRA_MTR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR5), uint32_t) & BM_AIPS_MPRA_MTR5) |
mbed_official | 146:f64d43ff0c18 | 229 | |
mbed_official | 146:f64d43ff0c18 | 230 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 231 | //! @brief Set the MTR5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 232 | #define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 233 | #endif |
mbed_official | 146:f64d43ff0c18 | 234 | //@} |
mbed_official | 146:f64d43ff0c18 | 235 | |
mbed_official | 146:f64d43ff0c18 | 236 | /*! |
mbed_official | 146:f64d43ff0c18 | 237 | * @name Register AIPS_MPRA, field MPL4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 238 | * |
mbed_official | 146:f64d43ff0c18 | 239 | * Specifies how the privilege level of the master is determined. |
mbed_official | 146:f64d43ff0c18 | 240 | * |
mbed_official | 146:f64d43ff0c18 | 241 | * Values: |
mbed_official | 146:f64d43ff0c18 | 242 | * - 0 - Accesses from this master are forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 243 | * - 1 - Accesses from this master are not forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 244 | */ |
mbed_official | 146:f64d43ff0c18 | 245 | //@{ |
mbed_official | 146:f64d43ff0c18 | 246 | #define BP_AIPS_MPRA_MPL4 (12U) //!< Bit position for AIPS_MPRA_MPL4. |
mbed_official | 146:f64d43ff0c18 | 247 | #define BM_AIPS_MPRA_MPL4 (0x00001000U) //!< Bit mask for AIPS_MPRA_MPL4. |
mbed_official | 146:f64d43ff0c18 | 248 | #define BS_AIPS_MPRA_MPL4 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL4. |
mbed_official | 146:f64d43ff0c18 | 249 | |
mbed_official | 146:f64d43ff0c18 | 250 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 251 | //! @brief Read current value of the AIPS_MPRA_MPL4 field. |
mbed_official | 146:f64d43ff0c18 | 252 | #define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4)) |
mbed_official | 146:f64d43ff0c18 | 253 | #endif |
mbed_official | 146:f64d43ff0c18 | 254 | |
mbed_official | 146:f64d43ff0c18 | 255 | //! @brief Format value for bitfield AIPS_MPRA_MPL4. |
mbed_official | 146:f64d43ff0c18 | 256 | #define BF_AIPS_MPRA_MPL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL4), uint32_t) & BM_AIPS_MPRA_MPL4) |
mbed_official | 146:f64d43ff0c18 | 257 | |
mbed_official | 146:f64d43ff0c18 | 258 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 259 | //! @brief Set the MPL4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 260 | #define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 261 | #endif |
mbed_official | 146:f64d43ff0c18 | 262 | //@} |
mbed_official | 146:f64d43ff0c18 | 263 | |
mbed_official | 146:f64d43ff0c18 | 264 | /*! |
mbed_official | 146:f64d43ff0c18 | 265 | * @name Register AIPS_MPRA, field MTW4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 266 | * |
mbed_official | 146:f64d43ff0c18 | 267 | * Determines whether the master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 268 | * |
mbed_official | 146:f64d43ff0c18 | 269 | * Values: |
mbed_official | 146:f64d43ff0c18 | 270 | * - 0 - This master is not trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 271 | * - 1 - This master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 272 | */ |
mbed_official | 146:f64d43ff0c18 | 273 | //@{ |
mbed_official | 146:f64d43ff0c18 | 274 | #define BP_AIPS_MPRA_MTW4 (13U) //!< Bit position for AIPS_MPRA_MTW4. |
mbed_official | 146:f64d43ff0c18 | 275 | #define BM_AIPS_MPRA_MTW4 (0x00002000U) //!< Bit mask for AIPS_MPRA_MTW4. |
mbed_official | 146:f64d43ff0c18 | 276 | #define BS_AIPS_MPRA_MTW4 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW4. |
mbed_official | 146:f64d43ff0c18 | 277 | |
mbed_official | 146:f64d43ff0c18 | 278 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 279 | //! @brief Read current value of the AIPS_MPRA_MTW4 field. |
mbed_official | 146:f64d43ff0c18 | 280 | #define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4)) |
mbed_official | 146:f64d43ff0c18 | 281 | #endif |
mbed_official | 146:f64d43ff0c18 | 282 | |
mbed_official | 146:f64d43ff0c18 | 283 | //! @brief Format value for bitfield AIPS_MPRA_MTW4. |
mbed_official | 146:f64d43ff0c18 | 284 | #define BF_AIPS_MPRA_MTW4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW4), uint32_t) & BM_AIPS_MPRA_MTW4) |
mbed_official | 146:f64d43ff0c18 | 285 | |
mbed_official | 146:f64d43ff0c18 | 286 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 287 | //! @brief Set the MTW4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 288 | #define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 289 | #endif |
mbed_official | 146:f64d43ff0c18 | 290 | //@} |
mbed_official | 146:f64d43ff0c18 | 291 | |
mbed_official | 146:f64d43ff0c18 | 292 | /*! |
mbed_official | 146:f64d43ff0c18 | 293 | * @name Register AIPS_MPRA, field MTR4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 294 | * |
mbed_official | 146:f64d43ff0c18 | 295 | * Determines whether the master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 296 | * |
mbed_official | 146:f64d43ff0c18 | 297 | * Values: |
mbed_official | 146:f64d43ff0c18 | 298 | * - 0 - This master is not trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 299 | * - 1 - This master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 300 | */ |
mbed_official | 146:f64d43ff0c18 | 301 | //@{ |
mbed_official | 146:f64d43ff0c18 | 302 | #define BP_AIPS_MPRA_MTR4 (14U) //!< Bit position for AIPS_MPRA_MTR4. |
mbed_official | 146:f64d43ff0c18 | 303 | #define BM_AIPS_MPRA_MTR4 (0x00004000U) //!< Bit mask for AIPS_MPRA_MTR4. |
mbed_official | 146:f64d43ff0c18 | 304 | #define BS_AIPS_MPRA_MTR4 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR4. |
mbed_official | 146:f64d43ff0c18 | 305 | |
mbed_official | 146:f64d43ff0c18 | 306 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 307 | //! @brief Read current value of the AIPS_MPRA_MTR4 field. |
mbed_official | 146:f64d43ff0c18 | 308 | #define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4)) |
mbed_official | 146:f64d43ff0c18 | 309 | #endif |
mbed_official | 146:f64d43ff0c18 | 310 | |
mbed_official | 146:f64d43ff0c18 | 311 | //! @brief Format value for bitfield AIPS_MPRA_MTR4. |
mbed_official | 146:f64d43ff0c18 | 312 | #define BF_AIPS_MPRA_MTR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR4), uint32_t) & BM_AIPS_MPRA_MTR4) |
mbed_official | 146:f64d43ff0c18 | 313 | |
mbed_official | 146:f64d43ff0c18 | 314 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 315 | //! @brief Set the MTR4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 316 | #define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 317 | #endif |
mbed_official | 146:f64d43ff0c18 | 318 | //@} |
mbed_official | 146:f64d43ff0c18 | 319 | |
mbed_official | 146:f64d43ff0c18 | 320 | /*! |
mbed_official | 146:f64d43ff0c18 | 321 | * @name Register AIPS_MPRA, field MPL3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 322 | * |
mbed_official | 146:f64d43ff0c18 | 323 | * Specifies how the privilege level of the master is determined. |
mbed_official | 146:f64d43ff0c18 | 324 | * |
mbed_official | 146:f64d43ff0c18 | 325 | * Values: |
mbed_official | 146:f64d43ff0c18 | 326 | * - 0 - Accesses from this master are forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 327 | * - 1 - Accesses from this master are not forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 328 | */ |
mbed_official | 146:f64d43ff0c18 | 329 | //@{ |
mbed_official | 146:f64d43ff0c18 | 330 | #define BP_AIPS_MPRA_MPL3 (16U) //!< Bit position for AIPS_MPRA_MPL3. |
mbed_official | 146:f64d43ff0c18 | 331 | #define BM_AIPS_MPRA_MPL3 (0x00010000U) //!< Bit mask for AIPS_MPRA_MPL3. |
mbed_official | 146:f64d43ff0c18 | 332 | #define BS_AIPS_MPRA_MPL3 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL3. |
mbed_official | 146:f64d43ff0c18 | 333 | |
mbed_official | 146:f64d43ff0c18 | 334 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 335 | //! @brief Read current value of the AIPS_MPRA_MPL3 field. |
mbed_official | 146:f64d43ff0c18 | 336 | #define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3)) |
mbed_official | 146:f64d43ff0c18 | 337 | #endif |
mbed_official | 146:f64d43ff0c18 | 338 | |
mbed_official | 146:f64d43ff0c18 | 339 | //! @brief Format value for bitfield AIPS_MPRA_MPL3. |
mbed_official | 146:f64d43ff0c18 | 340 | #define BF_AIPS_MPRA_MPL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL3), uint32_t) & BM_AIPS_MPRA_MPL3) |
mbed_official | 146:f64d43ff0c18 | 341 | |
mbed_official | 146:f64d43ff0c18 | 342 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 343 | //! @brief Set the MPL3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 344 | #define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 345 | #endif |
mbed_official | 146:f64d43ff0c18 | 346 | //@} |
mbed_official | 146:f64d43ff0c18 | 347 | |
mbed_official | 146:f64d43ff0c18 | 348 | /*! |
mbed_official | 146:f64d43ff0c18 | 349 | * @name Register AIPS_MPRA, field MTW3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 350 | * |
mbed_official | 146:f64d43ff0c18 | 351 | * Determines whether the master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 352 | * |
mbed_official | 146:f64d43ff0c18 | 353 | * Values: |
mbed_official | 146:f64d43ff0c18 | 354 | * - 0 - This master is not trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 355 | * - 1 - This master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 356 | */ |
mbed_official | 146:f64d43ff0c18 | 357 | //@{ |
mbed_official | 146:f64d43ff0c18 | 358 | #define BP_AIPS_MPRA_MTW3 (17U) //!< Bit position for AIPS_MPRA_MTW3. |
mbed_official | 146:f64d43ff0c18 | 359 | #define BM_AIPS_MPRA_MTW3 (0x00020000U) //!< Bit mask for AIPS_MPRA_MTW3. |
mbed_official | 146:f64d43ff0c18 | 360 | #define BS_AIPS_MPRA_MTW3 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW3. |
mbed_official | 146:f64d43ff0c18 | 361 | |
mbed_official | 146:f64d43ff0c18 | 362 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 363 | //! @brief Read current value of the AIPS_MPRA_MTW3 field. |
mbed_official | 146:f64d43ff0c18 | 364 | #define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3)) |
mbed_official | 146:f64d43ff0c18 | 365 | #endif |
mbed_official | 146:f64d43ff0c18 | 366 | |
mbed_official | 146:f64d43ff0c18 | 367 | //! @brief Format value for bitfield AIPS_MPRA_MTW3. |
mbed_official | 146:f64d43ff0c18 | 368 | #define BF_AIPS_MPRA_MTW3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW3), uint32_t) & BM_AIPS_MPRA_MTW3) |
mbed_official | 146:f64d43ff0c18 | 369 | |
mbed_official | 146:f64d43ff0c18 | 370 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 371 | //! @brief Set the MTW3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 372 | #define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 373 | #endif |
mbed_official | 146:f64d43ff0c18 | 374 | //@} |
mbed_official | 146:f64d43ff0c18 | 375 | |
mbed_official | 146:f64d43ff0c18 | 376 | /*! |
mbed_official | 146:f64d43ff0c18 | 377 | * @name Register AIPS_MPRA, field MTR3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 378 | * |
mbed_official | 146:f64d43ff0c18 | 379 | * Determines whether the master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 380 | * |
mbed_official | 146:f64d43ff0c18 | 381 | * Values: |
mbed_official | 146:f64d43ff0c18 | 382 | * - 0 - This master is not trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 383 | * - 1 - This master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 384 | */ |
mbed_official | 146:f64d43ff0c18 | 385 | //@{ |
mbed_official | 146:f64d43ff0c18 | 386 | #define BP_AIPS_MPRA_MTR3 (18U) //!< Bit position for AIPS_MPRA_MTR3. |
mbed_official | 146:f64d43ff0c18 | 387 | #define BM_AIPS_MPRA_MTR3 (0x00040000U) //!< Bit mask for AIPS_MPRA_MTR3. |
mbed_official | 146:f64d43ff0c18 | 388 | #define BS_AIPS_MPRA_MTR3 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR3. |
mbed_official | 146:f64d43ff0c18 | 389 | |
mbed_official | 146:f64d43ff0c18 | 390 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 391 | //! @brief Read current value of the AIPS_MPRA_MTR3 field. |
mbed_official | 146:f64d43ff0c18 | 392 | #define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3)) |
mbed_official | 146:f64d43ff0c18 | 393 | #endif |
mbed_official | 146:f64d43ff0c18 | 394 | |
mbed_official | 146:f64d43ff0c18 | 395 | //! @brief Format value for bitfield AIPS_MPRA_MTR3. |
mbed_official | 146:f64d43ff0c18 | 396 | #define BF_AIPS_MPRA_MTR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR3), uint32_t) & BM_AIPS_MPRA_MTR3) |
mbed_official | 146:f64d43ff0c18 | 397 | |
mbed_official | 146:f64d43ff0c18 | 398 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 399 | //! @brief Set the MTR3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 400 | #define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 401 | #endif |
mbed_official | 146:f64d43ff0c18 | 402 | //@} |
mbed_official | 146:f64d43ff0c18 | 403 | |
mbed_official | 146:f64d43ff0c18 | 404 | /*! |
mbed_official | 146:f64d43ff0c18 | 405 | * @name Register AIPS_MPRA, field MPL2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 406 | * |
mbed_official | 146:f64d43ff0c18 | 407 | * Specifies how the privilege level of the master is determined. |
mbed_official | 146:f64d43ff0c18 | 408 | * |
mbed_official | 146:f64d43ff0c18 | 409 | * Values: |
mbed_official | 146:f64d43ff0c18 | 410 | * - 0 - Accesses from this master are forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 411 | * - 1 - Accesses from this master are not forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 412 | */ |
mbed_official | 146:f64d43ff0c18 | 413 | //@{ |
mbed_official | 146:f64d43ff0c18 | 414 | #define BP_AIPS_MPRA_MPL2 (20U) //!< Bit position for AIPS_MPRA_MPL2. |
mbed_official | 146:f64d43ff0c18 | 415 | #define BM_AIPS_MPRA_MPL2 (0x00100000U) //!< Bit mask for AIPS_MPRA_MPL2. |
mbed_official | 146:f64d43ff0c18 | 416 | #define BS_AIPS_MPRA_MPL2 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL2. |
mbed_official | 146:f64d43ff0c18 | 417 | |
mbed_official | 146:f64d43ff0c18 | 418 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 419 | //! @brief Read current value of the AIPS_MPRA_MPL2 field. |
mbed_official | 146:f64d43ff0c18 | 420 | #define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2)) |
mbed_official | 146:f64d43ff0c18 | 421 | #endif |
mbed_official | 146:f64d43ff0c18 | 422 | |
mbed_official | 146:f64d43ff0c18 | 423 | //! @brief Format value for bitfield AIPS_MPRA_MPL2. |
mbed_official | 146:f64d43ff0c18 | 424 | #define BF_AIPS_MPRA_MPL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL2), uint32_t) & BM_AIPS_MPRA_MPL2) |
mbed_official | 146:f64d43ff0c18 | 425 | |
mbed_official | 146:f64d43ff0c18 | 426 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 427 | //! @brief Set the MPL2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 428 | #define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 429 | #endif |
mbed_official | 146:f64d43ff0c18 | 430 | //@} |
mbed_official | 146:f64d43ff0c18 | 431 | |
mbed_official | 146:f64d43ff0c18 | 432 | /*! |
mbed_official | 146:f64d43ff0c18 | 433 | * @name Register AIPS_MPRA, field MTW2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 434 | * |
mbed_official | 146:f64d43ff0c18 | 435 | * Determines whether the master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 436 | * |
mbed_official | 146:f64d43ff0c18 | 437 | * Values: |
mbed_official | 146:f64d43ff0c18 | 438 | * - 0 - This master is not trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 439 | * - 1 - This master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 440 | */ |
mbed_official | 146:f64d43ff0c18 | 441 | //@{ |
mbed_official | 146:f64d43ff0c18 | 442 | #define BP_AIPS_MPRA_MTW2 (21U) //!< Bit position for AIPS_MPRA_MTW2. |
mbed_official | 146:f64d43ff0c18 | 443 | #define BM_AIPS_MPRA_MTW2 (0x00200000U) //!< Bit mask for AIPS_MPRA_MTW2. |
mbed_official | 146:f64d43ff0c18 | 444 | #define BS_AIPS_MPRA_MTW2 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW2. |
mbed_official | 146:f64d43ff0c18 | 445 | |
mbed_official | 146:f64d43ff0c18 | 446 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 447 | //! @brief Read current value of the AIPS_MPRA_MTW2 field. |
mbed_official | 146:f64d43ff0c18 | 448 | #define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2)) |
mbed_official | 146:f64d43ff0c18 | 449 | #endif |
mbed_official | 146:f64d43ff0c18 | 450 | |
mbed_official | 146:f64d43ff0c18 | 451 | //! @brief Format value for bitfield AIPS_MPRA_MTW2. |
mbed_official | 146:f64d43ff0c18 | 452 | #define BF_AIPS_MPRA_MTW2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW2), uint32_t) & BM_AIPS_MPRA_MTW2) |
mbed_official | 146:f64d43ff0c18 | 453 | |
mbed_official | 146:f64d43ff0c18 | 454 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 455 | //! @brief Set the MTW2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 456 | #define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 457 | #endif |
mbed_official | 146:f64d43ff0c18 | 458 | //@} |
mbed_official | 146:f64d43ff0c18 | 459 | |
mbed_official | 146:f64d43ff0c18 | 460 | /*! |
mbed_official | 146:f64d43ff0c18 | 461 | * @name Register AIPS_MPRA, field MTR2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 462 | * |
mbed_official | 146:f64d43ff0c18 | 463 | * Determines whether the master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 464 | * |
mbed_official | 146:f64d43ff0c18 | 465 | * Values: |
mbed_official | 146:f64d43ff0c18 | 466 | * - 0 - This master is not trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 467 | * - 1 - This master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 468 | */ |
mbed_official | 146:f64d43ff0c18 | 469 | //@{ |
mbed_official | 146:f64d43ff0c18 | 470 | #define BP_AIPS_MPRA_MTR2 (22U) //!< Bit position for AIPS_MPRA_MTR2. |
mbed_official | 146:f64d43ff0c18 | 471 | #define BM_AIPS_MPRA_MTR2 (0x00400000U) //!< Bit mask for AIPS_MPRA_MTR2. |
mbed_official | 146:f64d43ff0c18 | 472 | #define BS_AIPS_MPRA_MTR2 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR2. |
mbed_official | 146:f64d43ff0c18 | 473 | |
mbed_official | 146:f64d43ff0c18 | 474 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 475 | //! @brief Read current value of the AIPS_MPRA_MTR2 field. |
mbed_official | 146:f64d43ff0c18 | 476 | #define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2)) |
mbed_official | 146:f64d43ff0c18 | 477 | #endif |
mbed_official | 146:f64d43ff0c18 | 478 | |
mbed_official | 146:f64d43ff0c18 | 479 | //! @brief Format value for bitfield AIPS_MPRA_MTR2. |
mbed_official | 146:f64d43ff0c18 | 480 | #define BF_AIPS_MPRA_MTR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR2), uint32_t) & BM_AIPS_MPRA_MTR2) |
mbed_official | 146:f64d43ff0c18 | 481 | |
mbed_official | 146:f64d43ff0c18 | 482 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 483 | //! @brief Set the MTR2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 484 | #define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 485 | #endif |
mbed_official | 146:f64d43ff0c18 | 486 | //@} |
mbed_official | 146:f64d43ff0c18 | 487 | |
mbed_official | 146:f64d43ff0c18 | 488 | /*! |
mbed_official | 146:f64d43ff0c18 | 489 | * @name Register AIPS_MPRA, field MPL1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 490 | * |
mbed_official | 146:f64d43ff0c18 | 491 | * Specifies how the privilege level of the master is determined. |
mbed_official | 146:f64d43ff0c18 | 492 | * |
mbed_official | 146:f64d43ff0c18 | 493 | * Values: |
mbed_official | 146:f64d43ff0c18 | 494 | * - 0 - Accesses from this master are forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 495 | * - 1 - Accesses from this master are not forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 496 | */ |
mbed_official | 146:f64d43ff0c18 | 497 | //@{ |
mbed_official | 146:f64d43ff0c18 | 498 | #define BP_AIPS_MPRA_MPL1 (24U) //!< Bit position for AIPS_MPRA_MPL1. |
mbed_official | 146:f64d43ff0c18 | 499 | #define BM_AIPS_MPRA_MPL1 (0x01000000U) //!< Bit mask for AIPS_MPRA_MPL1. |
mbed_official | 146:f64d43ff0c18 | 500 | #define BS_AIPS_MPRA_MPL1 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL1. |
mbed_official | 146:f64d43ff0c18 | 501 | |
mbed_official | 146:f64d43ff0c18 | 502 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 503 | //! @brief Read current value of the AIPS_MPRA_MPL1 field. |
mbed_official | 146:f64d43ff0c18 | 504 | #define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1)) |
mbed_official | 146:f64d43ff0c18 | 505 | #endif |
mbed_official | 146:f64d43ff0c18 | 506 | |
mbed_official | 146:f64d43ff0c18 | 507 | //! @brief Format value for bitfield AIPS_MPRA_MPL1. |
mbed_official | 146:f64d43ff0c18 | 508 | #define BF_AIPS_MPRA_MPL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL1), uint32_t) & BM_AIPS_MPRA_MPL1) |
mbed_official | 146:f64d43ff0c18 | 509 | |
mbed_official | 146:f64d43ff0c18 | 510 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 511 | //! @brief Set the MPL1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 512 | #define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 513 | #endif |
mbed_official | 146:f64d43ff0c18 | 514 | //@} |
mbed_official | 146:f64d43ff0c18 | 515 | |
mbed_official | 146:f64d43ff0c18 | 516 | /*! |
mbed_official | 146:f64d43ff0c18 | 517 | * @name Register AIPS_MPRA, field MTW1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 518 | * |
mbed_official | 146:f64d43ff0c18 | 519 | * Determines whether the master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 520 | * |
mbed_official | 146:f64d43ff0c18 | 521 | * Values: |
mbed_official | 146:f64d43ff0c18 | 522 | * - 0 - This master is not trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 523 | * - 1 - This master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 524 | */ |
mbed_official | 146:f64d43ff0c18 | 525 | //@{ |
mbed_official | 146:f64d43ff0c18 | 526 | #define BP_AIPS_MPRA_MTW1 (25U) //!< Bit position for AIPS_MPRA_MTW1. |
mbed_official | 146:f64d43ff0c18 | 527 | #define BM_AIPS_MPRA_MTW1 (0x02000000U) //!< Bit mask for AIPS_MPRA_MTW1. |
mbed_official | 146:f64d43ff0c18 | 528 | #define BS_AIPS_MPRA_MTW1 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW1. |
mbed_official | 146:f64d43ff0c18 | 529 | |
mbed_official | 146:f64d43ff0c18 | 530 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 531 | //! @brief Read current value of the AIPS_MPRA_MTW1 field. |
mbed_official | 146:f64d43ff0c18 | 532 | #define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1)) |
mbed_official | 146:f64d43ff0c18 | 533 | #endif |
mbed_official | 146:f64d43ff0c18 | 534 | |
mbed_official | 146:f64d43ff0c18 | 535 | //! @brief Format value for bitfield AIPS_MPRA_MTW1. |
mbed_official | 146:f64d43ff0c18 | 536 | #define BF_AIPS_MPRA_MTW1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW1), uint32_t) & BM_AIPS_MPRA_MTW1) |
mbed_official | 146:f64d43ff0c18 | 537 | |
mbed_official | 146:f64d43ff0c18 | 538 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 539 | //! @brief Set the MTW1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 540 | #define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 541 | #endif |
mbed_official | 146:f64d43ff0c18 | 542 | //@} |
mbed_official | 146:f64d43ff0c18 | 543 | |
mbed_official | 146:f64d43ff0c18 | 544 | /*! |
mbed_official | 146:f64d43ff0c18 | 545 | * @name Register AIPS_MPRA, field MTR1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 546 | * |
mbed_official | 146:f64d43ff0c18 | 547 | * Determines whether the master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 548 | * |
mbed_official | 146:f64d43ff0c18 | 549 | * Values: |
mbed_official | 146:f64d43ff0c18 | 550 | * - 0 - This master is not trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 551 | * - 1 - This master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 552 | */ |
mbed_official | 146:f64d43ff0c18 | 553 | //@{ |
mbed_official | 146:f64d43ff0c18 | 554 | #define BP_AIPS_MPRA_MTR1 (26U) //!< Bit position for AIPS_MPRA_MTR1. |
mbed_official | 146:f64d43ff0c18 | 555 | #define BM_AIPS_MPRA_MTR1 (0x04000000U) //!< Bit mask for AIPS_MPRA_MTR1. |
mbed_official | 146:f64d43ff0c18 | 556 | #define BS_AIPS_MPRA_MTR1 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR1. |
mbed_official | 146:f64d43ff0c18 | 557 | |
mbed_official | 146:f64d43ff0c18 | 558 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 559 | //! @brief Read current value of the AIPS_MPRA_MTR1 field. |
mbed_official | 146:f64d43ff0c18 | 560 | #define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1)) |
mbed_official | 146:f64d43ff0c18 | 561 | #endif |
mbed_official | 146:f64d43ff0c18 | 562 | |
mbed_official | 146:f64d43ff0c18 | 563 | //! @brief Format value for bitfield AIPS_MPRA_MTR1. |
mbed_official | 146:f64d43ff0c18 | 564 | #define BF_AIPS_MPRA_MTR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR1), uint32_t) & BM_AIPS_MPRA_MTR1) |
mbed_official | 146:f64d43ff0c18 | 565 | |
mbed_official | 146:f64d43ff0c18 | 566 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 567 | //! @brief Set the MTR1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 568 | #define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 569 | #endif |
mbed_official | 146:f64d43ff0c18 | 570 | //@} |
mbed_official | 146:f64d43ff0c18 | 571 | |
mbed_official | 146:f64d43ff0c18 | 572 | /*! |
mbed_official | 146:f64d43ff0c18 | 573 | * @name Register AIPS_MPRA, field MPL0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 574 | * |
mbed_official | 146:f64d43ff0c18 | 575 | * Specifies how the privilege level of the master is determined. |
mbed_official | 146:f64d43ff0c18 | 576 | * |
mbed_official | 146:f64d43ff0c18 | 577 | * Values: |
mbed_official | 146:f64d43ff0c18 | 578 | * - 0 - Accesses from this master are forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 579 | * - 1 - Accesses from this master are not forced to user-mode. |
mbed_official | 146:f64d43ff0c18 | 580 | */ |
mbed_official | 146:f64d43ff0c18 | 581 | //@{ |
mbed_official | 146:f64d43ff0c18 | 582 | #define BP_AIPS_MPRA_MPL0 (28U) //!< Bit position for AIPS_MPRA_MPL0. |
mbed_official | 146:f64d43ff0c18 | 583 | #define BM_AIPS_MPRA_MPL0 (0x10000000U) //!< Bit mask for AIPS_MPRA_MPL0. |
mbed_official | 146:f64d43ff0c18 | 584 | #define BS_AIPS_MPRA_MPL0 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL0. |
mbed_official | 146:f64d43ff0c18 | 585 | |
mbed_official | 146:f64d43ff0c18 | 586 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 587 | //! @brief Read current value of the AIPS_MPRA_MPL0 field. |
mbed_official | 146:f64d43ff0c18 | 588 | #define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0)) |
mbed_official | 146:f64d43ff0c18 | 589 | #endif |
mbed_official | 146:f64d43ff0c18 | 590 | |
mbed_official | 146:f64d43ff0c18 | 591 | //! @brief Format value for bitfield AIPS_MPRA_MPL0. |
mbed_official | 146:f64d43ff0c18 | 592 | #define BF_AIPS_MPRA_MPL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL0), uint32_t) & BM_AIPS_MPRA_MPL0) |
mbed_official | 146:f64d43ff0c18 | 593 | |
mbed_official | 146:f64d43ff0c18 | 594 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 595 | //! @brief Set the MPL0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 596 | #define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 597 | #endif |
mbed_official | 146:f64d43ff0c18 | 598 | //@} |
mbed_official | 146:f64d43ff0c18 | 599 | |
mbed_official | 146:f64d43ff0c18 | 600 | /*! |
mbed_official | 146:f64d43ff0c18 | 601 | * @name Register AIPS_MPRA, field MTW0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 602 | * |
mbed_official | 146:f64d43ff0c18 | 603 | * Determines whether the master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 604 | * |
mbed_official | 146:f64d43ff0c18 | 605 | * Values: |
mbed_official | 146:f64d43ff0c18 | 606 | * - 0 - This master is not trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 607 | * - 1 - This master is trusted for write accesses. |
mbed_official | 146:f64d43ff0c18 | 608 | */ |
mbed_official | 146:f64d43ff0c18 | 609 | //@{ |
mbed_official | 146:f64d43ff0c18 | 610 | #define BP_AIPS_MPRA_MTW0 (29U) //!< Bit position for AIPS_MPRA_MTW0. |
mbed_official | 146:f64d43ff0c18 | 611 | #define BM_AIPS_MPRA_MTW0 (0x20000000U) //!< Bit mask for AIPS_MPRA_MTW0. |
mbed_official | 146:f64d43ff0c18 | 612 | #define BS_AIPS_MPRA_MTW0 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW0. |
mbed_official | 146:f64d43ff0c18 | 613 | |
mbed_official | 146:f64d43ff0c18 | 614 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 615 | //! @brief Read current value of the AIPS_MPRA_MTW0 field. |
mbed_official | 146:f64d43ff0c18 | 616 | #define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0)) |
mbed_official | 146:f64d43ff0c18 | 617 | #endif |
mbed_official | 146:f64d43ff0c18 | 618 | |
mbed_official | 146:f64d43ff0c18 | 619 | //! @brief Format value for bitfield AIPS_MPRA_MTW0. |
mbed_official | 146:f64d43ff0c18 | 620 | #define BF_AIPS_MPRA_MTW0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW0), uint32_t) & BM_AIPS_MPRA_MTW0) |
mbed_official | 146:f64d43ff0c18 | 621 | |
mbed_official | 146:f64d43ff0c18 | 622 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 623 | //! @brief Set the MTW0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 624 | #define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 625 | #endif |
mbed_official | 146:f64d43ff0c18 | 626 | //@} |
mbed_official | 146:f64d43ff0c18 | 627 | |
mbed_official | 146:f64d43ff0c18 | 628 | /*! |
mbed_official | 146:f64d43ff0c18 | 629 | * @name Register AIPS_MPRA, field MTR0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 630 | * |
mbed_official | 146:f64d43ff0c18 | 631 | * Determines whether the master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 632 | * |
mbed_official | 146:f64d43ff0c18 | 633 | * Values: |
mbed_official | 146:f64d43ff0c18 | 634 | * - 0 - This master is not trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 635 | * - 1 - This master is trusted for read accesses. |
mbed_official | 146:f64d43ff0c18 | 636 | */ |
mbed_official | 146:f64d43ff0c18 | 637 | //@{ |
mbed_official | 146:f64d43ff0c18 | 638 | #define BP_AIPS_MPRA_MTR0 (30U) //!< Bit position for AIPS_MPRA_MTR0. |
mbed_official | 146:f64d43ff0c18 | 639 | #define BM_AIPS_MPRA_MTR0 (0x40000000U) //!< Bit mask for AIPS_MPRA_MTR0. |
mbed_official | 146:f64d43ff0c18 | 640 | #define BS_AIPS_MPRA_MTR0 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR0. |
mbed_official | 146:f64d43ff0c18 | 641 | |
mbed_official | 146:f64d43ff0c18 | 642 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 643 | //! @brief Read current value of the AIPS_MPRA_MTR0 field. |
mbed_official | 146:f64d43ff0c18 | 644 | #define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0)) |
mbed_official | 146:f64d43ff0c18 | 645 | #endif |
mbed_official | 146:f64d43ff0c18 | 646 | |
mbed_official | 146:f64d43ff0c18 | 647 | //! @brief Format value for bitfield AIPS_MPRA_MTR0. |
mbed_official | 146:f64d43ff0c18 | 648 | #define BF_AIPS_MPRA_MTR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR0), uint32_t) & BM_AIPS_MPRA_MTR0) |
mbed_official | 146:f64d43ff0c18 | 649 | |
mbed_official | 146:f64d43ff0c18 | 650 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 651 | //! @brief Set the MTR0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 652 | #define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 653 | #endif |
mbed_official | 146:f64d43ff0c18 | 654 | //@} |
mbed_official | 146:f64d43ff0c18 | 655 | |
mbed_official | 146:f64d43ff0c18 | 656 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 657 | // HW_AIPS_PACRA - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 658 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 659 | |
mbed_official | 146:f64d43ff0c18 | 660 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 661 | /*! |
mbed_official | 146:f64d43ff0c18 | 662 | * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 663 | * |
mbed_official | 146:f64d43ff0c18 | 664 | * Reset value: 0x50004000U |
mbed_official | 146:f64d43ff0c18 | 665 | * |
mbed_official | 146:f64d43ff0c18 | 666 | * Each PACR register consists of eight 4-bit PACR fields. Each PACR field |
mbed_official | 146:f64d43ff0c18 | 667 | * defines the access levels for a particular peripheral. The mapping between a |
mbed_official | 146:f64d43ff0c18 | 668 | * peripheral and its PACR field is shown in the table below. The peripheral assignment |
mbed_official | 146:f64d43ff0c18 | 669 | * to each PACR is defined by the memory map slot that the peripheral is |
mbed_official | 146:f64d43ff0c18 | 670 | * assigned to. See this chip's memory map for the assignment of a particular |
mbed_official | 146:f64d43ff0c18 | 671 | * peripheral. The following table shows the location of each peripheral slot's PACR field |
mbed_official | 146:f64d43ff0c18 | 672 | * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] |
mbed_official | 146:f64d43ff0c18 | 673 | * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 |
mbed_official | 146:f64d43ff0c18 | 674 | * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC |
mbed_official | 146:f64d43ff0c18 | 675 | * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 |
mbed_official | 146:f64d43ff0c18 | 676 | * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 |
mbed_official | 146:f64d43ff0c18 | 677 | * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 |
mbed_official | 146:f64d43ff0c18 | 678 | * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 |
mbed_official | 146:f64d43ff0c18 | 679 | * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH |
mbed_official | 146:f64d43ff0c18 | 680 | * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 |
mbed_official | 146:f64d43ff0c18 | 681 | * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 |
mbed_official | 146:f64d43ff0c18 | 682 | * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 |
mbed_official | 146:f64d43ff0c18 | 683 | * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 |
mbed_official | 146:f64d43ff0c18 | 684 | * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 |
mbed_official | 146:f64d43ff0c18 | 685 | * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 |
mbed_official | 146:f64d43ff0c18 | 686 | * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 |
mbed_official | 146:f64d43ff0c18 | 687 | * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 |
mbed_official | 146:f64d43ff0c18 | 688 | * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR |
mbed_official | 146:f64d43ff0c18 | 689 | * A-D, which control peripheral slots 0-31, are shown below. The following |
mbed_official | 146:f64d43ff0c18 | 690 | * section, PACRPeripheral Access Control Register , shows the register field |
mbed_official | 146:f64d43ff0c18 | 691 | * descriptions for PACR E-P. All PACR registers are identical. They are divided into two |
mbed_official | 146:f64d43ff0c18 | 692 | * sections because they occupy two non-contiguous address spaces. |
mbed_official | 146:f64d43ff0c18 | 693 | */ |
mbed_official | 146:f64d43ff0c18 | 694 | typedef union _hw_aips_pacra |
mbed_official | 146:f64d43ff0c18 | 695 | { |
mbed_official | 146:f64d43ff0c18 | 696 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 697 | struct _hw_aips_pacra_bitfields |
mbed_official | 146:f64d43ff0c18 | 698 | { |
mbed_official | 146:f64d43ff0c18 | 699 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 700 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 701 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 702 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 703 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 704 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 705 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 706 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 707 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 708 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 709 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 710 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 711 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 712 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 713 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 714 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 715 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 716 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 717 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 718 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 719 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 720 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 721 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 722 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 723 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 724 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 725 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 726 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 727 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 728 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 729 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 730 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 731 | } B; |
mbed_official | 146:f64d43ff0c18 | 732 | } hw_aips_pacra_t; |
mbed_official | 146:f64d43ff0c18 | 733 | #endif |
mbed_official | 146:f64d43ff0c18 | 734 | |
mbed_official | 146:f64d43ff0c18 | 735 | /*! |
mbed_official | 146:f64d43ff0c18 | 736 | * @name Constants and macros for entire AIPS_PACRA register |
mbed_official | 146:f64d43ff0c18 | 737 | */ |
mbed_official | 146:f64d43ff0c18 | 738 | //@{ |
mbed_official | 146:f64d43ff0c18 | 739 | #define HW_AIPS_PACRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x20U) |
mbed_official | 146:f64d43ff0c18 | 740 | |
mbed_official | 146:f64d43ff0c18 | 741 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 742 | #define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 743 | #define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U) |
mbed_official | 146:f64d43ff0c18 | 744 | #define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 745 | #define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 746 | #define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 747 | #define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 748 | #endif |
mbed_official | 146:f64d43ff0c18 | 749 | //@} |
mbed_official | 146:f64d43ff0c18 | 750 | |
mbed_official | 146:f64d43ff0c18 | 751 | /* |
mbed_official | 146:f64d43ff0c18 | 752 | * Constants & macros for individual AIPS_PACRA bitfields |
mbed_official | 146:f64d43ff0c18 | 753 | */ |
mbed_official | 146:f64d43ff0c18 | 754 | |
mbed_official | 146:f64d43ff0c18 | 755 | /*! |
mbed_official | 146:f64d43ff0c18 | 756 | * @name Register AIPS_PACRA, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 757 | * |
mbed_official | 146:f64d43ff0c18 | 758 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 759 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 760 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 761 | * |
mbed_official | 146:f64d43ff0c18 | 762 | * Values: |
mbed_official | 146:f64d43ff0c18 | 763 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 764 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 765 | */ |
mbed_official | 146:f64d43ff0c18 | 766 | //@{ |
mbed_official | 146:f64d43ff0c18 | 767 | #define BP_AIPS_PACRA_TP7 (0U) //!< Bit position for AIPS_PACRA_TP7. |
mbed_official | 146:f64d43ff0c18 | 768 | #define BM_AIPS_PACRA_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRA_TP7. |
mbed_official | 146:f64d43ff0c18 | 769 | #define BS_AIPS_PACRA_TP7 (1U) //!< Bit field size in bits for AIPS_PACRA_TP7. |
mbed_official | 146:f64d43ff0c18 | 770 | |
mbed_official | 146:f64d43ff0c18 | 771 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 772 | //! @brief Read current value of the AIPS_PACRA_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 773 | #define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7)) |
mbed_official | 146:f64d43ff0c18 | 774 | #endif |
mbed_official | 146:f64d43ff0c18 | 775 | |
mbed_official | 146:f64d43ff0c18 | 776 | //! @brief Format value for bitfield AIPS_PACRA_TP7. |
mbed_official | 146:f64d43ff0c18 | 777 | #define BF_AIPS_PACRA_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP7), uint32_t) & BM_AIPS_PACRA_TP7) |
mbed_official | 146:f64d43ff0c18 | 778 | |
mbed_official | 146:f64d43ff0c18 | 779 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 780 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 781 | #define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 782 | #endif |
mbed_official | 146:f64d43ff0c18 | 783 | //@} |
mbed_official | 146:f64d43ff0c18 | 784 | |
mbed_official | 146:f64d43ff0c18 | 785 | /*! |
mbed_official | 146:f64d43ff0c18 | 786 | * @name Register AIPS_PACRA, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 787 | * |
mbed_official | 146:f64d43ff0c18 | 788 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 789 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 790 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 791 | * |
mbed_official | 146:f64d43ff0c18 | 792 | * Values: |
mbed_official | 146:f64d43ff0c18 | 793 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 794 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 795 | */ |
mbed_official | 146:f64d43ff0c18 | 796 | //@{ |
mbed_official | 146:f64d43ff0c18 | 797 | #define BP_AIPS_PACRA_WP7 (1U) //!< Bit position for AIPS_PACRA_WP7. |
mbed_official | 146:f64d43ff0c18 | 798 | #define BM_AIPS_PACRA_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRA_WP7. |
mbed_official | 146:f64d43ff0c18 | 799 | #define BS_AIPS_PACRA_WP7 (1U) //!< Bit field size in bits for AIPS_PACRA_WP7. |
mbed_official | 146:f64d43ff0c18 | 800 | |
mbed_official | 146:f64d43ff0c18 | 801 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 802 | //! @brief Read current value of the AIPS_PACRA_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 803 | #define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7)) |
mbed_official | 146:f64d43ff0c18 | 804 | #endif |
mbed_official | 146:f64d43ff0c18 | 805 | |
mbed_official | 146:f64d43ff0c18 | 806 | //! @brief Format value for bitfield AIPS_PACRA_WP7. |
mbed_official | 146:f64d43ff0c18 | 807 | #define BF_AIPS_PACRA_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP7), uint32_t) & BM_AIPS_PACRA_WP7) |
mbed_official | 146:f64d43ff0c18 | 808 | |
mbed_official | 146:f64d43ff0c18 | 809 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 810 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 811 | #define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 812 | #endif |
mbed_official | 146:f64d43ff0c18 | 813 | //@} |
mbed_official | 146:f64d43ff0c18 | 814 | |
mbed_official | 146:f64d43ff0c18 | 815 | /*! |
mbed_official | 146:f64d43ff0c18 | 816 | * @name Register AIPS_PACRA, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 817 | * |
mbed_official | 146:f64d43ff0c18 | 818 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 819 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 820 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 821 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 822 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 823 | * |
mbed_official | 146:f64d43ff0c18 | 824 | * Values: |
mbed_official | 146:f64d43ff0c18 | 825 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 826 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 827 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 828 | */ |
mbed_official | 146:f64d43ff0c18 | 829 | //@{ |
mbed_official | 146:f64d43ff0c18 | 830 | #define BP_AIPS_PACRA_SP7 (2U) //!< Bit position for AIPS_PACRA_SP7. |
mbed_official | 146:f64d43ff0c18 | 831 | #define BM_AIPS_PACRA_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRA_SP7. |
mbed_official | 146:f64d43ff0c18 | 832 | #define BS_AIPS_PACRA_SP7 (1U) //!< Bit field size in bits for AIPS_PACRA_SP7. |
mbed_official | 146:f64d43ff0c18 | 833 | |
mbed_official | 146:f64d43ff0c18 | 834 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 835 | //! @brief Read current value of the AIPS_PACRA_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 836 | #define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7)) |
mbed_official | 146:f64d43ff0c18 | 837 | #endif |
mbed_official | 146:f64d43ff0c18 | 838 | |
mbed_official | 146:f64d43ff0c18 | 839 | //! @brief Format value for bitfield AIPS_PACRA_SP7. |
mbed_official | 146:f64d43ff0c18 | 840 | #define BF_AIPS_PACRA_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP7), uint32_t) & BM_AIPS_PACRA_SP7) |
mbed_official | 146:f64d43ff0c18 | 841 | |
mbed_official | 146:f64d43ff0c18 | 842 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 843 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 844 | #define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 845 | #endif |
mbed_official | 146:f64d43ff0c18 | 846 | //@} |
mbed_official | 146:f64d43ff0c18 | 847 | |
mbed_official | 146:f64d43ff0c18 | 848 | /*! |
mbed_official | 146:f64d43ff0c18 | 849 | * @name Register AIPS_PACRA, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 850 | * |
mbed_official | 146:f64d43ff0c18 | 851 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 852 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 853 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 854 | * |
mbed_official | 146:f64d43ff0c18 | 855 | * Values: |
mbed_official | 146:f64d43ff0c18 | 856 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 857 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 858 | */ |
mbed_official | 146:f64d43ff0c18 | 859 | //@{ |
mbed_official | 146:f64d43ff0c18 | 860 | #define BP_AIPS_PACRA_TP6 (4U) //!< Bit position for AIPS_PACRA_TP6. |
mbed_official | 146:f64d43ff0c18 | 861 | #define BM_AIPS_PACRA_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRA_TP6. |
mbed_official | 146:f64d43ff0c18 | 862 | #define BS_AIPS_PACRA_TP6 (1U) //!< Bit field size in bits for AIPS_PACRA_TP6. |
mbed_official | 146:f64d43ff0c18 | 863 | |
mbed_official | 146:f64d43ff0c18 | 864 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 865 | //! @brief Read current value of the AIPS_PACRA_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 866 | #define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6)) |
mbed_official | 146:f64d43ff0c18 | 867 | #endif |
mbed_official | 146:f64d43ff0c18 | 868 | |
mbed_official | 146:f64d43ff0c18 | 869 | //! @brief Format value for bitfield AIPS_PACRA_TP6. |
mbed_official | 146:f64d43ff0c18 | 870 | #define BF_AIPS_PACRA_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP6), uint32_t) & BM_AIPS_PACRA_TP6) |
mbed_official | 146:f64d43ff0c18 | 871 | |
mbed_official | 146:f64d43ff0c18 | 872 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 873 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 874 | #define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 875 | #endif |
mbed_official | 146:f64d43ff0c18 | 876 | //@} |
mbed_official | 146:f64d43ff0c18 | 877 | |
mbed_official | 146:f64d43ff0c18 | 878 | /*! |
mbed_official | 146:f64d43ff0c18 | 879 | * @name Register AIPS_PACRA, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 880 | * |
mbed_official | 146:f64d43ff0c18 | 881 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 882 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 883 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 884 | * |
mbed_official | 146:f64d43ff0c18 | 885 | * Values: |
mbed_official | 146:f64d43ff0c18 | 886 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 887 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 888 | */ |
mbed_official | 146:f64d43ff0c18 | 889 | //@{ |
mbed_official | 146:f64d43ff0c18 | 890 | #define BP_AIPS_PACRA_WP6 (5U) //!< Bit position for AIPS_PACRA_WP6. |
mbed_official | 146:f64d43ff0c18 | 891 | #define BM_AIPS_PACRA_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRA_WP6. |
mbed_official | 146:f64d43ff0c18 | 892 | #define BS_AIPS_PACRA_WP6 (1U) //!< Bit field size in bits for AIPS_PACRA_WP6. |
mbed_official | 146:f64d43ff0c18 | 893 | |
mbed_official | 146:f64d43ff0c18 | 894 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 895 | //! @brief Read current value of the AIPS_PACRA_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 896 | #define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6)) |
mbed_official | 146:f64d43ff0c18 | 897 | #endif |
mbed_official | 146:f64d43ff0c18 | 898 | |
mbed_official | 146:f64d43ff0c18 | 899 | //! @brief Format value for bitfield AIPS_PACRA_WP6. |
mbed_official | 146:f64d43ff0c18 | 900 | #define BF_AIPS_PACRA_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP6), uint32_t) & BM_AIPS_PACRA_WP6) |
mbed_official | 146:f64d43ff0c18 | 901 | |
mbed_official | 146:f64d43ff0c18 | 902 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 903 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 904 | #define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 905 | #endif |
mbed_official | 146:f64d43ff0c18 | 906 | //@} |
mbed_official | 146:f64d43ff0c18 | 907 | |
mbed_official | 146:f64d43ff0c18 | 908 | /*! |
mbed_official | 146:f64d43ff0c18 | 909 | * @name Register AIPS_PACRA, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 910 | * |
mbed_official | 146:f64d43ff0c18 | 911 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 912 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 913 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 914 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 915 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 916 | * |
mbed_official | 146:f64d43ff0c18 | 917 | * Values: |
mbed_official | 146:f64d43ff0c18 | 918 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 919 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 920 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 921 | */ |
mbed_official | 146:f64d43ff0c18 | 922 | //@{ |
mbed_official | 146:f64d43ff0c18 | 923 | #define BP_AIPS_PACRA_SP6 (6U) //!< Bit position for AIPS_PACRA_SP6. |
mbed_official | 146:f64d43ff0c18 | 924 | #define BM_AIPS_PACRA_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRA_SP6. |
mbed_official | 146:f64d43ff0c18 | 925 | #define BS_AIPS_PACRA_SP6 (1U) //!< Bit field size in bits for AIPS_PACRA_SP6. |
mbed_official | 146:f64d43ff0c18 | 926 | |
mbed_official | 146:f64d43ff0c18 | 927 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 928 | //! @brief Read current value of the AIPS_PACRA_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 929 | #define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6)) |
mbed_official | 146:f64d43ff0c18 | 930 | #endif |
mbed_official | 146:f64d43ff0c18 | 931 | |
mbed_official | 146:f64d43ff0c18 | 932 | //! @brief Format value for bitfield AIPS_PACRA_SP6. |
mbed_official | 146:f64d43ff0c18 | 933 | #define BF_AIPS_PACRA_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP6), uint32_t) & BM_AIPS_PACRA_SP6) |
mbed_official | 146:f64d43ff0c18 | 934 | |
mbed_official | 146:f64d43ff0c18 | 935 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 936 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 937 | #define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 938 | #endif |
mbed_official | 146:f64d43ff0c18 | 939 | //@} |
mbed_official | 146:f64d43ff0c18 | 940 | |
mbed_official | 146:f64d43ff0c18 | 941 | /*! |
mbed_official | 146:f64d43ff0c18 | 942 | * @name Register AIPS_PACRA, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 943 | * |
mbed_official | 146:f64d43ff0c18 | 944 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 945 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 946 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 947 | * |
mbed_official | 146:f64d43ff0c18 | 948 | * Values: |
mbed_official | 146:f64d43ff0c18 | 949 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 950 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 951 | */ |
mbed_official | 146:f64d43ff0c18 | 952 | //@{ |
mbed_official | 146:f64d43ff0c18 | 953 | #define BP_AIPS_PACRA_TP5 (8U) //!< Bit position for AIPS_PACRA_TP5. |
mbed_official | 146:f64d43ff0c18 | 954 | #define BM_AIPS_PACRA_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRA_TP5. |
mbed_official | 146:f64d43ff0c18 | 955 | #define BS_AIPS_PACRA_TP5 (1U) //!< Bit field size in bits for AIPS_PACRA_TP5. |
mbed_official | 146:f64d43ff0c18 | 956 | |
mbed_official | 146:f64d43ff0c18 | 957 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 958 | //! @brief Read current value of the AIPS_PACRA_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 959 | #define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5)) |
mbed_official | 146:f64d43ff0c18 | 960 | #endif |
mbed_official | 146:f64d43ff0c18 | 961 | |
mbed_official | 146:f64d43ff0c18 | 962 | //! @brief Format value for bitfield AIPS_PACRA_TP5. |
mbed_official | 146:f64d43ff0c18 | 963 | #define BF_AIPS_PACRA_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP5), uint32_t) & BM_AIPS_PACRA_TP5) |
mbed_official | 146:f64d43ff0c18 | 964 | |
mbed_official | 146:f64d43ff0c18 | 965 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 966 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 967 | #define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 968 | #endif |
mbed_official | 146:f64d43ff0c18 | 969 | //@} |
mbed_official | 146:f64d43ff0c18 | 970 | |
mbed_official | 146:f64d43ff0c18 | 971 | /*! |
mbed_official | 146:f64d43ff0c18 | 972 | * @name Register AIPS_PACRA, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 973 | * |
mbed_official | 146:f64d43ff0c18 | 974 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 975 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 976 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 977 | * |
mbed_official | 146:f64d43ff0c18 | 978 | * Values: |
mbed_official | 146:f64d43ff0c18 | 979 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 980 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 981 | */ |
mbed_official | 146:f64d43ff0c18 | 982 | //@{ |
mbed_official | 146:f64d43ff0c18 | 983 | #define BP_AIPS_PACRA_WP5 (9U) //!< Bit position for AIPS_PACRA_WP5. |
mbed_official | 146:f64d43ff0c18 | 984 | #define BM_AIPS_PACRA_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRA_WP5. |
mbed_official | 146:f64d43ff0c18 | 985 | #define BS_AIPS_PACRA_WP5 (1U) //!< Bit field size in bits for AIPS_PACRA_WP5. |
mbed_official | 146:f64d43ff0c18 | 986 | |
mbed_official | 146:f64d43ff0c18 | 987 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 988 | //! @brief Read current value of the AIPS_PACRA_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 989 | #define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5)) |
mbed_official | 146:f64d43ff0c18 | 990 | #endif |
mbed_official | 146:f64d43ff0c18 | 991 | |
mbed_official | 146:f64d43ff0c18 | 992 | //! @brief Format value for bitfield AIPS_PACRA_WP5. |
mbed_official | 146:f64d43ff0c18 | 993 | #define BF_AIPS_PACRA_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP5), uint32_t) & BM_AIPS_PACRA_WP5) |
mbed_official | 146:f64d43ff0c18 | 994 | |
mbed_official | 146:f64d43ff0c18 | 995 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 996 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 997 | #define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 998 | #endif |
mbed_official | 146:f64d43ff0c18 | 999 | //@} |
mbed_official | 146:f64d43ff0c18 | 1000 | |
mbed_official | 146:f64d43ff0c18 | 1001 | /*! |
mbed_official | 146:f64d43ff0c18 | 1002 | * @name Register AIPS_PACRA, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 1003 | * |
mbed_official | 146:f64d43ff0c18 | 1004 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1005 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1006 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1007 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1008 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1009 | * |
mbed_official | 146:f64d43ff0c18 | 1010 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1011 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1012 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1013 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1014 | */ |
mbed_official | 146:f64d43ff0c18 | 1015 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1016 | #define BP_AIPS_PACRA_SP5 (10U) //!< Bit position for AIPS_PACRA_SP5. |
mbed_official | 146:f64d43ff0c18 | 1017 | #define BM_AIPS_PACRA_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRA_SP5. |
mbed_official | 146:f64d43ff0c18 | 1018 | #define BS_AIPS_PACRA_SP5 (1U) //!< Bit field size in bits for AIPS_PACRA_SP5. |
mbed_official | 146:f64d43ff0c18 | 1019 | |
mbed_official | 146:f64d43ff0c18 | 1020 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1021 | //! @brief Read current value of the AIPS_PACRA_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 1022 | #define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5)) |
mbed_official | 146:f64d43ff0c18 | 1023 | #endif |
mbed_official | 146:f64d43ff0c18 | 1024 | |
mbed_official | 146:f64d43ff0c18 | 1025 | //! @brief Format value for bitfield AIPS_PACRA_SP5. |
mbed_official | 146:f64d43ff0c18 | 1026 | #define BF_AIPS_PACRA_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP5), uint32_t) & BM_AIPS_PACRA_SP5) |
mbed_official | 146:f64d43ff0c18 | 1027 | |
mbed_official | 146:f64d43ff0c18 | 1028 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1029 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1030 | #define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1031 | #endif |
mbed_official | 146:f64d43ff0c18 | 1032 | //@} |
mbed_official | 146:f64d43ff0c18 | 1033 | |
mbed_official | 146:f64d43ff0c18 | 1034 | /*! |
mbed_official | 146:f64d43ff0c18 | 1035 | * @name Register AIPS_PACRA, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 1036 | * |
mbed_official | 146:f64d43ff0c18 | 1037 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1038 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1039 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1040 | * |
mbed_official | 146:f64d43ff0c18 | 1041 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1042 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1043 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1044 | */ |
mbed_official | 146:f64d43ff0c18 | 1045 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1046 | #define BP_AIPS_PACRA_TP4 (12U) //!< Bit position for AIPS_PACRA_TP4. |
mbed_official | 146:f64d43ff0c18 | 1047 | #define BM_AIPS_PACRA_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRA_TP4. |
mbed_official | 146:f64d43ff0c18 | 1048 | #define BS_AIPS_PACRA_TP4 (1U) //!< Bit field size in bits for AIPS_PACRA_TP4. |
mbed_official | 146:f64d43ff0c18 | 1049 | |
mbed_official | 146:f64d43ff0c18 | 1050 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1051 | //! @brief Read current value of the AIPS_PACRA_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 1052 | #define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4)) |
mbed_official | 146:f64d43ff0c18 | 1053 | #endif |
mbed_official | 146:f64d43ff0c18 | 1054 | |
mbed_official | 146:f64d43ff0c18 | 1055 | //! @brief Format value for bitfield AIPS_PACRA_TP4. |
mbed_official | 146:f64d43ff0c18 | 1056 | #define BF_AIPS_PACRA_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP4), uint32_t) & BM_AIPS_PACRA_TP4) |
mbed_official | 146:f64d43ff0c18 | 1057 | |
mbed_official | 146:f64d43ff0c18 | 1058 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1059 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1060 | #define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1061 | #endif |
mbed_official | 146:f64d43ff0c18 | 1062 | //@} |
mbed_official | 146:f64d43ff0c18 | 1063 | |
mbed_official | 146:f64d43ff0c18 | 1064 | /*! |
mbed_official | 146:f64d43ff0c18 | 1065 | * @name Register AIPS_PACRA, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 1066 | * |
mbed_official | 146:f64d43ff0c18 | 1067 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 1068 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 1069 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1070 | * |
mbed_official | 146:f64d43ff0c18 | 1071 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1072 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1073 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1074 | */ |
mbed_official | 146:f64d43ff0c18 | 1075 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1076 | #define BP_AIPS_PACRA_WP4 (13U) //!< Bit position for AIPS_PACRA_WP4. |
mbed_official | 146:f64d43ff0c18 | 1077 | #define BM_AIPS_PACRA_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRA_WP4. |
mbed_official | 146:f64d43ff0c18 | 1078 | #define BS_AIPS_PACRA_WP4 (1U) //!< Bit field size in bits for AIPS_PACRA_WP4. |
mbed_official | 146:f64d43ff0c18 | 1079 | |
mbed_official | 146:f64d43ff0c18 | 1080 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1081 | //! @brief Read current value of the AIPS_PACRA_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 1082 | #define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4)) |
mbed_official | 146:f64d43ff0c18 | 1083 | #endif |
mbed_official | 146:f64d43ff0c18 | 1084 | |
mbed_official | 146:f64d43ff0c18 | 1085 | //! @brief Format value for bitfield AIPS_PACRA_WP4. |
mbed_official | 146:f64d43ff0c18 | 1086 | #define BF_AIPS_PACRA_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP4), uint32_t) & BM_AIPS_PACRA_WP4) |
mbed_official | 146:f64d43ff0c18 | 1087 | |
mbed_official | 146:f64d43ff0c18 | 1088 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1089 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1090 | #define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1091 | #endif |
mbed_official | 146:f64d43ff0c18 | 1092 | //@} |
mbed_official | 146:f64d43ff0c18 | 1093 | |
mbed_official | 146:f64d43ff0c18 | 1094 | /*! |
mbed_official | 146:f64d43ff0c18 | 1095 | * @name Register AIPS_PACRA, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 1096 | * |
mbed_official | 146:f64d43ff0c18 | 1097 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1098 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1099 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1100 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1101 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1102 | * |
mbed_official | 146:f64d43ff0c18 | 1103 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1104 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1105 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1106 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1107 | */ |
mbed_official | 146:f64d43ff0c18 | 1108 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1109 | #define BP_AIPS_PACRA_SP4 (14U) //!< Bit position for AIPS_PACRA_SP4. |
mbed_official | 146:f64d43ff0c18 | 1110 | #define BM_AIPS_PACRA_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRA_SP4. |
mbed_official | 146:f64d43ff0c18 | 1111 | #define BS_AIPS_PACRA_SP4 (1U) //!< Bit field size in bits for AIPS_PACRA_SP4. |
mbed_official | 146:f64d43ff0c18 | 1112 | |
mbed_official | 146:f64d43ff0c18 | 1113 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1114 | //! @brief Read current value of the AIPS_PACRA_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 1115 | #define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4)) |
mbed_official | 146:f64d43ff0c18 | 1116 | #endif |
mbed_official | 146:f64d43ff0c18 | 1117 | |
mbed_official | 146:f64d43ff0c18 | 1118 | //! @brief Format value for bitfield AIPS_PACRA_SP4. |
mbed_official | 146:f64d43ff0c18 | 1119 | #define BF_AIPS_PACRA_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP4), uint32_t) & BM_AIPS_PACRA_SP4) |
mbed_official | 146:f64d43ff0c18 | 1120 | |
mbed_official | 146:f64d43ff0c18 | 1121 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1122 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1123 | #define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1124 | #endif |
mbed_official | 146:f64d43ff0c18 | 1125 | //@} |
mbed_official | 146:f64d43ff0c18 | 1126 | |
mbed_official | 146:f64d43ff0c18 | 1127 | /*! |
mbed_official | 146:f64d43ff0c18 | 1128 | * @name Register AIPS_PACRA, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 1129 | * |
mbed_official | 146:f64d43ff0c18 | 1130 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1131 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1132 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1133 | * |
mbed_official | 146:f64d43ff0c18 | 1134 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1135 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1136 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1137 | */ |
mbed_official | 146:f64d43ff0c18 | 1138 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1139 | #define BP_AIPS_PACRA_TP3 (16U) //!< Bit position for AIPS_PACRA_TP3. |
mbed_official | 146:f64d43ff0c18 | 1140 | #define BM_AIPS_PACRA_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRA_TP3. |
mbed_official | 146:f64d43ff0c18 | 1141 | #define BS_AIPS_PACRA_TP3 (1U) //!< Bit field size in bits for AIPS_PACRA_TP3. |
mbed_official | 146:f64d43ff0c18 | 1142 | |
mbed_official | 146:f64d43ff0c18 | 1143 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1144 | //! @brief Read current value of the AIPS_PACRA_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 1145 | #define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3)) |
mbed_official | 146:f64d43ff0c18 | 1146 | #endif |
mbed_official | 146:f64d43ff0c18 | 1147 | |
mbed_official | 146:f64d43ff0c18 | 1148 | //! @brief Format value for bitfield AIPS_PACRA_TP3. |
mbed_official | 146:f64d43ff0c18 | 1149 | #define BF_AIPS_PACRA_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP3), uint32_t) & BM_AIPS_PACRA_TP3) |
mbed_official | 146:f64d43ff0c18 | 1150 | |
mbed_official | 146:f64d43ff0c18 | 1151 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1152 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1153 | #define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1154 | #endif |
mbed_official | 146:f64d43ff0c18 | 1155 | //@} |
mbed_official | 146:f64d43ff0c18 | 1156 | |
mbed_official | 146:f64d43ff0c18 | 1157 | /*! |
mbed_official | 146:f64d43ff0c18 | 1158 | * @name Register AIPS_PACRA, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 1159 | * |
mbed_official | 146:f64d43ff0c18 | 1160 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 1161 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 1162 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1163 | * |
mbed_official | 146:f64d43ff0c18 | 1164 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1165 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1166 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1167 | */ |
mbed_official | 146:f64d43ff0c18 | 1168 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1169 | #define BP_AIPS_PACRA_WP3 (17U) //!< Bit position for AIPS_PACRA_WP3. |
mbed_official | 146:f64d43ff0c18 | 1170 | #define BM_AIPS_PACRA_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRA_WP3. |
mbed_official | 146:f64d43ff0c18 | 1171 | #define BS_AIPS_PACRA_WP3 (1U) //!< Bit field size in bits for AIPS_PACRA_WP3. |
mbed_official | 146:f64d43ff0c18 | 1172 | |
mbed_official | 146:f64d43ff0c18 | 1173 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1174 | //! @brief Read current value of the AIPS_PACRA_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 1175 | #define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3)) |
mbed_official | 146:f64d43ff0c18 | 1176 | #endif |
mbed_official | 146:f64d43ff0c18 | 1177 | |
mbed_official | 146:f64d43ff0c18 | 1178 | //! @brief Format value for bitfield AIPS_PACRA_WP3. |
mbed_official | 146:f64d43ff0c18 | 1179 | #define BF_AIPS_PACRA_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP3), uint32_t) & BM_AIPS_PACRA_WP3) |
mbed_official | 146:f64d43ff0c18 | 1180 | |
mbed_official | 146:f64d43ff0c18 | 1181 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1182 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1183 | #define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1184 | #endif |
mbed_official | 146:f64d43ff0c18 | 1185 | //@} |
mbed_official | 146:f64d43ff0c18 | 1186 | |
mbed_official | 146:f64d43ff0c18 | 1187 | /*! |
mbed_official | 146:f64d43ff0c18 | 1188 | * @name Register AIPS_PACRA, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 1189 | * |
mbed_official | 146:f64d43ff0c18 | 1190 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1191 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1192 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 1193 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 1194 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 1195 | * |
mbed_official | 146:f64d43ff0c18 | 1196 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1197 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1198 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1199 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1200 | */ |
mbed_official | 146:f64d43ff0c18 | 1201 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1202 | #define BP_AIPS_PACRA_SP3 (18U) //!< Bit position for AIPS_PACRA_SP3. |
mbed_official | 146:f64d43ff0c18 | 1203 | #define BM_AIPS_PACRA_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRA_SP3. |
mbed_official | 146:f64d43ff0c18 | 1204 | #define BS_AIPS_PACRA_SP3 (1U) //!< Bit field size in bits for AIPS_PACRA_SP3. |
mbed_official | 146:f64d43ff0c18 | 1205 | |
mbed_official | 146:f64d43ff0c18 | 1206 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1207 | //! @brief Read current value of the AIPS_PACRA_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 1208 | #define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3)) |
mbed_official | 146:f64d43ff0c18 | 1209 | #endif |
mbed_official | 146:f64d43ff0c18 | 1210 | |
mbed_official | 146:f64d43ff0c18 | 1211 | //! @brief Format value for bitfield AIPS_PACRA_SP3. |
mbed_official | 146:f64d43ff0c18 | 1212 | #define BF_AIPS_PACRA_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP3), uint32_t) & BM_AIPS_PACRA_SP3) |
mbed_official | 146:f64d43ff0c18 | 1213 | |
mbed_official | 146:f64d43ff0c18 | 1214 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1215 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1216 | #define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1217 | #endif |
mbed_official | 146:f64d43ff0c18 | 1218 | //@} |
mbed_official | 146:f64d43ff0c18 | 1219 | |
mbed_official | 146:f64d43ff0c18 | 1220 | /*! |
mbed_official | 146:f64d43ff0c18 | 1221 | * @name Register AIPS_PACRA, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 1222 | * |
mbed_official | 146:f64d43ff0c18 | 1223 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1224 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1225 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1226 | * |
mbed_official | 146:f64d43ff0c18 | 1227 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1228 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1229 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1230 | */ |
mbed_official | 146:f64d43ff0c18 | 1231 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1232 | #define BP_AIPS_PACRA_TP2 (20U) //!< Bit position for AIPS_PACRA_TP2. |
mbed_official | 146:f64d43ff0c18 | 1233 | #define BM_AIPS_PACRA_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRA_TP2. |
mbed_official | 146:f64d43ff0c18 | 1234 | #define BS_AIPS_PACRA_TP2 (1U) //!< Bit field size in bits for AIPS_PACRA_TP2. |
mbed_official | 146:f64d43ff0c18 | 1235 | |
mbed_official | 146:f64d43ff0c18 | 1236 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1237 | //! @brief Read current value of the AIPS_PACRA_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 1238 | #define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2)) |
mbed_official | 146:f64d43ff0c18 | 1239 | #endif |
mbed_official | 146:f64d43ff0c18 | 1240 | |
mbed_official | 146:f64d43ff0c18 | 1241 | //! @brief Format value for bitfield AIPS_PACRA_TP2. |
mbed_official | 146:f64d43ff0c18 | 1242 | #define BF_AIPS_PACRA_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP2), uint32_t) & BM_AIPS_PACRA_TP2) |
mbed_official | 146:f64d43ff0c18 | 1243 | |
mbed_official | 146:f64d43ff0c18 | 1244 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1245 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1246 | #define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1247 | #endif |
mbed_official | 146:f64d43ff0c18 | 1248 | //@} |
mbed_official | 146:f64d43ff0c18 | 1249 | |
mbed_official | 146:f64d43ff0c18 | 1250 | /*! |
mbed_official | 146:f64d43ff0c18 | 1251 | * @name Register AIPS_PACRA, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 1252 | * |
mbed_official | 146:f64d43ff0c18 | 1253 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 1254 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 1255 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1256 | * |
mbed_official | 146:f64d43ff0c18 | 1257 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1258 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1259 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1260 | */ |
mbed_official | 146:f64d43ff0c18 | 1261 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1262 | #define BP_AIPS_PACRA_WP2 (21U) //!< Bit position for AIPS_PACRA_WP2. |
mbed_official | 146:f64d43ff0c18 | 1263 | #define BM_AIPS_PACRA_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRA_WP2. |
mbed_official | 146:f64d43ff0c18 | 1264 | #define BS_AIPS_PACRA_WP2 (1U) //!< Bit field size in bits for AIPS_PACRA_WP2. |
mbed_official | 146:f64d43ff0c18 | 1265 | |
mbed_official | 146:f64d43ff0c18 | 1266 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1267 | //! @brief Read current value of the AIPS_PACRA_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 1268 | #define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2)) |
mbed_official | 146:f64d43ff0c18 | 1269 | #endif |
mbed_official | 146:f64d43ff0c18 | 1270 | |
mbed_official | 146:f64d43ff0c18 | 1271 | //! @brief Format value for bitfield AIPS_PACRA_WP2. |
mbed_official | 146:f64d43ff0c18 | 1272 | #define BF_AIPS_PACRA_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP2), uint32_t) & BM_AIPS_PACRA_WP2) |
mbed_official | 146:f64d43ff0c18 | 1273 | |
mbed_official | 146:f64d43ff0c18 | 1274 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1275 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1276 | #define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1277 | #endif |
mbed_official | 146:f64d43ff0c18 | 1278 | //@} |
mbed_official | 146:f64d43ff0c18 | 1279 | |
mbed_official | 146:f64d43ff0c18 | 1280 | /*! |
mbed_official | 146:f64d43ff0c18 | 1281 | * @name Register AIPS_PACRA, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 1282 | * |
mbed_official | 146:f64d43ff0c18 | 1283 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1284 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1285 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1286 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1287 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1288 | * |
mbed_official | 146:f64d43ff0c18 | 1289 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1290 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1291 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1292 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1293 | */ |
mbed_official | 146:f64d43ff0c18 | 1294 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1295 | #define BP_AIPS_PACRA_SP2 (22U) //!< Bit position for AIPS_PACRA_SP2. |
mbed_official | 146:f64d43ff0c18 | 1296 | #define BM_AIPS_PACRA_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRA_SP2. |
mbed_official | 146:f64d43ff0c18 | 1297 | #define BS_AIPS_PACRA_SP2 (1U) //!< Bit field size in bits for AIPS_PACRA_SP2. |
mbed_official | 146:f64d43ff0c18 | 1298 | |
mbed_official | 146:f64d43ff0c18 | 1299 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1300 | //! @brief Read current value of the AIPS_PACRA_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 1301 | #define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2)) |
mbed_official | 146:f64d43ff0c18 | 1302 | #endif |
mbed_official | 146:f64d43ff0c18 | 1303 | |
mbed_official | 146:f64d43ff0c18 | 1304 | //! @brief Format value for bitfield AIPS_PACRA_SP2. |
mbed_official | 146:f64d43ff0c18 | 1305 | #define BF_AIPS_PACRA_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP2), uint32_t) & BM_AIPS_PACRA_SP2) |
mbed_official | 146:f64d43ff0c18 | 1306 | |
mbed_official | 146:f64d43ff0c18 | 1307 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1308 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1309 | #define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1310 | #endif |
mbed_official | 146:f64d43ff0c18 | 1311 | //@} |
mbed_official | 146:f64d43ff0c18 | 1312 | |
mbed_official | 146:f64d43ff0c18 | 1313 | /*! |
mbed_official | 146:f64d43ff0c18 | 1314 | * @name Register AIPS_PACRA, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 1315 | * |
mbed_official | 146:f64d43ff0c18 | 1316 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1317 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1318 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1319 | * |
mbed_official | 146:f64d43ff0c18 | 1320 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1321 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1322 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1323 | */ |
mbed_official | 146:f64d43ff0c18 | 1324 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1325 | #define BP_AIPS_PACRA_TP1 (24U) //!< Bit position for AIPS_PACRA_TP1. |
mbed_official | 146:f64d43ff0c18 | 1326 | #define BM_AIPS_PACRA_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRA_TP1. |
mbed_official | 146:f64d43ff0c18 | 1327 | #define BS_AIPS_PACRA_TP1 (1U) //!< Bit field size in bits for AIPS_PACRA_TP1. |
mbed_official | 146:f64d43ff0c18 | 1328 | |
mbed_official | 146:f64d43ff0c18 | 1329 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1330 | //! @brief Read current value of the AIPS_PACRA_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 1331 | #define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1)) |
mbed_official | 146:f64d43ff0c18 | 1332 | #endif |
mbed_official | 146:f64d43ff0c18 | 1333 | |
mbed_official | 146:f64d43ff0c18 | 1334 | //! @brief Format value for bitfield AIPS_PACRA_TP1. |
mbed_official | 146:f64d43ff0c18 | 1335 | #define BF_AIPS_PACRA_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP1), uint32_t) & BM_AIPS_PACRA_TP1) |
mbed_official | 146:f64d43ff0c18 | 1336 | |
mbed_official | 146:f64d43ff0c18 | 1337 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1338 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1339 | #define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1340 | #endif |
mbed_official | 146:f64d43ff0c18 | 1341 | //@} |
mbed_official | 146:f64d43ff0c18 | 1342 | |
mbed_official | 146:f64d43ff0c18 | 1343 | /*! |
mbed_official | 146:f64d43ff0c18 | 1344 | * @name Register AIPS_PACRA, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 1345 | * |
mbed_official | 146:f64d43ff0c18 | 1346 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 1347 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 1348 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1349 | * |
mbed_official | 146:f64d43ff0c18 | 1350 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1351 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1352 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1353 | */ |
mbed_official | 146:f64d43ff0c18 | 1354 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1355 | #define BP_AIPS_PACRA_WP1 (25U) //!< Bit position for AIPS_PACRA_WP1. |
mbed_official | 146:f64d43ff0c18 | 1356 | #define BM_AIPS_PACRA_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRA_WP1. |
mbed_official | 146:f64d43ff0c18 | 1357 | #define BS_AIPS_PACRA_WP1 (1U) //!< Bit field size in bits for AIPS_PACRA_WP1. |
mbed_official | 146:f64d43ff0c18 | 1358 | |
mbed_official | 146:f64d43ff0c18 | 1359 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1360 | //! @brief Read current value of the AIPS_PACRA_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 1361 | #define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1)) |
mbed_official | 146:f64d43ff0c18 | 1362 | #endif |
mbed_official | 146:f64d43ff0c18 | 1363 | |
mbed_official | 146:f64d43ff0c18 | 1364 | //! @brief Format value for bitfield AIPS_PACRA_WP1. |
mbed_official | 146:f64d43ff0c18 | 1365 | #define BF_AIPS_PACRA_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP1), uint32_t) & BM_AIPS_PACRA_WP1) |
mbed_official | 146:f64d43ff0c18 | 1366 | |
mbed_official | 146:f64d43ff0c18 | 1367 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1368 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1369 | #define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1370 | #endif |
mbed_official | 146:f64d43ff0c18 | 1371 | //@} |
mbed_official | 146:f64d43ff0c18 | 1372 | |
mbed_official | 146:f64d43ff0c18 | 1373 | /*! |
mbed_official | 146:f64d43ff0c18 | 1374 | * @name Register AIPS_PACRA, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 1375 | * |
mbed_official | 146:f64d43ff0c18 | 1376 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1377 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1378 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1379 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1380 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1381 | * |
mbed_official | 146:f64d43ff0c18 | 1382 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1383 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1384 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1385 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1386 | */ |
mbed_official | 146:f64d43ff0c18 | 1387 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1388 | #define BP_AIPS_PACRA_SP1 (26U) //!< Bit position for AIPS_PACRA_SP1. |
mbed_official | 146:f64d43ff0c18 | 1389 | #define BM_AIPS_PACRA_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRA_SP1. |
mbed_official | 146:f64d43ff0c18 | 1390 | #define BS_AIPS_PACRA_SP1 (1U) //!< Bit field size in bits for AIPS_PACRA_SP1. |
mbed_official | 146:f64d43ff0c18 | 1391 | |
mbed_official | 146:f64d43ff0c18 | 1392 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1393 | //! @brief Read current value of the AIPS_PACRA_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 1394 | #define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1)) |
mbed_official | 146:f64d43ff0c18 | 1395 | #endif |
mbed_official | 146:f64d43ff0c18 | 1396 | |
mbed_official | 146:f64d43ff0c18 | 1397 | //! @brief Format value for bitfield AIPS_PACRA_SP1. |
mbed_official | 146:f64d43ff0c18 | 1398 | #define BF_AIPS_PACRA_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP1), uint32_t) & BM_AIPS_PACRA_SP1) |
mbed_official | 146:f64d43ff0c18 | 1399 | |
mbed_official | 146:f64d43ff0c18 | 1400 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1401 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1402 | #define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1403 | #endif |
mbed_official | 146:f64d43ff0c18 | 1404 | //@} |
mbed_official | 146:f64d43ff0c18 | 1405 | |
mbed_official | 146:f64d43ff0c18 | 1406 | /*! |
mbed_official | 146:f64d43ff0c18 | 1407 | * @name Register AIPS_PACRA, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 1408 | * |
mbed_official | 146:f64d43ff0c18 | 1409 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1410 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1411 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1412 | * |
mbed_official | 146:f64d43ff0c18 | 1413 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1414 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1415 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1416 | */ |
mbed_official | 146:f64d43ff0c18 | 1417 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1418 | #define BP_AIPS_PACRA_TP0 (28U) //!< Bit position for AIPS_PACRA_TP0. |
mbed_official | 146:f64d43ff0c18 | 1419 | #define BM_AIPS_PACRA_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRA_TP0. |
mbed_official | 146:f64d43ff0c18 | 1420 | #define BS_AIPS_PACRA_TP0 (1U) //!< Bit field size in bits for AIPS_PACRA_TP0. |
mbed_official | 146:f64d43ff0c18 | 1421 | |
mbed_official | 146:f64d43ff0c18 | 1422 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1423 | //! @brief Read current value of the AIPS_PACRA_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 1424 | #define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0)) |
mbed_official | 146:f64d43ff0c18 | 1425 | #endif |
mbed_official | 146:f64d43ff0c18 | 1426 | |
mbed_official | 146:f64d43ff0c18 | 1427 | //! @brief Format value for bitfield AIPS_PACRA_TP0. |
mbed_official | 146:f64d43ff0c18 | 1428 | #define BF_AIPS_PACRA_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP0), uint32_t) & BM_AIPS_PACRA_TP0) |
mbed_official | 146:f64d43ff0c18 | 1429 | |
mbed_official | 146:f64d43ff0c18 | 1430 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1431 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1432 | #define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1433 | #endif |
mbed_official | 146:f64d43ff0c18 | 1434 | //@} |
mbed_official | 146:f64d43ff0c18 | 1435 | |
mbed_official | 146:f64d43ff0c18 | 1436 | /*! |
mbed_official | 146:f64d43ff0c18 | 1437 | * @name Register AIPS_PACRA, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 1438 | * |
mbed_official | 146:f64d43ff0c18 | 1439 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 1440 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 1441 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1442 | * |
mbed_official | 146:f64d43ff0c18 | 1443 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1444 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1445 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1446 | */ |
mbed_official | 146:f64d43ff0c18 | 1447 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1448 | #define BP_AIPS_PACRA_WP0 (29U) //!< Bit position for AIPS_PACRA_WP0. |
mbed_official | 146:f64d43ff0c18 | 1449 | #define BM_AIPS_PACRA_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRA_WP0. |
mbed_official | 146:f64d43ff0c18 | 1450 | #define BS_AIPS_PACRA_WP0 (1U) //!< Bit field size in bits for AIPS_PACRA_WP0. |
mbed_official | 146:f64d43ff0c18 | 1451 | |
mbed_official | 146:f64d43ff0c18 | 1452 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1453 | //! @brief Read current value of the AIPS_PACRA_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 1454 | #define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0)) |
mbed_official | 146:f64d43ff0c18 | 1455 | #endif |
mbed_official | 146:f64d43ff0c18 | 1456 | |
mbed_official | 146:f64d43ff0c18 | 1457 | //! @brief Format value for bitfield AIPS_PACRA_WP0. |
mbed_official | 146:f64d43ff0c18 | 1458 | #define BF_AIPS_PACRA_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP0), uint32_t) & BM_AIPS_PACRA_WP0) |
mbed_official | 146:f64d43ff0c18 | 1459 | |
mbed_official | 146:f64d43ff0c18 | 1460 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1461 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1462 | #define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1463 | #endif |
mbed_official | 146:f64d43ff0c18 | 1464 | //@} |
mbed_official | 146:f64d43ff0c18 | 1465 | |
mbed_official | 146:f64d43ff0c18 | 1466 | /*! |
mbed_official | 146:f64d43ff0c18 | 1467 | * @name Register AIPS_PACRA, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 1468 | * |
mbed_official | 146:f64d43ff0c18 | 1469 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1470 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1471 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1472 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1473 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1474 | * |
mbed_official | 146:f64d43ff0c18 | 1475 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1476 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1477 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1478 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1479 | */ |
mbed_official | 146:f64d43ff0c18 | 1480 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1481 | #define BP_AIPS_PACRA_SP0 (30U) //!< Bit position for AIPS_PACRA_SP0. |
mbed_official | 146:f64d43ff0c18 | 1482 | #define BM_AIPS_PACRA_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRA_SP0. |
mbed_official | 146:f64d43ff0c18 | 1483 | #define BS_AIPS_PACRA_SP0 (1U) //!< Bit field size in bits for AIPS_PACRA_SP0. |
mbed_official | 146:f64d43ff0c18 | 1484 | |
mbed_official | 146:f64d43ff0c18 | 1485 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1486 | //! @brief Read current value of the AIPS_PACRA_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 1487 | #define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0)) |
mbed_official | 146:f64d43ff0c18 | 1488 | #endif |
mbed_official | 146:f64d43ff0c18 | 1489 | |
mbed_official | 146:f64d43ff0c18 | 1490 | //! @brief Format value for bitfield AIPS_PACRA_SP0. |
mbed_official | 146:f64d43ff0c18 | 1491 | #define BF_AIPS_PACRA_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP0), uint32_t) & BM_AIPS_PACRA_SP0) |
mbed_official | 146:f64d43ff0c18 | 1492 | |
mbed_official | 146:f64d43ff0c18 | 1493 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1494 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1495 | #define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1496 | #endif |
mbed_official | 146:f64d43ff0c18 | 1497 | //@} |
mbed_official | 146:f64d43ff0c18 | 1498 | |
mbed_official | 146:f64d43ff0c18 | 1499 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1500 | // HW_AIPS_PACRB - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 1501 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1502 | |
mbed_official | 146:f64d43ff0c18 | 1503 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1504 | /*! |
mbed_official | 146:f64d43ff0c18 | 1505 | * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1506 | * |
mbed_official | 146:f64d43ff0c18 | 1507 | * Reset value: 0x44004400U |
mbed_official | 146:f64d43ff0c18 | 1508 | * |
mbed_official | 146:f64d43ff0c18 | 1509 | * Each PACR register consists of eight 4-bit PACR fields. Each PACR field |
mbed_official | 146:f64d43ff0c18 | 1510 | * defines the access levels for a particular peripheral. The mapping between a |
mbed_official | 146:f64d43ff0c18 | 1511 | * peripheral and its PACR field is shown in the table below. The peripheral assignment |
mbed_official | 146:f64d43ff0c18 | 1512 | * to each PACR is defined by the memory map slot that the peripheral is |
mbed_official | 146:f64d43ff0c18 | 1513 | * assigned to. See this chip's memory map for the assignment of a particular |
mbed_official | 146:f64d43ff0c18 | 1514 | * peripheral. The following table shows the location of each peripheral slot's PACR field |
mbed_official | 146:f64d43ff0c18 | 1515 | * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] |
mbed_official | 146:f64d43ff0c18 | 1516 | * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 |
mbed_official | 146:f64d43ff0c18 | 1517 | * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC |
mbed_official | 146:f64d43ff0c18 | 1518 | * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 |
mbed_official | 146:f64d43ff0c18 | 1519 | * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 |
mbed_official | 146:f64d43ff0c18 | 1520 | * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 |
mbed_official | 146:f64d43ff0c18 | 1521 | * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 |
mbed_official | 146:f64d43ff0c18 | 1522 | * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH |
mbed_official | 146:f64d43ff0c18 | 1523 | * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 |
mbed_official | 146:f64d43ff0c18 | 1524 | * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 |
mbed_official | 146:f64d43ff0c18 | 1525 | * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 |
mbed_official | 146:f64d43ff0c18 | 1526 | * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 |
mbed_official | 146:f64d43ff0c18 | 1527 | * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 |
mbed_official | 146:f64d43ff0c18 | 1528 | * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 |
mbed_official | 146:f64d43ff0c18 | 1529 | * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 |
mbed_official | 146:f64d43ff0c18 | 1530 | * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 |
mbed_official | 146:f64d43ff0c18 | 1531 | * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR |
mbed_official | 146:f64d43ff0c18 | 1532 | * A-D, which control peripheral slots 0-31, are shown below. The following |
mbed_official | 146:f64d43ff0c18 | 1533 | * section, PACRPeripheral Access Control Register , shows the register field |
mbed_official | 146:f64d43ff0c18 | 1534 | * descriptions for PACR E-P. All PACR registers are identical. They are divided into two |
mbed_official | 146:f64d43ff0c18 | 1535 | * sections because they occupy two non-contiguous address spaces. |
mbed_official | 146:f64d43ff0c18 | 1536 | */ |
mbed_official | 146:f64d43ff0c18 | 1537 | typedef union _hw_aips_pacrb |
mbed_official | 146:f64d43ff0c18 | 1538 | { |
mbed_official | 146:f64d43ff0c18 | 1539 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1540 | struct _hw_aips_pacrb_bitfields |
mbed_official | 146:f64d43ff0c18 | 1541 | { |
mbed_official | 146:f64d43ff0c18 | 1542 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1543 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1544 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1545 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 1546 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1547 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1548 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1549 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 1550 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1551 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1552 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1553 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 1554 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1555 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1556 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1557 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 1558 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1559 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1560 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1561 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 1562 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1563 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1564 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1565 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 1566 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1567 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1568 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1569 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 1570 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 1571 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 1572 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 1573 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 1574 | } B; |
mbed_official | 146:f64d43ff0c18 | 1575 | } hw_aips_pacrb_t; |
mbed_official | 146:f64d43ff0c18 | 1576 | #endif |
mbed_official | 146:f64d43ff0c18 | 1577 | |
mbed_official | 146:f64d43ff0c18 | 1578 | /*! |
mbed_official | 146:f64d43ff0c18 | 1579 | * @name Constants and macros for entire AIPS_PACRB register |
mbed_official | 146:f64d43ff0c18 | 1580 | */ |
mbed_official | 146:f64d43ff0c18 | 1581 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1582 | #define HW_AIPS_PACRB_ADDR(x) (REGS_AIPS_BASE(x) + 0x24U) |
mbed_official | 146:f64d43ff0c18 | 1583 | |
mbed_official | 146:f64d43ff0c18 | 1584 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1585 | #define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 1586 | #define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U) |
mbed_official | 146:f64d43ff0c18 | 1587 | #define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1588 | #define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1589 | #define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1590 | #define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1591 | #endif |
mbed_official | 146:f64d43ff0c18 | 1592 | //@} |
mbed_official | 146:f64d43ff0c18 | 1593 | |
mbed_official | 146:f64d43ff0c18 | 1594 | /* |
mbed_official | 146:f64d43ff0c18 | 1595 | * Constants & macros for individual AIPS_PACRB bitfields |
mbed_official | 146:f64d43ff0c18 | 1596 | */ |
mbed_official | 146:f64d43ff0c18 | 1597 | |
mbed_official | 146:f64d43ff0c18 | 1598 | /*! |
mbed_official | 146:f64d43ff0c18 | 1599 | * @name Register AIPS_PACRB, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1600 | * |
mbed_official | 146:f64d43ff0c18 | 1601 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1602 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1603 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1604 | * |
mbed_official | 146:f64d43ff0c18 | 1605 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1606 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1607 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1608 | */ |
mbed_official | 146:f64d43ff0c18 | 1609 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1610 | #define BP_AIPS_PACRB_TP7 (0U) //!< Bit position for AIPS_PACRB_TP7. |
mbed_official | 146:f64d43ff0c18 | 1611 | #define BM_AIPS_PACRB_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRB_TP7. |
mbed_official | 146:f64d43ff0c18 | 1612 | #define BS_AIPS_PACRB_TP7 (1U) //!< Bit field size in bits for AIPS_PACRB_TP7. |
mbed_official | 146:f64d43ff0c18 | 1613 | |
mbed_official | 146:f64d43ff0c18 | 1614 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1615 | //! @brief Read current value of the AIPS_PACRB_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 1616 | #define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7)) |
mbed_official | 146:f64d43ff0c18 | 1617 | #endif |
mbed_official | 146:f64d43ff0c18 | 1618 | |
mbed_official | 146:f64d43ff0c18 | 1619 | //! @brief Format value for bitfield AIPS_PACRB_TP7. |
mbed_official | 146:f64d43ff0c18 | 1620 | #define BF_AIPS_PACRB_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP7), uint32_t) & BM_AIPS_PACRB_TP7) |
mbed_official | 146:f64d43ff0c18 | 1621 | |
mbed_official | 146:f64d43ff0c18 | 1622 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1623 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1624 | #define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1625 | #endif |
mbed_official | 146:f64d43ff0c18 | 1626 | //@} |
mbed_official | 146:f64d43ff0c18 | 1627 | |
mbed_official | 146:f64d43ff0c18 | 1628 | /*! |
mbed_official | 146:f64d43ff0c18 | 1629 | * @name Register AIPS_PACRB, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1630 | * |
mbed_official | 146:f64d43ff0c18 | 1631 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 1632 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 1633 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1634 | * |
mbed_official | 146:f64d43ff0c18 | 1635 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1636 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1637 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1638 | */ |
mbed_official | 146:f64d43ff0c18 | 1639 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1640 | #define BP_AIPS_PACRB_WP7 (1U) //!< Bit position for AIPS_PACRB_WP7. |
mbed_official | 146:f64d43ff0c18 | 1641 | #define BM_AIPS_PACRB_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRB_WP7. |
mbed_official | 146:f64d43ff0c18 | 1642 | #define BS_AIPS_PACRB_WP7 (1U) //!< Bit field size in bits for AIPS_PACRB_WP7. |
mbed_official | 146:f64d43ff0c18 | 1643 | |
mbed_official | 146:f64d43ff0c18 | 1644 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1645 | //! @brief Read current value of the AIPS_PACRB_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 1646 | #define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7)) |
mbed_official | 146:f64d43ff0c18 | 1647 | #endif |
mbed_official | 146:f64d43ff0c18 | 1648 | |
mbed_official | 146:f64d43ff0c18 | 1649 | //! @brief Format value for bitfield AIPS_PACRB_WP7. |
mbed_official | 146:f64d43ff0c18 | 1650 | #define BF_AIPS_PACRB_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP7), uint32_t) & BM_AIPS_PACRB_WP7) |
mbed_official | 146:f64d43ff0c18 | 1651 | |
mbed_official | 146:f64d43ff0c18 | 1652 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1653 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1654 | #define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1655 | #endif |
mbed_official | 146:f64d43ff0c18 | 1656 | //@} |
mbed_official | 146:f64d43ff0c18 | 1657 | |
mbed_official | 146:f64d43ff0c18 | 1658 | /*! |
mbed_official | 146:f64d43ff0c18 | 1659 | * @name Register AIPS_PACRB, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1660 | * |
mbed_official | 146:f64d43ff0c18 | 1661 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1662 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1663 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1664 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1665 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1666 | * |
mbed_official | 146:f64d43ff0c18 | 1667 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1668 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1669 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1670 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1671 | */ |
mbed_official | 146:f64d43ff0c18 | 1672 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1673 | #define BP_AIPS_PACRB_SP7 (2U) //!< Bit position for AIPS_PACRB_SP7. |
mbed_official | 146:f64d43ff0c18 | 1674 | #define BM_AIPS_PACRB_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRB_SP7. |
mbed_official | 146:f64d43ff0c18 | 1675 | #define BS_AIPS_PACRB_SP7 (1U) //!< Bit field size in bits for AIPS_PACRB_SP7. |
mbed_official | 146:f64d43ff0c18 | 1676 | |
mbed_official | 146:f64d43ff0c18 | 1677 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1678 | //! @brief Read current value of the AIPS_PACRB_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 1679 | #define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7)) |
mbed_official | 146:f64d43ff0c18 | 1680 | #endif |
mbed_official | 146:f64d43ff0c18 | 1681 | |
mbed_official | 146:f64d43ff0c18 | 1682 | //! @brief Format value for bitfield AIPS_PACRB_SP7. |
mbed_official | 146:f64d43ff0c18 | 1683 | #define BF_AIPS_PACRB_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP7), uint32_t) & BM_AIPS_PACRB_SP7) |
mbed_official | 146:f64d43ff0c18 | 1684 | |
mbed_official | 146:f64d43ff0c18 | 1685 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1686 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1687 | #define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1688 | #endif |
mbed_official | 146:f64d43ff0c18 | 1689 | //@} |
mbed_official | 146:f64d43ff0c18 | 1690 | |
mbed_official | 146:f64d43ff0c18 | 1691 | /*! |
mbed_official | 146:f64d43ff0c18 | 1692 | * @name Register AIPS_PACRB, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1693 | * |
mbed_official | 146:f64d43ff0c18 | 1694 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1695 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1696 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1697 | * |
mbed_official | 146:f64d43ff0c18 | 1698 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1699 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1700 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1701 | */ |
mbed_official | 146:f64d43ff0c18 | 1702 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1703 | #define BP_AIPS_PACRB_TP6 (4U) //!< Bit position for AIPS_PACRB_TP6. |
mbed_official | 146:f64d43ff0c18 | 1704 | #define BM_AIPS_PACRB_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRB_TP6. |
mbed_official | 146:f64d43ff0c18 | 1705 | #define BS_AIPS_PACRB_TP6 (1U) //!< Bit field size in bits for AIPS_PACRB_TP6. |
mbed_official | 146:f64d43ff0c18 | 1706 | |
mbed_official | 146:f64d43ff0c18 | 1707 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1708 | //! @brief Read current value of the AIPS_PACRB_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 1709 | #define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6)) |
mbed_official | 146:f64d43ff0c18 | 1710 | #endif |
mbed_official | 146:f64d43ff0c18 | 1711 | |
mbed_official | 146:f64d43ff0c18 | 1712 | //! @brief Format value for bitfield AIPS_PACRB_TP6. |
mbed_official | 146:f64d43ff0c18 | 1713 | #define BF_AIPS_PACRB_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP6), uint32_t) & BM_AIPS_PACRB_TP6) |
mbed_official | 146:f64d43ff0c18 | 1714 | |
mbed_official | 146:f64d43ff0c18 | 1715 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1716 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1717 | #define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1718 | #endif |
mbed_official | 146:f64d43ff0c18 | 1719 | //@} |
mbed_official | 146:f64d43ff0c18 | 1720 | |
mbed_official | 146:f64d43ff0c18 | 1721 | /*! |
mbed_official | 146:f64d43ff0c18 | 1722 | * @name Register AIPS_PACRB, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1723 | * |
mbed_official | 146:f64d43ff0c18 | 1724 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 1725 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 1726 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1727 | * |
mbed_official | 146:f64d43ff0c18 | 1728 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1729 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1730 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1731 | */ |
mbed_official | 146:f64d43ff0c18 | 1732 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1733 | #define BP_AIPS_PACRB_WP6 (5U) //!< Bit position for AIPS_PACRB_WP6. |
mbed_official | 146:f64d43ff0c18 | 1734 | #define BM_AIPS_PACRB_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRB_WP6. |
mbed_official | 146:f64d43ff0c18 | 1735 | #define BS_AIPS_PACRB_WP6 (1U) //!< Bit field size in bits for AIPS_PACRB_WP6. |
mbed_official | 146:f64d43ff0c18 | 1736 | |
mbed_official | 146:f64d43ff0c18 | 1737 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1738 | //! @brief Read current value of the AIPS_PACRB_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 1739 | #define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6)) |
mbed_official | 146:f64d43ff0c18 | 1740 | #endif |
mbed_official | 146:f64d43ff0c18 | 1741 | |
mbed_official | 146:f64d43ff0c18 | 1742 | //! @brief Format value for bitfield AIPS_PACRB_WP6. |
mbed_official | 146:f64d43ff0c18 | 1743 | #define BF_AIPS_PACRB_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP6), uint32_t) & BM_AIPS_PACRB_WP6) |
mbed_official | 146:f64d43ff0c18 | 1744 | |
mbed_official | 146:f64d43ff0c18 | 1745 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1746 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1747 | #define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1748 | #endif |
mbed_official | 146:f64d43ff0c18 | 1749 | //@} |
mbed_official | 146:f64d43ff0c18 | 1750 | |
mbed_official | 146:f64d43ff0c18 | 1751 | /*! |
mbed_official | 146:f64d43ff0c18 | 1752 | * @name Register AIPS_PACRB, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1753 | * |
mbed_official | 146:f64d43ff0c18 | 1754 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1755 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1756 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1757 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1758 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1759 | * |
mbed_official | 146:f64d43ff0c18 | 1760 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1761 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1762 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1763 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1764 | */ |
mbed_official | 146:f64d43ff0c18 | 1765 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1766 | #define BP_AIPS_PACRB_SP6 (6U) //!< Bit position for AIPS_PACRB_SP6. |
mbed_official | 146:f64d43ff0c18 | 1767 | #define BM_AIPS_PACRB_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRB_SP6. |
mbed_official | 146:f64d43ff0c18 | 1768 | #define BS_AIPS_PACRB_SP6 (1U) //!< Bit field size in bits for AIPS_PACRB_SP6. |
mbed_official | 146:f64d43ff0c18 | 1769 | |
mbed_official | 146:f64d43ff0c18 | 1770 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1771 | //! @brief Read current value of the AIPS_PACRB_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 1772 | #define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6)) |
mbed_official | 146:f64d43ff0c18 | 1773 | #endif |
mbed_official | 146:f64d43ff0c18 | 1774 | |
mbed_official | 146:f64d43ff0c18 | 1775 | //! @brief Format value for bitfield AIPS_PACRB_SP6. |
mbed_official | 146:f64d43ff0c18 | 1776 | #define BF_AIPS_PACRB_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP6), uint32_t) & BM_AIPS_PACRB_SP6) |
mbed_official | 146:f64d43ff0c18 | 1777 | |
mbed_official | 146:f64d43ff0c18 | 1778 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1779 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1780 | #define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1781 | #endif |
mbed_official | 146:f64d43ff0c18 | 1782 | //@} |
mbed_official | 146:f64d43ff0c18 | 1783 | |
mbed_official | 146:f64d43ff0c18 | 1784 | /*! |
mbed_official | 146:f64d43ff0c18 | 1785 | * @name Register AIPS_PACRB, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 1786 | * |
mbed_official | 146:f64d43ff0c18 | 1787 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1788 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1789 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1790 | * |
mbed_official | 146:f64d43ff0c18 | 1791 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1792 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1793 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1794 | */ |
mbed_official | 146:f64d43ff0c18 | 1795 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1796 | #define BP_AIPS_PACRB_TP5 (8U) //!< Bit position for AIPS_PACRB_TP5. |
mbed_official | 146:f64d43ff0c18 | 1797 | #define BM_AIPS_PACRB_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRB_TP5. |
mbed_official | 146:f64d43ff0c18 | 1798 | #define BS_AIPS_PACRB_TP5 (1U) //!< Bit field size in bits for AIPS_PACRB_TP5. |
mbed_official | 146:f64d43ff0c18 | 1799 | |
mbed_official | 146:f64d43ff0c18 | 1800 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1801 | //! @brief Read current value of the AIPS_PACRB_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 1802 | #define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5)) |
mbed_official | 146:f64d43ff0c18 | 1803 | #endif |
mbed_official | 146:f64d43ff0c18 | 1804 | |
mbed_official | 146:f64d43ff0c18 | 1805 | //! @brief Format value for bitfield AIPS_PACRB_TP5. |
mbed_official | 146:f64d43ff0c18 | 1806 | #define BF_AIPS_PACRB_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP5), uint32_t) & BM_AIPS_PACRB_TP5) |
mbed_official | 146:f64d43ff0c18 | 1807 | |
mbed_official | 146:f64d43ff0c18 | 1808 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1809 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1810 | #define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1811 | #endif |
mbed_official | 146:f64d43ff0c18 | 1812 | //@} |
mbed_official | 146:f64d43ff0c18 | 1813 | |
mbed_official | 146:f64d43ff0c18 | 1814 | /*! |
mbed_official | 146:f64d43ff0c18 | 1815 | * @name Register AIPS_PACRB, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 1816 | * |
mbed_official | 146:f64d43ff0c18 | 1817 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 1818 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 1819 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1820 | * |
mbed_official | 146:f64d43ff0c18 | 1821 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1822 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1823 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1824 | */ |
mbed_official | 146:f64d43ff0c18 | 1825 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1826 | #define BP_AIPS_PACRB_WP5 (9U) //!< Bit position for AIPS_PACRB_WP5. |
mbed_official | 146:f64d43ff0c18 | 1827 | #define BM_AIPS_PACRB_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRB_WP5. |
mbed_official | 146:f64d43ff0c18 | 1828 | #define BS_AIPS_PACRB_WP5 (1U) //!< Bit field size in bits for AIPS_PACRB_WP5. |
mbed_official | 146:f64d43ff0c18 | 1829 | |
mbed_official | 146:f64d43ff0c18 | 1830 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1831 | //! @brief Read current value of the AIPS_PACRB_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 1832 | #define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5)) |
mbed_official | 146:f64d43ff0c18 | 1833 | #endif |
mbed_official | 146:f64d43ff0c18 | 1834 | |
mbed_official | 146:f64d43ff0c18 | 1835 | //! @brief Format value for bitfield AIPS_PACRB_WP5. |
mbed_official | 146:f64d43ff0c18 | 1836 | #define BF_AIPS_PACRB_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP5), uint32_t) & BM_AIPS_PACRB_WP5) |
mbed_official | 146:f64d43ff0c18 | 1837 | |
mbed_official | 146:f64d43ff0c18 | 1838 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1839 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1840 | #define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1841 | #endif |
mbed_official | 146:f64d43ff0c18 | 1842 | //@} |
mbed_official | 146:f64d43ff0c18 | 1843 | |
mbed_official | 146:f64d43ff0c18 | 1844 | /*! |
mbed_official | 146:f64d43ff0c18 | 1845 | * @name Register AIPS_PACRB, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 1846 | * |
mbed_official | 146:f64d43ff0c18 | 1847 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1848 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1849 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1850 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1851 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1852 | * |
mbed_official | 146:f64d43ff0c18 | 1853 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1854 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1855 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1856 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1857 | */ |
mbed_official | 146:f64d43ff0c18 | 1858 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1859 | #define BP_AIPS_PACRB_SP5 (10U) //!< Bit position for AIPS_PACRB_SP5. |
mbed_official | 146:f64d43ff0c18 | 1860 | #define BM_AIPS_PACRB_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRB_SP5. |
mbed_official | 146:f64d43ff0c18 | 1861 | #define BS_AIPS_PACRB_SP5 (1U) //!< Bit field size in bits for AIPS_PACRB_SP5. |
mbed_official | 146:f64d43ff0c18 | 1862 | |
mbed_official | 146:f64d43ff0c18 | 1863 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1864 | //! @brief Read current value of the AIPS_PACRB_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 1865 | #define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5)) |
mbed_official | 146:f64d43ff0c18 | 1866 | #endif |
mbed_official | 146:f64d43ff0c18 | 1867 | |
mbed_official | 146:f64d43ff0c18 | 1868 | //! @brief Format value for bitfield AIPS_PACRB_SP5. |
mbed_official | 146:f64d43ff0c18 | 1869 | #define BF_AIPS_PACRB_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP5), uint32_t) & BM_AIPS_PACRB_SP5) |
mbed_official | 146:f64d43ff0c18 | 1870 | |
mbed_official | 146:f64d43ff0c18 | 1871 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1872 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1873 | #define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1874 | #endif |
mbed_official | 146:f64d43ff0c18 | 1875 | //@} |
mbed_official | 146:f64d43ff0c18 | 1876 | |
mbed_official | 146:f64d43ff0c18 | 1877 | /*! |
mbed_official | 146:f64d43ff0c18 | 1878 | * @name Register AIPS_PACRB, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 1879 | * |
mbed_official | 146:f64d43ff0c18 | 1880 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1881 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1882 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1883 | * |
mbed_official | 146:f64d43ff0c18 | 1884 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1885 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1886 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1887 | */ |
mbed_official | 146:f64d43ff0c18 | 1888 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1889 | #define BP_AIPS_PACRB_TP4 (12U) //!< Bit position for AIPS_PACRB_TP4. |
mbed_official | 146:f64d43ff0c18 | 1890 | #define BM_AIPS_PACRB_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRB_TP4. |
mbed_official | 146:f64d43ff0c18 | 1891 | #define BS_AIPS_PACRB_TP4 (1U) //!< Bit field size in bits for AIPS_PACRB_TP4. |
mbed_official | 146:f64d43ff0c18 | 1892 | |
mbed_official | 146:f64d43ff0c18 | 1893 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1894 | //! @brief Read current value of the AIPS_PACRB_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 1895 | #define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4)) |
mbed_official | 146:f64d43ff0c18 | 1896 | #endif |
mbed_official | 146:f64d43ff0c18 | 1897 | |
mbed_official | 146:f64d43ff0c18 | 1898 | //! @brief Format value for bitfield AIPS_PACRB_TP4. |
mbed_official | 146:f64d43ff0c18 | 1899 | #define BF_AIPS_PACRB_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP4), uint32_t) & BM_AIPS_PACRB_TP4) |
mbed_official | 146:f64d43ff0c18 | 1900 | |
mbed_official | 146:f64d43ff0c18 | 1901 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1902 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1903 | #define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1904 | #endif |
mbed_official | 146:f64d43ff0c18 | 1905 | //@} |
mbed_official | 146:f64d43ff0c18 | 1906 | |
mbed_official | 146:f64d43ff0c18 | 1907 | /*! |
mbed_official | 146:f64d43ff0c18 | 1908 | * @name Register AIPS_PACRB, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 1909 | * |
mbed_official | 146:f64d43ff0c18 | 1910 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 1911 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 1912 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1913 | * |
mbed_official | 146:f64d43ff0c18 | 1914 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1915 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 1916 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 1917 | */ |
mbed_official | 146:f64d43ff0c18 | 1918 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1919 | #define BP_AIPS_PACRB_WP4 (13U) //!< Bit position for AIPS_PACRB_WP4. |
mbed_official | 146:f64d43ff0c18 | 1920 | #define BM_AIPS_PACRB_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRB_WP4. |
mbed_official | 146:f64d43ff0c18 | 1921 | #define BS_AIPS_PACRB_WP4 (1U) //!< Bit field size in bits for AIPS_PACRB_WP4. |
mbed_official | 146:f64d43ff0c18 | 1922 | |
mbed_official | 146:f64d43ff0c18 | 1923 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1924 | //! @brief Read current value of the AIPS_PACRB_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 1925 | #define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4)) |
mbed_official | 146:f64d43ff0c18 | 1926 | #endif |
mbed_official | 146:f64d43ff0c18 | 1927 | |
mbed_official | 146:f64d43ff0c18 | 1928 | //! @brief Format value for bitfield AIPS_PACRB_WP4. |
mbed_official | 146:f64d43ff0c18 | 1929 | #define BF_AIPS_PACRB_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP4), uint32_t) & BM_AIPS_PACRB_WP4) |
mbed_official | 146:f64d43ff0c18 | 1930 | |
mbed_official | 146:f64d43ff0c18 | 1931 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1932 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1933 | #define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1934 | #endif |
mbed_official | 146:f64d43ff0c18 | 1935 | //@} |
mbed_official | 146:f64d43ff0c18 | 1936 | |
mbed_official | 146:f64d43ff0c18 | 1937 | /*! |
mbed_official | 146:f64d43ff0c18 | 1938 | * @name Register AIPS_PACRB, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 1939 | * |
mbed_official | 146:f64d43ff0c18 | 1940 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1941 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 1942 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 1943 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 1944 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 1945 | * |
mbed_official | 146:f64d43ff0c18 | 1946 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1947 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 1948 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 1949 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 1950 | */ |
mbed_official | 146:f64d43ff0c18 | 1951 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1952 | #define BP_AIPS_PACRB_SP4 (14U) //!< Bit position for AIPS_PACRB_SP4. |
mbed_official | 146:f64d43ff0c18 | 1953 | #define BM_AIPS_PACRB_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRB_SP4. |
mbed_official | 146:f64d43ff0c18 | 1954 | #define BS_AIPS_PACRB_SP4 (1U) //!< Bit field size in bits for AIPS_PACRB_SP4. |
mbed_official | 146:f64d43ff0c18 | 1955 | |
mbed_official | 146:f64d43ff0c18 | 1956 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1957 | //! @brief Read current value of the AIPS_PACRB_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 1958 | #define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4)) |
mbed_official | 146:f64d43ff0c18 | 1959 | #endif |
mbed_official | 146:f64d43ff0c18 | 1960 | |
mbed_official | 146:f64d43ff0c18 | 1961 | //! @brief Format value for bitfield AIPS_PACRB_SP4. |
mbed_official | 146:f64d43ff0c18 | 1962 | #define BF_AIPS_PACRB_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP4), uint32_t) & BM_AIPS_PACRB_SP4) |
mbed_official | 146:f64d43ff0c18 | 1963 | |
mbed_official | 146:f64d43ff0c18 | 1964 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1965 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1966 | #define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1967 | #endif |
mbed_official | 146:f64d43ff0c18 | 1968 | //@} |
mbed_official | 146:f64d43ff0c18 | 1969 | |
mbed_official | 146:f64d43ff0c18 | 1970 | /*! |
mbed_official | 146:f64d43ff0c18 | 1971 | * @name Register AIPS_PACRB, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 1972 | * |
mbed_official | 146:f64d43ff0c18 | 1973 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 1974 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 1975 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 1976 | * |
mbed_official | 146:f64d43ff0c18 | 1977 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1978 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 1979 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 1980 | */ |
mbed_official | 146:f64d43ff0c18 | 1981 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1982 | #define BP_AIPS_PACRB_TP3 (16U) //!< Bit position for AIPS_PACRB_TP3. |
mbed_official | 146:f64d43ff0c18 | 1983 | #define BM_AIPS_PACRB_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRB_TP3. |
mbed_official | 146:f64d43ff0c18 | 1984 | #define BS_AIPS_PACRB_TP3 (1U) //!< Bit field size in bits for AIPS_PACRB_TP3. |
mbed_official | 146:f64d43ff0c18 | 1985 | |
mbed_official | 146:f64d43ff0c18 | 1986 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1987 | //! @brief Read current value of the AIPS_PACRB_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 1988 | #define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3)) |
mbed_official | 146:f64d43ff0c18 | 1989 | #endif |
mbed_official | 146:f64d43ff0c18 | 1990 | |
mbed_official | 146:f64d43ff0c18 | 1991 | //! @brief Format value for bitfield AIPS_PACRB_TP3. |
mbed_official | 146:f64d43ff0c18 | 1992 | #define BF_AIPS_PACRB_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP3), uint32_t) & BM_AIPS_PACRB_TP3) |
mbed_official | 146:f64d43ff0c18 | 1993 | |
mbed_official | 146:f64d43ff0c18 | 1994 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1995 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1996 | #define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1997 | #endif |
mbed_official | 146:f64d43ff0c18 | 1998 | //@} |
mbed_official | 146:f64d43ff0c18 | 1999 | |
mbed_official | 146:f64d43ff0c18 | 2000 | /*! |
mbed_official | 146:f64d43ff0c18 | 2001 | * @name Register AIPS_PACRB, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 2002 | * |
mbed_official | 146:f64d43ff0c18 | 2003 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 2004 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 2005 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2006 | * |
mbed_official | 146:f64d43ff0c18 | 2007 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2008 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2009 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2010 | */ |
mbed_official | 146:f64d43ff0c18 | 2011 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2012 | #define BP_AIPS_PACRB_WP3 (17U) //!< Bit position for AIPS_PACRB_WP3. |
mbed_official | 146:f64d43ff0c18 | 2013 | #define BM_AIPS_PACRB_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRB_WP3. |
mbed_official | 146:f64d43ff0c18 | 2014 | #define BS_AIPS_PACRB_WP3 (1U) //!< Bit field size in bits for AIPS_PACRB_WP3. |
mbed_official | 146:f64d43ff0c18 | 2015 | |
mbed_official | 146:f64d43ff0c18 | 2016 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2017 | //! @brief Read current value of the AIPS_PACRB_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 2018 | #define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3)) |
mbed_official | 146:f64d43ff0c18 | 2019 | #endif |
mbed_official | 146:f64d43ff0c18 | 2020 | |
mbed_official | 146:f64d43ff0c18 | 2021 | //! @brief Format value for bitfield AIPS_PACRB_WP3. |
mbed_official | 146:f64d43ff0c18 | 2022 | #define BF_AIPS_PACRB_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP3), uint32_t) & BM_AIPS_PACRB_WP3) |
mbed_official | 146:f64d43ff0c18 | 2023 | |
mbed_official | 146:f64d43ff0c18 | 2024 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2025 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2026 | #define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2027 | #endif |
mbed_official | 146:f64d43ff0c18 | 2028 | //@} |
mbed_official | 146:f64d43ff0c18 | 2029 | |
mbed_official | 146:f64d43ff0c18 | 2030 | /*! |
mbed_official | 146:f64d43ff0c18 | 2031 | * @name Register AIPS_PACRB, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 2032 | * |
mbed_official | 146:f64d43ff0c18 | 2033 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2034 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2035 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 2036 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 2037 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 2038 | * |
mbed_official | 146:f64d43ff0c18 | 2039 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2040 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2041 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2042 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2043 | */ |
mbed_official | 146:f64d43ff0c18 | 2044 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2045 | #define BP_AIPS_PACRB_SP3 (18U) //!< Bit position for AIPS_PACRB_SP3. |
mbed_official | 146:f64d43ff0c18 | 2046 | #define BM_AIPS_PACRB_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRB_SP3. |
mbed_official | 146:f64d43ff0c18 | 2047 | #define BS_AIPS_PACRB_SP3 (1U) //!< Bit field size in bits for AIPS_PACRB_SP3. |
mbed_official | 146:f64d43ff0c18 | 2048 | |
mbed_official | 146:f64d43ff0c18 | 2049 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2050 | //! @brief Read current value of the AIPS_PACRB_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 2051 | #define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3)) |
mbed_official | 146:f64d43ff0c18 | 2052 | #endif |
mbed_official | 146:f64d43ff0c18 | 2053 | |
mbed_official | 146:f64d43ff0c18 | 2054 | //! @brief Format value for bitfield AIPS_PACRB_SP3. |
mbed_official | 146:f64d43ff0c18 | 2055 | #define BF_AIPS_PACRB_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP3), uint32_t) & BM_AIPS_PACRB_SP3) |
mbed_official | 146:f64d43ff0c18 | 2056 | |
mbed_official | 146:f64d43ff0c18 | 2057 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2058 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2059 | #define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2060 | #endif |
mbed_official | 146:f64d43ff0c18 | 2061 | //@} |
mbed_official | 146:f64d43ff0c18 | 2062 | |
mbed_official | 146:f64d43ff0c18 | 2063 | /*! |
mbed_official | 146:f64d43ff0c18 | 2064 | * @name Register AIPS_PACRB, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 2065 | * |
mbed_official | 146:f64d43ff0c18 | 2066 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2067 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2068 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2069 | * |
mbed_official | 146:f64d43ff0c18 | 2070 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2071 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2072 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2073 | */ |
mbed_official | 146:f64d43ff0c18 | 2074 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2075 | #define BP_AIPS_PACRB_TP2 (20U) //!< Bit position for AIPS_PACRB_TP2. |
mbed_official | 146:f64d43ff0c18 | 2076 | #define BM_AIPS_PACRB_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRB_TP2. |
mbed_official | 146:f64d43ff0c18 | 2077 | #define BS_AIPS_PACRB_TP2 (1U) //!< Bit field size in bits for AIPS_PACRB_TP2. |
mbed_official | 146:f64d43ff0c18 | 2078 | |
mbed_official | 146:f64d43ff0c18 | 2079 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2080 | //! @brief Read current value of the AIPS_PACRB_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 2081 | #define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2)) |
mbed_official | 146:f64d43ff0c18 | 2082 | #endif |
mbed_official | 146:f64d43ff0c18 | 2083 | |
mbed_official | 146:f64d43ff0c18 | 2084 | //! @brief Format value for bitfield AIPS_PACRB_TP2. |
mbed_official | 146:f64d43ff0c18 | 2085 | #define BF_AIPS_PACRB_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP2), uint32_t) & BM_AIPS_PACRB_TP2) |
mbed_official | 146:f64d43ff0c18 | 2086 | |
mbed_official | 146:f64d43ff0c18 | 2087 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2088 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2089 | #define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2090 | #endif |
mbed_official | 146:f64d43ff0c18 | 2091 | //@} |
mbed_official | 146:f64d43ff0c18 | 2092 | |
mbed_official | 146:f64d43ff0c18 | 2093 | /*! |
mbed_official | 146:f64d43ff0c18 | 2094 | * @name Register AIPS_PACRB, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 2095 | * |
mbed_official | 146:f64d43ff0c18 | 2096 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 2097 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 2098 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2099 | * |
mbed_official | 146:f64d43ff0c18 | 2100 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2101 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2102 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2103 | */ |
mbed_official | 146:f64d43ff0c18 | 2104 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2105 | #define BP_AIPS_PACRB_WP2 (21U) //!< Bit position for AIPS_PACRB_WP2. |
mbed_official | 146:f64d43ff0c18 | 2106 | #define BM_AIPS_PACRB_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRB_WP2. |
mbed_official | 146:f64d43ff0c18 | 2107 | #define BS_AIPS_PACRB_WP2 (1U) //!< Bit field size in bits for AIPS_PACRB_WP2. |
mbed_official | 146:f64d43ff0c18 | 2108 | |
mbed_official | 146:f64d43ff0c18 | 2109 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2110 | //! @brief Read current value of the AIPS_PACRB_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 2111 | #define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2)) |
mbed_official | 146:f64d43ff0c18 | 2112 | #endif |
mbed_official | 146:f64d43ff0c18 | 2113 | |
mbed_official | 146:f64d43ff0c18 | 2114 | //! @brief Format value for bitfield AIPS_PACRB_WP2. |
mbed_official | 146:f64d43ff0c18 | 2115 | #define BF_AIPS_PACRB_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP2), uint32_t) & BM_AIPS_PACRB_WP2) |
mbed_official | 146:f64d43ff0c18 | 2116 | |
mbed_official | 146:f64d43ff0c18 | 2117 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2118 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2119 | #define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2120 | #endif |
mbed_official | 146:f64d43ff0c18 | 2121 | //@} |
mbed_official | 146:f64d43ff0c18 | 2122 | |
mbed_official | 146:f64d43ff0c18 | 2123 | /*! |
mbed_official | 146:f64d43ff0c18 | 2124 | * @name Register AIPS_PACRB, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 2125 | * |
mbed_official | 146:f64d43ff0c18 | 2126 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2127 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2128 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2129 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2130 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2131 | * |
mbed_official | 146:f64d43ff0c18 | 2132 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2133 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2134 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2135 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2136 | */ |
mbed_official | 146:f64d43ff0c18 | 2137 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2138 | #define BP_AIPS_PACRB_SP2 (22U) //!< Bit position for AIPS_PACRB_SP2. |
mbed_official | 146:f64d43ff0c18 | 2139 | #define BM_AIPS_PACRB_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRB_SP2. |
mbed_official | 146:f64d43ff0c18 | 2140 | #define BS_AIPS_PACRB_SP2 (1U) //!< Bit field size in bits for AIPS_PACRB_SP2. |
mbed_official | 146:f64d43ff0c18 | 2141 | |
mbed_official | 146:f64d43ff0c18 | 2142 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2143 | //! @brief Read current value of the AIPS_PACRB_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 2144 | #define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2)) |
mbed_official | 146:f64d43ff0c18 | 2145 | #endif |
mbed_official | 146:f64d43ff0c18 | 2146 | |
mbed_official | 146:f64d43ff0c18 | 2147 | //! @brief Format value for bitfield AIPS_PACRB_SP2. |
mbed_official | 146:f64d43ff0c18 | 2148 | #define BF_AIPS_PACRB_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP2), uint32_t) & BM_AIPS_PACRB_SP2) |
mbed_official | 146:f64d43ff0c18 | 2149 | |
mbed_official | 146:f64d43ff0c18 | 2150 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2151 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2152 | #define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2153 | #endif |
mbed_official | 146:f64d43ff0c18 | 2154 | //@} |
mbed_official | 146:f64d43ff0c18 | 2155 | |
mbed_official | 146:f64d43ff0c18 | 2156 | /*! |
mbed_official | 146:f64d43ff0c18 | 2157 | * @name Register AIPS_PACRB, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 2158 | * |
mbed_official | 146:f64d43ff0c18 | 2159 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2160 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2161 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2162 | * |
mbed_official | 146:f64d43ff0c18 | 2163 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2164 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2165 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2166 | */ |
mbed_official | 146:f64d43ff0c18 | 2167 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2168 | #define BP_AIPS_PACRB_TP1 (24U) //!< Bit position for AIPS_PACRB_TP1. |
mbed_official | 146:f64d43ff0c18 | 2169 | #define BM_AIPS_PACRB_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRB_TP1. |
mbed_official | 146:f64d43ff0c18 | 2170 | #define BS_AIPS_PACRB_TP1 (1U) //!< Bit field size in bits for AIPS_PACRB_TP1. |
mbed_official | 146:f64d43ff0c18 | 2171 | |
mbed_official | 146:f64d43ff0c18 | 2172 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2173 | //! @brief Read current value of the AIPS_PACRB_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 2174 | #define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1)) |
mbed_official | 146:f64d43ff0c18 | 2175 | #endif |
mbed_official | 146:f64d43ff0c18 | 2176 | |
mbed_official | 146:f64d43ff0c18 | 2177 | //! @brief Format value for bitfield AIPS_PACRB_TP1. |
mbed_official | 146:f64d43ff0c18 | 2178 | #define BF_AIPS_PACRB_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP1), uint32_t) & BM_AIPS_PACRB_TP1) |
mbed_official | 146:f64d43ff0c18 | 2179 | |
mbed_official | 146:f64d43ff0c18 | 2180 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2181 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2182 | #define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2183 | #endif |
mbed_official | 146:f64d43ff0c18 | 2184 | //@} |
mbed_official | 146:f64d43ff0c18 | 2185 | |
mbed_official | 146:f64d43ff0c18 | 2186 | /*! |
mbed_official | 146:f64d43ff0c18 | 2187 | * @name Register AIPS_PACRB, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 2188 | * |
mbed_official | 146:f64d43ff0c18 | 2189 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 2190 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 2191 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2192 | * |
mbed_official | 146:f64d43ff0c18 | 2193 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2194 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2195 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2196 | */ |
mbed_official | 146:f64d43ff0c18 | 2197 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2198 | #define BP_AIPS_PACRB_WP1 (25U) //!< Bit position for AIPS_PACRB_WP1. |
mbed_official | 146:f64d43ff0c18 | 2199 | #define BM_AIPS_PACRB_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRB_WP1. |
mbed_official | 146:f64d43ff0c18 | 2200 | #define BS_AIPS_PACRB_WP1 (1U) //!< Bit field size in bits for AIPS_PACRB_WP1. |
mbed_official | 146:f64d43ff0c18 | 2201 | |
mbed_official | 146:f64d43ff0c18 | 2202 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2203 | //! @brief Read current value of the AIPS_PACRB_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 2204 | #define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1)) |
mbed_official | 146:f64d43ff0c18 | 2205 | #endif |
mbed_official | 146:f64d43ff0c18 | 2206 | |
mbed_official | 146:f64d43ff0c18 | 2207 | //! @brief Format value for bitfield AIPS_PACRB_WP1. |
mbed_official | 146:f64d43ff0c18 | 2208 | #define BF_AIPS_PACRB_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP1), uint32_t) & BM_AIPS_PACRB_WP1) |
mbed_official | 146:f64d43ff0c18 | 2209 | |
mbed_official | 146:f64d43ff0c18 | 2210 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2211 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2212 | #define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2213 | #endif |
mbed_official | 146:f64d43ff0c18 | 2214 | //@} |
mbed_official | 146:f64d43ff0c18 | 2215 | |
mbed_official | 146:f64d43ff0c18 | 2216 | /*! |
mbed_official | 146:f64d43ff0c18 | 2217 | * @name Register AIPS_PACRB, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 2218 | * |
mbed_official | 146:f64d43ff0c18 | 2219 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2220 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2221 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2222 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2223 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2224 | * |
mbed_official | 146:f64d43ff0c18 | 2225 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2226 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2227 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2228 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2229 | */ |
mbed_official | 146:f64d43ff0c18 | 2230 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2231 | #define BP_AIPS_PACRB_SP1 (26U) //!< Bit position for AIPS_PACRB_SP1. |
mbed_official | 146:f64d43ff0c18 | 2232 | #define BM_AIPS_PACRB_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRB_SP1. |
mbed_official | 146:f64d43ff0c18 | 2233 | #define BS_AIPS_PACRB_SP1 (1U) //!< Bit field size in bits for AIPS_PACRB_SP1. |
mbed_official | 146:f64d43ff0c18 | 2234 | |
mbed_official | 146:f64d43ff0c18 | 2235 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2236 | //! @brief Read current value of the AIPS_PACRB_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 2237 | #define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1)) |
mbed_official | 146:f64d43ff0c18 | 2238 | #endif |
mbed_official | 146:f64d43ff0c18 | 2239 | |
mbed_official | 146:f64d43ff0c18 | 2240 | //! @brief Format value for bitfield AIPS_PACRB_SP1. |
mbed_official | 146:f64d43ff0c18 | 2241 | #define BF_AIPS_PACRB_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP1), uint32_t) & BM_AIPS_PACRB_SP1) |
mbed_official | 146:f64d43ff0c18 | 2242 | |
mbed_official | 146:f64d43ff0c18 | 2243 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2244 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2245 | #define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2246 | #endif |
mbed_official | 146:f64d43ff0c18 | 2247 | //@} |
mbed_official | 146:f64d43ff0c18 | 2248 | |
mbed_official | 146:f64d43ff0c18 | 2249 | /*! |
mbed_official | 146:f64d43ff0c18 | 2250 | * @name Register AIPS_PACRB, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 2251 | * |
mbed_official | 146:f64d43ff0c18 | 2252 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2253 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2254 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2255 | * |
mbed_official | 146:f64d43ff0c18 | 2256 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2257 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2258 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2259 | */ |
mbed_official | 146:f64d43ff0c18 | 2260 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2261 | #define BP_AIPS_PACRB_TP0 (28U) //!< Bit position for AIPS_PACRB_TP0. |
mbed_official | 146:f64d43ff0c18 | 2262 | #define BM_AIPS_PACRB_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRB_TP0. |
mbed_official | 146:f64d43ff0c18 | 2263 | #define BS_AIPS_PACRB_TP0 (1U) //!< Bit field size in bits for AIPS_PACRB_TP0. |
mbed_official | 146:f64d43ff0c18 | 2264 | |
mbed_official | 146:f64d43ff0c18 | 2265 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2266 | //! @brief Read current value of the AIPS_PACRB_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 2267 | #define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0)) |
mbed_official | 146:f64d43ff0c18 | 2268 | #endif |
mbed_official | 146:f64d43ff0c18 | 2269 | |
mbed_official | 146:f64d43ff0c18 | 2270 | //! @brief Format value for bitfield AIPS_PACRB_TP0. |
mbed_official | 146:f64d43ff0c18 | 2271 | #define BF_AIPS_PACRB_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP0), uint32_t) & BM_AIPS_PACRB_TP0) |
mbed_official | 146:f64d43ff0c18 | 2272 | |
mbed_official | 146:f64d43ff0c18 | 2273 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2274 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2275 | #define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2276 | #endif |
mbed_official | 146:f64d43ff0c18 | 2277 | //@} |
mbed_official | 146:f64d43ff0c18 | 2278 | |
mbed_official | 146:f64d43ff0c18 | 2279 | /*! |
mbed_official | 146:f64d43ff0c18 | 2280 | * @name Register AIPS_PACRB, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 2281 | * |
mbed_official | 146:f64d43ff0c18 | 2282 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 2283 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 2284 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2285 | * |
mbed_official | 146:f64d43ff0c18 | 2286 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2287 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2288 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2289 | */ |
mbed_official | 146:f64d43ff0c18 | 2290 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2291 | #define BP_AIPS_PACRB_WP0 (29U) //!< Bit position for AIPS_PACRB_WP0. |
mbed_official | 146:f64d43ff0c18 | 2292 | #define BM_AIPS_PACRB_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRB_WP0. |
mbed_official | 146:f64d43ff0c18 | 2293 | #define BS_AIPS_PACRB_WP0 (1U) //!< Bit field size in bits for AIPS_PACRB_WP0. |
mbed_official | 146:f64d43ff0c18 | 2294 | |
mbed_official | 146:f64d43ff0c18 | 2295 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2296 | //! @brief Read current value of the AIPS_PACRB_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 2297 | #define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0)) |
mbed_official | 146:f64d43ff0c18 | 2298 | #endif |
mbed_official | 146:f64d43ff0c18 | 2299 | |
mbed_official | 146:f64d43ff0c18 | 2300 | //! @brief Format value for bitfield AIPS_PACRB_WP0. |
mbed_official | 146:f64d43ff0c18 | 2301 | #define BF_AIPS_PACRB_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP0), uint32_t) & BM_AIPS_PACRB_WP0) |
mbed_official | 146:f64d43ff0c18 | 2302 | |
mbed_official | 146:f64d43ff0c18 | 2303 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2304 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2305 | #define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2306 | #endif |
mbed_official | 146:f64d43ff0c18 | 2307 | //@} |
mbed_official | 146:f64d43ff0c18 | 2308 | |
mbed_official | 146:f64d43ff0c18 | 2309 | /*! |
mbed_official | 146:f64d43ff0c18 | 2310 | * @name Register AIPS_PACRB, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 2311 | * |
mbed_official | 146:f64d43ff0c18 | 2312 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2313 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2314 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2315 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2316 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2317 | * |
mbed_official | 146:f64d43ff0c18 | 2318 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2319 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2320 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2321 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2322 | */ |
mbed_official | 146:f64d43ff0c18 | 2323 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2324 | #define BP_AIPS_PACRB_SP0 (30U) //!< Bit position for AIPS_PACRB_SP0. |
mbed_official | 146:f64d43ff0c18 | 2325 | #define BM_AIPS_PACRB_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRB_SP0. |
mbed_official | 146:f64d43ff0c18 | 2326 | #define BS_AIPS_PACRB_SP0 (1U) //!< Bit field size in bits for AIPS_PACRB_SP0. |
mbed_official | 146:f64d43ff0c18 | 2327 | |
mbed_official | 146:f64d43ff0c18 | 2328 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2329 | //! @brief Read current value of the AIPS_PACRB_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 2330 | #define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0)) |
mbed_official | 146:f64d43ff0c18 | 2331 | #endif |
mbed_official | 146:f64d43ff0c18 | 2332 | |
mbed_official | 146:f64d43ff0c18 | 2333 | //! @brief Format value for bitfield AIPS_PACRB_SP0. |
mbed_official | 146:f64d43ff0c18 | 2334 | #define BF_AIPS_PACRB_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP0), uint32_t) & BM_AIPS_PACRB_SP0) |
mbed_official | 146:f64d43ff0c18 | 2335 | |
mbed_official | 146:f64d43ff0c18 | 2336 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2337 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2338 | #define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2339 | #endif |
mbed_official | 146:f64d43ff0c18 | 2340 | //@} |
mbed_official | 146:f64d43ff0c18 | 2341 | |
mbed_official | 146:f64d43ff0c18 | 2342 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2343 | // HW_AIPS_PACRC - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 2344 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2345 | |
mbed_official | 146:f64d43ff0c18 | 2346 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2347 | /*! |
mbed_official | 146:f64d43ff0c18 | 2348 | * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 2349 | * |
mbed_official | 146:f64d43ff0c18 | 2350 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 2351 | * |
mbed_official | 146:f64d43ff0c18 | 2352 | * Each PACR register consists of eight 4-bit PACR fields. Each PACR field |
mbed_official | 146:f64d43ff0c18 | 2353 | * defines the access levels for a particular peripheral. The mapping between a |
mbed_official | 146:f64d43ff0c18 | 2354 | * peripheral and its PACR field is shown in the table below. The peripheral assignment |
mbed_official | 146:f64d43ff0c18 | 2355 | * to each PACR is defined by the memory map slot that the peripheral is |
mbed_official | 146:f64d43ff0c18 | 2356 | * assigned to. See this chip's memory map for the assignment of a particular |
mbed_official | 146:f64d43ff0c18 | 2357 | * peripheral. The following table shows the location of each peripheral slot's PACR field |
mbed_official | 146:f64d43ff0c18 | 2358 | * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] |
mbed_official | 146:f64d43ff0c18 | 2359 | * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 |
mbed_official | 146:f64d43ff0c18 | 2360 | * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC |
mbed_official | 146:f64d43ff0c18 | 2361 | * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 |
mbed_official | 146:f64d43ff0c18 | 2362 | * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 |
mbed_official | 146:f64d43ff0c18 | 2363 | * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 |
mbed_official | 146:f64d43ff0c18 | 2364 | * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 |
mbed_official | 146:f64d43ff0c18 | 2365 | * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH |
mbed_official | 146:f64d43ff0c18 | 2366 | * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 |
mbed_official | 146:f64d43ff0c18 | 2367 | * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 |
mbed_official | 146:f64d43ff0c18 | 2368 | * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 |
mbed_official | 146:f64d43ff0c18 | 2369 | * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 |
mbed_official | 146:f64d43ff0c18 | 2370 | * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 |
mbed_official | 146:f64d43ff0c18 | 2371 | * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 |
mbed_official | 146:f64d43ff0c18 | 2372 | * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 |
mbed_official | 146:f64d43ff0c18 | 2373 | * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 |
mbed_official | 146:f64d43ff0c18 | 2374 | * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR |
mbed_official | 146:f64d43ff0c18 | 2375 | * A-D, which control peripheral slots 0-31, are shown below. The following |
mbed_official | 146:f64d43ff0c18 | 2376 | * section, PACRPeripheral Access Control Register , shows the register field |
mbed_official | 146:f64d43ff0c18 | 2377 | * descriptions for PACR E-P. All PACR registers are identical. They are divided into two |
mbed_official | 146:f64d43ff0c18 | 2378 | * sections because they occupy two non-contiguous address spaces. |
mbed_official | 146:f64d43ff0c18 | 2379 | */ |
mbed_official | 146:f64d43ff0c18 | 2380 | typedef union _hw_aips_pacrc |
mbed_official | 146:f64d43ff0c18 | 2381 | { |
mbed_official | 146:f64d43ff0c18 | 2382 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 2383 | struct _hw_aips_pacrc_bitfields |
mbed_official | 146:f64d43ff0c18 | 2384 | { |
mbed_official | 146:f64d43ff0c18 | 2385 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2386 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2387 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2388 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 2389 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2390 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2391 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2392 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 2393 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2394 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2395 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2396 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 2397 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2398 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2399 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2400 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 2401 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2402 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2403 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2404 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 2405 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2406 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2407 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2408 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 2409 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2410 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2411 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2412 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 2413 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 2414 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 2415 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 2416 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 2417 | } B; |
mbed_official | 146:f64d43ff0c18 | 2418 | } hw_aips_pacrc_t; |
mbed_official | 146:f64d43ff0c18 | 2419 | #endif |
mbed_official | 146:f64d43ff0c18 | 2420 | |
mbed_official | 146:f64d43ff0c18 | 2421 | /*! |
mbed_official | 146:f64d43ff0c18 | 2422 | * @name Constants and macros for entire AIPS_PACRC register |
mbed_official | 146:f64d43ff0c18 | 2423 | */ |
mbed_official | 146:f64d43ff0c18 | 2424 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2425 | #define HW_AIPS_PACRC_ADDR(x) (REGS_AIPS_BASE(x) + 0x28U) |
mbed_official | 146:f64d43ff0c18 | 2426 | |
mbed_official | 146:f64d43ff0c18 | 2427 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2428 | #define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2429 | #define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U) |
mbed_official | 146:f64d43ff0c18 | 2430 | #define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2431 | #define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2432 | #define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2433 | #define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2434 | #endif |
mbed_official | 146:f64d43ff0c18 | 2435 | //@} |
mbed_official | 146:f64d43ff0c18 | 2436 | |
mbed_official | 146:f64d43ff0c18 | 2437 | /* |
mbed_official | 146:f64d43ff0c18 | 2438 | * Constants & macros for individual AIPS_PACRC bitfields |
mbed_official | 146:f64d43ff0c18 | 2439 | */ |
mbed_official | 146:f64d43ff0c18 | 2440 | |
mbed_official | 146:f64d43ff0c18 | 2441 | /*! |
mbed_official | 146:f64d43ff0c18 | 2442 | * @name Register AIPS_PACRC, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2443 | * |
mbed_official | 146:f64d43ff0c18 | 2444 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2445 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2446 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2447 | * |
mbed_official | 146:f64d43ff0c18 | 2448 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2449 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2450 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2451 | */ |
mbed_official | 146:f64d43ff0c18 | 2452 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2453 | #define BP_AIPS_PACRC_TP7 (0U) //!< Bit position for AIPS_PACRC_TP7. |
mbed_official | 146:f64d43ff0c18 | 2454 | #define BM_AIPS_PACRC_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRC_TP7. |
mbed_official | 146:f64d43ff0c18 | 2455 | #define BS_AIPS_PACRC_TP7 (1U) //!< Bit field size in bits for AIPS_PACRC_TP7. |
mbed_official | 146:f64d43ff0c18 | 2456 | |
mbed_official | 146:f64d43ff0c18 | 2457 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2458 | //! @brief Read current value of the AIPS_PACRC_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 2459 | #define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7)) |
mbed_official | 146:f64d43ff0c18 | 2460 | #endif |
mbed_official | 146:f64d43ff0c18 | 2461 | |
mbed_official | 146:f64d43ff0c18 | 2462 | //! @brief Format value for bitfield AIPS_PACRC_TP7. |
mbed_official | 146:f64d43ff0c18 | 2463 | #define BF_AIPS_PACRC_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP7), uint32_t) & BM_AIPS_PACRC_TP7) |
mbed_official | 146:f64d43ff0c18 | 2464 | |
mbed_official | 146:f64d43ff0c18 | 2465 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2466 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2467 | #define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2468 | #endif |
mbed_official | 146:f64d43ff0c18 | 2469 | //@} |
mbed_official | 146:f64d43ff0c18 | 2470 | |
mbed_official | 146:f64d43ff0c18 | 2471 | /*! |
mbed_official | 146:f64d43ff0c18 | 2472 | * @name Register AIPS_PACRC, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 2473 | * |
mbed_official | 146:f64d43ff0c18 | 2474 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 2475 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 2476 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2477 | * |
mbed_official | 146:f64d43ff0c18 | 2478 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2479 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2480 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2481 | */ |
mbed_official | 146:f64d43ff0c18 | 2482 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2483 | #define BP_AIPS_PACRC_WP7 (1U) //!< Bit position for AIPS_PACRC_WP7. |
mbed_official | 146:f64d43ff0c18 | 2484 | #define BM_AIPS_PACRC_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRC_WP7. |
mbed_official | 146:f64d43ff0c18 | 2485 | #define BS_AIPS_PACRC_WP7 (1U) //!< Bit field size in bits for AIPS_PACRC_WP7. |
mbed_official | 146:f64d43ff0c18 | 2486 | |
mbed_official | 146:f64d43ff0c18 | 2487 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2488 | //! @brief Read current value of the AIPS_PACRC_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 2489 | #define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7)) |
mbed_official | 146:f64d43ff0c18 | 2490 | #endif |
mbed_official | 146:f64d43ff0c18 | 2491 | |
mbed_official | 146:f64d43ff0c18 | 2492 | //! @brief Format value for bitfield AIPS_PACRC_WP7. |
mbed_official | 146:f64d43ff0c18 | 2493 | #define BF_AIPS_PACRC_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP7), uint32_t) & BM_AIPS_PACRC_WP7) |
mbed_official | 146:f64d43ff0c18 | 2494 | |
mbed_official | 146:f64d43ff0c18 | 2495 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2496 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2497 | #define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2498 | #endif |
mbed_official | 146:f64d43ff0c18 | 2499 | //@} |
mbed_official | 146:f64d43ff0c18 | 2500 | |
mbed_official | 146:f64d43ff0c18 | 2501 | /*! |
mbed_official | 146:f64d43ff0c18 | 2502 | * @name Register AIPS_PACRC, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 2503 | * |
mbed_official | 146:f64d43ff0c18 | 2504 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2505 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2506 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2507 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2508 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2509 | * |
mbed_official | 146:f64d43ff0c18 | 2510 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2511 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2512 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2513 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2514 | */ |
mbed_official | 146:f64d43ff0c18 | 2515 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2516 | #define BP_AIPS_PACRC_SP7 (2U) //!< Bit position for AIPS_PACRC_SP7. |
mbed_official | 146:f64d43ff0c18 | 2517 | #define BM_AIPS_PACRC_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRC_SP7. |
mbed_official | 146:f64d43ff0c18 | 2518 | #define BS_AIPS_PACRC_SP7 (1U) //!< Bit field size in bits for AIPS_PACRC_SP7. |
mbed_official | 146:f64d43ff0c18 | 2519 | |
mbed_official | 146:f64d43ff0c18 | 2520 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2521 | //! @brief Read current value of the AIPS_PACRC_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 2522 | #define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7)) |
mbed_official | 146:f64d43ff0c18 | 2523 | #endif |
mbed_official | 146:f64d43ff0c18 | 2524 | |
mbed_official | 146:f64d43ff0c18 | 2525 | //! @brief Format value for bitfield AIPS_PACRC_SP7. |
mbed_official | 146:f64d43ff0c18 | 2526 | #define BF_AIPS_PACRC_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP7), uint32_t) & BM_AIPS_PACRC_SP7) |
mbed_official | 146:f64d43ff0c18 | 2527 | |
mbed_official | 146:f64d43ff0c18 | 2528 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2529 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2530 | #define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2531 | #endif |
mbed_official | 146:f64d43ff0c18 | 2532 | //@} |
mbed_official | 146:f64d43ff0c18 | 2533 | |
mbed_official | 146:f64d43ff0c18 | 2534 | /*! |
mbed_official | 146:f64d43ff0c18 | 2535 | * @name Register AIPS_PACRC, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 2536 | * |
mbed_official | 146:f64d43ff0c18 | 2537 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2538 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2539 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2540 | * |
mbed_official | 146:f64d43ff0c18 | 2541 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2542 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2543 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2544 | */ |
mbed_official | 146:f64d43ff0c18 | 2545 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2546 | #define BP_AIPS_PACRC_TP6 (4U) //!< Bit position for AIPS_PACRC_TP6. |
mbed_official | 146:f64d43ff0c18 | 2547 | #define BM_AIPS_PACRC_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRC_TP6. |
mbed_official | 146:f64d43ff0c18 | 2548 | #define BS_AIPS_PACRC_TP6 (1U) //!< Bit field size in bits for AIPS_PACRC_TP6. |
mbed_official | 146:f64d43ff0c18 | 2549 | |
mbed_official | 146:f64d43ff0c18 | 2550 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2551 | //! @brief Read current value of the AIPS_PACRC_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 2552 | #define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6)) |
mbed_official | 146:f64d43ff0c18 | 2553 | #endif |
mbed_official | 146:f64d43ff0c18 | 2554 | |
mbed_official | 146:f64d43ff0c18 | 2555 | //! @brief Format value for bitfield AIPS_PACRC_TP6. |
mbed_official | 146:f64d43ff0c18 | 2556 | #define BF_AIPS_PACRC_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP6), uint32_t) & BM_AIPS_PACRC_TP6) |
mbed_official | 146:f64d43ff0c18 | 2557 | |
mbed_official | 146:f64d43ff0c18 | 2558 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2559 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2560 | #define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2561 | #endif |
mbed_official | 146:f64d43ff0c18 | 2562 | //@} |
mbed_official | 146:f64d43ff0c18 | 2563 | |
mbed_official | 146:f64d43ff0c18 | 2564 | /*! |
mbed_official | 146:f64d43ff0c18 | 2565 | * @name Register AIPS_PACRC, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 2566 | * |
mbed_official | 146:f64d43ff0c18 | 2567 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 2568 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 2569 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2570 | * |
mbed_official | 146:f64d43ff0c18 | 2571 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2572 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2573 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2574 | */ |
mbed_official | 146:f64d43ff0c18 | 2575 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2576 | #define BP_AIPS_PACRC_WP6 (5U) //!< Bit position for AIPS_PACRC_WP6. |
mbed_official | 146:f64d43ff0c18 | 2577 | #define BM_AIPS_PACRC_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRC_WP6. |
mbed_official | 146:f64d43ff0c18 | 2578 | #define BS_AIPS_PACRC_WP6 (1U) //!< Bit field size in bits for AIPS_PACRC_WP6. |
mbed_official | 146:f64d43ff0c18 | 2579 | |
mbed_official | 146:f64d43ff0c18 | 2580 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2581 | //! @brief Read current value of the AIPS_PACRC_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 2582 | #define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6)) |
mbed_official | 146:f64d43ff0c18 | 2583 | #endif |
mbed_official | 146:f64d43ff0c18 | 2584 | |
mbed_official | 146:f64d43ff0c18 | 2585 | //! @brief Format value for bitfield AIPS_PACRC_WP6. |
mbed_official | 146:f64d43ff0c18 | 2586 | #define BF_AIPS_PACRC_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP6), uint32_t) & BM_AIPS_PACRC_WP6) |
mbed_official | 146:f64d43ff0c18 | 2587 | |
mbed_official | 146:f64d43ff0c18 | 2588 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2589 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2590 | #define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2591 | #endif |
mbed_official | 146:f64d43ff0c18 | 2592 | //@} |
mbed_official | 146:f64d43ff0c18 | 2593 | |
mbed_official | 146:f64d43ff0c18 | 2594 | /*! |
mbed_official | 146:f64d43ff0c18 | 2595 | * @name Register AIPS_PACRC, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 2596 | * |
mbed_official | 146:f64d43ff0c18 | 2597 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2598 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2599 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2600 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2601 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2602 | * |
mbed_official | 146:f64d43ff0c18 | 2603 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2604 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2605 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2606 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2607 | */ |
mbed_official | 146:f64d43ff0c18 | 2608 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2609 | #define BP_AIPS_PACRC_SP6 (6U) //!< Bit position for AIPS_PACRC_SP6. |
mbed_official | 146:f64d43ff0c18 | 2610 | #define BM_AIPS_PACRC_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRC_SP6. |
mbed_official | 146:f64d43ff0c18 | 2611 | #define BS_AIPS_PACRC_SP6 (1U) //!< Bit field size in bits for AIPS_PACRC_SP6. |
mbed_official | 146:f64d43ff0c18 | 2612 | |
mbed_official | 146:f64d43ff0c18 | 2613 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2614 | //! @brief Read current value of the AIPS_PACRC_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 2615 | #define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6)) |
mbed_official | 146:f64d43ff0c18 | 2616 | #endif |
mbed_official | 146:f64d43ff0c18 | 2617 | |
mbed_official | 146:f64d43ff0c18 | 2618 | //! @brief Format value for bitfield AIPS_PACRC_SP6. |
mbed_official | 146:f64d43ff0c18 | 2619 | #define BF_AIPS_PACRC_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP6), uint32_t) & BM_AIPS_PACRC_SP6) |
mbed_official | 146:f64d43ff0c18 | 2620 | |
mbed_official | 146:f64d43ff0c18 | 2621 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2622 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2623 | #define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2624 | #endif |
mbed_official | 146:f64d43ff0c18 | 2625 | //@} |
mbed_official | 146:f64d43ff0c18 | 2626 | |
mbed_official | 146:f64d43ff0c18 | 2627 | /*! |
mbed_official | 146:f64d43ff0c18 | 2628 | * @name Register AIPS_PACRC, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 2629 | * |
mbed_official | 146:f64d43ff0c18 | 2630 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2631 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2632 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2633 | * |
mbed_official | 146:f64d43ff0c18 | 2634 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2635 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2636 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2637 | */ |
mbed_official | 146:f64d43ff0c18 | 2638 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2639 | #define BP_AIPS_PACRC_TP5 (8U) //!< Bit position for AIPS_PACRC_TP5. |
mbed_official | 146:f64d43ff0c18 | 2640 | #define BM_AIPS_PACRC_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRC_TP5. |
mbed_official | 146:f64d43ff0c18 | 2641 | #define BS_AIPS_PACRC_TP5 (1U) //!< Bit field size in bits for AIPS_PACRC_TP5. |
mbed_official | 146:f64d43ff0c18 | 2642 | |
mbed_official | 146:f64d43ff0c18 | 2643 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2644 | //! @brief Read current value of the AIPS_PACRC_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 2645 | #define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5)) |
mbed_official | 146:f64d43ff0c18 | 2646 | #endif |
mbed_official | 146:f64d43ff0c18 | 2647 | |
mbed_official | 146:f64d43ff0c18 | 2648 | //! @brief Format value for bitfield AIPS_PACRC_TP5. |
mbed_official | 146:f64d43ff0c18 | 2649 | #define BF_AIPS_PACRC_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP5), uint32_t) & BM_AIPS_PACRC_TP5) |
mbed_official | 146:f64d43ff0c18 | 2650 | |
mbed_official | 146:f64d43ff0c18 | 2651 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2652 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2653 | #define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2654 | #endif |
mbed_official | 146:f64d43ff0c18 | 2655 | //@} |
mbed_official | 146:f64d43ff0c18 | 2656 | |
mbed_official | 146:f64d43ff0c18 | 2657 | /*! |
mbed_official | 146:f64d43ff0c18 | 2658 | * @name Register AIPS_PACRC, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 2659 | * |
mbed_official | 146:f64d43ff0c18 | 2660 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 2661 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 2662 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2663 | * |
mbed_official | 146:f64d43ff0c18 | 2664 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2665 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2666 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2667 | */ |
mbed_official | 146:f64d43ff0c18 | 2668 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2669 | #define BP_AIPS_PACRC_WP5 (9U) //!< Bit position for AIPS_PACRC_WP5. |
mbed_official | 146:f64d43ff0c18 | 2670 | #define BM_AIPS_PACRC_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRC_WP5. |
mbed_official | 146:f64d43ff0c18 | 2671 | #define BS_AIPS_PACRC_WP5 (1U) //!< Bit field size in bits for AIPS_PACRC_WP5. |
mbed_official | 146:f64d43ff0c18 | 2672 | |
mbed_official | 146:f64d43ff0c18 | 2673 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2674 | //! @brief Read current value of the AIPS_PACRC_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 2675 | #define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5)) |
mbed_official | 146:f64d43ff0c18 | 2676 | #endif |
mbed_official | 146:f64d43ff0c18 | 2677 | |
mbed_official | 146:f64d43ff0c18 | 2678 | //! @brief Format value for bitfield AIPS_PACRC_WP5. |
mbed_official | 146:f64d43ff0c18 | 2679 | #define BF_AIPS_PACRC_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP5), uint32_t) & BM_AIPS_PACRC_WP5) |
mbed_official | 146:f64d43ff0c18 | 2680 | |
mbed_official | 146:f64d43ff0c18 | 2681 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2682 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2683 | #define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2684 | #endif |
mbed_official | 146:f64d43ff0c18 | 2685 | //@} |
mbed_official | 146:f64d43ff0c18 | 2686 | |
mbed_official | 146:f64d43ff0c18 | 2687 | /*! |
mbed_official | 146:f64d43ff0c18 | 2688 | * @name Register AIPS_PACRC, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 2689 | * |
mbed_official | 146:f64d43ff0c18 | 2690 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2691 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2692 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2693 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2694 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2695 | * |
mbed_official | 146:f64d43ff0c18 | 2696 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2697 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2698 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2699 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2700 | */ |
mbed_official | 146:f64d43ff0c18 | 2701 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2702 | #define BP_AIPS_PACRC_SP5 (10U) //!< Bit position for AIPS_PACRC_SP5. |
mbed_official | 146:f64d43ff0c18 | 2703 | #define BM_AIPS_PACRC_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRC_SP5. |
mbed_official | 146:f64d43ff0c18 | 2704 | #define BS_AIPS_PACRC_SP5 (1U) //!< Bit field size in bits for AIPS_PACRC_SP5. |
mbed_official | 146:f64d43ff0c18 | 2705 | |
mbed_official | 146:f64d43ff0c18 | 2706 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2707 | //! @brief Read current value of the AIPS_PACRC_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 2708 | #define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5)) |
mbed_official | 146:f64d43ff0c18 | 2709 | #endif |
mbed_official | 146:f64d43ff0c18 | 2710 | |
mbed_official | 146:f64d43ff0c18 | 2711 | //! @brief Format value for bitfield AIPS_PACRC_SP5. |
mbed_official | 146:f64d43ff0c18 | 2712 | #define BF_AIPS_PACRC_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP5), uint32_t) & BM_AIPS_PACRC_SP5) |
mbed_official | 146:f64d43ff0c18 | 2713 | |
mbed_official | 146:f64d43ff0c18 | 2714 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2715 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2716 | #define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2717 | #endif |
mbed_official | 146:f64d43ff0c18 | 2718 | //@} |
mbed_official | 146:f64d43ff0c18 | 2719 | |
mbed_official | 146:f64d43ff0c18 | 2720 | /*! |
mbed_official | 146:f64d43ff0c18 | 2721 | * @name Register AIPS_PACRC, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 2722 | * |
mbed_official | 146:f64d43ff0c18 | 2723 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2724 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2725 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2726 | * |
mbed_official | 146:f64d43ff0c18 | 2727 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2728 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2729 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2730 | */ |
mbed_official | 146:f64d43ff0c18 | 2731 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2732 | #define BP_AIPS_PACRC_TP4 (12U) //!< Bit position for AIPS_PACRC_TP4. |
mbed_official | 146:f64d43ff0c18 | 2733 | #define BM_AIPS_PACRC_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRC_TP4. |
mbed_official | 146:f64d43ff0c18 | 2734 | #define BS_AIPS_PACRC_TP4 (1U) //!< Bit field size in bits for AIPS_PACRC_TP4. |
mbed_official | 146:f64d43ff0c18 | 2735 | |
mbed_official | 146:f64d43ff0c18 | 2736 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2737 | //! @brief Read current value of the AIPS_PACRC_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 2738 | #define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4)) |
mbed_official | 146:f64d43ff0c18 | 2739 | #endif |
mbed_official | 146:f64d43ff0c18 | 2740 | |
mbed_official | 146:f64d43ff0c18 | 2741 | //! @brief Format value for bitfield AIPS_PACRC_TP4. |
mbed_official | 146:f64d43ff0c18 | 2742 | #define BF_AIPS_PACRC_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP4), uint32_t) & BM_AIPS_PACRC_TP4) |
mbed_official | 146:f64d43ff0c18 | 2743 | |
mbed_official | 146:f64d43ff0c18 | 2744 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2745 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2746 | #define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2747 | #endif |
mbed_official | 146:f64d43ff0c18 | 2748 | //@} |
mbed_official | 146:f64d43ff0c18 | 2749 | |
mbed_official | 146:f64d43ff0c18 | 2750 | /*! |
mbed_official | 146:f64d43ff0c18 | 2751 | * @name Register AIPS_PACRC, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 2752 | * |
mbed_official | 146:f64d43ff0c18 | 2753 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 2754 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 2755 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2756 | * |
mbed_official | 146:f64d43ff0c18 | 2757 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2758 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2759 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2760 | */ |
mbed_official | 146:f64d43ff0c18 | 2761 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2762 | #define BP_AIPS_PACRC_WP4 (13U) //!< Bit position for AIPS_PACRC_WP4. |
mbed_official | 146:f64d43ff0c18 | 2763 | #define BM_AIPS_PACRC_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRC_WP4. |
mbed_official | 146:f64d43ff0c18 | 2764 | #define BS_AIPS_PACRC_WP4 (1U) //!< Bit field size in bits for AIPS_PACRC_WP4. |
mbed_official | 146:f64d43ff0c18 | 2765 | |
mbed_official | 146:f64d43ff0c18 | 2766 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2767 | //! @brief Read current value of the AIPS_PACRC_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 2768 | #define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4)) |
mbed_official | 146:f64d43ff0c18 | 2769 | #endif |
mbed_official | 146:f64d43ff0c18 | 2770 | |
mbed_official | 146:f64d43ff0c18 | 2771 | //! @brief Format value for bitfield AIPS_PACRC_WP4. |
mbed_official | 146:f64d43ff0c18 | 2772 | #define BF_AIPS_PACRC_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP4), uint32_t) & BM_AIPS_PACRC_WP4) |
mbed_official | 146:f64d43ff0c18 | 2773 | |
mbed_official | 146:f64d43ff0c18 | 2774 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2775 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2776 | #define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2777 | #endif |
mbed_official | 146:f64d43ff0c18 | 2778 | //@} |
mbed_official | 146:f64d43ff0c18 | 2779 | |
mbed_official | 146:f64d43ff0c18 | 2780 | /*! |
mbed_official | 146:f64d43ff0c18 | 2781 | * @name Register AIPS_PACRC, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 2782 | * |
mbed_official | 146:f64d43ff0c18 | 2783 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2784 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2785 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2786 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2787 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2788 | * |
mbed_official | 146:f64d43ff0c18 | 2789 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2790 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2791 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2792 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2793 | */ |
mbed_official | 146:f64d43ff0c18 | 2794 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2795 | #define BP_AIPS_PACRC_SP4 (14U) //!< Bit position for AIPS_PACRC_SP4. |
mbed_official | 146:f64d43ff0c18 | 2796 | #define BM_AIPS_PACRC_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRC_SP4. |
mbed_official | 146:f64d43ff0c18 | 2797 | #define BS_AIPS_PACRC_SP4 (1U) //!< Bit field size in bits for AIPS_PACRC_SP4. |
mbed_official | 146:f64d43ff0c18 | 2798 | |
mbed_official | 146:f64d43ff0c18 | 2799 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2800 | //! @brief Read current value of the AIPS_PACRC_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 2801 | #define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4)) |
mbed_official | 146:f64d43ff0c18 | 2802 | #endif |
mbed_official | 146:f64d43ff0c18 | 2803 | |
mbed_official | 146:f64d43ff0c18 | 2804 | //! @brief Format value for bitfield AIPS_PACRC_SP4. |
mbed_official | 146:f64d43ff0c18 | 2805 | #define BF_AIPS_PACRC_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP4), uint32_t) & BM_AIPS_PACRC_SP4) |
mbed_official | 146:f64d43ff0c18 | 2806 | |
mbed_official | 146:f64d43ff0c18 | 2807 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2808 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2809 | #define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2810 | #endif |
mbed_official | 146:f64d43ff0c18 | 2811 | //@} |
mbed_official | 146:f64d43ff0c18 | 2812 | |
mbed_official | 146:f64d43ff0c18 | 2813 | /*! |
mbed_official | 146:f64d43ff0c18 | 2814 | * @name Register AIPS_PACRC, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 2815 | * |
mbed_official | 146:f64d43ff0c18 | 2816 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2817 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2818 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2819 | * |
mbed_official | 146:f64d43ff0c18 | 2820 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2821 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2822 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2823 | */ |
mbed_official | 146:f64d43ff0c18 | 2824 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2825 | #define BP_AIPS_PACRC_TP3 (16U) //!< Bit position for AIPS_PACRC_TP3. |
mbed_official | 146:f64d43ff0c18 | 2826 | #define BM_AIPS_PACRC_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRC_TP3. |
mbed_official | 146:f64d43ff0c18 | 2827 | #define BS_AIPS_PACRC_TP3 (1U) //!< Bit field size in bits for AIPS_PACRC_TP3. |
mbed_official | 146:f64d43ff0c18 | 2828 | |
mbed_official | 146:f64d43ff0c18 | 2829 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2830 | //! @brief Read current value of the AIPS_PACRC_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 2831 | #define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3)) |
mbed_official | 146:f64d43ff0c18 | 2832 | #endif |
mbed_official | 146:f64d43ff0c18 | 2833 | |
mbed_official | 146:f64d43ff0c18 | 2834 | //! @brief Format value for bitfield AIPS_PACRC_TP3. |
mbed_official | 146:f64d43ff0c18 | 2835 | #define BF_AIPS_PACRC_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP3), uint32_t) & BM_AIPS_PACRC_TP3) |
mbed_official | 146:f64d43ff0c18 | 2836 | |
mbed_official | 146:f64d43ff0c18 | 2837 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2838 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2839 | #define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2840 | #endif |
mbed_official | 146:f64d43ff0c18 | 2841 | //@} |
mbed_official | 146:f64d43ff0c18 | 2842 | |
mbed_official | 146:f64d43ff0c18 | 2843 | /*! |
mbed_official | 146:f64d43ff0c18 | 2844 | * @name Register AIPS_PACRC, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 2845 | * |
mbed_official | 146:f64d43ff0c18 | 2846 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 2847 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 2848 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2849 | * |
mbed_official | 146:f64d43ff0c18 | 2850 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2851 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2852 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2853 | */ |
mbed_official | 146:f64d43ff0c18 | 2854 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2855 | #define BP_AIPS_PACRC_WP3 (17U) //!< Bit position for AIPS_PACRC_WP3. |
mbed_official | 146:f64d43ff0c18 | 2856 | #define BM_AIPS_PACRC_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRC_WP3. |
mbed_official | 146:f64d43ff0c18 | 2857 | #define BS_AIPS_PACRC_WP3 (1U) //!< Bit field size in bits for AIPS_PACRC_WP3. |
mbed_official | 146:f64d43ff0c18 | 2858 | |
mbed_official | 146:f64d43ff0c18 | 2859 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2860 | //! @brief Read current value of the AIPS_PACRC_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 2861 | #define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3)) |
mbed_official | 146:f64d43ff0c18 | 2862 | #endif |
mbed_official | 146:f64d43ff0c18 | 2863 | |
mbed_official | 146:f64d43ff0c18 | 2864 | //! @brief Format value for bitfield AIPS_PACRC_WP3. |
mbed_official | 146:f64d43ff0c18 | 2865 | #define BF_AIPS_PACRC_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP3), uint32_t) & BM_AIPS_PACRC_WP3) |
mbed_official | 146:f64d43ff0c18 | 2866 | |
mbed_official | 146:f64d43ff0c18 | 2867 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2868 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2869 | #define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2870 | #endif |
mbed_official | 146:f64d43ff0c18 | 2871 | //@} |
mbed_official | 146:f64d43ff0c18 | 2872 | |
mbed_official | 146:f64d43ff0c18 | 2873 | /*! |
mbed_official | 146:f64d43ff0c18 | 2874 | * @name Register AIPS_PACRC, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 2875 | * |
mbed_official | 146:f64d43ff0c18 | 2876 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2877 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2878 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 2879 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 2880 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 2881 | * |
mbed_official | 146:f64d43ff0c18 | 2882 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2883 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2884 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2885 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2886 | */ |
mbed_official | 146:f64d43ff0c18 | 2887 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2888 | #define BP_AIPS_PACRC_SP3 (18U) //!< Bit position for AIPS_PACRC_SP3. |
mbed_official | 146:f64d43ff0c18 | 2889 | #define BM_AIPS_PACRC_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRC_SP3. |
mbed_official | 146:f64d43ff0c18 | 2890 | #define BS_AIPS_PACRC_SP3 (1U) //!< Bit field size in bits for AIPS_PACRC_SP3. |
mbed_official | 146:f64d43ff0c18 | 2891 | |
mbed_official | 146:f64d43ff0c18 | 2892 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2893 | //! @brief Read current value of the AIPS_PACRC_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 2894 | #define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3)) |
mbed_official | 146:f64d43ff0c18 | 2895 | #endif |
mbed_official | 146:f64d43ff0c18 | 2896 | |
mbed_official | 146:f64d43ff0c18 | 2897 | //! @brief Format value for bitfield AIPS_PACRC_SP3. |
mbed_official | 146:f64d43ff0c18 | 2898 | #define BF_AIPS_PACRC_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP3), uint32_t) & BM_AIPS_PACRC_SP3) |
mbed_official | 146:f64d43ff0c18 | 2899 | |
mbed_official | 146:f64d43ff0c18 | 2900 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2901 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2902 | #define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2903 | #endif |
mbed_official | 146:f64d43ff0c18 | 2904 | //@} |
mbed_official | 146:f64d43ff0c18 | 2905 | |
mbed_official | 146:f64d43ff0c18 | 2906 | /*! |
mbed_official | 146:f64d43ff0c18 | 2907 | * @name Register AIPS_PACRC, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 2908 | * |
mbed_official | 146:f64d43ff0c18 | 2909 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 2910 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 2911 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2912 | * |
mbed_official | 146:f64d43ff0c18 | 2913 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2914 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 2915 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 2916 | */ |
mbed_official | 146:f64d43ff0c18 | 2917 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2918 | #define BP_AIPS_PACRC_TP2 (20U) //!< Bit position for AIPS_PACRC_TP2. |
mbed_official | 146:f64d43ff0c18 | 2919 | #define BM_AIPS_PACRC_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRC_TP2. |
mbed_official | 146:f64d43ff0c18 | 2920 | #define BS_AIPS_PACRC_TP2 (1U) //!< Bit field size in bits for AIPS_PACRC_TP2. |
mbed_official | 146:f64d43ff0c18 | 2921 | |
mbed_official | 146:f64d43ff0c18 | 2922 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2923 | //! @brief Read current value of the AIPS_PACRC_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 2924 | #define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2)) |
mbed_official | 146:f64d43ff0c18 | 2925 | #endif |
mbed_official | 146:f64d43ff0c18 | 2926 | |
mbed_official | 146:f64d43ff0c18 | 2927 | //! @brief Format value for bitfield AIPS_PACRC_TP2. |
mbed_official | 146:f64d43ff0c18 | 2928 | #define BF_AIPS_PACRC_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP2), uint32_t) & BM_AIPS_PACRC_TP2) |
mbed_official | 146:f64d43ff0c18 | 2929 | |
mbed_official | 146:f64d43ff0c18 | 2930 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2931 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2932 | #define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2933 | #endif |
mbed_official | 146:f64d43ff0c18 | 2934 | //@} |
mbed_official | 146:f64d43ff0c18 | 2935 | |
mbed_official | 146:f64d43ff0c18 | 2936 | /*! |
mbed_official | 146:f64d43ff0c18 | 2937 | * @name Register AIPS_PACRC, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 2938 | * |
mbed_official | 146:f64d43ff0c18 | 2939 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 2940 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 2941 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 2942 | * |
mbed_official | 146:f64d43ff0c18 | 2943 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2944 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 2945 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 2946 | */ |
mbed_official | 146:f64d43ff0c18 | 2947 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2948 | #define BP_AIPS_PACRC_WP2 (21U) //!< Bit position for AIPS_PACRC_WP2. |
mbed_official | 146:f64d43ff0c18 | 2949 | #define BM_AIPS_PACRC_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRC_WP2. |
mbed_official | 146:f64d43ff0c18 | 2950 | #define BS_AIPS_PACRC_WP2 (1U) //!< Bit field size in bits for AIPS_PACRC_WP2. |
mbed_official | 146:f64d43ff0c18 | 2951 | |
mbed_official | 146:f64d43ff0c18 | 2952 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2953 | //! @brief Read current value of the AIPS_PACRC_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 2954 | #define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2)) |
mbed_official | 146:f64d43ff0c18 | 2955 | #endif |
mbed_official | 146:f64d43ff0c18 | 2956 | |
mbed_official | 146:f64d43ff0c18 | 2957 | //! @brief Format value for bitfield AIPS_PACRC_WP2. |
mbed_official | 146:f64d43ff0c18 | 2958 | #define BF_AIPS_PACRC_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP2), uint32_t) & BM_AIPS_PACRC_WP2) |
mbed_official | 146:f64d43ff0c18 | 2959 | |
mbed_official | 146:f64d43ff0c18 | 2960 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2961 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2962 | #define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2963 | #endif |
mbed_official | 146:f64d43ff0c18 | 2964 | //@} |
mbed_official | 146:f64d43ff0c18 | 2965 | |
mbed_official | 146:f64d43ff0c18 | 2966 | /*! |
mbed_official | 146:f64d43ff0c18 | 2967 | * @name Register AIPS_PACRC, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 2968 | * |
mbed_official | 146:f64d43ff0c18 | 2969 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2970 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 2971 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 2972 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 2973 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 2974 | * |
mbed_official | 146:f64d43ff0c18 | 2975 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2976 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 2977 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 2978 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 2979 | */ |
mbed_official | 146:f64d43ff0c18 | 2980 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2981 | #define BP_AIPS_PACRC_SP2 (22U) //!< Bit position for AIPS_PACRC_SP2. |
mbed_official | 146:f64d43ff0c18 | 2982 | #define BM_AIPS_PACRC_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRC_SP2. |
mbed_official | 146:f64d43ff0c18 | 2983 | #define BS_AIPS_PACRC_SP2 (1U) //!< Bit field size in bits for AIPS_PACRC_SP2. |
mbed_official | 146:f64d43ff0c18 | 2984 | |
mbed_official | 146:f64d43ff0c18 | 2985 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2986 | //! @brief Read current value of the AIPS_PACRC_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 2987 | #define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2)) |
mbed_official | 146:f64d43ff0c18 | 2988 | #endif |
mbed_official | 146:f64d43ff0c18 | 2989 | |
mbed_official | 146:f64d43ff0c18 | 2990 | //! @brief Format value for bitfield AIPS_PACRC_SP2. |
mbed_official | 146:f64d43ff0c18 | 2991 | #define BF_AIPS_PACRC_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP2), uint32_t) & BM_AIPS_PACRC_SP2) |
mbed_official | 146:f64d43ff0c18 | 2992 | |
mbed_official | 146:f64d43ff0c18 | 2993 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2994 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2995 | #define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2996 | #endif |
mbed_official | 146:f64d43ff0c18 | 2997 | //@} |
mbed_official | 146:f64d43ff0c18 | 2998 | |
mbed_official | 146:f64d43ff0c18 | 2999 | /*! |
mbed_official | 146:f64d43ff0c18 | 3000 | * @name Register AIPS_PACRC, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 3001 | * |
mbed_official | 146:f64d43ff0c18 | 3002 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3003 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3004 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3005 | * |
mbed_official | 146:f64d43ff0c18 | 3006 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3007 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3008 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3009 | */ |
mbed_official | 146:f64d43ff0c18 | 3010 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3011 | #define BP_AIPS_PACRC_TP1 (24U) //!< Bit position for AIPS_PACRC_TP1. |
mbed_official | 146:f64d43ff0c18 | 3012 | #define BM_AIPS_PACRC_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRC_TP1. |
mbed_official | 146:f64d43ff0c18 | 3013 | #define BS_AIPS_PACRC_TP1 (1U) //!< Bit field size in bits for AIPS_PACRC_TP1. |
mbed_official | 146:f64d43ff0c18 | 3014 | |
mbed_official | 146:f64d43ff0c18 | 3015 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3016 | //! @brief Read current value of the AIPS_PACRC_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 3017 | #define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1)) |
mbed_official | 146:f64d43ff0c18 | 3018 | #endif |
mbed_official | 146:f64d43ff0c18 | 3019 | |
mbed_official | 146:f64d43ff0c18 | 3020 | //! @brief Format value for bitfield AIPS_PACRC_TP1. |
mbed_official | 146:f64d43ff0c18 | 3021 | #define BF_AIPS_PACRC_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP1), uint32_t) & BM_AIPS_PACRC_TP1) |
mbed_official | 146:f64d43ff0c18 | 3022 | |
mbed_official | 146:f64d43ff0c18 | 3023 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3024 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3025 | #define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3026 | #endif |
mbed_official | 146:f64d43ff0c18 | 3027 | //@} |
mbed_official | 146:f64d43ff0c18 | 3028 | |
mbed_official | 146:f64d43ff0c18 | 3029 | /*! |
mbed_official | 146:f64d43ff0c18 | 3030 | * @name Register AIPS_PACRC, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 3031 | * |
mbed_official | 146:f64d43ff0c18 | 3032 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 3033 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 3034 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3035 | * |
mbed_official | 146:f64d43ff0c18 | 3036 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3037 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3038 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3039 | */ |
mbed_official | 146:f64d43ff0c18 | 3040 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3041 | #define BP_AIPS_PACRC_WP1 (25U) //!< Bit position for AIPS_PACRC_WP1. |
mbed_official | 146:f64d43ff0c18 | 3042 | #define BM_AIPS_PACRC_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRC_WP1. |
mbed_official | 146:f64d43ff0c18 | 3043 | #define BS_AIPS_PACRC_WP1 (1U) //!< Bit field size in bits for AIPS_PACRC_WP1. |
mbed_official | 146:f64d43ff0c18 | 3044 | |
mbed_official | 146:f64d43ff0c18 | 3045 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3046 | //! @brief Read current value of the AIPS_PACRC_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 3047 | #define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1)) |
mbed_official | 146:f64d43ff0c18 | 3048 | #endif |
mbed_official | 146:f64d43ff0c18 | 3049 | |
mbed_official | 146:f64d43ff0c18 | 3050 | //! @brief Format value for bitfield AIPS_PACRC_WP1. |
mbed_official | 146:f64d43ff0c18 | 3051 | #define BF_AIPS_PACRC_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP1), uint32_t) & BM_AIPS_PACRC_WP1) |
mbed_official | 146:f64d43ff0c18 | 3052 | |
mbed_official | 146:f64d43ff0c18 | 3053 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3054 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3055 | #define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3056 | #endif |
mbed_official | 146:f64d43ff0c18 | 3057 | //@} |
mbed_official | 146:f64d43ff0c18 | 3058 | |
mbed_official | 146:f64d43ff0c18 | 3059 | /*! |
mbed_official | 146:f64d43ff0c18 | 3060 | * @name Register AIPS_PACRC, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 3061 | * |
mbed_official | 146:f64d43ff0c18 | 3062 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3063 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3064 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3065 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3066 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3067 | * |
mbed_official | 146:f64d43ff0c18 | 3068 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3069 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3070 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3071 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3072 | */ |
mbed_official | 146:f64d43ff0c18 | 3073 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3074 | #define BP_AIPS_PACRC_SP1 (26U) //!< Bit position for AIPS_PACRC_SP1. |
mbed_official | 146:f64d43ff0c18 | 3075 | #define BM_AIPS_PACRC_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRC_SP1. |
mbed_official | 146:f64d43ff0c18 | 3076 | #define BS_AIPS_PACRC_SP1 (1U) //!< Bit field size in bits for AIPS_PACRC_SP1. |
mbed_official | 146:f64d43ff0c18 | 3077 | |
mbed_official | 146:f64d43ff0c18 | 3078 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3079 | //! @brief Read current value of the AIPS_PACRC_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 3080 | #define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1)) |
mbed_official | 146:f64d43ff0c18 | 3081 | #endif |
mbed_official | 146:f64d43ff0c18 | 3082 | |
mbed_official | 146:f64d43ff0c18 | 3083 | //! @brief Format value for bitfield AIPS_PACRC_SP1. |
mbed_official | 146:f64d43ff0c18 | 3084 | #define BF_AIPS_PACRC_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP1), uint32_t) & BM_AIPS_PACRC_SP1) |
mbed_official | 146:f64d43ff0c18 | 3085 | |
mbed_official | 146:f64d43ff0c18 | 3086 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3087 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3088 | #define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3089 | #endif |
mbed_official | 146:f64d43ff0c18 | 3090 | //@} |
mbed_official | 146:f64d43ff0c18 | 3091 | |
mbed_official | 146:f64d43ff0c18 | 3092 | /*! |
mbed_official | 146:f64d43ff0c18 | 3093 | * @name Register AIPS_PACRC, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 3094 | * |
mbed_official | 146:f64d43ff0c18 | 3095 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3096 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3097 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3098 | * |
mbed_official | 146:f64d43ff0c18 | 3099 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3100 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3101 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3102 | */ |
mbed_official | 146:f64d43ff0c18 | 3103 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3104 | #define BP_AIPS_PACRC_TP0 (28U) //!< Bit position for AIPS_PACRC_TP0. |
mbed_official | 146:f64d43ff0c18 | 3105 | #define BM_AIPS_PACRC_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRC_TP0. |
mbed_official | 146:f64d43ff0c18 | 3106 | #define BS_AIPS_PACRC_TP0 (1U) //!< Bit field size in bits for AIPS_PACRC_TP0. |
mbed_official | 146:f64d43ff0c18 | 3107 | |
mbed_official | 146:f64d43ff0c18 | 3108 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3109 | //! @brief Read current value of the AIPS_PACRC_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 3110 | #define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0)) |
mbed_official | 146:f64d43ff0c18 | 3111 | #endif |
mbed_official | 146:f64d43ff0c18 | 3112 | |
mbed_official | 146:f64d43ff0c18 | 3113 | //! @brief Format value for bitfield AIPS_PACRC_TP0. |
mbed_official | 146:f64d43ff0c18 | 3114 | #define BF_AIPS_PACRC_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP0), uint32_t) & BM_AIPS_PACRC_TP0) |
mbed_official | 146:f64d43ff0c18 | 3115 | |
mbed_official | 146:f64d43ff0c18 | 3116 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3117 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3118 | #define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3119 | #endif |
mbed_official | 146:f64d43ff0c18 | 3120 | //@} |
mbed_official | 146:f64d43ff0c18 | 3121 | |
mbed_official | 146:f64d43ff0c18 | 3122 | /*! |
mbed_official | 146:f64d43ff0c18 | 3123 | * @name Register AIPS_PACRC, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 3124 | * |
mbed_official | 146:f64d43ff0c18 | 3125 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 3126 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 3127 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3128 | * |
mbed_official | 146:f64d43ff0c18 | 3129 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3130 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3131 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3132 | */ |
mbed_official | 146:f64d43ff0c18 | 3133 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3134 | #define BP_AIPS_PACRC_WP0 (29U) //!< Bit position for AIPS_PACRC_WP0. |
mbed_official | 146:f64d43ff0c18 | 3135 | #define BM_AIPS_PACRC_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRC_WP0. |
mbed_official | 146:f64d43ff0c18 | 3136 | #define BS_AIPS_PACRC_WP0 (1U) //!< Bit field size in bits for AIPS_PACRC_WP0. |
mbed_official | 146:f64d43ff0c18 | 3137 | |
mbed_official | 146:f64d43ff0c18 | 3138 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3139 | //! @brief Read current value of the AIPS_PACRC_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 3140 | #define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0)) |
mbed_official | 146:f64d43ff0c18 | 3141 | #endif |
mbed_official | 146:f64d43ff0c18 | 3142 | |
mbed_official | 146:f64d43ff0c18 | 3143 | //! @brief Format value for bitfield AIPS_PACRC_WP0. |
mbed_official | 146:f64d43ff0c18 | 3144 | #define BF_AIPS_PACRC_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP0), uint32_t) & BM_AIPS_PACRC_WP0) |
mbed_official | 146:f64d43ff0c18 | 3145 | |
mbed_official | 146:f64d43ff0c18 | 3146 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3147 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3148 | #define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3149 | #endif |
mbed_official | 146:f64d43ff0c18 | 3150 | //@} |
mbed_official | 146:f64d43ff0c18 | 3151 | |
mbed_official | 146:f64d43ff0c18 | 3152 | /*! |
mbed_official | 146:f64d43ff0c18 | 3153 | * @name Register AIPS_PACRC, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 3154 | * |
mbed_official | 146:f64d43ff0c18 | 3155 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3156 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3157 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3158 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3159 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3160 | * |
mbed_official | 146:f64d43ff0c18 | 3161 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3162 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3163 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3164 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3165 | */ |
mbed_official | 146:f64d43ff0c18 | 3166 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3167 | #define BP_AIPS_PACRC_SP0 (30U) //!< Bit position for AIPS_PACRC_SP0. |
mbed_official | 146:f64d43ff0c18 | 3168 | #define BM_AIPS_PACRC_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRC_SP0. |
mbed_official | 146:f64d43ff0c18 | 3169 | #define BS_AIPS_PACRC_SP0 (1U) //!< Bit field size in bits for AIPS_PACRC_SP0. |
mbed_official | 146:f64d43ff0c18 | 3170 | |
mbed_official | 146:f64d43ff0c18 | 3171 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3172 | //! @brief Read current value of the AIPS_PACRC_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 3173 | #define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0)) |
mbed_official | 146:f64d43ff0c18 | 3174 | #endif |
mbed_official | 146:f64d43ff0c18 | 3175 | |
mbed_official | 146:f64d43ff0c18 | 3176 | //! @brief Format value for bitfield AIPS_PACRC_SP0. |
mbed_official | 146:f64d43ff0c18 | 3177 | #define BF_AIPS_PACRC_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP0), uint32_t) & BM_AIPS_PACRC_SP0) |
mbed_official | 146:f64d43ff0c18 | 3178 | |
mbed_official | 146:f64d43ff0c18 | 3179 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3180 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3181 | #define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3182 | #endif |
mbed_official | 146:f64d43ff0c18 | 3183 | //@} |
mbed_official | 146:f64d43ff0c18 | 3184 | |
mbed_official | 146:f64d43ff0c18 | 3185 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3186 | // HW_AIPS_PACRD - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 3187 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3188 | |
mbed_official | 146:f64d43ff0c18 | 3189 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3190 | /*! |
mbed_official | 146:f64d43ff0c18 | 3191 | * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 3192 | * |
mbed_official | 146:f64d43ff0c18 | 3193 | * Reset value: 0x00000004U |
mbed_official | 146:f64d43ff0c18 | 3194 | * |
mbed_official | 146:f64d43ff0c18 | 3195 | * Each PACR register consists of eight 4-bit PACR fields. Each PACR field |
mbed_official | 146:f64d43ff0c18 | 3196 | * defines the access levels for a particular peripheral. The mapping between a |
mbed_official | 146:f64d43ff0c18 | 3197 | * peripheral and its PACR field is shown in the table below. The peripheral assignment |
mbed_official | 146:f64d43ff0c18 | 3198 | * to each PACR is defined by the memory map slot that the peripheral is |
mbed_official | 146:f64d43ff0c18 | 3199 | * assigned to. See this chip's memory map for the assignment of a particular |
mbed_official | 146:f64d43ff0c18 | 3200 | * peripheral. The following table shows the location of each peripheral slot's PACR field |
mbed_official | 146:f64d43ff0c18 | 3201 | * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] |
mbed_official | 146:f64d43ff0c18 | 3202 | * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 |
mbed_official | 146:f64d43ff0c18 | 3203 | * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC |
mbed_official | 146:f64d43ff0c18 | 3204 | * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 |
mbed_official | 146:f64d43ff0c18 | 3205 | * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 |
mbed_official | 146:f64d43ff0c18 | 3206 | * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 |
mbed_official | 146:f64d43ff0c18 | 3207 | * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 |
mbed_official | 146:f64d43ff0c18 | 3208 | * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH |
mbed_official | 146:f64d43ff0c18 | 3209 | * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 |
mbed_official | 146:f64d43ff0c18 | 3210 | * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 |
mbed_official | 146:f64d43ff0c18 | 3211 | * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 |
mbed_official | 146:f64d43ff0c18 | 3212 | * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 |
mbed_official | 146:f64d43ff0c18 | 3213 | * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 |
mbed_official | 146:f64d43ff0c18 | 3214 | * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 |
mbed_official | 146:f64d43ff0c18 | 3215 | * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 |
mbed_official | 146:f64d43ff0c18 | 3216 | * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 |
mbed_official | 146:f64d43ff0c18 | 3217 | * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR |
mbed_official | 146:f64d43ff0c18 | 3218 | * A-D, which control peripheral slots 0-31, are shown below. The following |
mbed_official | 146:f64d43ff0c18 | 3219 | * section, PACRPeripheral Access Control Register , shows the register field |
mbed_official | 146:f64d43ff0c18 | 3220 | * descriptions for PACR E-P. All PACR registers are identical. They are divided into two |
mbed_official | 146:f64d43ff0c18 | 3221 | * sections because they occupy two non-contiguous address spaces. |
mbed_official | 146:f64d43ff0c18 | 3222 | */ |
mbed_official | 146:f64d43ff0c18 | 3223 | typedef union _hw_aips_pacrd |
mbed_official | 146:f64d43ff0c18 | 3224 | { |
mbed_official | 146:f64d43ff0c18 | 3225 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 3226 | struct _hw_aips_pacrd_bitfields |
mbed_official | 146:f64d43ff0c18 | 3227 | { |
mbed_official | 146:f64d43ff0c18 | 3228 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3229 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3230 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3231 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 3232 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3233 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3234 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3235 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 3236 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3237 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3238 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3239 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 3240 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3241 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3242 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3243 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 3244 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3245 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3246 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3247 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 3248 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3249 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3250 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3251 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 3252 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3253 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3254 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3255 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 3256 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 3257 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 3258 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 3259 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 3260 | } B; |
mbed_official | 146:f64d43ff0c18 | 3261 | } hw_aips_pacrd_t; |
mbed_official | 146:f64d43ff0c18 | 3262 | #endif |
mbed_official | 146:f64d43ff0c18 | 3263 | |
mbed_official | 146:f64d43ff0c18 | 3264 | /*! |
mbed_official | 146:f64d43ff0c18 | 3265 | * @name Constants and macros for entire AIPS_PACRD register |
mbed_official | 146:f64d43ff0c18 | 3266 | */ |
mbed_official | 146:f64d43ff0c18 | 3267 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3268 | #define HW_AIPS_PACRD_ADDR(x) (REGS_AIPS_BASE(x) + 0x2CU) |
mbed_official | 146:f64d43ff0c18 | 3269 | |
mbed_official | 146:f64d43ff0c18 | 3270 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3271 | #define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3272 | #define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U) |
mbed_official | 146:f64d43ff0c18 | 3273 | #define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3274 | #define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3275 | #define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3276 | #define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3277 | #endif |
mbed_official | 146:f64d43ff0c18 | 3278 | //@} |
mbed_official | 146:f64d43ff0c18 | 3279 | |
mbed_official | 146:f64d43ff0c18 | 3280 | /* |
mbed_official | 146:f64d43ff0c18 | 3281 | * Constants & macros for individual AIPS_PACRD bitfields |
mbed_official | 146:f64d43ff0c18 | 3282 | */ |
mbed_official | 146:f64d43ff0c18 | 3283 | |
mbed_official | 146:f64d43ff0c18 | 3284 | /*! |
mbed_official | 146:f64d43ff0c18 | 3285 | * @name Register AIPS_PACRD, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3286 | * |
mbed_official | 146:f64d43ff0c18 | 3287 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3288 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3289 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3290 | * |
mbed_official | 146:f64d43ff0c18 | 3291 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3292 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3293 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3294 | */ |
mbed_official | 146:f64d43ff0c18 | 3295 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3296 | #define BP_AIPS_PACRD_TP7 (0U) //!< Bit position for AIPS_PACRD_TP7. |
mbed_official | 146:f64d43ff0c18 | 3297 | #define BM_AIPS_PACRD_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRD_TP7. |
mbed_official | 146:f64d43ff0c18 | 3298 | #define BS_AIPS_PACRD_TP7 (1U) //!< Bit field size in bits for AIPS_PACRD_TP7. |
mbed_official | 146:f64d43ff0c18 | 3299 | |
mbed_official | 146:f64d43ff0c18 | 3300 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3301 | //! @brief Read current value of the AIPS_PACRD_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 3302 | #define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7)) |
mbed_official | 146:f64d43ff0c18 | 3303 | #endif |
mbed_official | 146:f64d43ff0c18 | 3304 | |
mbed_official | 146:f64d43ff0c18 | 3305 | //! @brief Format value for bitfield AIPS_PACRD_TP7. |
mbed_official | 146:f64d43ff0c18 | 3306 | #define BF_AIPS_PACRD_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP7), uint32_t) & BM_AIPS_PACRD_TP7) |
mbed_official | 146:f64d43ff0c18 | 3307 | |
mbed_official | 146:f64d43ff0c18 | 3308 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3309 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3310 | #define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3311 | #endif |
mbed_official | 146:f64d43ff0c18 | 3312 | //@} |
mbed_official | 146:f64d43ff0c18 | 3313 | |
mbed_official | 146:f64d43ff0c18 | 3314 | /*! |
mbed_official | 146:f64d43ff0c18 | 3315 | * @name Register AIPS_PACRD, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 3316 | * |
mbed_official | 146:f64d43ff0c18 | 3317 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 3318 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 3319 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3320 | * |
mbed_official | 146:f64d43ff0c18 | 3321 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3322 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3323 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3324 | */ |
mbed_official | 146:f64d43ff0c18 | 3325 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3326 | #define BP_AIPS_PACRD_WP7 (1U) //!< Bit position for AIPS_PACRD_WP7. |
mbed_official | 146:f64d43ff0c18 | 3327 | #define BM_AIPS_PACRD_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRD_WP7. |
mbed_official | 146:f64d43ff0c18 | 3328 | #define BS_AIPS_PACRD_WP7 (1U) //!< Bit field size in bits for AIPS_PACRD_WP7. |
mbed_official | 146:f64d43ff0c18 | 3329 | |
mbed_official | 146:f64d43ff0c18 | 3330 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3331 | //! @brief Read current value of the AIPS_PACRD_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 3332 | #define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7)) |
mbed_official | 146:f64d43ff0c18 | 3333 | #endif |
mbed_official | 146:f64d43ff0c18 | 3334 | |
mbed_official | 146:f64d43ff0c18 | 3335 | //! @brief Format value for bitfield AIPS_PACRD_WP7. |
mbed_official | 146:f64d43ff0c18 | 3336 | #define BF_AIPS_PACRD_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP7), uint32_t) & BM_AIPS_PACRD_WP7) |
mbed_official | 146:f64d43ff0c18 | 3337 | |
mbed_official | 146:f64d43ff0c18 | 3338 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3339 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3340 | #define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3341 | #endif |
mbed_official | 146:f64d43ff0c18 | 3342 | //@} |
mbed_official | 146:f64d43ff0c18 | 3343 | |
mbed_official | 146:f64d43ff0c18 | 3344 | /*! |
mbed_official | 146:f64d43ff0c18 | 3345 | * @name Register AIPS_PACRD, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 3346 | * |
mbed_official | 146:f64d43ff0c18 | 3347 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3348 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3349 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3350 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3351 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3352 | * |
mbed_official | 146:f64d43ff0c18 | 3353 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3354 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3355 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3356 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3357 | */ |
mbed_official | 146:f64d43ff0c18 | 3358 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3359 | #define BP_AIPS_PACRD_SP7 (2U) //!< Bit position for AIPS_PACRD_SP7. |
mbed_official | 146:f64d43ff0c18 | 3360 | #define BM_AIPS_PACRD_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRD_SP7. |
mbed_official | 146:f64d43ff0c18 | 3361 | #define BS_AIPS_PACRD_SP7 (1U) //!< Bit field size in bits for AIPS_PACRD_SP7. |
mbed_official | 146:f64d43ff0c18 | 3362 | |
mbed_official | 146:f64d43ff0c18 | 3363 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3364 | //! @brief Read current value of the AIPS_PACRD_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 3365 | #define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7)) |
mbed_official | 146:f64d43ff0c18 | 3366 | #endif |
mbed_official | 146:f64d43ff0c18 | 3367 | |
mbed_official | 146:f64d43ff0c18 | 3368 | //! @brief Format value for bitfield AIPS_PACRD_SP7. |
mbed_official | 146:f64d43ff0c18 | 3369 | #define BF_AIPS_PACRD_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP7), uint32_t) & BM_AIPS_PACRD_SP7) |
mbed_official | 146:f64d43ff0c18 | 3370 | |
mbed_official | 146:f64d43ff0c18 | 3371 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3372 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3373 | #define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3374 | #endif |
mbed_official | 146:f64d43ff0c18 | 3375 | //@} |
mbed_official | 146:f64d43ff0c18 | 3376 | |
mbed_official | 146:f64d43ff0c18 | 3377 | /*! |
mbed_official | 146:f64d43ff0c18 | 3378 | * @name Register AIPS_PACRD, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 3379 | * |
mbed_official | 146:f64d43ff0c18 | 3380 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3381 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3382 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3383 | * |
mbed_official | 146:f64d43ff0c18 | 3384 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3385 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3386 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3387 | */ |
mbed_official | 146:f64d43ff0c18 | 3388 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3389 | #define BP_AIPS_PACRD_TP6 (4U) //!< Bit position for AIPS_PACRD_TP6. |
mbed_official | 146:f64d43ff0c18 | 3390 | #define BM_AIPS_PACRD_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRD_TP6. |
mbed_official | 146:f64d43ff0c18 | 3391 | #define BS_AIPS_PACRD_TP6 (1U) //!< Bit field size in bits for AIPS_PACRD_TP6. |
mbed_official | 146:f64d43ff0c18 | 3392 | |
mbed_official | 146:f64d43ff0c18 | 3393 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3394 | //! @brief Read current value of the AIPS_PACRD_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 3395 | #define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6)) |
mbed_official | 146:f64d43ff0c18 | 3396 | #endif |
mbed_official | 146:f64d43ff0c18 | 3397 | |
mbed_official | 146:f64d43ff0c18 | 3398 | //! @brief Format value for bitfield AIPS_PACRD_TP6. |
mbed_official | 146:f64d43ff0c18 | 3399 | #define BF_AIPS_PACRD_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP6), uint32_t) & BM_AIPS_PACRD_TP6) |
mbed_official | 146:f64d43ff0c18 | 3400 | |
mbed_official | 146:f64d43ff0c18 | 3401 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3402 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3403 | #define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3404 | #endif |
mbed_official | 146:f64d43ff0c18 | 3405 | //@} |
mbed_official | 146:f64d43ff0c18 | 3406 | |
mbed_official | 146:f64d43ff0c18 | 3407 | /*! |
mbed_official | 146:f64d43ff0c18 | 3408 | * @name Register AIPS_PACRD, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 3409 | * |
mbed_official | 146:f64d43ff0c18 | 3410 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 3411 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 3412 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3413 | * |
mbed_official | 146:f64d43ff0c18 | 3414 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3415 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3416 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3417 | */ |
mbed_official | 146:f64d43ff0c18 | 3418 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3419 | #define BP_AIPS_PACRD_WP6 (5U) //!< Bit position for AIPS_PACRD_WP6. |
mbed_official | 146:f64d43ff0c18 | 3420 | #define BM_AIPS_PACRD_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRD_WP6. |
mbed_official | 146:f64d43ff0c18 | 3421 | #define BS_AIPS_PACRD_WP6 (1U) //!< Bit field size in bits for AIPS_PACRD_WP6. |
mbed_official | 146:f64d43ff0c18 | 3422 | |
mbed_official | 146:f64d43ff0c18 | 3423 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3424 | //! @brief Read current value of the AIPS_PACRD_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 3425 | #define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6)) |
mbed_official | 146:f64d43ff0c18 | 3426 | #endif |
mbed_official | 146:f64d43ff0c18 | 3427 | |
mbed_official | 146:f64d43ff0c18 | 3428 | //! @brief Format value for bitfield AIPS_PACRD_WP6. |
mbed_official | 146:f64d43ff0c18 | 3429 | #define BF_AIPS_PACRD_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP6), uint32_t) & BM_AIPS_PACRD_WP6) |
mbed_official | 146:f64d43ff0c18 | 3430 | |
mbed_official | 146:f64d43ff0c18 | 3431 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3432 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3433 | #define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3434 | #endif |
mbed_official | 146:f64d43ff0c18 | 3435 | //@} |
mbed_official | 146:f64d43ff0c18 | 3436 | |
mbed_official | 146:f64d43ff0c18 | 3437 | /*! |
mbed_official | 146:f64d43ff0c18 | 3438 | * @name Register AIPS_PACRD, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 3439 | * |
mbed_official | 146:f64d43ff0c18 | 3440 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3441 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3442 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3443 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3444 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3445 | * |
mbed_official | 146:f64d43ff0c18 | 3446 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3447 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3448 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3449 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3450 | */ |
mbed_official | 146:f64d43ff0c18 | 3451 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3452 | #define BP_AIPS_PACRD_SP6 (6U) //!< Bit position for AIPS_PACRD_SP6. |
mbed_official | 146:f64d43ff0c18 | 3453 | #define BM_AIPS_PACRD_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRD_SP6. |
mbed_official | 146:f64d43ff0c18 | 3454 | #define BS_AIPS_PACRD_SP6 (1U) //!< Bit field size in bits for AIPS_PACRD_SP6. |
mbed_official | 146:f64d43ff0c18 | 3455 | |
mbed_official | 146:f64d43ff0c18 | 3456 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3457 | //! @brief Read current value of the AIPS_PACRD_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 3458 | #define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6)) |
mbed_official | 146:f64d43ff0c18 | 3459 | #endif |
mbed_official | 146:f64d43ff0c18 | 3460 | |
mbed_official | 146:f64d43ff0c18 | 3461 | //! @brief Format value for bitfield AIPS_PACRD_SP6. |
mbed_official | 146:f64d43ff0c18 | 3462 | #define BF_AIPS_PACRD_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP6), uint32_t) & BM_AIPS_PACRD_SP6) |
mbed_official | 146:f64d43ff0c18 | 3463 | |
mbed_official | 146:f64d43ff0c18 | 3464 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3465 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3466 | #define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3467 | #endif |
mbed_official | 146:f64d43ff0c18 | 3468 | //@} |
mbed_official | 146:f64d43ff0c18 | 3469 | |
mbed_official | 146:f64d43ff0c18 | 3470 | /*! |
mbed_official | 146:f64d43ff0c18 | 3471 | * @name Register AIPS_PACRD, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 3472 | * |
mbed_official | 146:f64d43ff0c18 | 3473 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3474 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3475 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3476 | * |
mbed_official | 146:f64d43ff0c18 | 3477 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3478 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3479 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3480 | */ |
mbed_official | 146:f64d43ff0c18 | 3481 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3482 | #define BP_AIPS_PACRD_TP5 (8U) //!< Bit position for AIPS_PACRD_TP5. |
mbed_official | 146:f64d43ff0c18 | 3483 | #define BM_AIPS_PACRD_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRD_TP5. |
mbed_official | 146:f64d43ff0c18 | 3484 | #define BS_AIPS_PACRD_TP5 (1U) //!< Bit field size in bits for AIPS_PACRD_TP5. |
mbed_official | 146:f64d43ff0c18 | 3485 | |
mbed_official | 146:f64d43ff0c18 | 3486 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3487 | //! @brief Read current value of the AIPS_PACRD_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 3488 | #define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5)) |
mbed_official | 146:f64d43ff0c18 | 3489 | #endif |
mbed_official | 146:f64d43ff0c18 | 3490 | |
mbed_official | 146:f64d43ff0c18 | 3491 | //! @brief Format value for bitfield AIPS_PACRD_TP5. |
mbed_official | 146:f64d43ff0c18 | 3492 | #define BF_AIPS_PACRD_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP5), uint32_t) & BM_AIPS_PACRD_TP5) |
mbed_official | 146:f64d43ff0c18 | 3493 | |
mbed_official | 146:f64d43ff0c18 | 3494 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3495 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3496 | #define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3497 | #endif |
mbed_official | 146:f64d43ff0c18 | 3498 | //@} |
mbed_official | 146:f64d43ff0c18 | 3499 | |
mbed_official | 146:f64d43ff0c18 | 3500 | /*! |
mbed_official | 146:f64d43ff0c18 | 3501 | * @name Register AIPS_PACRD, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 3502 | * |
mbed_official | 146:f64d43ff0c18 | 3503 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 3504 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 3505 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3506 | * |
mbed_official | 146:f64d43ff0c18 | 3507 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3508 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3509 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3510 | */ |
mbed_official | 146:f64d43ff0c18 | 3511 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3512 | #define BP_AIPS_PACRD_WP5 (9U) //!< Bit position for AIPS_PACRD_WP5. |
mbed_official | 146:f64d43ff0c18 | 3513 | #define BM_AIPS_PACRD_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRD_WP5. |
mbed_official | 146:f64d43ff0c18 | 3514 | #define BS_AIPS_PACRD_WP5 (1U) //!< Bit field size in bits for AIPS_PACRD_WP5. |
mbed_official | 146:f64d43ff0c18 | 3515 | |
mbed_official | 146:f64d43ff0c18 | 3516 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3517 | //! @brief Read current value of the AIPS_PACRD_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 3518 | #define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5)) |
mbed_official | 146:f64d43ff0c18 | 3519 | #endif |
mbed_official | 146:f64d43ff0c18 | 3520 | |
mbed_official | 146:f64d43ff0c18 | 3521 | //! @brief Format value for bitfield AIPS_PACRD_WP5. |
mbed_official | 146:f64d43ff0c18 | 3522 | #define BF_AIPS_PACRD_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP5), uint32_t) & BM_AIPS_PACRD_WP5) |
mbed_official | 146:f64d43ff0c18 | 3523 | |
mbed_official | 146:f64d43ff0c18 | 3524 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3525 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3526 | #define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3527 | #endif |
mbed_official | 146:f64d43ff0c18 | 3528 | //@} |
mbed_official | 146:f64d43ff0c18 | 3529 | |
mbed_official | 146:f64d43ff0c18 | 3530 | /*! |
mbed_official | 146:f64d43ff0c18 | 3531 | * @name Register AIPS_PACRD, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 3532 | * |
mbed_official | 146:f64d43ff0c18 | 3533 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3534 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3535 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3536 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3537 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3538 | * |
mbed_official | 146:f64d43ff0c18 | 3539 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3540 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3541 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3542 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3543 | */ |
mbed_official | 146:f64d43ff0c18 | 3544 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3545 | #define BP_AIPS_PACRD_SP5 (10U) //!< Bit position for AIPS_PACRD_SP5. |
mbed_official | 146:f64d43ff0c18 | 3546 | #define BM_AIPS_PACRD_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRD_SP5. |
mbed_official | 146:f64d43ff0c18 | 3547 | #define BS_AIPS_PACRD_SP5 (1U) //!< Bit field size in bits for AIPS_PACRD_SP5. |
mbed_official | 146:f64d43ff0c18 | 3548 | |
mbed_official | 146:f64d43ff0c18 | 3549 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3550 | //! @brief Read current value of the AIPS_PACRD_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 3551 | #define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5)) |
mbed_official | 146:f64d43ff0c18 | 3552 | #endif |
mbed_official | 146:f64d43ff0c18 | 3553 | |
mbed_official | 146:f64d43ff0c18 | 3554 | //! @brief Format value for bitfield AIPS_PACRD_SP5. |
mbed_official | 146:f64d43ff0c18 | 3555 | #define BF_AIPS_PACRD_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP5), uint32_t) & BM_AIPS_PACRD_SP5) |
mbed_official | 146:f64d43ff0c18 | 3556 | |
mbed_official | 146:f64d43ff0c18 | 3557 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3558 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3559 | #define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3560 | #endif |
mbed_official | 146:f64d43ff0c18 | 3561 | //@} |
mbed_official | 146:f64d43ff0c18 | 3562 | |
mbed_official | 146:f64d43ff0c18 | 3563 | /*! |
mbed_official | 146:f64d43ff0c18 | 3564 | * @name Register AIPS_PACRD, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 3565 | * |
mbed_official | 146:f64d43ff0c18 | 3566 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3567 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3568 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3569 | * |
mbed_official | 146:f64d43ff0c18 | 3570 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3571 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3572 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3573 | */ |
mbed_official | 146:f64d43ff0c18 | 3574 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3575 | #define BP_AIPS_PACRD_TP4 (12U) //!< Bit position for AIPS_PACRD_TP4. |
mbed_official | 146:f64d43ff0c18 | 3576 | #define BM_AIPS_PACRD_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRD_TP4. |
mbed_official | 146:f64d43ff0c18 | 3577 | #define BS_AIPS_PACRD_TP4 (1U) //!< Bit field size in bits for AIPS_PACRD_TP4. |
mbed_official | 146:f64d43ff0c18 | 3578 | |
mbed_official | 146:f64d43ff0c18 | 3579 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3580 | //! @brief Read current value of the AIPS_PACRD_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 3581 | #define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4)) |
mbed_official | 146:f64d43ff0c18 | 3582 | #endif |
mbed_official | 146:f64d43ff0c18 | 3583 | |
mbed_official | 146:f64d43ff0c18 | 3584 | //! @brief Format value for bitfield AIPS_PACRD_TP4. |
mbed_official | 146:f64d43ff0c18 | 3585 | #define BF_AIPS_PACRD_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP4), uint32_t) & BM_AIPS_PACRD_TP4) |
mbed_official | 146:f64d43ff0c18 | 3586 | |
mbed_official | 146:f64d43ff0c18 | 3587 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3588 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3589 | #define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3590 | #endif |
mbed_official | 146:f64d43ff0c18 | 3591 | //@} |
mbed_official | 146:f64d43ff0c18 | 3592 | |
mbed_official | 146:f64d43ff0c18 | 3593 | /*! |
mbed_official | 146:f64d43ff0c18 | 3594 | * @name Register AIPS_PACRD, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 3595 | * |
mbed_official | 146:f64d43ff0c18 | 3596 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 3597 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 3598 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3599 | * |
mbed_official | 146:f64d43ff0c18 | 3600 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3601 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3602 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3603 | */ |
mbed_official | 146:f64d43ff0c18 | 3604 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3605 | #define BP_AIPS_PACRD_WP4 (13U) //!< Bit position for AIPS_PACRD_WP4. |
mbed_official | 146:f64d43ff0c18 | 3606 | #define BM_AIPS_PACRD_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRD_WP4. |
mbed_official | 146:f64d43ff0c18 | 3607 | #define BS_AIPS_PACRD_WP4 (1U) //!< Bit field size in bits for AIPS_PACRD_WP4. |
mbed_official | 146:f64d43ff0c18 | 3608 | |
mbed_official | 146:f64d43ff0c18 | 3609 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3610 | //! @brief Read current value of the AIPS_PACRD_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 3611 | #define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4)) |
mbed_official | 146:f64d43ff0c18 | 3612 | #endif |
mbed_official | 146:f64d43ff0c18 | 3613 | |
mbed_official | 146:f64d43ff0c18 | 3614 | //! @brief Format value for bitfield AIPS_PACRD_WP4. |
mbed_official | 146:f64d43ff0c18 | 3615 | #define BF_AIPS_PACRD_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP4), uint32_t) & BM_AIPS_PACRD_WP4) |
mbed_official | 146:f64d43ff0c18 | 3616 | |
mbed_official | 146:f64d43ff0c18 | 3617 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3618 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3619 | #define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3620 | #endif |
mbed_official | 146:f64d43ff0c18 | 3621 | //@} |
mbed_official | 146:f64d43ff0c18 | 3622 | |
mbed_official | 146:f64d43ff0c18 | 3623 | /*! |
mbed_official | 146:f64d43ff0c18 | 3624 | * @name Register AIPS_PACRD, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 3625 | * |
mbed_official | 146:f64d43ff0c18 | 3626 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3627 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3628 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3629 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3630 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3631 | * |
mbed_official | 146:f64d43ff0c18 | 3632 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3633 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3634 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3635 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3636 | */ |
mbed_official | 146:f64d43ff0c18 | 3637 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3638 | #define BP_AIPS_PACRD_SP4 (14U) //!< Bit position for AIPS_PACRD_SP4. |
mbed_official | 146:f64d43ff0c18 | 3639 | #define BM_AIPS_PACRD_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRD_SP4. |
mbed_official | 146:f64d43ff0c18 | 3640 | #define BS_AIPS_PACRD_SP4 (1U) //!< Bit field size in bits for AIPS_PACRD_SP4. |
mbed_official | 146:f64d43ff0c18 | 3641 | |
mbed_official | 146:f64d43ff0c18 | 3642 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3643 | //! @brief Read current value of the AIPS_PACRD_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 3644 | #define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4)) |
mbed_official | 146:f64d43ff0c18 | 3645 | #endif |
mbed_official | 146:f64d43ff0c18 | 3646 | |
mbed_official | 146:f64d43ff0c18 | 3647 | //! @brief Format value for bitfield AIPS_PACRD_SP4. |
mbed_official | 146:f64d43ff0c18 | 3648 | #define BF_AIPS_PACRD_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP4), uint32_t) & BM_AIPS_PACRD_SP4) |
mbed_official | 146:f64d43ff0c18 | 3649 | |
mbed_official | 146:f64d43ff0c18 | 3650 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3651 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3652 | #define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3653 | #endif |
mbed_official | 146:f64d43ff0c18 | 3654 | //@} |
mbed_official | 146:f64d43ff0c18 | 3655 | |
mbed_official | 146:f64d43ff0c18 | 3656 | /*! |
mbed_official | 146:f64d43ff0c18 | 3657 | * @name Register AIPS_PACRD, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 3658 | * |
mbed_official | 146:f64d43ff0c18 | 3659 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3660 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3661 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3662 | * |
mbed_official | 146:f64d43ff0c18 | 3663 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3664 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3665 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3666 | */ |
mbed_official | 146:f64d43ff0c18 | 3667 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3668 | #define BP_AIPS_PACRD_TP3 (16U) //!< Bit position for AIPS_PACRD_TP3. |
mbed_official | 146:f64d43ff0c18 | 3669 | #define BM_AIPS_PACRD_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRD_TP3. |
mbed_official | 146:f64d43ff0c18 | 3670 | #define BS_AIPS_PACRD_TP3 (1U) //!< Bit field size in bits for AIPS_PACRD_TP3. |
mbed_official | 146:f64d43ff0c18 | 3671 | |
mbed_official | 146:f64d43ff0c18 | 3672 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3673 | //! @brief Read current value of the AIPS_PACRD_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 3674 | #define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3)) |
mbed_official | 146:f64d43ff0c18 | 3675 | #endif |
mbed_official | 146:f64d43ff0c18 | 3676 | |
mbed_official | 146:f64d43ff0c18 | 3677 | //! @brief Format value for bitfield AIPS_PACRD_TP3. |
mbed_official | 146:f64d43ff0c18 | 3678 | #define BF_AIPS_PACRD_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP3), uint32_t) & BM_AIPS_PACRD_TP3) |
mbed_official | 146:f64d43ff0c18 | 3679 | |
mbed_official | 146:f64d43ff0c18 | 3680 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3681 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3682 | #define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3683 | #endif |
mbed_official | 146:f64d43ff0c18 | 3684 | //@} |
mbed_official | 146:f64d43ff0c18 | 3685 | |
mbed_official | 146:f64d43ff0c18 | 3686 | /*! |
mbed_official | 146:f64d43ff0c18 | 3687 | * @name Register AIPS_PACRD, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 3688 | * |
mbed_official | 146:f64d43ff0c18 | 3689 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 3690 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 3691 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3692 | * |
mbed_official | 146:f64d43ff0c18 | 3693 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3694 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3695 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3696 | */ |
mbed_official | 146:f64d43ff0c18 | 3697 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3698 | #define BP_AIPS_PACRD_WP3 (17U) //!< Bit position for AIPS_PACRD_WP3. |
mbed_official | 146:f64d43ff0c18 | 3699 | #define BM_AIPS_PACRD_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRD_WP3. |
mbed_official | 146:f64d43ff0c18 | 3700 | #define BS_AIPS_PACRD_WP3 (1U) //!< Bit field size in bits for AIPS_PACRD_WP3. |
mbed_official | 146:f64d43ff0c18 | 3701 | |
mbed_official | 146:f64d43ff0c18 | 3702 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3703 | //! @brief Read current value of the AIPS_PACRD_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 3704 | #define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3)) |
mbed_official | 146:f64d43ff0c18 | 3705 | #endif |
mbed_official | 146:f64d43ff0c18 | 3706 | |
mbed_official | 146:f64d43ff0c18 | 3707 | //! @brief Format value for bitfield AIPS_PACRD_WP3. |
mbed_official | 146:f64d43ff0c18 | 3708 | #define BF_AIPS_PACRD_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP3), uint32_t) & BM_AIPS_PACRD_WP3) |
mbed_official | 146:f64d43ff0c18 | 3709 | |
mbed_official | 146:f64d43ff0c18 | 3710 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3711 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3712 | #define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3713 | #endif |
mbed_official | 146:f64d43ff0c18 | 3714 | //@} |
mbed_official | 146:f64d43ff0c18 | 3715 | |
mbed_official | 146:f64d43ff0c18 | 3716 | /*! |
mbed_official | 146:f64d43ff0c18 | 3717 | * @name Register AIPS_PACRD, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 3718 | * |
mbed_official | 146:f64d43ff0c18 | 3719 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3720 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3721 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 3722 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 3723 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 3724 | * |
mbed_official | 146:f64d43ff0c18 | 3725 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3726 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3727 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3728 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3729 | */ |
mbed_official | 146:f64d43ff0c18 | 3730 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3731 | #define BP_AIPS_PACRD_SP3 (18U) //!< Bit position for AIPS_PACRD_SP3. |
mbed_official | 146:f64d43ff0c18 | 3732 | #define BM_AIPS_PACRD_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRD_SP3. |
mbed_official | 146:f64d43ff0c18 | 3733 | #define BS_AIPS_PACRD_SP3 (1U) //!< Bit field size in bits for AIPS_PACRD_SP3. |
mbed_official | 146:f64d43ff0c18 | 3734 | |
mbed_official | 146:f64d43ff0c18 | 3735 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3736 | //! @brief Read current value of the AIPS_PACRD_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 3737 | #define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3)) |
mbed_official | 146:f64d43ff0c18 | 3738 | #endif |
mbed_official | 146:f64d43ff0c18 | 3739 | |
mbed_official | 146:f64d43ff0c18 | 3740 | //! @brief Format value for bitfield AIPS_PACRD_SP3. |
mbed_official | 146:f64d43ff0c18 | 3741 | #define BF_AIPS_PACRD_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP3), uint32_t) & BM_AIPS_PACRD_SP3) |
mbed_official | 146:f64d43ff0c18 | 3742 | |
mbed_official | 146:f64d43ff0c18 | 3743 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3744 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3745 | #define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3746 | #endif |
mbed_official | 146:f64d43ff0c18 | 3747 | //@} |
mbed_official | 146:f64d43ff0c18 | 3748 | |
mbed_official | 146:f64d43ff0c18 | 3749 | /*! |
mbed_official | 146:f64d43ff0c18 | 3750 | * @name Register AIPS_PACRD, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 3751 | * |
mbed_official | 146:f64d43ff0c18 | 3752 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3753 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3754 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3755 | * |
mbed_official | 146:f64d43ff0c18 | 3756 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3757 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3758 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3759 | */ |
mbed_official | 146:f64d43ff0c18 | 3760 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3761 | #define BP_AIPS_PACRD_TP2 (20U) //!< Bit position for AIPS_PACRD_TP2. |
mbed_official | 146:f64d43ff0c18 | 3762 | #define BM_AIPS_PACRD_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRD_TP2. |
mbed_official | 146:f64d43ff0c18 | 3763 | #define BS_AIPS_PACRD_TP2 (1U) //!< Bit field size in bits for AIPS_PACRD_TP2. |
mbed_official | 146:f64d43ff0c18 | 3764 | |
mbed_official | 146:f64d43ff0c18 | 3765 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3766 | //! @brief Read current value of the AIPS_PACRD_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 3767 | #define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2)) |
mbed_official | 146:f64d43ff0c18 | 3768 | #endif |
mbed_official | 146:f64d43ff0c18 | 3769 | |
mbed_official | 146:f64d43ff0c18 | 3770 | //! @brief Format value for bitfield AIPS_PACRD_TP2. |
mbed_official | 146:f64d43ff0c18 | 3771 | #define BF_AIPS_PACRD_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP2), uint32_t) & BM_AIPS_PACRD_TP2) |
mbed_official | 146:f64d43ff0c18 | 3772 | |
mbed_official | 146:f64d43ff0c18 | 3773 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3774 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3775 | #define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3776 | #endif |
mbed_official | 146:f64d43ff0c18 | 3777 | //@} |
mbed_official | 146:f64d43ff0c18 | 3778 | |
mbed_official | 146:f64d43ff0c18 | 3779 | /*! |
mbed_official | 146:f64d43ff0c18 | 3780 | * @name Register AIPS_PACRD, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 3781 | * |
mbed_official | 146:f64d43ff0c18 | 3782 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 3783 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 3784 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3785 | * |
mbed_official | 146:f64d43ff0c18 | 3786 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3787 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3788 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3789 | */ |
mbed_official | 146:f64d43ff0c18 | 3790 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3791 | #define BP_AIPS_PACRD_WP2 (21U) //!< Bit position for AIPS_PACRD_WP2. |
mbed_official | 146:f64d43ff0c18 | 3792 | #define BM_AIPS_PACRD_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRD_WP2. |
mbed_official | 146:f64d43ff0c18 | 3793 | #define BS_AIPS_PACRD_WP2 (1U) //!< Bit field size in bits for AIPS_PACRD_WP2. |
mbed_official | 146:f64d43ff0c18 | 3794 | |
mbed_official | 146:f64d43ff0c18 | 3795 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3796 | //! @brief Read current value of the AIPS_PACRD_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 3797 | #define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2)) |
mbed_official | 146:f64d43ff0c18 | 3798 | #endif |
mbed_official | 146:f64d43ff0c18 | 3799 | |
mbed_official | 146:f64d43ff0c18 | 3800 | //! @brief Format value for bitfield AIPS_PACRD_WP2. |
mbed_official | 146:f64d43ff0c18 | 3801 | #define BF_AIPS_PACRD_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP2), uint32_t) & BM_AIPS_PACRD_WP2) |
mbed_official | 146:f64d43ff0c18 | 3802 | |
mbed_official | 146:f64d43ff0c18 | 3803 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3804 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3805 | #define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3806 | #endif |
mbed_official | 146:f64d43ff0c18 | 3807 | //@} |
mbed_official | 146:f64d43ff0c18 | 3808 | |
mbed_official | 146:f64d43ff0c18 | 3809 | /*! |
mbed_official | 146:f64d43ff0c18 | 3810 | * @name Register AIPS_PACRD, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 3811 | * |
mbed_official | 146:f64d43ff0c18 | 3812 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3813 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3814 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3815 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3816 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3817 | * |
mbed_official | 146:f64d43ff0c18 | 3818 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3819 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3820 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3821 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3822 | */ |
mbed_official | 146:f64d43ff0c18 | 3823 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3824 | #define BP_AIPS_PACRD_SP2 (22U) //!< Bit position for AIPS_PACRD_SP2. |
mbed_official | 146:f64d43ff0c18 | 3825 | #define BM_AIPS_PACRD_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRD_SP2. |
mbed_official | 146:f64d43ff0c18 | 3826 | #define BS_AIPS_PACRD_SP2 (1U) //!< Bit field size in bits for AIPS_PACRD_SP2. |
mbed_official | 146:f64d43ff0c18 | 3827 | |
mbed_official | 146:f64d43ff0c18 | 3828 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3829 | //! @brief Read current value of the AIPS_PACRD_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 3830 | #define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2)) |
mbed_official | 146:f64d43ff0c18 | 3831 | #endif |
mbed_official | 146:f64d43ff0c18 | 3832 | |
mbed_official | 146:f64d43ff0c18 | 3833 | //! @brief Format value for bitfield AIPS_PACRD_SP2. |
mbed_official | 146:f64d43ff0c18 | 3834 | #define BF_AIPS_PACRD_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP2), uint32_t) & BM_AIPS_PACRD_SP2) |
mbed_official | 146:f64d43ff0c18 | 3835 | |
mbed_official | 146:f64d43ff0c18 | 3836 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3837 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3838 | #define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3839 | #endif |
mbed_official | 146:f64d43ff0c18 | 3840 | //@} |
mbed_official | 146:f64d43ff0c18 | 3841 | |
mbed_official | 146:f64d43ff0c18 | 3842 | /*! |
mbed_official | 146:f64d43ff0c18 | 3843 | * @name Register AIPS_PACRD, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 3844 | * |
mbed_official | 146:f64d43ff0c18 | 3845 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3846 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3847 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3848 | * |
mbed_official | 146:f64d43ff0c18 | 3849 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3850 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3851 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3852 | */ |
mbed_official | 146:f64d43ff0c18 | 3853 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3854 | #define BP_AIPS_PACRD_TP1 (24U) //!< Bit position for AIPS_PACRD_TP1. |
mbed_official | 146:f64d43ff0c18 | 3855 | #define BM_AIPS_PACRD_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRD_TP1. |
mbed_official | 146:f64d43ff0c18 | 3856 | #define BS_AIPS_PACRD_TP1 (1U) //!< Bit field size in bits for AIPS_PACRD_TP1. |
mbed_official | 146:f64d43ff0c18 | 3857 | |
mbed_official | 146:f64d43ff0c18 | 3858 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3859 | //! @brief Read current value of the AIPS_PACRD_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 3860 | #define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1)) |
mbed_official | 146:f64d43ff0c18 | 3861 | #endif |
mbed_official | 146:f64d43ff0c18 | 3862 | |
mbed_official | 146:f64d43ff0c18 | 3863 | //! @brief Format value for bitfield AIPS_PACRD_TP1. |
mbed_official | 146:f64d43ff0c18 | 3864 | #define BF_AIPS_PACRD_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP1), uint32_t) & BM_AIPS_PACRD_TP1) |
mbed_official | 146:f64d43ff0c18 | 3865 | |
mbed_official | 146:f64d43ff0c18 | 3866 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3867 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3868 | #define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3869 | #endif |
mbed_official | 146:f64d43ff0c18 | 3870 | //@} |
mbed_official | 146:f64d43ff0c18 | 3871 | |
mbed_official | 146:f64d43ff0c18 | 3872 | /*! |
mbed_official | 146:f64d43ff0c18 | 3873 | * @name Register AIPS_PACRD, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 3874 | * |
mbed_official | 146:f64d43ff0c18 | 3875 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 3876 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 3877 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3878 | * |
mbed_official | 146:f64d43ff0c18 | 3879 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3880 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3881 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3882 | */ |
mbed_official | 146:f64d43ff0c18 | 3883 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3884 | #define BP_AIPS_PACRD_WP1 (25U) //!< Bit position for AIPS_PACRD_WP1. |
mbed_official | 146:f64d43ff0c18 | 3885 | #define BM_AIPS_PACRD_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRD_WP1. |
mbed_official | 146:f64d43ff0c18 | 3886 | #define BS_AIPS_PACRD_WP1 (1U) //!< Bit field size in bits for AIPS_PACRD_WP1. |
mbed_official | 146:f64d43ff0c18 | 3887 | |
mbed_official | 146:f64d43ff0c18 | 3888 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3889 | //! @brief Read current value of the AIPS_PACRD_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 3890 | #define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1)) |
mbed_official | 146:f64d43ff0c18 | 3891 | #endif |
mbed_official | 146:f64d43ff0c18 | 3892 | |
mbed_official | 146:f64d43ff0c18 | 3893 | //! @brief Format value for bitfield AIPS_PACRD_WP1. |
mbed_official | 146:f64d43ff0c18 | 3894 | #define BF_AIPS_PACRD_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP1), uint32_t) & BM_AIPS_PACRD_WP1) |
mbed_official | 146:f64d43ff0c18 | 3895 | |
mbed_official | 146:f64d43ff0c18 | 3896 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3897 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3898 | #define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3899 | #endif |
mbed_official | 146:f64d43ff0c18 | 3900 | //@} |
mbed_official | 146:f64d43ff0c18 | 3901 | |
mbed_official | 146:f64d43ff0c18 | 3902 | /*! |
mbed_official | 146:f64d43ff0c18 | 3903 | * @name Register AIPS_PACRD, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 3904 | * |
mbed_official | 146:f64d43ff0c18 | 3905 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3906 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 3907 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 3908 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 3909 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 3910 | * |
mbed_official | 146:f64d43ff0c18 | 3911 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3912 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3913 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 3914 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 3915 | */ |
mbed_official | 146:f64d43ff0c18 | 3916 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3917 | #define BP_AIPS_PACRD_SP1 (26U) //!< Bit position for AIPS_PACRD_SP1. |
mbed_official | 146:f64d43ff0c18 | 3918 | #define BM_AIPS_PACRD_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRD_SP1. |
mbed_official | 146:f64d43ff0c18 | 3919 | #define BS_AIPS_PACRD_SP1 (1U) //!< Bit field size in bits for AIPS_PACRD_SP1. |
mbed_official | 146:f64d43ff0c18 | 3920 | |
mbed_official | 146:f64d43ff0c18 | 3921 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3922 | //! @brief Read current value of the AIPS_PACRD_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 3923 | #define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1)) |
mbed_official | 146:f64d43ff0c18 | 3924 | #endif |
mbed_official | 146:f64d43ff0c18 | 3925 | |
mbed_official | 146:f64d43ff0c18 | 3926 | //! @brief Format value for bitfield AIPS_PACRD_SP1. |
mbed_official | 146:f64d43ff0c18 | 3927 | #define BF_AIPS_PACRD_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP1), uint32_t) & BM_AIPS_PACRD_SP1) |
mbed_official | 146:f64d43ff0c18 | 3928 | |
mbed_official | 146:f64d43ff0c18 | 3929 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3930 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3931 | #define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3932 | #endif |
mbed_official | 146:f64d43ff0c18 | 3933 | //@} |
mbed_official | 146:f64d43ff0c18 | 3934 | |
mbed_official | 146:f64d43ff0c18 | 3935 | /*! |
mbed_official | 146:f64d43ff0c18 | 3936 | * @name Register AIPS_PACRD, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 3937 | * |
mbed_official | 146:f64d43ff0c18 | 3938 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 3939 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 3940 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3941 | * |
mbed_official | 146:f64d43ff0c18 | 3942 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3943 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 3944 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 3945 | */ |
mbed_official | 146:f64d43ff0c18 | 3946 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3947 | #define BP_AIPS_PACRD_TP0 (28U) //!< Bit position for AIPS_PACRD_TP0. |
mbed_official | 146:f64d43ff0c18 | 3948 | #define BM_AIPS_PACRD_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRD_TP0. |
mbed_official | 146:f64d43ff0c18 | 3949 | #define BS_AIPS_PACRD_TP0 (1U) //!< Bit field size in bits for AIPS_PACRD_TP0. |
mbed_official | 146:f64d43ff0c18 | 3950 | |
mbed_official | 146:f64d43ff0c18 | 3951 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3952 | //! @brief Read current value of the AIPS_PACRD_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 3953 | #define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0)) |
mbed_official | 146:f64d43ff0c18 | 3954 | #endif |
mbed_official | 146:f64d43ff0c18 | 3955 | |
mbed_official | 146:f64d43ff0c18 | 3956 | //! @brief Format value for bitfield AIPS_PACRD_TP0. |
mbed_official | 146:f64d43ff0c18 | 3957 | #define BF_AIPS_PACRD_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP0), uint32_t) & BM_AIPS_PACRD_TP0) |
mbed_official | 146:f64d43ff0c18 | 3958 | |
mbed_official | 146:f64d43ff0c18 | 3959 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3960 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3961 | #define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3962 | #endif |
mbed_official | 146:f64d43ff0c18 | 3963 | //@} |
mbed_official | 146:f64d43ff0c18 | 3964 | |
mbed_official | 146:f64d43ff0c18 | 3965 | /*! |
mbed_official | 146:f64d43ff0c18 | 3966 | * @name Register AIPS_PACRD, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 3967 | * |
mbed_official | 146:f64d43ff0c18 | 3968 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 3969 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 3970 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 3971 | * |
mbed_official | 146:f64d43ff0c18 | 3972 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3973 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 3974 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 3975 | */ |
mbed_official | 146:f64d43ff0c18 | 3976 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3977 | #define BP_AIPS_PACRD_WP0 (29U) //!< Bit position for AIPS_PACRD_WP0. |
mbed_official | 146:f64d43ff0c18 | 3978 | #define BM_AIPS_PACRD_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRD_WP0. |
mbed_official | 146:f64d43ff0c18 | 3979 | #define BS_AIPS_PACRD_WP0 (1U) //!< Bit field size in bits for AIPS_PACRD_WP0. |
mbed_official | 146:f64d43ff0c18 | 3980 | |
mbed_official | 146:f64d43ff0c18 | 3981 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3982 | //! @brief Read current value of the AIPS_PACRD_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 3983 | #define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0)) |
mbed_official | 146:f64d43ff0c18 | 3984 | #endif |
mbed_official | 146:f64d43ff0c18 | 3985 | |
mbed_official | 146:f64d43ff0c18 | 3986 | //! @brief Format value for bitfield AIPS_PACRD_WP0. |
mbed_official | 146:f64d43ff0c18 | 3987 | #define BF_AIPS_PACRD_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP0), uint32_t) & BM_AIPS_PACRD_WP0) |
mbed_official | 146:f64d43ff0c18 | 3988 | |
mbed_official | 146:f64d43ff0c18 | 3989 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3990 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3991 | #define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3992 | #endif |
mbed_official | 146:f64d43ff0c18 | 3993 | //@} |
mbed_official | 146:f64d43ff0c18 | 3994 | |
mbed_official | 146:f64d43ff0c18 | 3995 | /*! |
mbed_official | 146:f64d43ff0c18 | 3996 | * @name Register AIPS_PACRD, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 3997 | * |
mbed_official | 146:f64d43ff0c18 | 3998 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 3999 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4000 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4001 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4002 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4003 | * |
mbed_official | 146:f64d43ff0c18 | 4004 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4005 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4006 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4007 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4008 | */ |
mbed_official | 146:f64d43ff0c18 | 4009 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4010 | #define BP_AIPS_PACRD_SP0 (30U) //!< Bit position for AIPS_PACRD_SP0. |
mbed_official | 146:f64d43ff0c18 | 4011 | #define BM_AIPS_PACRD_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRD_SP0. |
mbed_official | 146:f64d43ff0c18 | 4012 | #define BS_AIPS_PACRD_SP0 (1U) //!< Bit field size in bits for AIPS_PACRD_SP0. |
mbed_official | 146:f64d43ff0c18 | 4013 | |
mbed_official | 146:f64d43ff0c18 | 4014 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4015 | //! @brief Read current value of the AIPS_PACRD_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 4016 | #define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0)) |
mbed_official | 146:f64d43ff0c18 | 4017 | #endif |
mbed_official | 146:f64d43ff0c18 | 4018 | |
mbed_official | 146:f64d43ff0c18 | 4019 | //! @brief Format value for bitfield AIPS_PACRD_SP0. |
mbed_official | 146:f64d43ff0c18 | 4020 | #define BF_AIPS_PACRD_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP0), uint32_t) & BM_AIPS_PACRD_SP0) |
mbed_official | 146:f64d43ff0c18 | 4021 | |
mbed_official | 146:f64d43ff0c18 | 4022 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4023 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4024 | #define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4025 | #endif |
mbed_official | 146:f64d43ff0c18 | 4026 | //@} |
mbed_official | 146:f64d43ff0c18 | 4027 | |
mbed_official | 146:f64d43ff0c18 | 4028 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4029 | // HW_AIPS_PACRE - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 4030 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4031 | |
mbed_official | 146:f64d43ff0c18 | 4032 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4033 | /*! |
mbed_official | 146:f64d43ff0c18 | 4034 | * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4035 | * |
mbed_official | 146:f64d43ff0c18 | 4036 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 4037 | * |
mbed_official | 146:f64d43ff0c18 | 4038 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 4039 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 4040 | * registers. |
mbed_official | 146:f64d43ff0c18 | 4041 | */ |
mbed_official | 146:f64d43ff0c18 | 4042 | typedef union _hw_aips_pacre |
mbed_official | 146:f64d43ff0c18 | 4043 | { |
mbed_official | 146:f64d43ff0c18 | 4044 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 4045 | struct _hw_aips_pacre_bitfields |
mbed_official | 146:f64d43ff0c18 | 4046 | { |
mbed_official | 146:f64d43ff0c18 | 4047 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4048 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4049 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4050 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 4051 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4052 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4053 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4054 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 4055 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4056 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4057 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4058 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 4059 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4060 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4061 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4062 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 4063 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4064 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4065 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4066 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 4067 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4068 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4069 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4070 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 4071 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4072 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4073 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4074 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 4075 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4076 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4077 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4078 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 4079 | } B; |
mbed_official | 146:f64d43ff0c18 | 4080 | } hw_aips_pacre_t; |
mbed_official | 146:f64d43ff0c18 | 4081 | #endif |
mbed_official | 146:f64d43ff0c18 | 4082 | |
mbed_official | 146:f64d43ff0c18 | 4083 | /*! |
mbed_official | 146:f64d43ff0c18 | 4084 | * @name Constants and macros for entire AIPS_PACRE register |
mbed_official | 146:f64d43ff0c18 | 4085 | */ |
mbed_official | 146:f64d43ff0c18 | 4086 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4087 | #define HW_AIPS_PACRE_ADDR(x) (REGS_AIPS_BASE(x) + 0x40U) |
mbed_official | 146:f64d43ff0c18 | 4088 | |
mbed_official | 146:f64d43ff0c18 | 4089 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4090 | #define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4091 | #define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U) |
mbed_official | 146:f64d43ff0c18 | 4092 | #define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4093 | #define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4094 | #define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4095 | #define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4096 | #endif |
mbed_official | 146:f64d43ff0c18 | 4097 | //@} |
mbed_official | 146:f64d43ff0c18 | 4098 | |
mbed_official | 146:f64d43ff0c18 | 4099 | /* |
mbed_official | 146:f64d43ff0c18 | 4100 | * Constants & macros for individual AIPS_PACRE bitfields |
mbed_official | 146:f64d43ff0c18 | 4101 | */ |
mbed_official | 146:f64d43ff0c18 | 4102 | |
mbed_official | 146:f64d43ff0c18 | 4103 | /*! |
mbed_official | 146:f64d43ff0c18 | 4104 | * @name Register AIPS_PACRE, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4105 | * |
mbed_official | 146:f64d43ff0c18 | 4106 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4107 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4108 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4109 | * |
mbed_official | 146:f64d43ff0c18 | 4110 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4111 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4112 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4113 | */ |
mbed_official | 146:f64d43ff0c18 | 4114 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4115 | #define BP_AIPS_PACRE_TP7 (0U) //!< Bit position for AIPS_PACRE_TP7. |
mbed_official | 146:f64d43ff0c18 | 4116 | #define BM_AIPS_PACRE_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRE_TP7. |
mbed_official | 146:f64d43ff0c18 | 4117 | #define BS_AIPS_PACRE_TP7 (1U) //!< Bit field size in bits for AIPS_PACRE_TP7. |
mbed_official | 146:f64d43ff0c18 | 4118 | |
mbed_official | 146:f64d43ff0c18 | 4119 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4120 | //! @brief Read current value of the AIPS_PACRE_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 4121 | #define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7)) |
mbed_official | 146:f64d43ff0c18 | 4122 | #endif |
mbed_official | 146:f64d43ff0c18 | 4123 | |
mbed_official | 146:f64d43ff0c18 | 4124 | //! @brief Format value for bitfield AIPS_PACRE_TP7. |
mbed_official | 146:f64d43ff0c18 | 4125 | #define BF_AIPS_PACRE_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP7), uint32_t) & BM_AIPS_PACRE_TP7) |
mbed_official | 146:f64d43ff0c18 | 4126 | |
mbed_official | 146:f64d43ff0c18 | 4127 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4128 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4129 | #define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4130 | #endif |
mbed_official | 146:f64d43ff0c18 | 4131 | //@} |
mbed_official | 146:f64d43ff0c18 | 4132 | |
mbed_official | 146:f64d43ff0c18 | 4133 | /*! |
mbed_official | 146:f64d43ff0c18 | 4134 | * @name Register AIPS_PACRE, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 4135 | * |
mbed_official | 146:f64d43ff0c18 | 4136 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4137 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4138 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4139 | * |
mbed_official | 146:f64d43ff0c18 | 4140 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4141 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4142 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4143 | */ |
mbed_official | 146:f64d43ff0c18 | 4144 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4145 | #define BP_AIPS_PACRE_WP7 (1U) //!< Bit position for AIPS_PACRE_WP7. |
mbed_official | 146:f64d43ff0c18 | 4146 | #define BM_AIPS_PACRE_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRE_WP7. |
mbed_official | 146:f64d43ff0c18 | 4147 | #define BS_AIPS_PACRE_WP7 (1U) //!< Bit field size in bits for AIPS_PACRE_WP7. |
mbed_official | 146:f64d43ff0c18 | 4148 | |
mbed_official | 146:f64d43ff0c18 | 4149 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4150 | //! @brief Read current value of the AIPS_PACRE_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 4151 | #define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7)) |
mbed_official | 146:f64d43ff0c18 | 4152 | #endif |
mbed_official | 146:f64d43ff0c18 | 4153 | |
mbed_official | 146:f64d43ff0c18 | 4154 | //! @brief Format value for bitfield AIPS_PACRE_WP7. |
mbed_official | 146:f64d43ff0c18 | 4155 | #define BF_AIPS_PACRE_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP7), uint32_t) & BM_AIPS_PACRE_WP7) |
mbed_official | 146:f64d43ff0c18 | 4156 | |
mbed_official | 146:f64d43ff0c18 | 4157 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4158 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4159 | #define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4160 | #endif |
mbed_official | 146:f64d43ff0c18 | 4161 | //@} |
mbed_official | 146:f64d43ff0c18 | 4162 | |
mbed_official | 146:f64d43ff0c18 | 4163 | /*! |
mbed_official | 146:f64d43ff0c18 | 4164 | * @name Register AIPS_PACRE, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 4165 | * |
mbed_official | 146:f64d43ff0c18 | 4166 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4167 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4168 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4169 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4170 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4171 | * |
mbed_official | 146:f64d43ff0c18 | 4172 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4173 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4174 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4175 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4176 | */ |
mbed_official | 146:f64d43ff0c18 | 4177 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4178 | #define BP_AIPS_PACRE_SP7 (2U) //!< Bit position for AIPS_PACRE_SP7. |
mbed_official | 146:f64d43ff0c18 | 4179 | #define BM_AIPS_PACRE_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRE_SP7. |
mbed_official | 146:f64d43ff0c18 | 4180 | #define BS_AIPS_PACRE_SP7 (1U) //!< Bit field size in bits for AIPS_PACRE_SP7. |
mbed_official | 146:f64d43ff0c18 | 4181 | |
mbed_official | 146:f64d43ff0c18 | 4182 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4183 | //! @brief Read current value of the AIPS_PACRE_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 4184 | #define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7)) |
mbed_official | 146:f64d43ff0c18 | 4185 | #endif |
mbed_official | 146:f64d43ff0c18 | 4186 | |
mbed_official | 146:f64d43ff0c18 | 4187 | //! @brief Format value for bitfield AIPS_PACRE_SP7. |
mbed_official | 146:f64d43ff0c18 | 4188 | #define BF_AIPS_PACRE_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP7), uint32_t) & BM_AIPS_PACRE_SP7) |
mbed_official | 146:f64d43ff0c18 | 4189 | |
mbed_official | 146:f64d43ff0c18 | 4190 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4191 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4192 | #define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4193 | #endif |
mbed_official | 146:f64d43ff0c18 | 4194 | //@} |
mbed_official | 146:f64d43ff0c18 | 4195 | |
mbed_official | 146:f64d43ff0c18 | 4196 | /*! |
mbed_official | 146:f64d43ff0c18 | 4197 | * @name Register AIPS_PACRE, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 4198 | * |
mbed_official | 146:f64d43ff0c18 | 4199 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4200 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4201 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4202 | * |
mbed_official | 146:f64d43ff0c18 | 4203 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4204 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4205 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4206 | */ |
mbed_official | 146:f64d43ff0c18 | 4207 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4208 | #define BP_AIPS_PACRE_TP6 (4U) //!< Bit position for AIPS_PACRE_TP6. |
mbed_official | 146:f64d43ff0c18 | 4209 | #define BM_AIPS_PACRE_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRE_TP6. |
mbed_official | 146:f64d43ff0c18 | 4210 | #define BS_AIPS_PACRE_TP6 (1U) //!< Bit field size in bits for AIPS_PACRE_TP6. |
mbed_official | 146:f64d43ff0c18 | 4211 | |
mbed_official | 146:f64d43ff0c18 | 4212 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4213 | //! @brief Read current value of the AIPS_PACRE_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 4214 | #define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6)) |
mbed_official | 146:f64d43ff0c18 | 4215 | #endif |
mbed_official | 146:f64d43ff0c18 | 4216 | |
mbed_official | 146:f64d43ff0c18 | 4217 | //! @brief Format value for bitfield AIPS_PACRE_TP6. |
mbed_official | 146:f64d43ff0c18 | 4218 | #define BF_AIPS_PACRE_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP6), uint32_t) & BM_AIPS_PACRE_TP6) |
mbed_official | 146:f64d43ff0c18 | 4219 | |
mbed_official | 146:f64d43ff0c18 | 4220 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4221 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4222 | #define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4223 | #endif |
mbed_official | 146:f64d43ff0c18 | 4224 | //@} |
mbed_official | 146:f64d43ff0c18 | 4225 | |
mbed_official | 146:f64d43ff0c18 | 4226 | /*! |
mbed_official | 146:f64d43ff0c18 | 4227 | * @name Register AIPS_PACRE, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 4228 | * |
mbed_official | 146:f64d43ff0c18 | 4229 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4230 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4231 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4232 | * |
mbed_official | 146:f64d43ff0c18 | 4233 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4234 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4235 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4236 | */ |
mbed_official | 146:f64d43ff0c18 | 4237 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4238 | #define BP_AIPS_PACRE_WP6 (5U) //!< Bit position for AIPS_PACRE_WP6. |
mbed_official | 146:f64d43ff0c18 | 4239 | #define BM_AIPS_PACRE_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRE_WP6. |
mbed_official | 146:f64d43ff0c18 | 4240 | #define BS_AIPS_PACRE_WP6 (1U) //!< Bit field size in bits for AIPS_PACRE_WP6. |
mbed_official | 146:f64d43ff0c18 | 4241 | |
mbed_official | 146:f64d43ff0c18 | 4242 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4243 | //! @brief Read current value of the AIPS_PACRE_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 4244 | #define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6)) |
mbed_official | 146:f64d43ff0c18 | 4245 | #endif |
mbed_official | 146:f64d43ff0c18 | 4246 | |
mbed_official | 146:f64d43ff0c18 | 4247 | //! @brief Format value for bitfield AIPS_PACRE_WP6. |
mbed_official | 146:f64d43ff0c18 | 4248 | #define BF_AIPS_PACRE_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP6), uint32_t) & BM_AIPS_PACRE_WP6) |
mbed_official | 146:f64d43ff0c18 | 4249 | |
mbed_official | 146:f64d43ff0c18 | 4250 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4251 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4252 | #define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4253 | #endif |
mbed_official | 146:f64d43ff0c18 | 4254 | //@} |
mbed_official | 146:f64d43ff0c18 | 4255 | |
mbed_official | 146:f64d43ff0c18 | 4256 | /*! |
mbed_official | 146:f64d43ff0c18 | 4257 | * @name Register AIPS_PACRE, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 4258 | * |
mbed_official | 146:f64d43ff0c18 | 4259 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4260 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4261 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4262 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4263 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4264 | * |
mbed_official | 146:f64d43ff0c18 | 4265 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4266 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4267 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4268 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4269 | */ |
mbed_official | 146:f64d43ff0c18 | 4270 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4271 | #define BP_AIPS_PACRE_SP6 (6U) //!< Bit position for AIPS_PACRE_SP6. |
mbed_official | 146:f64d43ff0c18 | 4272 | #define BM_AIPS_PACRE_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRE_SP6. |
mbed_official | 146:f64d43ff0c18 | 4273 | #define BS_AIPS_PACRE_SP6 (1U) //!< Bit field size in bits for AIPS_PACRE_SP6. |
mbed_official | 146:f64d43ff0c18 | 4274 | |
mbed_official | 146:f64d43ff0c18 | 4275 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4276 | //! @brief Read current value of the AIPS_PACRE_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 4277 | #define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6)) |
mbed_official | 146:f64d43ff0c18 | 4278 | #endif |
mbed_official | 146:f64d43ff0c18 | 4279 | |
mbed_official | 146:f64d43ff0c18 | 4280 | //! @brief Format value for bitfield AIPS_PACRE_SP6. |
mbed_official | 146:f64d43ff0c18 | 4281 | #define BF_AIPS_PACRE_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP6), uint32_t) & BM_AIPS_PACRE_SP6) |
mbed_official | 146:f64d43ff0c18 | 4282 | |
mbed_official | 146:f64d43ff0c18 | 4283 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4284 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4285 | #define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4286 | #endif |
mbed_official | 146:f64d43ff0c18 | 4287 | //@} |
mbed_official | 146:f64d43ff0c18 | 4288 | |
mbed_official | 146:f64d43ff0c18 | 4289 | /*! |
mbed_official | 146:f64d43ff0c18 | 4290 | * @name Register AIPS_PACRE, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 4291 | * |
mbed_official | 146:f64d43ff0c18 | 4292 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4293 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4294 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4295 | * |
mbed_official | 146:f64d43ff0c18 | 4296 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4297 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4298 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4299 | */ |
mbed_official | 146:f64d43ff0c18 | 4300 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4301 | #define BP_AIPS_PACRE_TP5 (8U) //!< Bit position for AIPS_PACRE_TP5. |
mbed_official | 146:f64d43ff0c18 | 4302 | #define BM_AIPS_PACRE_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRE_TP5. |
mbed_official | 146:f64d43ff0c18 | 4303 | #define BS_AIPS_PACRE_TP5 (1U) //!< Bit field size in bits for AIPS_PACRE_TP5. |
mbed_official | 146:f64d43ff0c18 | 4304 | |
mbed_official | 146:f64d43ff0c18 | 4305 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4306 | //! @brief Read current value of the AIPS_PACRE_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 4307 | #define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5)) |
mbed_official | 146:f64d43ff0c18 | 4308 | #endif |
mbed_official | 146:f64d43ff0c18 | 4309 | |
mbed_official | 146:f64d43ff0c18 | 4310 | //! @brief Format value for bitfield AIPS_PACRE_TP5. |
mbed_official | 146:f64d43ff0c18 | 4311 | #define BF_AIPS_PACRE_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP5), uint32_t) & BM_AIPS_PACRE_TP5) |
mbed_official | 146:f64d43ff0c18 | 4312 | |
mbed_official | 146:f64d43ff0c18 | 4313 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4314 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4315 | #define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4316 | #endif |
mbed_official | 146:f64d43ff0c18 | 4317 | //@} |
mbed_official | 146:f64d43ff0c18 | 4318 | |
mbed_official | 146:f64d43ff0c18 | 4319 | /*! |
mbed_official | 146:f64d43ff0c18 | 4320 | * @name Register AIPS_PACRE, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 4321 | * |
mbed_official | 146:f64d43ff0c18 | 4322 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4323 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4324 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4325 | * |
mbed_official | 146:f64d43ff0c18 | 4326 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4327 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4328 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4329 | */ |
mbed_official | 146:f64d43ff0c18 | 4330 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4331 | #define BP_AIPS_PACRE_WP5 (9U) //!< Bit position for AIPS_PACRE_WP5. |
mbed_official | 146:f64d43ff0c18 | 4332 | #define BM_AIPS_PACRE_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRE_WP5. |
mbed_official | 146:f64d43ff0c18 | 4333 | #define BS_AIPS_PACRE_WP5 (1U) //!< Bit field size in bits for AIPS_PACRE_WP5. |
mbed_official | 146:f64d43ff0c18 | 4334 | |
mbed_official | 146:f64d43ff0c18 | 4335 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4336 | //! @brief Read current value of the AIPS_PACRE_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 4337 | #define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5)) |
mbed_official | 146:f64d43ff0c18 | 4338 | #endif |
mbed_official | 146:f64d43ff0c18 | 4339 | |
mbed_official | 146:f64d43ff0c18 | 4340 | //! @brief Format value for bitfield AIPS_PACRE_WP5. |
mbed_official | 146:f64d43ff0c18 | 4341 | #define BF_AIPS_PACRE_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP5), uint32_t) & BM_AIPS_PACRE_WP5) |
mbed_official | 146:f64d43ff0c18 | 4342 | |
mbed_official | 146:f64d43ff0c18 | 4343 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4344 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4345 | #define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4346 | #endif |
mbed_official | 146:f64d43ff0c18 | 4347 | //@} |
mbed_official | 146:f64d43ff0c18 | 4348 | |
mbed_official | 146:f64d43ff0c18 | 4349 | /*! |
mbed_official | 146:f64d43ff0c18 | 4350 | * @name Register AIPS_PACRE, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 4351 | * |
mbed_official | 146:f64d43ff0c18 | 4352 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4353 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4354 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4355 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4356 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4357 | * |
mbed_official | 146:f64d43ff0c18 | 4358 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4359 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4360 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4361 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4362 | */ |
mbed_official | 146:f64d43ff0c18 | 4363 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4364 | #define BP_AIPS_PACRE_SP5 (10U) //!< Bit position for AIPS_PACRE_SP5. |
mbed_official | 146:f64d43ff0c18 | 4365 | #define BM_AIPS_PACRE_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRE_SP5. |
mbed_official | 146:f64d43ff0c18 | 4366 | #define BS_AIPS_PACRE_SP5 (1U) //!< Bit field size in bits for AIPS_PACRE_SP5. |
mbed_official | 146:f64d43ff0c18 | 4367 | |
mbed_official | 146:f64d43ff0c18 | 4368 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4369 | //! @brief Read current value of the AIPS_PACRE_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 4370 | #define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5)) |
mbed_official | 146:f64d43ff0c18 | 4371 | #endif |
mbed_official | 146:f64d43ff0c18 | 4372 | |
mbed_official | 146:f64d43ff0c18 | 4373 | //! @brief Format value for bitfield AIPS_PACRE_SP5. |
mbed_official | 146:f64d43ff0c18 | 4374 | #define BF_AIPS_PACRE_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP5), uint32_t) & BM_AIPS_PACRE_SP5) |
mbed_official | 146:f64d43ff0c18 | 4375 | |
mbed_official | 146:f64d43ff0c18 | 4376 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4377 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4378 | #define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4379 | #endif |
mbed_official | 146:f64d43ff0c18 | 4380 | //@} |
mbed_official | 146:f64d43ff0c18 | 4381 | |
mbed_official | 146:f64d43ff0c18 | 4382 | /*! |
mbed_official | 146:f64d43ff0c18 | 4383 | * @name Register AIPS_PACRE, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 4384 | * |
mbed_official | 146:f64d43ff0c18 | 4385 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4386 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4387 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4388 | * |
mbed_official | 146:f64d43ff0c18 | 4389 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4390 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4391 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4392 | */ |
mbed_official | 146:f64d43ff0c18 | 4393 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4394 | #define BP_AIPS_PACRE_TP4 (12U) //!< Bit position for AIPS_PACRE_TP4. |
mbed_official | 146:f64d43ff0c18 | 4395 | #define BM_AIPS_PACRE_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRE_TP4. |
mbed_official | 146:f64d43ff0c18 | 4396 | #define BS_AIPS_PACRE_TP4 (1U) //!< Bit field size in bits for AIPS_PACRE_TP4. |
mbed_official | 146:f64d43ff0c18 | 4397 | |
mbed_official | 146:f64d43ff0c18 | 4398 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4399 | //! @brief Read current value of the AIPS_PACRE_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 4400 | #define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4)) |
mbed_official | 146:f64d43ff0c18 | 4401 | #endif |
mbed_official | 146:f64d43ff0c18 | 4402 | |
mbed_official | 146:f64d43ff0c18 | 4403 | //! @brief Format value for bitfield AIPS_PACRE_TP4. |
mbed_official | 146:f64d43ff0c18 | 4404 | #define BF_AIPS_PACRE_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP4), uint32_t) & BM_AIPS_PACRE_TP4) |
mbed_official | 146:f64d43ff0c18 | 4405 | |
mbed_official | 146:f64d43ff0c18 | 4406 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4407 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4408 | #define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4409 | #endif |
mbed_official | 146:f64d43ff0c18 | 4410 | //@} |
mbed_official | 146:f64d43ff0c18 | 4411 | |
mbed_official | 146:f64d43ff0c18 | 4412 | /*! |
mbed_official | 146:f64d43ff0c18 | 4413 | * @name Register AIPS_PACRE, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 4414 | * |
mbed_official | 146:f64d43ff0c18 | 4415 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4416 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4417 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4418 | * |
mbed_official | 146:f64d43ff0c18 | 4419 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4420 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4421 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4422 | */ |
mbed_official | 146:f64d43ff0c18 | 4423 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4424 | #define BP_AIPS_PACRE_WP4 (13U) //!< Bit position for AIPS_PACRE_WP4. |
mbed_official | 146:f64d43ff0c18 | 4425 | #define BM_AIPS_PACRE_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRE_WP4. |
mbed_official | 146:f64d43ff0c18 | 4426 | #define BS_AIPS_PACRE_WP4 (1U) //!< Bit field size in bits for AIPS_PACRE_WP4. |
mbed_official | 146:f64d43ff0c18 | 4427 | |
mbed_official | 146:f64d43ff0c18 | 4428 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4429 | //! @brief Read current value of the AIPS_PACRE_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 4430 | #define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4)) |
mbed_official | 146:f64d43ff0c18 | 4431 | #endif |
mbed_official | 146:f64d43ff0c18 | 4432 | |
mbed_official | 146:f64d43ff0c18 | 4433 | //! @brief Format value for bitfield AIPS_PACRE_WP4. |
mbed_official | 146:f64d43ff0c18 | 4434 | #define BF_AIPS_PACRE_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP4), uint32_t) & BM_AIPS_PACRE_WP4) |
mbed_official | 146:f64d43ff0c18 | 4435 | |
mbed_official | 146:f64d43ff0c18 | 4436 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4437 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4438 | #define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4439 | #endif |
mbed_official | 146:f64d43ff0c18 | 4440 | //@} |
mbed_official | 146:f64d43ff0c18 | 4441 | |
mbed_official | 146:f64d43ff0c18 | 4442 | /*! |
mbed_official | 146:f64d43ff0c18 | 4443 | * @name Register AIPS_PACRE, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 4444 | * |
mbed_official | 146:f64d43ff0c18 | 4445 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4446 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4447 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 4448 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 4449 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 4450 | * |
mbed_official | 146:f64d43ff0c18 | 4451 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4452 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4453 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4454 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4455 | */ |
mbed_official | 146:f64d43ff0c18 | 4456 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4457 | #define BP_AIPS_PACRE_SP4 (14U) //!< Bit position for AIPS_PACRE_SP4. |
mbed_official | 146:f64d43ff0c18 | 4458 | #define BM_AIPS_PACRE_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRE_SP4. |
mbed_official | 146:f64d43ff0c18 | 4459 | #define BS_AIPS_PACRE_SP4 (1U) //!< Bit field size in bits for AIPS_PACRE_SP4. |
mbed_official | 146:f64d43ff0c18 | 4460 | |
mbed_official | 146:f64d43ff0c18 | 4461 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4462 | //! @brief Read current value of the AIPS_PACRE_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 4463 | #define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4)) |
mbed_official | 146:f64d43ff0c18 | 4464 | #endif |
mbed_official | 146:f64d43ff0c18 | 4465 | |
mbed_official | 146:f64d43ff0c18 | 4466 | //! @brief Format value for bitfield AIPS_PACRE_SP4. |
mbed_official | 146:f64d43ff0c18 | 4467 | #define BF_AIPS_PACRE_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP4), uint32_t) & BM_AIPS_PACRE_SP4) |
mbed_official | 146:f64d43ff0c18 | 4468 | |
mbed_official | 146:f64d43ff0c18 | 4469 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4470 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4471 | #define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4472 | #endif |
mbed_official | 146:f64d43ff0c18 | 4473 | //@} |
mbed_official | 146:f64d43ff0c18 | 4474 | |
mbed_official | 146:f64d43ff0c18 | 4475 | /*! |
mbed_official | 146:f64d43ff0c18 | 4476 | * @name Register AIPS_PACRE, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 4477 | * |
mbed_official | 146:f64d43ff0c18 | 4478 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4479 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4480 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4481 | * |
mbed_official | 146:f64d43ff0c18 | 4482 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4483 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4484 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4485 | */ |
mbed_official | 146:f64d43ff0c18 | 4486 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4487 | #define BP_AIPS_PACRE_TP3 (16U) //!< Bit position for AIPS_PACRE_TP3. |
mbed_official | 146:f64d43ff0c18 | 4488 | #define BM_AIPS_PACRE_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRE_TP3. |
mbed_official | 146:f64d43ff0c18 | 4489 | #define BS_AIPS_PACRE_TP3 (1U) //!< Bit field size in bits for AIPS_PACRE_TP3. |
mbed_official | 146:f64d43ff0c18 | 4490 | |
mbed_official | 146:f64d43ff0c18 | 4491 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4492 | //! @brief Read current value of the AIPS_PACRE_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 4493 | #define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3)) |
mbed_official | 146:f64d43ff0c18 | 4494 | #endif |
mbed_official | 146:f64d43ff0c18 | 4495 | |
mbed_official | 146:f64d43ff0c18 | 4496 | //! @brief Format value for bitfield AIPS_PACRE_TP3. |
mbed_official | 146:f64d43ff0c18 | 4497 | #define BF_AIPS_PACRE_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP3), uint32_t) & BM_AIPS_PACRE_TP3) |
mbed_official | 146:f64d43ff0c18 | 4498 | |
mbed_official | 146:f64d43ff0c18 | 4499 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4500 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4501 | #define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4502 | #endif |
mbed_official | 146:f64d43ff0c18 | 4503 | //@} |
mbed_official | 146:f64d43ff0c18 | 4504 | |
mbed_official | 146:f64d43ff0c18 | 4505 | /*! |
mbed_official | 146:f64d43ff0c18 | 4506 | * @name Register AIPS_PACRE, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 4507 | * |
mbed_official | 146:f64d43ff0c18 | 4508 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 4509 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 4510 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4511 | * |
mbed_official | 146:f64d43ff0c18 | 4512 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4513 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4514 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4515 | */ |
mbed_official | 146:f64d43ff0c18 | 4516 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4517 | #define BP_AIPS_PACRE_WP3 (17U) //!< Bit position for AIPS_PACRE_WP3. |
mbed_official | 146:f64d43ff0c18 | 4518 | #define BM_AIPS_PACRE_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRE_WP3. |
mbed_official | 146:f64d43ff0c18 | 4519 | #define BS_AIPS_PACRE_WP3 (1U) //!< Bit field size in bits for AIPS_PACRE_WP3. |
mbed_official | 146:f64d43ff0c18 | 4520 | |
mbed_official | 146:f64d43ff0c18 | 4521 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4522 | //! @brief Read current value of the AIPS_PACRE_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 4523 | #define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3)) |
mbed_official | 146:f64d43ff0c18 | 4524 | #endif |
mbed_official | 146:f64d43ff0c18 | 4525 | |
mbed_official | 146:f64d43ff0c18 | 4526 | //! @brief Format value for bitfield AIPS_PACRE_WP3. |
mbed_official | 146:f64d43ff0c18 | 4527 | #define BF_AIPS_PACRE_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP3), uint32_t) & BM_AIPS_PACRE_WP3) |
mbed_official | 146:f64d43ff0c18 | 4528 | |
mbed_official | 146:f64d43ff0c18 | 4529 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4530 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4531 | #define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4532 | #endif |
mbed_official | 146:f64d43ff0c18 | 4533 | //@} |
mbed_official | 146:f64d43ff0c18 | 4534 | |
mbed_official | 146:f64d43ff0c18 | 4535 | /*! |
mbed_official | 146:f64d43ff0c18 | 4536 | * @name Register AIPS_PACRE, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 4537 | * |
mbed_official | 146:f64d43ff0c18 | 4538 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4539 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4540 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4541 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4542 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4543 | * |
mbed_official | 146:f64d43ff0c18 | 4544 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4545 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4546 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4547 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4548 | */ |
mbed_official | 146:f64d43ff0c18 | 4549 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4550 | #define BP_AIPS_PACRE_SP3 (18U) //!< Bit position for AIPS_PACRE_SP3. |
mbed_official | 146:f64d43ff0c18 | 4551 | #define BM_AIPS_PACRE_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRE_SP3. |
mbed_official | 146:f64d43ff0c18 | 4552 | #define BS_AIPS_PACRE_SP3 (1U) //!< Bit field size in bits for AIPS_PACRE_SP3. |
mbed_official | 146:f64d43ff0c18 | 4553 | |
mbed_official | 146:f64d43ff0c18 | 4554 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4555 | //! @brief Read current value of the AIPS_PACRE_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 4556 | #define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3)) |
mbed_official | 146:f64d43ff0c18 | 4557 | #endif |
mbed_official | 146:f64d43ff0c18 | 4558 | |
mbed_official | 146:f64d43ff0c18 | 4559 | //! @brief Format value for bitfield AIPS_PACRE_SP3. |
mbed_official | 146:f64d43ff0c18 | 4560 | #define BF_AIPS_PACRE_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP3), uint32_t) & BM_AIPS_PACRE_SP3) |
mbed_official | 146:f64d43ff0c18 | 4561 | |
mbed_official | 146:f64d43ff0c18 | 4562 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4563 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4564 | #define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4565 | #endif |
mbed_official | 146:f64d43ff0c18 | 4566 | //@} |
mbed_official | 146:f64d43ff0c18 | 4567 | |
mbed_official | 146:f64d43ff0c18 | 4568 | /*! |
mbed_official | 146:f64d43ff0c18 | 4569 | * @name Register AIPS_PACRE, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 4570 | * |
mbed_official | 146:f64d43ff0c18 | 4571 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4572 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4573 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4574 | * |
mbed_official | 146:f64d43ff0c18 | 4575 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4576 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4577 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4578 | */ |
mbed_official | 146:f64d43ff0c18 | 4579 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4580 | #define BP_AIPS_PACRE_TP2 (20U) //!< Bit position for AIPS_PACRE_TP2. |
mbed_official | 146:f64d43ff0c18 | 4581 | #define BM_AIPS_PACRE_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRE_TP2. |
mbed_official | 146:f64d43ff0c18 | 4582 | #define BS_AIPS_PACRE_TP2 (1U) //!< Bit field size in bits for AIPS_PACRE_TP2. |
mbed_official | 146:f64d43ff0c18 | 4583 | |
mbed_official | 146:f64d43ff0c18 | 4584 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4585 | //! @brief Read current value of the AIPS_PACRE_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 4586 | #define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2)) |
mbed_official | 146:f64d43ff0c18 | 4587 | #endif |
mbed_official | 146:f64d43ff0c18 | 4588 | |
mbed_official | 146:f64d43ff0c18 | 4589 | //! @brief Format value for bitfield AIPS_PACRE_TP2. |
mbed_official | 146:f64d43ff0c18 | 4590 | #define BF_AIPS_PACRE_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP2), uint32_t) & BM_AIPS_PACRE_TP2) |
mbed_official | 146:f64d43ff0c18 | 4591 | |
mbed_official | 146:f64d43ff0c18 | 4592 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4593 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4594 | #define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4595 | #endif |
mbed_official | 146:f64d43ff0c18 | 4596 | //@} |
mbed_official | 146:f64d43ff0c18 | 4597 | |
mbed_official | 146:f64d43ff0c18 | 4598 | /*! |
mbed_official | 146:f64d43ff0c18 | 4599 | * @name Register AIPS_PACRE, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 4600 | * |
mbed_official | 146:f64d43ff0c18 | 4601 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4602 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4603 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4604 | * |
mbed_official | 146:f64d43ff0c18 | 4605 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4606 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4607 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4608 | */ |
mbed_official | 146:f64d43ff0c18 | 4609 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4610 | #define BP_AIPS_PACRE_WP2 (21U) //!< Bit position for AIPS_PACRE_WP2. |
mbed_official | 146:f64d43ff0c18 | 4611 | #define BM_AIPS_PACRE_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRE_WP2. |
mbed_official | 146:f64d43ff0c18 | 4612 | #define BS_AIPS_PACRE_WP2 (1U) //!< Bit field size in bits for AIPS_PACRE_WP2. |
mbed_official | 146:f64d43ff0c18 | 4613 | |
mbed_official | 146:f64d43ff0c18 | 4614 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4615 | //! @brief Read current value of the AIPS_PACRE_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 4616 | #define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2)) |
mbed_official | 146:f64d43ff0c18 | 4617 | #endif |
mbed_official | 146:f64d43ff0c18 | 4618 | |
mbed_official | 146:f64d43ff0c18 | 4619 | //! @brief Format value for bitfield AIPS_PACRE_WP2. |
mbed_official | 146:f64d43ff0c18 | 4620 | #define BF_AIPS_PACRE_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP2), uint32_t) & BM_AIPS_PACRE_WP2) |
mbed_official | 146:f64d43ff0c18 | 4621 | |
mbed_official | 146:f64d43ff0c18 | 4622 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4623 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4624 | #define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4625 | #endif |
mbed_official | 146:f64d43ff0c18 | 4626 | //@} |
mbed_official | 146:f64d43ff0c18 | 4627 | |
mbed_official | 146:f64d43ff0c18 | 4628 | /*! |
mbed_official | 146:f64d43ff0c18 | 4629 | * @name Register AIPS_PACRE, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 4630 | * |
mbed_official | 146:f64d43ff0c18 | 4631 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4632 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4633 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 4634 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 4635 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 4636 | * |
mbed_official | 146:f64d43ff0c18 | 4637 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4638 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4639 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4640 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4641 | */ |
mbed_official | 146:f64d43ff0c18 | 4642 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4643 | #define BP_AIPS_PACRE_SP2 (22U) //!< Bit position for AIPS_PACRE_SP2. |
mbed_official | 146:f64d43ff0c18 | 4644 | #define BM_AIPS_PACRE_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRE_SP2. |
mbed_official | 146:f64d43ff0c18 | 4645 | #define BS_AIPS_PACRE_SP2 (1U) //!< Bit field size in bits for AIPS_PACRE_SP2. |
mbed_official | 146:f64d43ff0c18 | 4646 | |
mbed_official | 146:f64d43ff0c18 | 4647 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4648 | //! @brief Read current value of the AIPS_PACRE_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 4649 | #define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2)) |
mbed_official | 146:f64d43ff0c18 | 4650 | #endif |
mbed_official | 146:f64d43ff0c18 | 4651 | |
mbed_official | 146:f64d43ff0c18 | 4652 | //! @brief Format value for bitfield AIPS_PACRE_SP2. |
mbed_official | 146:f64d43ff0c18 | 4653 | #define BF_AIPS_PACRE_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP2), uint32_t) & BM_AIPS_PACRE_SP2) |
mbed_official | 146:f64d43ff0c18 | 4654 | |
mbed_official | 146:f64d43ff0c18 | 4655 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4656 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4657 | #define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4658 | #endif |
mbed_official | 146:f64d43ff0c18 | 4659 | //@} |
mbed_official | 146:f64d43ff0c18 | 4660 | |
mbed_official | 146:f64d43ff0c18 | 4661 | /*! |
mbed_official | 146:f64d43ff0c18 | 4662 | * @name Register AIPS_PACRE, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 4663 | * |
mbed_official | 146:f64d43ff0c18 | 4664 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4665 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4666 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4667 | * |
mbed_official | 146:f64d43ff0c18 | 4668 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4669 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4670 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4671 | */ |
mbed_official | 146:f64d43ff0c18 | 4672 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4673 | #define BP_AIPS_PACRE_TP1 (24U) //!< Bit position for AIPS_PACRE_TP1. |
mbed_official | 146:f64d43ff0c18 | 4674 | #define BM_AIPS_PACRE_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRE_TP1. |
mbed_official | 146:f64d43ff0c18 | 4675 | #define BS_AIPS_PACRE_TP1 (1U) //!< Bit field size in bits for AIPS_PACRE_TP1. |
mbed_official | 146:f64d43ff0c18 | 4676 | |
mbed_official | 146:f64d43ff0c18 | 4677 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4678 | //! @brief Read current value of the AIPS_PACRE_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 4679 | #define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1)) |
mbed_official | 146:f64d43ff0c18 | 4680 | #endif |
mbed_official | 146:f64d43ff0c18 | 4681 | |
mbed_official | 146:f64d43ff0c18 | 4682 | //! @brief Format value for bitfield AIPS_PACRE_TP1. |
mbed_official | 146:f64d43ff0c18 | 4683 | #define BF_AIPS_PACRE_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP1), uint32_t) & BM_AIPS_PACRE_TP1) |
mbed_official | 146:f64d43ff0c18 | 4684 | |
mbed_official | 146:f64d43ff0c18 | 4685 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4686 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4687 | #define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4688 | #endif |
mbed_official | 146:f64d43ff0c18 | 4689 | //@} |
mbed_official | 146:f64d43ff0c18 | 4690 | |
mbed_official | 146:f64d43ff0c18 | 4691 | /*! |
mbed_official | 146:f64d43ff0c18 | 4692 | * @name Register AIPS_PACRE, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 4693 | * |
mbed_official | 146:f64d43ff0c18 | 4694 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4695 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4696 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4697 | * |
mbed_official | 146:f64d43ff0c18 | 4698 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4699 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4700 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4701 | */ |
mbed_official | 146:f64d43ff0c18 | 4702 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4703 | #define BP_AIPS_PACRE_WP1 (25U) //!< Bit position for AIPS_PACRE_WP1. |
mbed_official | 146:f64d43ff0c18 | 4704 | #define BM_AIPS_PACRE_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRE_WP1. |
mbed_official | 146:f64d43ff0c18 | 4705 | #define BS_AIPS_PACRE_WP1 (1U) //!< Bit field size in bits for AIPS_PACRE_WP1. |
mbed_official | 146:f64d43ff0c18 | 4706 | |
mbed_official | 146:f64d43ff0c18 | 4707 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4708 | //! @brief Read current value of the AIPS_PACRE_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 4709 | #define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1)) |
mbed_official | 146:f64d43ff0c18 | 4710 | #endif |
mbed_official | 146:f64d43ff0c18 | 4711 | |
mbed_official | 146:f64d43ff0c18 | 4712 | //! @brief Format value for bitfield AIPS_PACRE_WP1. |
mbed_official | 146:f64d43ff0c18 | 4713 | #define BF_AIPS_PACRE_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP1), uint32_t) & BM_AIPS_PACRE_WP1) |
mbed_official | 146:f64d43ff0c18 | 4714 | |
mbed_official | 146:f64d43ff0c18 | 4715 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4716 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4717 | #define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4718 | #endif |
mbed_official | 146:f64d43ff0c18 | 4719 | //@} |
mbed_official | 146:f64d43ff0c18 | 4720 | |
mbed_official | 146:f64d43ff0c18 | 4721 | /*! |
mbed_official | 146:f64d43ff0c18 | 4722 | * @name Register AIPS_PACRE, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 4723 | * |
mbed_official | 146:f64d43ff0c18 | 4724 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4725 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4726 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 4727 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4728 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4729 | * |
mbed_official | 146:f64d43ff0c18 | 4730 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4731 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4732 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4733 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4734 | */ |
mbed_official | 146:f64d43ff0c18 | 4735 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4736 | #define BP_AIPS_PACRE_SP1 (26U) //!< Bit position for AIPS_PACRE_SP1. |
mbed_official | 146:f64d43ff0c18 | 4737 | #define BM_AIPS_PACRE_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRE_SP1. |
mbed_official | 146:f64d43ff0c18 | 4738 | #define BS_AIPS_PACRE_SP1 (1U) //!< Bit field size in bits for AIPS_PACRE_SP1. |
mbed_official | 146:f64d43ff0c18 | 4739 | |
mbed_official | 146:f64d43ff0c18 | 4740 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4741 | //! @brief Read current value of the AIPS_PACRE_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 4742 | #define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1)) |
mbed_official | 146:f64d43ff0c18 | 4743 | #endif |
mbed_official | 146:f64d43ff0c18 | 4744 | |
mbed_official | 146:f64d43ff0c18 | 4745 | //! @brief Format value for bitfield AIPS_PACRE_SP1. |
mbed_official | 146:f64d43ff0c18 | 4746 | #define BF_AIPS_PACRE_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP1), uint32_t) & BM_AIPS_PACRE_SP1) |
mbed_official | 146:f64d43ff0c18 | 4747 | |
mbed_official | 146:f64d43ff0c18 | 4748 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4749 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4750 | #define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4751 | #endif |
mbed_official | 146:f64d43ff0c18 | 4752 | //@} |
mbed_official | 146:f64d43ff0c18 | 4753 | |
mbed_official | 146:f64d43ff0c18 | 4754 | /*! |
mbed_official | 146:f64d43ff0c18 | 4755 | * @name Register AIPS_PACRE, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 4756 | * |
mbed_official | 146:f64d43ff0c18 | 4757 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4758 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4759 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4760 | * |
mbed_official | 146:f64d43ff0c18 | 4761 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4762 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4763 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4764 | */ |
mbed_official | 146:f64d43ff0c18 | 4765 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4766 | #define BP_AIPS_PACRE_TP0 (28U) //!< Bit position for AIPS_PACRE_TP0. |
mbed_official | 146:f64d43ff0c18 | 4767 | #define BM_AIPS_PACRE_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRE_TP0. |
mbed_official | 146:f64d43ff0c18 | 4768 | #define BS_AIPS_PACRE_TP0 (1U) //!< Bit field size in bits for AIPS_PACRE_TP0. |
mbed_official | 146:f64d43ff0c18 | 4769 | |
mbed_official | 146:f64d43ff0c18 | 4770 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4771 | //! @brief Read current value of the AIPS_PACRE_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 4772 | #define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0)) |
mbed_official | 146:f64d43ff0c18 | 4773 | #endif |
mbed_official | 146:f64d43ff0c18 | 4774 | |
mbed_official | 146:f64d43ff0c18 | 4775 | //! @brief Format value for bitfield AIPS_PACRE_TP0. |
mbed_official | 146:f64d43ff0c18 | 4776 | #define BF_AIPS_PACRE_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP0), uint32_t) & BM_AIPS_PACRE_TP0) |
mbed_official | 146:f64d43ff0c18 | 4777 | |
mbed_official | 146:f64d43ff0c18 | 4778 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4779 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4780 | #define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4781 | #endif |
mbed_official | 146:f64d43ff0c18 | 4782 | //@} |
mbed_official | 146:f64d43ff0c18 | 4783 | |
mbed_official | 146:f64d43ff0c18 | 4784 | /*! |
mbed_official | 146:f64d43ff0c18 | 4785 | * @name Register AIPS_PACRE, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 4786 | * |
mbed_official | 146:f64d43ff0c18 | 4787 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4788 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4789 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4790 | * |
mbed_official | 146:f64d43ff0c18 | 4791 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4792 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4793 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4794 | */ |
mbed_official | 146:f64d43ff0c18 | 4795 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4796 | #define BP_AIPS_PACRE_WP0 (29U) //!< Bit position for AIPS_PACRE_WP0. |
mbed_official | 146:f64d43ff0c18 | 4797 | #define BM_AIPS_PACRE_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRE_WP0. |
mbed_official | 146:f64d43ff0c18 | 4798 | #define BS_AIPS_PACRE_WP0 (1U) //!< Bit field size in bits for AIPS_PACRE_WP0. |
mbed_official | 146:f64d43ff0c18 | 4799 | |
mbed_official | 146:f64d43ff0c18 | 4800 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4801 | //! @brief Read current value of the AIPS_PACRE_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 4802 | #define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0)) |
mbed_official | 146:f64d43ff0c18 | 4803 | #endif |
mbed_official | 146:f64d43ff0c18 | 4804 | |
mbed_official | 146:f64d43ff0c18 | 4805 | //! @brief Format value for bitfield AIPS_PACRE_WP0. |
mbed_official | 146:f64d43ff0c18 | 4806 | #define BF_AIPS_PACRE_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP0), uint32_t) & BM_AIPS_PACRE_WP0) |
mbed_official | 146:f64d43ff0c18 | 4807 | |
mbed_official | 146:f64d43ff0c18 | 4808 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4809 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4810 | #define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4811 | #endif |
mbed_official | 146:f64d43ff0c18 | 4812 | //@} |
mbed_official | 146:f64d43ff0c18 | 4813 | |
mbed_official | 146:f64d43ff0c18 | 4814 | /*! |
mbed_official | 146:f64d43ff0c18 | 4815 | * @name Register AIPS_PACRE, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 4816 | * |
mbed_official | 146:f64d43ff0c18 | 4817 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4818 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4819 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4820 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4821 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4822 | * |
mbed_official | 146:f64d43ff0c18 | 4823 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4824 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4825 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4826 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4827 | */ |
mbed_official | 146:f64d43ff0c18 | 4828 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4829 | #define BP_AIPS_PACRE_SP0 (30U) //!< Bit position for AIPS_PACRE_SP0. |
mbed_official | 146:f64d43ff0c18 | 4830 | #define BM_AIPS_PACRE_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRE_SP0. |
mbed_official | 146:f64d43ff0c18 | 4831 | #define BS_AIPS_PACRE_SP0 (1U) //!< Bit field size in bits for AIPS_PACRE_SP0. |
mbed_official | 146:f64d43ff0c18 | 4832 | |
mbed_official | 146:f64d43ff0c18 | 4833 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4834 | //! @brief Read current value of the AIPS_PACRE_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 4835 | #define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0)) |
mbed_official | 146:f64d43ff0c18 | 4836 | #endif |
mbed_official | 146:f64d43ff0c18 | 4837 | |
mbed_official | 146:f64d43ff0c18 | 4838 | //! @brief Format value for bitfield AIPS_PACRE_SP0. |
mbed_official | 146:f64d43ff0c18 | 4839 | #define BF_AIPS_PACRE_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP0), uint32_t) & BM_AIPS_PACRE_SP0) |
mbed_official | 146:f64d43ff0c18 | 4840 | |
mbed_official | 146:f64d43ff0c18 | 4841 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4842 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4843 | #define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4844 | #endif |
mbed_official | 146:f64d43ff0c18 | 4845 | //@} |
mbed_official | 146:f64d43ff0c18 | 4846 | |
mbed_official | 146:f64d43ff0c18 | 4847 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4848 | // HW_AIPS_PACRF - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 4849 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4850 | |
mbed_official | 146:f64d43ff0c18 | 4851 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4852 | /*! |
mbed_official | 146:f64d43ff0c18 | 4853 | * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4854 | * |
mbed_official | 146:f64d43ff0c18 | 4855 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 4856 | * |
mbed_official | 146:f64d43ff0c18 | 4857 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 4858 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 4859 | * registers. |
mbed_official | 146:f64d43ff0c18 | 4860 | */ |
mbed_official | 146:f64d43ff0c18 | 4861 | typedef union _hw_aips_pacrf |
mbed_official | 146:f64d43ff0c18 | 4862 | { |
mbed_official | 146:f64d43ff0c18 | 4863 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 4864 | struct _hw_aips_pacrf_bitfields |
mbed_official | 146:f64d43ff0c18 | 4865 | { |
mbed_official | 146:f64d43ff0c18 | 4866 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4867 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4868 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4869 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 4870 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4871 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4872 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4873 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 4874 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4875 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4876 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4877 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 4878 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4879 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4880 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4881 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 4882 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4883 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4884 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4885 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 4886 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4887 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4888 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4889 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 4890 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4891 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4892 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4893 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 4894 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 4895 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 4896 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 4897 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 4898 | } B; |
mbed_official | 146:f64d43ff0c18 | 4899 | } hw_aips_pacrf_t; |
mbed_official | 146:f64d43ff0c18 | 4900 | #endif |
mbed_official | 146:f64d43ff0c18 | 4901 | |
mbed_official | 146:f64d43ff0c18 | 4902 | /*! |
mbed_official | 146:f64d43ff0c18 | 4903 | * @name Constants and macros for entire AIPS_PACRF register |
mbed_official | 146:f64d43ff0c18 | 4904 | */ |
mbed_official | 146:f64d43ff0c18 | 4905 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4906 | #define HW_AIPS_PACRF_ADDR(x) (REGS_AIPS_BASE(x) + 0x44U) |
mbed_official | 146:f64d43ff0c18 | 4907 | |
mbed_official | 146:f64d43ff0c18 | 4908 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4909 | #define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4910 | #define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U) |
mbed_official | 146:f64d43ff0c18 | 4911 | #define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4912 | #define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4913 | #define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4914 | #define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4915 | #endif |
mbed_official | 146:f64d43ff0c18 | 4916 | //@} |
mbed_official | 146:f64d43ff0c18 | 4917 | |
mbed_official | 146:f64d43ff0c18 | 4918 | /* |
mbed_official | 146:f64d43ff0c18 | 4919 | * Constants & macros for individual AIPS_PACRF bitfields |
mbed_official | 146:f64d43ff0c18 | 4920 | */ |
mbed_official | 146:f64d43ff0c18 | 4921 | |
mbed_official | 146:f64d43ff0c18 | 4922 | /*! |
mbed_official | 146:f64d43ff0c18 | 4923 | * @name Register AIPS_PACRF, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4924 | * |
mbed_official | 146:f64d43ff0c18 | 4925 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 4926 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 4927 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4928 | * |
mbed_official | 146:f64d43ff0c18 | 4929 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4930 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 4931 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 4932 | */ |
mbed_official | 146:f64d43ff0c18 | 4933 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4934 | #define BP_AIPS_PACRF_TP7 (0U) //!< Bit position for AIPS_PACRF_TP7. |
mbed_official | 146:f64d43ff0c18 | 4935 | #define BM_AIPS_PACRF_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRF_TP7. |
mbed_official | 146:f64d43ff0c18 | 4936 | #define BS_AIPS_PACRF_TP7 (1U) //!< Bit field size in bits for AIPS_PACRF_TP7. |
mbed_official | 146:f64d43ff0c18 | 4937 | |
mbed_official | 146:f64d43ff0c18 | 4938 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4939 | //! @brief Read current value of the AIPS_PACRF_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 4940 | #define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7)) |
mbed_official | 146:f64d43ff0c18 | 4941 | #endif |
mbed_official | 146:f64d43ff0c18 | 4942 | |
mbed_official | 146:f64d43ff0c18 | 4943 | //! @brief Format value for bitfield AIPS_PACRF_TP7. |
mbed_official | 146:f64d43ff0c18 | 4944 | #define BF_AIPS_PACRF_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP7), uint32_t) & BM_AIPS_PACRF_TP7) |
mbed_official | 146:f64d43ff0c18 | 4945 | |
mbed_official | 146:f64d43ff0c18 | 4946 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4947 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4948 | #define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4949 | #endif |
mbed_official | 146:f64d43ff0c18 | 4950 | //@} |
mbed_official | 146:f64d43ff0c18 | 4951 | |
mbed_official | 146:f64d43ff0c18 | 4952 | /*! |
mbed_official | 146:f64d43ff0c18 | 4953 | * @name Register AIPS_PACRF, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 4954 | * |
mbed_official | 146:f64d43ff0c18 | 4955 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 4956 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 4957 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 4958 | * |
mbed_official | 146:f64d43ff0c18 | 4959 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4960 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 4961 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 4962 | */ |
mbed_official | 146:f64d43ff0c18 | 4963 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4964 | #define BP_AIPS_PACRF_WP7 (1U) //!< Bit position for AIPS_PACRF_WP7. |
mbed_official | 146:f64d43ff0c18 | 4965 | #define BM_AIPS_PACRF_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRF_WP7. |
mbed_official | 146:f64d43ff0c18 | 4966 | #define BS_AIPS_PACRF_WP7 (1U) //!< Bit field size in bits for AIPS_PACRF_WP7. |
mbed_official | 146:f64d43ff0c18 | 4967 | |
mbed_official | 146:f64d43ff0c18 | 4968 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4969 | //! @brief Read current value of the AIPS_PACRF_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 4970 | #define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7)) |
mbed_official | 146:f64d43ff0c18 | 4971 | #endif |
mbed_official | 146:f64d43ff0c18 | 4972 | |
mbed_official | 146:f64d43ff0c18 | 4973 | //! @brief Format value for bitfield AIPS_PACRF_WP7. |
mbed_official | 146:f64d43ff0c18 | 4974 | #define BF_AIPS_PACRF_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP7), uint32_t) & BM_AIPS_PACRF_WP7) |
mbed_official | 146:f64d43ff0c18 | 4975 | |
mbed_official | 146:f64d43ff0c18 | 4976 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4977 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4978 | #define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4979 | #endif |
mbed_official | 146:f64d43ff0c18 | 4980 | //@} |
mbed_official | 146:f64d43ff0c18 | 4981 | |
mbed_official | 146:f64d43ff0c18 | 4982 | /*! |
mbed_official | 146:f64d43ff0c18 | 4983 | * @name Register AIPS_PACRF, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 4984 | * |
mbed_official | 146:f64d43ff0c18 | 4985 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4986 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 4987 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 4988 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 4989 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 4990 | * |
mbed_official | 146:f64d43ff0c18 | 4991 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4992 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 4993 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 4994 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 4995 | */ |
mbed_official | 146:f64d43ff0c18 | 4996 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4997 | #define BP_AIPS_PACRF_SP7 (2U) //!< Bit position for AIPS_PACRF_SP7. |
mbed_official | 146:f64d43ff0c18 | 4998 | #define BM_AIPS_PACRF_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRF_SP7. |
mbed_official | 146:f64d43ff0c18 | 4999 | #define BS_AIPS_PACRF_SP7 (1U) //!< Bit field size in bits for AIPS_PACRF_SP7. |
mbed_official | 146:f64d43ff0c18 | 5000 | |
mbed_official | 146:f64d43ff0c18 | 5001 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5002 | //! @brief Read current value of the AIPS_PACRF_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 5003 | #define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7)) |
mbed_official | 146:f64d43ff0c18 | 5004 | #endif |
mbed_official | 146:f64d43ff0c18 | 5005 | |
mbed_official | 146:f64d43ff0c18 | 5006 | //! @brief Format value for bitfield AIPS_PACRF_SP7. |
mbed_official | 146:f64d43ff0c18 | 5007 | #define BF_AIPS_PACRF_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP7), uint32_t) & BM_AIPS_PACRF_SP7) |
mbed_official | 146:f64d43ff0c18 | 5008 | |
mbed_official | 146:f64d43ff0c18 | 5009 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5010 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5011 | #define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5012 | #endif |
mbed_official | 146:f64d43ff0c18 | 5013 | //@} |
mbed_official | 146:f64d43ff0c18 | 5014 | |
mbed_official | 146:f64d43ff0c18 | 5015 | /*! |
mbed_official | 146:f64d43ff0c18 | 5016 | * @name Register AIPS_PACRF, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 5017 | * |
mbed_official | 146:f64d43ff0c18 | 5018 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5019 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5020 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5021 | * |
mbed_official | 146:f64d43ff0c18 | 5022 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5023 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5024 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5025 | */ |
mbed_official | 146:f64d43ff0c18 | 5026 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5027 | #define BP_AIPS_PACRF_TP6 (4U) //!< Bit position for AIPS_PACRF_TP6. |
mbed_official | 146:f64d43ff0c18 | 5028 | #define BM_AIPS_PACRF_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRF_TP6. |
mbed_official | 146:f64d43ff0c18 | 5029 | #define BS_AIPS_PACRF_TP6 (1U) //!< Bit field size in bits for AIPS_PACRF_TP6. |
mbed_official | 146:f64d43ff0c18 | 5030 | |
mbed_official | 146:f64d43ff0c18 | 5031 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5032 | //! @brief Read current value of the AIPS_PACRF_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 5033 | #define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6)) |
mbed_official | 146:f64d43ff0c18 | 5034 | #endif |
mbed_official | 146:f64d43ff0c18 | 5035 | |
mbed_official | 146:f64d43ff0c18 | 5036 | //! @brief Format value for bitfield AIPS_PACRF_TP6. |
mbed_official | 146:f64d43ff0c18 | 5037 | #define BF_AIPS_PACRF_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP6), uint32_t) & BM_AIPS_PACRF_TP6) |
mbed_official | 146:f64d43ff0c18 | 5038 | |
mbed_official | 146:f64d43ff0c18 | 5039 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5040 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5041 | #define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5042 | #endif |
mbed_official | 146:f64d43ff0c18 | 5043 | //@} |
mbed_official | 146:f64d43ff0c18 | 5044 | |
mbed_official | 146:f64d43ff0c18 | 5045 | /*! |
mbed_official | 146:f64d43ff0c18 | 5046 | * @name Register AIPS_PACRF, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 5047 | * |
mbed_official | 146:f64d43ff0c18 | 5048 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5049 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5050 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5051 | * |
mbed_official | 146:f64d43ff0c18 | 5052 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5053 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5054 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5055 | */ |
mbed_official | 146:f64d43ff0c18 | 5056 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5057 | #define BP_AIPS_PACRF_WP6 (5U) //!< Bit position for AIPS_PACRF_WP6. |
mbed_official | 146:f64d43ff0c18 | 5058 | #define BM_AIPS_PACRF_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRF_WP6. |
mbed_official | 146:f64d43ff0c18 | 5059 | #define BS_AIPS_PACRF_WP6 (1U) //!< Bit field size in bits for AIPS_PACRF_WP6. |
mbed_official | 146:f64d43ff0c18 | 5060 | |
mbed_official | 146:f64d43ff0c18 | 5061 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5062 | //! @brief Read current value of the AIPS_PACRF_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 5063 | #define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6)) |
mbed_official | 146:f64d43ff0c18 | 5064 | #endif |
mbed_official | 146:f64d43ff0c18 | 5065 | |
mbed_official | 146:f64d43ff0c18 | 5066 | //! @brief Format value for bitfield AIPS_PACRF_WP6. |
mbed_official | 146:f64d43ff0c18 | 5067 | #define BF_AIPS_PACRF_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP6), uint32_t) & BM_AIPS_PACRF_WP6) |
mbed_official | 146:f64d43ff0c18 | 5068 | |
mbed_official | 146:f64d43ff0c18 | 5069 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5070 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5071 | #define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5072 | #endif |
mbed_official | 146:f64d43ff0c18 | 5073 | //@} |
mbed_official | 146:f64d43ff0c18 | 5074 | |
mbed_official | 146:f64d43ff0c18 | 5075 | /*! |
mbed_official | 146:f64d43ff0c18 | 5076 | * @name Register AIPS_PACRF, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 5077 | * |
mbed_official | 146:f64d43ff0c18 | 5078 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5079 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5080 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5081 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5082 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5083 | * |
mbed_official | 146:f64d43ff0c18 | 5084 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5085 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5086 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5087 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5088 | */ |
mbed_official | 146:f64d43ff0c18 | 5089 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5090 | #define BP_AIPS_PACRF_SP6 (6U) //!< Bit position for AIPS_PACRF_SP6. |
mbed_official | 146:f64d43ff0c18 | 5091 | #define BM_AIPS_PACRF_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRF_SP6. |
mbed_official | 146:f64d43ff0c18 | 5092 | #define BS_AIPS_PACRF_SP6 (1U) //!< Bit field size in bits for AIPS_PACRF_SP6. |
mbed_official | 146:f64d43ff0c18 | 5093 | |
mbed_official | 146:f64d43ff0c18 | 5094 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5095 | //! @brief Read current value of the AIPS_PACRF_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 5096 | #define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6)) |
mbed_official | 146:f64d43ff0c18 | 5097 | #endif |
mbed_official | 146:f64d43ff0c18 | 5098 | |
mbed_official | 146:f64d43ff0c18 | 5099 | //! @brief Format value for bitfield AIPS_PACRF_SP6. |
mbed_official | 146:f64d43ff0c18 | 5100 | #define BF_AIPS_PACRF_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP6), uint32_t) & BM_AIPS_PACRF_SP6) |
mbed_official | 146:f64d43ff0c18 | 5101 | |
mbed_official | 146:f64d43ff0c18 | 5102 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5103 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5104 | #define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5105 | #endif |
mbed_official | 146:f64d43ff0c18 | 5106 | //@} |
mbed_official | 146:f64d43ff0c18 | 5107 | |
mbed_official | 146:f64d43ff0c18 | 5108 | /*! |
mbed_official | 146:f64d43ff0c18 | 5109 | * @name Register AIPS_PACRF, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 5110 | * |
mbed_official | 146:f64d43ff0c18 | 5111 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5112 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5113 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5114 | * |
mbed_official | 146:f64d43ff0c18 | 5115 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5116 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5117 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5118 | */ |
mbed_official | 146:f64d43ff0c18 | 5119 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5120 | #define BP_AIPS_PACRF_TP5 (8U) //!< Bit position for AIPS_PACRF_TP5. |
mbed_official | 146:f64d43ff0c18 | 5121 | #define BM_AIPS_PACRF_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRF_TP5. |
mbed_official | 146:f64d43ff0c18 | 5122 | #define BS_AIPS_PACRF_TP5 (1U) //!< Bit field size in bits for AIPS_PACRF_TP5. |
mbed_official | 146:f64d43ff0c18 | 5123 | |
mbed_official | 146:f64d43ff0c18 | 5124 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5125 | //! @brief Read current value of the AIPS_PACRF_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 5126 | #define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5)) |
mbed_official | 146:f64d43ff0c18 | 5127 | #endif |
mbed_official | 146:f64d43ff0c18 | 5128 | |
mbed_official | 146:f64d43ff0c18 | 5129 | //! @brief Format value for bitfield AIPS_PACRF_TP5. |
mbed_official | 146:f64d43ff0c18 | 5130 | #define BF_AIPS_PACRF_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP5), uint32_t) & BM_AIPS_PACRF_TP5) |
mbed_official | 146:f64d43ff0c18 | 5131 | |
mbed_official | 146:f64d43ff0c18 | 5132 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5133 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5134 | #define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5135 | #endif |
mbed_official | 146:f64d43ff0c18 | 5136 | //@} |
mbed_official | 146:f64d43ff0c18 | 5137 | |
mbed_official | 146:f64d43ff0c18 | 5138 | /*! |
mbed_official | 146:f64d43ff0c18 | 5139 | * @name Register AIPS_PACRF, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 5140 | * |
mbed_official | 146:f64d43ff0c18 | 5141 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5142 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5143 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5144 | * |
mbed_official | 146:f64d43ff0c18 | 5145 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5146 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5147 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5148 | */ |
mbed_official | 146:f64d43ff0c18 | 5149 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5150 | #define BP_AIPS_PACRF_WP5 (9U) //!< Bit position for AIPS_PACRF_WP5. |
mbed_official | 146:f64d43ff0c18 | 5151 | #define BM_AIPS_PACRF_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRF_WP5. |
mbed_official | 146:f64d43ff0c18 | 5152 | #define BS_AIPS_PACRF_WP5 (1U) //!< Bit field size in bits for AIPS_PACRF_WP5. |
mbed_official | 146:f64d43ff0c18 | 5153 | |
mbed_official | 146:f64d43ff0c18 | 5154 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5155 | //! @brief Read current value of the AIPS_PACRF_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 5156 | #define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5)) |
mbed_official | 146:f64d43ff0c18 | 5157 | #endif |
mbed_official | 146:f64d43ff0c18 | 5158 | |
mbed_official | 146:f64d43ff0c18 | 5159 | //! @brief Format value for bitfield AIPS_PACRF_WP5. |
mbed_official | 146:f64d43ff0c18 | 5160 | #define BF_AIPS_PACRF_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP5), uint32_t) & BM_AIPS_PACRF_WP5) |
mbed_official | 146:f64d43ff0c18 | 5161 | |
mbed_official | 146:f64d43ff0c18 | 5162 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5163 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5164 | #define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5165 | #endif |
mbed_official | 146:f64d43ff0c18 | 5166 | //@} |
mbed_official | 146:f64d43ff0c18 | 5167 | |
mbed_official | 146:f64d43ff0c18 | 5168 | /*! |
mbed_official | 146:f64d43ff0c18 | 5169 | * @name Register AIPS_PACRF, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 5170 | * |
mbed_official | 146:f64d43ff0c18 | 5171 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5172 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5173 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5174 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5175 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5176 | * |
mbed_official | 146:f64d43ff0c18 | 5177 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5178 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5179 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5180 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5181 | */ |
mbed_official | 146:f64d43ff0c18 | 5182 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5183 | #define BP_AIPS_PACRF_SP5 (10U) //!< Bit position for AIPS_PACRF_SP5. |
mbed_official | 146:f64d43ff0c18 | 5184 | #define BM_AIPS_PACRF_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRF_SP5. |
mbed_official | 146:f64d43ff0c18 | 5185 | #define BS_AIPS_PACRF_SP5 (1U) //!< Bit field size in bits for AIPS_PACRF_SP5. |
mbed_official | 146:f64d43ff0c18 | 5186 | |
mbed_official | 146:f64d43ff0c18 | 5187 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5188 | //! @brief Read current value of the AIPS_PACRF_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 5189 | #define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5)) |
mbed_official | 146:f64d43ff0c18 | 5190 | #endif |
mbed_official | 146:f64d43ff0c18 | 5191 | |
mbed_official | 146:f64d43ff0c18 | 5192 | //! @brief Format value for bitfield AIPS_PACRF_SP5. |
mbed_official | 146:f64d43ff0c18 | 5193 | #define BF_AIPS_PACRF_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP5), uint32_t) & BM_AIPS_PACRF_SP5) |
mbed_official | 146:f64d43ff0c18 | 5194 | |
mbed_official | 146:f64d43ff0c18 | 5195 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5196 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5197 | #define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5198 | #endif |
mbed_official | 146:f64d43ff0c18 | 5199 | //@} |
mbed_official | 146:f64d43ff0c18 | 5200 | |
mbed_official | 146:f64d43ff0c18 | 5201 | /*! |
mbed_official | 146:f64d43ff0c18 | 5202 | * @name Register AIPS_PACRF, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 5203 | * |
mbed_official | 146:f64d43ff0c18 | 5204 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5205 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5206 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5207 | * |
mbed_official | 146:f64d43ff0c18 | 5208 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5209 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5210 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5211 | */ |
mbed_official | 146:f64d43ff0c18 | 5212 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5213 | #define BP_AIPS_PACRF_TP4 (12U) //!< Bit position for AIPS_PACRF_TP4. |
mbed_official | 146:f64d43ff0c18 | 5214 | #define BM_AIPS_PACRF_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRF_TP4. |
mbed_official | 146:f64d43ff0c18 | 5215 | #define BS_AIPS_PACRF_TP4 (1U) //!< Bit field size in bits for AIPS_PACRF_TP4. |
mbed_official | 146:f64d43ff0c18 | 5216 | |
mbed_official | 146:f64d43ff0c18 | 5217 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5218 | //! @brief Read current value of the AIPS_PACRF_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 5219 | #define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4)) |
mbed_official | 146:f64d43ff0c18 | 5220 | #endif |
mbed_official | 146:f64d43ff0c18 | 5221 | |
mbed_official | 146:f64d43ff0c18 | 5222 | //! @brief Format value for bitfield AIPS_PACRF_TP4. |
mbed_official | 146:f64d43ff0c18 | 5223 | #define BF_AIPS_PACRF_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP4), uint32_t) & BM_AIPS_PACRF_TP4) |
mbed_official | 146:f64d43ff0c18 | 5224 | |
mbed_official | 146:f64d43ff0c18 | 5225 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5226 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5227 | #define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5228 | #endif |
mbed_official | 146:f64d43ff0c18 | 5229 | //@} |
mbed_official | 146:f64d43ff0c18 | 5230 | |
mbed_official | 146:f64d43ff0c18 | 5231 | /*! |
mbed_official | 146:f64d43ff0c18 | 5232 | * @name Register AIPS_PACRF, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 5233 | * |
mbed_official | 146:f64d43ff0c18 | 5234 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5235 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5236 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5237 | * |
mbed_official | 146:f64d43ff0c18 | 5238 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5239 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5240 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5241 | */ |
mbed_official | 146:f64d43ff0c18 | 5242 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5243 | #define BP_AIPS_PACRF_WP4 (13U) //!< Bit position for AIPS_PACRF_WP4. |
mbed_official | 146:f64d43ff0c18 | 5244 | #define BM_AIPS_PACRF_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRF_WP4. |
mbed_official | 146:f64d43ff0c18 | 5245 | #define BS_AIPS_PACRF_WP4 (1U) //!< Bit field size in bits for AIPS_PACRF_WP4. |
mbed_official | 146:f64d43ff0c18 | 5246 | |
mbed_official | 146:f64d43ff0c18 | 5247 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5248 | //! @brief Read current value of the AIPS_PACRF_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 5249 | #define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4)) |
mbed_official | 146:f64d43ff0c18 | 5250 | #endif |
mbed_official | 146:f64d43ff0c18 | 5251 | |
mbed_official | 146:f64d43ff0c18 | 5252 | //! @brief Format value for bitfield AIPS_PACRF_WP4. |
mbed_official | 146:f64d43ff0c18 | 5253 | #define BF_AIPS_PACRF_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP4), uint32_t) & BM_AIPS_PACRF_WP4) |
mbed_official | 146:f64d43ff0c18 | 5254 | |
mbed_official | 146:f64d43ff0c18 | 5255 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5256 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5257 | #define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5258 | #endif |
mbed_official | 146:f64d43ff0c18 | 5259 | //@} |
mbed_official | 146:f64d43ff0c18 | 5260 | |
mbed_official | 146:f64d43ff0c18 | 5261 | /*! |
mbed_official | 146:f64d43ff0c18 | 5262 | * @name Register AIPS_PACRF, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 5263 | * |
mbed_official | 146:f64d43ff0c18 | 5264 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5265 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5266 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 5267 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 5268 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 5269 | * |
mbed_official | 146:f64d43ff0c18 | 5270 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5271 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5272 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5273 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5274 | */ |
mbed_official | 146:f64d43ff0c18 | 5275 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5276 | #define BP_AIPS_PACRF_SP4 (14U) //!< Bit position for AIPS_PACRF_SP4. |
mbed_official | 146:f64d43ff0c18 | 5277 | #define BM_AIPS_PACRF_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRF_SP4. |
mbed_official | 146:f64d43ff0c18 | 5278 | #define BS_AIPS_PACRF_SP4 (1U) //!< Bit field size in bits for AIPS_PACRF_SP4. |
mbed_official | 146:f64d43ff0c18 | 5279 | |
mbed_official | 146:f64d43ff0c18 | 5280 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5281 | //! @brief Read current value of the AIPS_PACRF_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 5282 | #define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4)) |
mbed_official | 146:f64d43ff0c18 | 5283 | #endif |
mbed_official | 146:f64d43ff0c18 | 5284 | |
mbed_official | 146:f64d43ff0c18 | 5285 | //! @brief Format value for bitfield AIPS_PACRF_SP4. |
mbed_official | 146:f64d43ff0c18 | 5286 | #define BF_AIPS_PACRF_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP4), uint32_t) & BM_AIPS_PACRF_SP4) |
mbed_official | 146:f64d43ff0c18 | 5287 | |
mbed_official | 146:f64d43ff0c18 | 5288 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5289 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5290 | #define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5291 | #endif |
mbed_official | 146:f64d43ff0c18 | 5292 | //@} |
mbed_official | 146:f64d43ff0c18 | 5293 | |
mbed_official | 146:f64d43ff0c18 | 5294 | /*! |
mbed_official | 146:f64d43ff0c18 | 5295 | * @name Register AIPS_PACRF, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 5296 | * |
mbed_official | 146:f64d43ff0c18 | 5297 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5298 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5299 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5300 | * |
mbed_official | 146:f64d43ff0c18 | 5301 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5302 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5303 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5304 | */ |
mbed_official | 146:f64d43ff0c18 | 5305 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5306 | #define BP_AIPS_PACRF_TP3 (16U) //!< Bit position for AIPS_PACRF_TP3. |
mbed_official | 146:f64d43ff0c18 | 5307 | #define BM_AIPS_PACRF_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRF_TP3. |
mbed_official | 146:f64d43ff0c18 | 5308 | #define BS_AIPS_PACRF_TP3 (1U) //!< Bit field size in bits for AIPS_PACRF_TP3. |
mbed_official | 146:f64d43ff0c18 | 5309 | |
mbed_official | 146:f64d43ff0c18 | 5310 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5311 | //! @brief Read current value of the AIPS_PACRF_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 5312 | #define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3)) |
mbed_official | 146:f64d43ff0c18 | 5313 | #endif |
mbed_official | 146:f64d43ff0c18 | 5314 | |
mbed_official | 146:f64d43ff0c18 | 5315 | //! @brief Format value for bitfield AIPS_PACRF_TP3. |
mbed_official | 146:f64d43ff0c18 | 5316 | #define BF_AIPS_PACRF_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP3), uint32_t) & BM_AIPS_PACRF_TP3) |
mbed_official | 146:f64d43ff0c18 | 5317 | |
mbed_official | 146:f64d43ff0c18 | 5318 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5319 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5320 | #define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5321 | #endif |
mbed_official | 146:f64d43ff0c18 | 5322 | //@} |
mbed_official | 146:f64d43ff0c18 | 5323 | |
mbed_official | 146:f64d43ff0c18 | 5324 | /*! |
mbed_official | 146:f64d43ff0c18 | 5325 | * @name Register AIPS_PACRF, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 5326 | * |
mbed_official | 146:f64d43ff0c18 | 5327 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 5328 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 5329 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5330 | * |
mbed_official | 146:f64d43ff0c18 | 5331 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5332 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5333 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5334 | */ |
mbed_official | 146:f64d43ff0c18 | 5335 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5336 | #define BP_AIPS_PACRF_WP3 (17U) //!< Bit position for AIPS_PACRF_WP3. |
mbed_official | 146:f64d43ff0c18 | 5337 | #define BM_AIPS_PACRF_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRF_WP3. |
mbed_official | 146:f64d43ff0c18 | 5338 | #define BS_AIPS_PACRF_WP3 (1U) //!< Bit field size in bits for AIPS_PACRF_WP3. |
mbed_official | 146:f64d43ff0c18 | 5339 | |
mbed_official | 146:f64d43ff0c18 | 5340 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5341 | //! @brief Read current value of the AIPS_PACRF_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 5342 | #define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3)) |
mbed_official | 146:f64d43ff0c18 | 5343 | #endif |
mbed_official | 146:f64d43ff0c18 | 5344 | |
mbed_official | 146:f64d43ff0c18 | 5345 | //! @brief Format value for bitfield AIPS_PACRF_WP3. |
mbed_official | 146:f64d43ff0c18 | 5346 | #define BF_AIPS_PACRF_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP3), uint32_t) & BM_AIPS_PACRF_WP3) |
mbed_official | 146:f64d43ff0c18 | 5347 | |
mbed_official | 146:f64d43ff0c18 | 5348 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5349 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5350 | #define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5351 | #endif |
mbed_official | 146:f64d43ff0c18 | 5352 | //@} |
mbed_official | 146:f64d43ff0c18 | 5353 | |
mbed_official | 146:f64d43ff0c18 | 5354 | /*! |
mbed_official | 146:f64d43ff0c18 | 5355 | * @name Register AIPS_PACRF, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 5356 | * |
mbed_official | 146:f64d43ff0c18 | 5357 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5358 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5359 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5360 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5361 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5362 | * |
mbed_official | 146:f64d43ff0c18 | 5363 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5364 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5365 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5366 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5367 | */ |
mbed_official | 146:f64d43ff0c18 | 5368 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5369 | #define BP_AIPS_PACRF_SP3 (18U) //!< Bit position for AIPS_PACRF_SP3. |
mbed_official | 146:f64d43ff0c18 | 5370 | #define BM_AIPS_PACRF_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRF_SP3. |
mbed_official | 146:f64d43ff0c18 | 5371 | #define BS_AIPS_PACRF_SP3 (1U) //!< Bit field size in bits for AIPS_PACRF_SP3. |
mbed_official | 146:f64d43ff0c18 | 5372 | |
mbed_official | 146:f64d43ff0c18 | 5373 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5374 | //! @brief Read current value of the AIPS_PACRF_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 5375 | #define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3)) |
mbed_official | 146:f64d43ff0c18 | 5376 | #endif |
mbed_official | 146:f64d43ff0c18 | 5377 | |
mbed_official | 146:f64d43ff0c18 | 5378 | //! @brief Format value for bitfield AIPS_PACRF_SP3. |
mbed_official | 146:f64d43ff0c18 | 5379 | #define BF_AIPS_PACRF_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP3), uint32_t) & BM_AIPS_PACRF_SP3) |
mbed_official | 146:f64d43ff0c18 | 5380 | |
mbed_official | 146:f64d43ff0c18 | 5381 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5382 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5383 | #define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5384 | #endif |
mbed_official | 146:f64d43ff0c18 | 5385 | //@} |
mbed_official | 146:f64d43ff0c18 | 5386 | |
mbed_official | 146:f64d43ff0c18 | 5387 | /*! |
mbed_official | 146:f64d43ff0c18 | 5388 | * @name Register AIPS_PACRF, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 5389 | * |
mbed_official | 146:f64d43ff0c18 | 5390 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5391 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5392 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5393 | * |
mbed_official | 146:f64d43ff0c18 | 5394 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5395 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5396 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5397 | */ |
mbed_official | 146:f64d43ff0c18 | 5398 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5399 | #define BP_AIPS_PACRF_TP2 (20U) //!< Bit position for AIPS_PACRF_TP2. |
mbed_official | 146:f64d43ff0c18 | 5400 | #define BM_AIPS_PACRF_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRF_TP2. |
mbed_official | 146:f64d43ff0c18 | 5401 | #define BS_AIPS_PACRF_TP2 (1U) //!< Bit field size in bits for AIPS_PACRF_TP2. |
mbed_official | 146:f64d43ff0c18 | 5402 | |
mbed_official | 146:f64d43ff0c18 | 5403 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5404 | //! @brief Read current value of the AIPS_PACRF_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 5405 | #define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2)) |
mbed_official | 146:f64d43ff0c18 | 5406 | #endif |
mbed_official | 146:f64d43ff0c18 | 5407 | |
mbed_official | 146:f64d43ff0c18 | 5408 | //! @brief Format value for bitfield AIPS_PACRF_TP2. |
mbed_official | 146:f64d43ff0c18 | 5409 | #define BF_AIPS_PACRF_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP2), uint32_t) & BM_AIPS_PACRF_TP2) |
mbed_official | 146:f64d43ff0c18 | 5410 | |
mbed_official | 146:f64d43ff0c18 | 5411 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5412 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5413 | #define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5414 | #endif |
mbed_official | 146:f64d43ff0c18 | 5415 | //@} |
mbed_official | 146:f64d43ff0c18 | 5416 | |
mbed_official | 146:f64d43ff0c18 | 5417 | /*! |
mbed_official | 146:f64d43ff0c18 | 5418 | * @name Register AIPS_PACRF, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 5419 | * |
mbed_official | 146:f64d43ff0c18 | 5420 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5421 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5422 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5423 | * |
mbed_official | 146:f64d43ff0c18 | 5424 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5425 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5426 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5427 | */ |
mbed_official | 146:f64d43ff0c18 | 5428 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5429 | #define BP_AIPS_PACRF_WP2 (21U) //!< Bit position for AIPS_PACRF_WP2. |
mbed_official | 146:f64d43ff0c18 | 5430 | #define BM_AIPS_PACRF_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRF_WP2. |
mbed_official | 146:f64d43ff0c18 | 5431 | #define BS_AIPS_PACRF_WP2 (1U) //!< Bit field size in bits for AIPS_PACRF_WP2. |
mbed_official | 146:f64d43ff0c18 | 5432 | |
mbed_official | 146:f64d43ff0c18 | 5433 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5434 | //! @brief Read current value of the AIPS_PACRF_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 5435 | #define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2)) |
mbed_official | 146:f64d43ff0c18 | 5436 | #endif |
mbed_official | 146:f64d43ff0c18 | 5437 | |
mbed_official | 146:f64d43ff0c18 | 5438 | //! @brief Format value for bitfield AIPS_PACRF_WP2. |
mbed_official | 146:f64d43ff0c18 | 5439 | #define BF_AIPS_PACRF_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP2), uint32_t) & BM_AIPS_PACRF_WP2) |
mbed_official | 146:f64d43ff0c18 | 5440 | |
mbed_official | 146:f64d43ff0c18 | 5441 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5442 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5443 | #define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5444 | #endif |
mbed_official | 146:f64d43ff0c18 | 5445 | //@} |
mbed_official | 146:f64d43ff0c18 | 5446 | |
mbed_official | 146:f64d43ff0c18 | 5447 | /*! |
mbed_official | 146:f64d43ff0c18 | 5448 | * @name Register AIPS_PACRF, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 5449 | * |
mbed_official | 146:f64d43ff0c18 | 5450 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5451 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5452 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 5453 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 5454 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 5455 | * |
mbed_official | 146:f64d43ff0c18 | 5456 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5457 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5458 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5459 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5460 | */ |
mbed_official | 146:f64d43ff0c18 | 5461 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5462 | #define BP_AIPS_PACRF_SP2 (22U) //!< Bit position for AIPS_PACRF_SP2. |
mbed_official | 146:f64d43ff0c18 | 5463 | #define BM_AIPS_PACRF_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRF_SP2. |
mbed_official | 146:f64d43ff0c18 | 5464 | #define BS_AIPS_PACRF_SP2 (1U) //!< Bit field size in bits for AIPS_PACRF_SP2. |
mbed_official | 146:f64d43ff0c18 | 5465 | |
mbed_official | 146:f64d43ff0c18 | 5466 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5467 | //! @brief Read current value of the AIPS_PACRF_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 5468 | #define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2)) |
mbed_official | 146:f64d43ff0c18 | 5469 | #endif |
mbed_official | 146:f64d43ff0c18 | 5470 | |
mbed_official | 146:f64d43ff0c18 | 5471 | //! @brief Format value for bitfield AIPS_PACRF_SP2. |
mbed_official | 146:f64d43ff0c18 | 5472 | #define BF_AIPS_PACRF_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP2), uint32_t) & BM_AIPS_PACRF_SP2) |
mbed_official | 146:f64d43ff0c18 | 5473 | |
mbed_official | 146:f64d43ff0c18 | 5474 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5475 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5476 | #define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5477 | #endif |
mbed_official | 146:f64d43ff0c18 | 5478 | //@} |
mbed_official | 146:f64d43ff0c18 | 5479 | |
mbed_official | 146:f64d43ff0c18 | 5480 | /*! |
mbed_official | 146:f64d43ff0c18 | 5481 | * @name Register AIPS_PACRF, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 5482 | * |
mbed_official | 146:f64d43ff0c18 | 5483 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5484 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5485 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5486 | * |
mbed_official | 146:f64d43ff0c18 | 5487 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5488 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5489 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5490 | */ |
mbed_official | 146:f64d43ff0c18 | 5491 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5492 | #define BP_AIPS_PACRF_TP1 (24U) //!< Bit position for AIPS_PACRF_TP1. |
mbed_official | 146:f64d43ff0c18 | 5493 | #define BM_AIPS_PACRF_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRF_TP1. |
mbed_official | 146:f64d43ff0c18 | 5494 | #define BS_AIPS_PACRF_TP1 (1U) //!< Bit field size in bits for AIPS_PACRF_TP1. |
mbed_official | 146:f64d43ff0c18 | 5495 | |
mbed_official | 146:f64d43ff0c18 | 5496 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5497 | //! @brief Read current value of the AIPS_PACRF_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 5498 | #define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1)) |
mbed_official | 146:f64d43ff0c18 | 5499 | #endif |
mbed_official | 146:f64d43ff0c18 | 5500 | |
mbed_official | 146:f64d43ff0c18 | 5501 | //! @brief Format value for bitfield AIPS_PACRF_TP1. |
mbed_official | 146:f64d43ff0c18 | 5502 | #define BF_AIPS_PACRF_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP1), uint32_t) & BM_AIPS_PACRF_TP1) |
mbed_official | 146:f64d43ff0c18 | 5503 | |
mbed_official | 146:f64d43ff0c18 | 5504 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5505 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5506 | #define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5507 | #endif |
mbed_official | 146:f64d43ff0c18 | 5508 | //@} |
mbed_official | 146:f64d43ff0c18 | 5509 | |
mbed_official | 146:f64d43ff0c18 | 5510 | /*! |
mbed_official | 146:f64d43ff0c18 | 5511 | * @name Register AIPS_PACRF, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 5512 | * |
mbed_official | 146:f64d43ff0c18 | 5513 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5514 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5515 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5516 | * |
mbed_official | 146:f64d43ff0c18 | 5517 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5518 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5519 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5520 | */ |
mbed_official | 146:f64d43ff0c18 | 5521 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5522 | #define BP_AIPS_PACRF_WP1 (25U) //!< Bit position for AIPS_PACRF_WP1. |
mbed_official | 146:f64d43ff0c18 | 5523 | #define BM_AIPS_PACRF_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRF_WP1. |
mbed_official | 146:f64d43ff0c18 | 5524 | #define BS_AIPS_PACRF_WP1 (1U) //!< Bit field size in bits for AIPS_PACRF_WP1. |
mbed_official | 146:f64d43ff0c18 | 5525 | |
mbed_official | 146:f64d43ff0c18 | 5526 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5527 | //! @brief Read current value of the AIPS_PACRF_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 5528 | #define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1)) |
mbed_official | 146:f64d43ff0c18 | 5529 | #endif |
mbed_official | 146:f64d43ff0c18 | 5530 | |
mbed_official | 146:f64d43ff0c18 | 5531 | //! @brief Format value for bitfield AIPS_PACRF_WP1. |
mbed_official | 146:f64d43ff0c18 | 5532 | #define BF_AIPS_PACRF_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP1), uint32_t) & BM_AIPS_PACRF_WP1) |
mbed_official | 146:f64d43ff0c18 | 5533 | |
mbed_official | 146:f64d43ff0c18 | 5534 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5535 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5536 | #define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5537 | #endif |
mbed_official | 146:f64d43ff0c18 | 5538 | //@} |
mbed_official | 146:f64d43ff0c18 | 5539 | |
mbed_official | 146:f64d43ff0c18 | 5540 | /*! |
mbed_official | 146:f64d43ff0c18 | 5541 | * @name Register AIPS_PACRF, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 5542 | * |
mbed_official | 146:f64d43ff0c18 | 5543 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5544 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5545 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 5546 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5547 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5548 | * |
mbed_official | 146:f64d43ff0c18 | 5549 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5550 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5551 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5552 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5553 | */ |
mbed_official | 146:f64d43ff0c18 | 5554 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5555 | #define BP_AIPS_PACRF_SP1 (26U) //!< Bit position for AIPS_PACRF_SP1. |
mbed_official | 146:f64d43ff0c18 | 5556 | #define BM_AIPS_PACRF_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRF_SP1. |
mbed_official | 146:f64d43ff0c18 | 5557 | #define BS_AIPS_PACRF_SP1 (1U) //!< Bit field size in bits for AIPS_PACRF_SP1. |
mbed_official | 146:f64d43ff0c18 | 5558 | |
mbed_official | 146:f64d43ff0c18 | 5559 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5560 | //! @brief Read current value of the AIPS_PACRF_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 5561 | #define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1)) |
mbed_official | 146:f64d43ff0c18 | 5562 | #endif |
mbed_official | 146:f64d43ff0c18 | 5563 | |
mbed_official | 146:f64d43ff0c18 | 5564 | //! @brief Format value for bitfield AIPS_PACRF_SP1. |
mbed_official | 146:f64d43ff0c18 | 5565 | #define BF_AIPS_PACRF_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP1), uint32_t) & BM_AIPS_PACRF_SP1) |
mbed_official | 146:f64d43ff0c18 | 5566 | |
mbed_official | 146:f64d43ff0c18 | 5567 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5568 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5569 | #define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5570 | #endif |
mbed_official | 146:f64d43ff0c18 | 5571 | //@} |
mbed_official | 146:f64d43ff0c18 | 5572 | |
mbed_official | 146:f64d43ff0c18 | 5573 | /*! |
mbed_official | 146:f64d43ff0c18 | 5574 | * @name Register AIPS_PACRF, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 5575 | * |
mbed_official | 146:f64d43ff0c18 | 5576 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5577 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5578 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5579 | * |
mbed_official | 146:f64d43ff0c18 | 5580 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5581 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5582 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5583 | */ |
mbed_official | 146:f64d43ff0c18 | 5584 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5585 | #define BP_AIPS_PACRF_TP0 (28U) //!< Bit position for AIPS_PACRF_TP0. |
mbed_official | 146:f64d43ff0c18 | 5586 | #define BM_AIPS_PACRF_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRF_TP0. |
mbed_official | 146:f64d43ff0c18 | 5587 | #define BS_AIPS_PACRF_TP0 (1U) //!< Bit field size in bits for AIPS_PACRF_TP0. |
mbed_official | 146:f64d43ff0c18 | 5588 | |
mbed_official | 146:f64d43ff0c18 | 5589 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5590 | //! @brief Read current value of the AIPS_PACRF_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 5591 | #define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0)) |
mbed_official | 146:f64d43ff0c18 | 5592 | #endif |
mbed_official | 146:f64d43ff0c18 | 5593 | |
mbed_official | 146:f64d43ff0c18 | 5594 | //! @brief Format value for bitfield AIPS_PACRF_TP0. |
mbed_official | 146:f64d43ff0c18 | 5595 | #define BF_AIPS_PACRF_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP0), uint32_t) & BM_AIPS_PACRF_TP0) |
mbed_official | 146:f64d43ff0c18 | 5596 | |
mbed_official | 146:f64d43ff0c18 | 5597 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5598 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5599 | #define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5600 | #endif |
mbed_official | 146:f64d43ff0c18 | 5601 | //@} |
mbed_official | 146:f64d43ff0c18 | 5602 | |
mbed_official | 146:f64d43ff0c18 | 5603 | /*! |
mbed_official | 146:f64d43ff0c18 | 5604 | * @name Register AIPS_PACRF, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 5605 | * |
mbed_official | 146:f64d43ff0c18 | 5606 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5607 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5608 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5609 | * |
mbed_official | 146:f64d43ff0c18 | 5610 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5611 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5612 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5613 | */ |
mbed_official | 146:f64d43ff0c18 | 5614 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5615 | #define BP_AIPS_PACRF_WP0 (29U) //!< Bit position for AIPS_PACRF_WP0. |
mbed_official | 146:f64d43ff0c18 | 5616 | #define BM_AIPS_PACRF_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRF_WP0. |
mbed_official | 146:f64d43ff0c18 | 5617 | #define BS_AIPS_PACRF_WP0 (1U) //!< Bit field size in bits for AIPS_PACRF_WP0. |
mbed_official | 146:f64d43ff0c18 | 5618 | |
mbed_official | 146:f64d43ff0c18 | 5619 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5620 | //! @brief Read current value of the AIPS_PACRF_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 5621 | #define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0)) |
mbed_official | 146:f64d43ff0c18 | 5622 | #endif |
mbed_official | 146:f64d43ff0c18 | 5623 | |
mbed_official | 146:f64d43ff0c18 | 5624 | //! @brief Format value for bitfield AIPS_PACRF_WP0. |
mbed_official | 146:f64d43ff0c18 | 5625 | #define BF_AIPS_PACRF_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP0), uint32_t) & BM_AIPS_PACRF_WP0) |
mbed_official | 146:f64d43ff0c18 | 5626 | |
mbed_official | 146:f64d43ff0c18 | 5627 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5628 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5629 | #define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5630 | #endif |
mbed_official | 146:f64d43ff0c18 | 5631 | //@} |
mbed_official | 146:f64d43ff0c18 | 5632 | |
mbed_official | 146:f64d43ff0c18 | 5633 | /*! |
mbed_official | 146:f64d43ff0c18 | 5634 | * @name Register AIPS_PACRF, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 5635 | * |
mbed_official | 146:f64d43ff0c18 | 5636 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5637 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5638 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5639 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5640 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5641 | * |
mbed_official | 146:f64d43ff0c18 | 5642 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5643 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5644 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5645 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5646 | */ |
mbed_official | 146:f64d43ff0c18 | 5647 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5648 | #define BP_AIPS_PACRF_SP0 (30U) //!< Bit position for AIPS_PACRF_SP0. |
mbed_official | 146:f64d43ff0c18 | 5649 | #define BM_AIPS_PACRF_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRF_SP0. |
mbed_official | 146:f64d43ff0c18 | 5650 | #define BS_AIPS_PACRF_SP0 (1U) //!< Bit field size in bits for AIPS_PACRF_SP0. |
mbed_official | 146:f64d43ff0c18 | 5651 | |
mbed_official | 146:f64d43ff0c18 | 5652 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5653 | //! @brief Read current value of the AIPS_PACRF_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 5654 | #define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0)) |
mbed_official | 146:f64d43ff0c18 | 5655 | #endif |
mbed_official | 146:f64d43ff0c18 | 5656 | |
mbed_official | 146:f64d43ff0c18 | 5657 | //! @brief Format value for bitfield AIPS_PACRF_SP0. |
mbed_official | 146:f64d43ff0c18 | 5658 | #define BF_AIPS_PACRF_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP0), uint32_t) & BM_AIPS_PACRF_SP0) |
mbed_official | 146:f64d43ff0c18 | 5659 | |
mbed_official | 146:f64d43ff0c18 | 5660 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5661 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5662 | #define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5663 | #endif |
mbed_official | 146:f64d43ff0c18 | 5664 | //@} |
mbed_official | 146:f64d43ff0c18 | 5665 | |
mbed_official | 146:f64d43ff0c18 | 5666 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5667 | // HW_AIPS_PACRG - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 5668 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 5669 | |
mbed_official | 146:f64d43ff0c18 | 5670 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5671 | /*! |
mbed_official | 146:f64d43ff0c18 | 5672 | * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 5673 | * |
mbed_official | 146:f64d43ff0c18 | 5674 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 5675 | * |
mbed_official | 146:f64d43ff0c18 | 5676 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 5677 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 5678 | * registers. |
mbed_official | 146:f64d43ff0c18 | 5679 | */ |
mbed_official | 146:f64d43ff0c18 | 5680 | typedef union _hw_aips_pacrg |
mbed_official | 146:f64d43ff0c18 | 5681 | { |
mbed_official | 146:f64d43ff0c18 | 5682 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 5683 | struct _hw_aips_pacrg_bitfields |
mbed_official | 146:f64d43ff0c18 | 5684 | { |
mbed_official | 146:f64d43ff0c18 | 5685 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5686 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5687 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5688 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 5689 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5690 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5691 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5692 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 5693 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5694 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5695 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5696 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 5697 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5698 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5699 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5700 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 5701 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5702 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5703 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5704 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 5705 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5706 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5707 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5708 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 5709 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5710 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5711 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5712 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 5713 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 5714 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 5715 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 5716 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 5717 | } B; |
mbed_official | 146:f64d43ff0c18 | 5718 | } hw_aips_pacrg_t; |
mbed_official | 146:f64d43ff0c18 | 5719 | #endif |
mbed_official | 146:f64d43ff0c18 | 5720 | |
mbed_official | 146:f64d43ff0c18 | 5721 | /*! |
mbed_official | 146:f64d43ff0c18 | 5722 | * @name Constants and macros for entire AIPS_PACRG register |
mbed_official | 146:f64d43ff0c18 | 5723 | */ |
mbed_official | 146:f64d43ff0c18 | 5724 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5725 | #define HW_AIPS_PACRG_ADDR(x) (REGS_AIPS_BASE(x) + 0x48U) |
mbed_official | 146:f64d43ff0c18 | 5726 | |
mbed_official | 146:f64d43ff0c18 | 5727 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5728 | #define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 5729 | #define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U) |
mbed_official | 146:f64d43ff0c18 | 5730 | #define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 5731 | #define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 5732 | #define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 5733 | #define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 5734 | #endif |
mbed_official | 146:f64d43ff0c18 | 5735 | //@} |
mbed_official | 146:f64d43ff0c18 | 5736 | |
mbed_official | 146:f64d43ff0c18 | 5737 | /* |
mbed_official | 146:f64d43ff0c18 | 5738 | * Constants & macros for individual AIPS_PACRG bitfields |
mbed_official | 146:f64d43ff0c18 | 5739 | */ |
mbed_official | 146:f64d43ff0c18 | 5740 | |
mbed_official | 146:f64d43ff0c18 | 5741 | /*! |
mbed_official | 146:f64d43ff0c18 | 5742 | * @name Register AIPS_PACRG, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 5743 | * |
mbed_official | 146:f64d43ff0c18 | 5744 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5745 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5746 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5747 | * |
mbed_official | 146:f64d43ff0c18 | 5748 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5749 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5750 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5751 | */ |
mbed_official | 146:f64d43ff0c18 | 5752 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5753 | #define BP_AIPS_PACRG_TP7 (0U) //!< Bit position for AIPS_PACRG_TP7. |
mbed_official | 146:f64d43ff0c18 | 5754 | #define BM_AIPS_PACRG_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRG_TP7. |
mbed_official | 146:f64d43ff0c18 | 5755 | #define BS_AIPS_PACRG_TP7 (1U) //!< Bit field size in bits for AIPS_PACRG_TP7. |
mbed_official | 146:f64d43ff0c18 | 5756 | |
mbed_official | 146:f64d43ff0c18 | 5757 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5758 | //! @brief Read current value of the AIPS_PACRG_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 5759 | #define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7)) |
mbed_official | 146:f64d43ff0c18 | 5760 | #endif |
mbed_official | 146:f64d43ff0c18 | 5761 | |
mbed_official | 146:f64d43ff0c18 | 5762 | //! @brief Format value for bitfield AIPS_PACRG_TP7. |
mbed_official | 146:f64d43ff0c18 | 5763 | #define BF_AIPS_PACRG_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP7), uint32_t) & BM_AIPS_PACRG_TP7) |
mbed_official | 146:f64d43ff0c18 | 5764 | |
mbed_official | 146:f64d43ff0c18 | 5765 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5766 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5767 | #define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5768 | #endif |
mbed_official | 146:f64d43ff0c18 | 5769 | //@} |
mbed_official | 146:f64d43ff0c18 | 5770 | |
mbed_official | 146:f64d43ff0c18 | 5771 | /*! |
mbed_official | 146:f64d43ff0c18 | 5772 | * @name Register AIPS_PACRG, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 5773 | * |
mbed_official | 146:f64d43ff0c18 | 5774 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5775 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5776 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5777 | * |
mbed_official | 146:f64d43ff0c18 | 5778 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5779 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5780 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5781 | */ |
mbed_official | 146:f64d43ff0c18 | 5782 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5783 | #define BP_AIPS_PACRG_WP7 (1U) //!< Bit position for AIPS_PACRG_WP7. |
mbed_official | 146:f64d43ff0c18 | 5784 | #define BM_AIPS_PACRG_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRG_WP7. |
mbed_official | 146:f64d43ff0c18 | 5785 | #define BS_AIPS_PACRG_WP7 (1U) //!< Bit field size in bits for AIPS_PACRG_WP7. |
mbed_official | 146:f64d43ff0c18 | 5786 | |
mbed_official | 146:f64d43ff0c18 | 5787 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5788 | //! @brief Read current value of the AIPS_PACRG_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 5789 | #define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7)) |
mbed_official | 146:f64d43ff0c18 | 5790 | #endif |
mbed_official | 146:f64d43ff0c18 | 5791 | |
mbed_official | 146:f64d43ff0c18 | 5792 | //! @brief Format value for bitfield AIPS_PACRG_WP7. |
mbed_official | 146:f64d43ff0c18 | 5793 | #define BF_AIPS_PACRG_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP7), uint32_t) & BM_AIPS_PACRG_WP7) |
mbed_official | 146:f64d43ff0c18 | 5794 | |
mbed_official | 146:f64d43ff0c18 | 5795 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5796 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5797 | #define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5798 | #endif |
mbed_official | 146:f64d43ff0c18 | 5799 | //@} |
mbed_official | 146:f64d43ff0c18 | 5800 | |
mbed_official | 146:f64d43ff0c18 | 5801 | /*! |
mbed_official | 146:f64d43ff0c18 | 5802 | * @name Register AIPS_PACRG, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 5803 | * |
mbed_official | 146:f64d43ff0c18 | 5804 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5805 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5806 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5807 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5808 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5809 | * |
mbed_official | 146:f64d43ff0c18 | 5810 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5811 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5812 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5813 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5814 | */ |
mbed_official | 146:f64d43ff0c18 | 5815 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5816 | #define BP_AIPS_PACRG_SP7 (2U) //!< Bit position for AIPS_PACRG_SP7. |
mbed_official | 146:f64d43ff0c18 | 5817 | #define BM_AIPS_PACRG_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRG_SP7. |
mbed_official | 146:f64d43ff0c18 | 5818 | #define BS_AIPS_PACRG_SP7 (1U) //!< Bit field size in bits for AIPS_PACRG_SP7. |
mbed_official | 146:f64d43ff0c18 | 5819 | |
mbed_official | 146:f64d43ff0c18 | 5820 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5821 | //! @brief Read current value of the AIPS_PACRG_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 5822 | #define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7)) |
mbed_official | 146:f64d43ff0c18 | 5823 | #endif |
mbed_official | 146:f64d43ff0c18 | 5824 | |
mbed_official | 146:f64d43ff0c18 | 5825 | //! @brief Format value for bitfield AIPS_PACRG_SP7. |
mbed_official | 146:f64d43ff0c18 | 5826 | #define BF_AIPS_PACRG_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP7), uint32_t) & BM_AIPS_PACRG_SP7) |
mbed_official | 146:f64d43ff0c18 | 5827 | |
mbed_official | 146:f64d43ff0c18 | 5828 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5829 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5830 | #define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5831 | #endif |
mbed_official | 146:f64d43ff0c18 | 5832 | //@} |
mbed_official | 146:f64d43ff0c18 | 5833 | |
mbed_official | 146:f64d43ff0c18 | 5834 | /*! |
mbed_official | 146:f64d43ff0c18 | 5835 | * @name Register AIPS_PACRG, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 5836 | * |
mbed_official | 146:f64d43ff0c18 | 5837 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5838 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5839 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5840 | * |
mbed_official | 146:f64d43ff0c18 | 5841 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5842 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5843 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5844 | */ |
mbed_official | 146:f64d43ff0c18 | 5845 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5846 | #define BP_AIPS_PACRG_TP6 (4U) //!< Bit position for AIPS_PACRG_TP6. |
mbed_official | 146:f64d43ff0c18 | 5847 | #define BM_AIPS_PACRG_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRG_TP6. |
mbed_official | 146:f64d43ff0c18 | 5848 | #define BS_AIPS_PACRG_TP6 (1U) //!< Bit field size in bits for AIPS_PACRG_TP6. |
mbed_official | 146:f64d43ff0c18 | 5849 | |
mbed_official | 146:f64d43ff0c18 | 5850 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5851 | //! @brief Read current value of the AIPS_PACRG_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 5852 | #define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6)) |
mbed_official | 146:f64d43ff0c18 | 5853 | #endif |
mbed_official | 146:f64d43ff0c18 | 5854 | |
mbed_official | 146:f64d43ff0c18 | 5855 | //! @brief Format value for bitfield AIPS_PACRG_TP6. |
mbed_official | 146:f64d43ff0c18 | 5856 | #define BF_AIPS_PACRG_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP6), uint32_t) & BM_AIPS_PACRG_TP6) |
mbed_official | 146:f64d43ff0c18 | 5857 | |
mbed_official | 146:f64d43ff0c18 | 5858 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5859 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5860 | #define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5861 | #endif |
mbed_official | 146:f64d43ff0c18 | 5862 | //@} |
mbed_official | 146:f64d43ff0c18 | 5863 | |
mbed_official | 146:f64d43ff0c18 | 5864 | /*! |
mbed_official | 146:f64d43ff0c18 | 5865 | * @name Register AIPS_PACRG, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 5866 | * |
mbed_official | 146:f64d43ff0c18 | 5867 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5868 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5869 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5870 | * |
mbed_official | 146:f64d43ff0c18 | 5871 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5872 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5873 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5874 | */ |
mbed_official | 146:f64d43ff0c18 | 5875 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5876 | #define BP_AIPS_PACRG_WP6 (5U) //!< Bit position for AIPS_PACRG_WP6. |
mbed_official | 146:f64d43ff0c18 | 5877 | #define BM_AIPS_PACRG_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRG_WP6. |
mbed_official | 146:f64d43ff0c18 | 5878 | #define BS_AIPS_PACRG_WP6 (1U) //!< Bit field size in bits for AIPS_PACRG_WP6. |
mbed_official | 146:f64d43ff0c18 | 5879 | |
mbed_official | 146:f64d43ff0c18 | 5880 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5881 | //! @brief Read current value of the AIPS_PACRG_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 5882 | #define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6)) |
mbed_official | 146:f64d43ff0c18 | 5883 | #endif |
mbed_official | 146:f64d43ff0c18 | 5884 | |
mbed_official | 146:f64d43ff0c18 | 5885 | //! @brief Format value for bitfield AIPS_PACRG_WP6. |
mbed_official | 146:f64d43ff0c18 | 5886 | #define BF_AIPS_PACRG_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP6), uint32_t) & BM_AIPS_PACRG_WP6) |
mbed_official | 146:f64d43ff0c18 | 5887 | |
mbed_official | 146:f64d43ff0c18 | 5888 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5889 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5890 | #define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5891 | #endif |
mbed_official | 146:f64d43ff0c18 | 5892 | //@} |
mbed_official | 146:f64d43ff0c18 | 5893 | |
mbed_official | 146:f64d43ff0c18 | 5894 | /*! |
mbed_official | 146:f64d43ff0c18 | 5895 | * @name Register AIPS_PACRG, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 5896 | * |
mbed_official | 146:f64d43ff0c18 | 5897 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5898 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5899 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5900 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5901 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5902 | * |
mbed_official | 146:f64d43ff0c18 | 5903 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5904 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5905 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5906 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 5907 | */ |
mbed_official | 146:f64d43ff0c18 | 5908 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5909 | #define BP_AIPS_PACRG_SP6 (6U) //!< Bit position for AIPS_PACRG_SP6. |
mbed_official | 146:f64d43ff0c18 | 5910 | #define BM_AIPS_PACRG_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRG_SP6. |
mbed_official | 146:f64d43ff0c18 | 5911 | #define BS_AIPS_PACRG_SP6 (1U) //!< Bit field size in bits for AIPS_PACRG_SP6. |
mbed_official | 146:f64d43ff0c18 | 5912 | |
mbed_official | 146:f64d43ff0c18 | 5913 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5914 | //! @brief Read current value of the AIPS_PACRG_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 5915 | #define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6)) |
mbed_official | 146:f64d43ff0c18 | 5916 | #endif |
mbed_official | 146:f64d43ff0c18 | 5917 | |
mbed_official | 146:f64d43ff0c18 | 5918 | //! @brief Format value for bitfield AIPS_PACRG_SP6. |
mbed_official | 146:f64d43ff0c18 | 5919 | #define BF_AIPS_PACRG_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP6), uint32_t) & BM_AIPS_PACRG_SP6) |
mbed_official | 146:f64d43ff0c18 | 5920 | |
mbed_official | 146:f64d43ff0c18 | 5921 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5922 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5923 | #define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5924 | #endif |
mbed_official | 146:f64d43ff0c18 | 5925 | //@} |
mbed_official | 146:f64d43ff0c18 | 5926 | |
mbed_official | 146:f64d43ff0c18 | 5927 | /*! |
mbed_official | 146:f64d43ff0c18 | 5928 | * @name Register AIPS_PACRG, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 5929 | * |
mbed_official | 146:f64d43ff0c18 | 5930 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 5931 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 5932 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5933 | * |
mbed_official | 146:f64d43ff0c18 | 5934 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5935 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 5936 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 5937 | */ |
mbed_official | 146:f64d43ff0c18 | 5938 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5939 | #define BP_AIPS_PACRG_TP5 (8U) //!< Bit position for AIPS_PACRG_TP5. |
mbed_official | 146:f64d43ff0c18 | 5940 | #define BM_AIPS_PACRG_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRG_TP5. |
mbed_official | 146:f64d43ff0c18 | 5941 | #define BS_AIPS_PACRG_TP5 (1U) //!< Bit field size in bits for AIPS_PACRG_TP5. |
mbed_official | 146:f64d43ff0c18 | 5942 | |
mbed_official | 146:f64d43ff0c18 | 5943 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5944 | //! @brief Read current value of the AIPS_PACRG_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 5945 | #define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5)) |
mbed_official | 146:f64d43ff0c18 | 5946 | #endif |
mbed_official | 146:f64d43ff0c18 | 5947 | |
mbed_official | 146:f64d43ff0c18 | 5948 | //! @brief Format value for bitfield AIPS_PACRG_TP5. |
mbed_official | 146:f64d43ff0c18 | 5949 | #define BF_AIPS_PACRG_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP5), uint32_t) & BM_AIPS_PACRG_TP5) |
mbed_official | 146:f64d43ff0c18 | 5950 | |
mbed_official | 146:f64d43ff0c18 | 5951 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5952 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5953 | #define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5954 | #endif |
mbed_official | 146:f64d43ff0c18 | 5955 | //@} |
mbed_official | 146:f64d43ff0c18 | 5956 | |
mbed_official | 146:f64d43ff0c18 | 5957 | /*! |
mbed_official | 146:f64d43ff0c18 | 5958 | * @name Register AIPS_PACRG, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 5959 | * |
mbed_official | 146:f64d43ff0c18 | 5960 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 5961 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 5962 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 5963 | * |
mbed_official | 146:f64d43ff0c18 | 5964 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5965 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 5966 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 5967 | */ |
mbed_official | 146:f64d43ff0c18 | 5968 | //@{ |
mbed_official | 146:f64d43ff0c18 | 5969 | #define BP_AIPS_PACRG_WP5 (9U) //!< Bit position for AIPS_PACRG_WP5. |
mbed_official | 146:f64d43ff0c18 | 5970 | #define BM_AIPS_PACRG_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRG_WP5. |
mbed_official | 146:f64d43ff0c18 | 5971 | #define BS_AIPS_PACRG_WP5 (1U) //!< Bit field size in bits for AIPS_PACRG_WP5. |
mbed_official | 146:f64d43ff0c18 | 5972 | |
mbed_official | 146:f64d43ff0c18 | 5973 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5974 | //! @brief Read current value of the AIPS_PACRG_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 5975 | #define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5)) |
mbed_official | 146:f64d43ff0c18 | 5976 | #endif |
mbed_official | 146:f64d43ff0c18 | 5977 | |
mbed_official | 146:f64d43ff0c18 | 5978 | //! @brief Format value for bitfield AIPS_PACRG_WP5. |
mbed_official | 146:f64d43ff0c18 | 5979 | #define BF_AIPS_PACRG_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP5), uint32_t) & BM_AIPS_PACRG_WP5) |
mbed_official | 146:f64d43ff0c18 | 5980 | |
mbed_official | 146:f64d43ff0c18 | 5981 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 5982 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 5983 | #define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 5984 | #endif |
mbed_official | 146:f64d43ff0c18 | 5985 | //@} |
mbed_official | 146:f64d43ff0c18 | 5986 | |
mbed_official | 146:f64d43ff0c18 | 5987 | /*! |
mbed_official | 146:f64d43ff0c18 | 5988 | * @name Register AIPS_PACRG, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 5989 | * |
mbed_official | 146:f64d43ff0c18 | 5990 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5991 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 5992 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 5993 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 5994 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 5995 | * |
mbed_official | 146:f64d43ff0c18 | 5996 | * Values: |
mbed_official | 146:f64d43ff0c18 | 5997 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 5998 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 5999 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6000 | */ |
mbed_official | 146:f64d43ff0c18 | 6001 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6002 | #define BP_AIPS_PACRG_SP5 (10U) //!< Bit position for AIPS_PACRG_SP5. |
mbed_official | 146:f64d43ff0c18 | 6003 | #define BM_AIPS_PACRG_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRG_SP5. |
mbed_official | 146:f64d43ff0c18 | 6004 | #define BS_AIPS_PACRG_SP5 (1U) //!< Bit field size in bits for AIPS_PACRG_SP5. |
mbed_official | 146:f64d43ff0c18 | 6005 | |
mbed_official | 146:f64d43ff0c18 | 6006 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6007 | //! @brief Read current value of the AIPS_PACRG_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 6008 | #define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5)) |
mbed_official | 146:f64d43ff0c18 | 6009 | #endif |
mbed_official | 146:f64d43ff0c18 | 6010 | |
mbed_official | 146:f64d43ff0c18 | 6011 | //! @brief Format value for bitfield AIPS_PACRG_SP5. |
mbed_official | 146:f64d43ff0c18 | 6012 | #define BF_AIPS_PACRG_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP5), uint32_t) & BM_AIPS_PACRG_SP5) |
mbed_official | 146:f64d43ff0c18 | 6013 | |
mbed_official | 146:f64d43ff0c18 | 6014 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6015 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6016 | #define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6017 | #endif |
mbed_official | 146:f64d43ff0c18 | 6018 | //@} |
mbed_official | 146:f64d43ff0c18 | 6019 | |
mbed_official | 146:f64d43ff0c18 | 6020 | /*! |
mbed_official | 146:f64d43ff0c18 | 6021 | * @name Register AIPS_PACRG, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 6022 | * |
mbed_official | 146:f64d43ff0c18 | 6023 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6024 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6025 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6026 | * |
mbed_official | 146:f64d43ff0c18 | 6027 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6028 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6029 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6030 | */ |
mbed_official | 146:f64d43ff0c18 | 6031 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6032 | #define BP_AIPS_PACRG_TP4 (12U) //!< Bit position for AIPS_PACRG_TP4. |
mbed_official | 146:f64d43ff0c18 | 6033 | #define BM_AIPS_PACRG_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRG_TP4. |
mbed_official | 146:f64d43ff0c18 | 6034 | #define BS_AIPS_PACRG_TP4 (1U) //!< Bit field size in bits for AIPS_PACRG_TP4. |
mbed_official | 146:f64d43ff0c18 | 6035 | |
mbed_official | 146:f64d43ff0c18 | 6036 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6037 | //! @brief Read current value of the AIPS_PACRG_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 6038 | #define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4)) |
mbed_official | 146:f64d43ff0c18 | 6039 | #endif |
mbed_official | 146:f64d43ff0c18 | 6040 | |
mbed_official | 146:f64d43ff0c18 | 6041 | //! @brief Format value for bitfield AIPS_PACRG_TP4. |
mbed_official | 146:f64d43ff0c18 | 6042 | #define BF_AIPS_PACRG_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP4), uint32_t) & BM_AIPS_PACRG_TP4) |
mbed_official | 146:f64d43ff0c18 | 6043 | |
mbed_official | 146:f64d43ff0c18 | 6044 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6045 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6046 | #define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6047 | #endif |
mbed_official | 146:f64d43ff0c18 | 6048 | //@} |
mbed_official | 146:f64d43ff0c18 | 6049 | |
mbed_official | 146:f64d43ff0c18 | 6050 | /*! |
mbed_official | 146:f64d43ff0c18 | 6051 | * @name Register AIPS_PACRG, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 6052 | * |
mbed_official | 146:f64d43ff0c18 | 6053 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6054 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6055 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6056 | * |
mbed_official | 146:f64d43ff0c18 | 6057 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6058 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6059 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6060 | */ |
mbed_official | 146:f64d43ff0c18 | 6061 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6062 | #define BP_AIPS_PACRG_WP4 (13U) //!< Bit position for AIPS_PACRG_WP4. |
mbed_official | 146:f64d43ff0c18 | 6063 | #define BM_AIPS_PACRG_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRG_WP4. |
mbed_official | 146:f64d43ff0c18 | 6064 | #define BS_AIPS_PACRG_WP4 (1U) //!< Bit field size in bits for AIPS_PACRG_WP4. |
mbed_official | 146:f64d43ff0c18 | 6065 | |
mbed_official | 146:f64d43ff0c18 | 6066 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6067 | //! @brief Read current value of the AIPS_PACRG_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 6068 | #define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4)) |
mbed_official | 146:f64d43ff0c18 | 6069 | #endif |
mbed_official | 146:f64d43ff0c18 | 6070 | |
mbed_official | 146:f64d43ff0c18 | 6071 | //! @brief Format value for bitfield AIPS_PACRG_WP4. |
mbed_official | 146:f64d43ff0c18 | 6072 | #define BF_AIPS_PACRG_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP4), uint32_t) & BM_AIPS_PACRG_WP4) |
mbed_official | 146:f64d43ff0c18 | 6073 | |
mbed_official | 146:f64d43ff0c18 | 6074 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6075 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6076 | #define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6077 | #endif |
mbed_official | 146:f64d43ff0c18 | 6078 | //@} |
mbed_official | 146:f64d43ff0c18 | 6079 | |
mbed_official | 146:f64d43ff0c18 | 6080 | /*! |
mbed_official | 146:f64d43ff0c18 | 6081 | * @name Register AIPS_PACRG, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 6082 | * |
mbed_official | 146:f64d43ff0c18 | 6083 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6084 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6085 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 6086 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 6087 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 6088 | * |
mbed_official | 146:f64d43ff0c18 | 6089 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6090 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6091 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6092 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6093 | */ |
mbed_official | 146:f64d43ff0c18 | 6094 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6095 | #define BP_AIPS_PACRG_SP4 (14U) //!< Bit position for AIPS_PACRG_SP4. |
mbed_official | 146:f64d43ff0c18 | 6096 | #define BM_AIPS_PACRG_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRG_SP4. |
mbed_official | 146:f64d43ff0c18 | 6097 | #define BS_AIPS_PACRG_SP4 (1U) //!< Bit field size in bits for AIPS_PACRG_SP4. |
mbed_official | 146:f64d43ff0c18 | 6098 | |
mbed_official | 146:f64d43ff0c18 | 6099 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6100 | //! @brief Read current value of the AIPS_PACRG_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 6101 | #define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4)) |
mbed_official | 146:f64d43ff0c18 | 6102 | #endif |
mbed_official | 146:f64d43ff0c18 | 6103 | |
mbed_official | 146:f64d43ff0c18 | 6104 | //! @brief Format value for bitfield AIPS_PACRG_SP4. |
mbed_official | 146:f64d43ff0c18 | 6105 | #define BF_AIPS_PACRG_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP4), uint32_t) & BM_AIPS_PACRG_SP4) |
mbed_official | 146:f64d43ff0c18 | 6106 | |
mbed_official | 146:f64d43ff0c18 | 6107 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6108 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6109 | #define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6110 | #endif |
mbed_official | 146:f64d43ff0c18 | 6111 | //@} |
mbed_official | 146:f64d43ff0c18 | 6112 | |
mbed_official | 146:f64d43ff0c18 | 6113 | /*! |
mbed_official | 146:f64d43ff0c18 | 6114 | * @name Register AIPS_PACRG, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 6115 | * |
mbed_official | 146:f64d43ff0c18 | 6116 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6117 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6118 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6119 | * |
mbed_official | 146:f64d43ff0c18 | 6120 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6121 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6122 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6123 | */ |
mbed_official | 146:f64d43ff0c18 | 6124 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6125 | #define BP_AIPS_PACRG_TP3 (16U) //!< Bit position for AIPS_PACRG_TP3. |
mbed_official | 146:f64d43ff0c18 | 6126 | #define BM_AIPS_PACRG_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRG_TP3. |
mbed_official | 146:f64d43ff0c18 | 6127 | #define BS_AIPS_PACRG_TP3 (1U) //!< Bit field size in bits for AIPS_PACRG_TP3. |
mbed_official | 146:f64d43ff0c18 | 6128 | |
mbed_official | 146:f64d43ff0c18 | 6129 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6130 | //! @brief Read current value of the AIPS_PACRG_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 6131 | #define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3)) |
mbed_official | 146:f64d43ff0c18 | 6132 | #endif |
mbed_official | 146:f64d43ff0c18 | 6133 | |
mbed_official | 146:f64d43ff0c18 | 6134 | //! @brief Format value for bitfield AIPS_PACRG_TP3. |
mbed_official | 146:f64d43ff0c18 | 6135 | #define BF_AIPS_PACRG_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP3), uint32_t) & BM_AIPS_PACRG_TP3) |
mbed_official | 146:f64d43ff0c18 | 6136 | |
mbed_official | 146:f64d43ff0c18 | 6137 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6138 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6139 | #define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6140 | #endif |
mbed_official | 146:f64d43ff0c18 | 6141 | //@} |
mbed_official | 146:f64d43ff0c18 | 6142 | |
mbed_official | 146:f64d43ff0c18 | 6143 | /*! |
mbed_official | 146:f64d43ff0c18 | 6144 | * @name Register AIPS_PACRG, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 6145 | * |
mbed_official | 146:f64d43ff0c18 | 6146 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 6147 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 6148 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6149 | * |
mbed_official | 146:f64d43ff0c18 | 6150 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6151 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6152 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6153 | */ |
mbed_official | 146:f64d43ff0c18 | 6154 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6155 | #define BP_AIPS_PACRG_WP3 (17U) //!< Bit position for AIPS_PACRG_WP3. |
mbed_official | 146:f64d43ff0c18 | 6156 | #define BM_AIPS_PACRG_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRG_WP3. |
mbed_official | 146:f64d43ff0c18 | 6157 | #define BS_AIPS_PACRG_WP3 (1U) //!< Bit field size in bits for AIPS_PACRG_WP3. |
mbed_official | 146:f64d43ff0c18 | 6158 | |
mbed_official | 146:f64d43ff0c18 | 6159 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6160 | //! @brief Read current value of the AIPS_PACRG_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 6161 | #define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3)) |
mbed_official | 146:f64d43ff0c18 | 6162 | #endif |
mbed_official | 146:f64d43ff0c18 | 6163 | |
mbed_official | 146:f64d43ff0c18 | 6164 | //! @brief Format value for bitfield AIPS_PACRG_WP3. |
mbed_official | 146:f64d43ff0c18 | 6165 | #define BF_AIPS_PACRG_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP3), uint32_t) & BM_AIPS_PACRG_WP3) |
mbed_official | 146:f64d43ff0c18 | 6166 | |
mbed_official | 146:f64d43ff0c18 | 6167 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6168 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6169 | #define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6170 | #endif |
mbed_official | 146:f64d43ff0c18 | 6171 | //@} |
mbed_official | 146:f64d43ff0c18 | 6172 | |
mbed_official | 146:f64d43ff0c18 | 6173 | /*! |
mbed_official | 146:f64d43ff0c18 | 6174 | * @name Register AIPS_PACRG, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 6175 | * |
mbed_official | 146:f64d43ff0c18 | 6176 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6177 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6178 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 6179 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6180 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 6181 | * |
mbed_official | 146:f64d43ff0c18 | 6182 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6183 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6184 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6185 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6186 | */ |
mbed_official | 146:f64d43ff0c18 | 6187 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6188 | #define BP_AIPS_PACRG_SP3 (18U) //!< Bit position for AIPS_PACRG_SP3. |
mbed_official | 146:f64d43ff0c18 | 6189 | #define BM_AIPS_PACRG_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRG_SP3. |
mbed_official | 146:f64d43ff0c18 | 6190 | #define BS_AIPS_PACRG_SP3 (1U) //!< Bit field size in bits for AIPS_PACRG_SP3. |
mbed_official | 146:f64d43ff0c18 | 6191 | |
mbed_official | 146:f64d43ff0c18 | 6192 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6193 | //! @brief Read current value of the AIPS_PACRG_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 6194 | #define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3)) |
mbed_official | 146:f64d43ff0c18 | 6195 | #endif |
mbed_official | 146:f64d43ff0c18 | 6196 | |
mbed_official | 146:f64d43ff0c18 | 6197 | //! @brief Format value for bitfield AIPS_PACRG_SP3. |
mbed_official | 146:f64d43ff0c18 | 6198 | #define BF_AIPS_PACRG_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP3), uint32_t) & BM_AIPS_PACRG_SP3) |
mbed_official | 146:f64d43ff0c18 | 6199 | |
mbed_official | 146:f64d43ff0c18 | 6200 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6201 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6202 | #define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6203 | #endif |
mbed_official | 146:f64d43ff0c18 | 6204 | //@} |
mbed_official | 146:f64d43ff0c18 | 6205 | |
mbed_official | 146:f64d43ff0c18 | 6206 | /*! |
mbed_official | 146:f64d43ff0c18 | 6207 | * @name Register AIPS_PACRG, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 6208 | * |
mbed_official | 146:f64d43ff0c18 | 6209 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6210 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6211 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6212 | * |
mbed_official | 146:f64d43ff0c18 | 6213 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6214 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6215 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6216 | */ |
mbed_official | 146:f64d43ff0c18 | 6217 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6218 | #define BP_AIPS_PACRG_TP2 (20U) //!< Bit position for AIPS_PACRG_TP2. |
mbed_official | 146:f64d43ff0c18 | 6219 | #define BM_AIPS_PACRG_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRG_TP2. |
mbed_official | 146:f64d43ff0c18 | 6220 | #define BS_AIPS_PACRG_TP2 (1U) //!< Bit field size in bits for AIPS_PACRG_TP2. |
mbed_official | 146:f64d43ff0c18 | 6221 | |
mbed_official | 146:f64d43ff0c18 | 6222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6223 | //! @brief Read current value of the AIPS_PACRG_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 6224 | #define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2)) |
mbed_official | 146:f64d43ff0c18 | 6225 | #endif |
mbed_official | 146:f64d43ff0c18 | 6226 | |
mbed_official | 146:f64d43ff0c18 | 6227 | //! @brief Format value for bitfield AIPS_PACRG_TP2. |
mbed_official | 146:f64d43ff0c18 | 6228 | #define BF_AIPS_PACRG_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP2), uint32_t) & BM_AIPS_PACRG_TP2) |
mbed_official | 146:f64d43ff0c18 | 6229 | |
mbed_official | 146:f64d43ff0c18 | 6230 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6231 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6232 | #define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6233 | #endif |
mbed_official | 146:f64d43ff0c18 | 6234 | //@} |
mbed_official | 146:f64d43ff0c18 | 6235 | |
mbed_official | 146:f64d43ff0c18 | 6236 | /*! |
mbed_official | 146:f64d43ff0c18 | 6237 | * @name Register AIPS_PACRG, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 6238 | * |
mbed_official | 146:f64d43ff0c18 | 6239 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6240 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6241 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6242 | * |
mbed_official | 146:f64d43ff0c18 | 6243 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6244 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6245 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6246 | */ |
mbed_official | 146:f64d43ff0c18 | 6247 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6248 | #define BP_AIPS_PACRG_WP2 (21U) //!< Bit position for AIPS_PACRG_WP2. |
mbed_official | 146:f64d43ff0c18 | 6249 | #define BM_AIPS_PACRG_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRG_WP2. |
mbed_official | 146:f64d43ff0c18 | 6250 | #define BS_AIPS_PACRG_WP2 (1U) //!< Bit field size in bits for AIPS_PACRG_WP2. |
mbed_official | 146:f64d43ff0c18 | 6251 | |
mbed_official | 146:f64d43ff0c18 | 6252 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6253 | //! @brief Read current value of the AIPS_PACRG_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 6254 | #define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2)) |
mbed_official | 146:f64d43ff0c18 | 6255 | #endif |
mbed_official | 146:f64d43ff0c18 | 6256 | |
mbed_official | 146:f64d43ff0c18 | 6257 | //! @brief Format value for bitfield AIPS_PACRG_WP2. |
mbed_official | 146:f64d43ff0c18 | 6258 | #define BF_AIPS_PACRG_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP2), uint32_t) & BM_AIPS_PACRG_WP2) |
mbed_official | 146:f64d43ff0c18 | 6259 | |
mbed_official | 146:f64d43ff0c18 | 6260 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6261 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6262 | #define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6263 | #endif |
mbed_official | 146:f64d43ff0c18 | 6264 | //@} |
mbed_official | 146:f64d43ff0c18 | 6265 | |
mbed_official | 146:f64d43ff0c18 | 6266 | /*! |
mbed_official | 146:f64d43ff0c18 | 6267 | * @name Register AIPS_PACRG, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 6268 | * |
mbed_official | 146:f64d43ff0c18 | 6269 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6270 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6271 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 6272 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 6273 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 6274 | * |
mbed_official | 146:f64d43ff0c18 | 6275 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6276 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6277 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6278 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6279 | */ |
mbed_official | 146:f64d43ff0c18 | 6280 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6281 | #define BP_AIPS_PACRG_SP2 (22U) //!< Bit position for AIPS_PACRG_SP2. |
mbed_official | 146:f64d43ff0c18 | 6282 | #define BM_AIPS_PACRG_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRG_SP2. |
mbed_official | 146:f64d43ff0c18 | 6283 | #define BS_AIPS_PACRG_SP2 (1U) //!< Bit field size in bits for AIPS_PACRG_SP2. |
mbed_official | 146:f64d43ff0c18 | 6284 | |
mbed_official | 146:f64d43ff0c18 | 6285 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6286 | //! @brief Read current value of the AIPS_PACRG_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 6287 | #define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2)) |
mbed_official | 146:f64d43ff0c18 | 6288 | #endif |
mbed_official | 146:f64d43ff0c18 | 6289 | |
mbed_official | 146:f64d43ff0c18 | 6290 | //! @brief Format value for bitfield AIPS_PACRG_SP2. |
mbed_official | 146:f64d43ff0c18 | 6291 | #define BF_AIPS_PACRG_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP2), uint32_t) & BM_AIPS_PACRG_SP2) |
mbed_official | 146:f64d43ff0c18 | 6292 | |
mbed_official | 146:f64d43ff0c18 | 6293 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6294 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6295 | #define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6296 | #endif |
mbed_official | 146:f64d43ff0c18 | 6297 | //@} |
mbed_official | 146:f64d43ff0c18 | 6298 | |
mbed_official | 146:f64d43ff0c18 | 6299 | /*! |
mbed_official | 146:f64d43ff0c18 | 6300 | * @name Register AIPS_PACRG, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 6301 | * |
mbed_official | 146:f64d43ff0c18 | 6302 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6303 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6304 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6305 | * |
mbed_official | 146:f64d43ff0c18 | 6306 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6307 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6308 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6309 | */ |
mbed_official | 146:f64d43ff0c18 | 6310 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6311 | #define BP_AIPS_PACRG_TP1 (24U) //!< Bit position for AIPS_PACRG_TP1. |
mbed_official | 146:f64d43ff0c18 | 6312 | #define BM_AIPS_PACRG_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRG_TP1. |
mbed_official | 146:f64d43ff0c18 | 6313 | #define BS_AIPS_PACRG_TP1 (1U) //!< Bit field size in bits for AIPS_PACRG_TP1. |
mbed_official | 146:f64d43ff0c18 | 6314 | |
mbed_official | 146:f64d43ff0c18 | 6315 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6316 | //! @brief Read current value of the AIPS_PACRG_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 6317 | #define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1)) |
mbed_official | 146:f64d43ff0c18 | 6318 | #endif |
mbed_official | 146:f64d43ff0c18 | 6319 | |
mbed_official | 146:f64d43ff0c18 | 6320 | //! @brief Format value for bitfield AIPS_PACRG_TP1. |
mbed_official | 146:f64d43ff0c18 | 6321 | #define BF_AIPS_PACRG_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP1), uint32_t) & BM_AIPS_PACRG_TP1) |
mbed_official | 146:f64d43ff0c18 | 6322 | |
mbed_official | 146:f64d43ff0c18 | 6323 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6324 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6325 | #define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6326 | #endif |
mbed_official | 146:f64d43ff0c18 | 6327 | //@} |
mbed_official | 146:f64d43ff0c18 | 6328 | |
mbed_official | 146:f64d43ff0c18 | 6329 | /*! |
mbed_official | 146:f64d43ff0c18 | 6330 | * @name Register AIPS_PACRG, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 6331 | * |
mbed_official | 146:f64d43ff0c18 | 6332 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6333 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6334 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6335 | * |
mbed_official | 146:f64d43ff0c18 | 6336 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6337 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6338 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6339 | */ |
mbed_official | 146:f64d43ff0c18 | 6340 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6341 | #define BP_AIPS_PACRG_WP1 (25U) //!< Bit position for AIPS_PACRG_WP1. |
mbed_official | 146:f64d43ff0c18 | 6342 | #define BM_AIPS_PACRG_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRG_WP1. |
mbed_official | 146:f64d43ff0c18 | 6343 | #define BS_AIPS_PACRG_WP1 (1U) //!< Bit field size in bits for AIPS_PACRG_WP1. |
mbed_official | 146:f64d43ff0c18 | 6344 | |
mbed_official | 146:f64d43ff0c18 | 6345 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6346 | //! @brief Read current value of the AIPS_PACRG_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 6347 | #define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1)) |
mbed_official | 146:f64d43ff0c18 | 6348 | #endif |
mbed_official | 146:f64d43ff0c18 | 6349 | |
mbed_official | 146:f64d43ff0c18 | 6350 | //! @brief Format value for bitfield AIPS_PACRG_WP1. |
mbed_official | 146:f64d43ff0c18 | 6351 | #define BF_AIPS_PACRG_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP1), uint32_t) & BM_AIPS_PACRG_WP1) |
mbed_official | 146:f64d43ff0c18 | 6352 | |
mbed_official | 146:f64d43ff0c18 | 6353 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6354 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6355 | #define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6356 | #endif |
mbed_official | 146:f64d43ff0c18 | 6357 | //@} |
mbed_official | 146:f64d43ff0c18 | 6358 | |
mbed_official | 146:f64d43ff0c18 | 6359 | /*! |
mbed_official | 146:f64d43ff0c18 | 6360 | * @name Register AIPS_PACRG, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 6361 | * |
mbed_official | 146:f64d43ff0c18 | 6362 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6363 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6364 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 6365 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6366 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 6367 | * |
mbed_official | 146:f64d43ff0c18 | 6368 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6369 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6370 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6371 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6372 | */ |
mbed_official | 146:f64d43ff0c18 | 6373 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6374 | #define BP_AIPS_PACRG_SP1 (26U) //!< Bit position for AIPS_PACRG_SP1. |
mbed_official | 146:f64d43ff0c18 | 6375 | #define BM_AIPS_PACRG_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRG_SP1. |
mbed_official | 146:f64d43ff0c18 | 6376 | #define BS_AIPS_PACRG_SP1 (1U) //!< Bit field size in bits for AIPS_PACRG_SP1. |
mbed_official | 146:f64d43ff0c18 | 6377 | |
mbed_official | 146:f64d43ff0c18 | 6378 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6379 | //! @brief Read current value of the AIPS_PACRG_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 6380 | #define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1)) |
mbed_official | 146:f64d43ff0c18 | 6381 | #endif |
mbed_official | 146:f64d43ff0c18 | 6382 | |
mbed_official | 146:f64d43ff0c18 | 6383 | //! @brief Format value for bitfield AIPS_PACRG_SP1. |
mbed_official | 146:f64d43ff0c18 | 6384 | #define BF_AIPS_PACRG_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP1), uint32_t) & BM_AIPS_PACRG_SP1) |
mbed_official | 146:f64d43ff0c18 | 6385 | |
mbed_official | 146:f64d43ff0c18 | 6386 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6387 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6388 | #define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6389 | #endif |
mbed_official | 146:f64d43ff0c18 | 6390 | //@} |
mbed_official | 146:f64d43ff0c18 | 6391 | |
mbed_official | 146:f64d43ff0c18 | 6392 | /*! |
mbed_official | 146:f64d43ff0c18 | 6393 | * @name Register AIPS_PACRG, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 6394 | * |
mbed_official | 146:f64d43ff0c18 | 6395 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6396 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6397 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6398 | * |
mbed_official | 146:f64d43ff0c18 | 6399 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6400 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6401 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6402 | */ |
mbed_official | 146:f64d43ff0c18 | 6403 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6404 | #define BP_AIPS_PACRG_TP0 (28U) //!< Bit position for AIPS_PACRG_TP0. |
mbed_official | 146:f64d43ff0c18 | 6405 | #define BM_AIPS_PACRG_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRG_TP0. |
mbed_official | 146:f64d43ff0c18 | 6406 | #define BS_AIPS_PACRG_TP0 (1U) //!< Bit field size in bits for AIPS_PACRG_TP0. |
mbed_official | 146:f64d43ff0c18 | 6407 | |
mbed_official | 146:f64d43ff0c18 | 6408 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6409 | //! @brief Read current value of the AIPS_PACRG_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 6410 | #define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0)) |
mbed_official | 146:f64d43ff0c18 | 6411 | #endif |
mbed_official | 146:f64d43ff0c18 | 6412 | |
mbed_official | 146:f64d43ff0c18 | 6413 | //! @brief Format value for bitfield AIPS_PACRG_TP0. |
mbed_official | 146:f64d43ff0c18 | 6414 | #define BF_AIPS_PACRG_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP0), uint32_t) & BM_AIPS_PACRG_TP0) |
mbed_official | 146:f64d43ff0c18 | 6415 | |
mbed_official | 146:f64d43ff0c18 | 6416 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6417 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6418 | #define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6419 | #endif |
mbed_official | 146:f64d43ff0c18 | 6420 | //@} |
mbed_official | 146:f64d43ff0c18 | 6421 | |
mbed_official | 146:f64d43ff0c18 | 6422 | /*! |
mbed_official | 146:f64d43ff0c18 | 6423 | * @name Register AIPS_PACRG, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 6424 | * |
mbed_official | 146:f64d43ff0c18 | 6425 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6426 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6427 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6428 | * |
mbed_official | 146:f64d43ff0c18 | 6429 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6430 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6431 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6432 | */ |
mbed_official | 146:f64d43ff0c18 | 6433 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6434 | #define BP_AIPS_PACRG_WP0 (29U) //!< Bit position for AIPS_PACRG_WP0. |
mbed_official | 146:f64d43ff0c18 | 6435 | #define BM_AIPS_PACRG_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRG_WP0. |
mbed_official | 146:f64d43ff0c18 | 6436 | #define BS_AIPS_PACRG_WP0 (1U) //!< Bit field size in bits for AIPS_PACRG_WP0. |
mbed_official | 146:f64d43ff0c18 | 6437 | |
mbed_official | 146:f64d43ff0c18 | 6438 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6439 | //! @brief Read current value of the AIPS_PACRG_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 6440 | #define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0)) |
mbed_official | 146:f64d43ff0c18 | 6441 | #endif |
mbed_official | 146:f64d43ff0c18 | 6442 | |
mbed_official | 146:f64d43ff0c18 | 6443 | //! @brief Format value for bitfield AIPS_PACRG_WP0. |
mbed_official | 146:f64d43ff0c18 | 6444 | #define BF_AIPS_PACRG_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP0), uint32_t) & BM_AIPS_PACRG_WP0) |
mbed_official | 146:f64d43ff0c18 | 6445 | |
mbed_official | 146:f64d43ff0c18 | 6446 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6447 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6448 | #define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6449 | #endif |
mbed_official | 146:f64d43ff0c18 | 6450 | //@} |
mbed_official | 146:f64d43ff0c18 | 6451 | |
mbed_official | 146:f64d43ff0c18 | 6452 | /*! |
mbed_official | 146:f64d43ff0c18 | 6453 | * @name Register AIPS_PACRG, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 6454 | * |
mbed_official | 146:f64d43ff0c18 | 6455 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6456 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6457 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 6458 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6459 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 6460 | * |
mbed_official | 146:f64d43ff0c18 | 6461 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6462 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6463 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6464 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6465 | */ |
mbed_official | 146:f64d43ff0c18 | 6466 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6467 | #define BP_AIPS_PACRG_SP0 (30U) //!< Bit position for AIPS_PACRG_SP0. |
mbed_official | 146:f64d43ff0c18 | 6468 | #define BM_AIPS_PACRG_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRG_SP0. |
mbed_official | 146:f64d43ff0c18 | 6469 | #define BS_AIPS_PACRG_SP0 (1U) //!< Bit field size in bits for AIPS_PACRG_SP0. |
mbed_official | 146:f64d43ff0c18 | 6470 | |
mbed_official | 146:f64d43ff0c18 | 6471 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6472 | //! @brief Read current value of the AIPS_PACRG_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 6473 | #define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0)) |
mbed_official | 146:f64d43ff0c18 | 6474 | #endif |
mbed_official | 146:f64d43ff0c18 | 6475 | |
mbed_official | 146:f64d43ff0c18 | 6476 | //! @brief Format value for bitfield AIPS_PACRG_SP0. |
mbed_official | 146:f64d43ff0c18 | 6477 | #define BF_AIPS_PACRG_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP0), uint32_t) & BM_AIPS_PACRG_SP0) |
mbed_official | 146:f64d43ff0c18 | 6478 | |
mbed_official | 146:f64d43ff0c18 | 6479 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6480 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6481 | #define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6482 | #endif |
mbed_official | 146:f64d43ff0c18 | 6483 | //@} |
mbed_official | 146:f64d43ff0c18 | 6484 | |
mbed_official | 146:f64d43ff0c18 | 6485 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 6486 | // HW_AIPS_PACRH - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 6487 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 6488 | |
mbed_official | 146:f64d43ff0c18 | 6489 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6490 | /*! |
mbed_official | 146:f64d43ff0c18 | 6491 | * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 6492 | * |
mbed_official | 146:f64d43ff0c18 | 6493 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 6494 | * |
mbed_official | 146:f64d43ff0c18 | 6495 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 6496 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 6497 | * registers. |
mbed_official | 146:f64d43ff0c18 | 6498 | */ |
mbed_official | 146:f64d43ff0c18 | 6499 | typedef union _hw_aips_pacrh |
mbed_official | 146:f64d43ff0c18 | 6500 | { |
mbed_official | 146:f64d43ff0c18 | 6501 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 6502 | struct _hw_aips_pacrh_bitfields |
mbed_official | 146:f64d43ff0c18 | 6503 | { |
mbed_official | 146:f64d43ff0c18 | 6504 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6505 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6506 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6507 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 6508 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6509 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6510 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6511 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 6512 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6513 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6514 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6515 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 6516 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6517 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6518 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6519 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 6520 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6521 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6522 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6523 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 6524 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6525 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6526 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6527 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 6528 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6529 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6530 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6531 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 6532 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 6533 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 6534 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 6535 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 6536 | } B; |
mbed_official | 146:f64d43ff0c18 | 6537 | } hw_aips_pacrh_t; |
mbed_official | 146:f64d43ff0c18 | 6538 | #endif |
mbed_official | 146:f64d43ff0c18 | 6539 | |
mbed_official | 146:f64d43ff0c18 | 6540 | /*! |
mbed_official | 146:f64d43ff0c18 | 6541 | * @name Constants and macros for entire AIPS_PACRH register |
mbed_official | 146:f64d43ff0c18 | 6542 | */ |
mbed_official | 146:f64d43ff0c18 | 6543 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6544 | #define HW_AIPS_PACRH_ADDR(x) (REGS_AIPS_BASE(x) + 0x4CU) |
mbed_official | 146:f64d43ff0c18 | 6545 | |
mbed_official | 146:f64d43ff0c18 | 6546 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6547 | #define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 6548 | #define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U) |
mbed_official | 146:f64d43ff0c18 | 6549 | #define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 6550 | #define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 6551 | #define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 6552 | #define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 6553 | #endif |
mbed_official | 146:f64d43ff0c18 | 6554 | //@} |
mbed_official | 146:f64d43ff0c18 | 6555 | |
mbed_official | 146:f64d43ff0c18 | 6556 | /* |
mbed_official | 146:f64d43ff0c18 | 6557 | * Constants & macros for individual AIPS_PACRH bitfields |
mbed_official | 146:f64d43ff0c18 | 6558 | */ |
mbed_official | 146:f64d43ff0c18 | 6559 | |
mbed_official | 146:f64d43ff0c18 | 6560 | /*! |
mbed_official | 146:f64d43ff0c18 | 6561 | * @name Register AIPS_PACRH, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 6562 | * |
mbed_official | 146:f64d43ff0c18 | 6563 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6564 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6565 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6566 | * |
mbed_official | 146:f64d43ff0c18 | 6567 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6568 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6569 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6570 | */ |
mbed_official | 146:f64d43ff0c18 | 6571 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6572 | #define BP_AIPS_PACRH_TP7 (0U) //!< Bit position for AIPS_PACRH_TP7. |
mbed_official | 146:f64d43ff0c18 | 6573 | #define BM_AIPS_PACRH_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRH_TP7. |
mbed_official | 146:f64d43ff0c18 | 6574 | #define BS_AIPS_PACRH_TP7 (1U) //!< Bit field size in bits for AIPS_PACRH_TP7. |
mbed_official | 146:f64d43ff0c18 | 6575 | |
mbed_official | 146:f64d43ff0c18 | 6576 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6577 | //! @brief Read current value of the AIPS_PACRH_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 6578 | #define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7)) |
mbed_official | 146:f64d43ff0c18 | 6579 | #endif |
mbed_official | 146:f64d43ff0c18 | 6580 | |
mbed_official | 146:f64d43ff0c18 | 6581 | //! @brief Format value for bitfield AIPS_PACRH_TP7. |
mbed_official | 146:f64d43ff0c18 | 6582 | #define BF_AIPS_PACRH_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP7), uint32_t) & BM_AIPS_PACRH_TP7) |
mbed_official | 146:f64d43ff0c18 | 6583 | |
mbed_official | 146:f64d43ff0c18 | 6584 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6585 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6586 | #define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6587 | #endif |
mbed_official | 146:f64d43ff0c18 | 6588 | //@} |
mbed_official | 146:f64d43ff0c18 | 6589 | |
mbed_official | 146:f64d43ff0c18 | 6590 | /*! |
mbed_official | 146:f64d43ff0c18 | 6591 | * @name Register AIPS_PACRH, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 6592 | * |
mbed_official | 146:f64d43ff0c18 | 6593 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6594 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6595 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6596 | * |
mbed_official | 146:f64d43ff0c18 | 6597 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6598 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6599 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6600 | */ |
mbed_official | 146:f64d43ff0c18 | 6601 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6602 | #define BP_AIPS_PACRH_WP7 (1U) //!< Bit position for AIPS_PACRH_WP7. |
mbed_official | 146:f64d43ff0c18 | 6603 | #define BM_AIPS_PACRH_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRH_WP7. |
mbed_official | 146:f64d43ff0c18 | 6604 | #define BS_AIPS_PACRH_WP7 (1U) //!< Bit field size in bits for AIPS_PACRH_WP7. |
mbed_official | 146:f64d43ff0c18 | 6605 | |
mbed_official | 146:f64d43ff0c18 | 6606 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6607 | //! @brief Read current value of the AIPS_PACRH_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 6608 | #define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7)) |
mbed_official | 146:f64d43ff0c18 | 6609 | #endif |
mbed_official | 146:f64d43ff0c18 | 6610 | |
mbed_official | 146:f64d43ff0c18 | 6611 | //! @brief Format value for bitfield AIPS_PACRH_WP7. |
mbed_official | 146:f64d43ff0c18 | 6612 | #define BF_AIPS_PACRH_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP7), uint32_t) & BM_AIPS_PACRH_WP7) |
mbed_official | 146:f64d43ff0c18 | 6613 | |
mbed_official | 146:f64d43ff0c18 | 6614 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6615 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6616 | #define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6617 | #endif |
mbed_official | 146:f64d43ff0c18 | 6618 | //@} |
mbed_official | 146:f64d43ff0c18 | 6619 | |
mbed_official | 146:f64d43ff0c18 | 6620 | /*! |
mbed_official | 146:f64d43ff0c18 | 6621 | * @name Register AIPS_PACRH, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 6622 | * |
mbed_official | 146:f64d43ff0c18 | 6623 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6624 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6625 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 6626 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6627 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 6628 | * |
mbed_official | 146:f64d43ff0c18 | 6629 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6630 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6631 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6632 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6633 | */ |
mbed_official | 146:f64d43ff0c18 | 6634 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6635 | #define BP_AIPS_PACRH_SP7 (2U) //!< Bit position for AIPS_PACRH_SP7. |
mbed_official | 146:f64d43ff0c18 | 6636 | #define BM_AIPS_PACRH_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRH_SP7. |
mbed_official | 146:f64d43ff0c18 | 6637 | #define BS_AIPS_PACRH_SP7 (1U) //!< Bit field size in bits for AIPS_PACRH_SP7. |
mbed_official | 146:f64d43ff0c18 | 6638 | |
mbed_official | 146:f64d43ff0c18 | 6639 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6640 | //! @brief Read current value of the AIPS_PACRH_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 6641 | #define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7)) |
mbed_official | 146:f64d43ff0c18 | 6642 | #endif |
mbed_official | 146:f64d43ff0c18 | 6643 | |
mbed_official | 146:f64d43ff0c18 | 6644 | //! @brief Format value for bitfield AIPS_PACRH_SP7. |
mbed_official | 146:f64d43ff0c18 | 6645 | #define BF_AIPS_PACRH_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP7), uint32_t) & BM_AIPS_PACRH_SP7) |
mbed_official | 146:f64d43ff0c18 | 6646 | |
mbed_official | 146:f64d43ff0c18 | 6647 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6648 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6649 | #define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6650 | #endif |
mbed_official | 146:f64d43ff0c18 | 6651 | //@} |
mbed_official | 146:f64d43ff0c18 | 6652 | |
mbed_official | 146:f64d43ff0c18 | 6653 | /*! |
mbed_official | 146:f64d43ff0c18 | 6654 | * @name Register AIPS_PACRH, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 6655 | * |
mbed_official | 146:f64d43ff0c18 | 6656 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6657 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6658 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6659 | * |
mbed_official | 146:f64d43ff0c18 | 6660 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6661 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6662 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6663 | */ |
mbed_official | 146:f64d43ff0c18 | 6664 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6665 | #define BP_AIPS_PACRH_TP6 (4U) //!< Bit position for AIPS_PACRH_TP6. |
mbed_official | 146:f64d43ff0c18 | 6666 | #define BM_AIPS_PACRH_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRH_TP6. |
mbed_official | 146:f64d43ff0c18 | 6667 | #define BS_AIPS_PACRH_TP6 (1U) //!< Bit field size in bits for AIPS_PACRH_TP6. |
mbed_official | 146:f64d43ff0c18 | 6668 | |
mbed_official | 146:f64d43ff0c18 | 6669 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6670 | //! @brief Read current value of the AIPS_PACRH_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 6671 | #define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6)) |
mbed_official | 146:f64d43ff0c18 | 6672 | #endif |
mbed_official | 146:f64d43ff0c18 | 6673 | |
mbed_official | 146:f64d43ff0c18 | 6674 | //! @brief Format value for bitfield AIPS_PACRH_TP6. |
mbed_official | 146:f64d43ff0c18 | 6675 | #define BF_AIPS_PACRH_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP6), uint32_t) & BM_AIPS_PACRH_TP6) |
mbed_official | 146:f64d43ff0c18 | 6676 | |
mbed_official | 146:f64d43ff0c18 | 6677 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6678 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6679 | #define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6680 | #endif |
mbed_official | 146:f64d43ff0c18 | 6681 | //@} |
mbed_official | 146:f64d43ff0c18 | 6682 | |
mbed_official | 146:f64d43ff0c18 | 6683 | /*! |
mbed_official | 146:f64d43ff0c18 | 6684 | * @name Register AIPS_PACRH, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 6685 | * |
mbed_official | 146:f64d43ff0c18 | 6686 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6687 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6688 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6689 | * |
mbed_official | 146:f64d43ff0c18 | 6690 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6691 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6692 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6693 | */ |
mbed_official | 146:f64d43ff0c18 | 6694 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6695 | #define BP_AIPS_PACRH_WP6 (5U) //!< Bit position for AIPS_PACRH_WP6. |
mbed_official | 146:f64d43ff0c18 | 6696 | #define BM_AIPS_PACRH_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRH_WP6. |
mbed_official | 146:f64d43ff0c18 | 6697 | #define BS_AIPS_PACRH_WP6 (1U) //!< Bit field size in bits for AIPS_PACRH_WP6. |
mbed_official | 146:f64d43ff0c18 | 6698 | |
mbed_official | 146:f64d43ff0c18 | 6699 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6700 | //! @brief Read current value of the AIPS_PACRH_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 6701 | #define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6)) |
mbed_official | 146:f64d43ff0c18 | 6702 | #endif |
mbed_official | 146:f64d43ff0c18 | 6703 | |
mbed_official | 146:f64d43ff0c18 | 6704 | //! @brief Format value for bitfield AIPS_PACRH_WP6. |
mbed_official | 146:f64d43ff0c18 | 6705 | #define BF_AIPS_PACRH_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP6), uint32_t) & BM_AIPS_PACRH_WP6) |
mbed_official | 146:f64d43ff0c18 | 6706 | |
mbed_official | 146:f64d43ff0c18 | 6707 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6708 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6709 | #define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6710 | #endif |
mbed_official | 146:f64d43ff0c18 | 6711 | //@} |
mbed_official | 146:f64d43ff0c18 | 6712 | |
mbed_official | 146:f64d43ff0c18 | 6713 | /*! |
mbed_official | 146:f64d43ff0c18 | 6714 | * @name Register AIPS_PACRH, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 6715 | * |
mbed_official | 146:f64d43ff0c18 | 6716 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6717 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6718 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 6719 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6720 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 6721 | * |
mbed_official | 146:f64d43ff0c18 | 6722 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6723 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6724 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6725 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6726 | */ |
mbed_official | 146:f64d43ff0c18 | 6727 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6728 | #define BP_AIPS_PACRH_SP6 (6U) //!< Bit position for AIPS_PACRH_SP6. |
mbed_official | 146:f64d43ff0c18 | 6729 | #define BM_AIPS_PACRH_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRH_SP6. |
mbed_official | 146:f64d43ff0c18 | 6730 | #define BS_AIPS_PACRH_SP6 (1U) //!< Bit field size in bits for AIPS_PACRH_SP6. |
mbed_official | 146:f64d43ff0c18 | 6731 | |
mbed_official | 146:f64d43ff0c18 | 6732 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6733 | //! @brief Read current value of the AIPS_PACRH_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 6734 | #define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6)) |
mbed_official | 146:f64d43ff0c18 | 6735 | #endif |
mbed_official | 146:f64d43ff0c18 | 6736 | |
mbed_official | 146:f64d43ff0c18 | 6737 | //! @brief Format value for bitfield AIPS_PACRH_SP6. |
mbed_official | 146:f64d43ff0c18 | 6738 | #define BF_AIPS_PACRH_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP6), uint32_t) & BM_AIPS_PACRH_SP6) |
mbed_official | 146:f64d43ff0c18 | 6739 | |
mbed_official | 146:f64d43ff0c18 | 6740 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6741 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6742 | #define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6743 | #endif |
mbed_official | 146:f64d43ff0c18 | 6744 | //@} |
mbed_official | 146:f64d43ff0c18 | 6745 | |
mbed_official | 146:f64d43ff0c18 | 6746 | /*! |
mbed_official | 146:f64d43ff0c18 | 6747 | * @name Register AIPS_PACRH, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 6748 | * |
mbed_official | 146:f64d43ff0c18 | 6749 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6750 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6751 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6752 | * |
mbed_official | 146:f64d43ff0c18 | 6753 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6754 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6755 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6756 | */ |
mbed_official | 146:f64d43ff0c18 | 6757 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6758 | #define BP_AIPS_PACRH_TP5 (8U) //!< Bit position for AIPS_PACRH_TP5. |
mbed_official | 146:f64d43ff0c18 | 6759 | #define BM_AIPS_PACRH_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRH_TP5. |
mbed_official | 146:f64d43ff0c18 | 6760 | #define BS_AIPS_PACRH_TP5 (1U) //!< Bit field size in bits for AIPS_PACRH_TP5. |
mbed_official | 146:f64d43ff0c18 | 6761 | |
mbed_official | 146:f64d43ff0c18 | 6762 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6763 | //! @brief Read current value of the AIPS_PACRH_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 6764 | #define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5)) |
mbed_official | 146:f64d43ff0c18 | 6765 | #endif |
mbed_official | 146:f64d43ff0c18 | 6766 | |
mbed_official | 146:f64d43ff0c18 | 6767 | //! @brief Format value for bitfield AIPS_PACRH_TP5. |
mbed_official | 146:f64d43ff0c18 | 6768 | #define BF_AIPS_PACRH_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP5), uint32_t) & BM_AIPS_PACRH_TP5) |
mbed_official | 146:f64d43ff0c18 | 6769 | |
mbed_official | 146:f64d43ff0c18 | 6770 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6771 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6772 | #define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6773 | #endif |
mbed_official | 146:f64d43ff0c18 | 6774 | //@} |
mbed_official | 146:f64d43ff0c18 | 6775 | |
mbed_official | 146:f64d43ff0c18 | 6776 | /*! |
mbed_official | 146:f64d43ff0c18 | 6777 | * @name Register AIPS_PACRH, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 6778 | * |
mbed_official | 146:f64d43ff0c18 | 6779 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6780 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6781 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6782 | * |
mbed_official | 146:f64d43ff0c18 | 6783 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6784 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6785 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6786 | */ |
mbed_official | 146:f64d43ff0c18 | 6787 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6788 | #define BP_AIPS_PACRH_WP5 (9U) //!< Bit position for AIPS_PACRH_WP5. |
mbed_official | 146:f64d43ff0c18 | 6789 | #define BM_AIPS_PACRH_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRH_WP5. |
mbed_official | 146:f64d43ff0c18 | 6790 | #define BS_AIPS_PACRH_WP5 (1U) //!< Bit field size in bits for AIPS_PACRH_WP5. |
mbed_official | 146:f64d43ff0c18 | 6791 | |
mbed_official | 146:f64d43ff0c18 | 6792 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6793 | //! @brief Read current value of the AIPS_PACRH_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 6794 | #define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5)) |
mbed_official | 146:f64d43ff0c18 | 6795 | #endif |
mbed_official | 146:f64d43ff0c18 | 6796 | |
mbed_official | 146:f64d43ff0c18 | 6797 | //! @brief Format value for bitfield AIPS_PACRH_WP5. |
mbed_official | 146:f64d43ff0c18 | 6798 | #define BF_AIPS_PACRH_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP5), uint32_t) & BM_AIPS_PACRH_WP5) |
mbed_official | 146:f64d43ff0c18 | 6799 | |
mbed_official | 146:f64d43ff0c18 | 6800 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6801 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6802 | #define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6803 | #endif |
mbed_official | 146:f64d43ff0c18 | 6804 | //@} |
mbed_official | 146:f64d43ff0c18 | 6805 | |
mbed_official | 146:f64d43ff0c18 | 6806 | /*! |
mbed_official | 146:f64d43ff0c18 | 6807 | * @name Register AIPS_PACRH, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 6808 | * |
mbed_official | 146:f64d43ff0c18 | 6809 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6810 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6811 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 6812 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6813 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 6814 | * |
mbed_official | 146:f64d43ff0c18 | 6815 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6816 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6817 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6818 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6819 | */ |
mbed_official | 146:f64d43ff0c18 | 6820 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6821 | #define BP_AIPS_PACRH_SP5 (10U) //!< Bit position for AIPS_PACRH_SP5. |
mbed_official | 146:f64d43ff0c18 | 6822 | #define BM_AIPS_PACRH_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRH_SP5. |
mbed_official | 146:f64d43ff0c18 | 6823 | #define BS_AIPS_PACRH_SP5 (1U) //!< Bit field size in bits for AIPS_PACRH_SP5. |
mbed_official | 146:f64d43ff0c18 | 6824 | |
mbed_official | 146:f64d43ff0c18 | 6825 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6826 | //! @brief Read current value of the AIPS_PACRH_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 6827 | #define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5)) |
mbed_official | 146:f64d43ff0c18 | 6828 | #endif |
mbed_official | 146:f64d43ff0c18 | 6829 | |
mbed_official | 146:f64d43ff0c18 | 6830 | //! @brief Format value for bitfield AIPS_PACRH_SP5. |
mbed_official | 146:f64d43ff0c18 | 6831 | #define BF_AIPS_PACRH_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP5), uint32_t) & BM_AIPS_PACRH_SP5) |
mbed_official | 146:f64d43ff0c18 | 6832 | |
mbed_official | 146:f64d43ff0c18 | 6833 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6834 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6835 | #define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6836 | #endif |
mbed_official | 146:f64d43ff0c18 | 6837 | //@} |
mbed_official | 146:f64d43ff0c18 | 6838 | |
mbed_official | 146:f64d43ff0c18 | 6839 | /*! |
mbed_official | 146:f64d43ff0c18 | 6840 | * @name Register AIPS_PACRH, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 6841 | * |
mbed_official | 146:f64d43ff0c18 | 6842 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6843 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6844 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6845 | * |
mbed_official | 146:f64d43ff0c18 | 6846 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6847 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6848 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6849 | */ |
mbed_official | 146:f64d43ff0c18 | 6850 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6851 | #define BP_AIPS_PACRH_TP4 (12U) //!< Bit position for AIPS_PACRH_TP4. |
mbed_official | 146:f64d43ff0c18 | 6852 | #define BM_AIPS_PACRH_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRH_TP4. |
mbed_official | 146:f64d43ff0c18 | 6853 | #define BS_AIPS_PACRH_TP4 (1U) //!< Bit field size in bits for AIPS_PACRH_TP4. |
mbed_official | 146:f64d43ff0c18 | 6854 | |
mbed_official | 146:f64d43ff0c18 | 6855 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6856 | //! @brief Read current value of the AIPS_PACRH_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 6857 | #define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4)) |
mbed_official | 146:f64d43ff0c18 | 6858 | #endif |
mbed_official | 146:f64d43ff0c18 | 6859 | |
mbed_official | 146:f64d43ff0c18 | 6860 | //! @brief Format value for bitfield AIPS_PACRH_TP4. |
mbed_official | 146:f64d43ff0c18 | 6861 | #define BF_AIPS_PACRH_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP4), uint32_t) & BM_AIPS_PACRH_TP4) |
mbed_official | 146:f64d43ff0c18 | 6862 | |
mbed_official | 146:f64d43ff0c18 | 6863 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6864 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6865 | #define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6866 | #endif |
mbed_official | 146:f64d43ff0c18 | 6867 | //@} |
mbed_official | 146:f64d43ff0c18 | 6868 | |
mbed_official | 146:f64d43ff0c18 | 6869 | /*! |
mbed_official | 146:f64d43ff0c18 | 6870 | * @name Register AIPS_PACRH, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 6871 | * |
mbed_official | 146:f64d43ff0c18 | 6872 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 6873 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 6874 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6875 | * |
mbed_official | 146:f64d43ff0c18 | 6876 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6877 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6878 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6879 | */ |
mbed_official | 146:f64d43ff0c18 | 6880 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6881 | #define BP_AIPS_PACRH_WP4 (13U) //!< Bit position for AIPS_PACRH_WP4. |
mbed_official | 146:f64d43ff0c18 | 6882 | #define BM_AIPS_PACRH_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRH_WP4. |
mbed_official | 146:f64d43ff0c18 | 6883 | #define BS_AIPS_PACRH_WP4 (1U) //!< Bit field size in bits for AIPS_PACRH_WP4. |
mbed_official | 146:f64d43ff0c18 | 6884 | |
mbed_official | 146:f64d43ff0c18 | 6885 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6886 | //! @brief Read current value of the AIPS_PACRH_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 6887 | #define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4)) |
mbed_official | 146:f64d43ff0c18 | 6888 | #endif |
mbed_official | 146:f64d43ff0c18 | 6889 | |
mbed_official | 146:f64d43ff0c18 | 6890 | //! @brief Format value for bitfield AIPS_PACRH_WP4. |
mbed_official | 146:f64d43ff0c18 | 6891 | #define BF_AIPS_PACRH_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP4), uint32_t) & BM_AIPS_PACRH_WP4) |
mbed_official | 146:f64d43ff0c18 | 6892 | |
mbed_official | 146:f64d43ff0c18 | 6893 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6894 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6895 | #define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6896 | #endif |
mbed_official | 146:f64d43ff0c18 | 6897 | //@} |
mbed_official | 146:f64d43ff0c18 | 6898 | |
mbed_official | 146:f64d43ff0c18 | 6899 | /*! |
mbed_official | 146:f64d43ff0c18 | 6900 | * @name Register AIPS_PACRH, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 6901 | * |
mbed_official | 146:f64d43ff0c18 | 6902 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6903 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6904 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 6905 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 6906 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 6907 | * |
mbed_official | 146:f64d43ff0c18 | 6908 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6909 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6910 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 6911 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 6912 | */ |
mbed_official | 146:f64d43ff0c18 | 6913 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6914 | #define BP_AIPS_PACRH_SP4 (14U) //!< Bit position for AIPS_PACRH_SP4. |
mbed_official | 146:f64d43ff0c18 | 6915 | #define BM_AIPS_PACRH_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRH_SP4. |
mbed_official | 146:f64d43ff0c18 | 6916 | #define BS_AIPS_PACRH_SP4 (1U) //!< Bit field size in bits for AIPS_PACRH_SP4. |
mbed_official | 146:f64d43ff0c18 | 6917 | |
mbed_official | 146:f64d43ff0c18 | 6918 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6919 | //! @brief Read current value of the AIPS_PACRH_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 6920 | #define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4)) |
mbed_official | 146:f64d43ff0c18 | 6921 | #endif |
mbed_official | 146:f64d43ff0c18 | 6922 | |
mbed_official | 146:f64d43ff0c18 | 6923 | //! @brief Format value for bitfield AIPS_PACRH_SP4. |
mbed_official | 146:f64d43ff0c18 | 6924 | #define BF_AIPS_PACRH_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP4), uint32_t) & BM_AIPS_PACRH_SP4) |
mbed_official | 146:f64d43ff0c18 | 6925 | |
mbed_official | 146:f64d43ff0c18 | 6926 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6927 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6928 | #define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6929 | #endif |
mbed_official | 146:f64d43ff0c18 | 6930 | //@} |
mbed_official | 146:f64d43ff0c18 | 6931 | |
mbed_official | 146:f64d43ff0c18 | 6932 | /*! |
mbed_official | 146:f64d43ff0c18 | 6933 | * @name Register AIPS_PACRH, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 6934 | * |
mbed_official | 146:f64d43ff0c18 | 6935 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 6936 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 6937 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6938 | * |
mbed_official | 146:f64d43ff0c18 | 6939 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6940 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 6941 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 6942 | */ |
mbed_official | 146:f64d43ff0c18 | 6943 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6944 | #define BP_AIPS_PACRH_TP3 (16U) //!< Bit position for AIPS_PACRH_TP3. |
mbed_official | 146:f64d43ff0c18 | 6945 | #define BM_AIPS_PACRH_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRH_TP3. |
mbed_official | 146:f64d43ff0c18 | 6946 | #define BS_AIPS_PACRH_TP3 (1U) //!< Bit field size in bits for AIPS_PACRH_TP3. |
mbed_official | 146:f64d43ff0c18 | 6947 | |
mbed_official | 146:f64d43ff0c18 | 6948 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6949 | //! @brief Read current value of the AIPS_PACRH_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 6950 | #define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3)) |
mbed_official | 146:f64d43ff0c18 | 6951 | #endif |
mbed_official | 146:f64d43ff0c18 | 6952 | |
mbed_official | 146:f64d43ff0c18 | 6953 | //! @brief Format value for bitfield AIPS_PACRH_TP3. |
mbed_official | 146:f64d43ff0c18 | 6954 | #define BF_AIPS_PACRH_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP3), uint32_t) & BM_AIPS_PACRH_TP3) |
mbed_official | 146:f64d43ff0c18 | 6955 | |
mbed_official | 146:f64d43ff0c18 | 6956 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6957 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6958 | #define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6959 | #endif |
mbed_official | 146:f64d43ff0c18 | 6960 | //@} |
mbed_official | 146:f64d43ff0c18 | 6961 | |
mbed_official | 146:f64d43ff0c18 | 6962 | /*! |
mbed_official | 146:f64d43ff0c18 | 6963 | * @name Register AIPS_PACRH, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 6964 | * |
mbed_official | 146:f64d43ff0c18 | 6965 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 6966 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 6967 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 6968 | * |
mbed_official | 146:f64d43ff0c18 | 6969 | * Values: |
mbed_official | 146:f64d43ff0c18 | 6970 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 6971 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 6972 | */ |
mbed_official | 146:f64d43ff0c18 | 6973 | //@{ |
mbed_official | 146:f64d43ff0c18 | 6974 | #define BP_AIPS_PACRH_WP3 (17U) //!< Bit position for AIPS_PACRH_WP3. |
mbed_official | 146:f64d43ff0c18 | 6975 | #define BM_AIPS_PACRH_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRH_WP3. |
mbed_official | 146:f64d43ff0c18 | 6976 | #define BS_AIPS_PACRH_WP3 (1U) //!< Bit field size in bits for AIPS_PACRH_WP3. |
mbed_official | 146:f64d43ff0c18 | 6977 | |
mbed_official | 146:f64d43ff0c18 | 6978 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6979 | //! @brief Read current value of the AIPS_PACRH_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 6980 | #define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3)) |
mbed_official | 146:f64d43ff0c18 | 6981 | #endif |
mbed_official | 146:f64d43ff0c18 | 6982 | |
mbed_official | 146:f64d43ff0c18 | 6983 | //! @brief Format value for bitfield AIPS_PACRH_WP3. |
mbed_official | 146:f64d43ff0c18 | 6984 | #define BF_AIPS_PACRH_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP3), uint32_t) & BM_AIPS_PACRH_WP3) |
mbed_official | 146:f64d43ff0c18 | 6985 | |
mbed_official | 146:f64d43ff0c18 | 6986 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 6987 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 6988 | #define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 6989 | #endif |
mbed_official | 146:f64d43ff0c18 | 6990 | //@} |
mbed_official | 146:f64d43ff0c18 | 6991 | |
mbed_official | 146:f64d43ff0c18 | 6992 | /*! |
mbed_official | 146:f64d43ff0c18 | 6993 | * @name Register AIPS_PACRH, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 6994 | * |
mbed_official | 146:f64d43ff0c18 | 6995 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 6996 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 6997 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 6998 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 6999 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7000 | * |
mbed_official | 146:f64d43ff0c18 | 7001 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7002 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7003 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7004 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7005 | */ |
mbed_official | 146:f64d43ff0c18 | 7006 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7007 | #define BP_AIPS_PACRH_SP3 (18U) //!< Bit position for AIPS_PACRH_SP3. |
mbed_official | 146:f64d43ff0c18 | 7008 | #define BM_AIPS_PACRH_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRH_SP3. |
mbed_official | 146:f64d43ff0c18 | 7009 | #define BS_AIPS_PACRH_SP3 (1U) //!< Bit field size in bits for AIPS_PACRH_SP3. |
mbed_official | 146:f64d43ff0c18 | 7010 | |
mbed_official | 146:f64d43ff0c18 | 7011 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7012 | //! @brief Read current value of the AIPS_PACRH_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 7013 | #define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3)) |
mbed_official | 146:f64d43ff0c18 | 7014 | #endif |
mbed_official | 146:f64d43ff0c18 | 7015 | |
mbed_official | 146:f64d43ff0c18 | 7016 | //! @brief Format value for bitfield AIPS_PACRH_SP3. |
mbed_official | 146:f64d43ff0c18 | 7017 | #define BF_AIPS_PACRH_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP3), uint32_t) & BM_AIPS_PACRH_SP3) |
mbed_official | 146:f64d43ff0c18 | 7018 | |
mbed_official | 146:f64d43ff0c18 | 7019 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7020 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7021 | #define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7022 | #endif |
mbed_official | 146:f64d43ff0c18 | 7023 | //@} |
mbed_official | 146:f64d43ff0c18 | 7024 | |
mbed_official | 146:f64d43ff0c18 | 7025 | /*! |
mbed_official | 146:f64d43ff0c18 | 7026 | * @name Register AIPS_PACRH, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 7027 | * |
mbed_official | 146:f64d43ff0c18 | 7028 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7029 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7030 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7031 | * |
mbed_official | 146:f64d43ff0c18 | 7032 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7033 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7034 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7035 | */ |
mbed_official | 146:f64d43ff0c18 | 7036 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7037 | #define BP_AIPS_PACRH_TP2 (20U) //!< Bit position for AIPS_PACRH_TP2. |
mbed_official | 146:f64d43ff0c18 | 7038 | #define BM_AIPS_PACRH_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRH_TP2. |
mbed_official | 146:f64d43ff0c18 | 7039 | #define BS_AIPS_PACRH_TP2 (1U) //!< Bit field size in bits for AIPS_PACRH_TP2. |
mbed_official | 146:f64d43ff0c18 | 7040 | |
mbed_official | 146:f64d43ff0c18 | 7041 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7042 | //! @brief Read current value of the AIPS_PACRH_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 7043 | #define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2)) |
mbed_official | 146:f64d43ff0c18 | 7044 | #endif |
mbed_official | 146:f64d43ff0c18 | 7045 | |
mbed_official | 146:f64d43ff0c18 | 7046 | //! @brief Format value for bitfield AIPS_PACRH_TP2. |
mbed_official | 146:f64d43ff0c18 | 7047 | #define BF_AIPS_PACRH_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP2), uint32_t) & BM_AIPS_PACRH_TP2) |
mbed_official | 146:f64d43ff0c18 | 7048 | |
mbed_official | 146:f64d43ff0c18 | 7049 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7050 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7051 | #define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7052 | #endif |
mbed_official | 146:f64d43ff0c18 | 7053 | //@} |
mbed_official | 146:f64d43ff0c18 | 7054 | |
mbed_official | 146:f64d43ff0c18 | 7055 | /*! |
mbed_official | 146:f64d43ff0c18 | 7056 | * @name Register AIPS_PACRH, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 7057 | * |
mbed_official | 146:f64d43ff0c18 | 7058 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7059 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7060 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7061 | * |
mbed_official | 146:f64d43ff0c18 | 7062 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7063 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7064 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7065 | */ |
mbed_official | 146:f64d43ff0c18 | 7066 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7067 | #define BP_AIPS_PACRH_WP2 (21U) //!< Bit position for AIPS_PACRH_WP2. |
mbed_official | 146:f64d43ff0c18 | 7068 | #define BM_AIPS_PACRH_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRH_WP2. |
mbed_official | 146:f64d43ff0c18 | 7069 | #define BS_AIPS_PACRH_WP2 (1U) //!< Bit field size in bits for AIPS_PACRH_WP2. |
mbed_official | 146:f64d43ff0c18 | 7070 | |
mbed_official | 146:f64d43ff0c18 | 7071 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7072 | //! @brief Read current value of the AIPS_PACRH_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 7073 | #define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2)) |
mbed_official | 146:f64d43ff0c18 | 7074 | #endif |
mbed_official | 146:f64d43ff0c18 | 7075 | |
mbed_official | 146:f64d43ff0c18 | 7076 | //! @brief Format value for bitfield AIPS_PACRH_WP2. |
mbed_official | 146:f64d43ff0c18 | 7077 | #define BF_AIPS_PACRH_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP2), uint32_t) & BM_AIPS_PACRH_WP2) |
mbed_official | 146:f64d43ff0c18 | 7078 | |
mbed_official | 146:f64d43ff0c18 | 7079 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7080 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7081 | #define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7082 | #endif |
mbed_official | 146:f64d43ff0c18 | 7083 | //@} |
mbed_official | 146:f64d43ff0c18 | 7084 | |
mbed_official | 146:f64d43ff0c18 | 7085 | /*! |
mbed_official | 146:f64d43ff0c18 | 7086 | * @name Register AIPS_PACRH, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 7087 | * |
mbed_official | 146:f64d43ff0c18 | 7088 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7089 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7090 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 7091 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 7092 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 7093 | * |
mbed_official | 146:f64d43ff0c18 | 7094 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7095 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7096 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7097 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7098 | */ |
mbed_official | 146:f64d43ff0c18 | 7099 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7100 | #define BP_AIPS_PACRH_SP2 (22U) //!< Bit position for AIPS_PACRH_SP2. |
mbed_official | 146:f64d43ff0c18 | 7101 | #define BM_AIPS_PACRH_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRH_SP2. |
mbed_official | 146:f64d43ff0c18 | 7102 | #define BS_AIPS_PACRH_SP2 (1U) //!< Bit field size in bits for AIPS_PACRH_SP2. |
mbed_official | 146:f64d43ff0c18 | 7103 | |
mbed_official | 146:f64d43ff0c18 | 7104 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7105 | //! @brief Read current value of the AIPS_PACRH_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 7106 | #define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2)) |
mbed_official | 146:f64d43ff0c18 | 7107 | #endif |
mbed_official | 146:f64d43ff0c18 | 7108 | |
mbed_official | 146:f64d43ff0c18 | 7109 | //! @brief Format value for bitfield AIPS_PACRH_SP2. |
mbed_official | 146:f64d43ff0c18 | 7110 | #define BF_AIPS_PACRH_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP2), uint32_t) & BM_AIPS_PACRH_SP2) |
mbed_official | 146:f64d43ff0c18 | 7111 | |
mbed_official | 146:f64d43ff0c18 | 7112 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7113 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7114 | #define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7115 | #endif |
mbed_official | 146:f64d43ff0c18 | 7116 | //@} |
mbed_official | 146:f64d43ff0c18 | 7117 | |
mbed_official | 146:f64d43ff0c18 | 7118 | /*! |
mbed_official | 146:f64d43ff0c18 | 7119 | * @name Register AIPS_PACRH, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 7120 | * |
mbed_official | 146:f64d43ff0c18 | 7121 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7122 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7123 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7124 | * |
mbed_official | 146:f64d43ff0c18 | 7125 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7126 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7127 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7128 | */ |
mbed_official | 146:f64d43ff0c18 | 7129 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7130 | #define BP_AIPS_PACRH_TP1 (24U) //!< Bit position for AIPS_PACRH_TP1. |
mbed_official | 146:f64d43ff0c18 | 7131 | #define BM_AIPS_PACRH_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRH_TP1. |
mbed_official | 146:f64d43ff0c18 | 7132 | #define BS_AIPS_PACRH_TP1 (1U) //!< Bit field size in bits for AIPS_PACRH_TP1. |
mbed_official | 146:f64d43ff0c18 | 7133 | |
mbed_official | 146:f64d43ff0c18 | 7134 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7135 | //! @brief Read current value of the AIPS_PACRH_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 7136 | #define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1)) |
mbed_official | 146:f64d43ff0c18 | 7137 | #endif |
mbed_official | 146:f64d43ff0c18 | 7138 | |
mbed_official | 146:f64d43ff0c18 | 7139 | //! @brief Format value for bitfield AIPS_PACRH_TP1. |
mbed_official | 146:f64d43ff0c18 | 7140 | #define BF_AIPS_PACRH_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP1), uint32_t) & BM_AIPS_PACRH_TP1) |
mbed_official | 146:f64d43ff0c18 | 7141 | |
mbed_official | 146:f64d43ff0c18 | 7142 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7143 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7144 | #define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7145 | #endif |
mbed_official | 146:f64d43ff0c18 | 7146 | //@} |
mbed_official | 146:f64d43ff0c18 | 7147 | |
mbed_official | 146:f64d43ff0c18 | 7148 | /*! |
mbed_official | 146:f64d43ff0c18 | 7149 | * @name Register AIPS_PACRH, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 7150 | * |
mbed_official | 146:f64d43ff0c18 | 7151 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7152 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7153 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7154 | * |
mbed_official | 146:f64d43ff0c18 | 7155 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7156 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7157 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7158 | */ |
mbed_official | 146:f64d43ff0c18 | 7159 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7160 | #define BP_AIPS_PACRH_WP1 (25U) //!< Bit position for AIPS_PACRH_WP1. |
mbed_official | 146:f64d43ff0c18 | 7161 | #define BM_AIPS_PACRH_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRH_WP1. |
mbed_official | 146:f64d43ff0c18 | 7162 | #define BS_AIPS_PACRH_WP1 (1U) //!< Bit field size in bits for AIPS_PACRH_WP1. |
mbed_official | 146:f64d43ff0c18 | 7163 | |
mbed_official | 146:f64d43ff0c18 | 7164 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7165 | //! @brief Read current value of the AIPS_PACRH_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 7166 | #define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1)) |
mbed_official | 146:f64d43ff0c18 | 7167 | #endif |
mbed_official | 146:f64d43ff0c18 | 7168 | |
mbed_official | 146:f64d43ff0c18 | 7169 | //! @brief Format value for bitfield AIPS_PACRH_WP1. |
mbed_official | 146:f64d43ff0c18 | 7170 | #define BF_AIPS_PACRH_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP1), uint32_t) & BM_AIPS_PACRH_WP1) |
mbed_official | 146:f64d43ff0c18 | 7171 | |
mbed_official | 146:f64d43ff0c18 | 7172 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7173 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7174 | #define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7175 | #endif |
mbed_official | 146:f64d43ff0c18 | 7176 | //@} |
mbed_official | 146:f64d43ff0c18 | 7177 | |
mbed_official | 146:f64d43ff0c18 | 7178 | /*! |
mbed_official | 146:f64d43ff0c18 | 7179 | * @name Register AIPS_PACRH, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 7180 | * |
mbed_official | 146:f64d43ff0c18 | 7181 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7182 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7183 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 7184 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 7185 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7186 | * |
mbed_official | 146:f64d43ff0c18 | 7187 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7188 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7189 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7190 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7191 | */ |
mbed_official | 146:f64d43ff0c18 | 7192 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7193 | #define BP_AIPS_PACRH_SP1 (26U) //!< Bit position for AIPS_PACRH_SP1. |
mbed_official | 146:f64d43ff0c18 | 7194 | #define BM_AIPS_PACRH_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRH_SP1. |
mbed_official | 146:f64d43ff0c18 | 7195 | #define BS_AIPS_PACRH_SP1 (1U) //!< Bit field size in bits for AIPS_PACRH_SP1. |
mbed_official | 146:f64d43ff0c18 | 7196 | |
mbed_official | 146:f64d43ff0c18 | 7197 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7198 | //! @brief Read current value of the AIPS_PACRH_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 7199 | #define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1)) |
mbed_official | 146:f64d43ff0c18 | 7200 | #endif |
mbed_official | 146:f64d43ff0c18 | 7201 | |
mbed_official | 146:f64d43ff0c18 | 7202 | //! @brief Format value for bitfield AIPS_PACRH_SP1. |
mbed_official | 146:f64d43ff0c18 | 7203 | #define BF_AIPS_PACRH_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP1), uint32_t) & BM_AIPS_PACRH_SP1) |
mbed_official | 146:f64d43ff0c18 | 7204 | |
mbed_official | 146:f64d43ff0c18 | 7205 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7206 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7207 | #define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7208 | #endif |
mbed_official | 146:f64d43ff0c18 | 7209 | //@} |
mbed_official | 146:f64d43ff0c18 | 7210 | |
mbed_official | 146:f64d43ff0c18 | 7211 | /*! |
mbed_official | 146:f64d43ff0c18 | 7212 | * @name Register AIPS_PACRH, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 7213 | * |
mbed_official | 146:f64d43ff0c18 | 7214 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7215 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7216 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7217 | * |
mbed_official | 146:f64d43ff0c18 | 7218 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7219 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7220 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7221 | */ |
mbed_official | 146:f64d43ff0c18 | 7222 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7223 | #define BP_AIPS_PACRH_TP0 (28U) //!< Bit position for AIPS_PACRH_TP0. |
mbed_official | 146:f64d43ff0c18 | 7224 | #define BM_AIPS_PACRH_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRH_TP0. |
mbed_official | 146:f64d43ff0c18 | 7225 | #define BS_AIPS_PACRH_TP0 (1U) //!< Bit field size in bits for AIPS_PACRH_TP0. |
mbed_official | 146:f64d43ff0c18 | 7226 | |
mbed_official | 146:f64d43ff0c18 | 7227 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7228 | //! @brief Read current value of the AIPS_PACRH_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 7229 | #define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0)) |
mbed_official | 146:f64d43ff0c18 | 7230 | #endif |
mbed_official | 146:f64d43ff0c18 | 7231 | |
mbed_official | 146:f64d43ff0c18 | 7232 | //! @brief Format value for bitfield AIPS_PACRH_TP0. |
mbed_official | 146:f64d43ff0c18 | 7233 | #define BF_AIPS_PACRH_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP0), uint32_t) & BM_AIPS_PACRH_TP0) |
mbed_official | 146:f64d43ff0c18 | 7234 | |
mbed_official | 146:f64d43ff0c18 | 7235 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7236 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7237 | #define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7238 | #endif |
mbed_official | 146:f64d43ff0c18 | 7239 | //@} |
mbed_official | 146:f64d43ff0c18 | 7240 | |
mbed_official | 146:f64d43ff0c18 | 7241 | /*! |
mbed_official | 146:f64d43ff0c18 | 7242 | * @name Register AIPS_PACRH, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 7243 | * |
mbed_official | 146:f64d43ff0c18 | 7244 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7245 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7246 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7247 | * |
mbed_official | 146:f64d43ff0c18 | 7248 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7249 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7250 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7251 | */ |
mbed_official | 146:f64d43ff0c18 | 7252 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7253 | #define BP_AIPS_PACRH_WP0 (29U) //!< Bit position for AIPS_PACRH_WP0. |
mbed_official | 146:f64d43ff0c18 | 7254 | #define BM_AIPS_PACRH_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRH_WP0. |
mbed_official | 146:f64d43ff0c18 | 7255 | #define BS_AIPS_PACRH_WP0 (1U) //!< Bit field size in bits for AIPS_PACRH_WP0. |
mbed_official | 146:f64d43ff0c18 | 7256 | |
mbed_official | 146:f64d43ff0c18 | 7257 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7258 | //! @brief Read current value of the AIPS_PACRH_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 7259 | #define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0)) |
mbed_official | 146:f64d43ff0c18 | 7260 | #endif |
mbed_official | 146:f64d43ff0c18 | 7261 | |
mbed_official | 146:f64d43ff0c18 | 7262 | //! @brief Format value for bitfield AIPS_PACRH_WP0. |
mbed_official | 146:f64d43ff0c18 | 7263 | #define BF_AIPS_PACRH_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP0), uint32_t) & BM_AIPS_PACRH_WP0) |
mbed_official | 146:f64d43ff0c18 | 7264 | |
mbed_official | 146:f64d43ff0c18 | 7265 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7266 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7267 | #define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7268 | #endif |
mbed_official | 146:f64d43ff0c18 | 7269 | //@} |
mbed_official | 146:f64d43ff0c18 | 7270 | |
mbed_official | 146:f64d43ff0c18 | 7271 | /*! |
mbed_official | 146:f64d43ff0c18 | 7272 | * @name Register AIPS_PACRH, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 7273 | * |
mbed_official | 146:f64d43ff0c18 | 7274 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7275 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7276 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 7277 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 7278 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7279 | * |
mbed_official | 146:f64d43ff0c18 | 7280 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7281 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7282 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7283 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7284 | */ |
mbed_official | 146:f64d43ff0c18 | 7285 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7286 | #define BP_AIPS_PACRH_SP0 (30U) //!< Bit position for AIPS_PACRH_SP0. |
mbed_official | 146:f64d43ff0c18 | 7287 | #define BM_AIPS_PACRH_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRH_SP0. |
mbed_official | 146:f64d43ff0c18 | 7288 | #define BS_AIPS_PACRH_SP0 (1U) //!< Bit field size in bits for AIPS_PACRH_SP0. |
mbed_official | 146:f64d43ff0c18 | 7289 | |
mbed_official | 146:f64d43ff0c18 | 7290 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7291 | //! @brief Read current value of the AIPS_PACRH_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 7292 | #define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0)) |
mbed_official | 146:f64d43ff0c18 | 7293 | #endif |
mbed_official | 146:f64d43ff0c18 | 7294 | |
mbed_official | 146:f64d43ff0c18 | 7295 | //! @brief Format value for bitfield AIPS_PACRH_SP0. |
mbed_official | 146:f64d43ff0c18 | 7296 | #define BF_AIPS_PACRH_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP0), uint32_t) & BM_AIPS_PACRH_SP0) |
mbed_official | 146:f64d43ff0c18 | 7297 | |
mbed_official | 146:f64d43ff0c18 | 7298 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7299 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7300 | #define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7301 | #endif |
mbed_official | 146:f64d43ff0c18 | 7302 | //@} |
mbed_official | 146:f64d43ff0c18 | 7303 | |
mbed_official | 146:f64d43ff0c18 | 7304 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 7305 | // HW_AIPS_PACRI - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 7306 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 7307 | |
mbed_official | 146:f64d43ff0c18 | 7308 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7309 | /*! |
mbed_official | 146:f64d43ff0c18 | 7310 | * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 7311 | * |
mbed_official | 146:f64d43ff0c18 | 7312 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 7313 | * |
mbed_official | 146:f64d43ff0c18 | 7314 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 7315 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 7316 | * registers. |
mbed_official | 146:f64d43ff0c18 | 7317 | */ |
mbed_official | 146:f64d43ff0c18 | 7318 | typedef union _hw_aips_pacri |
mbed_official | 146:f64d43ff0c18 | 7319 | { |
mbed_official | 146:f64d43ff0c18 | 7320 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 7321 | struct _hw_aips_pacri_bitfields |
mbed_official | 146:f64d43ff0c18 | 7322 | { |
mbed_official | 146:f64d43ff0c18 | 7323 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7324 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7325 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7326 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 7327 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7328 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7329 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7330 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 7331 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7332 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7333 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7334 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 7335 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7336 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7337 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7338 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 7339 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7340 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7341 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7342 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 7343 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7344 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7345 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7346 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 7347 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7348 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7349 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7350 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 7351 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 7352 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 7353 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 7354 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 7355 | } B; |
mbed_official | 146:f64d43ff0c18 | 7356 | } hw_aips_pacri_t; |
mbed_official | 146:f64d43ff0c18 | 7357 | #endif |
mbed_official | 146:f64d43ff0c18 | 7358 | |
mbed_official | 146:f64d43ff0c18 | 7359 | /*! |
mbed_official | 146:f64d43ff0c18 | 7360 | * @name Constants and macros for entire AIPS_PACRI register |
mbed_official | 146:f64d43ff0c18 | 7361 | */ |
mbed_official | 146:f64d43ff0c18 | 7362 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7363 | #define HW_AIPS_PACRI_ADDR(x) (REGS_AIPS_BASE(x) + 0x50U) |
mbed_official | 146:f64d43ff0c18 | 7364 | |
mbed_official | 146:f64d43ff0c18 | 7365 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7366 | #define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 7367 | #define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U) |
mbed_official | 146:f64d43ff0c18 | 7368 | #define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 7369 | #define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 7370 | #define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 7371 | #define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 7372 | #endif |
mbed_official | 146:f64d43ff0c18 | 7373 | //@} |
mbed_official | 146:f64d43ff0c18 | 7374 | |
mbed_official | 146:f64d43ff0c18 | 7375 | /* |
mbed_official | 146:f64d43ff0c18 | 7376 | * Constants & macros for individual AIPS_PACRI bitfields |
mbed_official | 146:f64d43ff0c18 | 7377 | */ |
mbed_official | 146:f64d43ff0c18 | 7378 | |
mbed_official | 146:f64d43ff0c18 | 7379 | /*! |
mbed_official | 146:f64d43ff0c18 | 7380 | * @name Register AIPS_PACRI, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 7381 | * |
mbed_official | 146:f64d43ff0c18 | 7382 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7383 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7384 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7385 | * |
mbed_official | 146:f64d43ff0c18 | 7386 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7387 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7388 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7389 | */ |
mbed_official | 146:f64d43ff0c18 | 7390 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7391 | #define BP_AIPS_PACRI_TP7 (0U) //!< Bit position for AIPS_PACRI_TP7. |
mbed_official | 146:f64d43ff0c18 | 7392 | #define BM_AIPS_PACRI_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRI_TP7. |
mbed_official | 146:f64d43ff0c18 | 7393 | #define BS_AIPS_PACRI_TP7 (1U) //!< Bit field size in bits for AIPS_PACRI_TP7. |
mbed_official | 146:f64d43ff0c18 | 7394 | |
mbed_official | 146:f64d43ff0c18 | 7395 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7396 | //! @brief Read current value of the AIPS_PACRI_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 7397 | #define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7)) |
mbed_official | 146:f64d43ff0c18 | 7398 | #endif |
mbed_official | 146:f64d43ff0c18 | 7399 | |
mbed_official | 146:f64d43ff0c18 | 7400 | //! @brief Format value for bitfield AIPS_PACRI_TP7. |
mbed_official | 146:f64d43ff0c18 | 7401 | #define BF_AIPS_PACRI_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP7), uint32_t) & BM_AIPS_PACRI_TP7) |
mbed_official | 146:f64d43ff0c18 | 7402 | |
mbed_official | 146:f64d43ff0c18 | 7403 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7404 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7405 | #define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7406 | #endif |
mbed_official | 146:f64d43ff0c18 | 7407 | //@} |
mbed_official | 146:f64d43ff0c18 | 7408 | |
mbed_official | 146:f64d43ff0c18 | 7409 | /*! |
mbed_official | 146:f64d43ff0c18 | 7410 | * @name Register AIPS_PACRI, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 7411 | * |
mbed_official | 146:f64d43ff0c18 | 7412 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7413 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7414 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7415 | * |
mbed_official | 146:f64d43ff0c18 | 7416 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7417 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7418 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7419 | */ |
mbed_official | 146:f64d43ff0c18 | 7420 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7421 | #define BP_AIPS_PACRI_WP7 (1U) //!< Bit position for AIPS_PACRI_WP7. |
mbed_official | 146:f64d43ff0c18 | 7422 | #define BM_AIPS_PACRI_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRI_WP7. |
mbed_official | 146:f64d43ff0c18 | 7423 | #define BS_AIPS_PACRI_WP7 (1U) //!< Bit field size in bits for AIPS_PACRI_WP7. |
mbed_official | 146:f64d43ff0c18 | 7424 | |
mbed_official | 146:f64d43ff0c18 | 7425 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7426 | //! @brief Read current value of the AIPS_PACRI_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 7427 | #define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7)) |
mbed_official | 146:f64d43ff0c18 | 7428 | #endif |
mbed_official | 146:f64d43ff0c18 | 7429 | |
mbed_official | 146:f64d43ff0c18 | 7430 | //! @brief Format value for bitfield AIPS_PACRI_WP7. |
mbed_official | 146:f64d43ff0c18 | 7431 | #define BF_AIPS_PACRI_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP7), uint32_t) & BM_AIPS_PACRI_WP7) |
mbed_official | 146:f64d43ff0c18 | 7432 | |
mbed_official | 146:f64d43ff0c18 | 7433 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7434 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7435 | #define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7436 | #endif |
mbed_official | 146:f64d43ff0c18 | 7437 | //@} |
mbed_official | 146:f64d43ff0c18 | 7438 | |
mbed_official | 146:f64d43ff0c18 | 7439 | /*! |
mbed_official | 146:f64d43ff0c18 | 7440 | * @name Register AIPS_PACRI, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 7441 | * |
mbed_official | 146:f64d43ff0c18 | 7442 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7443 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7444 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 7445 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 7446 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7447 | * |
mbed_official | 146:f64d43ff0c18 | 7448 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7449 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7450 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7451 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7452 | */ |
mbed_official | 146:f64d43ff0c18 | 7453 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7454 | #define BP_AIPS_PACRI_SP7 (2U) //!< Bit position for AIPS_PACRI_SP7. |
mbed_official | 146:f64d43ff0c18 | 7455 | #define BM_AIPS_PACRI_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRI_SP7. |
mbed_official | 146:f64d43ff0c18 | 7456 | #define BS_AIPS_PACRI_SP7 (1U) //!< Bit field size in bits for AIPS_PACRI_SP7. |
mbed_official | 146:f64d43ff0c18 | 7457 | |
mbed_official | 146:f64d43ff0c18 | 7458 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7459 | //! @brief Read current value of the AIPS_PACRI_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 7460 | #define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7)) |
mbed_official | 146:f64d43ff0c18 | 7461 | #endif |
mbed_official | 146:f64d43ff0c18 | 7462 | |
mbed_official | 146:f64d43ff0c18 | 7463 | //! @brief Format value for bitfield AIPS_PACRI_SP7. |
mbed_official | 146:f64d43ff0c18 | 7464 | #define BF_AIPS_PACRI_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP7), uint32_t) & BM_AIPS_PACRI_SP7) |
mbed_official | 146:f64d43ff0c18 | 7465 | |
mbed_official | 146:f64d43ff0c18 | 7466 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7467 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7468 | #define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7469 | #endif |
mbed_official | 146:f64d43ff0c18 | 7470 | //@} |
mbed_official | 146:f64d43ff0c18 | 7471 | |
mbed_official | 146:f64d43ff0c18 | 7472 | /*! |
mbed_official | 146:f64d43ff0c18 | 7473 | * @name Register AIPS_PACRI, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 7474 | * |
mbed_official | 146:f64d43ff0c18 | 7475 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7476 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7477 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7478 | * |
mbed_official | 146:f64d43ff0c18 | 7479 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7480 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7481 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7482 | */ |
mbed_official | 146:f64d43ff0c18 | 7483 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7484 | #define BP_AIPS_PACRI_TP6 (4U) //!< Bit position for AIPS_PACRI_TP6. |
mbed_official | 146:f64d43ff0c18 | 7485 | #define BM_AIPS_PACRI_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRI_TP6. |
mbed_official | 146:f64d43ff0c18 | 7486 | #define BS_AIPS_PACRI_TP6 (1U) //!< Bit field size in bits for AIPS_PACRI_TP6. |
mbed_official | 146:f64d43ff0c18 | 7487 | |
mbed_official | 146:f64d43ff0c18 | 7488 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7489 | //! @brief Read current value of the AIPS_PACRI_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 7490 | #define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6)) |
mbed_official | 146:f64d43ff0c18 | 7491 | #endif |
mbed_official | 146:f64d43ff0c18 | 7492 | |
mbed_official | 146:f64d43ff0c18 | 7493 | //! @brief Format value for bitfield AIPS_PACRI_TP6. |
mbed_official | 146:f64d43ff0c18 | 7494 | #define BF_AIPS_PACRI_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP6), uint32_t) & BM_AIPS_PACRI_TP6) |
mbed_official | 146:f64d43ff0c18 | 7495 | |
mbed_official | 146:f64d43ff0c18 | 7496 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7497 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7498 | #define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7499 | #endif |
mbed_official | 146:f64d43ff0c18 | 7500 | //@} |
mbed_official | 146:f64d43ff0c18 | 7501 | |
mbed_official | 146:f64d43ff0c18 | 7502 | /*! |
mbed_official | 146:f64d43ff0c18 | 7503 | * @name Register AIPS_PACRI, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 7504 | * |
mbed_official | 146:f64d43ff0c18 | 7505 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7506 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7507 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7508 | * |
mbed_official | 146:f64d43ff0c18 | 7509 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7510 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7511 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7512 | */ |
mbed_official | 146:f64d43ff0c18 | 7513 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7514 | #define BP_AIPS_PACRI_WP6 (5U) //!< Bit position for AIPS_PACRI_WP6. |
mbed_official | 146:f64d43ff0c18 | 7515 | #define BM_AIPS_PACRI_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRI_WP6. |
mbed_official | 146:f64d43ff0c18 | 7516 | #define BS_AIPS_PACRI_WP6 (1U) //!< Bit field size in bits for AIPS_PACRI_WP6. |
mbed_official | 146:f64d43ff0c18 | 7517 | |
mbed_official | 146:f64d43ff0c18 | 7518 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7519 | //! @brief Read current value of the AIPS_PACRI_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 7520 | #define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6)) |
mbed_official | 146:f64d43ff0c18 | 7521 | #endif |
mbed_official | 146:f64d43ff0c18 | 7522 | |
mbed_official | 146:f64d43ff0c18 | 7523 | //! @brief Format value for bitfield AIPS_PACRI_WP6. |
mbed_official | 146:f64d43ff0c18 | 7524 | #define BF_AIPS_PACRI_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP6), uint32_t) & BM_AIPS_PACRI_WP6) |
mbed_official | 146:f64d43ff0c18 | 7525 | |
mbed_official | 146:f64d43ff0c18 | 7526 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7527 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7528 | #define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7529 | #endif |
mbed_official | 146:f64d43ff0c18 | 7530 | //@} |
mbed_official | 146:f64d43ff0c18 | 7531 | |
mbed_official | 146:f64d43ff0c18 | 7532 | /*! |
mbed_official | 146:f64d43ff0c18 | 7533 | * @name Register AIPS_PACRI, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 7534 | * |
mbed_official | 146:f64d43ff0c18 | 7535 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7536 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7537 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 7538 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 7539 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7540 | * |
mbed_official | 146:f64d43ff0c18 | 7541 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7542 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7543 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7544 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7545 | */ |
mbed_official | 146:f64d43ff0c18 | 7546 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7547 | #define BP_AIPS_PACRI_SP6 (6U) //!< Bit position for AIPS_PACRI_SP6. |
mbed_official | 146:f64d43ff0c18 | 7548 | #define BM_AIPS_PACRI_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRI_SP6. |
mbed_official | 146:f64d43ff0c18 | 7549 | #define BS_AIPS_PACRI_SP6 (1U) //!< Bit field size in bits for AIPS_PACRI_SP6. |
mbed_official | 146:f64d43ff0c18 | 7550 | |
mbed_official | 146:f64d43ff0c18 | 7551 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7552 | //! @brief Read current value of the AIPS_PACRI_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 7553 | #define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6)) |
mbed_official | 146:f64d43ff0c18 | 7554 | #endif |
mbed_official | 146:f64d43ff0c18 | 7555 | |
mbed_official | 146:f64d43ff0c18 | 7556 | //! @brief Format value for bitfield AIPS_PACRI_SP6. |
mbed_official | 146:f64d43ff0c18 | 7557 | #define BF_AIPS_PACRI_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP6), uint32_t) & BM_AIPS_PACRI_SP6) |
mbed_official | 146:f64d43ff0c18 | 7558 | |
mbed_official | 146:f64d43ff0c18 | 7559 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7560 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7561 | #define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7562 | #endif |
mbed_official | 146:f64d43ff0c18 | 7563 | //@} |
mbed_official | 146:f64d43ff0c18 | 7564 | |
mbed_official | 146:f64d43ff0c18 | 7565 | /*! |
mbed_official | 146:f64d43ff0c18 | 7566 | * @name Register AIPS_PACRI, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 7567 | * |
mbed_official | 146:f64d43ff0c18 | 7568 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7569 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7570 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7571 | * |
mbed_official | 146:f64d43ff0c18 | 7572 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7573 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7574 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7575 | */ |
mbed_official | 146:f64d43ff0c18 | 7576 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7577 | #define BP_AIPS_PACRI_TP5 (8U) //!< Bit position for AIPS_PACRI_TP5. |
mbed_official | 146:f64d43ff0c18 | 7578 | #define BM_AIPS_PACRI_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRI_TP5. |
mbed_official | 146:f64d43ff0c18 | 7579 | #define BS_AIPS_PACRI_TP5 (1U) //!< Bit field size in bits for AIPS_PACRI_TP5. |
mbed_official | 146:f64d43ff0c18 | 7580 | |
mbed_official | 146:f64d43ff0c18 | 7581 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7582 | //! @brief Read current value of the AIPS_PACRI_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 7583 | #define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5)) |
mbed_official | 146:f64d43ff0c18 | 7584 | #endif |
mbed_official | 146:f64d43ff0c18 | 7585 | |
mbed_official | 146:f64d43ff0c18 | 7586 | //! @brief Format value for bitfield AIPS_PACRI_TP5. |
mbed_official | 146:f64d43ff0c18 | 7587 | #define BF_AIPS_PACRI_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP5), uint32_t) & BM_AIPS_PACRI_TP5) |
mbed_official | 146:f64d43ff0c18 | 7588 | |
mbed_official | 146:f64d43ff0c18 | 7589 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7590 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7591 | #define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7592 | #endif |
mbed_official | 146:f64d43ff0c18 | 7593 | //@} |
mbed_official | 146:f64d43ff0c18 | 7594 | |
mbed_official | 146:f64d43ff0c18 | 7595 | /*! |
mbed_official | 146:f64d43ff0c18 | 7596 | * @name Register AIPS_PACRI, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 7597 | * |
mbed_official | 146:f64d43ff0c18 | 7598 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7599 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7600 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7601 | * |
mbed_official | 146:f64d43ff0c18 | 7602 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7603 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7604 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7605 | */ |
mbed_official | 146:f64d43ff0c18 | 7606 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7607 | #define BP_AIPS_PACRI_WP5 (9U) //!< Bit position for AIPS_PACRI_WP5. |
mbed_official | 146:f64d43ff0c18 | 7608 | #define BM_AIPS_PACRI_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRI_WP5. |
mbed_official | 146:f64d43ff0c18 | 7609 | #define BS_AIPS_PACRI_WP5 (1U) //!< Bit field size in bits for AIPS_PACRI_WP5. |
mbed_official | 146:f64d43ff0c18 | 7610 | |
mbed_official | 146:f64d43ff0c18 | 7611 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7612 | //! @brief Read current value of the AIPS_PACRI_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 7613 | #define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5)) |
mbed_official | 146:f64d43ff0c18 | 7614 | #endif |
mbed_official | 146:f64d43ff0c18 | 7615 | |
mbed_official | 146:f64d43ff0c18 | 7616 | //! @brief Format value for bitfield AIPS_PACRI_WP5. |
mbed_official | 146:f64d43ff0c18 | 7617 | #define BF_AIPS_PACRI_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP5), uint32_t) & BM_AIPS_PACRI_WP5) |
mbed_official | 146:f64d43ff0c18 | 7618 | |
mbed_official | 146:f64d43ff0c18 | 7619 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7620 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7621 | #define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7622 | #endif |
mbed_official | 146:f64d43ff0c18 | 7623 | //@} |
mbed_official | 146:f64d43ff0c18 | 7624 | |
mbed_official | 146:f64d43ff0c18 | 7625 | /*! |
mbed_official | 146:f64d43ff0c18 | 7626 | * @name Register AIPS_PACRI, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 7627 | * |
mbed_official | 146:f64d43ff0c18 | 7628 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7629 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7630 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 7631 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 7632 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7633 | * |
mbed_official | 146:f64d43ff0c18 | 7634 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7635 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7636 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7637 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7638 | */ |
mbed_official | 146:f64d43ff0c18 | 7639 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7640 | #define BP_AIPS_PACRI_SP5 (10U) //!< Bit position for AIPS_PACRI_SP5. |
mbed_official | 146:f64d43ff0c18 | 7641 | #define BM_AIPS_PACRI_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRI_SP5. |
mbed_official | 146:f64d43ff0c18 | 7642 | #define BS_AIPS_PACRI_SP5 (1U) //!< Bit field size in bits for AIPS_PACRI_SP5. |
mbed_official | 146:f64d43ff0c18 | 7643 | |
mbed_official | 146:f64d43ff0c18 | 7644 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7645 | //! @brief Read current value of the AIPS_PACRI_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 7646 | #define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5)) |
mbed_official | 146:f64d43ff0c18 | 7647 | #endif |
mbed_official | 146:f64d43ff0c18 | 7648 | |
mbed_official | 146:f64d43ff0c18 | 7649 | //! @brief Format value for bitfield AIPS_PACRI_SP5. |
mbed_official | 146:f64d43ff0c18 | 7650 | #define BF_AIPS_PACRI_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP5), uint32_t) & BM_AIPS_PACRI_SP5) |
mbed_official | 146:f64d43ff0c18 | 7651 | |
mbed_official | 146:f64d43ff0c18 | 7652 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7653 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7654 | #define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7655 | #endif |
mbed_official | 146:f64d43ff0c18 | 7656 | //@} |
mbed_official | 146:f64d43ff0c18 | 7657 | |
mbed_official | 146:f64d43ff0c18 | 7658 | /*! |
mbed_official | 146:f64d43ff0c18 | 7659 | * @name Register AIPS_PACRI, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 7660 | * |
mbed_official | 146:f64d43ff0c18 | 7661 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7662 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7663 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7664 | * |
mbed_official | 146:f64d43ff0c18 | 7665 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7666 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7667 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7668 | */ |
mbed_official | 146:f64d43ff0c18 | 7669 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7670 | #define BP_AIPS_PACRI_TP4 (12U) //!< Bit position for AIPS_PACRI_TP4. |
mbed_official | 146:f64d43ff0c18 | 7671 | #define BM_AIPS_PACRI_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRI_TP4. |
mbed_official | 146:f64d43ff0c18 | 7672 | #define BS_AIPS_PACRI_TP4 (1U) //!< Bit field size in bits for AIPS_PACRI_TP4. |
mbed_official | 146:f64d43ff0c18 | 7673 | |
mbed_official | 146:f64d43ff0c18 | 7674 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7675 | //! @brief Read current value of the AIPS_PACRI_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 7676 | #define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4)) |
mbed_official | 146:f64d43ff0c18 | 7677 | #endif |
mbed_official | 146:f64d43ff0c18 | 7678 | |
mbed_official | 146:f64d43ff0c18 | 7679 | //! @brief Format value for bitfield AIPS_PACRI_TP4. |
mbed_official | 146:f64d43ff0c18 | 7680 | #define BF_AIPS_PACRI_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP4), uint32_t) & BM_AIPS_PACRI_TP4) |
mbed_official | 146:f64d43ff0c18 | 7681 | |
mbed_official | 146:f64d43ff0c18 | 7682 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7683 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7684 | #define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7685 | #endif |
mbed_official | 146:f64d43ff0c18 | 7686 | //@} |
mbed_official | 146:f64d43ff0c18 | 7687 | |
mbed_official | 146:f64d43ff0c18 | 7688 | /*! |
mbed_official | 146:f64d43ff0c18 | 7689 | * @name Register AIPS_PACRI, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 7690 | * |
mbed_official | 146:f64d43ff0c18 | 7691 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7692 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7693 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7694 | * |
mbed_official | 146:f64d43ff0c18 | 7695 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7696 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7697 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7698 | */ |
mbed_official | 146:f64d43ff0c18 | 7699 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7700 | #define BP_AIPS_PACRI_WP4 (13U) //!< Bit position for AIPS_PACRI_WP4. |
mbed_official | 146:f64d43ff0c18 | 7701 | #define BM_AIPS_PACRI_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRI_WP4. |
mbed_official | 146:f64d43ff0c18 | 7702 | #define BS_AIPS_PACRI_WP4 (1U) //!< Bit field size in bits for AIPS_PACRI_WP4. |
mbed_official | 146:f64d43ff0c18 | 7703 | |
mbed_official | 146:f64d43ff0c18 | 7704 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7705 | //! @brief Read current value of the AIPS_PACRI_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 7706 | #define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4)) |
mbed_official | 146:f64d43ff0c18 | 7707 | #endif |
mbed_official | 146:f64d43ff0c18 | 7708 | |
mbed_official | 146:f64d43ff0c18 | 7709 | //! @brief Format value for bitfield AIPS_PACRI_WP4. |
mbed_official | 146:f64d43ff0c18 | 7710 | #define BF_AIPS_PACRI_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP4), uint32_t) & BM_AIPS_PACRI_WP4) |
mbed_official | 146:f64d43ff0c18 | 7711 | |
mbed_official | 146:f64d43ff0c18 | 7712 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7713 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7714 | #define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7715 | #endif |
mbed_official | 146:f64d43ff0c18 | 7716 | //@} |
mbed_official | 146:f64d43ff0c18 | 7717 | |
mbed_official | 146:f64d43ff0c18 | 7718 | /*! |
mbed_official | 146:f64d43ff0c18 | 7719 | * @name Register AIPS_PACRI, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 7720 | * |
mbed_official | 146:f64d43ff0c18 | 7721 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7722 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7723 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 7724 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 7725 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 7726 | * |
mbed_official | 146:f64d43ff0c18 | 7727 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7728 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7729 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7730 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7731 | */ |
mbed_official | 146:f64d43ff0c18 | 7732 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7733 | #define BP_AIPS_PACRI_SP4 (14U) //!< Bit position for AIPS_PACRI_SP4. |
mbed_official | 146:f64d43ff0c18 | 7734 | #define BM_AIPS_PACRI_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRI_SP4. |
mbed_official | 146:f64d43ff0c18 | 7735 | #define BS_AIPS_PACRI_SP4 (1U) //!< Bit field size in bits for AIPS_PACRI_SP4. |
mbed_official | 146:f64d43ff0c18 | 7736 | |
mbed_official | 146:f64d43ff0c18 | 7737 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7738 | //! @brief Read current value of the AIPS_PACRI_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 7739 | #define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4)) |
mbed_official | 146:f64d43ff0c18 | 7740 | #endif |
mbed_official | 146:f64d43ff0c18 | 7741 | |
mbed_official | 146:f64d43ff0c18 | 7742 | //! @brief Format value for bitfield AIPS_PACRI_SP4. |
mbed_official | 146:f64d43ff0c18 | 7743 | #define BF_AIPS_PACRI_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP4), uint32_t) & BM_AIPS_PACRI_SP4) |
mbed_official | 146:f64d43ff0c18 | 7744 | |
mbed_official | 146:f64d43ff0c18 | 7745 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7746 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7747 | #define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7748 | #endif |
mbed_official | 146:f64d43ff0c18 | 7749 | //@} |
mbed_official | 146:f64d43ff0c18 | 7750 | |
mbed_official | 146:f64d43ff0c18 | 7751 | /*! |
mbed_official | 146:f64d43ff0c18 | 7752 | * @name Register AIPS_PACRI, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 7753 | * |
mbed_official | 146:f64d43ff0c18 | 7754 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7755 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7756 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7757 | * |
mbed_official | 146:f64d43ff0c18 | 7758 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7759 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7760 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7761 | */ |
mbed_official | 146:f64d43ff0c18 | 7762 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7763 | #define BP_AIPS_PACRI_TP3 (16U) //!< Bit position for AIPS_PACRI_TP3. |
mbed_official | 146:f64d43ff0c18 | 7764 | #define BM_AIPS_PACRI_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRI_TP3. |
mbed_official | 146:f64d43ff0c18 | 7765 | #define BS_AIPS_PACRI_TP3 (1U) //!< Bit field size in bits for AIPS_PACRI_TP3. |
mbed_official | 146:f64d43ff0c18 | 7766 | |
mbed_official | 146:f64d43ff0c18 | 7767 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7768 | //! @brief Read current value of the AIPS_PACRI_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 7769 | #define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3)) |
mbed_official | 146:f64d43ff0c18 | 7770 | #endif |
mbed_official | 146:f64d43ff0c18 | 7771 | |
mbed_official | 146:f64d43ff0c18 | 7772 | //! @brief Format value for bitfield AIPS_PACRI_TP3. |
mbed_official | 146:f64d43ff0c18 | 7773 | #define BF_AIPS_PACRI_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP3), uint32_t) & BM_AIPS_PACRI_TP3) |
mbed_official | 146:f64d43ff0c18 | 7774 | |
mbed_official | 146:f64d43ff0c18 | 7775 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7776 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7777 | #define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7778 | #endif |
mbed_official | 146:f64d43ff0c18 | 7779 | //@} |
mbed_official | 146:f64d43ff0c18 | 7780 | |
mbed_official | 146:f64d43ff0c18 | 7781 | /*! |
mbed_official | 146:f64d43ff0c18 | 7782 | * @name Register AIPS_PACRI, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 7783 | * |
mbed_official | 146:f64d43ff0c18 | 7784 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 7785 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 7786 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7787 | * |
mbed_official | 146:f64d43ff0c18 | 7788 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7789 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7790 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7791 | */ |
mbed_official | 146:f64d43ff0c18 | 7792 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7793 | #define BP_AIPS_PACRI_WP3 (17U) //!< Bit position for AIPS_PACRI_WP3. |
mbed_official | 146:f64d43ff0c18 | 7794 | #define BM_AIPS_PACRI_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRI_WP3. |
mbed_official | 146:f64d43ff0c18 | 7795 | #define BS_AIPS_PACRI_WP3 (1U) //!< Bit field size in bits for AIPS_PACRI_WP3. |
mbed_official | 146:f64d43ff0c18 | 7796 | |
mbed_official | 146:f64d43ff0c18 | 7797 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7798 | //! @brief Read current value of the AIPS_PACRI_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 7799 | #define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3)) |
mbed_official | 146:f64d43ff0c18 | 7800 | #endif |
mbed_official | 146:f64d43ff0c18 | 7801 | |
mbed_official | 146:f64d43ff0c18 | 7802 | //! @brief Format value for bitfield AIPS_PACRI_WP3. |
mbed_official | 146:f64d43ff0c18 | 7803 | #define BF_AIPS_PACRI_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP3), uint32_t) & BM_AIPS_PACRI_WP3) |
mbed_official | 146:f64d43ff0c18 | 7804 | |
mbed_official | 146:f64d43ff0c18 | 7805 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7806 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7807 | #define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7808 | #endif |
mbed_official | 146:f64d43ff0c18 | 7809 | //@} |
mbed_official | 146:f64d43ff0c18 | 7810 | |
mbed_official | 146:f64d43ff0c18 | 7811 | /*! |
mbed_official | 146:f64d43ff0c18 | 7812 | * @name Register AIPS_PACRI, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 7813 | * |
mbed_official | 146:f64d43ff0c18 | 7814 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7815 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7816 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 7817 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 7818 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 7819 | * |
mbed_official | 146:f64d43ff0c18 | 7820 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7821 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7822 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7823 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7824 | */ |
mbed_official | 146:f64d43ff0c18 | 7825 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7826 | #define BP_AIPS_PACRI_SP3 (18U) //!< Bit position for AIPS_PACRI_SP3. |
mbed_official | 146:f64d43ff0c18 | 7827 | #define BM_AIPS_PACRI_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRI_SP3. |
mbed_official | 146:f64d43ff0c18 | 7828 | #define BS_AIPS_PACRI_SP3 (1U) //!< Bit field size in bits for AIPS_PACRI_SP3. |
mbed_official | 146:f64d43ff0c18 | 7829 | |
mbed_official | 146:f64d43ff0c18 | 7830 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7831 | //! @brief Read current value of the AIPS_PACRI_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 7832 | #define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3)) |
mbed_official | 146:f64d43ff0c18 | 7833 | #endif |
mbed_official | 146:f64d43ff0c18 | 7834 | |
mbed_official | 146:f64d43ff0c18 | 7835 | //! @brief Format value for bitfield AIPS_PACRI_SP3. |
mbed_official | 146:f64d43ff0c18 | 7836 | #define BF_AIPS_PACRI_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP3), uint32_t) & BM_AIPS_PACRI_SP3) |
mbed_official | 146:f64d43ff0c18 | 7837 | |
mbed_official | 146:f64d43ff0c18 | 7838 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7839 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7840 | #define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7841 | #endif |
mbed_official | 146:f64d43ff0c18 | 7842 | //@} |
mbed_official | 146:f64d43ff0c18 | 7843 | |
mbed_official | 146:f64d43ff0c18 | 7844 | /*! |
mbed_official | 146:f64d43ff0c18 | 7845 | * @name Register AIPS_PACRI, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 7846 | * |
mbed_official | 146:f64d43ff0c18 | 7847 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7848 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7849 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7850 | * |
mbed_official | 146:f64d43ff0c18 | 7851 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7852 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7853 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7854 | */ |
mbed_official | 146:f64d43ff0c18 | 7855 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7856 | #define BP_AIPS_PACRI_TP2 (20U) //!< Bit position for AIPS_PACRI_TP2. |
mbed_official | 146:f64d43ff0c18 | 7857 | #define BM_AIPS_PACRI_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRI_TP2. |
mbed_official | 146:f64d43ff0c18 | 7858 | #define BS_AIPS_PACRI_TP2 (1U) //!< Bit field size in bits for AIPS_PACRI_TP2. |
mbed_official | 146:f64d43ff0c18 | 7859 | |
mbed_official | 146:f64d43ff0c18 | 7860 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7861 | //! @brief Read current value of the AIPS_PACRI_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 7862 | #define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2)) |
mbed_official | 146:f64d43ff0c18 | 7863 | #endif |
mbed_official | 146:f64d43ff0c18 | 7864 | |
mbed_official | 146:f64d43ff0c18 | 7865 | //! @brief Format value for bitfield AIPS_PACRI_TP2. |
mbed_official | 146:f64d43ff0c18 | 7866 | #define BF_AIPS_PACRI_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP2), uint32_t) & BM_AIPS_PACRI_TP2) |
mbed_official | 146:f64d43ff0c18 | 7867 | |
mbed_official | 146:f64d43ff0c18 | 7868 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7869 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7870 | #define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7871 | #endif |
mbed_official | 146:f64d43ff0c18 | 7872 | //@} |
mbed_official | 146:f64d43ff0c18 | 7873 | |
mbed_official | 146:f64d43ff0c18 | 7874 | /*! |
mbed_official | 146:f64d43ff0c18 | 7875 | * @name Register AIPS_PACRI, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 7876 | * |
mbed_official | 146:f64d43ff0c18 | 7877 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7878 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7879 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7880 | * |
mbed_official | 146:f64d43ff0c18 | 7881 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7882 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7883 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7884 | */ |
mbed_official | 146:f64d43ff0c18 | 7885 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7886 | #define BP_AIPS_PACRI_WP2 (21U) //!< Bit position for AIPS_PACRI_WP2. |
mbed_official | 146:f64d43ff0c18 | 7887 | #define BM_AIPS_PACRI_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRI_WP2. |
mbed_official | 146:f64d43ff0c18 | 7888 | #define BS_AIPS_PACRI_WP2 (1U) //!< Bit field size in bits for AIPS_PACRI_WP2. |
mbed_official | 146:f64d43ff0c18 | 7889 | |
mbed_official | 146:f64d43ff0c18 | 7890 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7891 | //! @brief Read current value of the AIPS_PACRI_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 7892 | #define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2)) |
mbed_official | 146:f64d43ff0c18 | 7893 | #endif |
mbed_official | 146:f64d43ff0c18 | 7894 | |
mbed_official | 146:f64d43ff0c18 | 7895 | //! @brief Format value for bitfield AIPS_PACRI_WP2. |
mbed_official | 146:f64d43ff0c18 | 7896 | #define BF_AIPS_PACRI_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP2), uint32_t) & BM_AIPS_PACRI_WP2) |
mbed_official | 146:f64d43ff0c18 | 7897 | |
mbed_official | 146:f64d43ff0c18 | 7898 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7899 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7900 | #define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7901 | #endif |
mbed_official | 146:f64d43ff0c18 | 7902 | //@} |
mbed_official | 146:f64d43ff0c18 | 7903 | |
mbed_official | 146:f64d43ff0c18 | 7904 | /*! |
mbed_official | 146:f64d43ff0c18 | 7905 | * @name Register AIPS_PACRI, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 7906 | * |
mbed_official | 146:f64d43ff0c18 | 7907 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7908 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 7909 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 7910 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 7911 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 7912 | * |
mbed_official | 146:f64d43ff0c18 | 7913 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7914 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 7915 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 7916 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 7917 | */ |
mbed_official | 146:f64d43ff0c18 | 7918 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7919 | #define BP_AIPS_PACRI_SP2 (22U) //!< Bit position for AIPS_PACRI_SP2. |
mbed_official | 146:f64d43ff0c18 | 7920 | #define BM_AIPS_PACRI_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRI_SP2. |
mbed_official | 146:f64d43ff0c18 | 7921 | #define BS_AIPS_PACRI_SP2 (1U) //!< Bit field size in bits for AIPS_PACRI_SP2. |
mbed_official | 146:f64d43ff0c18 | 7922 | |
mbed_official | 146:f64d43ff0c18 | 7923 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7924 | //! @brief Read current value of the AIPS_PACRI_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 7925 | #define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2)) |
mbed_official | 146:f64d43ff0c18 | 7926 | #endif |
mbed_official | 146:f64d43ff0c18 | 7927 | |
mbed_official | 146:f64d43ff0c18 | 7928 | //! @brief Format value for bitfield AIPS_PACRI_SP2. |
mbed_official | 146:f64d43ff0c18 | 7929 | #define BF_AIPS_PACRI_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP2), uint32_t) & BM_AIPS_PACRI_SP2) |
mbed_official | 146:f64d43ff0c18 | 7930 | |
mbed_official | 146:f64d43ff0c18 | 7931 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7932 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7933 | #define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7934 | #endif |
mbed_official | 146:f64d43ff0c18 | 7935 | //@} |
mbed_official | 146:f64d43ff0c18 | 7936 | |
mbed_official | 146:f64d43ff0c18 | 7937 | /*! |
mbed_official | 146:f64d43ff0c18 | 7938 | * @name Register AIPS_PACRI, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 7939 | * |
mbed_official | 146:f64d43ff0c18 | 7940 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 7941 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 7942 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7943 | * |
mbed_official | 146:f64d43ff0c18 | 7944 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7945 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 7946 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 7947 | */ |
mbed_official | 146:f64d43ff0c18 | 7948 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7949 | #define BP_AIPS_PACRI_TP1 (24U) //!< Bit position for AIPS_PACRI_TP1. |
mbed_official | 146:f64d43ff0c18 | 7950 | #define BM_AIPS_PACRI_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRI_TP1. |
mbed_official | 146:f64d43ff0c18 | 7951 | #define BS_AIPS_PACRI_TP1 (1U) //!< Bit field size in bits for AIPS_PACRI_TP1. |
mbed_official | 146:f64d43ff0c18 | 7952 | |
mbed_official | 146:f64d43ff0c18 | 7953 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7954 | //! @brief Read current value of the AIPS_PACRI_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 7955 | #define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1)) |
mbed_official | 146:f64d43ff0c18 | 7956 | #endif |
mbed_official | 146:f64d43ff0c18 | 7957 | |
mbed_official | 146:f64d43ff0c18 | 7958 | //! @brief Format value for bitfield AIPS_PACRI_TP1. |
mbed_official | 146:f64d43ff0c18 | 7959 | #define BF_AIPS_PACRI_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP1), uint32_t) & BM_AIPS_PACRI_TP1) |
mbed_official | 146:f64d43ff0c18 | 7960 | |
mbed_official | 146:f64d43ff0c18 | 7961 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7962 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7963 | #define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7964 | #endif |
mbed_official | 146:f64d43ff0c18 | 7965 | //@} |
mbed_official | 146:f64d43ff0c18 | 7966 | |
mbed_official | 146:f64d43ff0c18 | 7967 | /*! |
mbed_official | 146:f64d43ff0c18 | 7968 | * @name Register AIPS_PACRI, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 7969 | * |
mbed_official | 146:f64d43ff0c18 | 7970 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 7971 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 7972 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 7973 | * |
mbed_official | 146:f64d43ff0c18 | 7974 | * Values: |
mbed_official | 146:f64d43ff0c18 | 7975 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 7976 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 7977 | */ |
mbed_official | 146:f64d43ff0c18 | 7978 | //@{ |
mbed_official | 146:f64d43ff0c18 | 7979 | #define BP_AIPS_PACRI_WP1 (25U) //!< Bit position for AIPS_PACRI_WP1. |
mbed_official | 146:f64d43ff0c18 | 7980 | #define BM_AIPS_PACRI_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRI_WP1. |
mbed_official | 146:f64d43ff0c18 | 7981 | #define BS_AIPS_PACRI_WP1 (1U) //!< Bit field size in bits for AIPS_PACRI_WP1. |
mbed_official | 146:f64d43ff0c18 | 7982 | |
mbed_official | 146:f64d43ff0c18 | 7983 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7984 | //! @brief Read current value of the AIPS_PACRI_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 7985 | #define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1)) |
mbed_official | 146:f64d43ff0c18 | 7986 | #endif |
mbed_official | 146:f64d43ff0c18 | 7987 | |
mbed_official | 146:f64d43ff0c18 | 7988 | //! @brief Format value for bitfield AIPS_PACRI_WP1. |
mbed_official | 146:f64d43ff0c18 | 7989 | #define BF_AIPS_PACRI_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP1), uint32_t) & BM_AIPS_PACRI_WP1) |
mbed_official | 146:f64d43ff0c18 | 7990 | |
mbed_official | 146:f64d43ff0c18 | 7991 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 7992 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 7993 | #define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 7994 | #endif |
mbed_official | 146:f64d43ff0c18 | 7995 | //@} |
mbed_official | 146:f64d43ff0c18 | 7996 | |
mbed_official | 146:f64d43ff0c18 | 7997 | /*! |
mbed_official | 146:f64d43ff0c18 | 7998 | * @name Register AIPS_PACRI, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 7999 | * |
mbed_official | 146:f64d43ff0c18 | 8000 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8001 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8002 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 8003 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8004 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8005 | * |
mbed_official | 146:f64d43ff0c18 | 8006 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8007 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8008 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8009 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8010 | */ |
mbed_official | 146:f64d43ff0c18 | 8011 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8012 | #define BP_AIPS_PACRI_SP1 (26U) //!< Bit position for AIPS_PACRI_SP1. |
mbed_official | 146:f64d43ff0c18 | 8013 | #define BM_AIPS_PACRI_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRI_SP1. |
mbed_official | 146:f64d43ff0c18 | 8014 | #define BS_AIPS_PACRI_SP1 (1U) //!< Bit field size in bits for AIPS_PACRI_SP1. |
mbed_official | 146:f64d43ff0c18 | 8015 | |
mbed_official | 146:f64d43ff0c18 | 8016 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8017 | //! @brief Read current value of the AIPS_PACRI_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 8018 | #define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1)) |
mbed_official | 146:f64d43ff0c18 | 8019 | #endif |
mbed_official | 146:f64d43ff0c18 | 8020 | |
mbed_official | 146:f64d43ff0c18 | 8021 | //! @brief Format value for bitfield AIPS_PACRI_SP1. |
mbed_official | 146:f64d43ff0c18 | 8022 | #define BF_AIPS_PACRI_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP1), uint32_t) & BM_AIPS_PACRI_SP1) |
mbed_official | 146:f64d43ff0c18 | 8023 | |
mbed_official | 146:f64d43ff0c18 | 8024 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8025 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8026 | #define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8027 | #endif |
mbed_official | 146:f64d43ff0c18 | 8028 | //@} |
mbed_official | 146:f64d43ff0c18 | 8029 | |
mbed_official | 146:f64d43ff0c18 | 8030 | /*! |
mbed_official | 146:f64d43ff0c18 | 8031 | * @name Register AIPS_PACRI, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 8032 | * |
mbed_official | 146:f64d43ff0c18 | 8033 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8034 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8035 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8036 | * |
mbed_official | 146:f64d43ff0c18 | 8037 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8038 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8039 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8040 | */ |
mbed_official | 146:f64d43ff0c18 | 8041 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8042 | #define BP_AIPS_PACRI_TP0 (28U) //!< Bit position for AIPS_PACRI_TP0. |
mbed_official | 146:f64d43ff0c18 | 8043 | #define BM_AIPS_PACRI_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRI_TP0. |
mbed_official | 146:f64d43ff0c18 | 8044 | #define BS_AIPS_PACRI_TP0 (1U) //!< Bit field size in bits for AIPS_PACRI_TP0. |
mbed_official | 146:f64d43ff0c18 | 8045 | |
mbed_official | 146:f64d43ff0c18 | 8046 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8047 | //! @brief Read current value of the AIPS_PACRI_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 8048 | #define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0)) |
mbed_official | 146:f64d43ff0c18 | 8049 | #endif |
mbed_official | 146:f64d43ff0c18 | 8050 | |
mbed_official | 146:f64d43ff0c18 | 8051 | //! @brief Format value for bitfield AIPS_PACRI_TP0. |
mbed_official | 146:f64d43ff0c18 | 8052 | #define BF_AIPS_PACRI_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP0), uint32_t) & BM_AIPS_PACRI_TP0) |
mbed_official | 146:f64d43ff0c18 | 8053 | |
mbed_official | 146:f64d43ff0c18 | 8054 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8055 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8056 | #define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8057 | #endif |
mbed_official | 146:f64d43ff0c18 | 8058 | //@} |
mbed_official | 146:f64d43ff0c18 | 8059 | |
mbed_official | 146:f64d43ff0c18 | 8060 | /*! |
mbed_official | 146:f64d43ff0c18 | 8061 | * @name Register AIPS_PACRI, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 8062 | * |
mbed_official | 146:f64d43ff0c18 | 8063 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8064 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8065 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8066 | * |
mbed_official | 146:f64d43ff0c18 | 8067 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8068 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8069 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8070 | */ |
mbed_official | 146:f64d43ff0c18 | 8071 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8072 | #define BP_AIPS_PACRI_WP0 (29U) //!< Bit position for AIPS_PACRI_WP0. |
mbed_official | 146:f64d43ff0c18 | 8073 | #define BM_AIPS_PACRI_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRI_WP0. |
mbed_official | 146:f64d43ff0c18 | 8074 | #define BS_AIPS_PACRI_WP0 (1U) //!< Bit field size in bits for AIPS_PACRI_WP0. |
mbed_official | 146:f64d43ff0c18 | 8075 | |
mbed_official | 146:f64d43ff0c18 | 8076 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8077 | //! @brief Read current value of the AIPS_PACRI_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 8078 | #define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0)) |
mbed_official | 146:f64d43ff0c18 | 8079 | #endif |
mbed_official | 146:f64d43ff0c18 | 8080 | |
mbed_official | 146:f64d43ff0c18 | 8081 | //! @brief Format value for bitfield AIPS_PACRI_WP0. |
mbed_official | 146:f64d43ff0c18 | 8082 | #define BF_AIPS_PACRI_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP0), uint32_t) & BM_AIPS_PACRI_WP0) |
mbed_official | 146:f64d43ff0c18 | 8083 | |
mbed_official | 146:f64d43ff0c18 | 8084 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8085 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8086 | #define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8087 | #endif |
mbed_official | 146:f64d43ff0c18 | 8088 | //@} |
mbed_official | 146:f64d43ff0c18 | 8089 | |
mbed_official | 146:f64d43ff0c18 | 8090 | /*! |
mbed_official | 146:f64d43ff0c18 | 8091 | * @name Register AIPS_PACRI, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 8092 | * |
mbed_official | 146:f64d43ff0c18 | 8093 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8094 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8095 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 8096 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8097 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8098 | * |
mbed_official | 146:f64d43ff0c18 | 8099 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8100 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8101 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8102 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8103 | */ |
mbed_official | 146:f64d43ff0c18 | 8104 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8105 | #define BP_AIPS_PACRI_SP0 (30U) //!< Bit position for AIPS_PACRI_SP0. |
mbed_official | 146:f64d43ff0c18 | 8106 | #define BM_AIPS_PACRI_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRI_SP0. |
mbed_official | 146:f64d43ff0c18 | 8107 | #define BS_AIPS_PACRI_SP0 (1U) //!< Bit field size in bits for AIPS_PACRI_SP0. |
mbed_official | 146:f64d43ff0c18 | 8108 | |
mbed_official | 146:f64d43ff0c18 | 8109 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8110 | //! @brief Read current value of the AIPS_PACRI_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 8111 | #define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0)) |
mbed_official | 146:f64d43ff0c18 | 8112 | #endif |
mbed_official | 146:f64d43ff0c18 | 8113 | |
mbed_official | 146:f64d43ff0c18 | 8114 | //! @brief Format value for bitfield AIPS_PACRI_SP0. |
mbed_official | 146:f64d43ff0c18 | 8115 | #define BF_AIPS_PACRI_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP0), uint32_t) & BM_AIPS_PACRI_SP0) |
mbed_official | 146:f64d43ff0c18 | 8116 | |
mbed_official | 146:f64d43ff0c18 | 8117 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8118 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8119 | #define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8120 | #endif |
mbed_official | 146:f64d43ff0c18 | 8121 | //@} |
mbed_official | 146:f64d43ff0c18 | 8122 | |
mbed_official | 146:f64d43ff0c18 | 8123 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 8124 | // HW_AIPS_PACRJ - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 8125 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 8126 | |
mbed_official | 146:f64d43ff0c18 | 8127 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8128 | /*! |
mbed_official | 146:f64d43ff0c18 | 8129 | * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 8130 | * |
mbed_official | 146:f64d43ff0c18 | 8131 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 8132 | * |
mbed_official | 146:f64d43ff0c18 | 8133 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 8134 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 8135 | * registers. |
mbed_official | 146:f64d43ff0c18 | 8136 | */ |
mbed_official | 146:f64d43ff0c18 | 8137 | typedef union _hw_aips_pacrj |
mbed_official | 146:f64d43ff0c18 | 8138 | { |
mbed_official | 146:f64d43ff0c18 | 8139 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 8140 | struct _hw_aips_pacrj_bitfields |
mbed_official | 146:f64d43ff0c18 | 8141 | { |
mbed_official | 146:f64d43ff0c18 | 8142 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8143 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8144 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8145 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 8146 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8147 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8148 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8149 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 8150 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8151 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8152 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8153 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 8154 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8155 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8156 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8157 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 8158 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8159 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8160 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8161 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 8162 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8163 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8164 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8165 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 8166 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8167 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8168 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8169 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 8170 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8171 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8172 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8173 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 8174 | } B; |
mbed_official | 146:f64d43ff0c18 | 8175 | } hw_aips_pacrj_t; |
mbed_official | 146:f64d43ff0c18 | 8176 | #endif |
mbed_official | 146:f64d43ff0c18 | 8177 | |
mbed_official | 146:f64d43ff0c18 | 8178 | /*! |
mbed_official | 146:f64d43ff0c18 | 8179 | * @name Constants and macros for entire AIPS_PACRJ register |
mbed_official | 146:f64d43ff0c18 | 8180 | */ |
mbed_official | 146:f64d43ff0c18 | 8181 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8182 | #define HW_AIPS_PACRJ_ADDR(x) (REGS_AIPS_BASE(x) + 0x54U) |
mbed_official | 146:f64d43ff0c18 | 8183 | |
mbed_official | 146:f64d43ff0c18 | 8184 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8185 | #define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 8186 | #define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U) |
mbed_official | 146:f64d43ff0c18 | 8187 | #define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 8188 | #define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 8189 | #define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 8190 | #define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 8191 | #endif |
mbed_official | 146:f64d43ff0c18 | 8192 | //@} |
mbed_official | 146:f64d43ff0c18 | 8193 | |
mbed_official | 146:f64d43ff0c18 | 8194 | /* |
mbed_official | 146:f64d43ff0c18 | 8195 | * Constants & macros for individual AIPS_PACRJ bitfields |
mbed_official | 146:f64d43ff0c18 | 8196 | */ |
mbed_official | 146:f64d43ff0c18 | 8197 | |
mbed_official | 146:f64d43ff0c18 | 8198 | /*! |
mbed_official | 146:f64d43ff0c18 | 8199 | * @name Register AIPS_PACRJ, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 8200 | * |
mbed_official | 146:f64d43ff0c18 | 8201 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8202 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8203 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8204 | * |
mbed_official | 146:f64d43ff0c18 | 8205 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8206 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8207 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8208 | */ |
mbed_official | 146:f64d43ff0c18 | 8209 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8210 | #define BP_AIPS_PACRJ_TP7 (0U) //!< Bit position for AIPS_PACRJ_TP7. |
mbed_official | 146:f64d43ff0c18 | 8211 | #define BM_AIPS_PACRJ_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRJ_TP7. |
mbed_official | 146:f64d43ff0c18 | 8212 | #define BS_AIPS_PACRJ_TP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP7. |
mbed_official | 146:f64d43ff0c18 | 8213 | |
mbed_official | 146:f64d43ff0c18 | 8214 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8215 | //! @brief Read current value of the AIPS_PACRJ_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 8216 | #define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7)) |
mbed_official | 146:f64d43ff0c18 | 8217 | #endif |
mbed_official | 146:f64d43ff0c18 | 8218 | |
mbed_official | 146:f64d43ff0c18 | 8219 | //! @brief Format value for bitfield AIPS_PACRJ_TP7. |
mbed_official | 146:f64d43ff0c18 | 8220 | #define BF_AIPS_PACRJ_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP7), uint32_t) & BM_AIPS_PACRJ_TP7) |
mbed_official | 146:f64d43ff0c18 | 8221 | |
mbed_official | 146:f64d43ff0c18 | 8222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8223 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8224 | #define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8225 | #endif |
mbed_official | 146:f64d43ff0c18 | 8226 | //@} |
mbed_official | 146:f64d43ff0c18 | 8227 | |
mbed_official | 146:f64d43ff0c18 | 8228 | /*! |
mbed_official | 146:f64d43ff0c18 | 8229 | * @name Register AIPS_PACRJ, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 8230 | * |
mbed_official | 146:f64d43ff0c18 | 8231 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8232 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8233 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8234 | * |
mbed_official | 146:f64d43ff0c18 | 8235 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8236 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8237 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8238 | */ |
mbed_official | 146:f64d43ff0c18 | 8239 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8240 | #define BP_AIPS_PACRJ_WP7 (1U) //!< Bit position for AIPS_PACRJ_WP7. |
mbed_official | 146:f64d43ff0c18 | 8241 | #define BM_AIPS_PACRJ_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRJ_WP7. |
mbed_official | 146:f64d43ff0c18 | 8242 | #define BS_AIPS_PACRJ_WP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP7. |
mbed_official | 146:f64d43ff0c18 | 8243 | |
mbed_official | 146:f64d43ff0c18 | 8244 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8245 | //! @brief Read current value of the AIPS_PACRJ_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 8246 | #define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7)) |
mbed_official | 146:f64d43ff0c18 | 8247 | #endif |
mbed_official | 146:f64d43ff0c18 | 8248 | |
mbed_official | 146:f64d43ff0c18 | 8249 | //! @brief Format value for bitfield AIPS_PACRJ_WP7. |
mbed_official | 146:f64d43ff0c18 | 8250 | #define BF_AIPS_PACRJ_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP7), uint32_t) & BM_AIPS_PACRJ_WP7) |
mbed_official | 146:f64d43ff0c18 | 8251 | |
mbed_official | 146:f64d43ff0c18 | 8252 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8253 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8254 | #define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8255 | #endif |
mbed_official | 146:f64d43ff0c18 | 8256 | //@} |
mbed_official | 146:f64d43ff0c18 | 8257 | |
mbed_official | 146:f64d43ff0c18 | 8258 | /*! |
mbed_official | 146:f64d43ff0c18 | 8259 | * @name Register AIPS_PACRJ, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 8260 | * |
mbed_official | 146:f64d43ff0c18 | 8261 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8262 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8263 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 8264 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8265 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8266 | * |
mbed_official | 146:f64d43ff0c18 | 8267 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8268 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8269 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8270 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8271 | */ |
mbed_official | 146:f64d43ff0c18 | 8272 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8273 | #define BP_AIPS_PACRJ_SP7 (2U) //!< Bit position for AIPS_PACRJ_SP7. |
mbed_official | 146:f64d43ff0c18 | 8274 | #define BM_AIPS_PACRJ_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRJ_SP7. |
mbed_official | 146:f64d43ff0c18 | 8275 | #define BS_AIPS_PACRJ_SP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP7. |
mbed_official | 146:f64d43ff0c18 | 8276 | |
mbed_official | 146:f64d43ff0c18 | 8277 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8278 | //! @brief Read current value of the AIPS_PACRJ_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 8279 | #define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7)) |
mbed_official | 146:f64d43ff0c18 | 8280 | #endif |
mbed_official | 146:f64d43ff0c18 | 8281 | |
mbed_official | 146:f64d43ff0c18 | 8282 | //! @brief Format value for bitfield AIPS_PACRJ_SP7. |
mbed_official | 146:f64d43ff0c18 | 8283 | #define BF_AIPS_PACRJ_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP7), uint32_t) & BM_AIPS_PACRJ_SP7) |
mbed_official | 146:f64d43ff0c18 | 8284 | |
mbed_official | 146:f64d43ff0c18 | 8285 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8286 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8287 | #define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8288 | #endif |
mbed_official | 146:f64d43ff0c18 | 8289 | //@} |
mbed_official | 146:f64d43ff0c18 | 8290 | |
mbed_official | 146:f64d43ff0c18 | 8291 | /*! |
mbed_official | 146:f64d43ff0c18 | 8292 | * @name Register AIPS_PACRJ, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 8293 | * |
mbed_official | 146:f64d43ff0c18 | 8294 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8295 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8296 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8297 | * |
mbed_official | 146:f64d43ff0c18 | 8298 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8299 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8300 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8301 | */ |
mbed_official | 146:f64d43ff0c18 | 8302 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8303 | #define BP_AIPS_PACRJ_TP6 (4U) //!< Bit position for AIPS_PACRJ_TP6. |
mbed_official | 146:f64d43ff0c18 | 8304 | #define BM_AIPS_PACRJ_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRJ_TP6. |
mbed_official | 146:f64d43ff0c18 | 8305 | #define BS_AIPS_PACRJ_TP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP6. |
mbed_official | 146:f64d43ff0c18 | 8306 | |
mbed_official | 146:f64d43ff0c18 | 8307 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8308 | //! @brief Read current value of the AIPS_PACRJ_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 8309 | #define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6)) |
mbed_official | 146:f64d43ff0c18 | 8310 | #endif |
mbed_official | 146:f64d43ff0c18 | 8311 | |
mbed_official | 146:f64d43ff0c18 | 8312 | //! @brief Format value for bitfield AIPS_PACRJ_TP6. |
mbed_official | 146:f64d43ff0c18 | 8313 | #define BF_AIPS_PACRJ_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP6), uint32_t) & BM_AIPS_PACRJ_TP6) |
mbed_official | 146:f64d43ff0c18 | 8314 | |
mbed_official | 146:f64d43ff0c18 | 8315 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8316 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8317 | #define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8318 | #endif |
mbed_official | 146:f64d43ff0c18 | 8319 | //@} |
mbed_official | 146:f64d43ff0c18 | 8320 | |
mbed_official | 146:f64d43ff0c18 | 8321 | /*! |
mbed_official | 146:f64d43ff0c18 | 8322 | * @name Register AIPS_PACRJ, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 8323 | * |
mbed_official | 146:f64d43ff0c18 | 8324 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8325 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8326 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8327 | * |
mbed_official | 146:f64d43ff0c18 | 8328 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8329 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8330 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8331 | */ |
mbed_official | 146:f64d43ff0c18 | 8332 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8333 | #define BP_AIPS_PACRJ_WP6 (5U) //!< Bit position for AIPS_PACRJ_WP6. |
mbed_official | 146:f64d43ff0c18 | 8334 | #define BM_AIPS_PACRJ_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRJ_WP6. |
mbed_official | 146:f64d43ff0c18 | 8335 | #define BS_AIPS_PACRJ_WP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP6. |
mbed_official | 146:f64d43ff0c18 | 8336 | |
mbed_official | 146:f64d43ff0c18 | 8337 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8338 | //! @brief Read current value of the AIPS_PACRJ_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 8339 | #define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6)) |
mbed_official | 146:f64d43ff0c18 | 8340 | #endif |
mbed_official | 146:f64d43ff0c18 | 8341 | |
mbed_official | 146:f64d43ff0c18 | 8342 | //! @brief Format value for bitfield AIPS_PACRJ_WP6. |
mbed_official | 146:f64d43ff0c18 | 8343 | #define BF_AIPS_PACRJ_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP6), uint32_t) & BM_AIPS_PACRJ_WP6) |
mbed_official | 146:f64d43ff0c18 | 8344 | |
mbed_official | 146:f64d43ff0c18 | 8345 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8346 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8347 | #define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8348 | #endif |
mbed_official | 146:f64d43ff0c18 | 8349 | //@} |
mbed_official | 146:f64d43ff0c18 | 8350 | |
mbed_official | 146:f64d43ff0c18 | 8351 | /*! |
mbed_official | 146:f64d43ff0c18 | 8352 | * @name Register AIPS_PACRJ, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 8353 | * |
mbed_official | 146:f64d43ff0c18 | 8354 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8355 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8356 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 8357 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8358 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8359 | * |
mbed_official | 146:f64d43ff0c18 | 8360 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8361 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8362 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8363 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8364 | */ |
mbed_official | 146:f64d43ff0c18 | 8365 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8366 | #define BP_AIPS_PACRJ_SP6 (6U) //!< Bit position for AIPS_PACRJ_SP6. |
mbed_official | 146:f64d43ff0c18 | 8367 | #define BM_AIPS_PACRJ_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRJ_SP6. |
mbed_official | 146:f64d43ff0c18 | 8368 | #define BS_AIPS_PACRJ_SP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP6. |
mbed_official | 146:f64d43ff0c18 | 8369 | |
mbed_official | 146:f64d43ff0c18 | 8370 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8371 | //! @brief Read current value of the AIPS_PACRJ_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 8372 | #define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6)) |
mbed_official | 146:f64d43ff0c18 | 8373 | #endif |
mbed_official | 146:f64d43ff0c18 | 8374 | |
mbed_official | 146:f64d43ff0c18 | 8375 | //! @brief Format value for bitfield AIPS_PACRJ_SP6. |
mbed_official | 146:f64d43ff0c18 | 8376 | #define BF_AIPS_PACRJ_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP6), uint32_t) & BM_AIPS_PACRJ_SP6) |
mbed_official | 146:f64d43ff0c18 | 8377 | |
mbed_official | 146:f64d43ff0c18 | 8378 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8379 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8380 | #define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8381 | #endif |
mbed_official | 146:f64d43ff0c18 | 8382 | //@} |
mbed_official | 146:f64d43ff0c18 | 8383 | |
mbed_official | 146:f64d43ff0c18 | 8384 | /*! |
mbed_official | 146:f64d43ff0c18 | 8385 | * @name Register AIPS_PACRJ, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 8386 | * |
mbed_official | 146:f64d43ff0c18 | 8387 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8388 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8389 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8390 | * |
mbed_official | 146:f64d43ff0c18 | 8391 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8392 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8393 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8394 | */ |
mbed_official | 146:f64d43ff0c18 | 8395 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8396 | #define BP_AIPS_PACRJ_TP5 (8U) //!< Bit position for AIPS_PACRJ_TP5. |
mbed_official | 146:f64d43ff0c18 | 8397 | #define BM_AIPS_PACRJ_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRJ_TP5. |
mbed_official | 146:f64d43ff0c18 | 8398 | #define BS_AIPS_PACRJ_TP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP5. |
mbed_official | 146:f64d43ff0c18 | 8399 | |
mbed_official | 146:f64d43ff0c18 | 8400 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8401 | //! @brief Read current value of the AIPS_PACRJ_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 8402 | #define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5)) |
mbed_official | 146:f64d43ff0c18 | 8403 | #endif |
mbed_official | 146:f64d43ff0c18 | 8404 | |
mbed_official | 146:f64d43ff0c18 | 8405 | //! @brief Format value for bitfield AIPS_PACRJ_TP5. |
mbed_official | 146:f64d43ff0c18 | 8406 | #define BF_AIPS_PACRJ_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP5), uint32_t) & BM_AIPS_PACRJ_TP5) |
mbed_official | 146:f64d43ff0c18 | 8407 | |
mbed_official | 146:f64d43ff0c18 | 8408 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8409 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8410 | #define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8411 | #endif |
mbed_official | 146:f64d43ff0c18 | 8412 | //@} |
mbed_official | 146:f64d43ff0c18 | 8413 | |
mbed_official | 146:f64d43ff0c18 | 8414 | /*! |
mbed_official | 146:f64d43ff0c18 | 8415 | * @name Register AIPS_PACRJ, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 8416 | * |
mbed_official | 146:f64d43ff0c18 | 8417 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8418 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8419 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8420 | * |
mbed_official | 146:f64d43ff0c18 | 8421 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8422 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8423 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8424 | */ |
mbed_official | 146:f64d43ff0c18 | 8425 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8426 | #define BP_AIPS_PACRJ_WP5 (9U) //!< Bit position for AIPS_PACRJ_WP5. |
mbed_official | 146:f64d43ff0c18 | 8427 | #define BM_AIPS_PACRJ_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRJ_WP5. |
mbed_official | 146:f64d43ff0c18 | 8428 | #define BS_AIPS_PACRJ_WP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP5. |
mbed_official | 146:f64d43ff0c18 | 8429 | |
mbed_official | 146:f64d43ff0c18 | 8430 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8431 | //! @brief Read current value of the AIPS_PACRJ_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 8432 | #define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5)) |
mbed_official | 146:f64d43ff0c18 | 8433 | #endif |
mbed_official | 146:f64d43ff0c18 | 8434 | |
mbed_official | 146:f64d43ff0c18 | 8435 | //! @brief Format value for bitfield AIPS_PACRJ_WP5. |
mbed_official | 146:f64d43ff0c18 | 8436 | #define BF_AIPS_PACRJ_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP5), uint32_t) & BM_AIPS_PACRJ_WP5) |
mbed_official | 146:f64d43ff0c18 | 8437 | |
mbed_official | 146:f64d43ff0c18 | 8438 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8439 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8440 | #define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8441 | #endif |
mbed_official | 146:f64d43ff0c18 | 8442 | //@} |
mbed_official | 146:f64d43ff0c18 | 8443 | |
mbed_official | 146:f64d43ff0c18 | 8444 | /*! |
mbed_official | 146:f64d43ff0c18 | 8445 | * @name Register AIPS_PACRJ, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 8446 | * |
mbed_official | 146:f64d43ff0c18 | 8447 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8448 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8449 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 8450 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8451 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8452 | * |
mbed_official | 146:f64d43ff0c18 | 8453 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8454 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8455 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8456 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8457 | */ |
mbed_official | 146:f64d43ff0c18 | 8458 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8459 | #define BP_AIPS_PACRJ_SP5 (10U) //!< Bit position for AIPS_PACRJ_SP5. |
mbed_official | 146:f64d43ff0c18 | 8460 | #define BM_AIPS_PACRJ_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRJ_SP5. |
mbed_official | 146:f64d43ff0c18 | 8461 | #define BS_AIPS_PACRJ_SP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP5. |
mbed_official | 146:f64d43ff0c18 | 8462 | |
mbed_official | 146:f64d43ff0c18 | 8463 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8464 | //! @brief Read current value of the AIPS_PACRJ_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 8465 | #define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5)) |
mbed_official | 146:f64d43ff0c18 | 8466 | #endif |
mbed_official | 146:f64d43ff0c18 | 8467 | |
mbed_official | 146:f64d43ff0c18 | 8468 | //! @brief Format value for bitfield AIPS_PACRJ_SP5. |
mbed_official | 146:f64d43ff0c18 | 8469 | #define BF_AIPS_PACRJ_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP5), uint32_t) & BM_AIPS_PACRJ_SP5) |
mbed_official | 146:f64d43ff0c18 | 8470 | |
mbed_official | 146:f64d43ff0c18 | 8471 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8472 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8473 | #define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8474 | #endif |
mbed_official | 146:f64d43ff0c18 | 8475 | //@} |
mbed_official | 146:f64d43ff0c18 | 8476 | |
mbed_official | 146:f64d43ff0c18 | 8477 | /*! |
mbed_official | 146:f64d43ff0c18 | 8478 | * @name Register AIPS_PACRJ, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 8479 | * |
mbed_official | 146:f64d43ff0c18 | 8480 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8481 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8482 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8483 | * |
mbed_official | 146:f64d43ff0c18 | 8484 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8485 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8486 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8487 | */ |
mbed_official | 146:f64d43ff0c18 | 8488 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8489 | #define BP_AIPS_PACRJ_TP4 (12U) //!< Bit position for AIPS_PACRJ_TP4. |
mbed_official | 146:f64d43ff0c18 | 8490 | #define BM_AIPS_PACRJ_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRJ_TP4. |
mbed_official | 146:f64d43ff0c18 | 8491 | #define BS_AIPS_PACRJ_TP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP4. |
mbed_official | 146:f64d43ff0c18 | 8492 | |
mbed_official | 146:f64d43ff0c18 | 8493 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8494 | //! @brief Read current value of the AIPS_PACRJ_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 8495 | #define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4)) |
mbed_official | 146:f64d43ff0c18 | 8496 | #endif |
mbed_official | 146:f64d43ff0c18 | 8497 | |
mbed_official | 146:f64d43ff0c18 | 8498 | //! @brief Format value for bitfield AIPS_PACRJ_TP4. |
mbed_official | 146:f64d43ff0c18 | 8499 | #define BF_AIPS_PACRJ_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP4), uint32_t) & BM_AIPS_PACRJ_TP4) |
mbed_official | 146:f64d43ff0c18 | 8500 | |
mbed_official | 146:f64d43ff0c18 | 8501 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8502 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8503 | #define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8504 | #endif |
mbed_official | 146:f64d43ff0c18 | 8505 | //@} |
mbed_official | 146:f64d43ff0c18 | 8506 | |
mbed_official | 146:f64d43ff0c18 | 8507 | /*! |
mbed_official | 146:f64d43ff0c18 | 8508 | * @name Register AIPS_PACRJ, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 8509 | * |
mbed_official | 146:f64d43ff0c18 | 8510 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8511 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8512 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8513 | * |
mbed_official | 146:f64d43ff0c18 | 8514 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8515 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8516 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8517 | */ |
mbed_official | 146:f64d43ff0c18 | 8518 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8519 | #define BP_AIPS_PACRJ_WP4 (13U) //!< Bit position for AIPS_PACRJ_WP4. |
mbed_official | 146:f64d43ff0c18 | 8520 | #define BM_AIPS_PACRJ_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRJ_WP4. |
mbed_official | 146:f64d43ff0c18 | 8521 | #define BS_AIPS_PACRJ_WP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP4. |
mbed_official | 146:f64d43ff0c18 | 8522 | |
mbed_official | 146:f64d43ff0c18 | 8523 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8524 | //! @brief Read current value of the AIPS_PACRJ_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 8525 | #define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4)) |
mbed_official | 146:f64d43ff0c18 | 8526 | #endif |
mbed_official | 146:f64d43ff0c18 | 8527 | |
mbed_official | 146:f64d43ff0c18 | 8528 | //! @brief Format value for bitfield AIPS_PACRJ_WP4. |
mbed_official | 146:f64d43ff0c18 | 8529 | #define BF_AIPS_PACRJ_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP4), uint32_t) & BM_AIPS_PACRJ_WP4) |
mbed_official | 146:f64d43ff0c18 | 8530 | |
mbed_official | 146:f64d43ff0c18 | 8531 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8532 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8533 | #define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8534 | #endif |
mbed_official | 146:f64d43ff0c18 | 8535 | //@} |
mbed_official | 146:f64d43ff0c18 | 8536 | |
mbed_official | 146:f64d43ff0c18 | 8537 | /*! |
mbed_official | 146:f64d43ff0c18 | 8538 | * @name Register AIPS_PACRJ, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 8539 | * |
mbed_official | 146:f64d43ff0c18 | 8540 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8541 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8542 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 8543 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 8544 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 8545 | * |
mbed_official | 146:f64d43ff0c18 | 8546 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8547 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8548 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8549 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8550 | */ |
mbed_official | 146:f64d43ff0c18 | 8551 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8552 | #define BP_AIPS_PACRJ_SP4 (14U) //!< Bit position for AIPS_PACRJ_SP4. |
mbed_official | 146:f64d43ff0c18 | 8553 | #define BM_AIPS_PACRJ_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRJ_SP4. |
mbed_official | 146:f64d43ff0c18 | 8554 | #define BS_AIPS_PACRJ_SP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP4. |
mbed_official | 146:f64d43ff0c18 | 8555 | |
mbed_official | 146:f64d43ff0c18 | 8556 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8557 | //! @brief Read current value of the AIPS_PACRJ_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 8558 | #define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4)) |
mbed_official | 146:f64d43ff0c18 | 8559 | #endif |
mbed_official | 146:f64d43ff0c18 | 8560 | |
mbed_official | 146:f64d43ff0c18 | 8561 | //! @brief Format value for bitfield AIPS_PACRJ_SP4. |
mbed_official | 146:f64d43ff0c18 | 8562 | #define BF_AIPS_PACRJ_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP4), uint32_t) & BM_AIPS_PACRJ_SP4) |
mbed_official | 146:f64d43ff0c18 | 8563 | |
mbed_official | 146:f64d43ff0c18 | 8564 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8565 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8566 | #define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8567 | #endif |
mbed_official | 146:f64d43ff0c18 | 8568 | //@} |
mbed_official | 146:f64d43ff0c18 | 8569 | |
mbed_official | 146:f64d43ff0c18 | 8570 | /*! |
mbed_official | 146:f64d43ff0c18 | 8571 | * @name Register AIPS_PACRJ, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 8572 | * |
mbed_official | 146:f64d43ff0c18 | 8573 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8574 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8575 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8576 | * |
mbed_official | 146:f64d43ff0c18 | 8577 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8578 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8579 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8580 | */ |
mbed_official | 146:f64d43ff0c18 | 8581 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8582 | #define BP_AIPS_PACRJ_TP3 (16U) //!< Bit position for AIPS_PACRJ_TP3. |
mbed_official | 146:f64d43ff0c18 | 8583 | #define BM_AIPS_PACRJ_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRJ_TP3. |
mbed_official | 146:f64d43ff0c18 | 8584 | #define BS_AIPS_PACRJ_TP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP3. |
mbed_official | 146:f64d43ff0c18 | 8585 | |
mbed_official | 146:f64d43ff0c18 | 8586 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8587 | //! @brief Read current value of the AIPS_PACRJ_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 8588 | #define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3)) |
mbed_official | 146:f64d43ff0c18 | 8589 | #endif |
mbed_official | 146:f64d43ff0c18 | 8590 | |
mbed_official | 146:f64d43ff0c18 | 8591 | //! @brief Format value for bitfield AIPS_PACRJ_TP3. |
mbed_official | 146:f64d43ff0c18 | 8592 | #define BF_AIPS_PACRJ_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP3), uint32_t) & BM_AIPS_PACRJ_TP3) |
mbed_official | 146:f64d43ff0c18 | 8593 | |
mbed_official | 146:f64d43ff0c18 | 8594 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8595 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8596 | #define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8597 | #endif |
mbed_official | 146:f64d43ff0c18 | 8598 | //@} |
mbed_official | 146:f64d43ff0c18 | 8599 | |
mbed_official | 146:f64d43ff0c18 | 8600 | /*! |
mbed_official | 146:f64d43ff0c18 | 8601 | * @name Register AIPS_PACRJ, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 8602 | * |
mbed_official | 146:f64d43ff0c18 | 8603 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 8604 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 8605 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8606 | * |
mbed_official | 146:f64d43ff0c18 | 8607 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8608 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8609 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8610 | */ |
mbed_official | 146:f64d43ff0c18 | 8611 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8612 | #define BP_AIPS_PACRJ_WP3 (17U) //!< Bit position for AIPS_PACRJ_WP3. |
mbed_official | 146:f64d43ff0c18 | 8613 | #define BM_AIPS_PACRJ_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRJ_WP3. |
mbed_official | 146:f64d43ff0c18 | 8614 | #define BS_AIPS_PACRJ_WP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP3. |
mbed_official | 146:f64d43ff0c18 | 8615 | |
mbed_official | 146:f64d43ff0c18 | 8616 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8617 | //! @brief Read current value of the AIPS_PACRJ_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 8618 | #define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3)) |
mbed_official | 146:f64d43ff0c18 | 8619 | #endif |
mbed_official | 146:f64d43ff0c18 | 8620 | |
mbed_official | 146:f64d43ff0c18 | 8621 | //! @brief Format value for bitfield AIPS_PACRJ_WP3. |
mbed_official | 146:f64d43ff0c18 | 8622 | #define BF_AIPS_PACRJ_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP3), uint32_t) & BM_AIPS_PACRJ_WP3) |
mbed_official | 146:f64d43ff0c18 | 8623 | |
mbed_official | 146:f64d43ff0c18 | 8624 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8625 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8626 | #define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8627 | #endif |
mbed_official | 146:f64d43ff0c18 | 8628 | //@} |
mbed_official | 146:f64d43ff0c18 | 8629 | |
mbed_official | 146:f64d43ff0c18 | 8630 | /*! |
mbed_official | 146:f64d43ff0c18 | 8631 | * @name Register AIPS_PACRJ, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 8632 | * |
mbed_official | 146:f64d43ff0c18 | 8633 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8634 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8635 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 8636 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8637 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8638 | * |
mbed_official | 146:f64d43ff0c18 | 8639 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8640 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8641 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8642 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8643 | */ |
mbed_official | 146:f64d43ff0c18 | 8644 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8645 | #define BP_AIPS_PACRJ_SP3 (18U) //!< Bit position for AIPS_PACRJ_SP3. |
mbed_official | 146:f64d43ff0c18 | 8646 | #define BM_AIPS_PACRJ_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRJ_SP3. |
mbed_official | 146:f64d43ff0c18 | 8647 | #define BS_AIPS_PACRJ_SP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP3. |
mbed_official | 146:f64d43ff0c18 | 8648 | |
mbed_official | 146:f64d43ff0c18 | 8649 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8650 | //! @brief Read current value of the AIPS_PACRJ_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 8651 | #define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3)) |
mbed_official | 146:f64d43ff0c18 | 8652 | #endif |
mbed_official | 146:f64d43ff0c18 | 8653 | |
mbed_official | 146:f64d43ff0c18 | 8654 | //! @brief Format value for bitfield AIPS_PACRJ_SP3. |
mbed_official | 146:f64d43ff0c18 | 8655 | #define BF_AIPS_PACRJ_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP3), uint32_t) & BM_AIPS_PACRJ_SP3) |
mbed_official | 146:f64d43ff0c18 | 8656 | |
mbed_official | 146:f64d43ff0c18 | 8657 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8658 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8659 | #define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8660 | #endif |
mbed_official | 146:f64d43ff0c18 | 8661 | //@} |
mbed_official | 146:f64d43ff0c18 | 8662 | |
mbed_official | 146:f64d43ff0c18 | 8663 | /*! |
mbed_official | 146:f64d43ff0c18 | 8664 | * @name Register AIPS_PACRJ, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 8665 | * |
mbed_official | 146:f64d43ff0c18 | 8666 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8667 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8668 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8669 | * |
mbed_official | 146:f64d43ff0c18 | 8670 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8671 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8672 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8673 | */ |
mbed_official | 146:f64d43ff0c18 | 8674 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8675 | #define BP_AIPS_PACRJ_TP2 (20U) //!< Bit position for AIPS_PACRJ_TP2. |
mbed_official | 146:f64d43ff0c18 | 8676 | #define BM_AIPS_PACRJ_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRJ_TP2. |
mbed_official | 146:f64d43ff0c18 | 8677 | #define BS_AIPS_PACRJ_TP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP2. |
mbed_official | 146:f64d43ff0c18 | 8678 | |
mbed_official | 146:f64d43ff0c18 | 8679 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8680 | //! @brief Read current value of the AIPS_PACRJ_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 8681 | #define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2)) |
mbed_official | 146:f64d43ff0c18 | 8682 | #endif |
mbed_official | 146:f64d43ff0c18 | 8683 | |
mbed_official | 146:f64d43ff0c18 | 8684 | //! @brief Format value for bitfield AIPS_PACRJ_TP2. |
mbed_official | 146:f64d43ff0c18 | 8685 | #define BF_AIPS_PACRJ_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP2), uint32_t) & BM_AIPS_PACRJ_TP2) |
mbed_official | 146:f64d43ff0c18 | 8686 | |
mbed_official | 146:f64d43ff0c18 | 8687 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8688 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8689 | #define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8690 | #endif |
mbed_official | 146:f64d43ff0c18 | 8691 | //@} |
mbed_official | 146:f64d43ff0c18 | 8692 | |
mbed_official | 146:f64d43ff0c18 | 8693 | /*! |
mbed_official | 146:f64d43ff0c18 | 8694 | * @name Register AIPS_PACRJ, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 8695 | * |
mbed_official | 146:f64d43ff0c18 | 8696 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8697 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8698 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8699 | * |
mbed_official | 146:f64d43ff0c18 | 8700 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8701 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8702 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8703 | */ |
mbed_official | 146:f64d43ff0c18 | 8704 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8705 | #define BP_AIPS_PACRJ_WP2 (21U) //!< Bit position for AIPS_PACRJ_WP2. |
mbed_official | 146:f64d43ff0c18 | 8706 | #define BM_AIPS_PACRJ_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRJ_WP2. |
mbed_official | 146:f64d43ff0c18 | 8707 | #define BS_AIPS_PACRJ_WP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP2. |
mbed_official | 146:f64d43ff0c18 | 8708 | |
mbed_official | 146:f64d43ff0c18 | 8709 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8710 | //! @brief Read current value of the AIPS_PACRJ_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 8711 | #define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2)) |
mbed_official | 146:f64d43ff0c18 | 8712 | #endif |
mbed_official | 146:f64d43ff0c18 | 8713 | |
mbed_official | 146:f64d43ff0c18 | 8714 | //! @brief Format value for bitfield AIPS_PACRJ_WP2. |
mbed_official | 146:f64d43ff0c18 | 8715 | #define BF_AIPS_PACRJ_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP2), uint32_t) & BM_AIPS_PACRJ_WP2) |
mbed_official | 146:f64d43ff0c18 | 8716 | |
mbed_official | 146:f64d43ff0c18 | 8717 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8718 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8719 | #define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8720 | #endif |
mbed_official | 146:f64d43ff0c18 | 8721 | //@} |
mbed_official | 146:f64d43ff0c18 | 8722 | |
mbed_official | 146:f64d43ff0c18 | 8723 | /*! |
mbed_official | 146:f64d43ff0c18 | 8724 | * @name Register AIPS_PACRJ, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 8725 | * |
mbed_official | 146:f64d43ff0c18 | 8726 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8727 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8728 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 8729 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 8730 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 8731 | * |
mbed_official | 146:f64d43ff0c18 | 8732 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8733 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8734 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8735 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8736 | */ |
mbed_official | 146:f64d43ff0c18 | 8737 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8738 | #define BP_AIPS_PACRJ_SP2 (22U) //!< Bit position for AIPS_PACRJ_SP2. |
mbed_official | 146:f64d43ff0c18 | 8739 | #define BM_AIPS_PACRJ_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRJ_SP2. |
mbed_official | 146:f64d43ff0c18 | 8740 | #define BS_AIPS_PACRJ_SP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP2. |
mbed_official | 146:f64d43ff0c18 | 8741 | |
mbed_official | 146:f64d43ff0c18 | 8742 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8743 | //! @brief Read current value of the AIPS_PACRJ_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 8744 | #define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2)) |
mbed_official | 146:f64d43ff0c18 | 8745 | #endif |
mbed_official | 146:f64d43ff0c18 | 8746 | |
mbed_official | 146:f64d43ff0c18 | 8747 | //! @brief Format value for bitfield AIPS_PACRJ_SP2. |
mbed_official | 146:f64d43ff0c18 | 8748 | #define BF_AIPS_PACRJ_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP2), uint32_t) & BM_AIPS_PACRJ_SP2) |
mbed_official | 146:f64d43ff0c18 | 8749 | |
mbed_official | 146:f64d43ff0c18 | 8750 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8751 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8752 | #define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8753 | #endif |
mbed_official | 146:f64d43ff0c18 | 8754 | //@} |
mbed_official | 146:f64d43ff0c18 | 8755 | |
mbed_official | 146:f64d43ff0c18 | 8756 | /*! |
mbed_official | 146:f64d43ff0c18 | 8757 | * @name Register AIPS_PACRJ, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 8758 | * |
mbed_official | 146:f64d43ff0c18 | 8759 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8760 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8761 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8762 | * |
mbed_official | 146:f64d43ff0c18 | 8763 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8764 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8765 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8766 | */ |
mbed_official | 146:f64d43ff0c18 | 8767 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8768 | #define BP_AIPS_PACRJ_TP1 (24U) //!< Bit position for AIPS_PACRJ_TP1. |
mbed_official | 146:f64d43ff0c18 | 8769 | #define BM_AIPS_PACRJ_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRJ_TP1. |
mbed_official | 146:f64d43ff0c18 | 8770 | #define BS_AIPS_PACRJ_TP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP1. |
mbed_official | 146:f64d43ff0c18 | 8771 | |
mbed_official | 146:f64d43ff0c18 | 8772 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8773 | //! @brief Read current value of the AIPS_PACRJ_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 8774 | #define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1)) |
mbed_official | 146:f64d43ff0c18 | 8775 | #endif |
mbed_official | 146:f64d43ff0c18 | 8776 | |
mbed_official | 146:f64d43ff0c18 | 8777 | //! @brief Format value for bitfield AIPS_PACRJ_TP1. |
mbed_official | 146:f64d43ff0c18 | 8778 | #define BF_AIPS_PACRJ_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP1), uint32_t) & BM_AIPS_PACRJ_TP1) |
mbed_official | 146:f64d43ff0c18 | 8779 | |
mbed_official | 146:f64d43ff0c18 | 8780 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8781 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8782 | #define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8783 | #endif |
mbed_official | 146:f64d43ff0c18 | 8784 | //@} |
mbed_official | 146:f64d43ff0c18 | 8785 | |
mbed_official | 146:f64d43ff0c18 | 8786 | /*! |
mbed_official | 146:f64d43ff0c18 | 8787 | * @name Register AIPS_PACRJ, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 8788 | * |
mbed_official | 146:f64d43ff0c18 | 8789 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8790 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8791 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8792 | * |
mbed_official | 146:f64d43ff0c18 | 8793 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8794 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8795 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8796 | */ |
mbed_official | 146:f64d43ff0c18 | 8797 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8798 | #define BP_AIPS_PACRJ_WP1 (25U) //!< Bit position for AIPS_PACRJ_WP1. |
mbed_official | 146:f64d43ff0c18 | 8799 | #define BM_AIPS_PACRJ_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRJ_WP1. |
mbed_official | 146:f64d43ff0c18 | 8800 | #define BS_AIPS_PACRJ_WP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP1. |
mbed_official | 146:f64d43ff0c18 | 8801 | |
mbed_official | 146:f64d43ff0c18 | 8802 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8803 | //! @brief Read current value of the AIPS_PACRJ_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 8804 | #define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1)) |
mbed_official | 146:f64d43ff0c18 | 8805 | #endif |
mbed_official | 146:f64d43ff0c18 | 8806 | |
mbed_official | 146:f64d43ff0c18 | 8807 | //! @brief Format value for bitfield AIPS_PACRJ_WP1. |
mbed_official | 146:f64d43ff0c18 | 8808 | #define BF_AIPS_PACRJ_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP1), uint32_t) & BM_AIPS_PACRJ_WP1) |
mbed_official | 146:f64d43ff0c18 | 8809 | |
mbed_official | 146:f64d43ff0c18 | 8810 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8811 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8812 | #define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8813 | #endif |
mbed_official | 146:f64d43ff0c18 | 8814 | //@} |
mbed_official | 146:f64d43ff0c18 | 8815 | |
mbed_official | 146:f64d43ff0c18 | 8816 | /*! |
mbed_official | 146:f64d43ff0c18 | 8817 | * @name Register AIPS_PACRJ, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 8818 | * |
mbed_official | 146:f64d43ff0c18 | 8819 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8820 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8821 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 8822 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8823 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8824 | * |
mbed_official | 146:f64d43ff0c18 | 8825 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8826 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8827 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8828 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8829 | */ |
mbed_official | 146:f64d43ff0c18 | 8830 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8831 | #define BP_AIPS_PACRJ_SP1 (26U) //!< Bit position for AIPS_PACRJ_SP1. |
mbed_official | 146:f64d43ff0c18 | 8832 | #define BM_AIPS_PACRJ_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRJ_SP1. |
mbed_official | 146:f64d43ff0c18 | 8833 | #define BS_AIPS_PACRJ_SP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP1. |
mbed_official | 146:f64d43ff0c18 | 8834 | |
mbed_official | 146:f64d43ff0c18 | 8835 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8836 | //! @brief Read current value of the AIPS_PACRJ_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 8837 | #define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1)) |
mbed_official | 146:f64d43ff0c18 | 8838 | #endif |
mbed_official | 146:f64d43ff0c18 | 8839 | |
mbed_official | 146:f64d43ff0c18 | 8840 | //! @brief Format value for bitfield AIPS_PACRJ_SP1. |
mbed_official | 146:f64d43ff0c18 | 8841 | #define BF_AIPS_PACRJ_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP1), uint32_t) & BM_AIPS_PACRJ_SP1) |
mbed_official | 146:f64d43ff0c18 | 8842 | |
mbed_official | 146:f64d43ff0c18 | 8843 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8844 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8845 | #define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8846 | #endif |
mbed_official | 146:f64d43ff0c18 | 8847 | //@} |
mbed_official | 146:f64d43ff0c18 | 8848 | |
mbed_official | 146:f64d43ff0c18 | 8849 | /*! |
mbed_official | 146:f64d43ff0c18 | 8850 | * @name Register AIPS_PACRJ, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 8851 | * |
mbed_official | 146:f64d43ff0c18 | 8852 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 8853 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 8854 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8855 | * |
mbed_official | 146:f64d43ff0c18 | 8856 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8857 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 8858 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 8859 | */ |
mbed_official | 146:f64d43ff0c18 | 8860 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8861 | #define BP_AIPS_PACRJ_TP0 (28U) //!< Bit position for AIPS_PACRJ_TP0. |
mbed_official | 146:f64d43ff0c18 | 8862 | #define BM_AIPS_PACRJ_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRJ_TP0. |
mbed_official | 146:f64d43ff0c18 | 8863 | #define BS_AIPS_PACRJ_TP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP0. |
mbed_official | 146:f64d43ff0c18 | 8864 | |
mbed_official | 146:f64d43ff0c18 | 8865 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8866 | //! @brief Read current value of the AIPS_PACRJ_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 8867 | #define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0)) |
mbed_official | 146:f64d43ff0c18 | 8868 | #endif |
mbed_official | 146:f64d43ff0c18 | 8869 | |
mbed_official | 146:f64d43ff0c18 | 8870 | //! @brief Format value for bitfield AIPS_PACRJ_TP0. |
mbed_official | 146:f64d43ff0c18 | 8871 | #define BF_AIPS_PACRJ_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP0), uint32_t) & BM_AIPS_PACRJ_TP0) |
mbed_official | 146:f64d43ff0c18 | 8872 | |
mbed_official | 146:f64d43ff0c18 | 8873 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8874 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8875 | #define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8876 | #endif |
mbed_official | 146:f64d43ff0c18 | 8877 | //@} |
mbed_official | 146:f64d43ff0c18 | 8878 | |
mbed_official | 146:f64d43ff0c18 | 8879 | /*! |
mbed_official | 146:f64d43ff0c18 | 8880 | * @name Register AIPS_PACRJ, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 8881 | * |
mbed_official | 146:f64d43ff0c18 | 8882 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 8883 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 8884 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 8885 | * |
mbed_official | 146:f64d43ff0c18 | 8886 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8887 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 8888 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 8889 | */ |
mbed_official | 146:f64d43ff0c18 | 8890 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8891 | #define BP_AIPS_PACRJ_WP0 (29U) //!< Bit position for AIPS_PACRJ_WP0. |
mbed_official | 146:f64d43ff0c18 | 8892 | #define BM_AIPS_PACRJ_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRJ_WP0. |
mbed_official | 146:f64d43ff0c18 | 8893 | #define BS_AIPS_PACRJ_WP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP0. |
mbed_official | 146:f64d43ff0c18 | 8894 | |
mbed_official | 146:f64d43ff0c18 | 8895 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8896 | //! @brief Read current value of the AIPS_PACRJ_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 8897 | #define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0)) |
mbed_official | 146:f64d43ff0c18 | 8898 | #endif |
mbed_official | 146:f64d43ff0c18 | 8899 | |
mbed_official | 146:f64d43ff0c18 | 8900 | //! @brief Format value for bitfield AIPS_PACRJ_WP0. |
mbed_official | 146:f64d43ff0c18 | 8901 | #define BF_AIPS_PACRJ_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP0), uint32_t) & BM_AIPS_PACRJ_WP0) |
mbed_official | 146:f64d43ff0c18 | 8902 | |
mbed_official | 146:f64d43ff0c18 | 8903 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8904 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8905 | #define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8906 | #endif |
mbed_official | 146:f64d43ff0c18 | 8907 | //@} |
mbed_official | 146:f64d43ff0c18 | 8908 | |
mbed_official | 146:f64d43ff0c18 | 8909 | /*! |
mbed_official | 146:f64d43ff0c18 | 8910 | * @name Register AIPS_PACRJ, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 8911 | * |
mbed_official | 146:f64d43ff0c18 | 8912 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8913 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 8914 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 8915 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 8916 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 8917 | * |
mbed_official | 146:f64d43ff0c18 | 8918 | * Values: |
mbed_official | 146:f64d43ff0c18 | 8919 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 8920 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 8921 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 8922 | */ |
mbed_official | 146:f64d43ff0c18 | 8923 | //@{ |
mbed_official | 146:f64d43ff0c18 | 8924 | #define BP_AIPS_PACRJ_SP0 (30U) //!< Bit position for AIPS_PACRJ_SP0. |
mbed_official | 146:f64d43ff0c18 | 8925 | #define BM_AIPS_PACRJ_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRJ_SP0. |
mbed_official | 146:f64d43ff0c18 | 8926 | #define BS_AIPS_PACRJ_SP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP0. |
mbed_official | 146:f64d43ff0c18 | 8927 | |
mbed_official | 146:f64d43ff0c18 | 8928 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8929 | //! @brief Read current value of the AIPS_PACRJ_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 8930 | #define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0)) |
mbed_official | 146:f64d43ff0c18 | 8931 | #endif |
mbed_official | 146:f64d43ff0c18 | 8932 | |
mbed_official | 146:f64d43ff0c18 | 8933 | //! @brief Format value for bitfield AIPS_PACRJ_SP0. |
mbed_official | 146:f64d43ff0c18 | 8934 | #define BF_AIPS_PACRJ_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP0), uint32_t) & BM_AIPS_PACRJ_SP0) |
mbed_official | 146:f64d43ff0c18 | 8935 | |
mbed_official | 146:f64d43ff0c18 | 8936 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8937 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 8938 | #define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 8939 | #endif |
mbed_official | 146:f64d43ff0c18 | 8940 | //@} |
mbed_official | 146:f64d43ff0c18 | 8941 | |
mbed_official | 146:f64d43ff0c18 | 8942 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 8943 | // HW_AIPS_PACRK - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 8944 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 8945 | |
mbed_official | 146:f64d43ff0c18 | 8946 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 8947 | /*! |
mbed_official | 146:f64d43ff0c18 | 8948 | * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 8949 | * |
mbed_official | 146:f64d43ff0c18 | 8950 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 8951 | * |
mbed_official | 146:f64d43ff0c18 | 8952 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 8953 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 8954 | * registers. |
mbed_official | 146:f64d43ff0c18 | 8955 | */ |
mbed_official | 146:f64d43ff0c18 | 8956 | typedef union _hw_aips_pacrk |
mbed_official | 146:f64d43ff0c18 | 8957 | { |
mbed_official | 146:f64d43ff0c18 | 8958 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 8959 | struct _hw_aips_pacrk_bitfields |
mbed_official | 146:f64d43ff0c18 | 8960 | { |
mbed_official | 146:f64d43ff0c18 | 8961 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8962 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8963 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8964 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 8965 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8966 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8967 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8968 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 8969 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8970 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8971 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8972 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 8973 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8974 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8975 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8976 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 8977 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8978 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8979 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8980 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 8981 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8982 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8983 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8984 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 8985 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8986 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8987 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8988 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 8989 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 8990 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 8991 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 8992 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 8993 | } B; |
mbed_official | 146:f64d43ff0c18 | 8994 | } hw_aips_pacrk_t; |
mbed_official | 146:f64d43ff0c18 | 8995 | #endif |
mbed_official | 146:f64d43ff0c18 | 8996 | |
mbed_official | 146:f64d43ff0c18 | 8997 | /*! |
mbed_official | 146:f64d43ff0c18 | 8998 | * @name Constants and macros for entire AIPS_PACRK register |
mbed_official | 146:f64d43ff0c18 | 8999 | */ |
mbed_official | 146:f64d43ff0c18 | 9000 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9001 | #define HW_AIPS_PACRK_ADDR(x) (REGS_AIPS_BASE(x) + 0x58U) |
mbed_official | 146:f64d43ff0c18 | 9002 | |
mbed_official | 146:f64d43ff0c18 | 9003 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9004 | #define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 9005 | #define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U) |
mbed_official | 146:f64d43ff0c18 | 9006 | #define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 9007 | #define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 9008 | #define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 9009 | #define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 9010 | #endif |
mbed_official | 146:f64d43ff0c18 | 9011 | //@} |
mbed_official | 146:f64d43ff0c18 | 9012 | |
mbed_official | 146:f64d43ff0c18 | 9013 | /* |
mbed_official | 146:f64d43ff0c18 | 9014 | * Constants & macros for individual AIPS_PACRK bitfields |
mbed_official | 146:f64d43ff0c18 | 9015 | */ |
mbed_official | 146:f64d43ff0c18 | 9016 | |
mbed_official | 146:f64d43ff0c18 | 9017 | /*! |
mbed_official | 146:f64d43ff0c18 | 9018 | * @name Register AIPS_PACRK, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 9019 | * |
mbed_official | 146:f64d43ff0c18 | 9020 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9021 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9022 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9023 | * |
mbed_official | 146:f64d43ff0c18 | 9024 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9025 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9026 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9027 | */ |
mbed_official | 146:f64d43ff0c18 | 9028 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9029 | #define BP_AIPS_PACRK_TP7 (0U) //!< Bit position for AIPS_PACRK_TP7. |
mbed_official | 146:f64d43ff0c18 | 9030 | #define BM_AIPS_PACRK_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRK_TP7. |
mbed_official | 146:f64d43ff0c18 | 9031 | #define BS_AIPS_PACRK_TP7 (1U) //!< Bit field size in bits for AIPS_PACRK_TP7. |
mbed_official | 146:f64d43ff0c18 | 9032 | |
mbed_official | 146:f64d43ff0c18 | 9033 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9034 | //! @brief Read current value of the AIPS_PACRK_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 9035 | #define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7)) |
mbed_official | 146:f64d43ff0c18 | 9036 | #endif |
mbed_official | 146:f64d43ff0c18 | 9037 | |
mbed_official | 146:f64d43ff0c18 | 9038 | //! @brief Format value for bitfield AIPS_PACRK_TP7. |
mbed_official | 146:f64d43ff0c18 | 9039 | #define BF_AIPS_PACRK_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP7), uint32_t) & BM_AIPS_PACRK_TP7) |
mbed_official | 146:f64d43ff0c18 | 9040 | |
mbed_official | 146:f64d43ff0c18 | 9041 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9042 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9043 | #define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9044 | #endif |
mbed_official | 146:f64d43ff0c18 | 9045 | //@} |
mbed_official | 146:f64d43ff0c18 | 9046 | |
mbed_official | 146:f64d43ff0c18 | 9047 | /*! |
mbed_official | 146:f64d43ff0c18 | 9048 | * @name Register AIPS_PACRK, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 9049 | * |
mbed_official | 146:f64d43ff0c18 | 9050 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9051 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9052 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9053 | * |
mbed_official | 146:f64d43ff0c18 | 9054 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9055 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9056 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9057 | */ |
mbed_official | 146:f64d43ff0c18 | 9058 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9059 | #define BP_AIPS_PACRK_WP7 (1U) //!< Bit position for AIPS_PACRK_WP7. |
mbed_official | 146:f64d43ff0c18 | 9060 | #define BM_AIPS_PACRK_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRK_WP7. |
mbed_official | 146:f64d43ff0c18 | 9061 | #define BS_AIPS_PACRK_WP7 (1U) //!< Bit field size in bits for AIPS_PACRK_WP7. |
mbed_official | 146:f64d43ff0c18 | 9062 | |
mbed_official | 146:f64d43ff0c18 | 9063 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9064 | //! @brief Read current value of the AIPS_PACRK_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 9065 | #define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7)) |
mbed_official | 146:f64d43ff0c18 | 9066 | #endif |
mbed_official | 146:f64d43ff0c18 | 9067 | |
mbed_official | 146:f64d43ff0c18 | 9068 | //! @brief Format value for bitfield AIPS_PACRK_WP7. |
mbed_official | 146:f64d43ff0c18 | 9069 | #define BF_AIPS_PACRK_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP7), uint32_t) & BM_AIPS_PACRK_WP7) |
mbed_official | 146:f64d43ff0c18 | 9070 | |
mbed_official | 146:f64d43ff0c18 | 9071 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9072 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9073 | #define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9074 | #endif |
mbed_official | 146:f64d43ff0c18 | 9075 | //@} |
mbed_official | 146:f64d43ff0c18 | 9076 | |
mbed_official | 146:f64d43ff0c18 | 9077 | /*! |
mbed_official | 146:f64d43ff0c18 | 9078 | * @name Register AIPS_PACRK, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 9079 | * |
mbed_official | 146:f64d43ff0c18 | 9080 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9081 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9082 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9083 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9084 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9085 | * |
mbed_official | 146:f64d43ff0c18 | 9086 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9087 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9088 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9089 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9090 | */ |
mbed_official | 146:f64d43ff0c18 | 9091 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9092 | #define BP_AIPS_PACRK_SP7 (2U) //!< Bit position for AIPS_PACRK_SP7. |
mbed_official | 146:f64d43ff0c18 | 9093 | #define BM_AIPS_PACRK_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRK_SP7. |
mbed_official | 146:f64d43ff0c18 | 9094 | #define BS_AIPS_PACRK_SP7 (1U) //!< Bit field size in bits for AIPS_PACRK_SP7. |
mbed_official | 146:f64d43ff0c18 | 9095 | |
mbed_official | 146:f64d43ff0c18 | 9096 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9097 | //! @brief Read current value of the AIPS_PACRK_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 9098 | #define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7)) |
mbed_official | 146:f64d43ff0c18 | 9099 | #endif |
mbed_official | 146:f64d43ff0c18 | 9100 | |
mbed_official | 146:f64d43ff0c18 | 9101 | //! @brief Format value for bitfield AIPS_PACRK_SP7. |
mbed_official | 146:f64d43ff0c18 | 9102 | #define BF_AIPS_PACRK_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP7), uint32_t) & BM_AIPS_PACRK_SP7) |
mbed_official | 146:f64d43ff0c18 | 9103 | |
mbed_official | 146:f64d43ff0c18 | 9104 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9105 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9106 | #define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9107 | #endif |
mbed_official | 146:f64d43ff0c18 | 9108 | //@} |
mbed_official | 146:f64d43ff0c18 | 9109 | |
mbed_official | 146:f64d43ff0c18 | 9110 | /*! |
mbed_official | 146:f64d43ff0c18 | 9111 | * @name Register AIPS_PACRK, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 9112 | * |
mbed_official | 146:f64d43ff0c18 | 9113 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9114 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9115 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9116 | * |
mbed_official | 146:f64d43ff0c18 | 9117 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9118 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9119 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9120 | */ |
mbed_official | 146:f64d43ff0c18 | 9121 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9122 | #define BP_AIPS_PACRK_TP6 (4U) //!< Bit position for AIPS_PACRK_TP6. |
mbed_official | 146:f64d43ff0c18 | 9123 | #define BM_AIPS_PACRK_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRK_TP6. |
mbed_official | 146:f64d43ff0c18 | 9124 | #define BS_AIPS_PACRK_TP6 (1U) //!< Bit field size in bits for AIPS_PACRK_TP6. |
mbed_official | 146:f64d43ff0c18 | 9125 | |
mbed_official | 146:f64d43ff0c18 | 9126 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9127 | //! @brief Read current value of the AIPS_PACRK_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 9128 | #define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6)) |
mbed_official | 146:f64d43ff0c18 | 9129 | #endif |
mbed_official | 146:f64d43ff0c18 | 9130 | |
mbed_official | 146:f64d43ff0c18 | 9131 | //! @brief Format value for bitfield AIPS_PACRK_TP6. |
mbed_official | 146:f64d43ff0c18 | 9132 | #define BF_AIPS_PACRK_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP6), uint32_t) & BM_AIPS_PACRK_TP6) |
mbed_official | 146:f64d43ff0c18 | 9133 | |
mbed_official | 146:f64d43ff0c18 | 9134 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9135 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9136 | #define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9137 | #endif |
mbed_official | 146:f64d43ff0c18 | 9138 | //@} |
mbed_official | 146:f64d43ff0c18 | 9139 | |
mbed_official | 146:f64d43ff0c18 | 9140 | /*! |
mbed_official | 146:f64d43ff0c18 | 9141 | * @name Register AIPS_PACRK, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 9142 | * |
mbed_official | 146:f64d43ff0c18 | 9143 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9144 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9145 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9146 | * |
mbed_official | 146:f64d43ff0c18 | 9147 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9148 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9149 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9150 | */ |
mbed_official | 146:f64d43ff0c18 | 9151 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9152 | #define BP_AIPS_PACRK_WP6 (5U) //!< Bit position for AIPS_PACRK_WP6. |
mbed_official | 146:f64d43ff0c18 | 9153 | #define BM_AIPS_PACRK_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRK_WP6. |
mbed_official | 146:f64d43ff0c18 | 9154 | #define BS_AIPS_PACRK_WP6 (1U) //!< Bit field size in bits for AIPS_PACRK_WP6. |
mbed_official | 146:f64d43ff0c18 | 9155 | |
mbed_official | 146:f64d43ff0c18 | 9156 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9157 | //! @brief Read current value of the AIPS_PACRK_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 9158 | #define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6)) |
mbed_official | 146:f64d43ff0c18 | 9159 | #endif |
mbed_official | 146:f64d43ff0c18 | 9160 | |
mbed_official | 146:f64d43ff0c18 | 9161 | //! @brief Format value for bitfield AIPS_PACRK_WP6. |
mbed_official | 146:f64d43ff0c18 | 9162 | #define BF_AIPS_PACRK_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP6), uint32_t) & BM_AIPS_PACRK_WP6) |
mbed_official | 146:f64d43ff0c18 | 9163 | |
mbed_official | 146:f64d43ff0c18 | 9164 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9165 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9166 | #define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9167 | #endif |
mbed_official | 146:f64d43ff0c18 | 9168 | //@} |
mbed_official | 146:f64d43ff0c18 | 9169 | |
mbed_official | 146:f64d43ff0c18 | 9170 | /*! |
mbed_official | 146:f64d43ff0c18 | 9171 | * @name Register AIPS_PACRK, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 9172 | * |
mbed_official | 146:f64d43ff0c18 | 9173 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9174 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9175 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9176 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9177 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9178 | * |
mbed_official | 146:f64d43ff0c18 | 9179 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9180 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9181 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9182 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9183 | */ |
mbed_official | 146:f64d43ff0c18 | 9184 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9185 | #define BP_AIPS_PACRK_SP6 (6U) //!< Bit position for AIPS_PACRK_SP6. |
mbed_official | 146:f64d43ff0c18 | 9186 | #define BM_AIPS_PACRK_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRK_SP6. |
mbed_official | 146:f64d43ff0c18 | 9187 | #define BS_AIPS_PACRK_SP6 (1U) //!< Bit field size in bits for AIPS_PACRK_SP6. |
mbed_official | 146:f64d43ff0c18 | 9188 | |
mbed_official | 146:f64d43ff0c18 | 9189 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9190 | //! @brief Read current value of the AIPS_PACRK_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 9191 | #define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6)) |
mbed_official | 146:f64d43ff0c18 | 9192 | #endif |
mbed_official | 146:f64d43ff0c18 | 9193 | |
mbed_official | 146:f64d43ff0c18 | 9194 | //! @brief Format value for bitfield AIPS_PACRK_SP6. |
mbed_official | 146:f64d43ff0c18 | 9195 | #define BF_AIPS_PACRK_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP6), uint32_t) & BM_AIPS_PACRK_SP6) |
mbed_official | 146:f64d43ff0c18 | 9196 | |
mbed_official | 146:f64d43ff0c18 | 9197 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9198 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9199 | #define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9200 | #endif |
mbed_official | 146:f64d43ff0c18 | 9201 | //@} |
mbed_official | 146:f64d43ff0c18 | 9202 | |
mbed_official | 146:f64d43ff0c18 | 9203 | /*! |
mbed_official | 146:f64d43ff0c18 | 9204 | * @name Register AIPS_PACRK, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 9205 | * |
mbed_official | 146:f64d43ff0c18 | 9206 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9207 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9208 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9209 | * |
mbed_official | 146:f64d43ff0c18 | 9210 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9211 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9212 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9213 | */ |
mbed_official | 146:f64d43ff0c18 | 9214 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9215 | #define BP_AIPS_PACRK_TP5 (8U) //!< Bit position for AIPS_PACRK_TP5. |
mbed_official | 146:f64d43ff0c18 | 9216 | #define BM_AIPS_PACRK_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRK_TP5. |
mbed_official | 146:f64d43ff0c18 | 9217 | #define BS_AIPS_PACRK_TP5 (1U) //!< Bit field size in bits for AIPS_PACRK_TP5. |
mbed_official | 146:f64d43ff0c18 | 9218 | |
mbed_official | 146:f64d43ff0c18 | 9219 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9220 | //! @brief Read current value of the AIPS_PACRK_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 9221 | #define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5)) |
mbed_official | 146:f64d43ff0c18 | 9222 | #endif |
mbed_official | 146:f64d43ff0c18 | 9223 | |
mbed_official | 146:f64d43ff0c18 | 9224 | //! @brief Format value for bitfield AIPS_PACRK_TP5. |
mbed_official | 146:f64d43ff0c18 | 9225 | #define BF_AIPS_PACRK_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP5), uint32_t) & BM_AIPS_PACRK_TP5) |
mbed_official | 146:f64d43ff0c18 | 9226 | |
mbed_official | 146:f64d43ff0c18 | 9227 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9228 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9229 | #define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9230 | #endif |
mbed_official | 146:f64d43ff0c18 | 9231 | //@} |
mbed_official | 146:f64d43ff0c18 | 9232 | |
mbed_official | 146:f64d43ff0c18 | 9233 | /*! |
mbed_official | 146:f64d43ff0c18 | 9234 | * @name Register AIPS_PACRK, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 9235 | * |
mbed_official | 146:f64d43ff0c18 | 9236 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9237 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9238 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9239 | * |
mbed_official | 146:f64d43ff0c18 | 9240 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9241 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9242 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9243 | */ |
mbed_official | 146:f64d43ff0c18 | 9244 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9245 | #define BP_AIPS_PACRK_WP5 (9U) //!< Bit position for AIPS_PACRK_WP5. |
mbed_official | 146:f64d43ff0c18 | 9246 | #define BM_AIPS_PACRK_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRK_WP5. |
mbed_official | 146:f64d43ff0c18 | 9247 | #define BS_AIPS_PACRK_WP5 (1U) //!< Bit field size in bits for AIPS_PACRK_WP5. |
mbed_official | 146:f64d43ff0c18 | 9248 | |
mbed_official | 146:f64d43ff0c18 | 9249 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9250 | //! @brief Read current value of the AIPS_PACRK_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 9251 | #define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5)) |
mbed_official | 146:f64d43ff0c18 | 9252 | #endif |
mbed_official | 146:f64d43ff0c18 | 9253 | |
mbed_official | 146:f64d43ff0c18 | 9254 | //! @brief Format value for bitfield AIPS_PACRK_WP5. |
mbed_official | 146:f64d43ff0c18 | 9255 | #define BF_AIPS_PACRK_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP5), uint32_t) & BM_AIPS_PACRK_WP5) |
mbed_official | 146:f64d43ff0c18 | 9256 | |
mbed_official | 146:f64d43ff0c18 | 9257 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9258 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9259 | #define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9260 | #endif |
mbed_official | 146:f64d43ff0c18 | 9261 | //@} |
mbed_official | 146:f64d43ff0c18 | 9262 | |
mbed_official | 146:f64d43ff0c18 | 9263 | /*! |
mbed_official | 146:f64d43ff0c18 | 9264 | * @name Register AIPS_PACRK, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 9265 | * |
mbed_official | 146:f64d43ff0c18 | 9266 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9267 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9268 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9269 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9270 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9271 | * |
mbed_official | 146:f64d43ff0c18 | 9272 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9273 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9274 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9275 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9276 | */ |
mbed_official | 146:f64d43ff0c18 | 9277 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9278 | #define BP_AIPS_PACRK_SP5 (10U) //!< Bit position for AIPS_PACRK_SP5. |
mbed_official | 146:f64d43ff0c18 | 9279 | #define BM_AIPS_PACRK_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRK_SP5. |
mbed_official | 146:f64d43ff0c18 | 9280 | #define BS_AIPS_PACRK_SP5 (1U) //!< Bit field size in bits for AIPS_PACRK_SP5. |
mbed_official | 146:f64d43ff0c18 | 9281 | |
mbed_official | 146:f64d43ff0c18 | 9282 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9283 | //! @brief Read current value of the AIPS_PACRK_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 9284 | #define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5)) |
mbed_official | 146:f64d43ff0c18 | 9285 | #endif |
mbed_official | 146:f64d43ff0c18 | 9286 | |
mbed_official | 146:f64d43ff0c18 | 9287 | //! @brief Format value for bitfield AIPS_PACRK_SP5. |
mbed_official | 146:f64d43ff0c18 | 9288 | #define BF_AIPS_PACRK_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP5), uint32_t) & BM_AIPS_PACRK_SP5) |
mbed_official | 146:f64d43ff0c18 | 9289 | |
mbed_official | 146:f64d43ff0c18 | 9290 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9291 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9292 | #define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9293 | #endif |
mbed_official | 146:f64d43ff0c18 | 9294 | //@} |
mbed_official | 146:f64d43ff0c18 | 9295 | |
mbed_official | 146:f64d43ff0c18 | 9296 | /*! |
mbed_official | 146:f64d43ff0c18 | 9297 | * @name Register AIPS_PACRK, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 9298 | * |
mbed_official | 146:f64d43ff0c18 | 9299 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9300 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9301 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9302 | * |
mbed_official | 146:f64d43ff0c18 | 9303 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9304 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9305 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9306 | */ |
mbed_official | 146:f64d43ff0c18 | 9307 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9308 | #define BP_AIPS_PACRK_TP4 (12U) //!< Bit position for AIPS_PACRK_TP4. |
mbed_official | 146:f64d43ff0c18 | 9309 | #define BM_AIPS_PACRK_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRK_TP4. |
mbed_official | 146:f64d43ff0c18 | 9310 | #define BS_AIPS_PACRK_TP4 (1U) //!< Bit field size in bits for AIPS_PACRK_TP4. |
mbed_official | 146:f64d43ff0c18 | 9311 | |
mbed_official | 146:f64d43ff0c18 | 9312 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9313 | //! @brief Read current value of the AIPS_PACRK_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 9314 | #define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4)) |
mbed_official | 146:f64d43ff0c18 | 9315 | #endif |
mbed_official | 146:f64d43ff0c18 | 9316 | |
mbed_official | 146:f64d43ff0c18 | 9317 | //! @brief Format value for bitfield AIPS_PACRK_TP4. |
mbed_official | 146:f64d43ff0c18 | 9318 | #define BF_AIPS_PACRK_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP4), uint32_t) & BM_AIPS_PACRK_TP4) |
mbed_official | 146:f64d43ff0c18 | 9319 | |
mbed_official | 146:f64d43ff0c18 | 9320 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9321 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9322 | #define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9323 | #endif |
mbed_official | 146:f64d43ff0c18 | 9324 | //@} |
mbed_official | 146:f64d43ff0c18 | 9325 | |
mbed_official | 146:f64d43ff0c18 | 9326 | /*! |
mbed_official | 146:f64d43ff0c18 | 9327 | * @name Register AIPS_PACRK, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 9328 | * |
mbed_official | 146:f64d43ff0c18 | 9329 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9330 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9331 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9332 | * |
mbed_official | 146:f64d43ff0c18 | 9333 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9334 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9335 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9336 | */ |
mbed_official | 146:f64d43ff0c18 | 9337 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9338 | #define BP_AIPS_PACRK_WP4 (13U) //!< Bit position for AIPS_PACRK_WP4. |
mbed_official | 146:f64d43ff0c18 | 9339 | #define BM_AIPS_PACRK_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRK_WP4. |
mbed_official | 146:f64d43ff0c18 | 9340 | #define BS_AIPS_PACRK_WP4 (1U) //!< Bit field size in bits for AIPS_PACRK_WP4. |
mbed_official | 146:f64d43ff0c18 | 9341 | |
mbed_official | 146:f64d43ff0c18 | 9342 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9343 | //! @brief Read current value of the AIPS_PACRK_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 9344 | #define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4)) |
mbed_official | 146:f64d43ff0c18 | 9345 | #endif |
mbed_official | 146:f64d43ff0c18 | 9346 | |
mbed_official | 146:f64d43ff0c18 | 9347 | //! @brief Format value for bitfield AIPS_PACRK_WP4. |
mbed_official | 146:f64d43ff0c18 | 9348 | #define BF_AIPS_PACRK_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP4), uint32_t) & BM_AIPS_PACRK_WP4) |
mbed_official | 146:f64d43ff0c18 | 9349 | |
mbed_official | 146:f64d43ff0c18 | 9350 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9351 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9352 | #define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9353 | #endif |
mbed_official | 146:f64d43ff0c18 | 9354 | //@} |
mbed_official | 146:f64d43ff0c18 | 9355 | |
mbed_official | 146:f64d43ff0c18 | 9356 | /*! |
mbed_official | 146:f64d43ff0c18 | 9357 | * @name Register AIPS_PACRK, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 9358 | * |
mbed_official | 146:f64d43ff0c18 | 9359 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9360 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9361 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 9362 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 9363 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 9364 | * |
mbed_official | 146:f64d43ff0c18 | 9365 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9366 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9367 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9368 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9369 | */ |
mbed_official | 146:f64d43ff0c18 | 9370 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9371 | #define BP_AIPS_PACRK_SP4 (14U) //!< Bit position for AIPS_PACRK_SP4. |
mbed_official | 146:f64d43ff0c18 | 9372 | #define BM_AIPS_PACRK_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRK_SP4. |
mbed_official | 146:f64d43ff0c18 | 9373 | #define BS_AIPS_PACRK_SP4 (1U) //!< Bit field size in bits for AIPS_PACRK_SP4. |
mbed_official | 146:f64d43ff0c18 | 9374 | |
mbed_official | 146:f64d43ff0c18 | 9375 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9376 | //! @brief Read current value of the AIPS_PACRK_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 9377 | #define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4)) |
mbed_official | 146:f64d43ff0c18 | 9378 | #endif |
mbed_official | 146:f64d43ff0c18 | 9379 | |
mbed_official | 146:f64d43ff0c18 | 9380 | //! @brief Format value for bitfield AIPS_PACRK_SP4. |
mbed_official | 146:f64d43ff0c18 | 9381 | #define BF_AIPS_PACRK_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP4), uint32_t) & BM_AIPS_PACRK_SP4) |
mbed_official | 146:f64d43ff0c18 | 9382 | |
mbed_official | 146:f64d43ff0c18 | 9383 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9384 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9385 | #define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9386 | #endif |
mbed_official | 146:f64d43ff0c18 | 9387 | //@} |
mbed_official | 146:f64d43ff0c18 | 9388 | |
mbed_official | 146:f64d43ff0c18 | 9389 | /*! |
mbed_official | 146:f64d43ff0c18 | 9390 | * @name Register AIPS_PACRK, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 9391 | * |
mbed_official | 146:f64d43ff0c18 | 9392 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9393 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9394 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9395 | * |
mbed_official | 146:f64d43ff0c18 | 9396 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9397 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9398 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9399 | */ |
mbed_official | 146:f64d43ff0c18 | 9400 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9401 | #define BP_AIPS_PACRK_TP3 (16U) //!< Bit position for AIPS_PACRK_TP3. |
mbed_official | 146:f64d43ff0c18 | 9402 | #define BM_AIPS_PACRK_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRK_TP3. |
mbed_official | 146:f64d43ff0c18 | 9403 | #define BS_AIPS_PACRK_TP3 (1U) //!< Bit field size in bits for AIPS_PACRK_TP3. |
mbed_official | 146:f64d43ff0c18 | 9404 | |
mbed_official | 146:f64d43ff0c18 | 9405 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9406 | //! @brief Read current value of the AIPS_PACRK_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 9407 | #define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3)) |
mbed_official | 146:f64d43ff0c18 | 9408 | #endif |
mbed_official | 146:f64d43ff0c18 | 9409 | |
mbed_official | 146:f64d43ff0c18 | 9410 | //! @brief Format value for bitfield AIPS_PACRK_TP3. |
mbed_official | 146:f64d43ff0c18 | 9411 | #define BF_AIPS_PACRK_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP3), uint32_t) & BM_AIPS_PACRK_TP3) |
mbed_official | 146:f64d43ff0c18 | 9412 | |
mbed_official | 146:f64d43ff0c18 | 9413 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9414 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9415 | #define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9416 | #endif |
mbed_official | 146:f64d43ff0c18 | 9417 | //@} |
mbed_official | 146:f64d43ff0c18 | 9418 | |
mbed_official | 146:f64d43ff0c18 | 9419 | /*! |
mbed_official | 146:f64d43ff0c18 | 9420 | * @name Register AIPS_PACRK, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 9421 | * |
mbed_official | 146:f64d43ff0c18 | 9422 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 9423 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 9424 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9425 | * |
mbed_official | 146:f64d43ff0c18 | 9426 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9427 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9428 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9429 | */ |
mbed_official | 146:f64d43ff0c18 | 9430 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9431 | #define BP_AIPS_PACRK_WP3 (17U) //!< Bit position for AIPS_PACRK_WP3. |
mbed_official | 146:f64d43ff0c18 | 9432 | #define BM_AIPS_PACRK_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRK_WP3. |
mbed_official | 146:f64d43ff0c18 | 9433 | #define BS_AIPS_PACRK_WP3 (1U) //!< Bit field size in bits for AIPS_PACRK_WP3. |
mbed_official | 146:f64d43ff0c18 | 9434 | |
mbed_official | 146:f64d43ff0c18 | 9435 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9436 | //! @brief Read current value of the AIPS_PACRK_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 9437 | #define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3)) |
mbed_official | 146:f64d43ff0c18 | 9438 | #endif |
mbed_official | 146:f64d43ff0c18 | 9439 | |
mbed_official | 146:f64d43ff0c18 | 9440 | //! @brief Format value for bitfield AIPS_PACRK_WP3. |
mbed_official | 146:f64d43ff0c18 | 9441 | #define BF_AIPS_PACRK_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP3), uint32_t) & BM_AIPS_PACRK_WP3) |
mbed_official | 146:f64d43ff0c18 | 9442 | |
mbed_official | 146:f64d43ff0c18 | 9443 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9444 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9445 | #define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9446 | #endif |
mbed_official | 146:f64d43ff0c18 | 9447 | //@} |
mbed_official | 146:f64d43ff0c18 | 9448 | |
mbed_official | 146:f64d43ff0c18 | 9449 | /*! |
mbed_official | 146:f64d43ff0c18 | 9450 | * @name Register AIPS_PACRK, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 9451 | * |
mbed_official | 146:f64d43ff0c18 | 9452 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9453 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9454 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9455 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9456 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9457 | * |
mbed_official | 146:f64d43ff0c18 | 9458 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9459 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9460 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9461 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9462 | */ |
mbed_official | 146:f64d43ff0c18 | 9463 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9464 | #define BP_AIPS_PACRK_SP3 (18U) //!< Bit position for AIPS_PACRK_SP3. |
mbed_official | 146:f64d43ff0c18 | 9465 | #define BM_AIPS_PACRK_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRK_SP3. |
mbed_official | 146:f64d43ff0c18 | 9466 | #define BS_AIPS_PACRK_SP3 (1U) //!< Bit field size in bits for AIPS_PACRK_SP3. |
mbed_official | 146:f64d43ff0c18 | 9467 | |
mbed_official | 146:f64d43ff0c18 | 9468 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9469 | //! @brief Read current value of the AIPS_PACRK_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 9470 | #define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3)) |
mbed_official | 146:f64d43ff0c18 | 9471 | #endif |
mbed_official | 146:f64d43ff0c18 | 9472 | |
mbed_official | 146:f64d43ff0c18 | 9473 | //! @brief Format value for bitfield AIPS_PACRK_SP3. |
mbed_official | 146:f64d43ff0c18 | 9474 | #define BF_AIPS_PACRK_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP3), uint32_t) & BM_AIPS_PACRK_SP3) |
mbed_official | 146:f64d43ff0c18 | 9475 | |
mbed_official | 146:f64d43ff0c18 | 9476 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9477 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9478 | #define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9479 | #endif |
mbed_official | 146:f64d43ff0c18 | 9480 | //@} |
mbed_official | 146:f64d43ff0c18 | 9481 | |
mbed_official | 146:f64d43ff0c18 | 9482 | /*! |
mbed_official | 146:f64d43ff0c18 | 9483 | * @name Register AIPS_PACRK, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 9484 | * |
mbed_official | 146:f64d43ff0c18 | 9485 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9486 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9487 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9488 | * |
mbed_official | 146:f64d43ff0c18 | 9489 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9490 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9491 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9492 | */ |
mbed_official | 146:f64d43ff0c18 | 9493 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9494 | #define BP_AIPS_PACRK_TP2 (20U) //!< Bit position for AIPS_PACRK_TP2. |
mbed_official | 146:f64d43ff0c18 | 9495 | #define BM_AIPS_PACRK_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRK_TP2. |
mbed_official | 146:f64d43ff0c18 | 9496 | #define BS_AIPS_PACRK_TP2 (1U) //!< Bit field size in bits for AIPS_PACRK_TP2. |
mbed_official | 146:f64d43ff0c18 | 9497 | |
mbed_official | 146:f64d43ff0c18 | 9498 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9499 | //! @brief Read current value of the AIPS_PACRK_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 9500 | #define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2)) |
mbed_official | 146:f64d43ff0c18 | 9501 | #endif |
mbed_official | 146:f64d43ff0c18 | 9502 | |
mbed_official | 146:f64d43ff0c18 | 9503 | //! @brief Format value for bitfield AIPS_PACRK_TP2. |
mbed_official | 146:f64d43ff0c18 | 9504 | #define BF_AIPS_PACRK_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP2), uint32_t) & BM_AIPS_PACRK_TP2) |
mbed_official | 146:f64d43ff0c18 | 9505 | |
mbed_official | 146:f64d43ff0c18 | 9506 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9507 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9508 | #define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9509 | #endif |
mbed_official | 146:f64d43ff0c18 | 9510 | //@} |
mbed_official | 146:f64d43ff0c18 | 9511 | |
mbed_official | 146:f64d43ff0c18 | 9512 | /*! |
mbed_official | 146:f64d43ff0c18 | 9513 | * @name Register AIPS_PACRK, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 9514 | * |
mbed_official | 146:f64d43ff0c18 | 9515 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9516 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9517 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9518 | * |
mbed_official | 146:f64d43ff0c18 | 9519 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9520 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9521 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9522 | */ |
mbed_official | 146:f64d43ff0c18 | 9523 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9524 | #define BP_AIPS_PACRK_WP2 (21U) //!< Bit position for AIPS_PACRK_WP2. |
mbed_official | 146:f64d43ff0c18 | 9525 | #define BM_AIPS_PACRK_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRK_WP2. |
mbed_official | 146:f64d43ff0c18 | 9526 | #define BS_AIPS_PACRK_WP2 (1U) //!< Bit field size in bits for AIPS_PACRK_WP2. |
mbed_official | 146:f64d43ff0c18 | 9527 | |
mbed_official | 146:f64d43ff0c18 | 9528 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9529 | //! @brief Read current value of the AIPS_PACRK_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 9530 | #define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2)) |
mbed_official | 146:f64d43ff0c18 | 9531 | #endif |
mbed_official | 146:f64d43ff0c18 | 9532 | |
mbed_official | 146:f64d43ff0c18 | 9533 | //! @brief Format value for bitfield AIPS_PACRK_WP2. |
mbed_official | 146:f64d43ff0c18 | 9534 | #define BF_AIPS_PACRK_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP2), uint32_t) & BM_AIPS_PACRK_WP2) |
mbed_official | 146:f64d43ff0c18 | 9535 | |
mbed_official | 146:f64d43ff0c18 | 9536 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9537 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9538 | #define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9539 | #endif |
mbed_official | 146:f64d43ff0c18 | 9540 | //@} |
mbed_official | 146:f64d43ff0c18 | 9541 | |
mbed_official | 146:f64d43ff0c18 | 9542 | /*! |
mbed_official | 146:f64d43ff0c18 | 9543 | * @name Register AIPS_PACRK, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 9544 | * |
mbed_official | 146:f64d43ff0c18 | 9545 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9546 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9547 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 9548 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 9549 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 9550 | * |
mbed_official | 146:f64d43ff0c18 | 9551 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9552 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9553 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9554 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9555 | */ |
mbed_official | 146:f64d43ff0c18 | 9556 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9557 | #define BP_AIPS_PACRK_SP2 (22U) //!< Bit position for AIPS_PACRK_SP2. |
mbed_official | 146:f64d43ff0c18 | 9558 | #define BM_AIPS_PACRK_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRK_SP2. |
mbed_official | 146:f64d43ff0c18 | 9559 | #define BS_AIPS_PACRK_SP2 (1U) //!< Bit field size in bits for AIPS_PACRK_SP2. |
mbed_official | 146:f64d43ff0c18 | 9560 | |
mbed_official | 146:f64d43ff0c18 | 9561 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9562 | //! @brief Read current value of the AIPS_PACRK_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 9563 | #define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2)) |
mbed_official | 146:f64d43ff0c18 | 9564 | #endif |
mbed_official | 146:f64d43ff0c18 | 9565 | |
mbed_official | 146:f64d43ff0c18 | 9566 | //! @brief Format value for bitfield AIPS_PACRK_SP2. |
mbed_official | 146:f64d43ff0c18 | 9567 | #define BF_AIPS_PACRK_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP2), uint32_t) & BM_AIPS_PACRK_SP2) |
mbed_official | 146:f64d43ff0c18 | 9568 | |
mbed_official | 146:f64d43ff0c18 | 9569 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9570 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9571 | #define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9572 | #endif |
mbed_official | 146:f64d43ff0c18 | 9573 | //@} |
mbed_official | 146:f64d43ff0c18 | 9574 | |
mbed_official | 146:f64d43ff0c18 | 9575 | /*! |
mbed_official | 146:f64d43ff0c18 | 9576 | * @name Register AIPS_PACRK, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 9577 | * |
mbed_official | 146:f64d43ff0c18 | 9578 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9579 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9580 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9581 | * |
mbed_official | 146:f64d43ff0c18 | 9582 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9583 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9584 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9585 | */ |
mbed_official | 146:f64d43ff0c18 | 9586 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9587 | #define BP_AIPS_PACRK_TP1 (24U) //!< Bit position for AIPS_PACRK_TP1. |
mbed_official | 146:f64d43ff0c18 | 9588 | #define BM_AIPS_PACRK_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRK_TP1. |
mbed_official | 146:f64d43ff0c18 | 9589 | #define BS_AIPS_PACRK_TP1 (1U) //!< Bit field size in bits for AIPS_PACRK_TP1. |
mbed_official | 146:f64d43ff0c18 | 9590 | |
mbed_official | 146:f64d43ff0c18 | 9591 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9592 | //! @brief Read current value of the AIPS_PACRK_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 9593 | #define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1)) |
mbed_official | 146:f64d43ff0c18 | 9594 | #endif |
mbed_official | 146:f64d43ff0c18 | 9595 | |
mbed_official | 146:f64d43ff0c18 | 9596 | //! @brief Format value for bitfield AIPS_PACRK_TP1. |
mbed_official | 146:f64d43ff0c18 | 9597 | #define BF_AIPS_PACRK_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP1), uint32_t) & BM_AIPS_PACRK_TP1) |
mbed_official | 146:f64d43ff0c18 | 9598 | |
mbed_official | 146:f64d43ff0c18 | 9599 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9600 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9601 | #define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9602 | #endif |
mbed_official | 146:f64d43ff0c18 | 9603 | //@} |
mbed_official | 146:f64d43ff0c18 | 9604 | |
mbed_official | 146:f64d43ff0c18 | 9605 | /*! |
mbed_official | 146:f64d43ff0c18 | 9606 | * @name Register AIPS_PACRK, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 9607 | * |
mbed_official | 146:f64d43ff0c18 | 9608 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9609 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9610 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9611 | * |
mbed_official | 146:f64d43ff0c18 | 9612 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9613 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9614 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9615 | */ |
mbed_official | 146:f64d43ff0c18 | 9616 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9617 | #define BP_AIPS_PACRK_WP1 (25U) //!< Bit position for AIPS_PACRK_WP1. |
mbed_official | 146:f64d43ff0c18 | 9618 | #define BM_AIPS_PACRK_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRK_WP1. |
mbed_official | 146:f64d43ff0c18 | 9619 | #define BS_AIPS_PACRK_WP1 (1U) //!< Bit field size in bits for AIPS_PACRK_WP1. |
mbed_official | 146:f64d43ff0c18 | 9620 | |
mbed_official | 146:f64d43ff0c18 | 9621 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9622 | //! @brief Read current value of the AIPS_PACRK_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 9623 | #define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1)) |
mbed_official | 146:f64d43ff0c18 | 9624 | #endif |
mbed_official | 146:f64d43ff0c18 | 9625 | |
mbed_official | 146:f64d43ff0c18 | 9626 | //! @brief Format value for bitfield AIPS_PACRK_WP1. |
mbed_official | 146:f64d43ff0c18 | 9627 | #define BF_AIPS_PACRK_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP1), uint32_t) & BM_AIPS_PACRK_WP1) |
mbed_official | 146:f64d43ff0c18 | 9628 | |
mbed_official | 146:f64d43ff0c18 | 9629 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9630 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9631 | #define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9632 | #endif |
mbed_official | 146:f64d43ff0c18 | 9633 | //@} |
mbed_official | 146:f64d43ff0c18 | 9634 | |
mbed_official | 146:f64d43ff0c18 | 9635 | /*! |
mbed_official | 146:f64d43ff0c18 | 9636 | * @name Register AIPS_PACRK, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 9637 | * |
mbed_official | 146:f64d43ff0c18 | 9638 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9639 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9640 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 9641 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9642 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9643 | * |
mbed_official | 146:f64d43ff0c18 | 9644 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9645 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9646 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9647 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9648 | */ |
mbed_official | 146:f64d43ff0c18 | 9649 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9650 | #define BP_AIPS_PACRK_SP1 (26U) //!< Bit position for AIPS_PACRK_SP1. |
mbed_official | 146:f64d43ff0c18 | 9651 | #define BM_AIPS_PACRK_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRK_SP1. |
mbed_official | 146:f64d43ff0c18 | 9652 | #define BS_AIPS_PACRK_SP1 (1U) //!< Bit field size in bits for AIPS_PACRK_SP1. |
mbed_official | 146:f64d43ff0c18 | 9653 | |
mbed_official | 146:f64d43ff0c18 | 9654 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9655 | //! @brief Read current value of the AIPS_PACRK_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 9656 | #define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1)) |
mbed_official | 146:f64d43ff0c18 | 9657 | #endif |
mbed_official | 146:f64d43ff0c18 | 9658 | |
mbed_official | 146:f64d43ff0c18 | 9659 | //! @brief Format value for bitfield AIPS_PACRK_SP1. |
mbed_official | 146:f64d43ff0c18 | 9660 | #define BF_AIPS_PACRK_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP1), uint32_t) & BM_AIPS_PACRK_SP1) |
mbed_official | 146:f64d43ff0c18 | 9661 | |
mbed_official | 146:f64d43ff0c18 | 9662 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9663 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9664 | #define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9665 | #endif |
mbed_official | 146:f64d43ff0c18 | 9666 | //@} |
mbed_official | 146:f64d43ff0c18 | 9667 | |
mbed_official | 146:f64d43ff0c18 | 9668 | /*! |
mbed_official | 146:f64d43ff0c18 | 9669 | * @name Register AIPS_PACRK, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 9670 | * |
mbed_official | 146:f64d43ff0c18 | 9671 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9672 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9673 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9674 | * |
mbed_official | 146:f64d43ff0c18 | 9675 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9676 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9677 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9678 | */ |
mbed_official | 146:f64d43ff0c18 | 9679 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9680 | #define BP_AIPS_PACRK_TP0 (28U) //!< Bit position for AIPS_PACRK_TP0. |
mbed_official | 146:f64d43ff0c18 | 9681 | #define BM_AIPS_PACRK_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRK_TP0. |
mbed_official | 146:f64d43ff0c18 | 9682 | #define BS_AIPS_PACRK_TP0 (1U) //!< Bit field size in bits for AIPS_PACRK_TP0. |
mbed_official | 146:f64d43ff0c18 | 9683 | |
mbed_official | 146:f64d43ff0c18 | 9684 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9685 | //! @brief Read current value of the AIPS_PACRK_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 9686 | #define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0)) |
mbed_official | 146:f64d43ff0c18 | 9687 | #endif |
mbed_official | 146:f64d43ff0c18 | 9688 | |
mbed_official | 146:f64d43ff0c18 | 9689 | //! @brief Format value for bitfield AIPS_PACRK_TP0. |
mbed_official | 146:f64d43ff0c18 | 9690 | #define BF_AIPS_PACRK_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP0), uint32_t) & BM_AIPS_PACRK_TP0) |
mbed_official | 146:f64d43ff0c18 | 9691 | |
mbed_official | 146:f64d43ff0c18 | 9692 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9693 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9694 | #define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9695 | #endif |
mbed_official | 146:f64d43ff0c18 | 9696 | //@} |
mbed_official | 146:f64d43ff0c18 | 9697 | |
mbed_official | 146:f64d43ff0c18 | 9698 | /*! |
mbed_official | 146:f64d43ff0c18 | 9699 | * @name Register AIPS_PACRK, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 9700 | * |
mbed_official | 146:f64d43ff0c18 | 9701 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9702 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9703 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9704 | * |
mbed_official | 146:f64d43ff0c18 | 9705 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9706 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9707 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9708 | */ |
mbed_official | 146:f64d43ff0c18 | 9709 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9710 | #define BP_AIPS_PACRK_WP0 (29U) //!< Bit position for AIPS_PACRK_WP0. |
mbed_official | 146:f64d43ff0c18 | 9711 | #define BM_AIPS_PACRK_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRK_WP0. |
mbed_official | 146:f64d43ff0c18 | 9712 | #define BS_AIPS_PACRK_WP0 (1U) //!< Bit field size in bits for AIPS_PACRK_WP0. |
mbed_official | 146:f64d43ff0c18 | 9713 | |
mbed_official | 146:f64d43ff0c18 | 9714 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9715 | //! @brief Read current value of the AIPS_PACRK_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 9716 | #define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0)) |
mbed_official | 146:f64d43ff0c18 | 9717 | #endif |
mbed_official | 146:f64d43ff0c18 | 9718 | |
mbed_official | 146:f64d43ff0c18 | 9719 | //! @brief Format value for bitfield AIPS_PACRK_WP0. |
mbed_official | 146:f64d43ff0c18 | 9720 | #define BF_AIPS_PACRK_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP0), uint32_t) & BM_AIPS_PACRK_WP0) |
mbed_official | 146:f64d43ff0c18 | 9721 | |
mbed_official | 146:f64d43ff0c18 | 9722 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9723 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9724 | #define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9725 | #endif |
mbed_official | 146:f64d43ff0c18 | 9726 | //@} |
mbed_official | 146:f64d43ff0c18 | 9727 | |
mbed_official | 146:f64d43ff0c18 | 9728 | /*! |
mbed_official | 146:f64d43ff0c18 | 9729 | * @name Register AIPS_PACRK, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 9730 | * |
mbed_official | 146:f64d43ff0c18 | 9731 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9732 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9733 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9734 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9735 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9736 | * |
mbed_official | 146:f64d43ff0c18 | 9737 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9738 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9739 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9740 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9741 | */ |
mbed_official | 146:f64d43ff0c18 | 9742 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9743 | #define BP_AIPS_PACRK_SP0 (30U) //!< Bit position for AIPS_PACRK_SP0. |
mbed_official | 146:f64d43ff0c18 | 9744 | #define BM_AIPS_PACRK_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRK_SP0. |
mbed_official | 146:f64d43ff0c18 | 9745 | #define BS_AIPS_PACRK_SP0 (1U) //!< Bit field size in bits for AIPS_PACRK_SP0. |
mbed_official | 146:f64d43ff0c18 | 9746 | |
mbed_official | 146:f64d43ff0c18 | 9747 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9748 | //! @brief Read current value of the AIPS_PACRK_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 9749 | #define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0)) |
mbed_official | 146:f64d43ff0c18 | 9750 | #endif |
mbed_official | 146:f64d43ff0c18 | 9751 | |
mbed_official | 146:f64d43ff0c18 | 9752 | //! @brief Format value for bitfield AIPS_PACRK_SP0. |
mbed_official | 146:f64d43ff0c18 | 9753 | #define BF_AIPS_PACRK_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP0), uint32_t) & BM_AIPS_PACRK_SP0) |
mbed_official | 146:f64d43ff0c18 | 9754 | |
mbed_official | 146:f64d43ff0c18 | 9755 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9756 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9757 | #define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9758 | #endif |
mbed_official | 146:f64d43ff0c18 | 9759 | //@} |
mbed_official | 146:f64d43ff0c18 | 9760 | |
mbed_official | 146:f64d43ff0c18 | 9761 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 9762 | // HW_AIPS_PACRL - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 9763 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 9764 | |
mbed_official | 146:f64d43ff0c18 | 9765 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9766 | /*! |
mbed_official | 146:f64d43ff0c18 | 9767 | * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 9768 | * |
mbed_official | 146:f64d43ff0c18 | 9769 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 9770 | * |
mbed_official | 146:f64d43ff0c18 | 9771 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 9772 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 9773 | * registers. |
mbed_official | 146:f64d43ff0c18 | 9774 | */ |
mbed_official | 146:f64d43ff0c18 | 9775 | typedef union _hw_aips_pacrl |
mbed_official | 146:f64d43ff0c18 | 9776 | { |
mbed_official | 146:f64d43ff0c18 | 9777 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 9778 | struct _hw_aips_pacrl_bitfields |
mbed_official | 146:f64d43ff0c18 | 9779 | { |
mbed_official | 146:f64d43ff0c18 | 9780 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9781 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9782 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9783 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 9784 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9785 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9786 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9787 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 9788 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9789 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9790 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9791 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 9792 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9793 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9794 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9795 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 9796 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9797 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9798 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9799 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 9800 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9801 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9802 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9803 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 9804 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9805 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9806 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9807 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 9808 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 9809 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 9810 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 9811 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 9812 | } B; |
mbed_official | 146:f64d43ff0c18 | 9813 | } hw_aips_pacrl_t; |
mbed_official | 146:f64d43ff0c18 | 9814 | #endif |
mbed_official | 146:f64d43ff0c18 | 9815 | |
mbed_official | 146:f64d43ff0c18 | 9816 | /*! |
mbed_official | 146:f64d43ff0c18 | 9817 | * @name Constants and macros for entire AIPS_PACRL register |
mbed_official | 146:f64d43ff0c18 | 9818 | */ |
mbed_official | 146:f64d43ff0c18 | 9819 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9820 | #define HW_AIPS_PACRL_ADDR(x) (REGS_AIPS_BASE(x) + 0x5CU) |
mbed_official | 146:f64d43ff0c18 | 9821 | |
mbed_official | 146:f64d43ff0c18 | 9822 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9823 | #define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 9824 | #define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U) |
mbed_official | 146:f64d43ff0c18 | 9825 | #define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 9826 | #define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 9827 | #define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 9828 | #define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 9829 | #endif |
mbed_official | 146:f64d43ff0c18 | 9830 | //@} |
mbed_official | 146:f64d43ff0c18 | 9831 | |
mbed_official | 146:f64d43ff0c18 | 9832 | /* |
mbed_official | 146:f64d43ff0c18 | 9833 | * Constants & macros for individual AIPS_PACRL bitfields |
mbed_official | 146:f64d43ff0c18 | 9834 | */ |
mbed_official | 146:f64d43ff0c18 | 9835 | |
mbed_official | 146:f64d43ff0c18 | 9836 | /*! |
mbed_official | 146:f64d43ff0c18 | 9837 | * @name Register AIPS_PACRL, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 9838 | * |
mbed_official | 146:f64d43ff0c18 | 9839 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9840 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9841 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9842 | * |
mbed_official | 146:f64d43ff0c18 | 9843 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9844 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9845 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9846 | */ |
mbed_official | 146:f64d43ff0c18 | 9847 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9848 | #define BP_AIPS_PACRL_TP7 (0U) //!< Bit position for AIPS_PACRL_TP7. |
mbed_official | 146:f64d43ff0c18 | 9849 | #define BM_AIPS_PACRL_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRL_TP7. |
mbed_official | 146:f64d43ff0c18 | 9850 | #define BS_AIPS_PACRL_TP7 (1U) //!< Bit field size in bits for AIPS_PACRL_TP7. |
mbed_official | 146:f64d43ff0c18 | 9851 | |
mbed_official | 146:f64d43ff0c18 | 9852 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9853 | //! @brief Read current value of the AIPS_PACRL_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 9854 | #define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7)) |
mbed_official | 146:f64d43ff0c18 | 9855 | #endif |
mbed_official | 146:f64d43ff0c18 | 9856 | |
mbed_official | 146:f64d43ff0c18 | 9857 | //! @brief Format value for bitfield AIPS_PACRL_TP7. |
mbed_official | 146:f64d43ff0c18 | 9858 | #define BF_AIPS_PACRL_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP7), uint32_t) & BM_AIPS_PACRL_TP7) |
mbed_official | 146:f64d43ff0c18 | 9859 | |
mbed_official | 146:f64d43ff0c18 | 9860 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9861 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9862 | #define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9863 | #endif |
mbed_official | 146:f64d43ff0c18 | 9864 | //@} |
mbed_official | 146:f64d43ff0c18 | 9865 | |
mbed_official | 146:f64d43ff0c18 | 9866 | /*! |
mbed_official | 146:f64d43ff0c18 | 9867 | * @name Register AIPS_PACRL, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 9868 | * |
mbed_official | 146:f64d43ff0c18 | 9869 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9870 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9871 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9872 | * |
mbed_official | 146:f64d43ff0c18 | 9873 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9874 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9875 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9876 | */ |
mbed_official | 146:f64d43ff0c18 | 9877 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9878 | #define BP_AIPS_PACRL_WP7 (1U) //!< Bit position for AIPS_PACRL_WP7. |
mbed_official | 146:f64d43ff0c18 | 9879 | #define BM_AIPS_PACRL_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRL_WP7. |
mbed_official | 146:f64d43ff0c18 | 9880 | #define BS_AIPS_PACRL_WP7 (1U) //!< Bit field size in bits for AIPS_PACRL_WP7. |
mbed_official | 146:f64d43ff0c18 | 9881 | |
mbed_official | 146:f64d43ff0c18 | 9882 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9883 | //! @brief Read current value of the AIPS_PACRL_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 9884 | #define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7)) |
mbed_official | 146:f64d43ff0c18 | 9885 | #endif |
mbed_official | 146:f64d43ff0c18 | 9886 | |
mbed_official | 146:f64d43ff0c18 | 9887 | //! @brief Format value for bitfield AIPS_PACRL_WP7. |
mbed_official | 146:f64d43ff0c18 | 9888 | #define BF_AIPS_PACRL_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP7), uint32_t) & BM_AIPS_PACRL_WP7) |
mbed_official | 146:f64d43ff0c18 | 9889 | |
mbed_official | 146:f64d43ff0c18 | 9890 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9891 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9892 | #define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9893 | #endif |
mbed_official | 146:f64d43ff0c18 | 9894 | //@} |
mbed_official | 146:f64d43ff0c18 | 9895 | |
mbed_official | 146:f64d43ff0c18 | 9896 | /*! |
mbed_official | 146:f64d43ff0c18 | 9897 | * @name Register AIPS_PACRL, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 9898 | * |
mbed_official | 146:f64d43ff0c18 | 9899 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9900 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9901 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9902 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9903 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9904 | * |
mbed_official | 146:f64d43ff0c18 | 9905 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9906 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9907 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 9908 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 9909 | */ |
mbed_official | 146:f64d43ff0c18 | 9910 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9911 | #define BP_AIPS_PACRL_SP7 (2U) //!< Bit position for AIPS_PACRL_SP7. |
mbed_official | 146:f64d43ff0c18 | 9912 | #define BM_AIPS_PACRL_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRL_SP7. |
mbed_official | 146:f64d43ff0c18 | 9913 | #define BS_AIPS_PACRL_SP7 (1U) //!< Bit field size in bits for AIPS_PACRL_SP7. |
mbed_official | 146:f64d43ff0c18 | 9914 | |
mbed_official | 146:f64d43ff0c18 | 9915 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9916 | //! @brief Read current value of the AIPS_PACRL_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 9917 | #define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7)) |
mbed_official | 146:f64d43ff0c18 | 9918 | #endif |
mbed_official | 146:f64d43ff0c18 | 9919 | |
mbed_official | 146:f64d43ff0c18 | 9920 | //! @brief Format value for bitfield AIPS_PACRL_SP7. |
mbed_official | 146:f64d43ff0c18 | 9921 | #define BF_AIPS_PACRL_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP7), uint32_t) & BM_AIPS_PACRL_SP7) |
mbed_official | 146:f64d43ff0c18 | 9922 | |
mbed_official | 146:f64d43ff0c18 | 9923 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9924 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9925 | #define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9926 | #endif |
mbed_official | 146:f64d43ff0c18 | 9927 | //@} |
mbed_official | 146:f64d43ff0c18 | 9928 | |
mbed_official | 146:f64d43ff0c18 | 9929 | /*! |
mbed_official | 146:f64d43ff0c18 | 9930 | * @name Register AIPS_PACRL, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 9931 | * |
mbed_official | 146:f64d43ff0c18 | 9932 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 9933 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 9934 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9935 | * |
mbed_official | 146:f64d43ff0c18 | 9936 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9937 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 9938 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 9939 | */ |
mbed_official | 146:f64d43ff0c18 | 9940 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9941 | #define BP_AIPS_PACRL_TP6 (4U) //!< Bit position for AIPS_PACRL_TP6. |
mbed_official | 146:f64d43ff0c18 | 9942 | #define BM_AIPS_PACRL_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRL_TP6. |
mbed_official | 146:f64d43ff0c18 | 9943 | #define BS_AIPS_PACRL_TP6 (1U) //!< Bit field size in bits for AIPS_PACRL_TP6. |
mbed_official | 146:f64d43ff0c18 | 9944 | |
mbed_official | 146:f64d43ff0c18 | 9945 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9946 | //! @brief Read current value of the AIPS_PACRL_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 9947 | #define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6)) |
mbed_official | 146:f64d43ff0c18 | 9948 | #endif |
mbed_official | 146:f64d43ff0c18 | 9949 | |
mbed_official | 146:f64d43ff0c18 | 9950 | //! @brief Format value for bitfield AIPS_PACRL_TP6. |
mbed_official | 146:f64d43ff0c18 | 9951 | #define BF_AIPS_PACRL_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP6), uint32_t) & BM_AIPS_PACRL_TP6) |
mbed_official | 146:f64d43ff0c18 | 9952 | |
mbed_official | 146:f64d43ff0c18 | 9953 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9954 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9955 | #define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9956 | #endif |
mbed_official | 146:f64d43ff0c18 | 9957 | //@} |
mbed_official | 146:f64d43ff0c18 | 9958 | |
mbed_official | 146:f64d43ff0c18 | 9959 | /*! |
mbed_official | 146:f64d43ff0c18 | 9960 | * @name Register AIPS_PACRL, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 9961 | * |
mbed_official | 146:f64d43ff0c18 | 9962 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 9963 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 9964 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 9965 | * |
mbed_official | 146:f64d43ff0c18 | 9966 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9967 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 9968 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 9969 | */ |
mbed_official | 146:f64d43ff0c18 | 9970 | //@{ |
mbed_official | 146:f64d43ff0c18 | 9971 | #define BP_AIPS_PACRL_WP6 (5U) //!< Bit position for AIPS_PACRL_WP6. |
mbed_official | 146:f64d43ff0c18 | 9972 | #define BM_AIPS_PACRL_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRL_WP6. |
mbed_official | 146:f64d43ff0c18 | 9973 | #define BS_AIPS_PACRL_WP6 (1U) //!< Bit field size in bits for AIPS_PACRL_WP6. |
mbed_official | 146:f64d43ff0c18 | 9974 | |
mbed_official | 146:f64d43ff0c18 | 9975 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9976 | //! @brief Read current value of the AIPS_PACRL_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 9977 | #define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6)) |
mbed_official | 146:f64d43ff0c18 | 9978 | #endif |
mbed_official | 146:f64d43ff0c18 | 9979 | |
mbed_official | 146:f64d43ff0c18 | 9980 | //! @brief Format value for bitfield AIPS_PACRL_WP6. |
mbed_official | 146:f64d43ff0c18 | 9981 | #define BF_AIPS_PACRL_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP6), uint32_t) & BM_AIPS_PACRL_WP6) |
mbed_official | 146:f64d43ff0c18 | 9982 | |
mbed_official | 146:f64d43ff0c18 | 9983 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 9984 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 9985 | #define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 9986 | #endif |
mbed_official | 146:f64d43ff0c18 | 9987 | //@} |
mbed_official | 146:f64d43ff0c18 | 9988 | |
mbed_official | 146:f64d43ff0c18 | 9989 | /*! |
mbed_official | 146:f64d43ff0c18 | 9990 | * @name Register AIPS_PACRL, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 9991 | * |
mbed_official | 146:f64d43ff0c18 | 9992 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 9993 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 9994 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 9995 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 9996 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 9997 | * |
mbed_official | 146:f64d43ff0c18 | 9998 | * Values: |
mbed_official | 146:f64d43ff0c18 | 9999 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10000 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10001 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10002 | */ |
mbed_official | 146:f64d43ff0c18 | 10003 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10004 | #define BP_AIPS_PACRL_SP6 (6U) //!< Bit position for AIPS_PACRL_SP6. |
mbed_official | 146:f64d43ff0c18 | 10005 | #define BM_AIPS_PACRL_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRL_SP6. |
mbed_official | 146:f64d43ff0c18 | 10006 | #define BS_AIPS_PACRL_SP6 (1U) //!< Bit field size in bits for AIPS_PACRL_SP6. |
mbed_official | 146:f64d43ff0c18 | 10007 | |
mbed_official | 146:f64d43ff0c18 | 10008 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10009 | //! @brief Read current value of the AIPS_PACRL_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 10010 | #define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6)) |
mbed_official | 146:f64d43ff0c18 | 10011 | #endif |
mbed_official | 146:f64d43ff0c18 | 10012 | |
mbed_official | 146:f64d43ff0c18 | 10013 | //! @brief Format value for bitfield AIPS_PACRL_SP6. |
mbed_official | 146:f64d43ff0c18 | 10014 | #define BF_AIPS_PACRL_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP6), uint32_t) & BM_AIPS_PACRL_SP6) |
mbed_official | 146:f64d43ff0c18 | 10015 | |
mbed_official | 146:f64d43ff0c18 | 10016 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10017 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10018 | #define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10019 | #endif |
mbed_official | 146:f64d43ff0c18 | 10020 | //@} |
mbed_official | 146:f64d43ff0c18 | 10021 | |
mbed_official | 146:f64d43ff0c18 | 10022 | /*! |
mbed_official | 146:f64d43ff0c18 | 10023 | * @name Register AIPS_PACRL, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 10024 | * |
mbed_official | 146:f64d43ff0c18 | 10025 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10026 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10027 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10028 | * |
mbed_official | 146:f64d43ff0c18 | 10029 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10030 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10031 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10032 | */ |
mbed_official | 146:f64d43ff0c18 | 10033 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10034 | #define BP_AIPS_PACRL_TP5 (8U) //!< Bit position for AIPS_PACRL_TP5. |
mbed_official | 146:f64d43ff0c18 | 10035 | #define BM_AIPS_PACRL_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRL_TP5. |
mbed_official | 146:f64d43ff0c18 | 10036 | #define BS_AIPS_PACRL_TP5 (1U) //!< Bit field size in bits for AIPS_PACRL_TP5. |
mbed_official | 146:f64d43ff0c18 | 10037 | |
mbed_official | 146:f64d43ff0c18 | 10038 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10039 | //! @brief Read current value of the AIPS_PACRL_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 10040 | #define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5)) |
mbed_official | 146:f64d43ff0c18 | 10041 | #endif |
mbed_official | 146:f64d43ff0c18 | 10042 | |
mbed_official | 146:f64d43ff0c18 | 10043 | //! @brief Format value for bitfield AIPS_PACRL_TP5. |
mbed_official | 146:f64d43ff0c18 | 10044 | #define BF_AIPS_PACRL_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP5), uint32_t) & BM_AIPS_PACRL_TP5) |
mbed_official | 146:f64d43ff0c18 | 10045 | |
mbed_official | 146:f64d43ff0c18 | 10046 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10047 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10048 | #define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10049 | #endif |
mbed_official | 146:f64d43ff0c18 | 10050 | //@} |
mbed_official | 146:f64d43ff0c18 | 10051 | |
mbed_official | 146:f64d43ff0c18 | 10052 | /*! |
mbed_official | 146:f64d43ff0c18 | 10053 | * @name Register AIPS_PACRL, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 10054 | * |
mbed_official | 146:f64d43ff0c18 | 10055 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10056 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10057 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10058 | * |
mbed_official | 146:f64d43ff0c18 | 10059 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10060 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10061 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10062 | */ |
mbed_official | 146:f64d43ff0c18 | 10063 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10064 | #define BP_AIPS_PACRL_WP5 (9U) //!< Bit position for AIPS_PACRL_WP5. |
mbed_official | 146:f64d43ff0c18 | 10065 | #define BM_AIPS_PACRL_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRL_WP5. |
mbed_official | 146:f64d43ff0c18 | 10066 | #define BS_AIPS_PACRL_WP5 (1U) //!< Bit field size in bits for AIPS_PACRL_WP5. |
mbed_official | 146:f64d43ff0c18 | 10067 | |
mbed_official | 146:f64d43ff0c18 | 10068 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10069 | //! @brief Read current value of the AIPS_PACRL_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 10070 | #define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5)) |
mbed_official | 146:f64d43ff0c18 | 10071 | #endif |
mbed_official | 146:f64d43ff0c18 | 10072 | |
mbed_official | 146:f64d43ff0c18 | 10073 | //! @brief Format value for bitfield AIPS_PACRL_WP5. |
mbed_official | 146:f64d43ff0c18 | 10074 | #define BF_AIPS_PACRL_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP5), uint32_t) & BM_AIPS_PACRL_WP5) |
mbed_official | 146:f64d43ff0c18 | 10075 | |
mbed_official | 146:f64d43ff0c18 | 10076 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10077 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10078 | #define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10079 | #endif |
mbed_official | 146:f64d43ff0c18 | 10080 | //@} |
mbed_official | 146:f64d43ff0c18 | 10081 | |
mbed_official | 146:f64d43ff0c18 | 10082 | /*! |
mbed_official | 146:f64d43ff0c18 | 10083 | * @name Register AIPS_PACRL, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 10084 | * |
mbed_official | 146:f64d43ff0c18 | 10085 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10086 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10087 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 10088 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10089 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10090 | * |
mbed_official | 146:f64d43ff0c18 | 10091 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10092 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10093 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10094 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10095 | */ |
mbed_official | 146:f64d43ff0c18 | 10096 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10097 | #define BP_AIPS_PACRL_SP5 (10U) //!< Bit position for AIPS_PACRL_SP5. |
mbed_official | 146:f64d43ff0c18 | 10098 | #define BM_AIPS_PACRL_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRL_SP5. |
mbed_official | 146:f64d43ff0c18 | 10099 | #define BS_AIPS_PACRL_SP5 (1U) //!< Bit field size in bits for AIPS_PACRL_SP5. |
mbed_official | 146:f64d43ff0c18 | 10100 | |
mbed_official | 146:f64d43ff0c18 | 10101 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10102 | //! @brief Read current value of the AIPS_PACRL_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 10103 | #define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5)) |
mbed_official | 146:f64d43ff0c18 | 10104 | #endif |
mbed_official | 146:f64d43ff0c18 | 10105 | |
mbed_official | 146:f64d43ff0c18 | 10106 | //! @brief Format value for bitfield AIPS_PACRL_SP5. |
mbed_official | 146:f64d43ff0c18 | 10107 | #define BF_AIPS_PACRL_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP5), uint32_t) & BM_AIPS_PACRL_SP5) |
mbed_official | 146:f64d43ff0c18 | 10108 | |
mbed_official | 146:f64d43ff0c18 | 10109 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10110 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10111 | #define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10112 | #endif |
mbed_official | 146:f64d43ff0c18 | 10113 | //@} |
mbed_official | 146:f64d43ff0c18 | 10114 | |
mbed_official | 146:f64d43ff0c18 | 10115 | /*! |
mbed_official | 146:f64d43ff0c18 | 10116 | * @name Register AIPS_PACRL, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 10117 | * |
mbed_official | 146:f64d43ff0c18 | 10118 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10119 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10120 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10121 | * |
mbed_official | 146:f64d43ff0c18 | 10122 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10123 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10124 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10125 | */ |
mbed_official | 146:f64d43ff0c18 | 10126 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10127 | #define BP_AIPS_PACRL_TP4 (12U) //!< Bit position for AIPS_PACRL_TP4. |
mbed_official | 146:f64d43ff0c18 | 10128 | #define BM_AIPS_PACRL_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRL_TP4. |
mbed_official | 146:f64d43ff0c18 | 10129 | #define BS_AIPS_PACRL_TP4 (1U) //!< Bit field size in bits for AIPS_PACRL_TP4. |
mbed_official | 146:f64d43ff0c18 | 10130 | |
mbed_official | 146:f64d43ff0c18 | 10131 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10132 | //! @brief Read current value of the AIPS_PACRL_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 10133 | #define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4)) |
mbed_official | 146:f64d43ff0c18 | 10134 | #endif |
mbed_official | 146:f64d43ff0c18 | 10135 | |
mbed_official | 146:f64d43ff0c18 | 10136 | //! @brief Format value for bitfield AIPS_PACRL_TP4. |
mbed_official | 146:f64d43ff0c18 | 10137 | #define BF_AIPS_PACRL_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP4), uint32_t) & BM_AIPS_PACRL_TP4) |
mbed_official | 146:f64d43ff0c18 | 10138 | |
mbed_official | 146:f64d43ff0c18 | 10139 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10140 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10141 | #define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10142 | #endif |
mbed_official | 146:f64d43ff0c18 | 10143 | //@} |
mbed_official | 146:f64d43ff0c18 | 10144 | |
mbed_official | 146:f64d43ff0c18 | 10145 | /*! |
mbed_official | 146:f64d43ff0c18 | 10146 | * @name Register AIPS_PACRL, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 10147 | * |
mbed_official | 146:f64d43ff0c18 | 10148 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10149 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10150 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10151 | * |
mbed_official | 146:f64d43ff0c18 | 10152 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10153 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10154 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10155 | */ |
mbed_official | 146:f64d43ff0c18 | 10156 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10157 | #define BP_AIPS_PACRL_WP4 (13U) //!< Bit position for AIPS_PACRL_WP4. |
mbed_official | 146:f64d43ff0c18 | 10158 | #define BM_AIPS_PACRL_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRL_WP4. |
mbed_official | 146:f64d43ff0c18 | 10159 | #define BS_AIPS_PACRL_WP4 (1U) //!< Bit field size in bits for AIPS_PACRL_WP4. |
mbed_official | 146:f64d43ff0c18 | 10160 | |
mbed_official | 146:f64d43ff0c18 | 10161 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10162 | //! @brief Read current value of the AIPS_PACRL_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 10163 | #define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4)) |
mbed_official | 146:f64d43ff0c18 | 10164 | #endif |
mbed_official | 146:f64d43ff0c18 | 10165 | |
mbed_official | 146:f64d43ff0c18 | 10166 | //! @brief Format value for bitfield AIPS_PACRL_WP4. |
mbed_official | 146:f64d43ff0c18 | 10167 | #define BF_AIPS_PACRL_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP4), uint32_t) & BM_AIPS_PACRL_WP4) |
mbed_official | 146:f64d43ff0c18 | 10168 | |
mbed_official | 146:f64d43ff0c18 | 10169 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10170 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10171 | #define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10172 | #endif |
mbed_official | 146:f64d43ff0c18 | 10173 | //@} |
mbed_official | 146:f64d43ff0c18 | 10174 | |
mbed_official | 146:f64d43ff0c18 | 10175 | /*! |
mbed_official | 146:f64d43ff0c18 | 10176 | * @name Register AIPS_PACRL, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 10177 | * |
mbed_official | 146:f64d43ff0c18 | 10178 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10179 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10180 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 10181 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 10182 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 10183 | * |
mbed_official | 146:f64d43ff0c18 | 10184 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10185 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10186 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10187 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10188 | */ |
mbed_official | 146:f64d43ff0c18 | 10189 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10190 | #define BP_AIPS_PACRL_SP4 (14U) //!< Bit position for AIPS_PACRL_SP4. |
mbed_official | 146:f64d43ff0c18 | 10191 | #define BM_AIPS_PACRL_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRL_SP4. |
mbed_official | 146:f64d43ff0c18 | 10192 | #define BS_AIPS_PACRL_SP4 (1U) //!< Bit field size in bits for AIPS_PACRL_SP4. |
mbed_official | 146:f64d43ff0c18 | 10193 | |
mbed_official | 146:f64d43ff0c18 | 10194 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10195 | //! @brief Read current value of the AIPS_PACRL_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 10196 | #define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4)) |
mbed_official | 146:f64d43ff0c18 | 10197 | #endif |
mbed_official | 146:f64d43ff0c18 | 10198 | |
mbed_official | 146:f64d43ff0c18 | 10199 | //! @brief Format value for bitfield AIPS_PACRL_SP4. |
mbed_official | 146:f64d43ff0c18 | 10200 | #define BF_AIPS_PACRL_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP4), uint32_t) & BM_AIPS_PACRL_SP4) |
mbed_official | 146:f64d43ff0c18 | 10201 | |
mbed_official | 146:f64d43ff0c18 | 10202 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10203 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10204 | #define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10205 | #endif |
mbed_official | 146:f64d43ff0c18 | 10206 | //@} |
mbed_official | 146:f64d43ff0c18 | 10207 | |
mbed_official | 146:f64d43ff0c18 | 10208 | /*! |
mbed_official | 146:f64d43ff0c18 | 10209 | * @name Register AIPS_PACRL, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 10210 | * |
mbed_official | 146:f64d43ff0c18 | 10211 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10212 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10213 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10214 | * |
mbed_official | 146:f64d43ff0c18 | 10215 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10216 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10217 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10218 | */ |
mbed_official | 146:f64d43ff0c18 | 10219 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10220 | #define BP_AIPS_PACRL_TP3 (16U) //!< Bit position for AIPS_PACRL_TP3. |
mbed_official | 146:f64d43ff0c18 | 10221 | #define BM_AIPS_PACRL_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRL_TP3. |
mbed_official | 146:f64d43ff0c18 | 10222 | #define BS_AIPS_PACRL_TP3 (1U) //!< Bit field size in bits for AIPS_PACRL_TP3. |
mbed_official | 146:f64d43ff0c18 | 10223 | |
mbed_official | 146:f64d43ff0c18 | 10224 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10225 | //! @brief Read current value of the AIPS_PACRL_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 10226 | #define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3)) |
mbed_official | 146:f64d43ff0c18 | 10227 | #endif |
mbed_official | 146:f64d43ff0c18 | 10228 | |
mbed_official | 146:f64d43ff0c18 | 10229 | //! @brief Format value for bitfield AIPS_PACRL_TP3. |
mbed_official | 146:f64d43ff0c18 | 10230 | #define BF_AIPS_PACRL_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP3), uint32_t) & BM_AIPS_PACRL_TP3) |
mbed_official | 146:f64d43ff0c18 | 10231 | |
mbed_official | 146:f64d43ff0c18 | 10232 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10233 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10234 | #define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10235 | #endif |
mbed_official | 146:f64d43ff0c18 | 10236 | //@} |
mbed_official | 146:f64d43ff0c18 | 10237 | |
mbed_official | 146:f64d43ff0c18 | 10238 | /*! |
mbed_official | 146:f64d43ff0c18 | 10239 | * @name Register AIPS_PACRL, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 10240 | * |
mbed_official | 146:f64d43ff0c18 | 10241 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 10242 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 10243 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10244 | * |
mbed_official | 146:f64d43ff0c18 | 10245 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10246 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10247 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10248 | */ |
mbed_official | 146:f64d43ff0c18 | 10249 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10250 | #define BP_AIPS_PACRL_WP3 (17U) //!< Bit position for AIPS_PACRL_WP3. |
mbed_official | 146:f64d43ff0c18 | 10251 | #define BM_AIPS_PACRL_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRL_WP3. |
mbed_official | 146:f64d43ff0c18 | 10252 | #define BS_AIPS_PACRL_WP3 (1U) //!< Bit field size in bits for AIPS_PACRL_WP3. |
mbed_official | 146:f64d43ff0c18 | 10253 | |
mbed_official | 146:f64d43ff0c18 | 10254 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10255 | //! @brief Read current value of the AIPS_PACRL_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 10256 | #define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3)) |
mbed_official | 146:f64d43ff0c18 | 10257 | #endif |
mbed_official | 146:f64d43ff0c18 | 10258 | |
mbed_official | 146:f64d43ff0c18 | 10259 | //! @brief Format value for bitfield AIPS_PACRL_WP3. |
mbed_official | 146:f64d43ff0c18 | 10260 | #define BF_AIPS_PACRL_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP3), uint32_t) & BM_AIPS_PACRL_WP3) |
mbed_official | 146:f64d43ff0c18 | 10261 | |
mbed_official | 146:f64d43ff0c18 | 10262 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10263 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10264 | #define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10265 | #endif |
mbed_official | 146:f64d43ff0c18 | 10266 | //@} |
mbed_official | 146:f64d43ff0c18 | 10267 | |
mbed_official | 146:f64d43ff0c18 | 10268 | /*! |
mbed_official | 146:f64d43ff0c18 | 10269 | * @name Register AIPS_PACRL, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 10270 | * |
mbed_official | 146:f64d43ff0c18 | 10271 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10272 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10273 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 10274 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10275 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10276 | * |
mbed_official | 146:f64d43ff0c18 | 10277 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10278 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10279 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10280 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10281 | */ |
mbed_official | 146:f64d43ff0c18 | 10282 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10283 | #define BP_AIPS_PACRL_SP3 (18U) //!< Bit position for AIPS_PACRL_SP3. |
mbed_official | 146:f64d43ff0c18 | 10284 | #define BM_AIPS_PACRL_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRL_SP3. |
mbed_official | 146:f64d43ff0c18 | 10285 | #define BS_AIPS_PACRL_SP3 (1U) //!< Bit field size in bits for AIPS_PACRL_SP3. |
mbed_official | 146:f64d43ff0c18 | 10286 | |
mbed_official | 146:f64d43ff0c18 | 10287 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10288 | //! @brief Read current value of the AIPS_PACRL_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 10289 | #define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3)) |
mbed_official | 146:f64d43ff0c18 | 10290 | #endif |
mbed_official | 146:f64d43ff0c18 | 10291 | |
mbed_official | 146:f64d43ff0c18 | 10292 | //! @brief Format value for bitfield AIPS_PACRL_SP3. |
mbed_official | 146:f64d43ff0c18 | 10293 | #define BF_AIPS_PACRL_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP3), uint32_t) & BM_AIPS_PACRL_SP3) |
mbed_official | 146:f64d43ff0c18 | 10294 | |
mbed_official | 146:f64d43ff0c18 | 10295 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10296 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10297 | #define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10298 | #endif |
mbed_official | 146:f64d43ff0c18 | 10299 | //@} |
mbed_official | 146:f64d43ff0c18 | 10300 | |
mbed_official | 146:f64d43ff0c18 | 10301 | /*! |
mbed_official | 146:f64d43ff0c18 | 10302 | * @name Register AIPS_PACRL, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 10303 | * |
mbed_official | 146:f64d43ff0c18 | 10304 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10305 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10306 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10307 | * |
mbed_official | 146:f64d43ff0c18 | 10308 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10309 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10310 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10311 | */ |
mbed_official | 146:f64d43ff0c18 | 10312 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10313 | #define BP_AIPS_PACRL_TP2 (20U) //!< Bit position for AIPS_PACRL_TP2. |
mbed_official | 146:f64d43ff0c18 | 10314 | #define BM_AIPS_PACRL_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRL_TP2. |
mbed_official | 146:f64d43ff0c18 | 10315 | #define BS_AIPS_PACRL_TP2 (1U) //!< Bit field size in bits for AIPS_PACRL_TP2. |
mbed_official | 146:f64d43ff0c18 | 10316 | |
mbed_official | 146:f64d43ff0c18 | 10317 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10318 | //! @brief Read current value of the AIPS_PACRL_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 10319 | #define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2)) |
mbed_official | 146:f64d43ff0c18 | 10320 | #endif |
mbed_official | 146:f64d43ff0c18 | 10321 | |
mbed_official | 146:f64d43ff0c18 | 10322 | //! @brief Format value for bitfield AIPS_PACRL_TP2. |
mbed_official | 146:f64d43ff0c18 | 10323 | #define BF_AIPS_PACRL_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP2), uint32_t) & BM_AIPS_PACRL_TP2) |
mbed_official | 146:f64d43ff0c18 | 10324 | |
mbed_official | 146:f64d43ff0c18 | 10325 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10326 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10327 | #define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10328 | #endif |
mbed_official | 146:f64d43ff0c18 | 10329 | //@} |
mbed_official | 146:f64d43ff0c18 | 10330 | |
mbed_official | 146:f64d43ff0c18 | 10331 | /*! |
mbed_official | 146:f64d43ff0c18 | 10332 | * @name Register AIPS_PACRL, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 10333 | * |
mbed_official | 146:f64d43ff0c18 | 10334 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10335 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10336 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10337 | * |
mbed_official | 146:f64d43ff0c18 | 10338 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10339 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10340 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10341 | */ |
mbed_official | 146:f64d43ff0c18 | 10342 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10343 | #define BP_AIPS_PACRL_WP2 (21U) //!< Bit position for AIPS_PACRL_WP2. |
mbed_official | 146:f64d43ff0c18 | 10344 | #define BM_AIPS_PACRL_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRL_WP2. |
mbed_official | 146:f64d43ff0c18 | 10345 | #define BS_AIPS_PACRL_WP2 (1U) //!< Bit field size in bits for AIPS_PACRL_WP2. |
mbed_official | 146:f64d43ff0c18 | 10346 | |
mbed_official | 146:f64d43ff0c18 | 10347 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10348 | //! @brief Read current value of the AIPS_PACRL_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 10349 | #define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2)) |
mbed_official | 146:f64d43ff0c18 | 10350 | #endif |
mbed_official | 146:f64d43ff0c18 | 10351 | |
mbed_official | 146:f64d43ff0c18 | 10352 | //! @brief Format value for bitfield AIPS_PACRL_WP2. |
mbed_official | 146:f64d43ff0c18 | 10353 | #define BF_AIPS_PACRL_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP2), uint32_t) & BM_AIPS_PACRL_WP2) |
mbed_official | 146:f64d43ff0c18 | 10354 | |
mbed_official | 146:f64d43ff0c18 | 10355 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10356 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10357 | #define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10358 | #endif |
mbed_official | 146:f64d43ff0c18 | 10359 | //@} |
mbed_official | 146:f64d43ff0c18 | 10360 | |
mbed_official | 146:f64d43ff0c18 | 10361 | /*! |
mbed_official | 146:f64d43ff0c18 | 10362 | * @name Register AIPS_PACRL, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 10363 | * |
mbed_official | 146:f64d43ff0c18 | 10364 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10365 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10366 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 10367 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 10368 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 10369 | * |
mbed_official | 146:f64d43ff0c18 | 10370 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10371 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10372 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10373 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10374 | */ |
mbed_official | 146:f64d43ff0c18 | 10375 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10376 | #define BP_AIPS_PACRL_SP2 (22U) //!< Bit position for AIPS_PACRL_SP2. |
mbed_official | 146:f64d43ff0c18 | 10377 | #define BM_AIPS_PACRL_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRL_SP2. |
mbed_official | 146:f64d43ff0c18 | 10378 | #define BS_AIPS_PACRL_SP2 (1U) //!< Bit field size in bits for AIPS_PACRL_SP2. |
mbed_official | 146:f64d43ff0c18 | 10379 | |
mbed_official | 146:f64d43ff0c18 | 10380 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10381 | //! @brief Read current value of the AIPS_PACRL_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 10382 | #define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2)) |
mbed_official | 146:f64d43ff0c18 | 10383 | #endif |
mbed_official | 146:f64d43ff0c18 | 10384 | |
mbed_official | 146:f64d43ff0c18 | 10385 | //! @brief Format value for bitfield AIPS_PACRL_SP2. |
mbed_official | 146:f64d43ff0c18 | 10386 | #define BF_AIPS_PACRL_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP2), uint32_t) & BM_AIPS_PACRL_SP2) |
mbed_official | 146:f64d43ff0c18 | 10387 | |
mbed_official | 146:f64d43ff0c18 | 10388 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10389 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10390 | #define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10391 | #endif |
mbed_official | 146:f64d43ff0c18 | 10392 | //@} |
mbed_official | 146:f64d43ff0c18 | 10393 | |
mbed_official | 146:f64d43ff0c18 | 10394 | /*! |
mbed_official | 146:f64d43ff0c18 | 10395 | * @name Register AIPS_PACRL, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 10396 | * |
mbed_official | 146:f64d43ff0c18 | 10397 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10398 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10399 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10400 | * |
mbed_official | 146:f64d43ff0c18 | 10401 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10402 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10403 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10404 | */ |
mbed_official | 146:f64d43ff0c18 | 10405 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10406 | #define BP_AIPS_PACRL_TP1 (24U) //!< Bit position for AIPS_PACRL_TP1. |
mbed_official | 146:f64d43ff0c18 | 10407 | #define BM_AIPS_PACRL_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRL_TP1. |
mbed_official | 146:f64d43ff0c18 | 10408 | #define BS_AIPS_PACRL_TP1 (1U) //!< Bit field size in bits for AIPS_PACRL_TP1. |
mbed_official | 146:f64d43ff0c18 | 10409 | |
mbed_official | 146:f64d43ff0c18 | 10410 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10411 | //! @brief Read current value of the AIPS_PACRL_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 10412 | #define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1)) |
mbed_official | 146:f64d43ff0c18 | 10413 | #endif |
mbed_official | 146:f64d43ff0c18 | 10414 | |
mbed_official | 146:f64d43ff0c18 | 10415 | //! @brief Format value for bitfield AIPS_PACRL_TP1. |
mbed_official | 146:f64d43ff0c18 | 10416 | #define BF_AIPS_PACRL_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP1), uint32_t) & BM_AIPS_PACRL_TP1) |
mbed_official | 146:f64d43ff0c18 | 10417 | |
mbed_official | 146:f64d43ff0c18 | 10418 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10419 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10420 | #define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10421 | #endif |
mbed_official | 146:f64d43ff0c18 | 10422 | //@} |
mbed_official | 146:f64d43ff0c18 | 10423 | |
mbed_official | 146:f64d43ff0c18 | 10424 | /*! |
mbed_official | 146:f64d43ff0c18 | 10425 | * @name Register AIPS_PACRL, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 10426 | * |
mbed_official | 146:f64d43ff0c18 | 10427 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10428 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10429 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10430 | * |
mbed_official | 146:f64d43ff0c18 | 10431 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10432 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10433 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10434 | */ |
mbed_official | 146:f64d43ff0c18 | 10435 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10436 | #define BP_AIPS_PACRL_WP1 (25U) //!< Bit position for AIPS_PACRL_WP1. |
mbed_official | 146:f64d43ff0c18 | 10437 | #define BM_AIPS_PACRL_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRL_WP1. |
mbed_official | 146:f64d43ff0c18 | 10438 | #define BS_AIPS_PACRL_WP1 (1U) //!< Bit field size in bits for AIPS_PACRL_WP1. |
mbed_official | 146:f64d43ff0c18 | 10439 | |
mbed_official | 146:f64d43ff0c18 | 10440 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10441 | //! @brief Read current value of the AIPS_PACRL_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 10442 | #define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1)) |
mbed_official | 146:f64d43ff0c18 | 10443 | #endif |
mbed_official | 146:f64d43ff0c18 | 10444 | |
mbed_official | 146:f64d43ff0c18 | 10445 | //! @brief Format value for bitfield AIPS_PACRL_WP1. |
mbed_official | 146:f64d43ff0c18 | 10446 | #define BF_AIPS_PACRL_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP1), uint32_t) & BM_AIPS_PACRL_WP1) |
mbed_official | 146:f64d43ff0c18 | 10447 | |
mbed_official | 146:f64d43ff0c18 | 10448 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10449 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10450 | #define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10451 | #endif |
mbed_official | 146:f64d43ff0c18 | 10452 | //@} |
mbed_official | 146:f64d43ff0c18 | 10453 | |
mbed_official | 146:f64d43ff0c18 | 10454 | /*! |
mbed_official | 146:f64d43ff0c18 | 10455 | * @name Register AIPS_PACRL, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 10456 | * |
mbed_official | 146:f64d43ff0c18 | 10457 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10458 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10459 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 10460 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10461 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10462 | * |
mbed_official | 146:f64d43ff0c18 | 10463 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10464 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10465 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10466 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10467 | */ |
mbed_official | 146:f64d43ff0c18 | 10468 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10469 | #define BP_AIPS_PACRL_SP1 (26U) //!< Bit position for AIPS_PACRL_SP1. |
mbed_official | 146:f64d43ff0c18 | 10470 | #define BM_AIPS_PACRL_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRL_SP1. |
mbed_official | 146:f64d43ff0c18 | 10471 | #define BS_AIPS_PACRL_SP1 (1U) //!< Bit field size in bits for AIPS_PACRL_SP1. |
mbed_official | 146:f64d43ff0c18 | 10472 | |
mbed_official | 146:f64d43ff0c18 | 10473 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10474 | //! @brief Read current value of the AIPS_PACRL_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 10475 | #define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1)) |
mbed_official | 146:f64d43ff0c18 | 10476 | #endif |
mbed_official | 146:f64d43ff0c18 | 10477 | |
mbed_official | 146:f64d43ff0c18 | 10478 | //! @brief Format value for bitfield AIPS_PACRL_SP1. |
mbed_official | 146:f64d43ff0c18 | 10479 | #define BF_AIPS_PACRL_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP1), uint32_t) & BM_AIPS_PACRL_SP1) |
mbed_official | 146:f64d43ff0c18 | 10480 | |
mbed_official | 146:f64d43ff0c18 | 10481 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10482 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10483 | #define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10484 | #endif |
mbed_official | 146:f64d43ff0c18 | 10485 | //@} |
mbed_official | 146:f64d43ff0c18 | 10486 | |
mbed_official | 146:f64d43ff0c18 | 10487 | /*! |
mbed_official | 146:f64d43ff0c18 | 10488 | * @name Register AIPS_PACRL, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 10489 | * |
mbed_official | 146:f64d43ff0c18 | 10490 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10491 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10492 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10493 | * |
mbed_official | 146:f64d43ff0c18 | 10494 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10495 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10496 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10497 | */ |
mbed_official | 146:f64d43ff0c18 | 10498 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10499 | #define BP_AIPS_PACRL_TP0 (28U) //!< Bit position for AIPS_PACRL_TP0. |
mbed_official | 146:f64d43ff0c18 | 10500 | #define BM_AIPS_PACRL_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRL_TP0. |
mbed_official | 146:f64d43ff0c18 | 10501 | #define BS_AIPS_PACRL_TP0 (1U) //!< Bit field size in bits for AIPS_PACRL_TP0. |
mbed_official | 146:f64d43ff0c18 | 10502 | |
mbed_official | 146:f64d43ff0c18 | 10503 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10504 | //! @brief Read current value of the AIPS_PACRL_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 10505 | #define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0)) |
mbed_official | 146:f64d43ff0c18 | 10506 | #endif |
mbed_official | 146:f64d43ff0c18 | 10507 | |
mbed_official | 146:f64d43ff0c18 | 10508 | //! @brief Format value for bitfield AIPS_PACRL_TP0. |
mbed_official | 146:f64d43ff0c18 | 10509 | #define BF_AIPS_PACRL_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP0), uint32_t) & BM_AIPS_PACRL_TP0) |
mbed_official | 146:f64d43ff0c18 | 10510 | |
mbed_official | 146:f64d43ff0c18 | 10511 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10512 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10513 | #define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10514 | #endif |
mbed_official | 146:f64d43ff0c18 | 10515 | //@} |
mbed_official | 146:f64d43ff0c18 | 10516 | |
mbed_official | 146:f64d43ff0c18 | 10517 | /*! |
mbed_official | 146:f64d43ff0c18 | 10518 | * @name Register AIPS_PACRL, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 10519 | * |
mbed_official | 146:f64d43ff0c18 | 10520 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10521 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10522 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10523 | * |
mbed_official | 146:f64d43ff0c18 | 10524 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10525 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10526 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10527 | */ |
mbed_official | 146:f64d43ff0c18 | 10528 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10529 | #define BP_AIPS_PACRL_WP0 (29U) //!< Bit position for AIPS_PACRL_WP0. |
mbed_official | 146:f64d43ff0c18 | 10530 | #define BM_AIPS_PACRL_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRL_WP0. |
mbed_official | 146:f64d43ff0c18 | 10531 | #define BS_AIPS_PACRL_WP0 (1U) //!< Bit field size in bits for AIPS_PACRL_WP0. |
mbed_official | 146:f64d43ff0c18 | 10532 | |
mbed_official | 146:f64d43ff0c18 | 10533 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10534 | //! @brief Read current value of the AIPS_PACRL_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 10535 | #define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0)) |
mbed_official | 146:f64d43ff0c18 | 10536 | #endif |
mbed_official | 146:f64d43ff0c18 | 10537 | |
mbed_official | 146:f64d43ff0c18 | 10538 | //! @brief Format value for bitfield AIPS_PACRL_WP0. |
mbed_official | 146:f64d43ff0c18 | 10539 | #define BF_AIPS_PACRL_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP0), uint32_t) & BM_AIPS_PACRL_WP0) |
mbed_official | 146:f64d43ff0c18 | 10540 | |
mbed_official | 146:f64d43ff0c18 | 10541 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10542 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10543 | #define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10544 | #endif |
mbed_official | 146:f64d43ff0c18 | 10545 | //@} |
mbed_official | 146:f64d43ff0c18 | 10546 | |
mbed_official | 146:f64d43ff0c18 | 10547 | /*! |
mbed_official | 146:f64d43ff0c18 | 10548 | * @name Register AIPS_PACRL, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 10549 | * |
mbed_official | 146:f64d43ff0c18 | 10550 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10551 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10552 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 10553 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10554 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10555 | * |
mbed_official | 146:f64d43ff0c18 | 10556 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10557 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10558 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10559 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10560 | */ |
mbed_official | 146:f64d43ff0c18 | 10561 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10562 | #define BP_AIPS_PACRL_SP0 (30U) //!< Bit position for AIPS_PACRL_SP0. |
mbed_official | 146:f64d43ff0c18 | 10563 | #define BM_AIPS_PACRL_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRL_SP0. |
mbed_official | 146:f64d43ff0c18 | 10564 | #define BS_AIPS_PACRL_SP0 (1U) //!< Bit field size in bits for AIPS_PACRL_SP0. |
mbed_official | 146:f64d43ff0c18 | 10565 | |
mbed_official | 146:f64d43ff0c18 | 10566 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10567 | //! @brief Read current value of the AIPS_PACRL_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 10568 | #define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0)) |
mbed_official | 146:f64d43ff0c18 | 10569 | #endif |
mbed_official | 146:f64d43ff0c18 | 10570 | |
mbed_official | 146:f64d43ff0c18 | 10571 | //! @brief Format value for bitfield AIPS_PACRL_SP0. |
mbed_official | 146:f64d43ff0c18 | 10572 | #define BF_AIPS_PACRL_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP0), uint32_t) & BM_AIPS_PACRL_SP0) |
mbed_official | 146:f64d43ff0c18 | 10573 | |
mbed_official | 146:f64d43ff0c18 | 10574 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10575 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10576 | #define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10577 | #endif |
mbed_official | 146:f64d43ff0c18 | 10578 | //@} |
mbed_official | 146:f64d43ff0c18 | 10579 | |
mbed_official | 146:f64d43ff0c18 | 10580 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 10581 | // HW_AIPS_PACRM - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 10582 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 10583 | |
mbed_official | 146:f64d43ff0c18 | 10584 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10585 | /*! |
mbed_official | 146:f64d43ff0c18 | 10586 | * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 10587 | * |
mbed_official | 146:f64d43ff0c18 | 10588 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 10589 | * |
mbed_official | 146:f64d43ff0c18 | 10590 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 10591 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 10592 | * registers. |
mbed_official | 146:f64d43ff0c18 | 10593 | */ |
mbed_official | 146:f64d43ff0c18 | 10594 | typedef union _hw_aips_pacrm |
mbed_official | 146:f64d43ff0c18 | 10595 | { |
mbed_official | 146:f64d43ff0c18 | 10596 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 10597 | struct _hw_aips_pacrm_bitfields |
mbed_official | 146:f64d43ff0c18 | 10598 | { |
mbed_official | 146:f64d43ff0c18 | 10599 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10600 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10601 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10602 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 10603 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10604 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10605 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10606 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 10607 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10608 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10609 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10610 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 10611 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10612 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10613 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10614 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 10615 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10616 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10617 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10618 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 10619 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10620 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10621 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10622 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 10623 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10624 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10625 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10626 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 10627 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 10628 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 10629 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 10630 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 10631 | } B; |
mbed_official | 146:f64d43ff0c18 | 10632 | } hw_aips_pacrm_t; |
mbed_official | 146:f64d43ff0c18 | 10633 | #endif |
mbed_official | 146:f64d43ff0c18 | 10634 | |
mbed_official | 146:f64d43ff0c18 | 10635 | /*! |
mbed_official | 146:f64d43ff0c18 | 10636 | * @name Constants and macros for entire AIPS_PACRM register |
mbed_official | 146:f64d43ff0c18 | 10637 | */ |
mbed_official | 146:f64d43ff0c18 | 10638 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10639 | #define HW_AIPS_PACRM_ADDR(x) (REGS_AIPS_BASE(x) + 0x60U) |
mbed_official | 146:f64d43ff0c18 | 10640 | |
mbed_official | 146:f64d43ff0c18 | 10641 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10642 | #define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 10643 | #define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U) |
mbed_official | 146:f64d43ff0c18 | 10644 | #define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 10645 | #define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 10646 | #define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 10647 | #define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 10648 | #endif |
mbed_official | 146:f64d43ff0c18 | 10649 | //@} |
mbed_official | 146:f64d43ff0c18 | 10650 | |
mbed_official | 146:f64d43ff0c18 | 10651 | /* |
mbed_official | 146:f64d43ff0c18 | 10652 | * Constants & macros for individual AIPS_PACRM bitfields |
mbed_official | 146:f64d43ff0c18 | 10653 | */ |
mbed_official | 146:f64d43ff0c18 | 10654 | |
mbed_official | 146:f64d43ff0c18 | 10655 | /*! |
mbed_official | 146:f64d43ff0c18 | 10656 | * @name Register AIPS_PACRM, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 10657 | * |
mbed_official | 146:f64d43ff0c18 | 10658 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10659 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10660 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10661 | * |
mbed_official | 146:f64d43ff0c18 | 10662 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10663 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10664 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10665 | */ |
mbed_official | 146:f64d43ff0c18 | 10666 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10667 | #define BP_AIPS_PACRM_TP7 (0U) //!< Bit position for AIPS_PACRM_TP7. |
mbed_official | 146:f64d43ff0c18 | 10668 | #define BM_AIPS_PACRM_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRM_TP7. |
mbed_official | 146:f64d43ff0c18 | 10669 | #define BS_AIPS_PACRM_TP7 (1U) //!< Bit field size in bits for AIPS_PACRM_TP7. |
mbed_official | 146:f64d43ff0c18 | 10670 | |
mbed_official | 146:f64d43ff0c18 | 10671 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10672 | //! @brief Read current value of the AIPS_PACRM_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 10673 | #define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7)) |
mbed_official | 146:f64d43ff0c18 | 10674 | #endif |
mbed_official | 146:f64d43ff0c18 | 10675 | |
mbed_official | 146:f64d43ff0c18 | 10676 | //! @brief Format value for bitfield AIPS_PACRM_TP7. |
mbed_official | 146:f64d43ff0c18 | 10677 | #define BF_AIPS_PACRM_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP7), uint32_t) & BM_AIPS_PACRM_TP7) |
mbed_official | 146:f64d43ff0c18 | 10678 | |
mbed_official | 146:f64d43ff0c18 | 10679 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10680 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10681 | #define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10682 | #endif |
mbed_official | 146:f64d43ff0c18 | 10683 | //@} |
mbed_official | 146:f64d43ff0c18 | 10684 | |
mbed_official | 146:f64d43ff0c18 | 10685 | /*! |
mbed_official | 146:f64d43ff0c18 | 10686 | * @name Register AIPS_PACRM, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 10687 | * |
mbed_official | 146:f64d43ff0c18 | 10688 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10689 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10690 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10691 | * |
mbed_official | 146:f64d43ff0c18 | 10692 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10693 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10694 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10695 | */ |
mbed_official | 146:f64d43ff0c18 | 10696 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10697 | #define BP_AIPS_PACRM_WP7 (1U) //!< Bit position for AIPS_PACRM_WP7. |
mbed_official | 146:f64d43ff0c18 | 10698 | #define BM_AIPS_PACRM_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRM_WP7. |
mbed_official | 146:f64d43ff0c18 | 10699 | #define BS_AIPS_PACRM_WP7 (1U) //!< Bit field size in bits for AIPS_PACRM_WP7. |
mbed_official | 146:f64d43ff0c18 | 10700 | |
mbed_official | 146:f64d43ff0c18 | 10701 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10702 | //! @brief Read current value of the AIPS_PACRM_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 10703 | #define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7)) |
mbed_official | 146:f64d43ff0c18 | 10704 | #endif |
mbed_official | 146:f64d43ff0c18 | 10705 | |
mbed_official | 146:f64d43ff0c18 | 10706 | //! @brief Format value for bitfield AIPS_PACRM_WP7. |
mbed_official | 146:f64d43ff0c18 | 10707 | #define BF_AIPS_PACRM_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP7), uint32_t) & BM_AIPS_PACRM_WP7) |
mbed_official | 146:f64d43ff0c18 | 10708 | |
mbed_official | 146:f64d43ff0c18 | 10709 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10710 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10711 | #define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10712 | #endif |
mbed_official | 146:f64d43ff0c18 | 10713 | //@} |
mbed_official | 146:f64d43ff0c18 | 10714 | |
mbed_official | 146:f64d43ff0c18 | 10715 | /*! |
mbed_official | 146:f64d43ff0c18 | 10716 | * @name Register AIPS_PACRM, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 10717 | * |
mbed_official | 146:f64d43ff0c18 | 10718 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10719 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10720 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 10721 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10722 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10723 | * |
mbed_official | 146:f64d43ff0c18 | 10724 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10725 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10726 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10727 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10728 | */ |
mbed_official | 146:f64d43ff0c18 | 10729 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10730 | #define BP_AIPS_PACRM_SP7 (2U) //!< Bit position for AIPS_PACRM_SP7. |
mbed_official | 146:f64d43ff0c18 | 10731 | #define BM_AIPS_PACRM_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRM_SP7. |
mbed_official | 146:f64d43ff0c18 | 10732 | #define BS_AIPS_PACRM_SP7 (1U) //!< Bit field size in bits for AIPS_PACRM_SP7. |
mbed_official | 146:f64d43ff0c18 | 10733 | |
mbed_official | 146:f64d43ff0c18 | 10734 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10735 | //! @brief Read current value of the AIPS_PACRM_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 10736 | #define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7)) |
mbed_official | 146:f64d43ff0c18 | 10737 | #endif |
mbed_official | 146:f64d43ff0c18 | 10738 | |
mbed_official | 146:f64d43ff0c18 | 10739 | //! @brief Format value for bitfield AIPS_PACRM_SP7. |
mbed_official | 146:f64d43ff0c18 | 10740 | #define BF_AIPS_PACRM_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP7), uint32_t) & BM_AIPS_PACRM_SP7) |
mbed_official | 146:f64d43ff0c18 | 10741 | |
mbed_official | 146:f64d43ff0c18 | 10742 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10743 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10744 | #define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10745 | #endif |
mbed_official | 146:f64d43ff0c18 | 10746 | //@} |
mbed_official | 146:f64d43ff0c18 | 10747 | |
mbed_official | 146:f64d43ff0c18 | 10748 | /*! |
mbed_official | 146:f64d43ff0c18 | 10749 | * @name Register AIPS_PACRM, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 10750 | * |
mbed_official | 146:f64d43ff0c18 | 10751 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10752 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10753 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10754 | * |
mbed_official | 146:f64d43ff0c18 | 10755 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10756 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10757 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10758 | */ |
mbed_official | 146:f64d43ff0c18 | 10759 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10760 | #define BP_AIPS_PACRM_TP6 (4U) //!< Bit position for AIPS_PACRM_TP6. |
mbed_official | 146:f64d43ff0c18 | 10761 | #define BM_AIPS_PACRM_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRM_TP6. |
mbed_official | 146:f64d43ff0c18 | 10762 | #define BS_AIPS_PACRM_TP6 (1U) //!< Bit field size in bits for AIPS_PACRM_TP6. |
mbed_official | 146:f64d43ff0c18 | 10763 | |
mbed_official | 146:f64d43ff0c18 | 10764 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10765 | //! @brief Read current value of the AIPS_PACRM_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 10766 | #define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6)) |
mbed_official | 146:f64d43ff0c18 | 10767 | #endif |
mbed_official | 146:f64d43ff0c18 | 10768 | |
mbed_official | 146:f64d43ff0c18 | 10769 | //! @brief Format value for bitfield AIPS_PACRM_TP6. |
mbed_official | 146:f64d43ff0c18 | 10770 | #define BF_AIPS_PACRM_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP6), uint32_t) & BM_AIPS_PACRM_TP6) |
mbed_official | 146:f64d43ff0c18 | 10771 | |
mbed_official | 146:f64d43ff0c18 | 10772 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10773 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10774 | #define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10775 | #endif |
mbed_official | 146:f64d43ff0c18 | 10776 | //@} |
mbed_official | 146:f64d43ff0c18 | 10777 | |
mbed_official | 146:f64d43ff0c18 | 10778 | /*! |
mbed_official | 146:f64d43ff0c18 | 10779 | * @name Register AIPS_PACRM, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 10780 | * |
mbed_official | 146:f64d43ff0c18 | 10781 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10782 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10783 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10784 | * |
mbed_official | 146:f64d43ff0c18 | 10785 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10786 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10787 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10788 | */ |
mbed_official | 146:f64d43ff0c18 | 10789 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10790 | #define BP_AIPS_PACRM_WP6 (5U) //!< Bit position for AIPS_PACRM_WP6. |
mbed_official | 146:f64d43ff0c18 | 10791 | #define BM_AIPS_PACRM_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRM_WP6. |
mbed_official | 146:f64d43ff0c18 | 10792 | #define BS_AIPS_PACRM_WP6 (1U) //!< Bit field size in bits for AIPS_PACRM_WP6. |
mbed_official | 146:f64d43ff0c18 | 10793 | |
mbed_official | 146:f64d43ff0c18 | 10794 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10795 | //! @brief Read current value of the AIPS_PACRM_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 10796 | #define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6)) |
mbed_official | 146:f64d43ff0c18 | 10797 | #endif |
mbed_official | 146:f64d43ff0c18 | 10798 | |
mbed_official | 146:f64d43ff0c18 | 10799 | //! @brief Format value for bitfield AIPS_PACRM_WP6. |
mbed_official | 146:f64d43ff0c18 | 10800 | #define BF_AIPS_PACRM_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP6), uint32_t) & BM_AIPS_PACRM_WP6) |
mbed_official | 146:f64d43ff0c18 | 10801 | |
mbed_official | 146:f64d43ff0c18 | 10802 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10803 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10804 | #define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10805 | #endif |
mbed_official | 146:f64d43ff0c18 | 10806 | //@} |
mbed_official | 146:f64d43ff0c18 | 10807 | |
mbed_official | 146:f64d43ff0c18 | 10808 | /*! |
mbed_official | 146:f64d43ff0c18 | 10809 | * @name Register AIPS_PACRM, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 10810 | * |
mbed_official | 146:f64d43ff0c18 | 10811 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10812 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10813 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 10814 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10815 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10816 | * |
mbed_official | 146:f64d43ff0c18 | 10817 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10818 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10819 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10820 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10821 | */ |
mbed_official | 146:f64d43ff0c18 | 10822 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10823 | #define BP_AIPS_PACRM_SP6 (6U) //!< Bit position for AIPS_PACRM_SP6. |
mbed_official | 146:f64d43ff0c18 | 10824 | #define BM_AIPS_PACRM_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRM_SP6. |
mbed_official | 146:f64d43ff0c18 | 10825 | #define BS_AIPS_PACRM_SP6 (1U) //!< Bit field size in bits for AIPS_PACRM_SP6. |
mbed_official | 146:f64d43ff0c18 | 10826 | |
mbed_official | 146:f64d43ff0c18 | 10827 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10828 | //! @brief Read current value of the AIPS_PACRM_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 10829 | #define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6)) |
mbed_official | 146:f64d43ff0c18 | 10830 | #endif |
mbed_official | 146:f64d43ff0c18 | 10831 | |
mbed_official | 146:f64d43ff0c18 | 10832 | //! @brief Format value for bitfield AIPS_PACRM_SP6. |
mbed_official | 146:f64d43ff0c18 | 10833 | #define BF_AIPS_PACRM_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP6), uint32_t) & BM_AIPS_PACRM_SP6) |
mbed_official | 146:f64d43ff0c18 | 10834 | |
mbed_official | 146:f64d43ff0c18 | 10835 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10836 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10837 | #define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10838 | #endif |
mbed_official | 146:f64d43ff0c18 | 10839 | //@} |
mbed_official | 146:f64d43ff0c18 | 10840 | |
mbed_official | 146:f64d43ff0c18 | 10841 | /*! |
mbed_official | 146:f64d43ff0c18 | 10842 | * @name Register AIPS_PACRM, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 10843 | * |
mbed_official | 146:f64d43ff0c18 | 10844 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10845 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10846 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10847 | * |
mbed_official | 146:f64d43ff0c18 | 10848 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10849 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10850 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10851 | */ |
mbed_official | 146:f64d43ff0c18 | 10852 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10853 | #define BP_AIPS_PACRM_TP5 (8U) //!< Bit position for AIPS_PACRM_TP5. |
mbed_official | 146:f64d43ff0c18 | 10854 | #define BM_AIPS_PACRM_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRM_TP5. |
mbed_official | 146:f64d43ff0c18 | 10855 | #define BS_AIPS_PACRM_TP5 (1U) //!< Bit field size in bits for AIPS_PACRM_TP5. |
mbed_official | 146:f64d43ff0c18 | 10856 | |
mbed_official | 146:f64d43ff0c18 | 10857 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10858 | //! @brief Read current value of the AIPS_PACRM_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 10859 | #define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5)) |
mbed_official | 146:f64d43ff0c18 | 10860 | #endif |
mbed_official | 146:f64d43ff0c18 | 10861 | |
mbed_official | 146:f64d43ff0c18 | 10862 | //! @brief Format value for bitfield AIPS_PACRM_TP5. |
mbed_official | 146:f64d43ff0c18 | 10863 | #define BF_AIPS_PACRM_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP5), uint32_t) & BM_AIPS_PACRM_TP5) |
mbed_official | 146:f64d43ff0c18 | 10864 | |
mbed_official | 146:f64d43ff0c18 | 10865 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10866 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10867 | #define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10868 | #endif |
mbed_official | 146:f64d43ff0c18 | 10869 | //@} |
mbed_official | 146:f64d43ff0c18 | 10870 | |
mbed_official | 146:f64d43ff0c18 | 10871 | /*! |
mbed_official | 146:f64d43ff0c18 | 10872 | * @name Register AIPS_PACRM, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 10873 | * |
mbed_official | 146:f64d43ff0c18 | 10874 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10875 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10876 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10877 | * |
mbed_official | 146:f64d43ff0c18 | 10878 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10879 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10880 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10881 | */ |
mbed_official | 146:f64d43ff0c18 | 10882 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10883 | #define BP_AIPS_PACRM_WP5 (9U) //!< Bit position for AIPS_PACRM_WP5. |
mbed_official | 146:f64d43ff0c18 | 10884 | #define BM_AIPS_PACRM_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRM_WP5. |
mbed_official | 146:f64d43ff0c18 | 10885 | #define BS_AIPS_PACRM_WP5 (1U) //!< Bit field size in bits for AIPS_PACRM_WP5. |
mbed_official | 146:f64d43ff0c18 | 10886 | |
mbed_official | 146:f64d43ff0c18 | 10887 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10888 | //! @brief Read current value of the AIPS_PACRM_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 10889 | #define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5)) |
mbed_official | 146:f64d43ff0c18 | 10890 | #endif |
mbed_official | 146:f64d43ff0c18 | 10891 | |
mbed_official | 146:f64d43ff0c18 | 10892 | //! @brief Format value for bitfield AIPS_PACRM_WP5. |
mbed_official | 146:f64d43ff0c18 | 10893 | #define BF_AIPS_PACRM_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP5), uint32_t) & BM_AIPS_PACRM_WP5) |
mbed_official | 146:f64d43ff0c18 | 10894 | |
mbed_official | 146:f64d43ff0c18 | 10895 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10896 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10897 | #define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10898 | #endif |
mbed_official | 146:f64d43ff0c18 | 10899 | //@} |
mbed_official | 146:f64d43ff0c18 | 10900 | |
mbed_official | 146:f64d43ff0c18 | 10901 | /*! |
mbed_official | 146:f64d43ff0c18 | 10902 | * @name Register AIPS_PACRM, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 10903 | * |
mbed_official | 146:f64d43ff0c18 | 10904 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10905 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10906 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 10907 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 10908 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 10909 | * |
mbed_official | 146:f64d43ff0c18 | 10910 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10911 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10912 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 10913 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 10914 | */ |
mbed_official | 146:f64d43ff0c18 | 10915 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10916 | #define BP_AIPS_PACRM_SP5 (10U) //!< Bit position for AIPS_PACRM_SP5. |
mbed_official | 146:f64d43ff0c18 | 10917 | #define BM_AIPS_PACRM_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRM_SP5. |
mbed_official | 146:f64d43ff0c18 | 10918 | #define BS_AIPS_PACRM_SP5 (1U) //!< Bit field size in bits for AIPS_PACRM_SP5. |
mbed_official | 146:f64d43ff0c18 | 10919 | |
mbed_official | 146:f64d43ff0c18 | 10920 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10921 | //! @brief Read current value of the AIPS_PACRM_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 10922 | #define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5)) |
mbed_official | 146:f64d43ff0c18 | 10923 | #endif |
mbed_official | 146:f64d43ff0c18 | 10924 | |
mbed_official | 146:f64d43ff0c18 | 10925 | //! @brief Format value for bitfield AIPS_PACRM_SP5. |
mbed_official | 146:f64d43ff0c18 | 10926 | #define BF_AIPS_PACRM_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP5), uint32_t) & BM_AIPS_PACRM_SP5) |
mbed_official | 146:f64d43ff0c18 | 10927 | |
mbed_official | 146:f64d43ff0c18 | 10928 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10929 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10930 | #define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10931 | #endif |
mbed_official | 146:f64d43ff0c18 | 10932 | //@} |
mbed_official | 146:f64d43ff0c18 | 10933 | |
mbed_official | 146:f64d43ff0c18 | 10934 | /*! |
mbed_official | 146:f64d43ff0c18 | 10935 | * @name Register AIPS_PACRM, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 10936 | * |
mbed_official | 146:f64d43ff0c18 | 10937 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 10938 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 10939 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10940 | * |
mbed_official | 146:f64d43ff0c18 | 10941 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10942 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 10943 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 10944 | */ |
mbed_official | 146:f64d43ff0c18 | 10945 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10946 | #define BP_AIPS_PACRM_TP4 (12U) //!< Bit position for AIPS_PACRM_TP4. |
mbed_official | 146:f64d43ff0c18 | 10947 | #define BM_AIPS_PACRM_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRM_TP4. |
mbed_official | 146:f64d43ff0c18 | 10948 | #define BS_AIPS_PACRM_TP4 (1U) //!< Bit field size in bits for AIPS_PACRM_TP4. |
mbed_official | 146:f64d43ff0c18 | 10949 | |
mbed_official | 146:f64d43ff0c18 | 10950 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10951 | //! @brief Read current value of the AIPS_PACRM_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 10952 | #define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4)) |
mbed_official | 146:f64d43ff0c18 | 10953 | #endif |
mbed_official | 146:f64d43ff0c18 | 10954 | |
mbed_official | 146:f64d43ff0c18 | 10955 | //! @brief Format value for bitfield AIPS_PACRM_TP4. |
mbed_official | 146:f64d43ff0c18 | 10956 | #define BF_AIPS_PACRM_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP4), uint32_t) & BM_AIPS_PACRM_TP4) |
mbed_official | 146:f64d43ff0c18 | 10957 | |
mbed_official | 146:f64d43ff0c18 | 10958 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10959 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10960 | #define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10961 | #endif |
mbed_official | 146:f64d43ff0c18 | 10962 | //@} |
mbed_official | 146:f64d43ff0c18 | 10963 | |
mbed_official | 146:f64d43ff0c18 | 10964 | /*! |
mbed_official | 146:f64d43ff0c18 | 10965 | * @name Register AIPS_PACRM, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 10966 | * |
mbed_official | 146:f64d43ff0c18 | 10967 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 10968 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 10969 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 10970 | * |
mbed_official | 146:f64d43ff0c18 | 10971 | * Values: |
mbed_official | 146:f64d43ff0c18 | 10972 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 10973 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 10974 | */ |
mbed_official | 146:f64d43ff0c18 | 10975 | //@{ |
mbed_official | 146:f64d43ff0c18 | 10976 | #define BP_AIPS_PACRM_WP4 (13U) //!< Bit position for AIPS_PACRM_WP4. |
mbed_official | 146:f64d43ff0c18 | 10977 | #define BM_AIPS_PACRM_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRM_WP4. |
mbed_official | 146:f64d43ff0c18 | 10978 | #define BS_AIPS_PACRM_WP4 (1U) //!< Bit field size in bits for AIPS_PACRM_WP4. |
mbed_official | 146:f64d43ff0c18 | 10979 | |
mbed_official | 146:f64d43ff0c18 | 10980 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10981 | //! @brief Read current value of the AIPS_PACRM_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 10982 | #define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4)) |
mbed_official | 146:f64d43ff0c18 | 10983 | #endif |
mbed_official | 146:f64d43ff0c18 | 10984 | |
mbed_official | 146:f64d43ff0c18 | 10985 | //! @brief Format value for bitfield AIPS_PACRM_WP4. |
mbed_official | 146:f64d43ff0c18 | 10986 | #define BF_AIPS_PACRM_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP4), uint32_t) & BM_AIPS_PACRM_WP4) |
mbed_official | 146:f64d43ff0c18 | 10987 | |
mbed_official | 146:f64d43ff0c18 | 10988 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 10989 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 10990 | #define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 10991 | #endif |
mbed_official | 146:f64d43ff0c18 | 10992 | //@} |
mbed_official | 146:f64d43ff0c18 | 10993 | |
mbed_official | 146:f64d43ff0c18 | 10994 | /*! |
mbed_official | 146:f64d43ff0c18 | 10995 | * @name Register AIPS_PACRM, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 10996 | * |
mbed_official | 146:f64d43ff0c18 | 10997 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 10998 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 10999 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 11000 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 11001 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 11002 | * |
mbed_official | 146:f64d43ff0c18 | 11003 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11004 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11005 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11006 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11007 | */ |
mbed_official | 146:f64d43ff0c18 | 11008 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11009 | #define BP_AIPS_PACRM_SP4 (14U) //!< Bit position for AIPS_PACRM_SP4. |
mbed_official | 146:f64d43ff0c18 | 11010 | #define BM_AIPS_PACRM_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRM_SP4. |
mbed_official | 146:f64d43ff0c18 | 11011 | #define BS_AIPS_PACRM_SP4 (1U) //!< Bit field size in bits for AIPS_PACRM_SP4. |
mbed_official | 146:f64d43ff0c18 | 11012 | |
mbed_official | 146:f64d43ff0c18 | 11013 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11014 | //! @brief Read current value of the AIPS_PACRM_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 11015 | #define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4)) |
mbed_official | 146:f64d43ff0c18 | 11016 | #endif |
mbed_official | 146:f64d43ff0c18 | 11017 | |
mbed_official | 146:f64d43ff0c18 | 11018 | //! @brief Format value for bitfield AIPS_PACRM_SP4. |
mbed_official | 146:f64d43ff0c18 | 11019 | #define BF_AIPS_PACRM_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP4), uint32_t) & BM_AIPS_PACRM_SP4) |
mbed_official | 146:f64d43ff0c18 | 11020 | |
mbed_official | 146:f64d43ff0c18 | 11021 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11022 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11023 | #define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11024 | #endif |
mbed_official | 146:f64d43ff0c18 | 11025 | //@} |
mbed_official | 146:f64d43ff0c18 | 11026 | |
mbed_official | 146:f64d43ff0c18 | 11027 | /*! |
mbed_official | 146:f64d43ff0c18 | 11028 | * @name Register AIPS_PACRM, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 11029 | * |
mbed_official | 146:f64d43ff0c18 | 11030 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11031 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11032 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11033 | * |
mbed_official | 146:f64d43ff0c18 | 11034 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11035 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11036 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11037 | */ |
mbed_official | 146:f64d43ff0c18 | 11038 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11039 | #define BP_AIPS_PACRM_TP3 (16U) //!< Bit position for AIPS_PACRM_TP3. |
mbed_official | 146:f64d43ff0c18 | 11040 | #define BM_AIPS_PACRM_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRM_TP3. |
mbed_official | 146:f64d43ff0c18 | 11041 | #define BS_AIPS_PACRM_TP3 (1U) //!< Bit field size in bits for AIPS_PACRM_TP3. |
mbed_official | 146:f64d43ff0c18 | 11042 | |
mbed_official | 146:f64d43ff0c18 | 11043 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11044 | //! @brief Read current value of the AIPS_PACRM_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 11045 | #define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3)) |
mbed_official | 146:f64d43ff0c18 | 11046 | #endif |
mbed_official | 146:f64d43ff0c18 | 11047 | |
mbed_official | 146:f64d43ff0c18 | 11048 | //! @brief Format value for bitfield AIPS_PACRM_TP3. |
mbed_official | 146:f64d43ff0c18 | 11049 | #define BF_AIPS_PACRM_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP3), uint32_t) & BM_AIPS_PACRM_TP3) |
mbed_official | 146:f64d43ff0c18 | 11050 | |
mbed_official | 146:f64d43ff0c18 | 11051 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11052 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11053 | #define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11054 | #endif |
mbed_official | 146:f64d43ff0c18 | 11055 | //@} |
mbed_official | 146:f64d43ff0c18 | 11056 | |
mbed_official | 146:f64d43ff0c18 | 11057 | /*! |
mbed_official | 146:f64d43ff0c18 | 11058 | * @name Register AIPS_PACRM, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 11059 | * |
mbed_official | 146:f64d43ff0c18 | 11060 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 11061 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 11062 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11063 | * |
mbed_official | 146:f64d43ff0c18 | 11064 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11065 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11066 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11067 | */ |
mbed_official | 146:f64d43ff0c18 | 11068 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11069 | #define BP_AIPS_PACRM_WP3 (17U) //!< Bit position for AIPS_PACRM_WP3. |
mbed_official | 146:f64d43ff0c18 | 11070 | #define BM_AIPS_PACRM_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRM_WP3. |
mbed_official | 146:f64d43ff0c18 | 11071 | #define BS_AIPS_PACRM_WP3 (1U) //!< Bit field size in bits for AIPS_PACRM_WP3. |
mbed_official | 146:f64d43ff0c18 | 11072 | |
mbed_official | 146:f64d43ff0c18 | 11073 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11074 | //! @brief Read current value of the AIPS_PACRM_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 11075 | #define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3)) |
mbed_official | 146:f64d43ff0c18 | 11076 | #endif |
mbed_official | 146:f64d43ff0c18 | 11077 | |
mbed_official | 146:f64d43ff0c18 | 11078 | //! @brief Format value for bitfield AIPS_PACRM_WP3. |
mbed_official | 146:f64d43ff0c18 | 11079 | #define BF_AIPS_PACRM_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP3), uint32_t) & BM_AIPS_PACRM_WP3) |
mbed_official | 146:f64d43ff0c18 | 11080 | |
mbed_official | 146:f64d43ff0c18 | 11081 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11082 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11083 | #define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11084 | #endif |
mbed_official | 146:f64d43ff0c18 | 11085 | //@} |
mbed_official | 146:f64d43ff0c18 | 11086 | |
mbed_official | 146:f64d43ff0c18 | 11087 | /*! |
mbed_official | 146:f64d43ff0c18 | 11088 | * @name Register AIPS_PACRM, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 11089 | * |
mbed_official | 146:f64d43ff0c18 | 11090 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11091 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11092 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 11093 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11094 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11095 | * |
mbed_official | 146:f64d43ff0c18 | 11096 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11097 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11098 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11099 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11100 | */ |
mbed_official | 146:f64d43ff0c18 | 11101 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11102 | #define BP_AIPS_PACRM_SP3 (18U) //!< Bit position for AIPS_PACRM_SP3. |
mbed_official | 146:f64d43ff0c18 | 11103 | #define BM_AIPS_PACRM_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRM_SP3. |
mbed_official | 146:f64d43ff0c18 | 11104 | #define BS_AIPS_PACRM_SP3 (1U) //!< Bit field size in bits for AIPS_PACRM_SP3. |
mbed_official | 146:f64d43ff0c18 | 11105 | |
mbed_official | 146:f64d43ff0c18 | 11106 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11107 | //! @brief Read current value of the AIPS_PACRM_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 11108 | #define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3)) |
mbed_official | 146:f64d43ff0c18 | 11109 | #endif |
mbed_official | 146:f64d43ff0c18 | 11110 | |
mbed_official | 146:f64d43ff0c18 | 11111 | //! @brief Format value for bitfield AIPS_PACRM_SP3. |
mbed_official | 146:f64d43ff0c18 | 11112 | #define BF_AIPS_PACRM_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP3), uint32_t) & BM_AIPS_PACRM_SP3) |
mbed_official | 146:f64d43ff0c18 | 11113 | |
mbed_official | 146:f64d43ff0c18 | 11114 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11115 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11116 | #define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11117 | #endif |
mbed_official | 146:f64d43ff0c18 | 11118 | //@} |
mbed_official | 146:f64d43ff0c18 | 11119 | |
mbed_official | 146:f64d43ff0c18 | 11120 | /*! |
mbed_official | 146:f64d43ff0c18 | 11121 | * @name Register AIPS_PACRM, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 11122 | * |
mbed_official | 146:f64d43ff0c18 | 11123 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11124 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11125 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11126 | * |
mbed_official | 146:f64d43ff0c18 | 11127 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11128 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11129 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11130 | */ |
mbed_official | 146:f64d43ff0c18 | 11131 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11132 | #define BP_AIPS_PACRM_TP2 (20U) //!< Bit position for AIPS_PACRM_TP2. |
mbed_official | 146:f64d43ff0c18 | 11133 | #define BM_AIPS_PACRM_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRM_TP2. |
mbed_official | 146:f64d43ff0c18 | 11134 | #define BS_AIPS_PACRM_TP2 (1U) //!< Bit field size in bits for AIPS_PACRM_TP2. |
mbed_official | 146:f64d43ff0c18 | 11135 | |
mbed_official | 146:f64d43ff0c18 | 11136 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11137 | //! @brief Read current value of the AIPS_PACRM_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 11138 | #define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2)) |
mbed_official | 146:f64d43ff0c18 | 11139 | #endif |
mbed_official | 146:f64d43ff0c18 | 11140 | |
mbed_official | 146:f64d43ff0c18 | 11141 | //! @brief Format value for bitfield AIPS_PACRM_TP2. |
mbed_official | 146:f64d43ff0c18 | 11142 | #define BF_AIPS_PACRM_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP2), uint32_t) & BM_AIPS_PACRM_TP2) |
mbed_official | 146:f64d43ff0c18 | 11143 | |
mbed_official | 146:f64d43ff0c18 | 11144 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11145 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11146 | #define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11147 | #endif |
mbed_official | 146:f64d43ff0c18 | 11148 | //@} |
mbed_official | 146:f64d43ff0c18 | 11149 | |
mbed_official | 146:f64d43ff0c18 | 11150 | /*! |
mbed_official | 146:f64d43ff0c18 | 11151 | * @name Register AIPS_PACRM, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 11152 | * |
mbed_official | 146:f64d43ff0c18 | 11153 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11154 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11155 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11156 | * |
mbed_official | 146:f64d43ff0c18 | 11157 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11158 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11159 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11160 | */ |
mbed_official | 146:f64d43ff0c18 | 11161 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11162 | #define BP_AIPS_PACRM_WP2 (21U) //!< Bit position for AIPS_PACRM_WP2. |
mbed_official | 146:f64d43ff0c18 | 11163 | #define BM_AIPS_PACRM_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRM_WP2. |
mbed_official | 146:f64d43ff0c18 | 11164 | #define BS_AIPS_PACRM_WP2 (1U) //!< Bit field size in bits for AIPS_PACRM_WP2. |
mbed_official | 146:f64d43ff0c18 | 11165 | |
mbed_official | 146:f64d43ff0c18 | 11166 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11167 | //! @brief Read current value of the AIPS_PACRM_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 11168 | #define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2)) |
mbed_official | 146:f64d43ff0c18 | 11169 | #endif |
mbed_official | 146:f64d43ff0c18 | 11170 | |
mbed_official | 146:f64d43ff0c18 | 11171 | //! @brief Format value for bitfield AIPS_PACRM_WP2. |
mbed_official | 146:f64d43ff0c18 | 11172 | #define BF_AIPS_PACRM_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP2), uint32_t) & BM_AIPS_PACRM_WP2) |
mbed_official | 146:f64d43ff0c18 | 11173 | |
mbed_official | 146:f64d43ff0c18 | 11174 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11175 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11176 | #define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11177 | #endif |
mbed_official | 146:f64d43ff0c18 | 11178 | //@} |
mbed_official | 146:f64d43ff0c18 | 11179 | |
mbed_official | 146:f64d43ff0c18 | 11180 | /*! |
mbed_official | 146:f64d43ff0c18 | 11181 | * @name Register AIPS_PACRM, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 11182 | * |
mbed_official | 146:f64d43ff0c18 | 11183 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11184 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11185 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 11186 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 11187 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 11188 | * |
mbed_official | 146:f64d43ff0c18 | 11189 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11190 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11191 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11192 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11193 | */ |
mbed_official | 146:f64d43ff0c18 | 11194 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11195 | #define BP_AIPS_PACRM_SP2 (22U) //!< Bit position for AIPS_PACRM_SP2. |
mbed_official | 146:f64d43ff0c18 | 11196 | #define BM_AIPS_PACRM_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRM_SP2. |
mbed_official | 146:f64d43ff0c18 | 11197 | #define BS_AIPS_PACRM_SP2 (1U) //!< Bit field size in bits for AIPS_PACRM_SP2. |
mbed_official | 146:f64d43ff0c18 | 11198 | |
mbed_official | 146:f64d43ff0c18 | 11199 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11200 | //! @brief Read current value of the AIPS_PACRM_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 11201 | #define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2)) |
mbed_official | 146:f64d43ff0c18 | 11202 | #endif |
mbed_official | 146:f64d43ff0c18 | 11203 | |
mbed_official | 146:f64d43ff0c18 | 11204 | //! @brief Format value for bitfield AIPS_PACRM_SP2. |
mbed_official | 146:f64d43ff0c18 | 11205 | #define BF_AIPS_PACRM_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP2), uint32_t) & BM_AIPS_PACRM_SP2) |
mbed_official | 146:f64d43ff0c18 | 11206 | |
mbed_official | 146:f64d43ff0c18 | 11207 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11208 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11209 | #define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11210 | #endif |
mbed_official | 146:f64d43ff0c18 | 11211 | //@} |
mbed_official | 146:f64d43ff0c18 | 11212 | |
mbed_official | 146:f64d43ff0c18 | 11213 | /*! |
mbed_official | 146:f64d43ff0c18 | 11214 | * @name Register AIPS_PACRM, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 11215 | * |
mbed_official | 146:f64d43ff0c18 | 11216 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11217 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11218 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11219 | * |
mbed_official | 146:f64d43ff0c18 | 11220 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11221 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11222 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11223 | */ |
mbed_official | 146:f64d43ff0c18 | 11224 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11225 | #define BP_AIPS_PACRM_TP1 (24U) //!< Bit position for AIPS_PACRM_TP1. |
mbed_official | 146:f64d43ff0c18 | 11226 | #define BM_AIPS_PACRM_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRM_TP1. |
mbed_official | 146:f64d43ff0c18 | 11227 | #define BS_AIPS_PACRM_TP1 (1U) //!< Bit field size in bits for AIPS_PACRM_TP1. |
mbed_official | 146:f64d43ff0c18 | 11228 | |
mbed_official | 146:f64d43ff0c18 | 11229 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11230 | //! @brief Read current value of the AIPS_PACRM_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 11231 | #define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1)) |
mbed_official | 146:f64d43ff0c18 | 11232 | #endif |
mbed_official | 146:f64d43ff0c18 | 11233 | |
mbed_official | 146:f64d43ff0c18 | 11234 | //! @brief Format value for bitfield AIPS_PACRM_TP1. |
mbed_official | 146:f64d43ff0c18 | 11235 | #define BF_AIPS_PACRM_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP1), uint32_t) & BM_AIPS_PACRM_TP1) |
mbed_official | 146:f64d43ff0c18 | 11236 | |
mbed_official | 146:f64d43ff0c18 | 11237 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11238 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11239 | #define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11240 | #endif |
mbed_official | 146:f64d43ff0c18 | 11241 | //@} |
mbed_official | 146:f64d43ff0c18 | 11242 | |
mbed_official | 146:f64d43ff0c18 | 11243 | /*! |
mbed_official | 146:f64d43ff0c18 | 11244 | * @name Register AIPS_PACRM, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 11245 | * |
mbed_official | 146:f64d43ff0c18 | 11246 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11247 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11248 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11249 | * |
mbed_official | 146:f64d43ff0c18 | 11250 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11251 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11252 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11253 | */ |
mbed_official | 146:f64d43ff0c18 | 11254 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11255 | #define BP_AIPS_PACRM_WP1 (25U) //!< Bit position for AIPS_PACRM_WP1. |
mbed_official | 146:f64d43ff0c18 | 11256 | #define BM_AIPS_PACRM_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRM_WP1. |
mbed_official | 146:f64d43ff0c18 | 11257 | #define BS_AIPS_PACRM_WP1 (1U) //!< Bit field size in bits for AIPS_PACRM_WP1. |
mbed_official | 146:f64d43ff0c18 | 11258 | |
mbed_official | 146:f64d43ff0c18 | 11259 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11260 | //! @brief Read current value of the AIPS_PACRM_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 11261 | #define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1)) |
mbed_official | 146:f64d43ff0c18 | 11262 | #endif |
mbed_official | 146:f64d43ff0c18 | 11263 | |
mbed_official | 146:f64d43ff0c18 | 11264 | //! @brief Format value for bitfield AIPS_PACRM_WP1. |
mbed_official | 146:f64d43ff0c18 | 11265 | #define BF_AIPS_PACRM_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP1), uint32_t) & BM_AIPS_PACRM_WP1) |
mbed_official | 146:f64d43ff0c18 | 11266 | |
mbed_official | 146:f64d43ff0c18 | 11267 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11268 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11269 | #define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11270 | #endif |
mbed_official | 146:f64d43ff0c18 | 11271 | //@} |
mbed_official | 146:f64d43ff0c18 | 11272 | |
mbed_official | 146:f64d43ff0c18 | 11273 | /*! |
mbed_official | 146:f64d43ff0c18 | 11274 | * @name Register AIPS_PACRM, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 11275 | * |
mbed_official | 146:f64d43ff0c18 | 11276 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11277 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11278 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 11279 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11280 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11281 | * |
mbed_official | 146:f64d43ff0c18 | 11282 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11283 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11284 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11285 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11286 | */ |
mbed_official | 146:f64d43ff0c18 | 11287 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11288 | #define BP_AIPS_PACRM_SP1 (26U) //!< Bit position for AIPS_PACRM_SP1. |
mbed_official | 146:f64d43ff0c18 | 11289 | #define BM_AIPS_PACRM_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRM_SP1. |
mbed_official | 146:f64d43ff0c18 | 11290 | #define BS_AIPS_PACRM_SP1 (1U) //!< Bit field size in bits for AIPS_PACRM_SP1. |
mbed_official | 146:f64d43ff0c18 | 11291 | |
mbed_official | 146:f64d43ff0c18 | 11292 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11293 | //! @brief Read current value of the AIPS_PACRM_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 11294 | #define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1)) |
mbed_official | 146:f64d43ff0c18 | 11295 | #endif |
mbed_official | 146:f64d43ff0c18 | 11296 | |
mbed_official | 146:f64d43ff0c18 | 11297 | //! @brief Format value for bitfield AIPS_PACRM_SP1. |
mbed_official | 146:f64d43ff0c18 | 11298 | #define BF_AIPS_PACRM_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP1), uint32_t) & BM_AIPS_PACRM_SP1) |
mbed_official | 146:f64d43ff0c18 | 11299 | |
mbed_official | 146:f64d43ff0c18 | 11300 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11301 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11302 | #define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11303 | #endif |
mbed_official | 146:f64d43ff0c18 | 11304 | //@} |
mbed_official | 146:f64d43ff0c18 | 11305 | |
mbed_official | 146:f64d43ff0c18 | 11306 | /*! |
mbed_official | 146:f64d43ff0c18 | 11307 | * @name Register AIPS_PACRM, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 11308 | * |
mbed_official | 146:f64d43ff0c18 | 11309 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11310 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11311 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11312 | * |
mbed_official | 146:f64d43ff0c18 | 11313 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11314 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11315 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11316 | */ |
mbed_official | 146:f64d43ff0c18 | 11317 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11318 | #define BP_AIPS_PACRM_TP0 (28U) //!< Bit position for AIPS_PACRM_TP0. |
mbed_official | 146:f64d43ff0c18 | 11319 | #define BM_AIPS_PACRM_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRM_TP0. |
mbed_official | 146:f64d43ff0c18 | 11320 | #define BS_AIPS_PACRM_TP0 (1U) //!< Bit field size in bits for AIPS_PACRM_TP0. |
mbed_official | 146:f64d43ff0c18 | 11321 | |
mbed_official | 146:f64d43ff0c18 | 11322 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11323 | //! @brief Read current value of the AIPS_PACRM_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 11324 | #define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0)) |
mbed_official | 146:f64d43ff0c18 | 11325 | #endif |
mbed_official | 146:f64d43ff0c18 | 11326 | |
mbed_official | 146:f64d43ff0c18 | 11327 | //! @brief Format value for bitfield AIPS_PACRM_TP0. |
mbed_official | 146:f64d43ff0c18 | 11328 | #define BF_AIPS_PACRM_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP0), uint32_t) & BM_AIPS_PACRM_TP0) |
mbed_official | 146:f64d43ff0c18 | 11329 | |
mbed_official | 146:f64d43ff0c18 | 11330 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11331 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11332 | #define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11333 | #endif |
mbed_official | 146:f64d43ff0c18 | 11334 | //@} |
mbed_official | 146:f64d43ff0c18 | 11335 | |
mbed_official | 146:f64d43ff0c18 | 11336 | /*! |
mbed_official | 146:f64d43ff0c18 | 11337 | * @name Register AIPS_PACRM, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 11338 | * |
mbed_official | 146:f64d43ff0c18 | 11339 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11340 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11341 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11342 | * |
mbed_official | 146:f64d43ff0c18 | 11343 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11344 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11345 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11346 | */ |
mbed_official | 146:f64d43ff0c18 | 11347 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11348 | #define BP_AIPS_PACRM_WP0 (29U) //!< Bit position for AIPS_PACRM_WP0. |
mbed_official | 146:f64d43ff0c18 | 11349 | #define BM_AIPS_PACRM_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRM_WP0. |
mbed_official | 146:f64d43ff0c18 | 11350 | #define BS_AIPS_PACRM_WP0 (1U) //!< Bit field size in bits for AIPS_PACRM_WP0. |
mbed_official | 146:f64d43ff0c18 | 11351 | |
mbed_official | 146:f64d43ff0c18 | 11352 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11353 | //! @brief Read current value of the AIPS_PACRM_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 11354 | #define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0)) |
mbed_official | 146:f64d43ff0c18 | 11355 | #endif |
mbed_official | 146:f64d43ff0c18 | 11356 | |
mbed_official | 146:f64d43ff0c18 | 11357 | //! @brief Format value for bitfield AIPS_PACRM_WP0. |
mbed_official | 146:f64d43ff0c18 | 11358 | #define BF_AIPS_PACRM_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP0), uint32_t) & BM_AIPS_PACRM_WP0) |
mbed_official | 146:f64d43ff0c18 | 11359 | |
mbed_official | 146:f64d43ff0c18 | 11360 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11361 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11362 | #define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11363 | #endif |
mbed_official | 146:f64d43ff0c18 | 11364 | //@} |
mbed_official | 146:f64d43ff0c18 | 11365 | |
mbed_official | 146:f64d43ff0c18 | 11366 | /*! |
mbed_official | 146:f64d43ff0c18 | 11367 | * @name Register AIPS_PACRM, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 11368 | * |
mbed_official | 146:f64d43ff0c18 | 11369 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11370 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11371 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 11372 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11373 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11374 | * |
mbed_official | 146:f64d43ff0c18 | 11375 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11376 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11377 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11378 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11379 | */ |
mbed_official | 146:f64d43ff0c18 | 11380 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11381 | #define BP_AIPS_PACRM_SP0 (30U) //!< Bit position for AIPS_PACRM_SP0. |
mbed_official | 146:f64d43ff0c18 | 11382 | #define BM_AIPS_PACRM_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRM_SP0. |
mbed_official | 146:f64d43ff0c18 | 11383 | #define BS_AIPS_PACRM_SP0 (1U) //!< Bit field size in bits for AIPS_PACRM_SP0. |
mbed_official | 146:f64d43ff0c18 | 11384 | |
mbed_official | 146:f64d43ff0c18 | 11385 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11386 | //! @brief Read current value of the AIPS_PACRM_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 11387 | #define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0)) |
mbed_official | 146:f64d43ff0c18 | 11388 | #endif |
mbed_official | 146:f64d43ff0c18 | 11389 | |
mbed_official | 146:f64d43ff0c18 | 11390 | //! @brief Format value for bitfield AIPS_PACRM_SP0. |
mbed_official | 146:f64d43ff0c18 | 11391 | #define BF_AIPS_PACRM_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP0), uint32_t) & BM_AIPS_PACRM_SP0) |
mbed_official | 146:f64d43ff0c18 | 11392 | |
mbed_official | 146:f64d43ff0c18 | 11393 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11394 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11395 | #define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11396 | #endif |
mbed_official | 146:f64d43ff0c18 | 11397 | //@} |
mbed_official | 146:f64d43ff0c18 | 11398 | |
mbed_official | 146:f64d43ff0c18 | 11399 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 11400 | // HW_AIPS_PACRN - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 11401 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 11402 | |
mbed_official | 146:f64d43ff0c18 | 11403 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11404 | /*! |
mbed_official | 146:f64d43ff0c18 | 11405 | * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 11406 | * |
mbed_official | 146:f64d43ff0c18 | 11407 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 11408 | * |
mbed_official | 146:f64d43ff0c18 | 11409 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 11410 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 11411 | * registers. |
mbed_official | 146:f64d43ff0c18 | 11412 | */ |
mbed_official | 146:f64d43ff0c18 | 11413 | typedef union _hw_aips_pacrn |
mbed_official | 146:f64d43ff0c18 | 11414 | { |
mbed_official | 146:f64d43ff0c18 | 11415 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 11416 | struct _hw_aips_pacrn_bitfields |
mbed_official | 146:f64d43ff0c18 | 11417 | { |
mbed_official | 146:f64d43ff0c18 | 11418 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11419 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11420 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11421 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 11422 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11423 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11424 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11425 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 11426 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11427 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11428 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11429 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 11430 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11431 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11432 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11433 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 11434 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11435 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11436 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11437 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 11438 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11439 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11440 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11441 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 11442 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11443 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11444 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11445 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 11446 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 11447 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 11448 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 11449 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 11450 | } B; |
mbed_official | 146:f64d43ff0c18 | 11451 | } hw_aips_pacrn_t; |
mbed_official | 146:f64d43ff0c18 | 11452 | #endif |
mbed_official | 146:f64d43ff0c18 | 11453 | |
mbed_official | 146:f64d43ff0c18 | 11454 | /*! |
mbed_official | 146:f64d43ff0c18 | 11455 | * @name Constants and macros for entire AIPS_PACRN register |
mbed_official | 146:f64d43ff0c18 | 11456 | */ |
mbed_official | 146:f64d43ff0c18 | 11457 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11458 | #define HW_AIPS_PACRN_ADDR(x) (REGS_AIPS_BASE(x) + 0x64U) |
mbed_official | 146:f64d43ff0c18 | 11459 | |
mbed_official | 146:f64d43ff0c18 | 11460 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11461 | #define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 11462 | #define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U) |
mbed_official | 146:f64d43ff0c18 | 11463 | #define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 11464 | #define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 11465 | #define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 11466 | #define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 11467 | #endif |
mbed_official | 146:f64d43ff0c18 | 11468 | //@} |
mbed_official | 146:f64d43ff0c18 | 11469 | |
mbed_official | 146:f64d43ff0c18 | 11470 | /* |
mbed_official | 146:f64d43ff0c18 | 11471 | * Constants & macros for individual AIPS_PACRN bitfields |
mbed_official | 146:f64d43ff0c18 | 11472 | */ |
mbed_official | 146:f64d43ff0c18 | 11473 | |
mbed_official | 146:f64d43ff0c18 | 11474 | /*! |
mbed_official | 146:f64d43ff0c18 | 11475 | * @name Register AIPS_PACRN, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 11476 | * |
mbed_official | 146:f64d43ff0c18 | 11477 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11478 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11479 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11480 | * |
mbed_official | 146:f64d43ff0c18 | 11481 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11482 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11483 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11484 | */ |
mbed_official | 146:f64d43ff0c18 | 11485 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11486 | #define BP_AIPS_PACRN_TP7 (0U) //!< Bit position for AIPS_PACRN_TP7. |
mbed_official | 146:f64d43ff0c18 | 11487 | #define BM_AIPS_PACRN_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRN_TP7. |
mbed_official | 146:f64d43ff0c18 | 11488 | #define BS_AIPS_PACRN_TP7 (1U) //!< Bit field size in bits for AIPS_PACRN_TP7. |
mbed_official | 146:f64d43ff0c18 | 11489 | |
mbed_official | 146:f64d43ff0c18 | 11490 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11491 | //! @brief Read current value of the AIPS_PACRN_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 11492 | #define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7)) |
mbed_official | 146:f64d43ff0c18 | 11493 | #endif |
mbed_official | 146:f64d43ff0c18 | 11494 | |
mbed_official | 146:f64d43ff0c18 | 11495 | //! @brief Format value for bitfield AIPS_PACRN_TP7. |
mbed_official | 146:f64d43ff0c18 | 11496 | #define BF_AIPS_PACRN_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP7), uint32_t) & BM_AIPS_PACRN_TP7) |
mbed_official | 146:f64d43ff0c18 | 11497 | |
mbed_official | 146:f64d43ff0c18 | 11498 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11499 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11500 | #define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11501 | #endif |
mbed_official | 146:f64d43ff0c18 | 11502 | //@} |
mbed_official | 146:f64d43ff0c18 | 11503 | |
mbed_official | 146:f64d43ff0c18 | 11504 | /*! |
mbed_official | 146:f64d43ff0c18 | 11505 | * @name Register AIPS_PACRN, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 11506 | * |
mbed_official | 146:f64d43ff0c18 | 11507 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11508 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11509 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11510 | * |
mbed_official | 146:f64d43ff0c18 | 11511 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11512 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11513 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11514 | */ |
mbed_official | 146:f64d43ff0c18 | 11515 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11516 | #define BP_AIPS_PACRN_WP7 (1U) //!< Bit position for AIPS_PACRN_WP7. |
mbed_official | 146:f64d43ff0c18 | 11517 | #define BM_AIPS_PACRN_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRN_WP7. |
mbed_official | 146:f64d43ff0c18 | 11518 | #define BS_AIPS_PACRN_WP7 (1U) //!< Bit field size in bits for AIPS_PACRN_WP7. |
mbed_official | 146:f64d43ff0c18 | 11519 | |
mbed_official | 146:f64d43ff0c18 | 11520 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11521 | //! @brief Read current value of the AIPS_PACRN_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 11522 | #define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7)) |
mbed_official | 146:f64d43ff0c18 | 11523 | #endif |
mbed_official | 146:f64d43ff0c18 | 11524 | |
mbed_official | 146:f64d43ff0c18 | 11525 | //! @brief Format value for bitfield AIPS_PACRN_WP7. |
mbed_official | 146:f64d43ff0c18 | 11526 | #define BF_AIPS_PACRN_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP7), uint32_t) & BM_AIPS_PACRN_WP7) |
mbed_official | 146:f64d43ff0c18 | 11527 | |
mbed_official | 146:f64d43ff0c18 | 11528 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11529 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11530 | #define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11531 | #endif |
mbed_official | 146:f64d43ff0c18 | 11532 | //@} |
mbed_official | 146:f64d43ff0c18 | 11533 | |
mbed_official | 146:f64d43ff0c18 | 11534 | /*! |
mbed_official | 146:f64d43ff0c18 | 11535 | * @name Register AIPS_PACRN, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 11536 | * |
mbed_official | 146:f64d43ff0c18 | 11537 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11538 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11539 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 11540 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11541 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11542 | * |
mbed_official | 146:f64d43ff0c18 | 11543 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11544 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11545 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11546 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11547 | */ |
mbed_official | 146:f64d43ff0c18 | 11548 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11549 | #define BP_AIPS_PACRN_SP7 (2U) //!< Bit position for AIPS_PACRN_SP7. |
mbed_official | 146:f64d43ff0c18 | 11550 | #define BM_AIPS_PACRN_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRN_SP7. |
mbed_official | 146:f64d43ff0c18 | 11551 | #define BS_AIPS_PACRN_SP7 (1U) //!< Bit field size in bits for AIPS_PACRN_SP7. |
mbed_official | 146:f64d43ff0c18 | 11552 | |
mbed_official | 146:f64d43ff0c18 | 11553 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11554 | //! @brief Read current value of the AIPS_PACRN_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 11555 | #define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7)) |
mbed_official | 146:f64d43ff0c18 | 11556 | #endif |
mbed_official | 146:f64d43ff0c18 | 11557 | |
mbed_official | 146:f64d43ff0c18 | 11558 | //! @brief Format value for bitfield AIPS_PACRN_SP7. |
mbed_official | 146:f64d43ff0c18 | 11559 | #define BF_AIPS_PACRN_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP7), uint32_t) & BM_AIPS_PACRN_SP7) |
mbed_official | 146:f64d43ff0c18 | 11560 | |
mbed_official | 146:f64d43ff0c18 | 11561 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11562 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11563 | #define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11564 | #endif |
mbed_official | 146:f64d43ff0c18 | 11565 | //@} |
mbed_official | 146:f64d43ff0c18 | 11566 | |
mbed_official | 146:f64d43ff0c18 | 11567 | /*! |
mbed_official | 146:f64d43ff0c18 | 11568 | * @name Register AIPS_PACRN, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 11569 | * |
mbed_official | 146:f64d43ff0c18 | 11570 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11571 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11572 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11573 | * |
mbed_official | 146:f64d43ff0c18 | 11574 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11575 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11576 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11577 | */ |
mbed_official | 146:f64d43ff0c18 | 11578 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11579 | #define BP_AIPS_PACRN_TP6 (4U) //!< Bit position for AIPS_PACRN_TP6. |
mbed_official | 146:f64d43ff0c18 | 11580 | #define BM_AIPS_PACRN_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRN_TP6. |
mbed_official | 146:f64d43ff0c18 | 11581 | #define BS_AIPS_PACRN_TP6 (1U) //!< Bit field size in bits for AIPS_PACRN_TP6. |
mbed_official | 146:f64d43ff0c18 | 11582 | |
mbed_official | 146:f64d43ff0c18 | 11583 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11584 | //! @brief Read current value of the AIPS_PACRN_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 11585 | #define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6)) |
mbed_official | 146:f64d43ff0c18 | 11586 | #endif |
mbed_official | 146:f64d43ff0c18 | 11587 | |
mbed_official | 146:f64d43ff0c18 | 11588 | //! @brief Format value for bitfield AIPS_PACRN_TP6. |
mbed_official | 146:f64d43ff0c18 | 11589 | #define BF_AIPS_PACRN_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP6), uint32_t) & BM_AIPS_PACRN_TP6) |
mbed_official | 146:f64d43ff0c18 | 11590 | |
mbed_official | 146:f64d43ff0c18 | 11591 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11592 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11593 | #define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11594 | #endif |
mbed_official | 146:f64d43ff0c18 | 11595 | //@} |
mbed_official | 146:f64d43ff0c18 | 11596 | |
mbed_official | 146:f64d43ff0c18 | 11597 | /*! |
mbed_official | 146:f64d43ff0c18 | 11598 | * @name Register AIPS_PACRN, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 11599 | * |
mbed_official | 146:f64d43ff0c18 | 11600 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11601 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11602 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11603 | * |
mbed_official | 146:f64d43ff0c18 | 11604 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11605 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11606 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11607 | */ |
mbed_official | 146:f64d43ff0c18 | 11608 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11609 | #define BP_AIPS_PACRN_WP6 (5U) //!< Bit position for AIPS_PACRN_WP6. |
mbed_official | 146:f64d43ff0c18 | 11610 | #define BM_AIPS_PACRN_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRN_WP6. |
mbed_official | 146:f64d43ff0c18 | 11611 | #define BS_AIPS_PACRN_WP6 (1U) //!< Bit field size in bits for AIPS_PACRN_WP6. |
mbed_official | 146:f64d43ff0c18 | 11612 | |
mbed_official | 146:f64d43ff0c18 | 11613 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11614 | //! @brief Read current value of the AIPS_PACRN_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 11615 | #define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6)) |
mbed_official | 146:f64d43ff0c18 | 11616 | #endif |
mbed_official | 146:f64d43ff0c18 | 11617 | |
mbed_official | 146:f64d43ff0c18 | 11618 | //! @brief Format value for bitfield AIPS_PACRN_WP6. |
mbed_official | 146:f64d43ff0c18 | 11619 | #define BF_AIPS_PACRN_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP6), uint32_t) & BM_AIPS_PACRN_WP6) |
mbed_official | 146:f64d43ff0c18 | 11620 | |
mbed_official | 146:f64d43ff0c18 | 11621 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11622 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11623 | #define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11624 | #endif |
mbed_official | 146:f64d43ff0c18 | 11625 | //@} |
mbed_official | 146:f64d43ff0c18 | 11626 | |
mbed_official | 146:f64d43ff0c18 | 11627 | /*! |
mbed_official | 146:f64d43ff0c18 | 11628 | * @name Register AIPS_PACRN, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 11629 | * |
mbed_official | 146:f64d43ff0c18 | 11630 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11631 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11632 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 11633 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11634 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11635 | * |
mbed_official | 146:f64d43ff0c18 | 11636 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11637 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11638 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11639 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11640 | */ |
mbed_official | 146:f64d43ff0c18 | 11641 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11642 | #define BP_AIPS_PACRN_SP6 (6U) //!< Bit position for AIPS_PACRN_SP6. |
mbed_official | 146:f64d43ff0c18 | 11643 | #define BM_AIPS_PACRN_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRN_SP6. |
mbed_official | 146:f64d43ff0c18 | 11644 | #define BS_AIPS_PACRN_SP6 (1U) //!< Bit field size in bits for AIPS_PACRN_SP6. |
mbed_official | 146:f64d43ff0c18 | 11645 | |
mbed_official | 146:f64d43ff0c18 | 11646 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11647 | //! @brief Read current value of the AIPS_PACRN_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 11648 | #define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6)) |
mbed_official | 146:f64d43ff0c18 | 11649 | #endif |
mbed_official | 146:f64d43ff0c18 | 11650 | |
mbed_official | 146:f64d43ff0c18 | 11651 | //! @brief Format value for bitfield AIPS_PACRN_SP6. |
mbed_official | 146:f64d43ff0c18 | 11652 | #define BF_AIPS_PACRN_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP6), uint32_t) & BM_AIPS_PACRN_SP6) |
mbed_official | 146:f64d43ff0c18 | 11653 | |
mbed_official | 146:f64d43ff0c18 | 11654 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11655 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11656 | #define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11657 | #endif |
mbed_official | 146:f64d43ff0c18 | 11658 | //@} |
mbed_official | 146:f64d43ff0c18 | 11659 | |
mbed_official | 146:f64d43ff0c18 | 11660 | /*! |
mbed_official | 146:f64d43ff0c18 | 11661 | * @name Register AIPS_PACRN, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 11662 | * |
mbed_official | 146:f64d43ff0c18 | 11663 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11664 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11665 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11666 | * |
mbed_official | 146:f64d43ff0c18 | 11667 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11668 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11669 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11670 | */ |
mbed_official | 146:f64d43ff0c18 | 11671 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11672 | #define BP_AIPS_PACRN_TP5 (8U) //!< Bit position for AIPS_PACRN_TP5. |
mbed_official | 146:f64d43ff0c18 | 11673 | #define BM_AIPS_PACRN_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRN_TP5. |
mbed_official | 146:f64d43ff0c18 | 11674 | #define BS_AIPS_PACRN_TP5 (1U) //!< Bit field size in bits for AIPS_PACRN_TP5. |
mbed_official | 146:f64d43ff0c18 | 11675 | |
mbed_official | 146:f64d43ff0c18 | 11676 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11677 | //! @brief Read current value of the AIPS_PACRN_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 11678 | #define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5)) |
mbed_official | 146:f64d43ff0c18 | 11679 | #endif |
mbed_official | 146:f64d43ff0c18 | 11680 | |
mbed_official | 146:f64d43ff0c18 | 11681 | //! @brief Format value for bitfield AIPS_PACRN_TP5. |
mbed_official | 146:f64d43ff0c18 | 11682 | #define BF_AIPS_PACRN_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP5), uint32_t) & BM_AIPS_PACRN_TP5) |
mbed_official | 146:f64d43ff0c18 | 11683 | |
mbed_official | 146:f64d43ff0c18 | 11684 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11685 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11686 | #define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11687 | #endif |
mbed_official | 146:f64d43ff0c18 | 11688 | //@} |
mbed_official | 146:f64d43ff0c18 | 11689 | |
mbed_official | 146:f64d43ff0c18 | 11690 | /*! |
mbed_official | 146:f64d43ff0c18 | 11691 | * @name Register AIPS_PACRN, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 11692 | * |
mbed_official | 146:f64d43ff0c18 | 11693 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11694 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11695 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11696 | * |
mbed_official | 146:f64d43ff0c18 | 11697 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11698 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11699 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11700 | */ |
mbed_official | 146:f64d43ff0c18 | 11701 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11702 | #define BP_AIPS_PACRN_WP5 (9U) //!< Bit position for AIPS_PACRN_WP5. |
mbed_official | 146:f64d43ff0c18 | 11703 | #define BM_AIPS_PACRN_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRN_WP5. |
mbed_official | 146:f64d43ff0c18 | 11704 | #define BS_AIPS_PACRN_WP5 (1U) //!< Bit field size in bits for AIPS_PACRN_WP5. |
mbed_official | 146:f64d43ff0c18 | 11705 | |
mbed_official | 146:f64d43ff0c18 | 11706 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11707 | //! @brief Read current value of the AIPS_PACRN_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 11708 | #define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5)) |
mbed_official | 146:f64d43ff0c18 | 11709 | #endif |
mbed_official | 146:f64d43ff0c18 | 11710 | |
mbed_official | 146:f64d43ff0c18 | 11711 | //! @brief Format value for bitfield AIPS_PACRN_WP5. |
mbed_official | 146:f64d43ff0c18 | 11712 | #define BF_AIPS_PACRN_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP5), uint32_t) & BM_AIPS_PACRN_WP5) |
mbed_official | 146:f64d43ff0c18 | 11713 | |
mbed_official | 146:f64d43ff0c18 | 11714 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11715 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11716 | #define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11717 | #endif |
mbed_official | 146:f64d43ff0c18 | 11718 | //@} |
mbed_official | 146:f64d43ff0c18 | 11719 | |
mbed_official | 146:f64d43ff0c18 | 11720 | /*! |
mbed_official | 146:f64d43ff0c18 | 11721 | * @name Register AIPS_PACRN, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 11722 | * |
mbed_official | 146:f64d43ff0c18 | 11723 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11724 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11725 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 11726 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11727 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11728 | * |
mbed_official | 146:f64d43ff0c18 | 11729 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11730 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11731 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11732 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11733 | */ |
mbed_official | 146:f64d43ff0c18 | 11734 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11735 | #define BP_AIPS_PACRN_SP5 (10U) //!< Bit position for AIPS_PACRN_SP5. |
mbed_official | 146:f64d43ff0c18 | 11736 | #define BM_AIPS_PACRN_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRN_SP5. |
mbed_official | 146:f64d43ff0c18 | 11737 | #define BS_AIPS_PACRN_SP5 (1U) //!< Bit field size in bits for AIPS_PACRN_SP5. |
mbed_official | 146:f64d43ff0c18 | 11738 | |
mbed_official | 146:f64d43ff0c18 | 11739 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11740 | //! @brief Read current value of the AIPS_PACRN_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 11741 | #define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5)) |
mbed_official | 146:f64d43ff0c18 | 11742 | #endif |
mbed_official | 146:f64d43ff0c18 | 11743 | |
mbed_official | 146:f64d43ff0c18 | 11744 | //! @brief Format value for bitfield AIPS_PACRN_SP5. |
mbed_official | 146:f64d43ff0c18 | 11745 | #define BF_AIPS_PACRN_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP5), uint32_t) & BM_AIPS_PACRN_SP5) |
mbed_official | 146:f64d43ff0c18 | 11746 | |
mbed_official | 146:f64d43ff0c18 | 11747 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11748 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11749 | #define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11750 | #endif |
mbed_official | 146:f64d43ff0c18 | 11751 | //@} |
mbed_official | 146:f64d43ff0c18 | 11752 | |
mbed_official | 146:f64d43ff0c18 | 11753 | /*! |
mbed_official | 146:f64d43ff0c18 | 11754 | * @name Register AIPS_PACRN, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 11755 | * |
mbed_official | 146:f64d43ff0c18 | 11756 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11757 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11758 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11759 | * |
mbed_official | 146:f64d43ff0c18 | 11760 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11761 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11762 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11763 | */ |
mbed_official | 146:f64d43ff0c18 | 11764 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11765 | #define BP_AIPS_PACRN_TP4 (12U) //!< Bit position for AIPS_PACRN_TP4. |
mbed_official | 146:f64d43ff0c18 | 11766 | #define BM_AIPS_PACRN_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRN_TP4. |
mbed_official | 146:f64d43ff0c18 | 11767 | #define BS_AIPS_PACRN_TP4 (1U) //!< Bit field size in bits for AIPS_PACRN_TP4. |
mbed_official | 146:f64d43ff0c18 | 11768 | |
mbed_official | 146:f64d43ff0c18 | 11769 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11770 | //! @brief Read current value of the AIPS_PACRN_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 11771 | #define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4)) |
mbed_official | 146:f64d43ff0c18 | 11772 | #endif |
mbed_official | 146:f64d43ff0c18 | 11773 | |
mbed_official | 146:f64d43ff0c18 | 11774 | //! @brief Format value for bitfield AIPS_PACRN_TP4. |
mbed_official | 146:f64d43ff0c18 | 11775 | #define BF_AIPS_PACRN_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP4), uint32_t) & BM_AIPS_PACRN_TP4) |
mbed_official | 146:f64d43ff0c18 | 11776 | |
mbed_official | 146:f64d43ff0c18 | 11777 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11778 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11779 | #define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11780 | #endif |
mbed_official | 146:f64d43ff0c18 | 11781 | //@} |
mbed_official | 146:f64d43ff0c18 | 11782 | |
mbed_official | 146:f64d43ff0c18 | 11783 | /*! |
mbed_official | 146:f64d43ff0c18 | 11784 | * @name Register AIPS_PACRN, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 11785 | * |
mbed_official | 146:f64d43ff0c18 | 11786 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11787 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11788 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11789 | * |
mbed_official | 146:f64d43ff0c18 | 11790 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11791 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11792 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11793 | */ |
mbed_official | 146:f64d43ff0c18 | 11794 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11795 | #define BP_AIPS_PACRN_WP4 (13U) //!< Bit position for AIPS_PACRN_WP4. |
mbed_official | 146:f64d43ff0c18 | 11796 | #define BM_AIPS_PACRN_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRN_WP4. |
mbed_official | 146:f64d43ff0c18 | 11797 | #define BS_AIPS_PACRN_WP4 (1U) //!< Bit field size in bits for AIPS_PACRN_WP4. |
mbed_official | 146:f64d43ff0c18 | 11798 | |
mbed_official | 146:f64d43ff0c18 | 11799 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11800 | //! @brief Read current value of the AIPS_PACRN_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 11801 | #define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4)) |
mbed_official | 146:f64d43ff0c18 | 11802 | #endif |
mbed_official | 146:f64d43ff0c18 | 11803 | |
mbed_official | 146:f64d43ff0c18 | 11804 | //! @brief Format value for bitfield AIPS_PACRN_WP4. |
mbed_official | 146:f64d43ff0c18 | 11805 | #define BF_AIPS_PACRN_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP4), uint32_t) & BM_AIPS_PACRN_WP4) |
mbed_official | 146:f64d43ff0c18 | 11806 | |
mbed_official | 146:f64d43ff0c18 | 11807 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11808 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11809 | #define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11810 | #endif |
mbed_official | 146:f64d43ff0c18 | 11811 | //@} |
mbed_official | 146:f64d43ff0c18 | 11812 | |
mbed_official | 146:f64d43ff0c18 | 11813 | /*! |
mbed_official | 146:f64d43ff0c18 | 11814 | * @name Register AIPS_PACRN, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 11815 | * |
mbed_official | 146:f64d43ff0c18 | 11816 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11817 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11818 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 11819 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 11820 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 11821 | * |
mbed_official | 146:f64d43ff0c18 | 11822 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11823 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11824 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11825 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11826 | */ |
mbed_official | 146:f64d43ff0c18 | 11827 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11828 | #define BP_AIPS_PACRN_SP4 (14U) //!< Bit position for AIPS_PACRN_SP4. |
mbed_official | 146:f64d43ff0c18 | 11829 | #define BM_AIPS_PACRN_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRN_SP4. |
mbed_official | 146:f64d43ff0c18 | 11830 | #define BS_AIPS_PACRN_SP4 (1U) //!< Bit field size in bits for AIPS_PACRN_SP4. |
mbed_official | 146:f64d43ff0c18 | 11831 | |
mbed_official | 146:f64d43ff0c18 | 11832 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11833 | //! @brief Read current value of the AIPS_PACRN_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 11834 | #define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4)) |
mbed_official | 146:f64d43ff0c18 | 11835 | #endif |
mbed_official | 146:f64d43ff0c18 | 11836 | |
mbed_official | 146:f64d43ff0c18 | 11837 | //! @brief Format value for bitfield AIPS_PACRN_SP4. |
mbed_official | 146:f64d43ff0c18 | 11838 | #define BF_AIPS_PACRN_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP4), uint32_t) & BM_AIPS_PACRN_SP4) |
mbed_official | 146:f64d43ff0c18 | 11839 | |
mbed_official | 146:f64d43ff0c18 | 11840 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11841 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11842 | #define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11843 | #endif |
mbed_official | 146:f64d43ff0c18 | 11844 | //@} |
mbed_official | 146:f64d43ff0c18 | 11845 | |
mbed_official | 146:f64d43ff0c18 | 11846 | /*! |
mbed_official | 146:f64d43ff0c18 | 11847 | * @name Register AIPS_PACRN, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 11848 | * |
mbed_official | 146:f64d43ff0c18 | 11849 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11850 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11851 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11852 | * |
mbed_official | 146:f64d43ff0c18 | 11853 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11854 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11855 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11856 | */ |
mbed_official | 146:f64d43ff0c18 | 11857 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11858 | #define BP_AIPS_PACRN_TP3 (16U) //!< Bit position for AIPS_PACRN_TP3. |
mbed_official | 146:f64d43ff0c18 | 11859 | #define BM_AIPS_PACRN_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRN_TP3. |
mbed_official | 146:f64d43ff0c18 | 11860 | #define BS_AIPS_PACRN_TP3 (1U) //!< Bit field size in bits for AIPS_PACRN_TP3. |
mbed_official | 146:f64d43ff0c18 | 11861 | |
mbed_official | 146:f64d43ff0c18 | 11862 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11863 | //! @brief Read current value of the AIPS_PACRN_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 11864 | #define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3)) |
mbed_official | 146:f64d43ff0c18 | 11865 | #endif |
mbed_official | 146:f64d43ff0c18 | 11866 | |
mbed_official | 146:f64d43ff0c18 | 11867 | //! @brief Format value for bitfield AIPS_PACRN_TP3. |
mbed_official | 146:f64d43ff0c18 | 11868 | #define BF_AIPS_PACRN_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP3), uint32_t) & BM_AIPS_PACRN_TP3) |
mbed_official | 146:f64d43ff0c18 | 11869 | |
mbed_official | 146:f64d43ff0c18 | 11870 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11871 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11872 | #define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11873 | #endif |
mbed_official | 146:f64d43ff0c18 | 11874 | //@} |
mbed_official | 146:f64d43ff0c18 | 11875 | |
mbed_official | 146:f64d43ff0c18 | 11876 | /*! |
mbed_official | 146:f64d43ff0c18 | 11877 | * @name Register AIPS_PACRN, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 11878 | * |
mbed_official | 146:f64d43ff0c18 | 11879 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 11880 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 11881 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11882 | * |
mbed_official | 146:f64d43ff0c18 | 11883 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11884 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11885 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11886 | */ |
mbed_official | 146:f64d43ff0c18 | 11887 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11888 | #define BP_AIPS_PACRN_WP3 (17U) //!< Bit position for AIPS_PACRN_WP3. |
mbed_official | 146:f64d43ff0c18 | 11889 | #define BM_AIPS_PACRN_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRN_WP3. |
mbed_official | 146:f64d43ff0c18 | 11890 | #define BS_AIPS_PACRN_WP3 (1U) //!< Bit field size in bits for AIPS_PACRN_WP3. |
mbed_official | 146:f64d43ff0c18 | 11891 | |
mbed_official | 146:f64d43ff0c18 | 11892 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11893 | //! @brief Read current value of the AIPS_PACRN_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 11894 | #define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3)) |
mbed_official | 146:f64d43ff0c18 | 11895 | #endif |
mbed_official | 146:f64d43ff0c18 | 11896 | |
mbed_official | 146:f64d43ff0c18 | 11897 | //! @brief Format value for bitfield AIPS_PACRN_WP3. |
mbed_official | 146:f64d43ff0c18 | 11898 | #define BF_AIPS_PACRN_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP3), uint32_t) & BM_AIPS_PACRN_WP3) |
mbed_official | 146:f64d43ff0c18 | 11899 | |
mbed_official | 146:f64d43ff0c18 | 11900 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11901 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11902 | #define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11903 | #endif |
mbed_official | 146:f64d43ff0c18 | 11904 | //@} |
mbed_official | 146:f64d43ff0c18 | 11905 | |
mbed_official | 146:f64d43ff0c18 | 11906 | /*! |
mbed_official | 146:f64d43ff0c18 | 11907 | * @name Register AIPS_PACRN, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 11908 | * |
mbed_official | 146:f64d43ff0c18 | 11909 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11910 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 11911 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 11912 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 11913 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 11914 | * |
mbed_official | 146:f64d43ff0c18 | 11915 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11916 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 11917 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 11918 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 11919 | */ |
mbed_official | 146:f64d43ff0c18 | 11920 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11921 | #define BP_AIPS_PACRN_SP3 (18U) //!< Bit position for AIPS_PACRN_SP3. |
mbed_official | 146:f64d43ff0c18 | 11922 | #define BM_AIPS_PACRN_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRN_SP3. |
mbed_official | 146:f64d43ff0c18 | 11923 | #define BS_AIPS_PACRN_SP3 (1U) //!< Bit field size in bits for AIPS_PACRN_SP3. |
mbed_official | 146:f64d43ff0c18 | 11924 | |
mbed_official | 146:f64d43ff0c18 | 11925 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11926 | //! @brief Read current value of the AIPS_PACRN_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 11927 | #define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3)) |
mbed_official | 146:f64d43ff0c18 | 11928 | #endif |
mbed_official | 146:f64d43ff0c18 | 11929 | |
mbed_official | 146:f64d43ff0c18 | 11930 | //! @brief Format value for bitfield AIPS_PACRN_SP3. |
mbed_official | 146:f64d43ff0c18 | 11931 | #define BF_AIPS_PACRN_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP3), uint32_t) & BM_AIPS_PACRN_SP3) |
mbed_official | 146:f64d43ff0c18 | 11932 | |
mbed_official | 146:f64d43ff0c18 | 11933 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11934 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11935 | #define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11936 | #endif |
mbed_official | 146:f64d43ff0c18 | 11937 | //@} |
mbed_official | 146:f64d43ff0c18 | 11938 | |
mbed_official | 146:f64d43ff0c18 | 11939 | /*! |
mbed_official | 146:f64d43ff0c18 | 11940 | * @name Register AIPS_PACRN, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 11941 | * |
mbed_official | 146:f64d43ff0c18 | 11942 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 11943 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 11944 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11945 | * |
mbed_official | 146:f64d43ff0c18 | 11946 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11947 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 11948 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 11949 | */ |
mbed_official | 146:f64d43ff0c18 | 11950 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11951 | #define BP_AIPS_PACRN_TP2 (20U) //!< Bit position for AIPS_PACRN_TP2. |
mbed_official | 146:f64d43ff0c18 | 11952 | #define BM_AIPS_PACRN_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRN_TP2. |
mbed_official | 146:f64d43ff0c18 | 11953 | #define BS_AIPS_PACRN_TP2 (1U) //!< Bit field size in bits for AIPS_PACRN_TP2. |
mbed_official | 146:f64d43ff0c18 | 11954 | |
mbed_official | 146:f64d43ff0c18 | 11955 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11956 | //! @brief Read current value of the AIPS_PACRN_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 11957 | #define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2)) |
mbed_official | 146:f64d43ff0c18 | 11958 | #endif |
mbed_official | 146:f64d43ff0c18 | 11959 | |
mbed_official | 146:f64d43ff0c18 | 11960 | //! @brief Format value for bitfield AIPS_PACRN_TP2. |
mbed_official | 146:f64d43ff0c18 | 11961 | #define BF_AIPS_PACRN_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP2), uint32_t) & BM_AIPS_PACRN_TP2) |
mbed_official | 146:f64d43ff0c18 | 11962 | |
mbed_official | 146:f64d43ff0c18 | 11963 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11964 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11965 | #define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11966 | #endif |
mbed_official | 146:f64d43ff0c18 | 11967 | //@} |
mbed_official | 146:f64d43ff0c18 | 11968 | |
mbed_official | 146:f64d43ff0c18 | 11969 | /*! |
mbed_official | 146:f64d43ff0c18 | 11970 | * @name Register AIPS_PACRN, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 11971 | * |
mbed_official | 146:f64d43ff0c18 | 11972 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 11973 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 11974 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 11975 | * |
mbed_official | 146:f64d43ff0c18 | 11976 | * Values: |
mbed_official | 146:f64d43ff0c18 | 11977 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 11978 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 11979 | */ |
mbed_official | 146:f64d43ff0c18 | 11980 | //@{ |
mbed_official | 146:f64d43ff0c18 | 11981 | #define BP_AIPS_PACRN_WP2 (21U) //!< Bit position for AIPS_PACRN_WP2. |
mbed_official | 146:f64d43ff0c18 | 11982 | #define BM_AIPS_PACRN_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRN_WP2. |
mbed_official | 146:f64d43ff0c18 | 11983 | #define BS_AIPS_PACRN_WP2 (1U) //!< Bit field size in bits for AIPS_PACRN_WP2. |
mbed_official | 146:f64d43ff0c18 | 11984 | |
mbed_official | 146:f64d43ff0c18 | 11985 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11986 | //! @brief Read current value of the AIPS_PACRN_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 11987 | #define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2)) |
mbed_official | 146:f64d43ff0c18 | 11988 | #endif |
mbed_official | 146:f64d43ff0c18 | 11989 | |
mbed_official | 146:f64d43ff0c18 | 11990 | //! @brief Format value for bitfield AIPS_PACRN_WP2. |
mbed_official | 146:f64d43ff0c18 | 11991 | #define BF_AIPS_PACRN_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP2), uint32_t) & BM_AIPS_PACRN_WP2) |
mbed_official | 146:f64d43ff0c18 | 11992 | |
mbed_official | 146:f64d43ff0c18 | 11993 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 11994 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 11995 | #define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 11996 | #endif |
mbed_official | 146:f64d43ff0c18 | 11997 | //@} |
mbed_official | 146:f64d43ff0c18 | 11998 | |
mbed_official | 146:f64d43ff0c18 | 11999 | /*! |
mbed_official | 146:f64d43ff0c18 | 12000 | * @name Register AIPS_PACRN, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 12001 | * |
mbed_official | 146:f64d43ff0c18 | 12002 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12003 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12004 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 12005 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 12006 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 12007 | * |
mbed_official | 146:f64d43ff0c18 | 12008 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12009 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12010 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12011 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12012 | */ |
mbed_official | 146:f64d43ff0c18 | 12013 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12014 | #define BP_AIPS_PACRN_SP2 (22U) //!< Bit position for AIPS_PACRN_SP2. |
mbed_official | 146:f64d43ff0c18 | 12015 | #define BM_AIPS_PACRN_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRN_SP2. |
mbed_official | 146:f64d43ff0c18 | 12016 | #define BS_AIPS_PACRN_SP2 (1U) //!< Bit field size in bits for AIPS_PACRN_SP2. |
mbed_official | 146:f64d43ff0c18 | 12017 | |
mbed_official | 146:f64d43ff0c18 | 12018 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12019 | //! @brief Read current value of the AIPS_PACRN_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 12020 | #define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2)) |
mbed_official | 146:f64d43ff0c18 | 12021 | #endif |
mbed_official | 146:f64d43ff0c18 | 12022 | |
mbed_official | 146:f64d43ff0c18 | 12023 | //! @brief Format value for bitfield AIPS_PACRN_SP2. |
mbed_official | 146:f64d43ff0c18 | 12024 | #define BF_AIPS_PACRN_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP2), uint32_t) & BM_AIPS_PACRN_SP2) |
mbed_official | 146:f64d43ff0c18 | 12025 | |
mbed_official | 146:f64d43ff0c18 | 12026 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12027 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12028 | #define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12029 | #endif |
mbed_official | 146:f64d43ff0c18 | 12030 | //@} |
mbed_official | 146:f64d43ff0c18 | 12031 | |
mbed_official | 146:f64d43ff0c18 | 12032 | /*! |
mbed_official | 146:f64d43ff0c18 | 12033 | * @name Register AIPS_PACRN, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 12034 | * |
mbed_official | 146:f64d43ff0c18 | 12035 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12036 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12037 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12038 | * |
mbed_official | 146:f64d43ff0c18 | 12039 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12040 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12041 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12042 | */ |
mbed_official | 146:f64d43ff0c18 | 12043 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12044 | #define BP_AIPS_PACRN_TP1 (24U) //!< Bit position for AIPS_PACRN_TP1. |
mbed_official | 146:f64d43ff0c18 | 12045 | #define BM_AIPS_PACRN_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRN_TP1. |
mbed_official | 146:f64d43ff0c18 | 12046 | #define BS_AIPS_PACRN_TP1 (1U) //!< Bit field size in bits for AIPS_PACRN_TP1. |
mbed_official | 146:f64d43ff0c18 | 12047 | |
mbed_official | 146:f64d43ff0c18 | 12048 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12049 | //! @brief Read current value of the AIPS_PACRN_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 12050 | #define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1)) |
mbed_official | 146:f64d43ff0c18 | 12051 | #endif |
mbed_official | 146:f64d43ff0c18 | 12052 | |
mbed_official | 146:f64d43ff0c18 | 12053 | //! @brief Format value for bitfield AIPS_PACRN_TP1. |
mbed_official | 146:f64d43ff0c18 | 12054 | #define BF_AIPS_PACRN_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP1), uint32_t) & BM_AIPS_PACRN_TP1) |
mbed_official | 146:f64d43ff0c18 | 12055 | |
mbed_official | 146:f64d43ff0c18 | 12056 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12057 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12058 | #define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12059 | #endif |
mbed_official | 146:f64d43ff0c18 | 12060 | //@} |
mbed_official | 146:f64d43ff0c18 | 12061 | |
mbed_official | 146:f64d43ff0c18 | 12062 | /*! |
mbed_official | 146:f64d43ff0c18 | 12063 | * @name Register AIPS_PACRN, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 12064 | * |
mbed_official | 146:f64d43ff0c18 | 12065 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12066 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12067 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12068 | * |
mbed_official | 146:f64d43ff0c18 | 12069 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12070 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12071 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12072 | */ |
mbed_official | 146:f64d43ff0c18 | 12073 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12074 | #define BP_AIPS_PACRN_WP1 (25U) //!< Bit position for AIPS_PACRN_WP1. |
mbed_official | 146:f64d43ff0c18 | 12075 | #define BM_AIPS_PACRN_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRN_WP1. |
mbed_official | 146:f64d43ff0c18 | 12076 | #define BS_AIPS_PACRN_WP1 (1U) //!< Bit field size in bits for AIPS_PACRN_WP1. |
mbed_official | 146:f64d43ff0c18 | 12077 | |
mbed_official | 146:f64d43ff0c18 | 12078 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12079 | //! @brief Read current value of the AIPS_PACRN_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 12080 | #define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1)) |
mbed_official | 146:f64d43ff0c18 | 12081 | #endif |
mbed_official | 146:f64d43ff0c18 | 12082 | |
mbed_official | 146:f64d43ff0c18 | 12083 | //! @brief Format value for bitfield AIPS_PACRN_WP1. |
mbed_official | 146:f64d43ff0c18 | 12084 | #define BF_AIPS_PACRN_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP1), uint32_t) & BM_AIPS_PACRN_WP1) |
mbed_official | 146:f64d43ff0c18 | 12085 | |
mbed_official | 146:f64d43ff0c18 | 12086 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12087 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12088 | #define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12089 | #endif |
mbed_official | 146:f64d43ff0c18 | 12090 | //@} |
mbed_official | 146:f64d43ff0c18 | 12091 | |
mbed_official | 146:f64d43ff0c18 | 12092 | /*! |
mbed_official | 146:f64d43ff0c18 | 12093 | * @name Register AIPS_PACRN, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 12094 | * |
mbed_official | 146:f64d43ff0c18 | 12095 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12096 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12097 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 12098 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12099 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12100 | * |
mbed_official | 146:f64d43ff0c18 | 12101 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12102 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12103 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12104 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12105 | */ |
mbed_official | 146:f64d43ff0c18 | 12106 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12107 | #define BP_AIPS_PACRN_SP1 (26U) //!< Bit position for AIPS_PACRN_SP1. |
mbed_official | 146:f64d43ff0c18 | 12108 | #define BM_AIPS_PACRN_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRN_SP1. |
mbed_official | 146:f64d43ff0c18 | 12109 | #define BS_AIPS_PACRN_SP1 (1U) //!< Bit field size in bits for AIPS_PACRN_SP1. |
mbed_official | 146:f64d43ff0c18 | 12110 | |
mbed_official | 146:f64d43ff0c18 | 12111 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12112 | //! @brief Read current value of the AIPS_PACRN_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 12113 | #define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1)) |
mbed_official | 146:f64d43ff0c18 | 12114 | #endif |
mbed_official | 146:f64d43ff0c18 | 12115 | |
mbed_official | 146:f64d43ff0c18 | 12116 | //! @brief Format value for bitfield AIPS_PACRN_SP1. |
mbed_official | 146:f64d43ff0c18 | 12117 | #define BF_AIPS_PACRN_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP1), uint32_t) & BM_AIPS_PACRN_SP1) |
mbed_official | 146:f64d43ff0c18 | 12118 | |
mbed_official | 146:f64d43ff0c18 | 12119 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12120 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12121 | #define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12122 | #endif |
mbed_official | 146:f64d43ff0c18 | 12123 | //@} |
mbed_official | 146:f64d43ff0c18 | 12124 | |
mbed_official | 146:f64d43ff0c18 | 12125 | /*! |
mbed_official | 146:f64d43ff0c18 | 12126 | * @name Register AIPS_PACRN, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 12127 | * |
mbed_official | 146:f64d43ff0c18 | 12128 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12129 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12130 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12131 | * |
mbed_official | 146:f64d43ff0c18 | 12132 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12133 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12134 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12135 | */ |
mbed_official | 146:f64d43ff0c18 | 12136 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12137 | #define BP_AIPS_PACRN_TP0 (28U) //!< Bit position for AIPS_PACRN_TP0. |
mbed_official | 146:f64d43ff0c18 | 12138 | #define BM_AIPS_PACRN_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRN_TP0. |
mbed_official | 146:f64d43ff0c18 | 12139 | #define BS_AIPS_PACRN_TP0 (1U) //!< Bit field size in bits for AIPS_PACRN_TP0. |
mbed_official | 146:f64d43ff0c18 | 12140 | |
mbed_official | 146:f64d43ff0c18 | 12141 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12142 | //! @brief Read current value of the AIPS_PACRN_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 12143 | #define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0)) |
mbed_official | 146:f64d43ff0c18 | 12144 | #endif |
mbed_official | 146:f64d43ff0c18 | 12145 | |
mbed_official | 146:f64d43ff0c18 | 12146 | //! @brief Format value for bitfield AIPS_PACRN_TP0. |
mbed_official | 146:f64d43ff0c18 | 12147 | #define BF_AIPS_PACRN_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP0), uint32_t) & BM_AIPS_PACRN_TP0) |
mbed_official | 146:f64d43ff0c18 | 12148 | |
mbed_official | 146:f64d43ff0c18 | 12149 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12150 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12151 | #define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12152 | #endif |
mbed_official | 146:f64d43ff0c18 | 12153 | //@} |
mbed_official | 146:f64d43ff0c18 | 12154 | |
mbed_official | 146:f64d43ff0c18 | 12155 | /*! |
mbed_official | 146:f64d43ff0c18 | 12156 | * @name Register AIPS_PACRN, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 12157 | * |
mbed_official | 146:f64d43ff0c18 | 12158 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12159 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12160 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12161 | * |
mbed_official | 146:f64d43ff0c18 | 12162 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12163 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12164 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12165 | */ |
mbed_official | 146:f64d43ff0c18 | 12166 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12167 | #define BP_AIPS_PACRN_WP0 (29U) //!< Bit position for AIPS_PACRN_WP0. |
mbed_official | 146:f64d43ff0c18 | 12168 | #define BM_AIPS_PACRN_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRN_WP0. |
mbed_official | 146:f64d43ff0c18 | 12169 | #define BS_AIPS_PACRN_WP0 (1U) //!< Bit field size in bits for AIPS_PACRN_WP0. |
mbed_official | 146:f64d43ff0c18 | 12170 | |
mbed_official | 146:f64d43ff0c18 | 12171 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12172 | //! @brief Read current value of the AIPS_PACRN_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 12173 | #define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0)) |
mbed_official | 146:f64d43ff0c18 | 12174 | #endif |
mbed_official | 146:f64d43ff0c18 | 12175 | |
mbed_official | 146:f64d43ff0c18 | 12176 | //! @brief Format value for bitfield AIPS_PACRN_WP0. |
mbed_official | 146:f64d43ff0c18 | 12177 | #define BF_AIPS_PACRN_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP0), uint32_t) & BM_AIPS_PACRN_WP0) |
mbed_official | 146:f64d43ff0c18 | 12178 | |
mbed_official | 146:f64d43ff0c18 | 12179 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12180 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12181 | #define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12182 | #endif |
mbed_official | 146:f64d43ff0c18 | 12183 | //@} |
mbed_official | 146:f64d43ff0c18 | 12184 | |
mbed_official | 146:f64d43ff0c18 | 12185 | /*! |
mbed_official | 146:f64d43ff0c18 | 12186 | * @name Register AIPS_PACRN, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 12187 | * |
mbed_official | 146:f64d43ff0c18 | 12188 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12189 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12190 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 12191 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12192 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12193 | * |
mbed_official | 146:f64d43ff0c18 | 12194 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12195 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12196 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12197 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12198 | */ |
mbed_official | 146:f64d43ff0c18 | 12199 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12200 | #define BP_AIPS_PACRN_SP0 (30U) //!< Bit position for AIPS_PACRN_SP0. |
mbed_official | 146:f64d43ff0c18 | 12201 | #define BM_AIPS_PACRN_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRN_SP0. |
mbed_official | 146:f64d43ff0c18 | 12202 | #define BS_AIPS_PACRN_SP0 (1U) //!< Bit field size in bits for AIPS_PACRN_SP0. |
mbed_official | 146:f64d43ff0c18 | 12203 | |
mbed_official | 146:f64d43ff0c18 | 12204 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12205 | //! @brief Read current value of the AIPS_PACRN_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 12206 | #define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0)) |
mbed_official | 146:f64d43ff0c18 | 12207 | #endif |
mbed_official | 146:f64d43ff0c18 | 12208 | |
mbed_official | 146:f64d43ff0c18 | 12209 | //! @brief Format value for bitfield AIPS_PACRN_SP0. |
mbed_official | 146:f64d43ff0c18 | 12210 | #define BF_AIPS_PACRN_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP0), uint32_t) & BM_AIPS_PACRN_SP0) |
mbed_official | 146:f64d43ff0c18 | 12211 | |
mbed_official | 146:f64d43ff0c18 | 12212 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12213 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12214 | #define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12215 | #endif |
mbed_official | 146:f64d43ff0c18 | 12216 | //@} |
mbed_official | 146:f64d43ff0c18 | 12217 | |
mbed_official | 146:f64d43ff0c18 | 12218 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 12219 | // HW_AIPS_PACRO - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 12220 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 12221 | |
mbed_official | 146:f64d43ff0c18 | 12222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12223 | /*! |
mbed_official | 146:f64d43ff0c18 | 12224 | * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 12225 | * |
mbed_official | 146:f64d43ff0c18 | 12226 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 12227 | * |
mbed_official | 146:f64d43ff0c18 | 12228 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 12229 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 12230 | * registers. |
mbed_official | 146:f64d43ff0c18 | 12231 | */ |
mbed_official | 146:f64d43ff0c18 | 12232 | typedef union _hw_aips_pacro |
mbed_official | 146:f64d43ff0c18 | 12233 | { |
mbed_official | 146:f64d43ff0c18 | 12234 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 12235 | struct _hw_aips_pacro_bitfields |
mbed_official | 146:f64d43ff0c18 | 12236 | { |
mbed_official | 146:f64d43ff0c18 | 12237 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12238 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12239 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12240 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 12241 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12242 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12243 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12244 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 12245 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12246 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12247 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12248 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 12249 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12250 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12251 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12252 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 12253 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12254 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12255 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12256 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 12257 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12258 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12259 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12260 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 12261 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12262 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12263 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12264 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 12265 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 12266 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 12267 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 12268 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 12269 | } B; |
mbed_official | 146:f64d43ff0c18 | 12270 | } hw_aips_pacro_t; |
mbed_official | 146:f64d43ff0c18 | 12271 | #endif |
mbed_official | 146:f64d43ff0c18 | 12272 | |
mbed_official | 146:f64d43ff0c18 | 12273 | /*! |
mbed_official | 146:f64d43ff0c18 | 12274 | * @name Constants and macros for entire AIPS_PACRO register |
mbed_official | 146:f64d43ff0c18 | 12275 | */ |
mbed_official | 146:f64d43ff0c18 | 12276 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12277 | #define HW_AIPS_PACRO_ADDR(x) (REGS_AIPS_BASE(x) + 0x68U) |
mbed_official | 146:f64d43ff0c18 | 12278 | |
mbed_official | 146:f64d43ff0c18 | 12279 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12280 | #define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 12281 | #define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U) |
mbed_official | 146:f64d43ff0c18 | 12282 | #define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 12283 | #define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 12284 | #define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 12285 | #define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 12286 | #endif |
mbed_official | 146:f64d43ff0c18 | 12287 | //@} |
mbed_official | 146:f64d43ff0c18 | 12288 | |
mbed_official | 146:f64d43ff0c18 | 12289 | /* |
mbed_official | 146:f64d43ff0c18 | 12290 | * Constants & macros for individual AIPS_PACRO bitfields |
mbed_official | 146:f64d43ff0c18 | 12291 | */ |
mbed_official | 146:f64d43ff0c18 | 12292 | |
mbed_official | 146:f64d43ff0c18 | 12293 | /*! |
mbed_official | 146:f64d43ff0c18 | 12294 | * @name Register AIPS_PACRO, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 12295 | * |
mbed_official | 146:f64d43ff0c18 | 12296 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12297 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12298 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12299 | * |
mbed_official | 146:f64d43ff0c18 | 12300 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12301 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12302 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12303 | */ |
mbed_official | 146:f64d43ff0c18 | 12304 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12305 | #define BP_AIPS_PACRO_TP7 (0U) //!< Bit position for AIPS_PACRO_TP7. |
mbed_official | 146:f64d43ff0c18 | 12306 | #define BM_AIPS_PACRO_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRO_TP7. |
mbed_official | 146:f64d43ff0c18 | 12307 | #define BS_AIPS_PACRO_TP7 (1U) //!< Bit field size in bits for AIPS_PACRO_TP7. |
mbed_official | 146:f64d43ff0c18 | 12308 | |
mbed_official | 146:f64d43ff0c18 | 12309 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12310 | //! @brief Read current value of the AIPS_PACRO_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 12311 | #define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7)) |
mbed_official | 146:f64d43ff0c18 | 12312 | #endif |
mbed_official | 146:f64d43ff0c18 | 12313 | |
mbed_official | 146:f64d43ff0c18 | 12314 | //! @brief Format value for bitfield AIPS_PACRO_TP7. |
mbed_official | 146:f64d43ff0c18 | 12315 | #define BF_AIPS_PACRO_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP7), uint32_t) & BM_AIPS_PACRO_TP7) |
mbed_official | 146:f64d43ff0c18 | 12316 | |
mbed_official | 146:f64d43ff0c18 | 12317 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12318 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12319 | #define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12320 | #endif |
mbed_official | 146:f64d43ff0c18 | 12321 | //@} |
mbed_official | 146:f64d43ff0c18 | 12322 | |
mbed_official | 146:f64d43ff0c18 | 12323 | /*! |
mbed_official | 146:f64d43ff0c18 | 12324 | * @name Register AIPS_PACRO, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 12325 | * |
mbed_official | 146:f64d43ff0c18 | 12326 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12327 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12328 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12329 | * |
mbed_official | 146:f64d43ff0c18 | 12330 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12331 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12332 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12333 | */ |
mbed_official | 146:f64d43ff0c18 | 12334 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12335 | #define BP_AIPS_PACRO_WP7 (1U) //!< Bit position for AIPS_PACRO_WP7. |
mbed_official | 146:f64d43ff0c18 | 12336 | #define BM_AIPS_PACRO_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRO_WP7. |
mbed_official | 146:f64d43ff0c18 | 12337 | #define BS_AIPS_PACRO_WP7 (1U) //!< Bit field size in bits for AIPS_PACRO_WP7. |
mbed_official | 146:f64d43ff0c18 | 12338 | |
mbed_official | 146:f64d43ff0c18 | 12339 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12340 | //! @brief Read current value of the AIPS_PACRO_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 12341 | #define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7)) |
mbed_official | 146:f64d43ff0c18 | 12342 | #endif |
mbed_official | 146:f64d43ff0c18 | 12343 | |
mbed_official | 146:f64d43ff0c18 | 12344 | //! @brief Format value for bitfield AIPS_PACRO_WP7. |
mbed_official | 146:f64d43ff0c18 | 12345 | #define BF_AIPS_PACRO_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP7), uint32_t) & BM_AIPS_PACRO_WP7) |
mbed_official | 146:f64d43ff0c18 | 12346 | |
mbed_official | 146:f64d43ff0c18 | 12347 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12348 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12349 | #define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12350 | #endif |
mbed_official | 146:f64d43ff0c18 | 12351 | //@} |
mbed_official | 146:f64d43ff0c18 | 12352 | |
mbed_official | 146:f64d43ff0c18 | 12353 | /*! |
mbed_official | 146:f64d43ff0c18 | 12354 | * @name Register AIPS_PACRO, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 12355 | * |
mbed_official | 146:f64d43ff0c18 | 12356 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12357 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12358 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 12359 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12360 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12361 | * |
mbed_official | 146:f64d43ff0c18 | 12362 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12363 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12364 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12365 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12366 | */ |
mbed_official | 146:f64d43ff0c18 | 12367 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12368 | #define BP_AIPS_PACRO_SP7 (2U) //!< Bit position for AIPS_PACRO_SP7. |
mbed_official | 146:f64d43ff0c18 | 12369 | #define BM_AIPS_PACRO_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRO_SP7. |
mbed_official | 146:f64d43ff0c18 | 12370 | #define BS_AIPS_PACRO_SP7 (1U) //!< Bit field size in bits for AIPS_PACRO_SP7. |
mbed_official | 146:f64d43ff0c18 | 12371 | |
mbed_official | 146:f64d43ff0c18 | 12372 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12373 | //! @brief Read current value of the AIPS_PACRO_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 12374 | #define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7)) |
mbed_official | 146:f64d43ff0c18 | 12375 | #endif |
mbed_official | 146:f64d43ff0c18 | 12376 | |
mbed_official | 146:f64d43ff0c18 | 12377 | //! @brief Format value for bitfield AIPS_PACRO_SP7. |
mbed_official | 146:f64d43ff0c18 | 12378 | #define BF_AIPS_PACRO_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP7), uint32_t) & BM_AIPS_PACRO_SP7) |
mbed_official | 146:f64d43ff0c18 | 12379 | |
mbed_official | 146:f64d43ff0c18 | 12380 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12381 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12382 | #define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12383 | #endif |
mbed_official | 146:f64d43ff0c18 | 12384 | //@} |
mbed_official | 146:f64d43ff0c18 | 12385 | |
mbed_official | 146:f64d43ff0c18 | 12386 | /*! |
mbed_official | 146:f64d43ff0c18 | 12387 | * @name Register AIPS_PACRO, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 12388 | * |
mbed_official | 146:f64d43ff0c18 | 12389 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12390 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12391 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12392 | * |
mbed_official | 146:f64d43ff0c18 | 12393 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12394 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12395 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12396 | */ |
mbed_official | 146:f64d43ff0c18 | 12397 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12398 | #define BP_AIPS_PACRO_TP6 (4U) //!< Bit position for AIPS_PACRO_TP6. |
mbed_official | 146:f64d43ff0c18 | 12399 | #define BM_AIPS_PACRO_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRO_TP6. |
mbed_official | 146:f64d43ff0c18 | 12400 | #define BS_AIPS_PACRO_TP6 (1U) //!< Bit field size in bits for AIPS_PACRO_TP6. |
mbed_official | 146:f64d43ff0c18 | 12401 | |
mbed_official | 146:f64d43ff0c18 | 12402 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12403 | //! @brief Read current value of the AIPS_PACRO_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 12404 | #define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6)) |
mbed_official | 146:f64d43ff0c18 | 12405 | #endif |
mbed_official | 146:f64d43ff0c18 | 12406 | |
mbed_official | 146:f64d43ff0c18 | 12407 | //! @brief Format value for bitfield AIPS_PACRO_TP6. |
mbed_official | 146:f64d43ff0c18 | 12408 | #define BF_AIPS_PACRO_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP6), uint32_t) & BM_AIPS_PACRO_TP6) |
mbed_official | 146:f64d43ff0c18 | 12409 | |
mbed_official | 146:f64d43ff0c18 | 12410 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12411 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12412 | #define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12413 | #endif |
mbed_official | 146:f64d43ff0c18 | 12414 | //@} |
mbed_official | 146:f64d43ff0c18 | 12415 | |
mbed_official | 146:f64d43ff0c18 | 12416 | /*! |
mbed_official | 146:f64d43ff0c18 | 12417 | * @name Register AIPS_PACRO, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 12418 | * |
mbed_official | 146:f64d43ff0c18 | 12419 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12420 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12421 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12422 | * |
mbed_official | 146:f64d43ff0c18 | 12423 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12424 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12425 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12426 | */ |
mbed_official | 146:f64d43ff0c18 | 12427 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12428 | #define BP_AIPS_PACRO_WP6 (5U) //!< Bit position for AIPS_PACRO_WP6. |
mbed_official | 146:f64d43ff0c18 | 12429 | #define BM_AIPS_PACRO_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRO_WP6. |
mbed_official | 146:f64d43ff0c18 | 12430 | #define BS_AIPS_PACRO_WP6 (1U) //!< Bit field size in bits for AIPS_PACRO_WP6. |
mbed_official | 146:f64d43ff0c18 | 12431 | |
mbed_official | 146:f64d43ff0c18 | 12432 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12433 | //! @brief Read current value of the AIPS_PACRO_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 12434 | #define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6)) |
mbed_official | 146:f64d43ff0c18 | 12435 | #endif |
mbed_official | 146:f64d43ff0c18 | 12436 | |
mbed_official | 146:f64d43ff0c18 | 12437 | //! @brief Format value for bitfield AIPS_PACRO_WP6. |
mbed_official | 146:f64d43ff0c18 | 12438 | #define BF_AIPS_PACRO_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP6), uint32_t) & BM_AIPS_PACRO_WP6) |
mbed_official | 146:f64d43ff0c18 | 12439 | |
mbed_official | 146:f64d43ff0c18 | 12440 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12441 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12442 | #define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12443 | #endif |
mbed_official | 146:f64d43ff0c18 | 12444 | //@} |
mbed_official | 146:f64d43ff0c18 | 12445 | |
mbed_official | 146:f64d43ff0c18 | 12446 | /*! |
mbed_official | 146:f64d43ff0c18 | 12447 | * @name Register AIPS_PACRO, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 12448 | * |
mbed_official | 146:f64d43ff0c18 | 12449 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12450 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12451 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 12452 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12453 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12454 | * |
mbed_official | 146:f64d43ff0c18 | 12455 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12456 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12457 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12458 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12459 | */ |
mbed_official | 146:f64d43ff0c18 | 12460 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12461 | #define BP_AIPS_PACRO_SP6 (6U) //!< Bit position for AIPS_PACRO_SP6. |
mbed_official | 146:f64d43ff0c18 | 12462 | #define BM_AIPS_PACRO_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRO_SP6. |
mbed_official | 146:f64d43ff0c18 | 12463 | #define BS_AIPS_PACRO_SP6 (1U) //!< Bit field size in bits for AIPS_PACRO_SP6. |
mbed_official | 146:f64d43ff0c18 | 12464 | |
mbed_official | 146:f64d43ff0c18 | 12465 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12466 | //! @brief Read current value of the AIPS_PACRO_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 12467 | #define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6)) |
mbed_official | 146:f64d43ff0c18 | 12468 | #endif |
mbed_official | 146:f64d43ff0c18 | 12469 | |
mbed_official | 146:f64d43ff0c18 | 12470 | //! @brief Format value for bitfield AIPS_PACRO_SP6. |
mbed_official | 146:f64d43ff0c18 | 12471 | #define BF_AIPS_PACRO_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP6), uint32_t) & BM_AIPS_PACRO_SP6) |
mbed_official | 146:f64d43ff0c18 | 12472 | |
mbed_official | 146:f64d43ff0c18 | 12473 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12474 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12475 | #define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12476 | #endif |
mbed_official | 146:f64d43ff0c18 | 12477 | //@} |
mbed_official | 146:f64d43ff0c18 | 12478 | |
mbed_official | 146:f64d43ff0c18 | 12479 | /*! |
mbed_official | 146:f64d43ff0c18 | 12480 | * @name Register AIPS_PACRO, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 12481 | * |
mbed_official | 146:f64d43ff0c18 | 12482 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12483 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12484 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12485 | * |
mbed_official | 146:f64d43ff0c18 | 12486 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12487 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12488 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12489 | */ |
mbed_official | 146:f64d43ff0c18 | 12490 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12491 | #define BP_AIPS_PACRO_TP5 (8U) //!< Bit position for AIPS_PACRO_TP5. |
mbed_official | 146:f64d43ff0c18 | 12492 | #define BM_AIPS_PACRO_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRO_TP5. |
mbed_official | 146:f64d43ff0c18 | 12493 | #define BS_AIPS_PACRO_TP5 (1U) //!< Bit field size in bits for AIPS_PACRO_TP5. |
mbed_official | 146:f64d43ff0c18 | 12494 | |
mbed_official | 146:f64d43ff0c18 | 12495 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12496 | //! @brief Read current value of the AIPS_PACRO_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 12497 | #define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5)) |
mbed_official | 146:f64d43ff0c18 | 12498 | #endif |
mbed_official | 146:f64d43ff0c18 | 12499 | |
mbed_official | 146:f64d43ff0c18 | 12500 | //! @brief Format value for bitfield AIPS_PACRO_TP5. |
mbed_official | 146:f64d43ff0c18 | 12501 | #define BF_AIPS_PACRO_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP5), uint32_t) & BM_AIPS_PACRO_TP5) |
mbed_official | 146:f64d43ff0c18 | 12502 | |
mbed_official | 146:f64d43ff0c18 | 12503 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12504 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12505 | #define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12506 | #endif |
mbed_official | 146:f64d43ff0c18 | 12507 | //@} |
mbed_official | 146:f64d43ff0c18 | 12508 | |
mbed_official | 146:f64d43ff0c18 | 12509 | /*! |
mbed_official | 146:f64d43ff0c18 | 12510 | * @name Register AIPS_PACRO, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 12511 | * |
mbed_official | 146:f64d43ff0c18 | 12512 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12513 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12514 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12515 | * |
mbed_official | 146:f64d43ff0c18 | 12516 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12517 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12518 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12519 | */ |
mbed_official | 146:f64d43ff0c18 | 12520 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12521 | #define BP_AIPS_PACRO_WP5 (9U) //!< Bit position for AIPS_PACRO_WP5. |
mbed_official | 146:f64d43ff0c18 | 12522 | #define BM_AIPS_PACRO_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRO_WP5. |
mbed_official | 146:f64d43ff0c18 | 12523 | #define BS_AIPS_PACRO_WP5 (1U) //!< Bit field size in bits for AIPS_PACRO_WP5. |
mbed_official | 146:f64d43ff0c18 | 12524 | |
mbed_official | 146:f64d43ff0c18 | 12525 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12526 | //! @brief Read current value of the AIPS_PACRO_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 12527 | #define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5)) |
mbed_official | 146:f64d43ff0c18 | 12528 | #endif |
mbed_official | 146:f64d43ff0c18 | 12529 | |
mbed_official | 146:f64d43ff0c18 | 12530 | //! @brief Format value for bitfield AIPS_PACRO_WP5. |
mbed_official | 146:f64d43ff0c18 | 12531 | #define BF_AIPS_PACRO_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP5), uint32_t) & BM_AIPS_PACRO_WP5) |
mbed_official | 146:f64d43ff0c18 | 12532 | |
mbed_official | 146:f64d43ff0c18 | 12533 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12534 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12535 | #define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12536 | #endif |
mbed_official | 146:f64d43ff0c18 | 12537 | //@} |
mbed_official | 146:f64d43ff0c18 | 12538 | |
mbed_official | 146:f64d43ff0c18 | 12539 | /*! |
mbed_official | 146:f64d43ff0c18 | 12540 | * @name Register AIPS_PACRO, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 12541 | * |
mbed_official | 146:f64d43ff0c18 | 12542 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12543 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12544 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 12545 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12546 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12547 | * |
mbed_official | 146:f64d43ff0c18 | 12548 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12549 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12550 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12551 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12552 | */ |
mbed_official | 146:f64d43ff0c18 | 12553 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12554 | #define BP_AIPS_PACRO_SP5 (10U) //!< Bit position for AIPS_PACRO_SP5. |
mbed_official | 146:f64d43ff0c18 | 12555 | #define BM_AIPS_PACRO_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRO_SP5. |
mbed_official | 146:f64d43ff0c18 | 12556 | #define BS_AIPS_PACRO_SP5 (1U) //!< Bit field size in bits for AIPS_PACRO_SP5. |
mbed_official | 146:f64d43ff0c18 | 12557 | |
mbed_official | 146:f64d43ff0c18 | 12558 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12559 | //! @brief Read current value of the AIPS_PACRO_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 12560 | #define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5)) |
mbed_official | 146:f64d43ff0c18 | 12561 | #endif |
mbed_official | 146:f64d43ff0c18 | 12562 | |
mbed_official | 146:f64d43ff0c18 | 12563 | //! @brief Format value for bitfield AIPS_PACRO_SP5. |
mbed_official | 146:f64d43ff0c18 | 12564 | #define BF_AIPS_PACRO_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP5), uint32_t) & BM_AIPS_PACRO_SP5) |
mbed_official | 146:f64d43ff0c18 | 12565 | |
mbed_official | 146:f64d43ff0c18 | 12566 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12567 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12568 | #define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12569 | #endif |
mbed_official | 146:f64d43ff0c18 | 12570 | //@} |
mbed_official | 146:f64d43ff0c18 | 12571 | |
mbed_official | 146:f64d43ff0c18 | 12572 | /*! |
mbed_official | 146:f64d43ff0c18 | 12573 | * @name Register AIPS_PACRO, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 12574 | * |
mbed_official | 146:f64d43ff0c18 | 12575 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12576 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12577 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12578 | * |
mbed_official | 146:f64d43ff0c18 | 12579 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12580 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12581 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12582 | */ |
mbed_official | 146:f64d43ff0c18 | 12583 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12584 | #define BP_AIPS_PACRO_TP4 (12U) //!< Bit position for AIPS_PACRO_TP4. |
mbed_official | 146:f64d43ff0c18 | 12585 | #define BM_AIPS_PACRO_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRO_TP4. |
mbed_official | 146:f64d43ff0c18 | 12586 | #define BS_AIPS_PACRO_TP4 (1U) //!< Bit field size in bits for AIPS_PACRO_TP4. |
mbed_official | 146:f64d43ff0c18 | 12587 | |
mbed_official | 146:f64d43ff0c18 | 12588 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12589 | //! @brief Read current value of the AIPS_PACRO_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 12590 | #define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4)) |
mbed_official | 146:f64d43ff0c18 | 12591 | #endif |
mbed_official | 146:f64d43ff0c18 | 12592 | |
mbed_official | 146:f64d43ff0c18 | 12593 | //! @brief Format value for bitfield AIPS_PACRO_TP4. |
mbed_official | 146:f64d43ff0c18 | 12594 | #define BF_AIPS_PACRO_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP4), uint32_t) & BM_AIPS_PACRO_TP4) |
mbed_official | 146:f64d43ff0c18 | 12595 | |
mbed_official | 146:f64d43ff0c18 | 12596 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12597 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12598 | #define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12599 | #endif |
mbed_official | 146:f64d43ff0c18 | 12600 | //@} |
mbed_official | 146:f64d43ff0c18 | 12601 | |
mbed_official | 146:f64d43ff0c18 | 12602 | /*! |
mbed_official | 146:f64d43ff0c18 | 12603 | * @name Register AIPS_PACRO, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 12604 | * |
mbed_official | 146:f64d43ff0c18 | 12605 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12606 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12607 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12608 | * |
mbed_official | 146:f64d43ff0c18 | 12609 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12610 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12611 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12612 | */ |
mbed_official | 146:f64d43ff0c18 | 12613 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12614 | #define BP_AIPS_PACRO_WP4 (13U) //!< Bit position for AIPS_PACRO_WP4. |
mbed_official | 146:f64d43ff0c18 | 12615 | #define BM_AIPS_PACRO_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRO_WP4. |
mbed_official | 146:f64d43ff0c18 | 12616 | #define BS_AIPS_PACRO_WP4 (1U) //!< Bit field size in bits for AIPS_PACRO_WP4. |
mbed_official | 146:f64d43ff0c18 | 12617 | |
mbed_official | 146:f64d43ff0c18 | 12618 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12619 | //! @brief Read current value of the AIPS_PACRO_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 12620 | #define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4)) |
mbed_official | 146:f64d43ff0c18 | 12621 | #endif |
mbed_official | 146:f64d43ff0c18 | 12622 | |
mbed_official | 146:f64d43ff0c18 | 12623 | //! @brief Format value for bitfield AIPS_PACRO_WP4. |
mbed_official | 146:f64d43ff0c18 | 12624 | #define BF_AIPS_PACRO_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP4), uint32_t) & BM_AIPS_PACRO_WP4) |
mbed_official | 146:f64d43ff0c18 | 12625 | |
mbed_official | 146:f64d43ff0c18 | 12626 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12627 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12628 | #define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12629 | #endif |
mbed_official | 146:f64d43ff0c18 | 12630 | //@} |
mbed_official | 146:f64d43ff0c18 | 12631 | |
mbed_official | 146:f64d43ff0c18 | 12632 | /*! |
mbed_official | 146:f64d43ff0c18 | 12633 | * @name Register AIPS_PACRO, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 12634 | * |
mbed_official | 146:f64d43ff0c18 | 12635 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12636 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12637 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 12638 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 12639 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 12640 | * |
mbed_official | 146:f64d43ff0c18 | 12641 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12642 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12643 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12644 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12645 | */ |
mbed_official | 146:f64d43ff0c18 | 12646 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12647 | #define BP_AIPS_PACRO_SP4 (14U) //!< Bit position for AIPS_PACRO_SP4. |
mbed_official | 146:f64d43ff0c18 | 12648 | #define BM_AIPS_PACRO_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRO_SP4. |
mbed_official | 146:f64d43ff0c18 | 12649 | #define BS_AIPS_PACRO_SP4 (1U) //!< Bit field size in bits for AIPS_PACRO_SP4. |
mbed_official | 146:f64d43ff0c18 | 12650 | |
mbed_official | 146:f64d43ff0c18 | 12651 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12652 | //! @brief Read current value of the AIPS_PACRO_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 12653 | #define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4)) |
mbed_official | 146:f64d43ff0c18 | 12654 | #endif |
mbed_official | 146:f64d43ff0c18 | 12655 | |
mbed_official | 146:f64d43ff0c18 | 12656 | //! @brief Format value for bitfield AIPS_PACRO_SP4. |
mbed_official | 146:f64d43ff0c18 | 12657 | #define BF_AIPS_PACRO_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP4), uint32_t) & BM_AIPS_PACRO_SP4) |
mbed_official | 146:f64d43ff0c18 | 12658 | |
mbed_official | 146:f64d43ff0c18 | 12659 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12660 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12661 | #define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12662 | #endif |
mbed_official | 146:f64d43ff0c18 | 12663 | //@} |
mbed_official | 146:f64d43ff0c18 | 12664 | |
mbed_official | 146:f64d43ff0c18 | 12665 | /*! |
mbed_official | 146:f64d43ff0c18 | 12666 | * @name Register AIPS_PACRO, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 12667 | * |
mbed_official | 146:f64d43ff0c18 | 12668 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12669 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12670 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12671 | * |
mbed_official | 146:f64d43ff0c18 | 12672 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12673 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12674 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12675 | */ |
mbed_official | 146:f64d43ff0c18 | 12676 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12677 | #define BP_AIPS_PACRO_TP3 (16U) //!< Bit position for AIPS_PACRO_TP3. |
mbed_official | 146:f64d43ff0c18 | 12678 | #define BM_AIPS_PACRO_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRO_TP3. |
mbed_official | 146:f64d43ff0c18 | 12679 | #define BS_AIPS_PACRO_TP3 (1U) //!< Bit field size in bits for AIPS_PACRO_TP3. |
mbed_official | 146:f64d43ff0c18 | 12680 | |
mbed_official | 146:f64d43ff0c18 | 12681 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12682 | //! @brief Read current value of the AIPS_PACRO_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 12683 | #define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3)) |
mbed_official | 146:f64d43ff0c18 | 12684 | #endif |
mbed_official | 146:f64d43ff0c18 | 12685 | |
mbed_official | 146:f64d43ff0c18 | 12686 | //! @brief Format value for bitfield AIPS_PACRO_TP3. |
mbed_official | 146:f64d43ff0c18 | 12687 | #define BF_AIPS_PACRO_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP3), uint32_t) & BM_AIPS_PACRO_TP3) |
mbed_official | 146:f64d43ff0c18 | 12688 | |
mbed_official | 146:f64d43ff0c18 | 12689 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12690 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12691 | #define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12692 | #endif |
mbed_official | 146:f64d43ff0c18 | 12693 | //@} |
mbed_official | 146:f64d43ff0c18 | 12694 | |
mbed_official | 146:f64d43ff0c18 | 12695 | /*! |
mbed_official | 146:f64d43ff0c18 | 12696 | * @name Register AIPS_PACRO, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 12697 | * |
mbed_official | 146:f64d43ff0c18 | 12698 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 12699 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 12700 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12701 | * |
mbed_official | 146:f64d43ff0c18 | 12702 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12703 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12704 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12705 | */ |
mbed_official | 146:f64d43ff0c18 | 12706 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12707 | #define BP_AIPS_PACRO_WP3 (17U) //!< Bit position for AIPS_PACRO_WP3. |
mbed_official | 146:f64d43ff0c18 | 12708 | #define BM_AIPS_PACRO_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRO_WP3. |
mbed_official | 146:f64d43ff0c18 | 12709 | #define BS_AIPS_PACRO_WP3 (1U) //!< Bit field size in bits for AIPS_PACRO_WP3. |
mbed_official | 146:f64d43ff0c18 | 12710 | |
mbed_official | 146:f64d43ff0c18 | 12711 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12712 | //! @brief Read current value of the AIPS_PACRO_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 12713 | #define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3)) |
mbed_official | 146:f64d43ff0c18 | 12714 | #endif |
mbed_official | 146:f64d43ff0c18 | 12715 | |
mbed_official | 146:f64d43ff0c18 | 12716 | //! @brief Format value for bitfield AIPS_PACRO_WP3. |
mbed_official | 146:f64d43ff0c18 | 12717 | #define BF_AIPS_PACRO_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP3), uint32_t) & BM_AIPS_PACRO_WP3) |
mbed_official | 146:f64d43ff0c18 | 12718 | |
mbed_official | 146:f64d43ff0c18 | 12719 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12720 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12721 | #define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12722 | #endif |
mbed_official | 146:f64d43ff0c18 | 12723 | //@} |
mbed_official | 146:f64d43ff0c18 | 12724 | |
mbed_official | 146:f64d43ff0c18 | 12725 | /*! |
mbed_official | 146:f64d43ff0c18 | 12726 | * @name Register AIPS_PACRO, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 12727 | * |
mbed_official | 146:f64d43ff0c18 | 12728 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12729 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12730 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 12731 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12732 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12733 | * |
mbed_official | 146:f64d43ff0c18 | 12734 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12735 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12736 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12737 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12738 | */ |
mbed_official | 146:f64d43ff0c18 | 12739 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12740 | #define BP_AIPS_PACRO_SP3 (18U) //!< Bit position for AIPS_PACRO_SP3. |
mbed_official | 146:f64d43ff0c18 | 12741 | #define BM_AIPS_PACRO_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRO_SP3. |
mbed_official | 146:f64d43ff0c18 | 12742 | #define BS_AIPS_PACRO_SP3 (1U) //!< Bit field size in bits for AIPS_PACRO_SP3. |
mbed_official | 146:f64d43ff0c18 | 12743 | |
mbed_official | 146:f64d43ff0c18 | 12744 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12745 | //! @brief Read current value of the AIPS_PACRO_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 12746 | #define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3)) |
mbed_official | 146:f64d43ff0c18 | 12747 | #endif |
mbed_official | 146:f64d43ff0c18 | 12748 | |
mbed_official | 146:f64d43ff0c18 | 12749 | //! @brief Format value for bitfield AIPS_PACRO_SP3. |
mbed_official | 146:f64d43ff0c18 | 12750 | #define BF_AIPS_PACRO_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP3), uint32_t) & BM_AIPS_PACRO_SP3) |
mbed_official | 146:f64d43ff0c18 | 12751 | |
mbed_official | 146:f64d43ff0c18 | 12752 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12753 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12754 | #define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12755 | #endif |
mbed_official | 146:f64d43ff0c18 | 12756 | //@} |
mbed_official | 146:f64d43ff0c18 | 12757 | |
mbed_official | 146:f64d43ff0c18 | 12758 | /*! |
mbed_official | 146:f64d43ff0c18 | 12759 | * @name Register AIPS_PACRO, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 12760 | * |
mbed_official | 146:f64d43ff0c18 | 12761 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12762 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12763 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12764 | * |
mbed_official | 146:f64d43ff0c18 | 12765 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12766 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12767 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12768 | */ |
mbed_official | 146:f64d43ff0c18 | 12769 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12770 | #define BP_AIPS_PACRO_TP2 (20U) //!< Bit position for AIPS_PACRO_TP2. |
mbed_official | 146:f64d43ff0c18 | 12771 | #define BM_AIPS_PACRO_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRO_TP2. |
mbed_official | 146:f64d43ff0c18 | 12772 | #define BS_AIPS_PACRO_TP2 (1U) //!< Bit field size in bits for AIPS_PACRO_TP2. |
mbed_official | 146:f64d43ff0c18 | 12773 | |
mbed_official | 146:f64d43ff0c18 | 12774 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12775 | //! @brief Read current value of the AIPS_PACRO_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 12776 | #define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2)) |
mbed_official | 146:f64d43ff0c18 | 12777 | #endif |
mbed_official | 146:f64d43ff0c18 | 12778 | |
mbed_official | 146:f64d43ff0c18 | 12779 | //! @brief Format value for bitfield AIPS_PACRO_TP2. |
mbed_official | 146:f64d43ff0c18 | 12780 | #define BF_AIPS_PACRO_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP2), uint32_t) & BM_AIPS_PACRO_TP2) |
mbed_official | 146:f64d43ff0c18 | 12781 | |
mbed_official | 146:f64d43ff0c18 | 12782 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12783 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12784 | #define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12785 | #endif |
mbed_official | 146:f64d43ff0c18 | 12786 | //@} |
mbed_official | 146:f64d43ff0c18 | 12787 | |
mbed_official | 146:f64d43ff0c18 | 12788 | /*! |
mbed_official | 146:f64d43ff0c18 | 12789 | * @name Register AIPS_PACRO, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 12790 | * |
mbed_official | 146:f64d43ff0c18 | 12791 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12792 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12793 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12794 | * |
mbed_official | 146:f64d43ff0c18 | 12795 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12796 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12797 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12798 | */ |
mbed_official | 146:f64d43ff0c18 | 12799 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12800 | #define BP_AIPS_PACRO_WP2 (21U) //!< Bit position for AIPS_PACRO_WP2. |
mbed_official | 146:f64d43ff0c18 | 12801 | #define BM_AIPS_PACRO_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRO_WP2. |
mbed_official | 146:f64d43ff0c18 | 12802 | #define BS_AIPS_PACRO_WP2 (1U) //!< Bit field size in bits for AIPS_PACRO_WP2. |
mbed_official | 146:f64d43ff0c18 | 12803 | |
mbed_official | 146:f64d43ff0c18 | 12804 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12805 | //! @brief Read current value of the AIPS_PACRO_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 12806 | #define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2)) |
mbed_official | 146:f64d43ff0c18 | 12807 | #endif |
mbed_official | 146:f64d43ff0c18 | 12808 | |
mbed_official | 146:f64d43ff0c18 | 12809 | //! @brief Format value for bitfield AIPS_PACRO_WP2. |
mbed_official | 146:f64d43ff0c18 | 12810 | #define BF_AIPS_PACRO_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP2), uint32_t) & BM_AIPS_PACRO_WP2) |
mbed_official | 146:f64d43ff0c18 | 12811 | |
mbed_official | 146:f64d43ff0c18 | 12812 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12813 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12814 | #define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12815 | #endif |
mbed_official | 146:f64d43ff0c18 | 12816 | //@} |
mbed_official | 146:f64d43ff0c18 | 12817 | |
mbed_official | 146:f64d43ff0c18 | 12818 | /*! |
mbed_official | 146:f64d43ff0c18 | 12819 | * @name Register AIPS_PACRO, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 12820 | * |
mbed_official | 146:f64d43ff0c18 | 12821 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12822 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12823 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 12824 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 12825 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 12826 | * |
mbed_official | 146:f64d43ff0c18 | 12827 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12828 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12829 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12830 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12831 | */ |
mbed_official | 146:f64d43ff0c18 | 12832 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12833 | #define BP_AIPS_PACRO_SP2 (22U) //!< Bit position for AIPS_PACRO_SP2. |
mbed_official | 146:f64d43ff0c18 | 12834 | #define BM_AIPS_PACRO_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRO_SP2. |
mbed_official | 146:f64d43ff0c18 | 12835 | #define BS_AIPS_PACRO_SP2 (1U) //!< Bit field size in bits for AIPS_PACRO_SP2. |
mbed_official | 146:f64d43ff0c18 | 12836 | |
mbed_official | 146:f64d43ff0c18 | 12837 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12838 | //! @brief Read current value of the AIPS_PACRO_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 12839 | #define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2)) |
mbed_official | 146:f64d43ff0c18 | 12840 | #endif |
mbed_official | 146:f64d43ff0c18 | 12841 | |
mbed_official | 146:f64d43ff0c18 | 12842 | //! @brief Format value for bitfield AIPS_PACRO_SP2. |
mbed_official | 146:f64d43ff0c18 | 12843 | #define BF_AIPS_PACRO_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP2), uint32_t) & BM_AIPS_PACRO_SP2) |
mbed_official | 146:f64d43ff0c18 | 12844 | |
mbed_official | 146:f64d43ff0c18 | 12845 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12846 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12847 | #define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12848 | #endif |
mbed_official | 146:f64d43ff0c18 | 12849 | //@} |
mbed_official | 146:f64d43ff0c18 | 12850 | |
mbed_official | 146:f64d43ff0c18 | 12851 | /*! |
mbed_official | 146:f64d43ff0c18 | 12852 | * @name Register AIPS_PACRO, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 12853 | * |
mbed_official | 146:f64d43ff0c18 | 12854 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12855 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12856 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12857 | * |
mbed_official | 146:f64d43ff0c18 | 12858 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12859 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12860 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12861 | */ |
mbed_official | 146:f64d43ff0c18 | 12862 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12863 | #define BP_AIPS_PACRO_TP1 (24U) //!< Bit position for AIPS_PACRO_TP1. |
mbed_official | 146:f64d43ff0c18 | 12864 | #define BM_AIPS_PACRO_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRO_TP1. |
mbed_official | 146:f64d43ff0c18 | 12865 | #define BS_AIPS_PACRO_TP1 (1U) //!< Bit field size in bits for AIPS_PACRO_TP1. |
mbed_official | 146:f64d43ff0c18 | 12866 | |
mbed_official | 146:f64d43ff0c18 | 12867 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12868 | //! @brief Read current value of the AIPS_PACRO_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 12869 | #define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1)) |
mbed_official | 146:f64d43ff0c18 | 12870 | #endif |
mbed_official | 146:f64d43ff0c18 | 12871 | |
mbed_official | 146:f64d43ff0c18 | 12872 | //! @brief Format value for bitfield AIPS_PACRO_TP1. |
mbed_official | 146:f64d43ff0c18 | 12873 | #define BF_AIPS_PACRO_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP1), uint32_t) & BM_AIPS_PACRO_TP1) |
mbed_official | 146:f64d43ff0c18 | 12874 | |
mbed_official | 146:f64d43ff0c18 | 12875 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12876 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12877 | #define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12878 | #endif |
mbed_official | 146:f64d43ff0c18 | 12879 | //@} |
mbed_official | 146:f64d43ff0c18 | 12880 | |
mbed_official | 146:f64d43ff0c18 | 12881 | /*! |
mbed_official | 146:f64d43ff0c18 | 12882 | * @name Register AIPS_PACRO, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 12883 | * |
mbed_official | 146:f64d43ff0c18 | 12884 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12885 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12886 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12887 | * |
mbed_official | 146:f64d43ff0c18 | 12888 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12889 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12890 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12891 | */ |
mbed_official | 146:f64d43ff0c18 | 12892 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12893 | #define BP_AIPS_PACRO_WP1 (25U) //!< Bit position for AIPS_PACRO_WP1. |
mbed_official | 146:f64d43ff0c18 | 12894 | #define BM_AIPS_PACRO_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRO_WP1. |
mbed_official | 146:f64d43ff0c18 | 12895 | #define BS_AIPS_PACRO_WP1 (1U) //!< Bit field size in bits for AIPS_PACRO_WP1. |
mbed_official | 146:f64d43ff0c18 | 12896 | |
mbed_official | 146:f64d43ff0c18 | 12897 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12898 | //! @brief Read current value of the AIPS_PACRO_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 12899 | #define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1)) |
mbed_official | 146:f64d43ff0c18 | 12900 | #endif |
mbed_official | 146:f64d43ff0c18 | 12901 | |
mbed_official | 146:f64d43ff0c18 | 12902 | //! @brief Format value for bitfield AIPS_PACRO_WP1. |
mbed_official | 146:f64d43ff0c18 | 12903 | #define BF_AIPS_PACRO_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP1), uint32_t) & BM_AIPS_PACRO_WP1) |
mbed_official | 146:f64d43ff0c18 | 12904 | |
mbed_official | 146:f64d43ff0c18 | 12905 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12906 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12907 | #define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12908 | #endif |
mbed_official | 146:f64d43ff0c18 | 12909 | //@} |
mbed_official | 146:f64d43ff0c18 | 12910 | |
mbed_official | 146:f64d43ff0c18 | 12911 | /*! |
mbed_official | 146:f64d43ff0c18 | 12912 | * @name Register AIPS_PACRO, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 12913 | * |
mbed_official | 146:f64d43ff0c18 | 12914 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12915 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 12916 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 12917 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 12918 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 12919 | * |
mbed_official | 146:f64d43ff0c18 | 12920 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12921 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 12922 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 12923 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 12924 | */ |
mbed_official | 146:f64d43ff0c18 | 12925 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12926 | #define BP_AIPS_PACRO_SP1 (26U) //!< Bit position for AIPS_PACRO_SP1. |
mbed_official | 146:f64d43ff0c18 | 12927 | #define BM_AIPS_PACRO_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRO_SP1. |
mbed_official | 146:f64d43ff0c18 | 12928 | #define BS_AIPS_PACRO_SP1 (1U) //!< Bit field size in bits for AIPS_PACRO_SP1. |
mbed_official | 146:f64d43ff0c18 | 12929 | |
mbed_official | 146:f64d43ff0c18 | 12930 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12931 | //! @brief Read current value of the AIPS_PACRO_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 12932 | #define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1)) |
mbed_official | 146:f64d43ff0c18 | 12933 | #endif |
mbed_official | 146:f64d43ff0c18 | 12934 | |
mbed_official | 146:f64d43ff0c18 | 12935 | //! @brief Format value for bitfield AIPS_PACRO_SP1. |
mbed_official | 146:f64d43ff0c18 | 12936 | #define BF_AIPS_PACRO_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP1), uint32_t) & BM_AIPS_PACRO_SP1) |
mbed_official | 146:f64d43ff0c18 | 12937 | |
mbed_official | 146:f64d43ff0c18 | 12938 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12939 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12940 | #define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12941 | #endif |
mbed_official | 146:f64d43ff0c18 | 12942 | //@} |
mbed_official | 146:f64d43ff0c18 | 12943 | |
mbed_official | 146:f64d43ff0c18 | 12944 | /*! |
mbed_official | 146:f64d43ff0c18 | 12945 | * @name Register AIPS_PACRO, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 12946 | * |
mbed_official | 146:f64d43ff0c18 | 12947 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 12948 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 12949 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12950 | * |
mbed_official | 146:f64d43ff0c18 | 12951 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12952 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 12953 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 12954 | */ |
mbed_official | 146:f64d43ff0c18 | 12955 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12956 | #define BP_AIPS_PACRO_TP0 (28U) //!< Bit position for AIPS_PACRO_TP0. |
mbed_official | 146:f64d43ff0c18 | 12957 | #define BM_AIPS_PACRO_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRO_TP0. |
mbed_official | 146:f64d43ff0c18 | 12958 | #define BS_AIPS_PACRO_TP0 (1U) //!< Bit field size in bits for AIPS_PACRO_TP0. |
mbed_official | 146:f64d43ff0c18 | 12959 | |
mbed_official | 146:f64d43ff0c18 | 12960 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12961 | //! @brief Read current value of the AIPS_PACRO_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 12962 | #define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0)) |
mbed_official | 146:f64d43ff0c18 | 12963 | #endif |
mbed_official | 146:f64d43ff0c18 | 12964 | |
mbed_official | 146:f64d43ff0c18 | 12965 | //! @brief Format value for bitfield AIPS_PACRO_TP0. |
mbed_official | 146:f64d43ff0c18 | 12966 | #define BF_AIPS_PACRO_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP0), uint32_t) & BM_AIPS_PACRO_TP0) |
mbed_official | 146:f64d43ff0c18 | 12967 | |
mbed_official | 146:f64d43ff0c18 | 12968 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12969 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 12970 | #define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 12971 | #endif |
mbed_official | 146:f64d43ff0c18 | 12972 | //@} |
mbed_official | 146:f64d43ff0c18 | 12973 | |
mbed_official | 146:f64d43ff0c18 | 12974 | /*! |
mbed_official | 146:f64d43ff0c18 | 12975 | * @name Register AIPS_PACRO, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 12976 | * |
mbed_official | 146:f64d43ff0c18 | 12977 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 12978 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 12979 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 12980 | * |
mbed_official | 146:f64d43ff0c18 | 12981 | * Values: |
mbed_official | 146:f64d43ff0c18 | 12982 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 12983 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 12984 | */ |
mbed_official | 146:f64d43ff0c18 | 12985 | //@{ |
mbed_official | 146:f64d43ff0c18 | 12986 | #define BP_AIPS_PACRO_WP0 (29U) //!< Bit position for AIPS_PACRO_WP0. |
mbed_official | 146:f64d43ff0c18 | 12987 | #define BM_AIPS_PACRO_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRO_WP0. |
mbed_official | 146:f64d43ff0c18 | 12988 | #define BS_AIPS_PACRO_WP0 (1U) //!< Bit field size in bits for AIPS_PACRO_WP0. |
mbed_official | 146:f64d43ff0c18 | 12989 | |
mbed_official | 146:f64d43ff0c18 | 12990 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12991 | //! @brief Read current value of the AIPS_PACRO_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 12992 | #define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0)) |
mbed_official | 146:f64d43ff0c18 | 12993 | #endif |
mbed_official | 146:f64d43ff0c18 | 12994 | |
mbed_official | 146:f64d43ff0c18 | 12995 | //! @brief Format value for bitfield AIPS_PACRO_WP0. |
mbed_official | 146:f64d43ff0c18 | 12996 | #define BF_AIPS_PACRO_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP0), uint32_t) & BM_AIPS_PACRO_WP0) |
mbed_official | 146:f64d43ff0c18 | 12997 | |
mbed_official | 146:f64d43ff0c18 | 12998 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 12999 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13000 | #define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13001 | #endif |
mbed_official | 146:f64d43ff0c18 | 13002 | //@} |
mbed_official | 146:f64d43ff0c18 | 13003 | |
mbed_official | 146:f64d43ff0c18 | 13004 | /*! |
mbed_official | 146:f64d43ff0c18 | 13005 | * @name Register AIPS_PACRO, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 13006 | * |
mbed_official | 146:f64d43ff0c18 | 13007 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13008 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13009 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13010 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13011 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13012 | * |
mbed_official | 146:f64d43ff0c18 | 13013 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13014 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13015 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13016 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13017 | */ |
mbed_official | 146:f64d43ff0c18 | 13018 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13019 | #define BP_AIPS_PACRO_SP0 (30U) //!< Bit position for AIPS_PACRO_SP0. |
mbed_official | 146:f64d43ff0c18 | 13020 | #define BM_AIPS_PACRO_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRO_SP0. |
mbed_official | 146:f64d43ff0c18 | 13021 | #define BS_AIPS_PACRO_SP0 (1U) //!< Bit field size in bits for AIPS_PACRO_SP0. |
mbed_official | 146:f64d43ff0c18 | 13022 | |
mbed_official | 146:f64d43ff0c18 | 13023 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13024 | //! @brief Read current value of the AIPS_PACRO_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 13025 | #define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0)) |
mbed_official | 146:f64d43ff0c18 | 13026 | #endif |
mbed_official | 146:f64d43ff0c18 | 13027 | |
mbed_official | 146:f64d43ff0c18 | 13028 | //! @brief Format value for bitfield AIPS_PACRO_SP0. |
mbed_official | 146:f64d43ff0c18 | 13029 | #define BF_AIPS_PACRO_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP0), uint32_t) & BM_AIPS_PACRO_SP0) |
mbed_official | 146:f64d43ff0c18 | 13030 | |
mbed_official | 146:f64d43ff0c18 | 13031 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13032 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13033 | #define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13034 | #endif |
mbed_official | 146:f64d43ff0c18 | 13035 | //@} |
mbed_official | 146:f64d43ff0c18 | 13036 | |
mbed_official | 146:f64d43ff0c18 | 13037 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 13038 | // HW_AIPS_PACRP - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 13039 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 13040 | |
mbed_official | 146:f64d43ff0c18 | 13041 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13042 | /*! |
mbed_official | 146:f64d43ff0c18 | 13043 | * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 13044 | * |
mbed_official | 146:f64d43ff0c18 | 13045 | * Reset value: 0x44444444U |
mbed_official | 146:f64d43ff0c18 | 13046 | * |
mbed_official | 146:f64d43ff0c18 | 13047 | * This section describes PACR registers E-P, which control peripheral slots |
mbed_official | 146:f64d43ff0c18 | 13048 | * 32-127. See PACRPeripheral Access Control Register for the description of these |
mbed_official | 146:f64d43ff0c18 | 13049 | * registers. |
mbed_official | 146:f64d43ff0c18 | 13050 | */ |
mbed_official | 146:f64d43ff0c18 | 13051 | typedef union _hw_aips_pacrp |
mbed_official | 146:f64d43ff0c18 | 13052 | { |
mbed_official | 146:f64d43ff0c18 | 13053 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 13054 | struct _hw_aips_pacrp_bitfields |
mbed_official | 146:f64d43ff0c18 | 13055 | { |
mbed_official | 146:f64d43ff0c18 | 13056 | uint32_t TP7 : 1; //!< [0] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13057 | uint32_t WP7 : 1; //!< [1] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13058 | uint32_t SP7 : 1; //!< [2] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13059 | uint32_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 13060 | uint32_t TP6 : 1; //!< [4] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13061 | uint32_t WP6 : 1; //!< [5] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13062 | uint32_t SP6 : 1; //!< [6] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13063 | uint32_t RESERVED1 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 13064 | uint32_t TP5 : 1; //!< [8] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13065 | uint32_t WP5 : 1; //!< [9] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13066 | uint32_t SP5 : 1; //!< [10] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13067 | uint32_t RESERVED2 : 1; //!< [11] |
mbed_official | 146:f64d43ff0c18 | 13068 | uint32_t TP4 : 1; //!< [12] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13069 | uint32_t WP4 : 1; //!< [13] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13070 | uint32_t SP4 : 1; //!< [14] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13071 | uint32_t RESERVED3 : 1; //!< [15] |
mbed_official | 146:f64d43ff0c18 | 13072 | uint32_t TP3 : 1; //!< [16] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13073 | uint32_t WP3 : 1; //!< [17] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13074 | uint32_t SP3 : 1; //!< [18] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13075 | uint32_t RESERVED4 : 1; //!< [19] |
mbed_official | 146:f64d43ff0c18 | 13076 | uint32_t TP2 : 1; //!< [20] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13077 | uint32_t WP2 : 1; //!< [21] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13078 | uint32_t SP2 : 1; //!< [22] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13079 | uint32_t RESERVED5 : 1; //!< [23] |
mbed_official | 146:f64d43ff0c18 | 13080 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13081 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13082 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13083 | uint32_t RESERVED6 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 13084 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13085 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13086 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13087 | uint32_t RESERVED7 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 13088 | } B; |
mbed_official | 146:f64d43ff0c18 | 13089 | } hw_aips_pacrp_t; |
mbed_official | 146:f64d43ff0c18 | 13090 | #endif |
mbed_official | 146:f64d43ff0c18 | 13091 | |
mbed_official | 146:f64d43ff0c18 | 13092 | /*! |
mbed_official | 146:f64d43ff0c18 | 13093 | * @name Constants and macros for entire AIPS_PACRP register |
mbed_official | 146:f64d43ff0c18 | 13094 | */ |
mbed_official | 146:f64d43ff0c18 | 13095 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13096 | #define HW_AIPS_PACRP_ADDR(x) (REGS_AIPS_BASE(x) + 0x6CU) |
mbed_official | 146:f64d43ff0c18 | 13097 | |
mbed_official | 146:f64d43ff0c18 | 13098 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13099 | #define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 13100 | #define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U) |
mbed_official | 146:f64d43ff0c18 | 13101 | #define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 13102 | #define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 13103 | #define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 13104 | #define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 13105 | #endif |
mbed_official | 146:f64d43ff0c18 | 13106 | //@} |
mbed_official | 146:f64d43ff0c18 | 13107 | |
mbed_official | 146:f64d43ff0c18 | 13108 | /* |
mbed_official | 146:f64d43ff0c18 | 13109 | * Constants & macros for individual AIPS_PACRP bitfields |
mbed_official | 146:f64d43ff0c18 | 13110 | */ |
mbed_official | 146:f64d43ff0c18 | 13111 | |
mbed_official | 146:f64d43ff0c18 | 13112 | /*! |
mbed_official | 146:f64d43ff0c18 | 13113 | * @name Register AIPS_PACRP, field TP7[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 13114 | * |
mbed_official | 146:f64d43ff0c18 | 13115 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13116 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13117 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13118 | * |
mbed_official | 146:f64d43ff0c18 | 13119 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13120 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13121 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13122 | */ |
mbed_official | 146:f64d43ff0c18 | 13123 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13124 | #define BP_AIPS_PACRP_TP7 (0U) //!< Bit position for AIPS_PACRP_TP7. |
mbed_official | 146:f64d43ff0c18 | 13125 | #define BM_AIPS_PACRP_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRP_TP7. |
mbed_official | 146:f64d43ff0c18 | 13126 | #define BS_AIPS_PACRP_TP7 (1U) //!< Bit field size in bits for AIPS_PACRP_TP7. |
mbed_official | 146:f64d43ff0c18 | 13127 | |
mbed_official | 146:f64d43ff0c18 | 13128 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13129 | //! @brief Read current value of the AIPS_PACRP_TP7 field. |
mbed_official | 146:f64d43ff0c18 | 13130 | #define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7)) |
mbed_official | 146:f64d43ff0c18 | 13131 | #endif |
mbed_official | 146:f64d43ff0c18 | 13132 | |
mbed_official | 146:f64d43ff0c18 | 13133 | //! @brief Format value for bitfield AIPS_PACRP_TP7. |
mbed_official | 146:f64d43ff0c18 | 13134 | #define BF_AIPS_PACRP_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP7), uint32_t) & BM_AIPS_PACRP_TP7) |
mbed_official | 146:f64d43ff0c18 | 13135 | |
mbed_official | 146:f64d43ff0c18 | 13136 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13137 | //! @brief Set the TP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13138 | #define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13139 | #endif |
mbed_official | 146:f64d43ff0c18 | 13140 | //@} |
mbed_official | 146:f64d43ff0c18 | 13141 | |
mbed_official | 146:f64d43ff0c18 | 13142 | /*! |
mbed_official | 146:f64d43ff0c18 | 13143 | * @name Register AIPS_PACRP, field WP7[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 13144 | * |
mbed_official | 146:f64d43ff0c18 | 13145 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13146 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13147 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13148 | * |
mbed_official | 146:f64d43ff0c18 | 13149 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13150 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13151 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13152 | */ |
mbed_official | 146:f64d43ff0c18 | 13153 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13154 | #define BP_AIPS_PACRP_WP7 (1U) //!< Bit position for AIPS_PACRP_WP7. |
mbed_official | 146:f64d43ff0c18 | 13155 | #define BM_AIPS_PACRP_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRP_WP7. |
mbed_official | 146:f64d43ff0c18 | 13156 | #define BS_AIPS_PACRP_WP7 (1U) //!< Bit field size in bits for AIPS_PACRP_WP7. |
mbed_official | 146:f64d43ff0c18 | 13157 | |
mbed_official | 146:f64d43ff0c18 | 13158 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13159 | //! @brief Read current value of the AIPS_PACRP_WP7 field. |
mbed_official | 146:f64d43ff0c18 | 13160 | #define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7)) |
mbed_official | 146:f64d43ff0c18 | 13161 | #endif |
mbed_official | 146:f64d43ff0c18 | 13162 | |
mbed_official | 146:f64d43ff0c18 | 13163 | //! @brief Format value for bitfield AIPS_PACRP_WP7. |
mbed_official | 146:f64d43ff0c18 | 13164 | #define BF_AIPS_PACRP_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP7), uint32_t) & BM_AIPS_PACRP_WP7) |
mbed_official | 146:f64d43ff0c18 | 13165 | |
mbed_official | 146:f64d43ff0c18 | 13166 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13167 | //! @brief Set the WP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13168 | #define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13169 | #endif |
mbed_official | 146:f64d43ff0c18 | 13170 | //@} |
mbed_official | 146:f64d43ff0c18 | 13171 | |
mbed_official | 146:f64d43ff0c18 | 13172 | /*! |
mbed_official | 146:f64d43ff0c18 | 13173 | * @name Register AIPS_PACRP, field SP7[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 13174 | * |
mbed_official | 146:f64d43ff0c18 | 13175 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13176 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13177 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13178 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13179 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13180 | * |
mbed_official | 146:f64d43ff0c18 | 13181 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13182 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13183 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13184 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13185 | */ |
mbed_official | 146:f64d43ff0c18 | 13186 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13187 | #define BP_AIPS_PACRP_SP7 (2U) //!< Bit position for AIPS_PACRP_SP7. |
mbed_official | 146:f64d43ff0c18 | 13188 | #define BM_AIPS_PACRP_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRP_SP7. |
mbed_official | 146:f64d43ff0c18 | 13189 | #define BS_AIPS_PACRP_SP7 (1U) //!< Bit field size in bits for AIPS_PACRP_SP7. |
mbed_official | 146:f64d43ff0c18 | 13190 | |
mbed_official | 146:f64d43ff0c18 | 13191 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13192 | //! @brief Read current value of the AIPS_PACRP_SP7 field. |
mbed_official | 146:f64d43ff0c18 | 13193 | #define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7)) |
mbed_official | 146:f64d43ff0c18 | 13194 | #endif |
mbed_official | 146:f64d43ff0c18 | 13195 | |
mbed_official | 146:f64d43ff0c18 | 13196 | //! @brief Format value for bitfield AIPS_PACRP_SP7. |
mbed_official | 146:f64d43ff0c18 | 13197 | #define BF_AIPS_PACRP_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP7), uint32_t) & BM_AIPS_PACRP_SP7) |
mbed_official | 146:f64d43ff0c18 | 13198 | |
mbed_official | 146:f64d43ff0c18 | 13199 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13200 | //! @brief Set the SP7 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13201 | #define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13202 | #endif |
mbed_official | 146:f64d43ff0c18 | 13203 | //@} |
mbed_official | 146:f64d43ff0c18 | 13204 | |
mbed_official | 146:f64d43ff0c18 | 13205 | /*! |
mbed_official | 146:f64d43ff0c18 | 13206 | * @name Register AIPS_PACRP, field TP6[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 13207 | * |
mbed_official | 146:f64d43ff0c18 | 13208 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13209 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13210 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13211 | * |
mbed_official | 146:f64d43ff0c18 | 13212 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13213 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13214 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13215 | */ |
mbed_official | 146:f64d43ff0c18 | 13216 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13217 | #define BP_AIPS_PACRP_TP6 (4U) //!< Bit position for AIPS_PACRP_TP6. |
mbed_official | 146:f64d43ff0c18 | 13218 | #define BM_AIPS_PACRP_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRP_TP6. |
mbed_official | 146:f64d43ff0c18 | 13219 | #define BS_AIPS_PACRP_TP6 (1U) //!< Bit field size in bits for AIPS_PACRP_TP6. |
mbed_official | 146:f64d43ff0c18 | 13220 | |
mbed_official | 146:f64d43ff0c18 | 13221 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13222 | //! @brief Read current value of the AIPS_PACRP_TP6 field. |
mbed_official | 146:f64d43ff0c18 | 13223 | #define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6)) |
mbed_official | 146:f64d43ff0c18 | 13224 | #endif |
mbed_official | 146:f64d43ff0c18 | 13225 | |
mbed_official | 146:f64d43ff0c18 | 13226 | //! @brief Format value for bitfield AIPS_PACRP_TP6. |
mbed_official | 146:f64d43ff0c18 | 13227 | #define BF_AIPS_PACRP_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP6), uint32_t) & BM_AIPS_PACRP_TP6) |
mbed_official | 146:f64d43ff0c18 | 13228 | |
mbed_official | 146:f64d43ff0c18 | 13229 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13230 | //! @brief Set the TP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13231 | #define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13232 | #endif |
mbed_official | 146:f64d43ff0c18 | 13233 | //@} |
mbed_official | 146:f64d43ff0c18 | 13234 | |
mbed_official | 146:f64d43ff0c18 | 13235 | /*! |
mbed_official | 146:f64d43ff0c18 | 13236 | * @name Register AIPS_PACRP, field WP6[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 13237 | * |
mbed_official | 146:f64d43ff0c18 | 13238 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13239 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13240 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13241 | * |
mbed_official | 146:f64d43ff0c18 | 13242 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13243 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13244 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13245 | */ |
mbed_official | 146:f64d43ff0c18 | 13246 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13247 | #define BP_AIPS_PACRP_WP6 (5U) //!< Bit position for AIPS_PACRP_WP6. |
mbed_official | 146:f64d43ff0c18 | 13248 | #define BM_AIPS_PACRP_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRP_WP6. |
mbed_official | 146:f64d43ff0c18 | 13249 | #define BS_AIPS_PACRP_WP6 (1U) //!< Bit field size in bits for AIPS_PACRP_WP6. |
mbed_official | 146:f64d43ff0c18 | 13250 | |
mbed_official | 146:f64d43ff0c18 | 13251 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13252 | //! @brief Read current value of the AIPS_PACRP_WP6 field. |
mbed_official | 146:f64d43ff0c18 | 13253 | #define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6)) |
mbed_official | 146:f64d43ff0c18 | 13254 | #endif |
mbed_official | 146:f64d43ff0c18 | 13255 | |
mbed_official | 146:f64d43ff0c18 | 13256 | //! @brief Format value for bitfield AIPS_PACRP_WP6. |
mbed_official | 146:f64d43ff0c18 | 13257 | #define BF_AIPS_PACRP_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP6), uint32_t) & BM_AIPS_PACRP_WP6) |
mbed_official | 146:f64d43ff0c18 | 13258 | |
mbed_official | 146:f64d43ff0c18 | 13259 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13260 | //! @brief Set the WP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13261 | #define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13262 | #endif |
mbed_official | 146:f64d43ff0c18 | 13263 | //@} |
mbed_official | 146:f64d43ff0c18 | 13264 | |
mbed_official | 146:f64d43ff0c18 | 13265 | /*! |
mbed_official | 146:f64d43ff0c18 | 13266 | * @name Register AIPS_PACRP, field SP6[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 13267 | * |
mbed_official | 146:f64d43ff0c18 | 13268 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13269 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13270 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13271 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13272 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13273 | * |
mbed_official | 146:f64d43ff0c18 | 13274 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13275 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13276 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13277 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13278 | */ |
mbed_official | 146:f64d43ff0c18 | 13279 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13280 | #define BP_AIPS_PACRP_SP6 (6U) //!< Bit position for AIPS_PACRP_SP6. |
mbed_official | 146:f64d43ff0c18 | 13281 | #define BM_AIPS_PACRP_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRP_SP6. |
mbed_official | 146:f64d43ff0c18 | 13282 | #define BS_AIPS_PACRP_SP6 (1U) //!< Bit field size in bits for AIPS_PACRP_SP6. |
mbed_official | 146:f64d43ff0c18 | 13283 | |
mbed_official | 146:f64d43ff0c18 | 13284 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13285 | //! @brief Read current value of the AIPS_PACRP_SP6 field. |
mbed_official | 146:f64d43ff0c18 | 13286 | #define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6)) |
mbed_official | 146:f64d43ff0c18 | 13287 | #endif |
mbed_official | 146:f64d43ff0c18 | 13288 | |
mbed_official | 146:f64d43ff0c18 | 13289 | //! @brief Format value for bitfield AIPS_PACRP_SP6. |
mbed_official | 146:f64d43ff0c18 | 13290 | #define BF_AIPS_PACRP_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP6), uint32_t) & BM_AIPS_PACRP_SP6) |
mbed_official | 146:f64d43ff0c18 | 13291 | |
mbed_official | 146:f64d43ff0c18 | 13292 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13293 | //! @brief Set the SP6 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13294 | #define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13295 | #endif |
mbed_official | 146:f64d43ff0c18 | 13296 | //@} |
mbed_official | 146:f64d43ff0c18 | 13297 | |
mbed_official | 146:f64d43ff0c18 | 13298 | /*! |
mbed_official | 146:f64d43ff0c18 | 13299 | * @name Register AIPS_PACRP, field TP5[8] (RW) |
mbed_official | 146:f64d43ff0c18 | 13300 | * |
mbed_official | 146:f64d43ff0c18 | 13301 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13302 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13303 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13304 | * |
mbed_official | 146:f64d43ff0c18 | 13305 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13306 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13307 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13308 | */ |
mbed_official | 146:f64d43ff0c18 | 13309 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13310 | #define BP_AIPS_PACRP_TP5 (8U) //!< Bit position for AIPS_PACRP_TP5. |
mbed_official | 146:f64d43ff0c18 | 13311 | #define BM_AIPS_PACRP_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRP_TP5. |
mbed_official | 146:f64d43ff0c18 | 13312 | #define BS_AIPS_PACRP_TP5 (1U) //!< Bit field size in bits for AIPS_PACRP_TP5. |
mbed_official | 146:f64d43ff0c18 | 13313 | |
mbed_official | 146:f64d43ff0c18 | 13314 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13315 | //! @brief Read current value of the AIPS_PACRP_TP5 field. |
mbed_official | 146:f64d43ff0c18 | 13316 | #define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5)) |
mbed_official | 146:f64d43ff0c18 | 13317 | #endif |
mbed_official | 146:f64d43ff0c18 | 13318 | |
mbed_official | 146:f64d43ff0c18 | 13319 | //! @brief Format value for bitfield AIPS_PACRP_TP5. |
mbed_official | 146:f64d43ff0c18 | 13320 | #define BF_AIPS_PACRP_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP5), uint32_t) & BM_AIPS_PACRP_TP5) |
mbed_official | 146:f64d43ff0c18 | 13321 | |
mbed_official | 146:f64d43ff0c18 | 13322 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13323 | //! @brief Set the TP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13324 | #define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13325 | #endif |
mbed_official | 146:f64d43ff0c18 | 13326 | //@} |
mbed_official | 146:f64d43ff0c18 | 13327 | |
mbed_official | 146:f64d43ff0c18 | 13328 | /*! |
mbed_official | 146:f64d43ff0c18 | 13329 | * @name Register AIPS_PACRP, field WP5[9] (RW) |
mbed_official | 146:f64d43ff0c18 | 13330 | * |
mbed_official | 146:f64d43ff0c18 | 13331 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13332 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13333 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13334 | * |
mbed_official | 146:f64d43ff0c18 | 13335 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13336 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13337 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13338 | */ |
mbed_official | 146:f64d43ff0c18 | 13339 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13340 | #define BP_AIPS_PACRP_WP5 (9U) //!< Bit position for AIPS_PACRP_WP5. |
mbed_official | 146:f64d43ff0c18 | 13341 | #define BM_AIPS_PACRP_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRP_WP5. |
mbed_official | 146:f64d43ff0c18 | 13342 | #define BS_AIPS_PACRP_WP5 (1U) //!< Bit field size in bits for AIPS_PACRP_WP5. |
mbed_official | 146:f64d43ff0c18 | 13343 | |
mbed_official | 146:f64d43ff0c18 | 13344 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13345 | //! @brief Read current value of the AIPS_PACRP_WP5 field. |
mbed_official | 146:f64d43ff0c18 | 13346 | #define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5)) |
mbed_official | 146:f64d43ff0c18 | 13347 | #endif |
mbed_official | 146:f64d43ff0c18 | 13348 | |
mbed_official | 146:f64d43ff0c18 | 13349 | //! @brief Format value for bitfield AIPS_PACRP_WP5. |
mbed_official | 146:f64d43ff0c18 | 13350 | #define BF_AIPS_PACRP_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP5), uint32_t) & BM_AIPS_PACRP_WP5) |
mbed_official | 146:f64d43ff0c18 | 13351 | |
mbed_official | 146:f64d43ff0c18 | 13352 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13353 | //! @brief Set the WP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13354 | #define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13355 | #endif |
mbed_official | 146:f64d43ff0c18 | 13356 | //@} |
mbed_official | 146:f64d43ff0c18 | 13357 | |
mbed_official | 146:f64d43ff0c18 | 13358 | /*! |
mbed_official | 146:f64d43ff0c18 | 13359 | * @name Register AIPS_PACRP, field SP5[10] (RW) |
mbed_official | 146:f64d43ff0c18 | 13360 | * |
mbed_official | 146:f64d43ff0c18 | 13361 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13362 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13363 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13364 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13365 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13366 | * |
mbed_official | 146:f64d43ff0c18 | 13367 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13368 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13369 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13370 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13371 | */ |
mbed_official | 146:f64d43ff0c18 | 13372 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13373 | #define BP_AIPS_PACRP_SP5 (10U) //!< Bit position for AIPS_PACRP_SP5. |
mbed_official | 146:f64d43ff0c18 | 13374 | #define BM_AIPS_PACRP_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRP_SP5. |
mbed_official | 146:f64d43ff0c18 | 13375 | #define BS_AIPS_PACRP_SP5 (1U) //!< Bit field size in bits for AIPS_PACRP_SP5. |
mbed_official | 146:f64d43ff0c18 | 13376 | |
mbed_official | 146:f64d43ff0c18 | 13377 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13378 | //! @brief Read current value of the AIPS_PACRP_SP5 field. |
mbed_official | 146:f64d43ff0c18 | 13379 | #define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5)) |
mbed_official | 146:f64d43ff0c18 | 13380 | #endif |
mbed_official | 146:f64d43ff0c18 | 13381 | |
mbed_official | 146:f64d43ff0c18 | 13382 | //! @brief Format value for bitfield AIPS_PACRP_SP5. |
mbed_official | 146:f64d43ff0c18 | 13383 | #define BF_AIPS_PACRP_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP5), uint32_t) & BM_AIPS_PACRP_SP5) |
mbed_official | 146:f64d43ff0c18 | 13384 | |
mbed_official | 146:f64d43ff0c18 | 13385 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13386 | //! @brief Set the SP5 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13387 | #define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13388 | #endif |
mbed_official | 146:f64d43ff0c18 | 13389 | //@} |
mbed_official | 146:f64d43ff0c18 | 13390 | |
mbed_official | 146:f64d43ff0c18 | 13391 | /*! |
mbed_official | 146:f64d43ff0c18 | 13392 | * @name Register AIPS_PACRP, field TP4[12] (RW) |
mbed_official | 146:f64d43ff0c18 | 13393 | * |
mbed_official | 146:f64d43ff0c18 | 13394 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13395 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13396 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13397 | * |
mbed_official | 146:f64d43ff0c18 | 13398 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13399 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13400 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13401 | */ |
mbed_official | 146:f64d43ff0c18 | 13402 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13403 | #define BP_AIPS_PACRP_TP4 (12U) //!< Bit position for AIPS_PACRP_TP4. |
mbed_official | 146:f64d43ff0c18 | 13404 | #define BM_AIPS_PACRP_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRP_TP4. |
mbed_official | 146:f64d43ff0c18 | 13405 | #define BS_AIPS_PACRP_TP4 (1U) //!< Bit field size in bits for AIPS_PACRP_TP4. |
mbed_official | 146:f64d43ff0c18 | 13406 | |
mbed_official | 146:f64d43ff0c18 | 13407 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13408 | //! @brief Read current value of the AIPS_PACRP_TP4 field. |
mbed_official | 146:f64d43ff0c18 | 13409 | #define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4)) |
mbed_official | 146:f64d43ff0c18 | 13410 | #endif |
mbed_official | 146:f64d43ff0c18 | 13411 | |
mbed_official | 146:f64d43ff0c18 | 13412 | //! @brief Format value for bitfield AIPS_PACRP_TP4. |
mbed_official | 146:f64d43ff0c18 | 13413 | #define BF_AIPS_PACRP_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP4), uint32_t) & BM_AIPS_PACRP_TP4) |
mbed_official | 146:f64d43ff0c18 | 13414 | |
mbed_official | 146:f64d43ff0c18 | 13415 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13416 | //! @brief Set the TP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13417 | #define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13418 | #endif |
mbed_official | 146:f64d43ff0c18 | 13419 | //@} |
mbed_official | 146:f64d43ff0c18 | 13420 | |
mbed_official | 146:f64d43ff0c18 | 13421 | /*! |
mbed_official | 146:f64d43ff0c18 | 13422 | * @name Register AIPS_PACRP, field WP4[13] (RW) |
mbed_official | 146:f64d43ff0c18 | 13423 | * |
mbed_official | 146:f64d43ff0c18 | 13424 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13425 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13426 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13427 | * |
mbed_official | 146:f64d43ff0c18 | 13428 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13429 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13430 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13431 | */ |
mbed_official | 146:f64d43ff0c18 | 13432 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13433 | #define BP_AIPS_PACRP_WP4 (13U) //!< Bit position for AIPS_PACRP_WP4. |
mbed_official | 146:f64d43ff0c18 | 13434 | #define BM_AIPS_PACRP_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRP_WP4. |
mbed_official | 146:f64d43ff0c18 | 13435 | #define BS_AIPS_PACRP_WP4 (1U) //!< Bit field size in bits for AIPS_PACRP_WP4. |
mbed_official | 146:f64d43ff0c18 | 13436 | |
mbed_official | 146:f64d43ff0c18 | 13437 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13438 | //! @brief Read current value of the AIPS_PACRP_WP4 field. |
mbed_official | 146:f64d43ff0c18 | 13439 | #define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4)) |
mbed_official | 146:f64d43ff0c18 | 13440 | #endif |
mbed_official | 146:f64d43ff0c18 | 13441 | |
mbed_official | 146:f64d43ff0c18 | 13442 | //! @brief Format value for bitfield AIPS_PACRP_WP4. |
mbed_official | 146:f64d43ff0c18 | 13443 | #define BF_AIPS_PACRP_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP4), uint32_t) & BM_AIPS_PACRP_WP4) |
mbed_official | 146:f64d43ff0c18 | 13444 | |
mbed_official | 146:f64d43ff0c18 | 13445 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13446 | //! @brief Set the WP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13447 | #define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13448 | #endif |
mbed_official | 146:f64d43ff0c18 | 13449 | //@} |
mbed_official | 146:f64d43ff0c18 | 13450 | |
mbed_official | 146:f64d43ff0c18 | 13451 | /*! |
mbed_official | 146:f64d43ff0c18 | 13452 | * @name Register AIPS_PACRP, field SP4[14] (RW) |
mbed_official | 146:f64d43ff0c18 | 13453 | * |
mbed_official | 146:f64d43ff0c18 | 13454 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13455 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13456 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 13457 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 13458 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 13459 | * |
mbed_official | 146:f64d43ff0c18 | 13460 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13461 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13462 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13463 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13464 | */ |
mbed_official | 146:f64d43ff0c18 | 13465 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13466 | #define BP_AIPS_PACRP_SP4 (14U) //!< Bit position for AIPS_PACRP_SP4. |
mbed_official | 146:f64d43ff0c18 | 13467 | #define BM_AIPS_PACRP_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRP_SP4. |
mbed_official | 146:f64d43ff0c18 | 13468 | #define BS_AIPS_PACRP_SP4 (1U) //!< Bit field size in bits for AIPS_PACRP_SP4. |
mbed_official | 146:f64d43ff0c18 | 13469 | |
mbed_official | 146:f64d43ff0c18 | 13470 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13471 | //! @brief Read current value of the AIPS_PACRP_SP4 field. |
mbed_official | 146:f64d43ff0c18 | 13472 | #define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4)) |
mbed_official | 146:f64d43ff0c18 | 13473 | #endif |
mbed_official | 146:f64d43ff0c18 | 13474 | |
mbed_official | 146:f64d43ff0c18 | 13475 | //! @brief Format value for bitfield AIPS_PACRP_SP4. |
mbed_official | 146:f64d43ff0c18 | 13476 | #define BF_AIPS_PACRP_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP4), uint32_t) & BM_AIPS_PACRP_SP4) |
mbed_official | 146:f64d43ff0c18 | 13477 | |
mbed_official | 146:f64d43ff0c18 | 13478 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13479 | //! @brief Set the SP4 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13480 | #define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13481 | #endif |
mbed_official | 146:f64d43ff0c18 | 13482 | //@} |
mbed_official | 146:f64d43ff0c18 | 13483 | |
mbed_official | 146:f64d43ff0c18 | 13484 | /*! |
mbed_official | 146:f64d43ff0c18 | 13485 | * @name Register AIPS_PACRP, field TP3[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 13486 | * |
mbed_official | 146:f64d43ff0c18 | 13487 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13488 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13489 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13490 | * |
mbed_official | 146:f64d43ff0c18 | 13491 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13492 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13493 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13494 | */ |
mbed_official | 146:f64d43ff0c18 | 13495 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13496 | #define BP_AIPS_PACRP_TP3 (16U) //!< Bit position for AIPS_PACRP_TP3. |
mbed_official | 146:f64d43ff0c18 | 13497 | #define BM_AIPS_PACRP_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRP_TP3. |
mbed_official | 146:f64d43ff0c18 | 13498 | #define BS_AIPS_PACRP_TP3 (1U) //!< Bit field size in bits for AIPS_PACRP_TP3. |
mbed_official | 146:f64d43ff0c18 | 13499 | |
mbed_official | 146:f64d43ff0c18 | 13500 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13501 | //! @brief Read current value of the AIPS_PACRP_TP3 field. |
mbed_official | 146:f64d43ff0c18 | 13502 | #define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3)) |
mbed_official | 146:f64d43ff0c18 | 13503 | #endif |
mbed_official | 146:f64d43ff0c18 | 13504 | |
mbed_official | 146:f64d43ff0c18 | 13505 | //! @brief Format value for bitfield AIPS_PACRP_TP3. |
mbed_official | 146:f64d43ff0c18 | 13506 | #define BF_AIPS_PACRP_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP3), uint32_t) & BM_AIPS_PACRP_TP3) |
mbed_official | 146:f64d43ff0c18 | 13507 | |
mbed_official | 146:f64d43ff0c18 | 13508 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13509 | //! @brief Set the TP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13510 | #define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13511 | #endif |
mbed_official | 146:f64d43ff0c18 | 13512 | //@} |
mbed_official | 146:f64d43ff0c18 | 13513 | |
mbed_official | 146:f64d43ff0c18 | 13514 | /*! |
mbed_official | 146:f64d43ff0c18 | 13515 | * @name Register AIPS_PACRP, field WP3[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 13516 | * |
mbed_official | 146:f64d43ff0c18 | 13517 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 13518 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 13519 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13520 | * |
mbed_official | 146:f64d43ff0c18 | 13521 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13522 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13523 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13524 | */ |
mbed_official | 146:f64d43ff0c18 | 13525 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13526 | #define BP_AIPS_PACRP_WP3 (17U) //!< Bit position for AIPS_PACRP_WP3. |
mbed_official | 146:f64d43ff0c18 | 13527 | #define BM_AIPS_PACRP_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRP_WP3. |
mbed_official | 146:f64d43ff0c18 | 13528 | #define BS_AIPS_PACRP_WP3 (1U) //!< Bit field size in bits for AIPS_PACRP_WP3. |
mbed_official | 146:f64d43ff0c18 | 13529 | |
mbed_official | 146:f64d43ff0c18 | 13530 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13531 | //! @brief Read current value of the AIPS_PACRP_WP3 field. |
mbed_official | 146:f64d43ff0c18 | 13532 | #define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3)) |
mbed_official | 146:f64d43ff0c18 | 13533 | #endif |
mbed_official | 146:f64d43ff0c18 | 13534 | |
mbed_official | 146:f64d43ff0c18 | 13535 | //! @brief Format value for bitfield AIPS_PACRP_WP3. |
mbed_official | 146:f64d43ff0c18 | 13536 | #define BF_AIPS_PACRP_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP3), uint32_t) & BM_AIPS_PACRP_WP3) |
mbed_official | 146:f64d43ff0c18 | 13537 | |
mbed_official | 146:f64d43ff0c18 | 13538 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13539 | //! @brief Set the WP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13540 | #define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13541 | #endif |
mbed_official | 146:f64d43ff0c18 | 13542 | //@} |
mbed_official | 146:f64d43ff0c18 | 13543 | |
mbed_official | 146:f64d43ff0c18 | 13544 | /*! |
mbed_official | 146:f64d43ff0c18 | 13545 | * @name Register AIPS_PACRP, field SP3[18] (RW) |
mbed_official | 146:f64d43ff0c18 | 13546 | * |
mbed_official | 146:f64d43ff0c18 | 13547 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13548 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13549 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13550 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13551 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13552 | * |
mbed_official | 146:f64d43ff0c18 | 13553 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13554 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13555 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13556 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13557 | */ |
mbed_official | 146:f64d43ff0c18 | 13558 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13559 | #define BP_AIPS_PACRP_SP3 (18U) //!< Bit position for AIPS_PACRP_SP3. |
mbed_official | 146:f64d43ff0c18 | 13560 | #define BM_AIPS_PACRP_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRP_SP3. |
mbed_official | 146:f64d43ff0c18 | 13561 | #define BS_AIPS_PACRP_SP3 (1U) //!< Bit field size in bits for AIPS_PACRP_SP3. |
mbed_official | 146:f64d43ff0c18 | 13562 | |
mbed_official | 146:f64d43ff0c18 | 13563 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13564 | //! @brief Read current value of the AIPS_PACRP_SP3 field. |
mbed_official | 146:f64d43ff0c18 | 13565 | #define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3)) |
mbed_official | 146:f64d43ff0c18 | 13566 | #endif |
mbed_official | 146:f64d43ff0c18 | 13567 | |
mbed_official | 146:f64d43ff0c18 | 13568 | //! @brief Format value for bitfield AIPS_PACRP_SP3. |
mbed_official | 146:f64d43ff0c18 | 13569 | #define BF_AIPS_PACRP_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP3), uint32_t) & BM_AIPS_PACRP_SP3) |
mbed_official | 146:f64d43ff0c18 | 13570 | |
mbed_official | 146:f64d43ff0c18 | 13571 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13572 | //! @brief Set the SP3 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13573 | #define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13574 | #endif |
mbed_official | 146:f64d43ff0c18 | 13575 | //@} |
mbed_official | 146:f64d43ff0c18 | 13576 | |
mbed_official | 146:f64d43ff0c18 | 13577 | /*! |
mbed_official | 146:f64d43ff0c18 | 13578 | * @name Register AIPS_PACRP, field TP2[20] (RW) |
mbed_official | 146:f64d43ff0c18 | 13579 | * |
mbed_official | 146:f64d43ff0c18 | 13580 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13581 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13582 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13583 | * |
mbed_official | 146:f64d43ff0c18 | 13584 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13585 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13586 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13587 | */ |
mbed_official | 146:f64d43ff0c18 | 13588 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13589 | #define BP_AIPS_PACRP_TP2 (20U) //!< Bit position for AIPS_PACRP_TP2. |
mbed_official | 146:f64d43ff0c18 | 13590 | #define BM_AIPS_PACRP_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRP_TP2. |
mbed_official | 146:f64d43ff0c18 | 13591 | #define BS_AIPS_PACRP_TP2 (1U) //!< Bit field size in bits for AIPS_PACRP_TP2. |
mbed_official | 146:f64d43ff0c18 | 13592 | |
mbed_official | 146:f64d43ff0c18 | 13593 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13594 | //! @brief Read current value of the AIPS_PACRP_TP2 field. |
mbed_official | 146:f64d43ff0c18 | 13595 | #define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2)) |
mbed_official | 146:f64d43ff0c18 | 13596 | #endif |
mbed_official | 146:f64d43ff0c18 | 13597 | |
mbed_official | 146:f64d43ff0c18 | 13598 | //! @brief Format value for bitfield AIPS_PACRP_TP2. |
mbed_official | 146:f64d43ff0c18 | 13599 | #define BF_AIPS_PACRP_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP2), uint32_t) & BM_AIPS_PACRP_TP2) |
mbed_official | 146:f64d43ff0c18 | 13600 | |
mbed_official | 146:f64d43ff0c18 | 13601 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13602 | //! @brief Set the TP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13603 | #define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13604 | #endif |
mbed_official | 146:f64d43ff0c18 | 13605 | //@} |
mbed_official | 146:f64d43ff0c18 | 13606 | |
mbed_official | 146:f64d43ff0c18 | 13607 | /*! |
mbed_official | 146:f64d43ff0c18 | 13608 | * @name Register AIPS_PACRP, field WP2[21] (RW) |
mbed_official | 146:f64d43ff0c18 | 13609 | * |
mbed_official | 146:f64d43ff0c18 | 13610 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13611 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13612 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13613 | * |
mbed_official | 146:f64d43ff0c18 | 13614 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13615 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13616 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13617 | */ |
mbed_official | 146:f64d43ff0c18 | 13618 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13619 | #define BP_AIPS_PACRP_WP2 (21U) //!< Bit position for AIPS_PACRP_WP2. |
mbed_official | 146:f64d43ff0c18 | 13620 | #define BM_AIPS_PACRP_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRP_WP2. |
mbed_official | 146:f64d43ff0c18 | 13621 | #define BS_AIPS_PACRP_WP2 (1U) //!< Bit field size in bits for AIPS_PACRP_WP2. |
mbed_official | 146:f64d43ff0c18 | 13622 | |
mbed_official | 146:f64d43ff0c18 | 13623 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13624 | //! @brief Read current value of the AIPS_PACRP_WP2 field. |
mbed_official | 146:f64d43ff0c18 | 13625 | #define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2)) |
mbed_official | 146:f64d43ff0c18 | 13626 | #endif |
mbed_official | 146:f64d43ff0c18 | 13627 | |
mbed_official | 146:f64d43ff0c18 | 13628 | //! @brief Format value for bitfield AIPS_PACRP_WP2. |
mbed_official | 146:f64d43ff0c18 | 13629 | #define BF_AIPS_PACRP_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP2), uint32_t) & BM_AIPS_PACRP_WP2) |
mbed_official | 146:f64d43ff0c18 | 13630 | |
mbed_official | 146:f64d43ff0c18 | 13631 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13632 | //! @brief Set the WP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13633 | #define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13634 | #endif |
mbed_official | 146:f64d43ff0c18 | 13635 | //@} |
mbed_official | 146:f64d43ff0c18 | 13636 | |
mbed_official | 146:f64d43ff0c18 | 13637 | /*! |
mbed_official | 146:f64d43ff0c18 | 13638 | * @name Register AIPS_PACRP, field SP2[22] (RW) |
mbed_official | 146:f64d43ff0c18 | 13639 | * |
mbed_official | 146:f64d43ff0c18 | 13640 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13641 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13642 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 13643 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 13644 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 13645 | * |
mbed_official | 146:f64d43ff0c18 | 13646 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13647 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13648 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13649 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13650 | */ |
mbed_official | 146:f64d43ff0c18 | 13651 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13652 | #define BP_AIPS_PACRP_SP2 (22U) //!< Bit position for AIPS_PACRP_SP2. |
mbed_official | 146:f64d43ff0c18 | 13653 | #define BM_AIPS_PACRP_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRP_SP2. |
mbed_official | 146:f64d43ff0c18 | 13654 | #define BS_AIPS_PACRP_SP2 (1U) //!< Bit field size in bits for AIPS_PACRP_SP2. |
mbed_official | 146:f64d43ff0c18 | 13655 | |
mbed_official | 146:f64d43ff0c18 | 13656 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13657 | //! @brief Read current value of the AIPS_PACRP_SP2 field. |
mbed_official | 146:f64d43ff0c18 | 13658 | #define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2)) |
mbed_official | 146:f64d43ff0c18 | 13659 | #endif |
mbed_official | 146:f64d43ff0c18 | 13660 | |
mbed_official | 146:f64d43ff0c18 | 13661 | //! @brief Format value for bitfield AIPS_PACRP_SP2. |
mbed_official | 146:f64d43ff0c18 | 13662 | #define BF_AIPS_PACRP_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP2), uint32_t) & BM_AIPS_PACRP_SP2) |
mbed_official | 146:f64d43ff0c18 | 13663 | |
mbed_official | 146:f64d43ff0c18 | 13664 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13665 | //! @brief Set the SP2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13666 | #define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13667 | #endif |
mbed_official | 146:f64d43ff0c18 | 13668 | //@} |
mbed_official | 146:f64d43ff0c18 | 13669 | |
mbed_official | 146:f64d43ff0c18 | 13670 | /*! |
mbed_official | 146:f64d43ff0c18 | 13671 | * @name Register AIPS_PACRP, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 13672 | * |
mbed_official | 146:f64d43ff0c18 | 13673 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13674 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13675 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13676 | * |
mbed_official | 146:f64d43ff0c18 | 13677 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13678 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13679 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13680 | */ |
mbed_official | 146:f64d43ff0c18 | 13681 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13682 | #define BP_AIPS_PACRP_TP1 (24U) //!< Bit position for AIPS_PACRP_TP1. |
mbed_official | 146:f64d43ff0c18 | 13683 | #define BM_AIPS_PACRP_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRP_TP1. |
mbed_official | 146:f64d43ff0c18 | 13684 | #define BS_AIPS_PACRP_TP1 (1U) //!< Bit field size in bits for AIPS_PACRP_TP1. |
mbed_official | 146:f64d43ff0c18 | 13685 | |
mbed_official | 146:f64d43ff0c18 | 13686 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13687 | //! @brief Read current value of the AIPS_PACRP_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 13688 | #define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1)) |
mbed_official | 146:f64d43ff0c18 | 13689 | #endif |
mbed_official | 146:f64d43ff0c18 | 13690 | |
mbed_official | 146:f64d43ff0c18 | 13691 | //! @brief Format value for bitfield AIPS_PACRP_TP1. |
mbed_official | 146:f64d43ff0c18 | 13692 | #define BF_AIPS_PACRP_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP1), uint32_t) & BM_AIPS_PACRP_TP1) |
mbed_official | 146:f64d43ff0c18 | 13693 | |
mbed_official | 146:f64d43ff0c18 | 13694 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13695 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13696 | #define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13697 | #endif |
mbed_official | 146:f64d43ff0c18 | 13698 | //@} |
mbed_official | 146:f64d43ff0c18 | 13699 | |
mbed_official | 146:f64d43ff0c18 | 13700 | /*! |
mbed_official | 146:f64d43ff0c18 | 13701 | * @name Register AIPS_PACRP, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 13702 | * |
mbed_official | 146:f64d43ff0c18 | 13703 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13704 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13705 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13706 | * |
mbed_official | 146:f64d43ff0c18 | 13707 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13708 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13709 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13710 | */ |
mbed_official | 146:f64d43ff0c18 | 13711 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13712 | #define BP_AIPS_PACRP_WP1 (25U) //!< Bit position for AIPS_PACRP_WP1. |
mbed_official | 146:f64d43ff0c18 | 13713 | #define BM_AIPS_PACRP_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRP_WP1. |
mbed_official | 146:f64d43ff0c18 | 13714 | #define BS_AIPS_PACRP_WP1 (1U) //!< Bit field size in bits for AIPS_PACRP_WP1. |
mbed_official | 146:f64d43ff0c18 | 13715 | |
mbed_official | 146:f64d43ff0c18 | 13716 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13717 | //! @brief Read current value of the AIPS_PACRP_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 13718 | #define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1)) |
mbed_official | 146:f64d43ff0c18 | 13719 | #endif |
mbed_official | 146:f64d43ff0c18 | 13720 | |
mbed_official | 146:f64d43ff0c18 | 13721 | //! @brief Format value for bitfield AIPS_PACRP_WP1. |
mbed_official | 146:f64d43ff0c18 | 13722 | #define BF_AIPS_PACRP_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP1), uint32_t) & BM_AIPS_PACRP_WP1) |
mbed_official | 146:f64d43ff0c18 | 13723 | |
mbed_official | 146:f64d43ff0c18 | 13724 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13725 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13726 | #define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13727 | #endif |
mbed_official | 146:f64d43ff0c18 | 13728 | //@} |
mbed_official | 146:f64d43ff0c18 | 13729 | |
mbed_official | 146:f64d43ff0c18 | 13730 | /*! |
mbed_official | 146:f64d43ff0c18 | 13731 | * @name Register AIPS_PACRP, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 13732 | * |
mbed_official | 146:f64d43ff0c18 | 13733 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13734 | * access. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13735 | * supervisor access attribute, and the MPRx[MPLn] control field for the master must |
mbed_official | 146:f64d43ff0c18 | 13736 | * be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13737 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13738 | * |
mbed_official | 146:f64d43ff0c18 | 13739 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13740 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13741 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13742 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13743 | */ |
mbed_official | 146:f64d43ff0c18 | 13744 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13745 | #define BP_AIPS_PACRP_SP1 (26U) //!< Bit position for AIPS_PACRP_SP1. |
mbed_official | 146:f64d43ff0c18 | 13746 | #define BM_AIPS_PACRP_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRP_SP1. |
mbed_official | 146:f64d43ff0c18 | 13747 | #define BS_AIPS_PACRP_SP1 (1U) //!< Bit field size in bits for AIPS_PACRP_SP1. |
mbed_official | 146:f64d43ff0c18 | 13748 | |
mbed_official | 146:f64d43ff0c18 | 13749 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13750 | //! @brief Read current value of the AIPS_PACRP_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 13751 | #define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1)) |
mbed_official | 146:f64d43ff0c18 | 13752 | #endif |
mbed_official | 146:f64d43ff0c18 | 13753 | |
mbed_official | 146:f64d43ff0c18 | 13754 | //! @brief Format value for bitfield AIPS_PACRP_SP1. |
mbed_official | 146:f64d43ff0c18 | 13755 | #define BF_AIPS_PACRP_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP1), uint32_t) & BM_AIPS_PACRP_SP1) |
mbed_official | 146:f64d43ff0c18 | 13756 | |
mbed_official | 146:f64d43ff0c18 | 13757 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13758 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13759 | #define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13760 | #endif |
mbed_official | 146:f64d43ff0c18 | 13761 | //@} |
mbed_official | 146:f64d43ff0c18 | 13762 | |
mbed_official | 146:f64d43ff0c18 | 13763 | /*! |
mbed_official | 146:f64d43ff0c18 | 13764 | * @name Register AIPS_PACRP, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 13765 | * |
mbed_official | 146:f64d43ff0c18 | 13766 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13767 | * When this bit is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13768 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13769 | * |
mbed_official | 146:f64d43ff0c18 | 13770 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13771 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13772 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13773 | */ |
mbed_official | 146:f64d43ff0c18 | 13774 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13775 | #define BP_AIPS_PACRP_TP0 (28U) //!< Bit position for AIPS_PACRP_TP0. |
mbed_official | 146:f64d43ff0c18 | 13776 | #define BM_AIPS_PACRP_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRP_TP0. |
mbed_official | 146:f64d43ff0c18 | 13777 | #define BS_AIPS_PACRP_TP0 (1U) //!< Bit field size in bits for AIPS_PACRP_TP0. |
mbed_official | 146:f64d43ff0c18 | 13778 | |
mbed_official | 146:f64d43ff0c18 | 13779 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13780 | //! @brief Read current value of the AIPS_PACRP_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 13781 | #define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0)) |
mbed_official | 146:f64d43ff0c18 | 13782 | #endif |
mbed_official | 146:f64d43ff0c18 | 13783 | |
mbed_official | 146:f64d43ff0c18 | 13784 | //! @brief Format value for bitfield AIPS_PACRP_TP0. |
mbed_official | 146:f64d43ff0c18 | 13785 | #define BF_AIPS_PACRP_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP0), uint32_t) & BM_AIPS_PACRP_TP0) |
mbed_official | 146:f64d43ff0c18 | 13786 | |
mbed_official | 146:f64d43ff0c18 | 13787 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13788 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13789 | #define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13790 | #endif |
mbed_official | 146:f64d43ff0c18 | 13791 | //@} |
mbed_official | 146:f64d43ff0c18 | 13792 | |
mbed_official | 146:f64d43ff0c18 | 13793 | /*! |
mbed_official | 146:f64d43ff0c18 | 13794 | * @name Register AIPS_PACRP, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 13795 | * |
mbed_official | 146:f64d43ff0c18 | 13796 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 13797 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 13798 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13799 | * |
mbed_official | 146:f64d43ff0c18 | 13800 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13801 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13802 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13803 | */ |
mbed_official | 146:f64d43ff0c18 | 13804 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13805 | #define BP_AIPS_PACRP_WP0 (29U) //!< Bit position for AIPS_PACRP_WP0. |
mbed_official | 146:f64d43ff0c18 | 13806 | #define BM_AIPS_PACRP_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRP_WP0. |
mbed_official | 146:f64d43ff0c18 | 13807 | #define BS_AIPS_PACRP_WP0 (1U) //!< Bit field size in bits for AIPS_PACRP_WP0. |
mbed_official | 146:f64d43ff0c18 | 13808 | |
mbed_official | 146:f64d43ff0c18 | 13809 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13810 | //! @brief Read current value of the AIPS_PACRP_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 13811 | #define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0)) |
mbed_official | 146:f64d43ff0c18 | 13812 | #endif |
mbed_official | 146:f64d43ff0c18 | 13813 | |
mbed_official | 146:f64d43ff0c18 | 13814 | //! @brief Format value for bitfield AIPS_PACRP_WP0. |
mbed_official | 146:f64d43ff0c18 | 13815 | #define BF_AIPS_PACRP_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP0), uint32_t) & BM_AIPS_PACRP_WP0) |
mbed_official | 146:f64d43ff0c18 | 13816 | |
mbed_official | 146:f64d43ff0c18 | 13817 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13818 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13819 | #define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13820 | #endif |
mbed_official | 146:f64d43ff0c18 | 13821 | //@} |
mbed_official | 146:f64d43ff0c18 | 13822 | |
mbed_official | 146:f64d43ff0c18 | 13823 | /*! |
mbed_official | 146:f64d43ff0c18 | 13824 | * @name Register AIPS_PACRP, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 13825 | * |
mbed_official | 146:f64d43ff0c18 | 13826 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13827 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13828 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13829 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13830 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13831 | * |
mbed_official | 146:f64d43ff0c18 | 13832 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13833 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13834 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13835 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13836 | */ |
mbed_official | 146:f64d43ff0c18 | 13837 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13838 | #define BP_AIPS_PACRP_SP0 (30U) //!< Bit position for AIPS_PACRP_SP0. |
mbed_official | 146:f64d43ff0c18 | 13839 | #define BM_AIPS_PACRP_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRP_SP0. |
mbed_official | 146:f64d43ff0c18 | 13840 | #define BS_AIPS_PACRP_SP0 (1U) //!< Bit field size in bits for AIPS_PACRP_SP0. |
mbed_official | 146:f64d43ff0c18 | 13841 | |
mbed_official | 146:f64d43ff0c18 | 13842 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13843 | //! @brief Read current value of the AIPS_PACRP_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 13844 | #define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0)) |
mbed_official | 146:f64d43ff0c18 | 13845 | #endif |
mbed_official | 146:f64d43ff0c18 | 13846 | |
mbed_official | 146:f64d43ff0c18 | 13847 | //! @brief Format value for bitfield AIPS_PACRP_SP0. |
mbed_official | 146:f64d43ff0c18 | 13848 | #define BF_AIPS_PACRP_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP0), uint32_t) & BM_AIPS_PACRP_SP0) |
mbed_official | 146:f64d43ff0c18 | 13849 | |
mbed_official | 146:f64d43ff0c18 | 13850 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13851 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13852 | #define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13853 | #endif |
mbed_official | 146:f64d43ff0c18 | 13854 | //@} |
mbed_official | 146:f64d43ff0c18 | 13855 | |
mbed_official | 146:f64d43ff0c18 | 13856 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 13857 | // HW_AIPS_PACRU - Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 13858 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 13859 | |
mbed_official | 146:f64d43ff0c18 | 13860 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13861 | /*! |
mbed_official | 146:f64d43ff0c18 | 13862 | * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 13863 | * |
mbed_official | 146:f64d43ff0c18 | 13864 | * Reset value: 0x44000000U |
mbed_official | 146:f64d43ff0c18 | 13865 | * |
mbed_official | 146:f64d43ff0c18 | 13866 | * PACRU defines the access levels for the two global spaces. |
mbed_official | 146:f64d43ff0c18 | 13867 | */ |
mbed_official | 146:f64d43ff0c18 | 13868 | typedef union _hw_aips_pacru |
mbed_official | 146:f64d43ff0c18 | 13869 | { |
mbed_official | 146:f64d43ff0c18 | 13870 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 13871 | struct _hw_aips_pacru_bitfields |
mbed_official | 146:f64d43ff0c18 | 13872 | { |
mbed_official | 146:f64d43ff0c18 | 13873 | uint32_t RESERVED0 : 24; //!< [23:0] |
mbed_official | 146:f64d43ff0c18 | 13874 | uint32_t TP1 : 1; //!< [24] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13875 | uint32_t WP1 : 1; //!< [25] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13876 | uint32_t SP1 : 1; //!< [26] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13877 | uint32_t RESERVED1 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 13878 | uint32_t TP0 : 1; //!< [28] Trusted Protect |
mbed_official | 146:f64d43ff0c18 | 13879 | uint32_t WP0 : 1; //!< [29] Write Protect |
mbed_official | 146:f64d43ff0c18 | 13880 | uint32_t SP0 : 1; //!< [30] Supervisor Protect |
mbed_official | 146:f64d43ff0c18 | 13881 | uint32_t RESERVED2 : 1; //!< [31] |
mbed_official | 146:f64d43ff0c18 | 13882 | } B; |
mbed_official | 146:f64d43ff0c18 | 13883 | } hw_aips_pacru_t; |
mbed_official | 146:f64d43ff0c18 | 13884 | #endif |
mbed_official | 146:f64d43ff0c18 | 13885 | |
mbed_official | 146:f64d43ff0c18 | 13886 | /*! |
mbed_official | 146:f64d43ff0c18 | 13887 | * @name Constants and macros for entire AIPS_PACRU register |
mbed_official | 146:f64d43ff0c18 | 13888 | */ |
mbed_official | 146:f64d43ff0c18 | 13889 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13890 | #define HW_AIPS_PACRU_ADDR(x) (REGS_AIPS_BASE(x) + 0x80U) |
mbed_official | 146:f64d43ff0c18 | 13891 | |
mbed_official | 146:f64d43ff0c18 | 13892 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13893 | #define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 13894 | #define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U) |
mbed_official | 146:f64d43ff0c18 | 13895 | #define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 13896 | #define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 13897 | #define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 13898 | #define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 13899 | #endif |
mbed_official | 146:f64d43ff0c18 | 13900 | //@} |
mbed_official | 146:f64d43ff0c18 | 13901 | |
mbed_official | 146:f64d43ff0c18 | 13902 | /* |
mbed_official | 146:f64d43ff0c18 | 13903 | * Constants & macros for individual AIPS_PACRU bitfields |
mbed_official | 146:f64d43ff0c18 | 13904 | */ |
mbed_official | 146:f64d43ff0c18 | 13905 | |
mbed_official | 146:f64d43ff0c18 | 13906 | /*! |
mbed_official | 146:f64d43ff0c18 | 13907 | * @name Register AIPS_PACRU, field TP1[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 13908 | * |
mbed_official | 146:f64d43ff0c18 | 13909 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 13910 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 13911 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13912 | * |
mbed_official | 146:f64d43ff0c18 | 13913 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13914 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 13915 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 13916 | */ |
mbed_official | 146:f64d43ff0c18 | 13917 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13918 | #define BP_AIPS_PACRU_TP1 (24U) //!< Bit position for AIPS_PACRU_TP1. |
mbed_official | 146:f64d43ff0c18 | 13919 | #define BM_AIPS_PACRU_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRU_TP1. |
mbed_official | 146:f64d43ff0c18 | 13920 | #define BS_AIPS_PACRU_TP1 (1U) //!< Bit field size in bits for AIPS_PACRU_TP1. |
mbed_official | 146:f64d43ff0c18 | 13921 | |
mbed_official | 146:f64d43ff0c18 | 13922 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13923 | //! @brief Read current value of the AIPS_PACRU_TP1 field. |
mbed_official | 146:f64d43ff0c18 | 13924 | #define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1)) |
mbed_official | 146:f64d43ff0c18 | 13925 | #endif |
mbed_official | 146:f64d43ff0c18 | 13926 | |
mbed_official | 146:f64d43ff0c18 | 13927 | //! @brief Format value for bitfield AIPS_PACRU_TP1. |
mbed_official | 146:f64d43ff0c18 | 13928 | #define BF_AIPS_PACRU_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP1), uint32_t) & BM_AIPS_PACRU_TP1) |
mbed_official | 146:f64d43ff0c18 | 13929 | |
mbed_official | 146:f64d43ff0c18 | 13930 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13931 | //! @brief Set the TP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13932 | #define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13933 | #endif |
mbed_official | 146:f64d43ff0c18 | 13934 | //@} |
mbed_official | 146:f64d43ff0c18 | 13935 | |
mbed_official | 146:f64d43ff0c18 | 13936 | /*! |
mbed_official | 146:f64d43ff0c18 | 13937 | * @name Register AIPS_PACRU, field WP1[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 13938 | * |
mbed_official | 146:f64d43ff0c18 | 13939 | * Determines whether the peripheral allows write accesss. When this bit is set |
mbed_official | 146:f64d43ff0c18 | 13940 | * and a write access is attempted, access terminates with an error response and |
mbed_official | 146:f64d43ff0c18 | 13941 | * no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 13942 | * |
mbed_official | 146:f64d43ff0c18 | 13943 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13944 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 13945 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 13946 | */ |
mbed_official | 146:f64d43ff0c18 | 13947 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13948 | #define BP_AIPS_PACRU_WP1 (25U) //!< Bit position for AIPS_PACRU_WP1. |
mbed_official | 146:f64d43ff0c18 | 13949 | #define BM_AIPS_PACRU_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRU_WP1. |
mbed_official | 146:f64d43ff0c18 | 13950 | #define BS_AIPS_PACRU_WP1 (1U) //!< Bit field size in bits for AIPS_PACRU_WP1. |
mbed_official | 146:f64d43ff0c18 | 13951 | |
mbed_official | 146:f64d43ff0c18 | 13952 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13953 | //! @brief Read current value of the AIPS_PACRU_WP1 field. |
mbed_official | 146:f64d43ff0c18 | 13954 | #define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1)) |
mbed_official | 146:f64d43ff0c18 | 13955 | #endif |
mbed_official | 146:f64d43ff0c18 | 13956 | |
mbed_official | 146:f64d43ff0c18 | 13957 | //! @brief Format value for bitfield AIPS_PACRU_WP1. |
mbed_official | 146:f64d43ff0c18 | 13958 | #define BF_AIPS_PACRU_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP1), uint32_t) & BM_AIPS_PACRU_WP1) |
mbed_official | 146:f64d43ff0c18 | 13959 | |
mbed_official | 146:f64d43ff0c18 | 13960 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13961 | //! @brief Set the WP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13962 | #define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13963 | #endif |
mbed_official | 146:f64d43ff0c18 | 13964 | //@} |
mbed_official | 146:f64d43ff0c18 | 13965 | |
mbed_official | 146:f64d43ff0c18 | 13966 | /*! |
mbed_official | 146:f64d43ff0c18 | 13967 | * @name Register AIPS_PACRU, field SP1[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 13968 | * |
mbed_official | 146:f64d43ff0c18 | 13969 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13970 | * accesses. When this field is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 13971 | * supervisor access attribute, and the MPRx[MPLn] control field for the master |
mbed_official | 146:f64d43ff0c18 | 13972 | * must be set. If not, access terminates with an error response and no peripheral |
mbed_official | 146:f64d43ff0c18 | 13973 | * access initiates. |
mbed_official | 146:f64d43ff0c18 | 13974 | * |
mbed_official | 146:f64d43ff0c18 | 13975 | * Values: |
mbed_official | 146:f64d43ff0c18 | 13976 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 13977 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 13978 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 13979 | */ |
mbed_official | 146:f64d43ff0c18 | 13980 | //@{ |
mbed_official | 146:f64d43ff0c18 | 13981 | #define BP_AIPS_PACRU_SP1 (26U) //!< Bit position for AIPS_PACRU_SP1. |
mbed_official | 146:f64d43ff0c18 | 13982 | #define BM_AIPS_PACRU_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRU_SP1. |
mbed_official | 146:f64d43ff0c18 | 13983 | #define BS_AIPS_PACRU_SP1 (1U) //!< Bit field size in bits for AIPS_PACRU_SP1. |
mbed_official | 146:f64d43ff0c18 | 13984 | |
mbed_official | 146:f64d43ff0c18 | 13985 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13986 | //! @brief Read current value of the AIPS_PACRU_SP1 field. |
mbed_official | 146:f64d43ff0c18 | 13987 | #define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1)) |
mbed_official | 146:f64d43ff0c18 | 13988 | #endif |
mbed_official | 146:f64d43ff0c18 | 13989 | |
mbed_official | 146:f64d43ff0c18 | 13990 | //! @brief Format value for bitfield AIPS_PACRU_SP1. |
mbed_official | 146:f64d43ff0c18 | 13991 | #define BF_AIPS_PACRU_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP1), uint32_t) & BM_AIPS_PACRU_SP1) |
mbed_official | 146:f64d43ff0c18 | 13992 | |
mbed_official | 146:f64d43ff0c18 | 13993 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 13994 | //! @brief Set the SP1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 13995 | #define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 13996 | #endif |
mbed_official | 146:f64d43ff0c18 | 13997 | //@} |
mbed_official | 146:f64d43ff0c18 | 13998 | |
mbed_official | 146:f64d43ff0c18 | 13999 | /*! |
mbed_official | 146:f64d43ff0c18 | 14000 | * @name Register AIPS_PACRU, field TP0[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 14001 | * |
mbed_official | 146:f64d43ff0c18 | 14002 | * Determines whether the peripheral allows accesses from an untrusted master. |
mbed_official | 146:f64d43ff0c18 | 14003 | * When this field is set and an access is attempted by an untrusted master, the |
mbed_official | 146:f64d43ff0c18 | 14004 | * access terminates with an error response and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 14005 | * |
mbed_official | 146:f64d43ff0c18 | 14006 | * Values: |
mbed_official | 146:f64d43ff0c18 | 14007 | * - 0 - Accesses from an untrusted master are allowed. |
mbed_official | 146:f64d43ff0c18 | 14008 | * - 1 - Accesses from an untrusted master are not allowed. |
mbed_official | 146:f64d43ff0c18 | 14009 | */ |
mbed_official | 146:f64d43ff0c18 | 14010 | //@{ |
mbed_official | 146:f64d43ff0c18 | 14011 | #define BP_AIPS_PACRU_TP0 (28U) //!< Bit position for AIPS_PACRU_TP0. |
mbed_official | 146:f64d43ff0c18 | 14012 | #define BM_AIPS_PACRU_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRU_TP0. |
mbed_official | 146:f64d43ff0c18 | 14013 | #define BS_AIPS_PACRU_TP0 (1U) //!< Bit field size in bits for AIPS_PACRU_TP0. |
mbed_official | 146:f64d43ff0c18 | 14014 | |
mbed_official | 146:f64d43ff0c18 | 14015 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14016 | //! @brief Read current value of the AIPS_PACRU_TP0 field. |
mbed_official | 146:f64d43ff0c18 | 14017 | #define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0)) |
mbed_official | 146:f64d43ff0c18 | 14018 | #endif |
mbed_official | 146:f64d43ff0c18 | 14019 | |
mbed_official | 146:f64d43ff0c18 | 14020 | //! @brief Format value for bitfield AIPS_PACRU_TP0. |
mbed_official | 146:f64d43ff0c18 | 14021 | #define BF_AIPS_PACRU_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP0), uint32_t) & BM_AIPS_PACRU_TP0) |
mbed_official | 146:f64d43ff0c18 | 14022 | |
mbed_official | 146:f64d43ff0c18 | 14023 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14024 | //! @brief Set the TP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 14025 | #define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 14026 | #endif |
mbed_official | 146:f64d43ff0c18 | 14027 | //@} |
mbed_official | 146:f64d43ff0c18 | 14028 | |
mbed_official | 146:f64d43ff0c18 | 14029 | /*! |
mbed_official | 146:f64d43ff0c18 | 14030 | * @name Register AIPS_PACRU, field WP0[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 14031 | * |
mbed_official | 146:f64d43ff0c18 | 14032 | * Determines whether the peripheral allows write accesses. When this field is |
mbed_official | 146:f64d43ff0c18 | 14033 | * set and a write access is attempted, access terminates with an error response |
mbed_official | 146:f64d43ff0c18 | 14034 | * and no peripheral access initiates. |
mbed_official | 146:f64d43ff0c18 | 14035 | * |
mbed_official | 146:f64d43ff0c18 | 14036 | * Values: |
mbed_official | 146:f64d43ff0c18 | 14037 | * - 0 - This peripheral allows write accesses. |
mbed_official | 146:f64d43ff0c18 | 14038 | * - 1 - This peripheral is write protected. |
mbed_official | 146:f64d43ff0c18 | 14039 | */ |
mbed_official | 146:f64d43ff0c18 | 14040 | //@{ |
mbed_official | 146:f64d43ff0c18 | 14041 | #define BP_AIPS_PACRU_WP0 (29U) //!< Bit position for AIPS_PACRU_WP0. |
mbed_official | 146:f64d43ff0c18 | 14042 | #define BM_AIPS_PACRU_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRU_WP0. |
mbed_official | 146:f64d43ff0c18 | 14043 | #define BS_AIPS_PACRU_WP0 (1U) //!< Bit field size in bits for AIPS_PACRU_WP0. |
mbed_official | 146:f64d43ff0c18 | 14044 | |
mbed_official | 146:f64d43ff0c18 | 14045 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14046 | //! @brief Read current value of the AIPS_PACRU_WP0 field. |
mbed_official | 146:f64d43ff0c18 | 14047 | #define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0)) |
mbed_official | 146:f64d43ff0c18 | 14048 | #endif |
mbed_official | 146:f64d43ff0c18 | 14049 | |
mbed_official | 146:f64d43ff0c18 | 14050 | //! @brief Format value for bitfield AIPS_PACRU_WP0. |
mbed_official | 146:f64d43ff0c18 | 14051 | #define BF_AIPS_PACRU_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP0), uint32_t) & BM_AIPS_PACRU_WP0) |
mbed_official | 146:f64d43ff0c18 | 14052 | |
mbed_official | 146:f64d43ff0c18 | 14053 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14054 | //! @brief Set the WP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 14055 | #define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 14056 | #endif |
mbed_official | 146:f64d43ff0c18 | 14057 | //@} |
mbed_official | 146:f64d43ff0c18 | 14058 | |
mbed_official | 146:f64d43ff0c18 | 14059 | /*! |
mbed_official | 146:f64d43ff0c18 | 14060 | * @name Register AIPS_PACRU, field SP0[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 14061 | * |
mbed_official | 146:f64d43ff0c18 | 14062 | * Determines whether the peripheral requires supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 14063 | * access. When this bit is set, the master privilege level must indicate the |
mbed_official | 146:f64d43ff0c18 | 14064 | * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be |
mbed_official | 146:f64d43ff0c18 | 14065 | * set. If not, access terminates with an error response and no peripheral access |
mbed_official | 146:f64d43ff0c18 | 14066 | * initiates. |
mbed_official | 146:f64d43ff0c18 | 14067 | * |
mbed_official | 146:f64d43ff0c18 | 14068 | * Values: |
mbed_official | 146:f64d43ff0c18 | 14069 | * - 0 - This peripheral does not require supervisor privilege level for |
mbed_official | 146:f64d43ff0c18 | 14070 | * accesses. |
mbed_official | 146:f64d43ff0c18 | 14071 | * - 1 - This peripheral requires supervisor privilege level for accesses. |
mbed_official | 146:f64d43ff0c18 | 14072 | */ |
mbed_official | 146:f64d43ff0c18 | 14073 | //@{ |
mbed_official | 146:f64d43ff0c18 | 14074 | #define BP_AIPS_PACRU_SP0 (30U) //!< Bit position for AIPS_PACRU_SP0. |
mbed_official | 146:f64d43ff0c18 | 14075 | #define BM_AIPS_PACRU_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRU_SP0. |
mbed_official | 146:f64d43ff0c18 | 14076 | #define BS_AIPS_PACRU_SP0 (1U) //!< Bit field size in bits for AIPS_PACRU_SP0. |
mbed_official | 146:f64d43ff0c18 | 14077 | |
mbed_official | 146:f64d43ff0c18 | 14078 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14079 | //! @brief Read current value of the AIPS_PACRU_SP0 field. |
mbed_official | 146:f64d43ff0c18 | 14080 | #define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0)) |
mbed_official | 146:f64d43ff0c18 | 14081 | #endif |
mbed_official | 146:f64d43ff0c18 | 14082 | |
mbed_official | 146:f64d43ff0c18 | 14083 | //! @brief Format value for bitfield AIPS_PACRU_SP0. |
mbed_official | 146:f64d43ff0c18 | 14084 | #define BF_AIPS_PACRU_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP0), uint32_t) & BM_AIPS_PACRU_SP0) |
mbed_official | 146:f64d43ff0c18 | 14085 | |
mbed_official | 146:f64d43ff0c18 | 14086 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14087 | //! @brief Set the SP0 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 14088 | #define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v)) |
mbed_official | 146:f64d43ff0c18 | 14089 | #endif |
mbed_official | 146:f64d43ff0c18 | 14090 | //@} |
mbed_official | 146:f64d43ff0c18 | 14091 | |
mbed_official | 146:f64d43ff0c18 | 14092 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 14093 | // hw_aips_t - module struct |
mbed_official | 146:f64d43ff0c18 | 14094 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 14095 | /*! |
mbed_official | 146:f64d43ff0c18 | 14096 | * @brief All AIPS module registers. |
mbed_official | 146:f64d43ff0c18 | 14097 | */ |
mbed_official | 146:f64d43ff0c18 | 14098 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 14099 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 14100 | typedef struct _hw_aips |
mbed_official | 146:f64d43ff0c18 | 14101 | { |
mbed_official | 146:f64d43ff0c18 | 14102 | __IO hw_aips_mpra_t MPRA; //!< [0x0] Master Privilege Register A |
mbed_official | 146:f64d43ff0c18 | 14103 | uint8_t _reserved0[28]; |
mbed_official | 146:f64d43ff0c18 | 14104 | __IO hw_aips_pacra_t PACRA; //!< [0x20] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14105 | __IO hw_aips_pacrb_t PACRB; //!< [0x24] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14106 | __IO hw_aips_pacrc_t PACRC; //!< [0x28] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14107 | __IO hw_aips_pacrd_t PACRD; //!< [0x2C] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14108 | uint8_t _reserved1[16]; |
mbed_official | 146:f64d43ff0c18 | 14109 | __IO hw_aips_pacre_t PACRE; //!< [0x40] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14110 | __IO hw_aips_pacrf_t PACRF; //!< [0x44] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14111 | __IO hw_aips_pacrg_t PACRG; //!< [0x48] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14112 | __IO hw_aips_pacrh_t PACRH; //!< [0x4C] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14113 | __IO hw_aips_pacri_t PACRI; //!< [0x50] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14114 | __IO hw_aips_pacrj_t PACRJ; //!< [0x54] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14115 | __IO hw_aips_pacrk_t PACRK; //!< [0x58] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14116 | __IO hw_aips_pacrl_t PACRL; //!< [0x5C] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14117 | __IO hw_aips_pacrm_t PACRM; //!< [0x60] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14118 | __IO hw_aips_pacrn_t PACRN; //!< [0x64] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14119 | __IO hw_aips_pacro_t PACRO; //!< [0x68] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14120 | __IO hw_aips_pacrp_t PACRP; //!< [0x6C] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14121 | uint8_t _reserved2[16]; |
mbed_official | 146:f64d43ff0c18 | 14122 | __IO hw_aips_pacru_t PACRU; //!< [0x80] Peripheral Access Control Register |
mbed_official | 146:f64d43ff0c18 | 14123 | } hw_aips_t; |
mbed_official | 146:f64d43ff0c18 | 14124 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 14125 | |
mbed_official | 146:f64d43ff0c18 | 14126 | //! @brief Macro to access all AIPS registers. |
mbed_official | 146:f64d43ff0c18 | 14127 | //! @param x AIPS instance number. |
mbed_official | 146:f64d43ff0c18 | 14128 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 14129 | //! use the '&' operator, like <code>&HW_AIPS(0)</code>. |
mbed_official | 146:f64d43ff0c18 | 14130 | #define HW_AIPS(x) (*(hw_aips_t *) REGS_AIPS_BASE(x)) |
mbed_official | 146:f64d43ff0c18 | 14131 | #endif |
mbed_official | 146:f64d43ff0c18 | 14132 | |
mbed_official | 146:f64d43ff0c18 | 14133 | #endif // __HW_AIPS_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 14134 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 14135 | // EOF |