Diff: targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c

Revision:

167:d5744491c362

Parent:

96:c359415e941f

Child:

169:60881100c991

--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c	Tue Apr 22 16:00:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c	Wed Apr 23 11:00:08 2014 +0100
@@ -30,10 +30,9 @@
 #include "PeripheralNames.h"
 
 // Timer selection:
-#define TIM_MST            TIM1
-#define TIM_MST_UP_IRQ     TIM1_UP_IRQn
-#define TIM_MST_OC_IRQ     TIM1_CC_IRQn
-#define TIM_MST_RCC        RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE)
+#define TIM_MST      TIM4
+#define TIM_MST_IRQ  TIM4_IRQn
+#define TIM_MST_RCC  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE)
 
 static int      us_ticker_inited = 0;
 static volatile uint32_t SlaveCounter = 0;
@@ -47,35 +46,30 @@
     TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE);
 }
 
-// Used to increment the slave counter
-static void tim_update_irq_handler(void) {
+static void tim_irq_handler(void) {
+    uint16_t cval = TIM_MST->CNT;
+
     if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) {
         TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update);
         SlaveCounter++;
     }
-}
 
-// Used by interrupt system
-static void tim_oc_irq_handler(void) {
-    uint16_t cval = TIM_MST->CNT;
-  
-    // Clear interrupt flag
     if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
         TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
-    }
-
-    if (oc_rem_part > 0) {
-        set_compare(oc_rem_part); // Finish the remaining time left
-        oc_rem_part = 0;
-    }
-    else {
-        if (oc_int_part > 0) {
-            set_compare(0xFFFF);
-            oc_rem_part = cval; // To finish the counter loop the next time
-            oc_int_part--;
+        if (oc_rem_part > 0) {
+            set_compare(oc_rem_part); // Finish the remaining time left
+            oc_rem_part = 0;
         }
         else {
-            us_ticker_irq_handler();
+            if (oc_int_part > 0) {
+                //set_compare(0);
+                //oc_rem_part = cval; // To finish the counter loop the next time
+                //if (oc_rem_part == 0) GPIOB->ODR ^= (1 << 6); // DEBUG         
+                oc_int_part--;
+            }
+            else {
+                us_ticker_irq_handler();
+            }
         }
     }
 }
@@ -101,12 +95,9 @@
     TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE);
     
     // Update interrupt used for 32-bit counter
-    NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_UP_IRQ);
-    
     // Output compare interrupt used for timeout feature
-    NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_OC_IRQ);
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)tim_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
   
     // Enable timer
     TIM_Cmd(TIM_MST, ENABLE);
@@ -158,7 +149,5 @@
 }
 
 void us_ticker_clear_interrupt(void) {
-    if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
-        TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
-    }
+    TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
 }