mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
Diff: targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c
- Revision:
- 214:b6ec89a903fb
- Parent:
- 103:9b881da47c92
- Child:
- 217:d0ccc61c1fd4
--- a/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c Mon May 26 18:30:07 2014 +0100 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c Tue May 27 08:15:07 2014 +0100 @@ -59,25 +59,25 @@ error("ADC pin mapping failed"); } uint32_t port = (pin >> 5); - // enable clock for GPIOx + // enable clock for GPIOx LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port)); - // pin enable - LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc); + // pin enable + LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc); // configure GPIO as input LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F)); - + // power up ADC if (obj->adc < ADC1_0) { // ADC0 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27); - } - else { - // ADC1 + } + else { + // ADC1 LPC_SYSCON->PDRUNCFG &= ~(1 << 11); LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28); - } + } // select IRC as async. clock, divided by 1 LPC_SYSCON->ADCASYNCCLKSEL = 0; @@ -95,12 +95,18 @@ } static inline uint32_t adc_read(analogin_t *obj) { + volatile uint32_t channels; __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1); + if (obj->adc >= ADC1_0) + channels = ((obj->adc - ADC1_0) & 0x1F); + else + channels = (obj->adc & 0x1F); + // select channel adc_reg->SEQA_CTRL &= ~(0xFFF); - adc_reg->SEQA_CTRL |= (1UL << (obj->adc & 0x1F)); + adc_reg->SEQA_CTRL |= (1UL << channels); // start conversion and sequence enable adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));