Diff: targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.c

Revision:

181:a4cbdfbbd2f4

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.c	Wed May 07 13:15:08 2014 +0100
@@ -0,0 +1,535 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    22-April-2014
+  * @brief   Extended RCC HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *  
+  @verbatim                
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    For CRS, RCC Extension HAL driver can be used as follows:
+
+      (#) In System clock configuration, HSI48 need to be enabled
+
+      (#] Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions like this
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate 
+                        directly reload value with target and synchronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Reset CRS registers to their default values.
+              (+++) Configure CRS registers with synchronization configuration 
+              (+++) Enable automatic calibration and frequency error counter feature
+
+          (##) A polling function is provided to wait for complete Synchronization
+              (+++) Call function 'HAL_RCCEx_CRSWaitSynchronization()'
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+              
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), 
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be 
+           incremented), while when it is detected during the upcounting phase it means that the actual frequency 
+           is higher (and that the TRIM value should be decremented).
+
+      (#) To use IT mode, user needs to handle it in calling different macros available to do it
+            (__HAL_RCC_CRS_XXX_IT). Interruptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler)
+              (+++) Call function HAL_RCCEx_CRSConfig()
+              (+++) Enable RCC_IRQn (thnaks to NVIC functions)
+              (+++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT)
+              [+++) Implement CRS status management in RCC_CRS_IRQHandler
+
+      (#) To force a SYNC EVENT, user can use function 'HAL_RCCEx_CRSSoftwareSynchronizationGenerate()'. Function can be 
+            called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+       
+   @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx 
+  * @brief RCC Extension HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Bit position in register */
+#define CRS_CFGR_FELIM_BITNUMBER    16
+#define CRS_CR_TRIM_BITNUMBER       8
+#define CRS_ISR_FECAP_BITNUMBER     16
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCCEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Group1 Extended Peripheral Control functions 
+ *  @brief  Extended Peripheral Control functions  
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Extended Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks 
+    frequencies.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+  *         RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, 
+  *         I2C1, RTC, USB/RNG  and LPTIM1 clocks).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0;   
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
+
+  /*------------------------------- USART1 Configuration ------------------------*/ 
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+    
+    /* Configure the USART1 clock source */
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+  
+  /*----------------------------- USART2 Configuration --------------------------*/ 
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+    
+    /* Configure the USART2 clock source */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+  }
+  
+  /*------------------------------ LPUART1 Configuration ------------------------*/ 
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+    
+    /* Configure the LPUAR1 clock source */
+    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+  }
+
+  /*------------------------------ I2C1 Configuration ------------------------*/ 
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+    
+    /* Configure the I2C1 clock source */
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+  }
+    
+  
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+        /* Enable Power Clock*/
+    __PWR_CLK_ENABLE();
+    
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+    
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+    
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }      
+    }
+    
+    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
+    if((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
+    {
+      /* Store the content of CSR register before the reset of Backup Domain */
+      tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of CSR register */
+      RCC->CSR = tmpreg;
+    }
+    
+    /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+    if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+    {
+      /* Get timeout */   
+      tickstart = HAL_GetTick();
+      
+      /* Wait till LSE is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }      
+      }  
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+#if !defined(STM32L051xx) && !defined(STM32L061xx)  
+ /*---------------------------- USB and RNG configuration --------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
+  {
+    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
+    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+  }
+#endif /* !(STM32L051xx) && !(STM32L061xx) */
+  
+  /*---------------------------- LPTIM1 configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
+  {
+    assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, 
+  *         I2C1, RTC, USB/RNG  and LPTIM1 clocks).
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+   /* Set all possible values for the extended clock type parameter -----------*/
+  /* Common part first */
+  #if !defined(STM32L051xx) && !defined(STM32L061xx)  
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_RTC     | \
+                                        RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_LPTIM1;
+  
+ #else 
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                        RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_RTC     | \
+                                        RCC_PERIPHCLK_LPTIM1;
+  #endif /* !(STM32L051xx) && !(STM32L061xx) */
+  
+  /* Get the USART1 configuration --------------------------------------------*/
+  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
+  /* Get the USART2 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
+   /* Get the LPUART1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+  /* Get the I2C1 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
+  /* Get the LPTIM1 clock source -----------------------------------------------*/
+  PeriphClkInit->LptimClockSelection   = __HAL_RCC_GET_LPTIM1_SOURCE();
+  /* Get the RTC clock source -----------------------------------------------*/
+  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
+
+#if !defined(STM32L051xx) && !defined(STM32L061xx)  
+  /* Get the USB/RNG clock source -----------------------------------------------*/
+  PeriphClkInit->UsbClockSelection  = __HAL_RCC_GET_USB_SOURCE();
+#endif /* !(STM32L051xx) && !(STM32L061xx) */
+}
+
+/**
+  * @brief  Enables the LSE Clock Security System.
+  * @param  None
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+   SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disables the LSE Clock Security System.
+  * @param  None
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+   CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
+}
+
+#if !defined(STM32L051xx) && !defined(STM32L061xx)
+    
+/**
+  * @brief  Start automatic synchronization using polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __CRS_FORCE_RESET();
+  __CRS_RELEASE_RESET();
+
+  /* Configure Synchronization input */
+  /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
+  CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL);
+
+  /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */
+  CRS->CFGR |= pInit->Prescaler;
+
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  CRS->CFGR |= pInit->Source;
+
+  /* Set the SYNCSPOL bits according to Polarity value */
+  CRS->CFGR |= pInit->Polarity;
+
+  /* Configure Frequency Error Measurement */
+  /* Clear RELOAD[15:0] & FELIM[7:0] bits*/
+  CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM);
+
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  CRS->CFGR |= pInit->ReloadValue;
+
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Clear TRIM[5:0] bits */
+  CRS->CR &= ~CRS_CR_TRIM;
+
+  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER);
+
+
+  /* START AUTOMATIC SYNCHRONIZATION*/
+  
+  /* Enable Automatic trimming */
+  __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
+
+  /* Enable Frequency error counter */
+  __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
+
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @param  None
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  CRS->CR |= CRS_CR_SWSYNC;
+}
+
+
+/**
+  * @brief  Function to return synchronization info 
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != NULL);
+  
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
+  
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR);
+  
+  
+}
+
+/**
+* @brief This function handles CRS Synchronization Timeout.
+* @param Timeout: Duration of the timeout
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg RCC_CRS_TIMEOUT
+*            @arg RCC_CRS_SYNCOK
+*            @arg RCC_CRS_SYNCWARM
+*            @arg RCC_CRS_SYNCERR
+*            @arg RCC_CRS_SYNCMISS
+*            @arg RCC_CRS_TRIMOV
+*/
+RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  RCC_CRSStatusTypeDef crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart = 0;
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+  
+  /* Check that if one of CRS flags have been set */
+  while(RCC_CRS_NONE == crsstatus)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((HAL_GetTick() - tickstart ) > Timeout)
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+    
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+    
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARM;
+    
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+    
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOV;
+    
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+    
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+    
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+    
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+    
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+    
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  }
+  
+  return crsstatus;
+}
+          
+#endif /* !(STM32L051xx) && !(STM32L061xx) */  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/