Diff: targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c

Revision:

227:7bd0639b8911

Parent:

113:65a335a675de

--- a/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c	Wed Jun 11 09:45:09 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c	Wed Jun 11 16:00:09 2014 +0100
@@ -13,6 +13,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+#include "mbed_assert.h"
 #include "gpio_api.h"
 #include "pinmap.h"
 #include "reserved_pins.h"
@@ -20,24 +21,26 @@
 static const PinName reserved_pins[] = TARGET_RESERVED_PINS;
 
 uint32_t gpio_set(PinName pin) {
+    MBED_ASSERT(pin != (PinName)NC);
     // PIO default value of following ports are not same as others
     unsigned i;
     int f = 0;
 
-    for (i = 0; i < sizeof(reserved_pins) / sizeof(PinName); i ++)
+    for (i = 0; i < sizeof(reserved_pins) / sizeof(PinName); i ++) {
         if (pin == reserved_pins[i]) {
             f = 1;
             break;
         }
-   
+    }
     pin_function(pin, f);
     return ((pin & 0x0F00) >> 8);
 }
 
 void gpio_init(gpio_t *obj, PinName pin) {
-    if(pin == NC) return;
+    obj->pin = pin;
+    if (pin == (PinName)NC)
+        return;
 
-    obj->pin = pin;
     LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
 
     obj->reg_mask_read = &port_reg->MASKED_ACCESS[1 << gpio_set(pin)];
@@ -50,9 +53,14 @@
 }
 
 void gpio_dir(gpio_t *obj, PinDirection direction) {
+    MBED_ASSERT(obj->pin != (PinName)NC);
     int pin_number = ((obj->pin & 0x0F00) >> 8);
     switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~(1 << pin_number); break;
-        case PIN_OUTPUT: *obj->reg_dir |=  (1 << pin_number); break;
+        case PIN_INPUT :
+            *obj->reg_dir &= ~(1 << pin_number);
+            break;
+        case PIN_OUTPUT:
+            *obj->reg_dir |= (1 << pin_number);
+            break;
     }
 }