Diff: targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c

Revision:

208:4557f4bb2dd5

Parent:

174:8bb9f3a33240

Child:

215:83cf97a28428

--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c	Fri May 23 08:45:06 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c	Fri May 23 10:30:07 2014 +0100
@@ -113,6 +113,9 @@
     obj->stopbits = USART_StopBits_1;
     obj->parity = USART_Parity_No;
 
+    obj->pin_tx = tx;
+    obj->pin_rx = rx;
+
     init_usart(obj);
 
     // The index is used by irq
@@ -128,6 +131,27 @@
 }
 
 void serial_free(serial_t *obj) {
+    // Reset UART and disable clock
+    if (obj->uart == UART_1) {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, DISABLE);
+    }
+    if (obj->uart == UART_2) {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, DISABLE);
+    }
+    if (obj->uart == UART_3) {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, DISABLE);
+    }
+
+    // Configure GPIOs
+    pin_function(obj->pin_tx, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0));
+    pin_function(obj->pin_rx, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0));
+
     serial_irq_ids[obj->index] = 0;
 }