mbed library sources
Dependents: frdm_kl05z_gpio_test
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targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/regs.h@146:f64d43ff0c18, 2014-04-02 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Apr 02 21:00:08 2014 +0100
- Revision:
- 146:f64d43ff0c18
Synchronized with git revision d537c51d26da35e031d537f7fc90380fc74cb207
Full URL: https://github.com/mbedmicro/mbed/commit/d537c51d26da35e031d537f7fc90380fc74cb207/
target K64F
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | |
mbed_official | 146:f64d43ff0c18 | 17 | #ifndef _REGS_H |
mbed_official | 146:f64d43ff0c18 | 18 | #define _REGS_H 1 |
mbed_official | 146:f64d43ff0c18 | 19 | |
mbed_official | 146:f64d43ff0c18 | 20 | #include <stdint.h> |
mbed_official | 146:f64d43ff0c18 | 21 | #include <stdlib.h> |
mbed_official | 146:f64d43ff0c18 | 22 | |
mbed_official | 146:f64d43ff0c18 | 23 | // |
mbed_official | 146:f64d43ff0c18 | 24 | // define base address of the register block only if it is not already |
mbed_official | 146:f64d43ff0c18 | 25 | // defined, which allows the compiler to override at build time for |
mbed_official | 146:f64d43ff0c18 | 26 | // users who've mapped their registers to locations other than the |
mbed_official | 146:f64d43ff0c18 | 27 | // physical location |
mbed_official | 146:f64d43ff0c18 | 28 | // |
mbed_official | 146:f64d43ff0c18 | 29 | |
mbed_official | 146:f64d43ff0c18 | 30 | #include <stdint.h> |
mbed_official | 146:f64d43ff0c18 | 31 | |
mbed_official | 146:f64d43ff0c18 | 32 | #ifndef REGS_BASE |
mbed_official | 146:f64d43ff0c18 | 33 | #define REGS_BASE 0x00000000 |
mbed_official | 146:f64d43ff0c18 | 34 | #endif |
mbed_official | 146:f64d43ff0c18 | 35 | |
mbed_official | 146:f64d43ff0c18 | 36 | // |
mbed_official | 146:f64d43ff0c18 | 37 | // common register types |
mbed_official | 146:f64d43ff0c18 | 38 | // |
mbed_official | 146:f64d43ff0c18 | 39 | |
mbed_official | 146:f64d43ff0c18 | 40 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 41 | typedef unsigned char reg8_t; |
mbed_official | 146:f64d43ff0c18 | 42 | typedef unsigned short reg16_t; |
mbed_official | 146:f64d43ff0c18 | 43 | typedef unsigned int reg32_t; |
mbed_official | 146:f64d43ff0c18 | 44 | #endif |
mbed_official | 146:f64d43ff0c18 | 45 | |
mbed_official | 146:f64d43ff0c18 | 46 | #ifdef __cplusplus |
mbed_official | 146:f64d43ff0c18 | 47 | #define __I volatile /*!< Defines 'read only' permissions */ |
mbed_official | 146:f64d43ff0c18 | 48 | #else |
mbed_official | 146:f64d43ff0c18 | 49 | #define __I volatile const /*!< Defines 'read only' permissions */ |
mbed_official | 146:f64d43ff0c18 | 50 | #endif |
mbed_official | 146:f64d43ff0c18 | 51 | #define __O volatile /*!< Defines 'write only' permissions */ |
mbed_official | 146:f64d43ff0c18 | 52 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
mbed_official | 146:f64d43ff0c18 | 53 | |
mbed_official | 146:f64d43ff0c18 | 54 | #define BME_AND_MASK (1<<26) |
mbed_official | 146:f64d43ff0c18 | 55 | #define BME_OR_MASK (1<<27) |
mbed_official | 146:f64d43ff0c18 | 56 | #define BME_XOR_MASK (3<<26) |
mbed_official | 146:f64d43ff0c18 | 57 | #define BME_BFI_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) |
mbed_official | 146:f64d43ff0c18 | 58 | #define BME_UBFX_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) |
mbed_official | 146:f64d43ff0c18 | 59 | |
mbed_official | 146:f64d43ff0c18 | 60 | /** |
mbed_official | 146:f64d43ff0c18 | 61 | * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region |
mbed_official | 146:f64d43ff0c18 | 62 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. |
mbed_official | 146:f64d43ff0c18 | 63 | * @param Reg Register to access. |
mbed_official | 146:f64d43ff0c18 | 64 | * @param Bit Bit number to access. |
mbed_official | 146:f64d43ff0c18 | 65 | * @return Value of the targeted bit in the bit band region. |
mbed_official | 146:f64d43ff0c18 | 66 | */ |
mbed_official | 146:f64d43ff0c18 | 67 | #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) |
mbed_official | 146:f64d43ff0c18 | 68 | |
mbed_official | 146:f64d43ff0c18 | 69 | /** |
mbed_official | 146:f64d43ff0c18 | 70 | * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region |
mbed_official | 146:f64d43ff0c18 | 71 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. |
mbed_official | 146:f64d43ff0c18 | 72 | * @param Reg Register to access. |
mbed_official | 146:f64d43ff0c18 | 73 | * @param Bit Bit number to access. |
mbed_official | 146:f64d43ff0c18 | 74 | * @return Value of the targeted bit in the bit band region. |
mbed_official | 146:f64d43ff0c18 | 75 | */ |
mbed_official | 146:f64d43ff0c18 | 76 | #define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) |
mbed_official | 146:f64d43ff0c18 | 77 | |
mbed_official | 146:f64d43ff0c18 | 78 | /** |
mbed_official | 146:f64d43ff0c18 | 79 | * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region |
mbed_official | 146:f64d43ff0c18 | 80 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. |
mbed_official | 146:f64d43ff0c18 | 81 | * @param Reg Register to access. |
mbed_official | 146:f64d43ff0c18 | 82 | * @param Bit Bit number to access. |
mbed_official | 146:f64d43ff0c18 | 83 | * @return Value of the targeted bit in the bit band region. |
mbed_official | 146:f64d43ff0c18 | 84 | */ |
mbed_official | 146:f64d43ff0c18 | 85 | #define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) |
mbed_official | 146:f64d43ff0c18 | 86 | |
mbed_official | 146:f64d43ff0c18 | 87 | // |
mbed_official | 146:f64d43ff0c18 | 88 | // Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is |
mbed_official | 146:f64d43ff0c18 | 89 | // used to simplify macro definitions in the module register headers. |
mbed_official | 146:f64d43ff0c18 | 90 | // |
mbed_official | 146:f64d43ff0c18 | 91 | #ifndef __REG_VALUE_TYPE |
mbed_official | 146:f64d43ff0c18 | 92 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 93 | #define __REG_VALUE_TYPE(v, t) ((t)(v)) |
mbed_official | 146:f64d43ff0c18 | 94 | #else |
mbed_official | 146:f64d43ff0c18 | 95 | #define __REG_VALUE_TYPE(v, t) (v) |
mbed_official | 146:f64d43ff0c18 | 96 | #endif |
mbed_official | 146:f64d43ff0c18 | 97 | #endif |
mbed_official | 146:f64d43ff0c18 | 98 | |
mbed_official | 146:f64d43ff0c18 | 99 | // |
mbed_official | 146:f64d43ff0c18 | 100 | // macros for single instance registers |
mbed_official | 146:f64d43ff0c18 | 101 | // |
mbed_official | 146:f64d43ff0c18 | 102 | |
mbed_official | 146:f64d43ff0c18 | 103 | #define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 104 | #define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 105 | #define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 106 | |
mbed_official | 146:f64d43ff0c18 | 107 | #define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 108 | #define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 109 | #define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 110 | |
mbed_official | 146:f64d43ff0c18 | 111 | #define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) |
mbed_official | 146:f64d43ff0c18 | 112 | #define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym |
mbed_official | 146:f64d43ff0c18 | 113 | |
mbed_official | 146:f64d43ff0c18 | 114 | #define BF_RD(reg, field) HW_##reg.B.field |
mbed_official | 146:f64d43ff0c18 | 115 | #define BF_WR(reg, field, v) BW_##reg##_##field(v) |
mbed_official | 146:f64d43ff0c18 | 116 | |
mbed_official | 146:f64d43ff0c18 | 117 | #define BF_CS1(reg, f1, v1) \ |
mbed_official | 146:f64d43ff0c18 | 118 | (HW_##reg##_CLR(BM_##reg##_##f1), \ |
mbed_official | 146:f64d43ff0c18 | 119 | HW_##reg##_SET(BF_##reg##_##f1(v1))) |
mbed_official | 146:f64d43ff0c18 | 120 | |
mbed_official | 146:f64d43ff0c18 | 121 | #define BF_CS2(reg, f1, v1, f2, v2) \ |
mbed_official | 146:f64d43ff0c18 | 122 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 123 | BM_##reg##_##f2), \ |
mbed_official | 146:f64d43ff0c18 | 124 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 125 | BF_##reg##_##f2(v2))) |
mbed_official | 146:f64d43ff0c18 | 126 | |
mbed_official | 146:f64d43ff0c18 | 127 | #define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ |
mbed_official | 146:f64d43ff0c18 | 128 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 129 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 130 | BM_##reg##_##f3), \ |
mbed_official | 146:f64d43ff0c18 | 131 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 132 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 133 | BF_##reg##_##f3(v3))) |
mbed_official | 146:f64d43ff0c18 | 134 | |
mbed_official | 146:f64d43ff0c18 | 135 | #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ |
mbed_official | 146:f64d43ff0c18 | 136 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 137 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 138 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 139 | BM_##reg##_##f4), \ |
mbed_official | 146:f64d43ff0c18 | 140 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 141 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 142 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 143 | BF_##reg##_##f4(v4))) |
mbed_official | 146:f64d43ff0c18 | 144 | |
mbed_official | 146:f64d43ff0c18 | 145 | #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ |
mbed_official | 146:f64d43ff0c18 | 146 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 147 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 148 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 149 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 150 | BM_##reg##_##f5), \ |
mbed_official | 146:f64d43ff0c18 | 151 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 152 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 153 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 154 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 155 | BF_##reg##_##f5(v5))) |
mbed_official | 146:f64d43ff0c18 | 156 | |
mbed_official | 146:f64d43ff0c18 | 157 | #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ |
mbed_official | 146:f64d43ff0c18 | 158 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 159 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 160 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 161 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 162 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 163 | BM_##reg##_##f6), \ |
mbed_official | 146:f64d43ff0c18 | 164 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 165 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 166 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 167 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 168 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 169 | BF_##reg##_##f6(v6))) |
mbed_official | 146:f64d43ff0c18 | 170 | |
mbed_official | 146:f64d43ff0c18 | 171 | #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ |
mbed_official | 146:f64d43ff0c18 | 172 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 173 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 174 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 175 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 176 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 177 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 178 | BM_##reg##_##f7), \ |
mbed_official | 146:f64d43ff0c18 | 179 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 180 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 181 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 182 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 183 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 184 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 185 | BF_##reg##_##f7(v7))) |
mbed_official | 146:f64d43ff0c18 | 186 | |
mbed_official | 146:f64d43ff0c18 | 187 | #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ |
mbed_official | 146:f64d43ff0c18 | 188 | (HW_##reg##_CLR(BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 189 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 190 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 191 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 192 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 193 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 194 | BM_##reg##_##f7 | \ |
mbed_official | 146:f64d43ff0c18 | 195 | BM_##reg##_##f8), \ |
mbed_official | 146:f64d43ff0c18 | 196 | HW_##reg##_SET(BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 197 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 198 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 199 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 200 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 201 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 202 | BF_##reg##_##f7(v7) | \ |
mbed_official | 146:f64d43ff0c18 | 203 | BF_##reg##_##f8(v8))) |
mbed_official | 146:f64d43ff0c18 | 204 | |
mbed_official | 146:f64d43ff0c18 | 205 | // |
mbed_official | 146:f64d43ff0c18 | 206 | // macros for multiple instance registers |
mbed_official | 146:f64d43ff0c18 | 207 | // |
mbed_official | 146:f64d43ff0c18 | 208 | |
mbed_official | 146:f64d43ff0c18 | 209 | #define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 210 | #define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 211 | #define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 212 | |
mbed_official | 146:f64d43ff0c18 | 213 | #define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 214 | #define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 215 | #define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 216 | |
mbed_official | 146:f64d43ff0c18 | 217 | #define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) |
mbed_official | 146:f64d43ff0c18 | 218 | #define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym |
mbed_official | 146:f64d43ff0c18 | 219 | |
mbed_official | 146:f64d43ff0c18 | 220 | #define BF_RDn(reg, n, field) HW_##reg(n).B.field |
mbed_official | 146:f64d43ff0c18 | 221 | #define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) |
mbed_official | 146:f64d43ff0c18 | 222 | |
mbed_official | 146:f64d43ff0c18 | 223 | #define BF_CS1n(reg, n, f1, v1) \ |
mbed_official | 146:f64d43ff0c18 | 224 | (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ |
mbed_official | 146:f64d43ff0c18 | 225 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) |
mbed_official | 146:f64d43ff0c18 | 226 | |
mbed_official | 146:f64d43ff0c18 | 227 | #define BF_CS2n(reg, n, f1, v1, f2, v2) \ |
mbed_official | 146:f64d43ff0c18 | 228 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 229 | BM_##reg##_##f2)), \ |
mbed_official | 146:f64d43ff0c18 | 230 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 231 | BF_##reg##_##f2(v2)))) |
mbed_official | 146:f64d43ff0c18 | 232 | |
mbed_official | 146:f64d43ff0c18 | 233 | #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ |
mbed_official | 146:f64d43ff0c18 | 234 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 235 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 236 | BM_##reg##_##f3)), \ |
mbed_official | 146:f64d43ff0c18 | 237 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 238 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 239 | BF_##reg##_##f3(v3)))) |
mbed_official | 146:f64d43ff0c18 | 240 | |
mbed_official | 146:f64d43ff0c18 | 241 | #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ |
mbed_official | 146:f64d43ff0c18 | 242 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 243 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 244 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 245 | BM_##reg##_##f4)), \ |
mbed_official | 146:f64d43ff0c18 | 246 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 247 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 248 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 249 | BF_##reg##_##f4(v4)))) |
mbed_official | 146:f64d43ff0c18 | 250 | |
mbed_official | 146:f64d43ff0c18 | 251 | #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ |
mbed_official | 146:f64d43ff0c18 | 252 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 253 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 254 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 255 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 256 | BM_##reg##_##f5)), \ |
mbed_official | 146:f64d43ff0c18 | 257 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 258 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 259 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 260 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 261 | BF_##reg##_##f5(v5)))) |
mbed_official | 146:f64d43ff0c18 | 262 | |
mbed_official | 146:f64d43ff0c18 | 263 | #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ |
mbed_official | 146:f64d43ff0c18 | 264 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 265 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 266 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 267 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 268 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 269 | BM_##reg##_##f6)), \ |
mbed_official | 146:f64d43ff0c18 | 270 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 271 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 272 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 273 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 274 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 275 | BF_##reg##_##f6(v6)))) |
mbed_official | 146:f64d43ff0c18 | 276 | |
mbed_official | 146:f64d43ff0c18 | 277 | #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ |
mbed_official | 146:f64d43ff0c18 | 278 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 279 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 280 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 281 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 282 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 283 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 284 | BM_##reg##_##f7)), \ |
mbed_official | 146:f64d43ff0c18 | 285 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 286 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 287 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 288 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 289 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 290 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 291 | BF_##reg##_##f7(v7)))) |
mbed_official | 146:f64d43ff0c18 | 292 | |
mbed_official | 146:f64d43ff0c18 | 293 | #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ |
mbed_official | 146:f64d43ff0c18 | 294 | (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 295 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 296 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 297 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 298 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 299 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 300 | BM_##reg##_##f7 | \ |
mbed_official | 146:f64d43ff0c18 | 301 | BM_##reg##_##f8)), \ |
mbed_official | 146:f64d43ff0c18 | 302 | HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 303 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 304 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 305 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 306 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 307 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 308 | BF_##reg##_##f7(v7) | \ |
mbed_official | 146:f64d43ff0c18 | 309 | BF_##reg##_##f8(v8)))) |
mbed_official | 146:f64d43ff0c18 | 310 | |
mbed_official | 146:f64d43ff0c18 | 311 | // |
mbed_official | 146:f64d43ff0c18 | 312 | // macros for single instance MULTI-BLOCK registers |
mbed_official | 146:f64d43ff0c18 | 313 | // |
mbed_official | 146:f64d43ff0c18 | 314 | |
mbed_official | 146:f64d43ff0c18 | 315 | #define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 316 | #define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 317 | #define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 318 | |
mbed_official | 146:f64d43ff0c18 | 319 | #define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 320 | #define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 321 | #define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 322 | |
mbed_official | 146:f64d43ff0c18 | 323 | #define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) |
mbed_official | 146:f64d43ff0c18 | 324 | #define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym |
mbed_official | 146:f64d43ff0c18 | 325 | |
mbed_official | 146:f64d43ff0c18 | 326 | #define BFn_RD(reg, blk, field) HW_##reg(blk).B.field |
mbed_official | 146:f64d43ff0c18 | 327 | #define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) |
mbed_official | 146:f64d43ff0c18 | 328 | |
mbed_official | 146:f64d43ff0c18 | 329 | #define BFn_CS1(reg, blk, f1, v1) \ |
mbed_official | 146:f64d43ff0c18 | 330 | (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ |
mbed_official | 146:f64d43ff0c18 | 331 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) |
mbed_official | 146:f64d43ff0c18 | 332 | |
mbed_official | 146:f64d43ff0c18 | 333 | #define BFn_CS2(reg, blk, f1, v1, f2, v2) \ |
mbed_official | 146:f64d43ff0c18 | 334 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 335 | BM_##reg##_##f2), \ |
mbed_official | 146:f64d43ff0c18 | 336 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 337 | BF_##reg##_##f2(v2))) |
mbed_official | 146:f64d43ff0c18 | 338 | |
mbed_official | 146:f64d43ff0c18 | 339 | #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ |
mbed_official | 146:f64d43ff0c18 | 340 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 341 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 342 | BM_##reg##_##f3), \ |
mbed_official | 146:f64d43ff0c18 | 343 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 344 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 345 | BF_##reg##_##f3(v3))) |
mbed_official | 146:f64d43ff0c18 | 346 | |
mbed_official | 146:f64d43ff0c18 | 347 | #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ |
mbed_official | 146:f64d43ff0c18 | 348 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 349 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 350 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 351 | BM_##reg##_##f4), \ |
mbed_official | 146:f64d43ff0c18 | 352 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 353 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 354 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 355 | BF_##reg##_##f4(v4))) |
mbed_official | 146:f64d43ff0c18 | 356 | |
mbed_official | 146:f64d43ff0c18 | 357 | #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ |
mbed_official | 146:f64d43ff0c18 | 358 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 359 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 360 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 361 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 362 | BM_##reg##_##f5), \ |
mbed_official | 146:f64d43ff0c18 | 363 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 364 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 365 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 366 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 367 | BF_##reg##_##f5(v5))) |
mbed_official | 146:f64d43ff0c18 | 368 | |
mbed_official | 146:f64d43ff0c18 | 369 | #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ |
mbed_official | 146:f64d43ff0c18 | 370 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 371 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 372 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 373 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 374 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 375 | BM_##reg##_##f6), \ |
mbed_official | 146:f64d43ff0c18 | 376 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 377 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 378 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 379 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 380 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 381 | BF_##reg##_##f6(v6))) |
mbed_official | 146:f64d43ff0c18 | 382 | |
mbed_official | 146:f64d43ff0c18 | 383 | #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ |
mbed_official | 146:f64d43ff0c18 | 384 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 385 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 386 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 387 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 388 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 389 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 390 | BM_##reg##_##f7), \ |
mbed_official | 146:f64d43ff0c18 | 391 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 392 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 393 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 394 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 395 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 396 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 397 | BF_##reg##_##f7(v7))) |
mbed_official | 146:f64d43ff0c18 | 398 | |
mbed_official | 146:f64d43ff0c18 | 399 | #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ |
mbed_official | 146:f64d43ff0c18 | 400 | (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 401 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 402 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 403 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 404 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 405 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 406 | BM_##reg##_##f7 | \ |
mbed_official | 146:f64d43ff0c18 | 407 | BM_##reg##_##f8), \ |
mbed_official | 146:f64d43ff0c18 | 408 | HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 409 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 410 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 411 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 412 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 413 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 414 | BF_##reg##_##f7(v7) | \ |
mbed_official | 146:f64d43ff0c18 | 415 | BF_##reg##_##f8(v8))) |
mbed_official | 146:f64d43ff0c18 | 416 | |
mbed_official | 146:f64d43ff0c18 | 417 | // |
mbed_official | 146:f64d43ff0c18 | 418 | // macros for MULTI-BLOCK multiple instance registers |
mbed_official | 146:f64d43ff0c18 | 419 | // |
mbed_official | 146:f64d43ff0c18 | 420 | |
mbed_official | 146:f64d43ff0c18 | 421 | #define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 422 | #define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 423 | #define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) |
mbed_official | 146:f64d43ff0c18 | 424 | |
mbed_official | 146:f64d43ff0c18 | 425 | #define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 426 | #define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 427 | #define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) |
mbed_official | 146:f64d43ff0c18 | 428 | |
mbed_official | 146:f64d43ff0c18 | 429 | #define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) |
mbed_official | 146:f64d43ff0c18 | 430 | #define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym |
mbed_official | 146:f64d43ff0c18 | 431 | |
mbed_official | 146:f64d43ff0c18 | 432 | #define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field |
mbed_official | 146:f64d43ff0c18 | 433 | #define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) |
mbed_official | 146:f64d43ff0c18 | 434 | |
mbed_official | 146:f64d43ff0c18 | 435 | #define BFn_CS1n(reg, blk, n, f1, v1) \ |
mbed_official | 146:f64d43ff0c18 | 436 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ |
mbed_official | 146:f64d43ff0c18 | 437 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) |
mbed_official | 146:f64d43ff0c18 | 438 | |
mbed_official | 146:f64d43ff0c18 | 439 | #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ |
mbed_official | 146:f64d43ff0c18 | 440 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 441 | BM_##reg##_##f2)), \ |
mbed_official | 146:f64d43ff0c18 | 442 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 443 | BF_##reg##_##f2(v2)))) |
mbed_official | 146:f64d43ff0c18 | 444 | |
mbed_official | 146:f64d43ff0c18 | 445 | #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ |
mbed_official | 146:f64d43ff0c18 | 446 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 447 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 448 | BM_##reg##_##f3)), \ |
mbed_official | 146:f64d43ff0c18 | 449 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 450 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 451 | BF_##reg##_##f3(v3)))) |
mbed_official | 146:f64d43ff0c18 | 452 | |
mbed_official | 146:f64d43ff0c18 | 453 | #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ |
mbed_official | 146:f64d43ff0c18 | 454 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 455 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 456 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 457 | BM_##reg##_##f4)), \ |
mbed_official | 146:f64d43ff0c18 | 458 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 459 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 460 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 461 | BF_##reg##_##f4(v4)))) |
mbed_official | 146:f64d43ff0c18 | 462 | |
mbed_official | 146:f64d43ff0c18 | 463 | #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ |
mbed_official | 146:f64d43ff0c18 | 464 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 465 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 466 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 467 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 468 | BM_##reg##_##f5)), \ |
mbed_official | 146:f64d43ff0c18 | 469 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 470 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 471 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 472 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 473 | BF_##reg##_##f5(v5)))) |
mbed_official | 146:f64d43ff0c18 | 474 | |
mbed_official | 146:f64d43ff0c18 | 475 | #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ |
mbed_official | 146:f64d43ff0c18 | 476 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 477 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 478 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 479 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 480 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 481 | BM_##reg##_##f6)), \ |
mbed_official | 146:f64d43ff0c18 | 482 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 483 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 484 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 485 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 486 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 487 | BF_##reg##_##f6(v6)))) |
mbed_official | 146:f64d43ff0c18 | 488 | |
mbed_official | 146:f64d43ff0c18 | 489 | #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ |
mbed_official | 146:f64d43ff0c18 | 490 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 491 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 492 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 493 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 494 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 495 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 496 | BM_##reg##_##f7)), \ |
mbed_official | 146:f64d43ff0c18 | 497 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 498 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 499 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 500 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 501 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 502 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 503 | BF_##reg##_##f7(v7)))) |
mbed_official | 146:f64d43ff0c18 | 504 | |
mbed_official | 146:f64d43ff0c18 | 505 | #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ |
mbed_official | 146:f64d43ff0c18 | 506 | (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ |
mbed_official | 146:f64d43ff0c18 | 507 | BM_##reg##_##f2 | \ |
mbed_official | 146:f64d43ff0c18 | 508 | BM_##reg##_##f3 | \ |
mbed_official | 146:f64d43ff0c18 | 509 | BM_##reg##_##f4 | \ |
mbed_official | 146:f64d43ff0c18 | 510 | BM_##reg##_##f5 | \ |
mbed_official | 146:f64d43ff0c18 | 511 | BM_##reg##_##f6 | \ |
mbed_official | 146:f64d43ff0c18 | 512 | BM_##reg##_##f7 | \ |
mbed_official | 146:f64d43ff0c18 | 513 | BM_##reg##_##f8)), \ |
mbed_official | 146:f64d43ff0c18 | 514 | HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ |
mbed_official | 146:f64d43ff0c18 | 515 | BF_##reg##_##f2(v2) | \ |
mbed_official | 146:f64d43ff0c18 | 516 | BF_##reg##_##f3(v3) | \ |
mbed_official | 146:f64d43ff0c18 | 517 | BF_##reg##_##f4(v4) | \ |
mbed_official | 146:f64d43ff0c18 | 518 | BF_##reg##_##f5(v5) | \ |
mbed_official | 146:f64d43ff0c18 | 519 | BF_##reg##_##f6(v6) | \ |
mbed_official | 146:f64d43ff0c18 | 520 | BF_##reg##_##f7(v7) | \ |
mbed_official | 146:f64d43ff0c18 | 521 | BF_##reg##_##f8(v8)))) |
mbed_official | 146:f64d43ff0c18 | 522 | |
mbed_official | 146:f64d43ff0c18 | 523 | #endif // _REGS_H |
mbed_official | 146:f64d43ff0c18 | 524 | |
mbed_official | 146:f64d43ff0c18 | 525 | //////////////////////////////////////////////////////////////////////////////// |