mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_uart.h@146:f64d43ff0c18, 2014-04-02 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Apr 02 21:00:08 2014 +0100
- Revision:
- 146:f64d43ff0c18
Synchronized with git revision d537c51d26da35e031d537f7fc90380fc74cb207
Full URL: https://github.com/mbedmicro/mbed/commit/d537c51d26da35e031d537f7fc90380fc74cb207/
target K64F
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_UART_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_UART_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 UART |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Serial Communication Interface |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_UART_BDH - UART Baud Rate Registers: High |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_UART_BDL - UART Baud Rate Registers: Low |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_UART_C1 - UART Control Register 1 |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_UART_C2 - UART Control Register 2 |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_UART_S1 - UART Status Register 1 |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_UART_S2 - UART Status Register 2 |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_UART_C3 - UART Control Register 3 |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_UART_D - UART Data Register |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_UART_MA1 - UART Match Address Registers 1 |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_UART_MA2 - UART Match Address Registers 2 |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_UART_C4 - UART Control Register 4 |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_UART_C5 - UART Control Register 5 |
mbed_official | 146:f64d43ff0c18 | 44 | * - HW_UART_ED - UART Extended Data Register |
mbed_official | 146:f64d43ff0c18 | 45 | * - HW_UART_MODEM - UART Modem Register |
mbed_official | 146:f64d43ff0c18 | 46 | * - HW_UART_IR - UART Infrared Register |
mbed_official | 146:f64d43ff0c18 | 47 | * - HW_UART_PFIFO - UART FIFO Parameters |
mbed_official | 146:f64d43ff0c18 | 48 | * - HW_UART_CFIFO - UART FIFO Control Register |
mbed_official | 146:f64d43ff0c18 | 49 | * - HW_UART_SFIFO - UART FIFO Status Register |
mbed_official | 146:f64d43ff0c18 | 50 | * - HW_UART_TWFIFO - UART FIFO Transmit Watermark |
mbed_official | 146:f64d43ff0c18 | 51 | * - HW_UART_TCFIFO - UART FIFO Transmit Count |
mbed_official | 146:f64d43ff0c18 | 52 | * - HW_UART_RWFIFO - UART FIFO Receive Watermark |
mbed_official | 146:f64d43ff0c18 | 53 | * - HW_UART_RCFIFO - UART FIFO Receive Count |
mbed_official | 146:f64d43ff0c18 | 54 | * - HW_UART_C7816 - UART 7816 Control Register |
mbed_official | 146:f64d43ff0c18 | 55 | * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register |
mbed_official | 146:f64d43ff0c18 | 56 | * - HW_UART_IS7816 - UART 7816 Interrupt Status Register |
mbed_official | 146:f64d43ff0c18 | 57 | * - HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register |
mbed_official | 146:f64d43ff0c18 | 58 | * - HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register |
mbed_official | 146:f64d43ff0c18 | 59 | * - HW_UART_WN7816 - UART 7816 Wait N Register |
mbed_official | 146:f64d43ff0c18 | 60 | * - HW_UART_WF7816 - UART 7816 Wait FD Register |
mbed_official | 146:f64d43ff0c18 | 61 | * - HW_UART_ET7816 - UART 7816 Error Threshold Register |
mbed_official | 146:f64d43ff0c18 | 62 | * - HW_UART_TL7816 - UART 7816 Transmit Length Register |
mbed_official | 146:f64d43ff0c18 | 63 | * |
mbed_official | 146:f64d43ff0c18 | 64 | * - hw_uart_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 65 | */ |
mbed_official | 146:f64d43ff0c18 | 66 | |
mbed_official | 146:f64d43ff0c18 | 67 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 68 | //@{ |
mbed_official | 146:f64d43ff0c18 | 69 | #ifndef REGS_UART_BASE |
mbed_official | 146:f64d43ff0c18 | 70 | #define HW_UART_INSTANCE_COUNT (6U) //!< Number of instances of the UART module. |
mbed_official | 146:f64d43ff0c18 | 71 | #define HW_UART0 (0U) //!< Instance number for UART0. |
mbed_official | 146:f64d43ff0c18 | 72 | #define HW_UART1 (1U) //!< Instance number for UART1. |
mbed_official | 146:f64d43ff0c18 | 73 | #define HW_UART2 (2U) //!< Instance number for UART2. |
mbed_official | 146:f64d43ff0c18 | 74 | #define HW_UART3 (3U) //!< Instance number for UART3. |
mbed_official | 146:f64d43ff0c18 | 75 | #define HW_UART4 (4U) //!< Instance number for UART4. |
mbed_official | 146:f64d43ff0c18 | 76 | #define HW_UART5 (5U) //!< Instance number for UART5. |
mbed_official | 146:f64d43ff0c18 | 77 | #define REGS_UART0_BASE (0x4006A000U) //!< Base address for UART0. |
mbed_official | 146:f64d43ff0c18 | 78 | #define REGS_UART1_BASE (0x4006B000U) //!< Base address for UART1. |
mbed_official | 146:f64d43ff0c18 | 79 | #define REGS_UART2_BASE (0x4006C000U) //!< Base address for UART2. |
mbed_official | 146:f64d43ff0c18 | 80 | #define REGS_UART3_BASE (0x4006D000U) //!< Base address for UART3. |
mbed_official | 146:f64d43ff0c18 | 81 | #define REGS_UART4_BASE (0x400EA000U) //!< Base address for UART4. |
mbed_official | 146:f64d43ff0c18 | 82 | #define REGS_UART5_BASE (0x400EB000U) //!< Base address for UART5. |
mbed_official | 146:f64d43ff0c18 | 83 | |
mbed_official | 146:f64d43ff0c18 | 84 | //! @brief Table of base addresses for UART instances. |
mbed_official | 146:f64d43ff0c18 | 85 | static const uint32_t __g_regs_UART_base_addresses[] = { |
mbed_official | 146:f64d43ff0c18 | 86 | REGS_UART0_BASE, |
mbed_official | 146:f64d43ff0c18 | 87 | REGS_UART1_BASE, |
mbed_official | 146:f64d43ff0c18 | 88 | REGS_UART2_BASE, |
mbed_official | 146:f64d43ff0c18 | 89 | REGS_UART3_BASE, |
mbed_official | 146:f64d43ff0c18 | 90 | REGS_UART4_BASE, |
mbed_official | 146:f64d43ff0c18 | 91 | REGS_UART5_BASE, |
mbed_official | 146:f64d43ff0c18 | 92 | }; |
mbed_official | 146:f64d43ff0c18 | 93 | |
mbed_official | 146:f64d43ff0c18 | 94 | //! @brief Get the base address of UART by instance number. |
mbed_official | 146:f64d43ff0c18 | 95 | //! @param x UART instance number, from 0 through 5. |
mbed_official | 146:f64d43ff0c18 | 96 | #define REGS_UART_BASE(x) (__g_regs_UART_base_addresses[(x)]) |
mbed_official | 146:f64d43ff0c18 | 97 | |
mbed_official | 146:f64d43ff0c18 | 98 | //! @brief Get the instance number given a base address. |
mbed_official | 146:f64d43ff0c18 | 99 | //! @param b Base address for an instance of UART. |
mbed_official | 146:f64d43ff0c18 | 100 | #define REGS_UART_INSTANCE(b) ((b) == REGS_UART0_BASE ? HW_UART0 : (b) == REGS_UART1_BASE ? HW_UART1 : (b) == REGS_UART2_BASE ? HW_UART2 : (b) == REGS_UART3_BASE ? HW_UART3 : (b) == REGS_UART4_BASE ? HW_UART4 : (b) == REGS_UART5_BASE ? HW_UART5 : 0) |
mbed_official | 146:f64d43ff0c18 | 101 | #endif |
mbed_official | 146:f64d43ff0c18 | 102 | //@} |
mbed_official | 146:f64d43ff0c18 | 103 | |
mbed_official | 146:f64d43ff0c18 | 104 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 105 | // HW_UART_BDH - UART Baud Rate Registers: High |
mbed_official | 146:f64d43ff0c18 | 106 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 107 | |
mbed_official | 146:f64d43ff0c18 | 108 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 109 | /*! |
mbed_official | 146:f64d43ff0c18 | 110 | * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW) |
mbed_official | 146:f64d43ff0c18 | 111 | * |
mbed_official | 146:f64d43ff0c18 | 112 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 113 | * |
mbed_official | 146:f64d43ff0c18 | 114 | * This register, along with the BDL register, controls the prescale divisor for |
mbed_official | 146:f64d43ff0c18 | 115 | * UART baud rate generation. To update the 13-bit baud rate setting |
mbed_official | 146:f64d43ff0c18 | 116 | * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write |
mbed_official | 146:f64d43ff0c18 | 117 | * to BDL. The working value in BDH does not change until BDL is written. BDL is |
mbed_official | 146:f64d43ff0c18 | 118 | * reset to a nonzero value, but after reset, the baud rate generator remains |
mbed_official | 146:f64d43ff0c18 | 119 | * disabled until the first time the receiver or transmitter is enabled, that is, |
mbed_official | 146:f64d43ff0c18 | 120 | * when C2[RE] or C2[TE] is set. |
mbed_official | 146:f64d43ff0c18 | 121 | */ |
mbed_official | 146:f64d43ff0c18 | 122 | typedef union _hw_uart_bdh |
mbed_official | 146:f64d43ff0c18 | 123 | { |
mbed_official | 146:f64d43ff0c18 | 124 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 125 | struct _hw_uart_bdh_bitfields |
mbed_official | 146:f64d43ff0c18 | 126 | { |
mbed_official | 146:f64d43ff0c18 | 127 | uint8_t SBR : 5; //!< [4:0] UART Baud Rate Bits |
mbed_official | 146:f64d43ff0c18 | 128 | uint8_t SBNS : 1; //!< [5] Stop Bit Number Select |
mbed_official | 146:f64d43ff0c18 | 129 | uint8_t RXEDGIE : 1; //!< [6] RxD Input Active Edge Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 130 | uint8_t LBKDIE : 1; //!< [7] LIN Break Detect Interrupt or DMA |
mbed_official | 146:f64d43ff0c18 | 131 | //! Request Enable |
mbed_official | 146:f64d43ff0c18 | 132 | } B; |
mbed_official | 146:f64d43ff0c18 | 133 | } hw_uart_bdh_t; |
mbed_official | 146:f64d43ff0c18 | 134 | #endif |
mbed_official | 146:f64d43ff0c18 | 135 | |
mbed_official | 146:f64d43ff0c18 | 136 | /*! |
mbed_official | 146:f64d43ff0c18 | 137 | * @name Constants and macros for entire UART_BDH register |
mbed_official | 146:f64d43ff0c18 | 138 | */ |
mbed_official | 146:f64d43ff0c18 | 139 | //@{ |
mbed_official | 146:f64d43ff0c18 | 140 | #define HW_UART_BDH_ADDR(x) (REGS_UART_BASE(x) + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 141 | |
mbed_official | 146:f64d43ff0c18 | 142 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 143 | #define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 144 | #define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U) |
mbed_official | 146:f64d43ff0c18 | 145 | #define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 146 | #define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 147 | #define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 148 | #define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 149 | #endif |
mbed_official | 146:f64d43ff0c18 | 150 | //@} |
mbed_official | 146:f64d43ff0c18 | 151 | |
mbed_official | 146:f64d43ff0c18 | 152 | /* |
mbed_official | 146:f64d43ff0c18 | 153 | * Constants & macros for individual UART_BDH bitfields |
mbed_official | 146:f64d43ff0c18 | 154 | */ |
mbed_official | 146:f64d43ff0c18 | 155 | |
mbed_official | 146:f64d43ff0c18 | 156 | /*! |
mbed_official | 146:f64d43ff0c18 | 157 | * @name Register UART_BDH, field SBR[4:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 158 | * |
mbed_official | 146:f64d43ff0c18 | 159 | * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate |
mbed_official | 146:f64d43ff0c18 | 160 | * generation for details. The baud rate generator is disabled until C2[TE] or |
mbed_official | 146:f64d43ff0c18 | 161 | * C2[RE] is set for the first time after reset.The baud rate generator is disabled |
mbed_official | 146:f64d43ff0c18 | 162 | * when SBR = 0. Writing to BDH has no effect without writing to BDL, because |
mbed_official | 146:f64d43ff0c18 | 163 | * writing to BDH puts the data in a temporary location until BDL is written. |
mbed_official | 146:f64d43ff0c18 | 164 | */ |
mbed_official | 146:f64d43ff0c18 | 165 | //@{ |
mbed_official | 146:f64d43ff0c18 | 166 | #define BP_UART_BDH_SBR (0U) //!< Bit position for UART_BDH_SBR. |
mbed_official | 146:f64d43ff0c18 | 167 | #define BM_UART_BDH_SBR (0x1FU) //!< Bit mask for UART_BDH_SBR. |
mbed_official | 146:f64d43ff0c18 | 168 | #define BS_UART_BDH_SBR (5U) //!< Bit field size in bits for UART_BDH_SBR. |
mbed_official | 146:f64d43ff0c18 | 169 | |
mbed_official | 146:f64d43ff0c18 | 170 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 171 | //! @brief Read current value of the UART_BDH_SBR field. |
mbed_official | 146:f64d43ff0c18 | 172 | #define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR) |
mbed_official | 146:f64d43ff0c18 | 173 | #endif |
mbed_official | 146:f64d43ff0c18 | 174 | |
mbed_official | 146:f64d43ff0c18 | 175 | //! @brief Format value for bitfield UART_BDH_SBR. |
mbed_official | 146:f64d43ff0c18 | 176 | #define BF_UART_BDH_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBR), uint8_t) & BM_UART_BDH_SBR) |
mbed_official | 146:f64d43ff0c18 | 177 | |
mbed_official | 146:f64d43ff0c18 | 178 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 179 | //! @brief Set the SBR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 180 | #define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v))) |
mbed_official | 146:f64d43ff0c18 | 181 | #endif |
mbed_official | 146:f64d43ff0c18 | 182 | //@} |
mbed_official | 146:f64d43ff0c18 | 183 | |
mbed_official | 146:f64d43ff0c18 | 184 | /*! |
mbed_official | 146:f64d43ff0c18 | 185 | * @name Register UART_BDH, field SBNS[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 186 | * |
mbed_official | 146:f64d43ff0c18 | 187 | * SBNS selects the number of stop bits present in a data frame. This field |
mbed_official | 146:f64d43ff0c18 | 188 | * valid for all 8, 9 and 10 bit data formats available. This field is not valid when |
mbed_official | 146:f64d43ff0c18 | 189 | * C7816[ISO7816E] is enabled. |
mbed_official | 146:f64d43ff0c18 | 190 | * |
mbed_official | 146:f64d43ff0c18 | 191 | * Values: |
mbed_official | 146:f64d43ff0c18 | 192 | * - 0 - Data frame consists of a single stop bit. |
mbed_official | 146:f64d43ff0c18 | 193 | * - 1 - Data frame consists of two stop bits. |
mbed_official | 146:f64d43ff0c18 | 194 | */ |
mbed_official | 146:f64d43ff0c18 | 195 | //@{ |
mbed_official | 146:f64d43ff0c18 | 196 | #define BP_UART_BDH_SBNS (5U) //!< Bit position for UART_BDH_SBNS. |
mbed_official | 146:f64d43ff0c18 | 197 | #define BM_UART_BDH_SBNS (0x20U) //!< Bit mask for UART_BDH_SBNS. |
mbed_official | 146:f64d43ff0c18 | 198 | #define BS_UART_BDH_SBNS (1U) //!< Bit field size in bits for UART_BDH_SBNS. |
mbed_official | 146:f64d43ff0c18 | 199 | |
mbed_official | 146:f64d43ff0c18 | 200 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 201 | //! @brief Read current value of the UART_BDH_SBNS field. |
mbed_official | 146:f64d43ff0c18 | 202 | #define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS)) |
mbed_official | 146:f64d43ff0c18 | 203 | #endif |
mbed_official | 146:f64d43ff0c18 | 204 | |
mbed_official | 146:f64d43ff0c18 | 205 | //! @brief Format value for bitfield UART_BDH_SBNS. |
mbed_official | 146:f64d43ff0c18 | 206 | #define BF_UART_BDH_SBNS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBNS), uint8_t) & BM_UART_BDH_SBNS) |
mbed_official | 146:f64d43ff0c18 | 207 | |
mbed_official | 146:f64d43ff0c18 | 208 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 209 | //! @brief Set the SBNS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 210 | #define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 211 | #endif |
mbed_official | 146:f64d43ff0c18 | 212 | //@} |
mbed_official | 146:f64d43ff0c18 | 213 | |
mbed_official | 146:f64d43ff0c18 | 214 | /*! |
mbed_official | 146:f64d43ff0c18 | 215 | * @name Register UART_BDH, field RXEDGIE[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 216 | * |
mbed_official | 146:f64d43ff0c18 | 217 | * Enables the receive input active edge, RXEDGIF, to generate interrupt |
mbed_official | 146:f64d43ff0c18 | 218 | * requests. |
mbed_official | 146:f64d43ff0c18 | 219 | * |
mbed_official | 146:f64d43ff0c18 | 220 | * Values: |
mbed_official | 146:f64d43ff0c18 | 221 | * - 0 - Hardware interrupts from RXEDGIF disabled using polling. |
mbed_official | 146:f64d43ff0c18 | 222 | * - 1 - RXEDGIF interrupt request enabled. |
mbed_official | 146:f64d43ff0c18 | 223 | */ |
mbed_official | 146:f64d43ff0c18 | 224 | //@{ |
mbed_official | 146:f64d43ff0c18 | 225 | #define BP_UART_BDH_RXEDGIE (6U) //!< Bit position for UART_BDH_RXEDGIE. |
mbed_official | 146:f64d43ff0c18 | 226 | #define BM_UART_BDH_RXEDGIE (0x40U) //!< Bit mask for UART_BDH_RXEDGIE. |
mbed_official | 146:f64d43ff0c18 | 227 | #define BS_UART_BDH_RXEDGIE (1U) //!< Bit field size in bits for UART_BDH_RXEDGIE. |
mbed_official | 146:f64d43ff0c18 | 228 | |
mbed_official | 146:f64d43ff0c18 | 229 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 230 | //! @brief Read current value of the UART_BDH_RXEDGIE field. |
mbed_official | 146:f64d43ff0c18 | 231 | #define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE)) |
mbed_official | 146:f64d43ff0c18 | 232 | #endif |
mbed_official | 146:f64d43ff0c18 | 233 | |
mbed_official | 146:f64d43ff0c18 | 234 | //! @brief Format value for bitfield UART_BDH_RXEDGIE. |
mbed_official | 146:f64d43ff0c18 | 235 | #define BF_UART_BDH_RXEDGIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_RXEDGIE), uint8_t) & BM_UART_BDH_RXEDGIE) |
mbed_official | 146:f64d43ff0c18 | 236 | |
mbed_official | 146:f64d43ff0c18 | 237 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 238 | //! @brief Set the RXEDGIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 239 | #define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 240 | #endif |
mbed_official | 146:f64d43ff0c18 | 241 | //@} |
mbed_official | 146:f64d43ff0c18 | 242 | |
mbed_official | 146:f64d43ff0c18 | 243 | /*! |
mbed_official | 146:f64d43ff0c18 | 244 | * @name Register UART_BDH, field LBKDIE[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 245 | * |
mbed_official | 146:f64d43ff0c18 | 246 | * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests |
mbed_official | 146:f64d43ff0c18 | 247 | * based on the state of LBKDDMAS. or DMA transfer requests, |
mbed_official | 146:f64d43ff0c18 | 248 | * |
mbed_official | 146:f64d43ff0c18 | 249 | * Values: |
mbed_official | 146:f64d43ff0c18 | 250 | * - 0 - LBKDIF interrupt and DMA transfer requests disabled. |
mbed_official | 146:f64d43ff0c18 | 251 | * - 1 - LBKDIF interrupt or DMA transfer requests enabled. |
mbed_official | 146:f64d43ff0c18 | 252 | */ |
mbed_official | 146:f64d43ff0c18 | 253 | //@{ |
mbed_official | 146:f64d43ff0c18 | 254 | #define BP_UART_BDH_LBKDIE (7U) //!< Bit position for UART_BDH_LBKDIE. |
mbed_official | 146:f64d43ff0c18 | 255 | #define BM_UART_BDH_LBKDIE (0x80U) //!< Bit mask for UART_BDH_LBKDIE. |
mbed_official | 146:f64d43ff0c18 | 256 | #define BS_UART_BDH_LBKDIE (1U) //!< Bit field size in bits for UART_BDH_LBKDIE. |
mbed_official | 146:f64d43ff0c18 | 257 | |
mbed_official | 146:f64d43ff0c18 | 258 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 259 | //! @brief Read current value of the UART_BDH_LBKDIE field. |
mbed_official | 146:f64d43ff0c18 | 260 | #define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE)) |
mbed_official | 146:f64d43ff0c18 | 261 | #endif |
mbed_official | 146:f64d43ff0c18 | 262 | |
mbed_official | 146:f64d43ff0c18 | 263 | //! @brief Format value for bitfield UART_BDH_LBKDIE. |
mbed_official | 146:f64d43ff0c18 | 264 | #define BF_UART_BDH_LBKDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_LBKDIE), uint8_t) & BM_UART_BDH_LBKDIE) |
mbed_official | 146:f64d43ff0c18 | 265 | |
mbed_official | 146:f64d43ff0c18 | 266 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 267 | //! @brief Set the LBKDIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 268 | #define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 269 | #endif |
mbed_official | 146:f64d43ff0c18 | 270 | //@} |
mbed_official | 146:f64d43ff0c18 | 271 | |
mbed_official | 146:f64d43ff0c18 | 272 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 273 | // HW_UART_BDL - UART Baud Rate Registers: Low |
mbed_official | 146:f64d43ff0c18 | 274 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 275 | |
mbed_official | 146:f64d43ff0c18 | 276 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 277 | /*! |
mbed_official | 146:f64d43ff0c18 | 278 | * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW) |
mbed_official | 146:f64d43ff0c18 | 279 | * |
mbed_official | 146:f64d43ff0c18 | 280 | * Reset value: 0x04U |
mbed_official | 146:f64d43ff0c18 | 281 | * |
mbed_official | 146:f64d43ff0c18 | 282 | * This register, along with the BDH register, controls the prescale divisor for |
mbed_official | 146:f64d43ff0c18 | 283 | * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0], |
mbed_official | 146:f64d43ff0c18 | 284 | * first write to BDH to buffer the high half of the new value and then write to |
mbed_official | 146:f64d43ff0c18 | 285 | * BDL. The working value in BDH does not change until BDL is written. BDL is |
mbed_official | 146:f64d43ff0c18 | 286 | * reset to a nonzero value, but after reset, the baud rate generator remains |
mbed_official | 146:f64d43ff0c18 | 287 | * disabled until the first time the receiver or transmitter is enabled, that is, when |
mbed_official | 146:f64d43ff0c18 | 288 | * C2[RE] or C2[TE] is set. |
mbed_official | 146:f64d43ff0c18 | 289 | */ |
mbed_official | 146:f64d43ff0c18 | 290 | typedef union _hw_uart_bdl |
mbed_official | 146:f64d43ff0c18 | 291 | { |
mbed_official | 146:f64d43ff0c18 | 292 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 293 | struct _hw_uart_bdl_bitfields |
mbed_official | 146:f64d43ff0c18 | 294 | { |
mbed_official | 146:f64d43ff0c18 | 295 | uint8_t SBR : 8; //!< [7:0] UART Baud Rate Bits |
mbed_official | 146:f64d43ff0c18 | 296 | } B; |
mbed_official | 146:f64d43ff0c18 | 297 | } hw_uart_bdl_t; |
mbed_official | 146:f64d43ff0c18 | 298 | #endif |
mbed_official | 146:f64d43ff0c18 | 299 | |
mbed_official | 146:f64d43ff0c18 | 300 | /*! |
mbed_official | 146:f64d43ff0c18 | 301 | * @name Constants and macros for entire UART_BDL register |
mbed_official | 146:f64d43ff0c18 | 302 | */ |
mbed_official | 146:f64d43ff0c18 | 303 | //@{ |
mbed_official | 146:f64d43ff0c18 | 304 | #define HW_UART_BDL_ADDR(x) (REGS_UART_BASE(x) + 0x1U) |
mbed_official | 146:f64d43ff0c18 | 305 | |
mbed_official | 146:f64d43ff0c18 | 306 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 307 | #define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 308 | #define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U) |
mbed_official | 146:f64d43ff0c18 | 309 | #define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 310 | #define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 311 | #define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 312 | #define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 313 | #endif |
mbed_official | 146:f64d43ff0c18 | 314 | //@} |
mbed_official | 146:f64d43ff0c18 | 315 | |
mbed_official | 146:f64d43ff0c18 | 316 | /* |
mbed_official | 146:f64d43ff0c18 | 317 | * Constants & macros for individual UART_BDL bitfields |
mbed_official | 146:f64d43ff0c18 | 318 | */ |
mbed_official | 146:f64d43ff0c18 | 319 | |
mbed_official | 146:f64d43ff0c18 | 320 | /*! |
mbed_official | 146:f64d43ff0c18 | 321 | * @name Register UART_BDL, field SBR[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 322 | * |
mbed_official | 146:f64d43ff0c18 | 323 | * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate |
mbed_official | 146:f64d43ff0c18 | 324 | * generation for details. The baud rate generator is disabled until C2[TE] or |
mbed_official | 146:f64d43ff0c18 | 325 | * C2[RE] is set for the first time after reset.The baud rate generator is disabled |
mbed_official | 146:f64d43ff0c18 | 326 | * when SBR = 0. Writing to BDH has no effect without writing to BDL, because |
mbed_official | 146:f64d43ff0c18 | 327 | * writing to BDH puts the data in a temporary location until BDL is written. When |
mbed_official | 146:f64d43ff0c18 | 328 | * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate |
mbed_official | 146:f64d43ff0c18 | 329 | * fields must be even, the least significant bit is 0. See MODEM register for more |
mbed_official | 146:f64d43ff0c18 | 330 | * details. |
mbed_official | 146:f64d43ff0c18 | 331 | */ |
mbed_official | 146:f64d43ff0c18 | 332 | //@{ |
mbed_official | 146:f64d43ff0c18 | 333 | #define BP_UART_BDL_SBR (0U) //!< Bit position for UART_BDL_SBR. |
mbed_official | 146:f64d43ff0c18 | 334 | #define BM_UART_BDL_SBR (0xFFU) //!< Bit mask for UART_BDL_SBR. |
mbed_official | 146:f64d43ff0c18 | 335 | #define BS_UART_BDL_SBR (8U) //!< Bit field size in bits for UART_BDL_SBR. |
mbed_official | 146:f64d43ff0c18 | 336 | |
mbed_official | 146:f64d43ff0c18 | 337 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 338 | //! @brief Read current value of the UART_BDL_SBR field. |
mbed_official | 146:f64d43ff0c18 | 339 | #define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U) |
mbed_official | 146:f64d43ff0c18 | 340 | #endif |
mbed_official | 146:f64d43ff0c18 | 341 | |
mbed_official | 146:f64d43ff0c18 | 342 | //! @brief Format value for bitfield UART_BDL_SBR. |
mbed_official | 146:f64d43ff0c18 | 343 | #define BF_UART_BDL_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDL_SBR), uint8_t) & BM_UART_BDL_SBR) |
mbed_official | 146:f64d43ff0c18 | 344 | |
mbed_official | 146:f64d43ff0c18 | 345 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 346 | //! @brief Set the SBR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 347 | #define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 348 | #endif |
mbed_official | 146:f64d43ff0c18 | 349 | //@} |
mbed_official | 146:f64d43ff0c18 | 350 | |
mbed_official | 146:f64d43ff0c18 | 351 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 352 | // HW_UART_C1 - UART Control Register 1 |
mbed_official | 146:f64d43ff0c18 | 353 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 354 | |
mbed_official | 146:f64d43ff0c18 | 355 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 356 | /*! |
mbed_official | 146:f64d43ff0c18 | 357 | * @brief HW_UART_C1 - UART Control Register 1 (RW) |
mbed_official | 146:f64d43ff0c18 | 358 | * |
mbed_official | 146:f64d43ff0c18 | 359 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 360 | * |
mbed_official | 146:f64d43ff0c18 | 361 | * This read/write register controls various optional features of the UART |
mbed_official | 146:f64d43ff0c18 | 362 | * system. |
mbed_official | 146:f64d43ff0c18 | 363 | */ |
mbed_official | 146:f64d43ff0c18 | 364 | typedef union _hw_uart_c1 |
mbed_official | 146:f64d43ff0c18 | 365 | { |
mbed_official | 146:f64d43ff0c18 | 366 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 367 | struct _hw_uart_c1_bitfields |
mbed_official | 146:f64d43ff0c18 | 368 | { |
mbed_official | 146:f64d43ff0c18 | 369 | uint8_t PT : 1; //!< [0] Parity Type |
mbed_official | 146:f64d43ff0c18 | 370 | uint8_t PE : 1; //!< [1] Parity Enable |
mbed_official | 146:f64d43ff0c18 | 371 | uint8_t ILT : 1; //!< [2] Idle Line Type Select |
mbed_official | 146:f64d43ff0c18 | 372 | uint8_t WAKE : 1; //!< [3] Receiver Wakeup Method Select |
mbed_official | 146:f64d43ff0c18 | 373 | uint8_t M : 1; //!< [4] 9-bit or 8-bit Mode Select |
mbed_official | 146:f64d43ff0c18 | 374 | uint8_t RSRC : 1; //!< [5] Receiver Source Select |
mbed_official | 146:f64d43ff0c18 | 375 | uint8_t UARTSWAI : 1; //!< [6] UART Stops in Wait Mode |
mbed_official | 146:f64d43ff0c18 | 376 | uint8_t LOOPS : 1; //!< [7] Loop Mode Select |
mbed_official | 146:f64d43ff0c18 | 377 | } B; |
mbed_official | 146:f64d43ff0c18 | 378 | } hw_uart_c1_t; |
mbed_official | 146:f64d43ff0c18 | 379 | #endif |
mbed_official | 146:f64d43ff0c18 | 380 | |
mbed_official | 146:f64d43ff0c18 | 381 | /*! |
mbed_official | 146:f64d43ff0c18 | 382 | * @name Constants and macros for entire UART_C1 register |
mbed_official | 146:f64d43ff0c18 | 383 | */ |
mbed_official | 146:f64d43ff0c18 | 384 | //@{ |
mbed_official | 146:f64d43ff0c18 | 385 | #define HW_UART_C1_ADDR(x) (REGS_UART_BASE(x) + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 386 | |
mbed_official | 146:f64d43ff0c18 | 387 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 388 | #define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 389 | #define HW_UART_C1_RD(x) (HW_UART_C1(x).U) |
mbed_official | 146:f64d43ff0c18 | 390 | #define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 391 | #define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 392 | #define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 393 | #define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 394 | #endif |
mbed_official | 146:f64d43ff0c18 | 395 | //@} |
mbed_official | 146:f64d43ff0c18 | 396 | |
mbed_official | 146:f64d43ff0c18 | 397 | /* |
mbed_official | 146:f64d43ff0c18 | 398 | * Constants & macros for individual UART_C1 bitfields |
mbed_official | 146:f64d43ff0c18 | 399 | */ |
mbed_official | 146:f64d43ff0c18 | 400 | |
mbed_official | 146:f64d43ff0c18 | 401 | /*! |
mbed_official | 146:f64d43ff0c18 | 402 | * @name Register UART_C1, field PT[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 403 | * |
mbed_official | 146:f64d43ff0c18 | 404 | * Determines whether the UART generates and checks for even parity or odd |
mbed_official | 146:f64d43ff0c18 | 405 | * parity. With even parity, an even number of 1s clears the parity bit and an odd |
mbed_official | 146:f64d43ff0c18 | 406 | * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the |
mbed_official | 146:f64d43ff0c18 | 407 | * parity bit and an even number of 1s sets the parity bit. This field must be |
mbed_official | 146:f64d43ff0c18 | 408 | * cleared when C7816[ISO_7816E] is set/enabled. |
mbed_official | 146:f64d43ff0c18 | 409 | * |
mbed_official | 146:f64d43ff0c18 | 410 | * Values: |
mbed_official | 146:f64d43ff0c18 | 411 | * - 0 - Even parity. |
mbed_official | 146:f64d43ff0c18 | 412 | * - 1 - Odd parity. |
mbed_official | 146:f64d43ff0c18 | 413 | */ |
mbed_official | 146:f64d43ff0c18 | 414 | //@{ |
mbed_official | 146:f64d43ff0c18 | 415 | #define BP_UART_C1_PT (0U) //!< Bit position for UART_C1_PT. |
mbed_official | 146:f64d43ff0c18 | 416 | #define BM_UART_C1_PT (0x01U) //!< Bit mask for UART_C1_PT. |
mbed_official | 146:f64d43ff0c18 | 417 | #define BS_UART_C1_PT (1U) //!< Bit field size in bits for UART_C1_PT. |
mbed_official | 146:f64d43ff0c18 | 418 | |
mbed_official | 146:f64d43ff0c18 | 419 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 420 | //! @brief Read current value of the UART_C1_PT field. |
mbed_official | 146:f64d43ff0c18 | 421 | #define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT)) |
mbed_official | 146:f64d43ff0c18 | 422 | #endif |
mbed_official | 146:f64d43ff0c18 | 423 | |
mbed_official | 146:f64d43ff0c18 | 424 | //! @brief Format value for bitfield UART_C1_PT. |
mbed_official | 146:f64d43ff0c18 | 425 | #define BF_UART_C1_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PT), uint8_t) & BM_UART_C1_PT) |
mbed_official | 146:f64d43ff0c18 | 426 | |
mbed_official | 146:f64d43ff0c18 | 427 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 428 | //! @brief Set the PT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 429 | #define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 430 | #endif |
mbed_official | 146:f64d43ff0c18 | 431 | //@} |
mbed_official | 146:f64d43ff0c18 | 432 | |
mbed_official | 146:f64d43ff0c18 | 433 | /*! |
mbed_official | 146:f64d43ff0c18 | 434 | * @name Register UART_C1, field PE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 435 | * |
mbed_official | 146:f64d43ff0c18 | 436 | * Enables the parity function. When parity is enabled, parity function inserts |
mbed_official | 146:f64d43ff0c18 | 437 | * a parity bit in the bit position immediately preceding the stop bit. This |
mbed_official | 146:f64d43ff0c18 | 438 | * field must be set when C7816[ISO_7816E] is set/enabled. |
mbed_official | 146:f64d43ff0c18 | 439 | * |
mbed_official | 146:f64d43ff0c18 | 440 | * Values: |
mbed_official | 146:f64d43ff0c18 | 441 | * - 0 - Parity function disabled. |
mbed_official | 146:f64d43ff0c18 | 442 | * - 1 - Parity function enabled. |
mbed_official | 146:f64d43ff0c18 | 443 | */ |
mbed_official | 146:f64d43ff0c18 | 444 | //@{ |
mbed_official | 146:f64d43ff0c18 | 445 | #define BP_UART_C1_PE (1U) //!< Bit position for UART_C1_PE. |
mbed_official | 146:f64d43ff0c18 | 446 | #define BM_UART_C1_PE (0x02U) //!< Bit mask for UART_C1_PE. |
mbed_official | 146:f64d43ff0c18 | 447 | #define BS_UART_C1_PE (1U) //!< Bit field size in bits for UART_C1_PE. |
mbed_official | 146:f64d43ff0c18 | 448 | |
mbed_official | 146:f64d43ff0c18 | 449 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 450 | //! @brief Read current value of the UART_C1_PE field. |
mbed_official | 146:f64d43ff0c18 | 451 | #define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE)) |
mbed_official | 146:f64d43ff0c18 | 452 | #endif |
mbed_official | 146:f64d43ff0c18 | 453 | |
mbed_official | 146:f64d43ff0c18 | 454 | //! @brief Format value for bitfield UART_C1_PE. |
mbed_official | 146:f64d43ff0c18 | 455 | #define BF_UART_C1_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PE), uint8_t) & BM_UART_C1_PE) |
mbed_official | 146:f64d43ff0c18 | 456 | |
mbed_official | 146:f64d43ff0c18 | 457 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 458 | //! @brief Set the PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 459 | #define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 460 | #endif |
mbed_official | 146:f64d43ff0c18 | 461 | //@} |
mbed_official | 146:f64d43ff0c18 | 462 | |
mbed_official | 146:f64d43ff0c18 | 463 | /*! |
mbed_official | 146:f64d43ff0c18 | 464 | * @name Register UART_C1, field ILT[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 465 | * |
mbed_official | 146:f64d43ff0c18 | 466 | * Determines when the receiver starts counting logic 1s as idle character bits. |
mbed_official | 146:f64d43ff0c18 | 467 | * The count begins either after a valid start bit or after the stop bit. If the |
mbed_official | 146:f64d43ff0c18 | 468 | * count begins after the start bit, then a string of logic 1s preceding the |
mbed_official | 146:f64d43ff0c18 | 469 | * stop bit can cause false recognition of an idle character. Beginning the count |
mbed_official | 146:f64d43ff0c18 | 470 | * after the stop bit avoids false idle character recognition, but requires |
mbed_official | 146:f64d43ff0c18 | 471 | * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a |
mbed_official | 146:f64d43ff0c18 | 472 | * logic of 1'b0 is automatically shifted after a received stop bit, therefore |
mbed_official | 146:f64d43ff0c18 | 473 | * resetting the idle count. In case the UART is programmed for IDLE line wakeup |
mbed_official | 146:f64d43ff0c18 | 474 | * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting |
mbed_official | 146:f64d43ff0c18 | 475 | * logic 1s as idle character bits. In idle line wakeup, an idle character is |
mbed_official | 146:f64d43ff0c18 | 476 | * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE, |
mbed_official | 146:f64d43ff0c18 | 477 | * and C4[M10] fields. |
mbed_official | 146:f64d43ff0c18 | 478 | * |
mbed_official | 146:f64d43ff0c18 | 479 | * Values: |
mbed_official | 146:f64d43ff0c18 | 480 | * - 0 - Idle character bit count starts after start bit. |
mbed_official | 146:f64d43ff0c18 | 481 | * - 1 - Idle character bit count starts after stop bit. |
mbed_official | 146:f64d43ff0c18 | 482 | */ |
mbed_official | 146:f64d43ff0c18 | 483 | //@{ |
mbed_official | 146:f64d43ff0c18 | 484 | #define BP_UART_C1_ILT (2U) //!< Bit position for UART_C1_ILT. |
mbed_official | 146:f64d43ff0c18 | 485 | #define BM_UART_C1_ILT (0x04U) //!< Bit mask for UART_C1_ILT. |
mbed_official | 146:f64d43ff0c18 | 486 | #define BS_UART_C1_ILT (1U) //!< Bit field size in bits for UART_C1_ILT. |
mbed_official | 146:f64d43ff0c18 | 487 | |
mbed_official | 146:f64d43ff0c18 | 488 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 489 | //! @brief Read current value of the UART_C1_ILT field. |
mbed_official | 146:f64d43ff0c18 | 490 | #define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT)) |
mbed_official | 146:f64d43ff0c18 | 491 | #endif |
mbed_official | 146:f64d43ff0c18 | 492 | |
mbed_official | 146:f64d43ff0c18 | 493 | //! @brief Format value for bitfield UART_C1_ILT. |
mbed_official | 146:f64d43ff0c18 | 494 | #define BF_UART_C1_ILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_ILT), uint8_t) & BM_UART_C1_ILT) |
mbed_official | 146:f64d43ff0c18 | 495 | |
mbed_official | 146:f64d43ff0c18 | 496 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 497 | //! @brief Set the ILT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 498 | #define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 499 | #endif |
mbed_official | 146:f64d43ff0c18 | 500 | //@} |
mbed_official | 146:f64d43ff0c18 | 501 | |
mbed_official | 146:f64d43ff0c18 | 502 | /*! |
mbed_official | 146:f64d43ff0c18 | 503 | * @name Register UART_C1, field WAKE[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 504 | * |
mbed_official | 146:f64d43ff0c18 | 505 | * Determines which condition wakes the UART: Address mark in the most |
mbed_official | 146:f64d43ff0c18 | 506 | * significant bit position of a received data character, or An idle condition on the |
mbed_official | 146:f64d43ff0c18 | 507 | * receive pin input signal. |
mbed_official | 146:f64d43ff0c18 | 508 | * |
mbed_official | 146:f64d43ff0c18 | 509 | * Values: |
mbed_official | 146:f64d43ff0c18 | 510 | * - 0 - Idle line wakeup. |
mbed_official | 146:f64d43ff0c18 | 511 | * - 1 - Address mark wakeup. |
mbed_official | 146:f64d43ff0c18 | 512 | */ |
mbed_official | 146:f64d43ff0c18 | 513 | //@{ |
mbed_official | 146:f64d43ff0c18 | 514 | #define BP_UART_C1_WAKE (3U) //!< Bit position for UART_C1_WAKE. |
mbed_official | 146:f64d43ff0c18 | 515 | #define BM_UART_C1_WAKE (0x08U) //!< Bit mask for UART_C1_WAKE. |
mbed_official | 146:f64d43ff0c18 | 516 | #define BS_UART_C1_WAKE (1U) //!< Bit field size in bits for UART_C1_WAKE. |
mbed_official | 146:f64d43ff0c18 | 517 | |
mbed_official | 146:f64d43ff0c18 | 518 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 519 | //! @brief Read current value of the UART_C1_WAKE field. |
mbed_official | 146:f64d43ff0c18 | 520 | #define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE)) |
mbed_official | 146:f64d43ff0c18 | 521 | #endif |
mbed_official | 146:f64d43ff0c18 | 522 | |
mbed_official | 146:f64d43ff0c18 | 523 | //! @brief Format value for bitfield UART_C1_WAKE. |
mbed_official | 146:f64d43ff0c18 | 524 | #define BF_UART_C1_WAKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_WAKE), uint8_t) & BM_UART_C1_WAKE) |
mbed_official | 146:f64d43ff0c18 | 525 | |
mbed_official | 146:f64d43ff0c18 | 526 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 527 | //! @brief Set the WAKE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 528 | #define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 529 | #endif |
mbed_official | 146:f64d43ff0c18 | 530 | //@} |
mbed_official | 146:f64d43ff0c18 | 531 | |
mbed_official | 146:f64d43ff0c18 | 532 | /*! |
mbed_official | 146:f64d43ff0c18 | 533 | * @name Register UART_C1, field M[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 534 | * |
mbed_official | 146:f64d43ff0c18 | 535 | * This field must be set when C7816[ISO_7816E] is set/enabled. |
mbed_official | 146:f64d43ff0c18 | 536 | * |
mbed_official | 146:f64d43ff0c18 | 537 | * Values: |
mbed_official | 146:f64d43ff0c18 | 538 | * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. |
mbed_official | 146:f64d43ff0c18 | 539 | * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. |
mbed_official | 146:f64d43ff0c18 | 540 | */ |
mbed_official | 146:f64d43ff0c18 | 541 | //@{ |
mbed_official | 146:f64d43ff0c18 | 542 | #define BP_UART_C1_M (4U) //!< Bit position for UART_C1_M. |
mbed_official | 146:f64d43ff0c18 | 543 | #define BM_UART_C1_M (0x10U) //!< Bit mask for UART_C1_M. |
mbed_official | 146:f64d43ff0c18 | 544 | #define BS_UART_C1_M (1U) //!< Bit field size in bits for UART_C1_M. |
mbed_official | 146:f64d43ff0c18 | 545 | |
mbed_official | 146:f64d43ff0c18 | 546 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 547 | //! @brief Read current value of the UART_C1_M field. |
mbed_official | 146:f64d43ff0c18 | 548 | #define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M)) |
mbed_official | 146:f64d43ff0c18 | 549 | #endif |
mbed_official | 146:f64d43ff0c18 | 550 | |
mbed_official | 146:f64d43ff0c18 | 551 | //! @brief Format value for bitfield UART_C1_M. |
mbed_official | 146:f64d43ff0c18 | 552 | #define BF_UART_C1_M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_M), uint8_t) & BM_UART_C1_M) |
mbed_official | 146:f64d43ff0c18 | 553 | |
mbed_official | 146:f64d43ff0c18 | 554 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 555 | //! @brief Set the M field to a new value. |
mbed_official | 146:f64d43ff0c18 | 556 | #define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v)) |
mbed_official | 146:f64d43ff0c18 | 557 | #endif |
mbed_official | 146:f64d43ff0c18 | 558 | //@} |
mbed_official | 146:f64d43ff0c18 | 559 | |
mbed_official | 146:f64d43ff0c18 | 560 | /*! |
mbed_official | 146:f64d43ff0c18 | 561 | * @name Register UART_C1, field RSRC[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 562 | * |
mbed_official | 146:f64d43ff0c18 | 563 | * This field has no meaning or effect unless the LOOPS field is set. When LOOPS |
mbed_official | 146:f64d43ff0c18 | 564 | * is set, the RSRC field determines the source for the receiver shift register |
mbed_official | 146:f64d43ff0c18 | 565 | * input. |
mbed_official | 146:f64d43ff0c18 | 566 | * |
mbed_official | 146:f64d43ff0c18 | 567 | * Values: |
mbed_official | 146:f64d43ff0c18 | 568 | * - 0 - Selects internal loop back mode. The receiver input is internally |
mbed_official | 146:f64d43ff0c18 | 569 | * connected to transmitter output. |
mbed_official | 146:f64d43ff0c18 | 570 | * - 1 - Single wire UART mode where the receiver input is connected to the |
mbed_official | 146:f64d43ff0c18 | 571 | * transmit pin input signal. |
mbed_official | 146:f64d43ff0c18 | 572 | */ |
mbed_official | 146:f64d43ff0c18 | 573 | //@{ |
mbed_official | 146:f64d43ff0c18 | 574 | #define BP_UART_C1_RSRC (5U) //!< Bit position for UART_C1_RSRC. |
mbed_official | 146:f64d43ff0c18 | 575 | #define BM_UART_C1_RSRC (0x20U) //!< Bit mask for UART_C1_RSRC. |
mbed_official | 146:f64d43ff0c18 | 576 | #define BS_UART_C1_RSRC (1U) //!< Bit field size in bits for UART_C1_RSRC. |
mbed_official | 146:f64d43ff0c18 | 577 | |
mbed_official | 146:f64d43ff0c18 | 578 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 579 | //! @brief Read current value of the UART_C1_RSRC field. |
mbed_official | 146:f64d43ff0c18 | 580 | #define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC)) |
mbed_official | 146:f64d43ff0c18 | 581 | #endif |
mbed_official | 146:f64d43ff0c18 | 582 | |
mbed_official | 146:f64d43ff0c18 | 583 | //! @brief Format value for bitfield UART_C1_RSRC. |
mbed_official | 146:f64d43ff0c18 | 584 | #define BF_UART_C1_RSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_RSRC), uint8_t) & BM_UART_C1_RSRC) |
mbed_official | 146:f64d43ff0c18 | 585 | |
mbed_official | 146:f64d43ff0c18 | 586 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 587 | //! @brief Set the RSRC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 588 | #define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 589 | #endif |
mbed_official | 146:f64d43ff0c18 | 590 | //@} |
mbed_official | 146:f64d43ff0c18 | 591 | |
mbed_official | 146:f64d43ff0c18 | 592 | /*! |
mbed_official | 146:f64d43ff0c18 | 593 | * @name Register UART_C1, field UARTSWAI[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 594 | * |
mbed_official | 146:f64d43ff0c18 | 595 | * Values: |
mbed_official | 146:f64d43ff0c18 | 596 | * - 0 - UART clock continues to run in Wait mode. |
mbed_official | 146:f64d43ff0c18 | 597 | * - 1 - UART clock freezes while CPU is in Wait mode. |
mbed_official | 146:f64d43ff0c18 | 598 | */ |
mbed_official | 146:f64d43ff0c18 | 599 | //@{ |
mbed_official | 146:f64d43ff0c18 | 600 | #define BP_UART_C1_UARTSWAI (6U) //!< Bit position for UART_C1_UARTSWAI. |
mbed_official | 146:f64d43ff0c18 | 601 | #define BM_UART_C1_UARTSWAI (0x40U) //!< Bit mask for UART_C1_UARTSWAI. |
mbed_official | 146:f64d43ff0c18 | 602 | #define BS_UART_C1_UARTSWAI (1U) //!< Bit field size in bits for UART_C1_UARTSWAI. |
mbed_official | 146:f64d43ff0c18 | 603 | |
mbed_official | 146:f64d43ff0c18 | 604 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 605 | //! @brief Read current value of the UART_C1_UARTSWAI field. |
mbed_official | 146:f64d43ff0c18 | 606 | #define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI)) |
mbed_official | 146:f64d43ff0c18 | 607 | #endif |
mbed_official | 146:f64d43ff0c18 | 608 | |
mbed_official | 146:f64d43ff0c18 | 609 | //! @brief Format value for bitfield UART_C1_UARTSWAI. |
mbed_official | 146:f64d43ff0c18 | 610 | #define BF_UART_C1_UARTSWAI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_UARTSWAI), uint8_t) & BM_UART_C1_UARTSWAI) |
mbed_official | 146:f64d43ff0c18 | 611 | |
mbed_official | 146:f64d43ff0c18 | 612 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 613 | //! @brief Set the UARTSWAI field to a new value. |
mbed_official | 146:f64d43ff0c18 | 614 | #define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v)) |
mbed_official | 146:f64d43ff0c18 | 615 | #endif |
mbed_official | 146:f64d43ff0c18 | 616 | //@} |
mbed_official | 146:f64d43ff0c18 | 617 | |
mbed_official | 146:f64d43ff0c18 | 618 | /*! |
mbed_official | 146:f64d43ff0c18 | 619 | * @name Register UART_C1, field LOOPS[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 620 | * |
mbed_official | 146:f64d43ff0c18 | 621 | * When LOOPS is set, the RxD pin is disconnected from the UART and the |
mbed_official | 146:f64d43ff0c18 | 622 | * transmitter output is internally connected to the receiver input. The transmitter and |
mbed_official | 146:f64d43ff0c18 | 623 | * the receiver must be enabled to use the loop function. |
mbed_official | 146:f64d43ff0c18 | 624 | * |
mbed_official | 146:f64d43ff0c18 | 625 | * Values: |
mbed_official | 146:f64d43ff0c18 | 626 | * - 0 - Normal operation. |
mbed_official | 146:f64d43ff0c18 | 627 | * - 1 - Loop mode where transmitter output is internally connected to receiver |
mbed_official | 146:f64d43ff0c18 | 628 | * input. The receiver input is determined by RSRC. |
mbed_official | 146:f64d43ff0c18 | 629 | */ |
mbed_official | 146:f64d43ff0c18 | 630 | //@{ |
mbed_official | 146:f64d43ff0c18 | 631 | #define BP_UART_C1_LOOPS (7U) //!< Bit position for UART_C1_LOOPS. |
mbed_official | 146:f64d43ff0c18 | 632 | #define BM_UART_C1_LOOPS (0x80U) //!< Bit mask for UART_C1_LOOPS. |
mbed_official | 146:f64d43ff0c18 | 633 | #define BS_UART_C1_LOOPS (1U) //!< Bit field size in bits for UART_C1_LOOPS. |
mbed_official | 146:f64d43ff0c18 | 634 | |
mbed_official | 146:f64d43ff0c18 | 635 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 636 | //! @brief Read current value of the UART_C1_LOOPS field. |
mbed_official | 146:f64d43ff0c18 | 637 | #define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS)) |
mbed_official | 146:f64d43ff0c18 | 638 | #endif |
mbed_official | 146:f64d43ff0c18 | 639 | |
mbed_official | 146:f64d43ff0c18 | 640 | //! @brief Format value for bitfield UART_C1_LOOPS. |
mbed_official | 146:f64d43ff0c18 | 641 | #define BF_UART_C1_LOOPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_LOOPS), uint8_t) & BM_UART_C1_LOOPS) |
mbed_official | 146:f64d43ff0c18 | 642 | |
mbed_official | 146:f64d43ff0c18 | 643 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 644 | //! @brief Set the LOOPS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 645 | #define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 646 | #endif |
mbed_official | 146:f64d43ff0c18 | 647 | //@} |
mbed_official | 146:f64d43ff0c18 | 648 | |
mbed_official | 146:f64d43ff0c18 | 649 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 650 | // HW_UART_C2 - UART Control Register 2 |
mbed_official | 146:f64d43ff0c18 | 651 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 652 | |
mbed_official | 146:f64d43ff0c18 | 653 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 654 | /*! |
mbed_official | 146:f64d43ff0c18 | 655 | * @brief HW_UART_C2 - UART Control Register 2 (RW) |
mbed_official | 146:f64d43ff0c18 | 656 | * |
mbed_official | 146:f64d43ff0c18 | 657 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 658 | * |
mbed_official | 146:f64d43ff0c18 | 659 | * This register can be read or written at any time. |
mbed_official | 146:f64d43ff0c18 | 660 | */ |
mbed_official | 146:f64d43ff0c18 | 661 | typedef union _hw_uart_c2 |
mbed_official | 146:f64d43ff0c18 | 662 | { |
mbed_official | 146:f64d43ff0c18 | 663 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 664 | struct _hw_uart_c2_bitfields |
mbed_official | 146:f64d43ff0c18 | 665 | { |
mbed_official | 146:f64d43ff0c18 | 666 | uint8_t SBK : 1; //!< [0] Send Break |
mbed_official | 146:f64d43ff0c18 | 667 | uint8_t RWU : 1; //!< [1] Receiver Wakeup Control |
mbed_official | 146:f64d43ff0c18 | 668 | uint8_t RE : 1; //!< [2] Receiver Enable |
mbed_official | 146:f64d43ff0c18 | 669 | uint8_t TE : 1; //!< [3] Transmitter Enable |
mbed_official | 146:f64d43ff0c18 | 670 | uint8_t ILIE : 1; //!< [4] Idle Line Interrupt DMA Transfer Enable |
mbed_official | 146:f64d43ff0c18 | 671 | uint8_t RIE : 1; //!< [5] Receiver Full Interrupt or DMA Transfer |
mbed_official | 146:f64d43ff0c18 | 672 | //! Enable |
mbed_official | 146:f64d43ff0c18 | 673 | uint8_t TCIE : 1; //!< [6] Transmission Complete Interrupt or DMA |
mbed_official | 146:f64d43ff0c18 | 674 | //! Transfer Enable |
mbed_official | 146:f64d43ff0c18 | 675 | uint8_t TIE : 1; //!< [7] Transmitter Interrupt or DMA Transfer |
mbed_official | 146:f64d43ff0c18 | 676 | //! Enable. |
mbed_official | 146:f64d43ff0c18 | 677 | } B; |
mbed_official | 146:f64d43ff0c18 | 678 | } hw_uart_c2_t; |
mbed_official | 146:f64d43ff0c18 | 679 | #endif |
mbed_official | 146:f64d43ff0c18 | 680 | |
mbed_official | 146:f64d43ff0c18 | 681 | /*! |
mbed_official | 146:f64d43ff0c18 | 682 | * @name Constants and macros for entire UART_C2 register |
mbed_official | 146:f64d43ff0c18 | 683 | */ |
mbed_official | 146:f64d43ff0c18 | 684 | //@{ |
mbed_official | 146:f64d43ff0c18 | 685 | #define HW_UART_C2_ADDR(x) (REGS_UART_BASE(x) + 0x3U) |
mbed_official | 146:f64d43ff0c18 | 686 | |
mbed_official | 146:f64d43ff0c18 | 687 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 688 | #define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 689 | #define HW_UART_C2_RD(x) (HW_UART_C2(x).U) |
mbed_official | 146:f64d43ff0c18 | 690 | #define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 691 | #define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 692 | #define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 693 | #define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 694 | #endif |
mbed_official | 146:f64d43ff0c18 | 695 | //@} |
mbed_official | 146:f64d43ff0c18 | 696 | |
mbed_official | 146:f64d43ff0c18 | 697 | /* |
mbed_official | 146:f64d43ff0c18 | 698 | * Constants & macros for individual UART_C2 bitfields |
mbed_official | 146:f64d43ff0c18 | 699 | */ |
mbed_official | 146:f64d43ff0c18 | 700 | |
mbed_official | 146:f64d43ff0c18 | 701 | /*! |
mbed_official | 146:f64d43ff0c18 | 702 | * @name Register UART_C2, field SBK[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 703 | * |
mbed_official | 146:f64d43ff0c18 | 704 | * Toggling SBK sends one break character from the following: See Transmitting |
mbed_official | 146:f64d43ff0c18 | 705 | * break characters for the number of logic 0s for the different configurations. |
mbed_official | 146:f64d43ff0c18 | 706 | * Toggling implies clearing the SBK field before the break character has finished |
mbed_official | 146:f64d43ff0c18 | 707 | * transmitting. As long as SBK is set, the transmitter continues to send |
mbed_official | 146:f64d43ff0c18 | 708 | * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits). |
mbed_official | 146:f64d43ff0c18 | 709 | * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit. |
mbed_official | 146:f64d43ff0c18 | 710 | * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13] |
mbed_official | 146:f64d43ff0c18 | 711 | * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when |
mbed_official | 146:f64d43ff0c18 | 712 | * C7816[ISO_7816E] is set. |
mbed_official | 146:f64d43ff0c18 | 713 | * |
mbed_official | 146:f64d43ff0c18 | 714 | * Values: |
mbed_official | 146:f64d43ff0c18 | 715 | * - 0 - Normal transmitter operation. |
mbed_official | 146:f64d43ff0c18 | 716 | * - 1 - Queue break characters to be sent. |
mbed_official | 146:f64d43ff0c18 | 717 | */ |
mbed_official | 146:f64d43ff0c18 | 718 | //@{ |
mbed_official | 146:f64d43ff0c18 | 719 | #define BP_UART_C2_SBK (0U) //!< Bit position for UART_C2_SBK. |
mbed_official | 146:f64d43ff0c18 | 720 | #define BM_UART_C2_SBK (0x01U) //!< Bit mask for UART_C2_SBK. |
mbed_official | 146:f64d43ff0c18 | 721 | #define BS_UART_C2_SBK (1U) //!< Bit field size in bits for UART_C2_SBK. |
mbed_official | 146:f64d43ff0c18 | 722 | |
mbed_official | 146:f64d43ff0c18 | 723 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 724 | //! @brief Read current value of the UART_C2_SBK field. |
mbed_official | 146:f64d43ff0c18 | 725 | #define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK)) |
mbed_official | 146:f64d43ff0c18 | 726 | #endif |
mbed_official | 146:f64d43ff0c18 | 727 | |
mbed_official | 146:f64d43ff0c18 | 728 | //! @brief Format value for bitfield UART_C2_SBK. |
mbed_official | 146:f64d43ff0c18 | 729 | #define BF_UART_C2_SBK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_SBK), uint8_t) & BM_UART_C2_SBK) |
mbed_official | 146:f64d43ff0c18 | 730 | |
mbed_official | 146:f64d43ff0c18 | 731 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 732 | //! @brief Set the SBK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 733 | #define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 734 | #endif |
mbed_official | 146:f64d43ff0c18 | 735 | //@} |
mbed_official | 146:f64d43ff0c18 | 736 | |
mbed_official | 146:f64d43ff0c18 | 737 | /*! |
mbed_official | 146:f64d43ff0c18 | 738 | * @name Register UART_C2, field RWU[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 739 | * |
mbed_official | 146:f64d43ff0c18 | 740 | * This field can be set to place the UART receiver in a standby state. RWU |
mbed_official | 146:f64d43ff0c18 | 741 | * automatically clears when an RWU event occurs, that is, an IDLE event when |
mbed_official | 146:f64d43ff0c18 | 742 | * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be |
mbed_official | 146:f64d43ff0c18 | 743 | * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup |
mbed_official | 146:f64d43ff0c18 | 744 | * on idle) if the channel is currently not idle. This can be determined by |
mbed_official | 146:f64d43ff0c18 | 745 | * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already |
mbed_official | 146:f64d43ff0c18 | 746 | * idle, it is possible that the UART will discard data. This is because the data |
mbed_official | 146:f64d43ff0c18 | 747 | * must be received or a LIN break detected after an IDLE is detected before IDLE |
mbed_official | 146:f64d43ff0c18 | 748 | * is allowed to reasserted. |
mbed_official | 146:f64d43ff0c18 | 749 | * |
mbed_official | 146:f64d43ff0c18 | 750 | * Values: |
mbed_official | 146:f64d43ff0c18 | 751 | * - 0 - Normal operation. |
mbed_official | 146:f64d43ff0c18 | 752 | * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt |
mbed_official | 146:f64d43ff0c18 | 753 | * requests. Normally, hardware wakes the receiver by automatically clearing |
mbed_official | 146:f64d43ff0c18 | 754 | * RWU. |
mbed_official | 146:f64d43ff0c18 | 755 | */ |
mbed_official | 146:f64d43ff0c18 | 756 | //@{ |
mbed_official | 146:f64d43ff0c18 | 757 | #define BP_UART_C2_RWU (1U) //!< Bit position for UART_C2_RWU. |
mbed_official | 146:f64d43ff0c18 | 758 | #define BM_UART_C2_RWU (0x02U) //!< Bit mask for UART_C2_RWU. |
mbed_official | 146:f64d43ff0c18 | 759 | #define BS_UART_C2_RWU (1U) //!< Bit field size in bits for UART_C2_RWU. |
mbed_official | 146:f64d43ff0c18 | 760 | |
mbed_official | 146:f64d43ff0c18 | 761 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 762 | //! @brief Read current value of the UART_C2_RWU field. |
mbed_official | 146:f64d43ff0c18 | 763 | #define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU)) |
mbed_official | 146:f64d43ff0c18 | 764 | #endif |
mbed_official | 146:f64d43ff0c18 | 765 | |
mbed_official | 146:f64d43ff0c18 | 766 | //! @brief Format value for bitfield UART_C2_RWU. |
mbed_official | 146:f64d43ff0c18 | 767 | #define BF_UART_C2_RWU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RWU), uint8_t) & BM_UART_C2_RWU) |
mbed_official | 146:f64d43ff0c18 | 768 | |
mbed_official | 146:f64d43ff0c18 | 769 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 770 | //! @brief Set the RWU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 771 | #define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v)) |
mbed_official | 146:f64d43ff0c18 | 772 | #endif |
mbed_official | 146:f64d43ff0c18 | 773 | //@} |
mbed_official | 146:f64d43ff0c18 | 774 | |
mbed_official | 146:f64d43ff0c18 | 775 | /*! |
mbed_official | 146:f64d43ff0c18 | 776 | * @name Register UART_C2, field RE[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 777 | * |
mbed_official | 146:f64d43ff0c18 | 778 | * Enables the UART receiver. |
mbed_official | 146:f64d43ff0c18 | 779 | * |
mbed_official | 146:f64d43ff0c18 | 780 | * Values: |
mbed_official | 146:f64d43ff0c18 | 781 | * - 0 - Receiver off. |
mbed_official | 146:f64d43ff0c18 | 782 | * - 1 - Receiver on. |
mbed_official | 146:f64d43ff0c18 | 783 | */ |
mbed_official | 146:f64d43ff0c18 | 784 | //@{ |
mbed_official | 146:f64d43ff0c18 | 785 | #define BP_UART_C2_RE (2U) //!< Bit position for UART_C2_RE. |
mbed_official | 146:f64d43ff0c18 | 786 | #define BM_UART_C2_RE (0x04U) //!< Bit mask for UART_C2_RE. |
mbed_official | 146:f64d43ff0c18 | 787 | #define BS_UART_C2_RE (1U) //!< Bit field size in bits for UART_C2_RE. |
mbed_official | 146:f64d43ff0c18 | 788 | |
mbed_official | 146:f64d43ff0c18 | 789 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 790 | //! @brief Read current value of the UART_C2_RE field. |
mbed_official | 146:f64d43ff0c18 | 791 | #define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE)) |
mbed_official | 146:f64d43ff0c18 | 792 | #endif |
mbed_official | 146:f64d43ff0c18 | 793 | |
mbed_official | 146:f64d43ff0c18 | 794 | //! @brief Format value for bitfield UART_C2_RE. |
mbed_official | 146:f64d43ff0c18 | 795 | #define BF_UART_C2_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RE), uint8_t) & BM_UART_C2_RE) |
mbed_official | 146:f64d43ff0c18 | 796 | |
mbed_official | 146:f64d43ff0c18 | 797 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 798 | //! @brief Set the RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 799 | #define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 800 | #endif |
mbed_official | 146:f64d43ff0c18 | 801 | //@} |
mbed_official | 146:f64d43ff0c18 | 802 | |
mbed_official | 146:f64d43ff0c18 | 803 | /*! |
mbed_official | 146:f64d43ff0c18 | 804 | * @name Register UART_C2, field TE[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 805 | * |
mbed_official | 146:f64d43ff0c18 | 806 | * Enables the UART transmitter. TE can be used to queue an idle preamble by |
mbed_official | 146:f64d43ff0c18 | 807 | * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and |
mbed_official | 146:f64d43ff0c18 | 808 | * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been |
mbed_official | 146:f64d43ff0c18 | 809 | * transmitted. This condition is detected when TL7816[TLEN] = 0 and four |
mbed_official | 146:f64d43ff0c18 | 810 | * additional characters are transmitted. |
mbed_official | 146:f64d43ff0c18 | 811 | * |
mbed_official | 146:f64d43ff0c18 | 812 | * Values: |
mbed_official | 146:f64d43ff0c18 | 813 | * - 0 - Transmitter off. |
mbed_official | 146:f64d43ff0c18 | 814 | * - 1 - Transmitter on. |
mbed_official | 146:f64d43ff0c18 | 815 | */ |
mbed_official | 146:f64d43ff0c18 | 816 | //@{ |
mbed_official | 146:f64d43ff0c18 | 817 | #define BP_UART_C2_TE (3U) //!< Bit position for UART_C2_TE. |
mbed_official | 146:f64d43ff0c18 | 818 | #define BM_UART_C2_TE (0x08U) //!< Bit mask for UART_C2_TE. |
mbed_official | 146:f64d43ff0c18 | 819 | #define BS_UART_C2_TE (1U) //!< Bit field size in bits for UART_C2_TE. |
mbed_official | 146:f64d43ff0c18 | 820 | |
mbed_official | 146:f64d43ff0c18 | 821 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 822 | //! @brief Read current value of the UART_C2_TE field. |
mbed_official | 146:f64d43ff0c18 | 823 | #define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE)) |
mbed_official | 146:f64d43ff0c18 | 824 | #endif |
mbed_official | 146:f64d43ff0c18 | 825 | |
mbed_official | 146:f64d43ff0c18 | 826 | //! @brief Format value for bitfield UART_C2_TE. |
mbed_official | 146:f64d43ff0c18 | 827 | #define BF_UART_C2_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TE), uint8_t) & BM_UART_C2_TE) |
mbed_official | 146:f64d43ff0c18 | 828 | |
mbed_official | 146:f64d43ff0c18 | 829 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 830 | //! @brief Set the TE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 831 | #define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 832 | #endif |
mbed_official | 146:f64d43ff0c18 | 833 | //@} |
mbed_official | 146:f64d43ff0c18 | 834 | |
mbed_official | 146:f64d43ff0c18 | 835 | /*! |
mbed_official | 146:f64d43ff0c18 | 836 | * @name Register UART_C2, field ILIE[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 837 | * |
mbed_official | 146:f64d43ff0c18 | 838 | * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA |
mbed_official | 146:f64d43ff0c18 | 839 | * transfer requests based on the state of C5[ILDMAS]. |
mbed_official | 146:f64d43ff0c18 | 840 | * |
mbed_official | 146:f64d43ff0c18 | 841 | * Values: |
mbed_official | 146:f64d43ff0c18 | 842 | * - 0 - IDLE interrupt requests disabled. and DMA transfer |
mbed_official | 146:f64d43ff0c18 | 843 | * - 1 - IDLE interrupt requests enabled. or DMA transfer |
mbed_official | 146:f64d43ff0c18 | 844 | */ |
mbed_official | 146:f64d43ff0c18 | 845 | //@{ |
mbed_official | 146:f64d43ff0c18 | 846 | #define BP_UART_C2_ILIE (4U) //!< Bit position for UART_C2_ILIE. |
mbed_official | 146:f64d43ff0c18 | 847 | #define BM_UART_C2_ILIE (0x10U) //!< Bit mask for UART_C2_ILIE. |
mbed_official | 146:f64d43ff0c18 | 848 | #define BS_UART_C2_ILIE (1U) //!< Bit field size in bits for UART_C2_ILIE. |
mbed_official | 146:f64d43ff0c18 | 849 | |
mbed_official | 146:f64d43ff0c18 | 850 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 851 | //! @brief Read current value of the UART_C2_ILIE field. |
mbed_official | 146:f64d43ff0c18 | 852 | #define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE)) |
mbed_official | 146:f64d43ff0c18 | 853 | #endif |
mbed_official | 146:f64d43ff0c18 | 854 | |
mbed_official | 146:f64d43ff0c18 | 855 | //! @brief Format value for bitfield UART_C2_ILIE. |
mbed_official | 146:f64d43ff0c18 | 856 | #define BF_UART_C2_ILIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_ILIE), uint8_t) & BM_UART_C2_ILIE) |
mbed_official | 146:f64d43ff0c18 | 857 | |
mbed_official | 146:f64d43ff0c18 | 858 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 859 | //! @brief Set the ILIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 860 | #define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 861 | #endif |
mbed_official | 146:f64d43ff0c18 | 862 | //@} |
mbed_official | 146:f64d43ff0c18 | 863 | |
mbed_official | 146:f64d43ff0c18 | 864 | /*! |
mbed_official | 146:f64d43ff0c18 | 865 | * @name Register UART_C2, field RIE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 866 | * |
mbed_official | 146:f64d43ff0c18 | 867 | * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, |
mbed_official | 146:f64d43ff0c18 | 868 | * based on the state of C5[RDMAS]. |
mbed_official | 146:f64d43ff0c18 | 869 | * |
mbed_official | 146:f64d43ff0c18 | 870 | * Values: |
mbed_official | 146:f64d43ff0c18 | 871 | * - 0 - RDRF interrupt and DMA transfer requests disabled. |
mbed_official | 146:f64d43ff0c18 | 872 | * - 1 - RDRF interrupt or DMA transfer requests enabled. |
mbed_official | 146:f64d43ff0c18 | 873 | */ |
mbed_official | 146:f64d43ff0c18 | 874 | //@{ |
mbed_official | 146:f64d43ff0c18 | 875 | #define BP_UART_C2_RIE (5U) //!< Bit position for UART_C2_RIE. |
mbed_official | 146:f64d43ff0c18 | 876 | #define BM_UART_C2_RIE (0x20U) //!< Bit mask for UART_C2_RIE. |
mbed_official | 146:f64d43ff0c18 | 877 | #define BS_UART_C2_RIE (1U) //!< Bit field size in bits for UART_C2_RIE. |
mbed_official | 146:f64d43ff0c18 | 878 | |
mbed_official | 146:f64d43ff0c18 | 879 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 880 | //! @brief Read current value of the UART_C2_RIE field. |
mbed_official | 146:f64d43ff0c18 | 881 | #define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE)) |
mbed_official | 146:f64d43ff0c18 | 882 | #endif |
mbed_official | 146:f64d43ff0c18 | 883 | |
mbed_official | 146:f64d43ff0c18 | 884 | //! @brief Format value for bitfield UART_C2_RIE. |
mbed_official | 146:f64d43ff0c18 | 885 | #define BF_UART_C2_RIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RIE), uint8_t) & BM_UART_C2_RIE) |
mbed_official | 146:f64d43ff0c18 | 886 | |
mbed_official | 146:f64d43ff0c18 | 887 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 888 | //! @brief Set the RIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 889 | #define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 890 | #endif |
mbed_official | 146:f64d43ff0c18 | 891 | //@} |
mbed_official | 146:f64d43ff0c18 | 892 | |
mbed_official | 146:f64d43ff0c18 | 893 | /*! |
mbed_official | 146:f64d43ff0c18 | 894 | * @name Register UART_C2, field TCIE[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 895 | * |
mbed_official | 146:f64d43ff0c18 | 896 | * Enables the transmission complete flag, S1[TC], to generate interrupt |
mbed_official | 146:f64d43ff0c18 | 897 | * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and |
mbed_official | 146:f64d43ff0c18 | 898 | * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be |
mbed_official | 146:f64d43ff0c18 | 899 | * written unless servicing a DMA request. |
mbed_official | 146:f64d43ff0c18 | 900 | * |
mbed_official | 146:f64d43ff0c18 | 901 | * Values: |
mbed_official | 146:f64d43ff0c18 | 902 | * - 0 - TC interrupt and DMA transfer requests disabled. |
mbed_official | 146:f64d43ff0c18 | 903 | * - 1 - TC interrupt or DMA transfer requests enabled. |
mbed_official | 146:f64d43ff0c18 | 904 | */ |
mbed_official | 146:f64d43ff0c18 | 905 | //@{ |
mbed_official | 146:f64d43ff0c18 | 906 | #define BP_UART_C2_TCIE (6U) //!< Bit position for UART_C2_TCIE. |
mbed_official | 146:f64d43ff0c18 | 907 | #define BM_UART_C2_TCIE (0x40U) //!< Bit mask for UART_C2_TCIE. |
mbed_official | 146:f64d43ff0c18 | 908 | #define BS_UART_C2_TCIE (1U) //!< Bit field size in bits for UART_C2_TCIE. |
mbed_official | 146:f64d43ff0c18 | 909 | |
mbed_official | 146:f64d43ff0c18 | 910 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 911 | //! @brief Read current value of the UART_C2_TCIE field. |
mbed_official | 146:f64d43ff0c18 | 912 | #define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE)) |
mbed_official | 146:f64d43ff0c18 | 913 | #endif |
mbed_official | 146:f64d43ff0c18 | 914 | |
mbed_official | 146:f64d43ff0c18 | 915 | //! @brief Format value for bitfield UART_C2_TCIE. |
mbed_official | 146:f64d43ff0c18 | 916 | #define BF_UART_C2_TCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TCIE), uint8_t) & BM_UART_C2_TCIE) |
mbed_official | 146:f64d43ff0c18 | 917 | |
mbed_official | 146:f64d43ff0c18 | 918 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 919 | //! @brief Set the TCIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 920 | #define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 921 | #endif |
mbed_official | 146:f64d43ff0c18 | 922 | //@} |
mbed_official | 146:f64d43ff0c18 | 923 | |
mbed_official | 146:f64d43ff0c18 | 924 | /*! |
mbed_official | 146:f64d43ff0c18 | 925 | * @name Register UART_C2, field TIE[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 926 | * |
mbed_official | 146:f64d43ff0c18 | 927 | * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, |
mbed_official | 146:f64d43ff0c18 | 928 | * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE |
mbed_official | 146:f64d43ff0c18 | 929 | * must be cleared, and D[D] must not be written unless servicing a DMA request. |
mbed_official | 146:f64d43ff0c18 | 930 | * |
mbed_official | 146:f64d43ff0c18 | 931 | * Values: |
mbed_official | 146:f64d43ff0c18 | 932 | * - 0 - TDRE interrupt and DMA transfer requests disabled. |
mbed_official | 146:f64d43ff0c18 | 933 | * - 1 - TDRE interrupt or DMA transfer requests enabled. |
mbed_official | 146:f64d43ff0c18 | 934 | */ |
mbed_official | 146:f64d43ff0c18 | 935 | //@{ |
mbed_official | 146:f64d43ff0c18 | 936 | #define BP_UART_C2_TIE (7U) //!< Bit position for UART_C2_TIE. |
mbed_official | 146:f64d43ff0c18 | 937 | #define BM_UART_C2_TIE (0x80U) //!< Bit mask for UART_C2_TIE. |
mbed_official | 146:f64d43ff0c18 | 938 | #define BS_UART_C2_TIE (1U) //!< Bit field size in bits for UART_C2_TIE. |
mbed_official | 146:f64d43ff0c18 | 939 | |
mbed_official | 146:f64d43ff0c18 | 940 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 941 | //! @brief Read current value of the UART_C2_TIE field. |
mbed_official | 146:f64d43ff0c18 | 942 | #define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE)) |
mbed_official | 146:f64d43ff0c18 | 943 | #endif |
mbed_official | 146:f64d43ff0c18 | 944 | |
mbed_official | 146:f64d43ff0c18 | 945 | //! @brief Format value for bitfield UART_C2_TIE. |
mbed_official | 146:f64d43ff0c18 | 946 | #define BF_UART_C2_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TIE), uint8_t) & BM_UART_C2_TIE) |
mbed_official | 146:f64d43ff0c18 | 947 | |
mbed_official | 146:f64d43ff0c18 | 948 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 949 | //! @brief Set the TIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 950 | #define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 951 | #endif |
mbed_official | 146:f64d43ff0c18 | 952 | //@} |
mbed_official | 146:f64d43ff0c18 | 953 | |
mbed_official | 146:f64d43ff0c18 | 954 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 955 | // HW_UART_S1 - UART Status Register 1 |
mbed_official | 146:f64d43ff0c18 | 956 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 957 | |
mbed_official | 146:f64d43ff0c18 | 958 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 959 | /*! |
mbed_official | 146:f64d43ff0c18 | 960 | * @brief HW_UART_S1 - UART Status Register 1 (RO) |
mbed_official | 146:f64d43ff0c18 | 961 | * |
mbed_official | 146:f64d43ff0c18 | 962 | * Reset value: 0xC0U |
mbed_official | 146:f64d43ff0c18 | 963 | * |
mbed_official | 146:f64d43ff0c18 | 964 | * The S1 register provides inputs to the MCU for generation of UART interrupts |
mbed_official | 146:f64d43ff0c18 | 965 | * or DMA requests. This register can also be polled by the MCU to check the |
mbed_official | 146:f64d43ff0c18 | 966 | * status of its fields. To clear a flag, the status register should be read followed |
mbed_official | 146:f64d43ff0c18 | 967 | * by a read or write to D register, depending on the interrupt flag type. Other |
mbed_official | 146:f64d43ff0c18 | 968 | * instructions can be executed between the two steps as long the handling of |
mbed_official | 146:f64d43ff0c18 | 969 | * I/O is not compromised, but the order of operations is important for flag |
mbed_official | 146:f64d43ff0c18 | 970 | * clearing. When a flag is configured to trigger a DMA request, assertion of the |
mbed_official | 146:f64d43ff0c18 | 971 | * associated DMA done signal from the DMA controller clears the flag. If the |
mbed_official | 146:f64d43ff0c18 | 972 | * condition that results in the assertion of the flag, interrupt, or DMA request is not |
mbed_official | 146:f64d43ff0c18 | 973 | * resolved prior to clearing the flag, the flag, and interrupt/DMA request, |
mbed_official | 146:f64d43ff0c18 | 974 | * reasserts. For example, if the DMA or interrupt service routine fails to write |
mbed_official | 146:f64d43ff0c18 | 975 | * sufficient data to the transmit buffer to raise it above the watermark level, the |
mbed_official | 146:f64d43ff0c18 | 976 | * flag reasserts and generates another interrupt or DMA request. Reading an |
mbed_official | 146:f64d43ff0c18 | 977 | * empty data register to clear one of the flags of the S1 register causes the FIFO |
mbed_official | 146:f64d43ff0c18 | 978 | * pointers to become misaligned. A receive FIFO flush reinitializes the |
mbed_official | 146:f64d43ff0c18 | 979 | * pointers. A better way to prevent this situation is to always leave one byte in FIFO |
mbed_official | 146:f64d43ff0c18 | 980 | * and this byte will be read eventually in clearing the flag bit. |
mbed_official | 146:f64d43ff0c18 | 981 | */ |
mbed_official | 146:f64d43ff0c18 | 982 | typedef union _hw_uart_s1 |
mbed_official | 146:f64d43ff0c18 | 983 | { |
mbed_official | 146:f64d43ff0c18 | 984 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 985 | struct _hw_uart_s1_bitfields |
mbed_official | 146:f64d43ff0c18 | 986 | { |
mbed_official | 146:f64d43ff0c18 | 987 | uint8_t PF : 1; //!< [0] Parity Error Flag |
mbed_official | 146:f64d43ff0c18 | 988 | uint8_t FE : 1; //!< [1] Framing Error Flag |
mbed_official | 146:f64d43ff0c18 | 989 | uint8_t NF : 1; //!< [2] Noise Flag |
mbed_official | 146:f64d43ff0c18 | 990 | uint8_t OR : 1; //!< [3] Receiver Overrun Flag |
mbed_official | 146:f64d43ff0c18 | 991 | uint8_t IDLE : 1; //!< [4] Idle Line Flag |
mbed_official | 146:f64d43ff0c18 | 992 | uint8_t RDRF : 1; //!< [5] Receive Data Register Full Flag |
mbed_official | 146:f64d43ff0c18 | 993 | uint8_t TC : 1; //!< [6] Transmit Complete Flag |
mbed_official | 146:f64d43ff0c18 | 994 | uint8_t TDRE : 1; //!< [7] Transmit Data Register Empty Flag |
mbed_official | 146:f64d43ff0c18 | 995 | } B; |
mbed_official | 146:f64d43ff0c18 | 996 | } hw_uart_s1_t; |
mbed_official | 146:f64d43ff0c18 | 997 | #endif |
mbed_official | 146:f64d43ff0c18 | 998 | |
mbed_official | 146:f64d43ff0c18 | 999 | /*! |
mbed_official | 146:f64d43ff0c18 | 1000 | * @name Constants and macros for entire UART_S1 register |
mbed_official | 146:f64d43ff0c18 | 1001 | */ |
mbed_official | 146:f64d43ff0c18 | 1002 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1003 | #define HW_UART_S1_ADDR(x) (REGS_UART_BASE(x) + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 1004 | |
mbed_official | 146:f64d43ff0c18 | 1005 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1006 | #define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 1007 | #define HW_UART_S1_RD(x) (HW_UART_S1(x).U) |
mbed_official | 146:f64d43ff0c18 | 1008 | #endif |
mbed_official | 146:f64d43ff0c18 | 1009 | //@} |
mbed_official | 146:f64d43ff0c18 | 1010 | |
mbed_official | 146:f64d43ff0c18 | 1011 | /* |
mbed_official | 146:f64d43ff0c18 | 1012 | * Constants & macros for individual UART_S1 bitfields |
mbed_official | 146:f64d43ff0c18 | 1013 | */ |
mbed_official | 146:f64d43ff0c18 | 1014 | |
mbed_official | 146:f64d43ff0c18 | 1015 | /*! |
mbed_official | 146:f64d43ff0c18 | 1016 | * @name Register UART_S1, field PF[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 1017 | * |
mbed_official | 146:f64d43ff0c18 | 1018 | * PF is set when PE is set and the parity of the received data does not match |
mbed_official | 146:f64d43ff0c18 | 1019 | * its parity bit. The PF is not set in the case of an overrun condition. When PF |
mbed_official | 146:f64d43ff0c18 | 1020 | * is set, it indicates only that a dataword was received with parity error since |
mbed_official | 146:f64d43ff0c18 | 1021 | * the last time it was cleared. There is no guarantee that the first dataword |
mbed_official | 146:f64d43ff0c18 | 1022 | * read from the receive buffer has a parity error or that there is only one |
mbed_official | 146:f64d43ff0c18 | 1023 | * dataword in the buffer that was received with a parity error, unless the receive |
mbed_official | 146:f64d43ff0c18 | 1024 | * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is |
mbed_official | 146:f64d43ff0c18 | 1025 | * disabled, Within the receive buffer structure the received dataword is tagged |
mbed_official | 146:f64d43ff0c18 | 1026 | * if it is received with a parity error. This information is available by reading |
mbed_official | 146:f64d43ff0c18 | 1027 | * the ED register prior to reading the D register. |
mbed_official | 146:f64d43ff0c18 | 1028 | * |
mbed_official | 146:f64d43ff0c18 | 1029 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1030 | * - 0 - No parity error detected since the last time this flag was cleared. If |
mbed_official | 146:f64d43ff0c18 | 1031 | * the receive buffer has a depth greater than 1, then there may be data in |
mbed_official | 146:f64d43ff0c18 | 1032 | * the receive buffer what was received with a parity error. |
mbed_official | 146:f64d43ff0c18 | 1033 | * - 1 - At least one dataword was received with a parity error since the last |
mbed_official | 146:f64d43ff0c18 | 1034 | * time this flag was cleared. |
mbed_official | 146:f64d43ff0c18 | 1035 | */ |
mbed_official | 146:f64d43ff0c18 | 1036 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1037 | #define BP_UART_S1_PF (0U) //!< Bit position for UART_S1_PF. |
mbed_official | 146:f64d43ff0c18 | 1038 | #define BM_UART_S1_PF (0x01U) //!< Bit mask for UART_S1_PF. |
mbed_official | 146:f64d43ff0c18 | 1039 | #define BS_UART_S1_PF (1U) //!< Bit field size in bits for UART_S1_PF. |
mbed_official | 146:f64d43ff0c18 | 1040 | |
mbed_official | 146:f64d43ff0c18 | 1041 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1042 | //! @brief Read current value of the UART_S1_PF field. |
mbed_official | 146:f64d43ff0c18 | 1043 | #define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF)) |
mbed_official | 146:f64d43ff0c18 | 1044 | #endif |
mbed_official | 146:f64d43ff0c18 | 1045 | //@} |
mbed_official | 146:f64d43ff0c18 | 1046 | |
mbed_official | 146:f64d43ff0c18 | 1047 | /*! |
mbed_official | 146:f64d43ff0c18 | 1048 | * @name Register UART_S1, field FE[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 1049 | * |
mbed_official | 146:f64d43ff0c18 | 1050 | * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set, |
mbed_official | 146:f64d43ff0c18 | 1051 | * then FE will set when a logic 0 is accepted for either of the two stop bits. |
mbed_official | 146:f64d43ff0c18 | 1052 | * FE does not set in the case of an overrun or while the LIN break detect feature |
mbed_official | 146:f64d43ff0c18 | 1053 | * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is |
mbed_official | 146:f64d43ff0c18 | 1054 | * cleared. To clear FE, read S1 with FE set and then read D. The last data in the |
mbed_official | 146:f64d43ff0c18 | 1055 | * receive buffer represents the data that was received with the frame error |
mbed_official | 146:f64d43ff0c18 | 1056 | * enabled. Framing errors are not supported when 7816E is set/enabled. However, if |
mbed_official | 146:f64d43ff0c18 | 1057 | * this flag is set, data is still not received in 7816 mode. |
mbed_official | 146:f64d43ff0c18 | 1058 | * |
mbed_official | 146:f64d43ff0c18 | 1059 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1060 | * - 0 - No framing error detected. |
mbed_official | 146:f64d43ff0c18 | 1061 | * - 1 - Framing error. |
mbed_official | 146:f64d43ff0c18 | 1062 | */ |
mbed_official | 146:f64d43ff0c18 | 1063 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1064 | #define BP_UART_S1_FE (1U) //!< Bit position for UART_S1_FE. |
mbed_official | 146:f64d43ff0c18 | 1065 | #define BM_UART_S1_FE (0x02U) //!< Bit mask for UART_S1_FE. |
mbed_official | 146:f64d43ff0c18 | 1066 | #define BS_UART_S1_FE (1U) //!< Bit field size in bits for UART_S1_FE. |
mbed_official | 146:f64d43ff0c18 | 1067 | |
mbed_official | 146:f64d43ff0c18 | 1068 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1069 | //! @brief Read current value of the UART_S1_FE field. |
mbed_official | 146:f64d43ff0c18 | 1070 | #define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE)) |
mbed_official | 146:f64d43ff0c18 | 1071 | #endif |
mbed_official | 146:f64d43ff0c18 | 1072 | //@} |
mbed_official | 146:f64d43ff0c18 | 1073 | |
mbed_official | 146:f64d43ff0c18 | 1074 | /*! |
mbed_official | 146:f64d43ff0c18 | 1075 | * @name Register UART_S1, field NF[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 1076 | * |
mbed_official | 146:f64d43ff0c18 | 1077 | * NF is set when the UART detects noise on the receiver input. NF does not |
mbed_official | 146:f64d43ff0c18 | 1078 | * become set in the case of an overrun or while the LIN break detect feature is |
mbed_official | 146:f64d43ff0c18 | 1079 | * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has |
mbed_official | 146:f64d43ff0c18 | 1080 | * been received with noise since the last time it was cleared. There is no |
mbed_official | 146:f64d43ff0c18 | 1081 | * guarantee that the first dataword read from the receive buffer has noise or that there |
mbed_official | 146:f64d43ff0c18 | 1082 | * is only one dataword in the buffer that was received with noise unless the |
mbed_official | 146:f64d43ff0c18 | 1083 | * receive buffer has a depth of one. To clear NF, read S1 and then read D. |
mbed_official | 146:f64d43ff0c18 | 1084 | * |
mbed_official | 146:f64d43ff0c18 | 1085 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1086 | * - 0 - No noise detected since the last time this flag was cleared. If the |
mbed_official | 146:f64d43ff0c18 | 1087 | * receive buffer has a depth greater than 1 then there may be data in the |
mbed_official | 146:f64d43ff0c18 | 1088 | * receiver buffer that was received with noise. |
mbed_official | 146:f64d43ff0c18 | 1089 | * - 1 - At least one dataword was received with noise detected since the last |
mbed_official | 146:f64d43ff0c18 | 1090 | * time the flag was cleared. |
mbed_official | 146:f64d43ff0c18 | 1091 | */ |
mbed_official | 146:f64d43ff0c18 | 1092 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1093 | #define BP_UART_S1_NF (2U) //!< Bit position for UART_S1_NF. |
mbed_official | 146:f64d43ff0c18 | 1094 | #define BM_UART_S1_NF (0x04U) //!< Bit mask for UART_S1_NF. |
mbed_official | 146:f64d43ff0c18 | 1095 | #define BS_UART_S1_NF (1U) //!< Bit field size in bits for UART_S1_NF. |
mbed_official | 146:f64d43ff0c18 | 1096 | |
mbed_official | 146:f64d43ff0c18 | 1097 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1098 | //! @brief Read current value of the UART_S1_NF field. |
mbed_official | 146:f64d43ff0c18 | 1099 | #define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF)) |
mbed_official | 146:f64d43ff0c18 | 1100 | #endif |
mbed_official | 146:f64d43ff0c18 | 1101 | //@} |
mbed_official | 146:f64d43ff0c18 | 1102 | |
mbed_official | 146:f64d43ff0c18 | 1103 | /*! |
mbed_official | 146:f64d43ff0c18 | 1104 | * @name Register UART_S1, field OR[3] (RO) |
mbed_official | 146:f64d43ff0c18 | 1105 | * |
mbed_official | 146:f64d43ff0c18 | 1106 | * OR is set when software fails to prevent the receive data register from |
mbed_official | 146:f64d43ff0c18 | 1107 | * overflowing with data. The OR bit is set immediately after the stop bit has been |
mbed_official | 146:f64d43ff0c18 | 1108 | * completely received for the dataword that overflows the buffer and all the other |
mbed_official | 146:f64d43ff0c18 | 1109 | * error flags (FE, NF, and PF) are prevented from setting. The data in the |
mbed_official | 146:f64d43ff0c18 | 1110 | * shift register is lost, but the data already in the UART data registers is not |
mbed_official | 146:f64d43ff0c18 | 1111 | * affected. If the OR flag is set, no data is stored in the data buffer even if |
mbed_official | 146:f64d43ff0c18 | 1112 | * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE |
mbed_official | 146:f64d43ff0c18 | 1113 | * flags are blocked from asserting, that is, transition from an inactive to an |
mbed_official | 146:f64d43ff0c18 | 1114 | * active state. To clear OR, read S1 when OR is set and then read D. See |
mbed_official | 146:f64d43ff0c18 | 1115 | * functional description for more details regarding the operation of the OR bit.If |
mbed_official | 146:f64d43ff0c18 | 1116 | * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF] |
mbed_official | 146:f64d43ff0c18 | 1117 | * is not cleared before the next data character is received. In 7816 mode, it is |
mbed_official | 146:f64d43ff0c18 | 1118 | * possible to configure a NACK to be returned by programing C7816[ONACK]. |
mbed_official | 146:f64d43ff0c18 | 1119 | * |
mbed_official | 146:f64d43ff0c18 | 1120 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1121 | * - 0 - No overrun has occurred since the last time the flag was cleared. |
mbed_official | 146:f64d43ff0c18 | 1122 | * - 1 - Overrun has occurred or the overrun flag has not been cleared since the |
mbed_official | 146:f64d43ff0c18 | 1123 | * last overrun occured. |
mbed_official | 146:f64d43ff0c18 | 1124 | */ |
mbed_official | 146:f64d43ff0c18 | 1125 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1126 | #define BP_UART_S1_OR (3U) //!< Bit position for UART_S1_OR. |
mbed_official | 146:f64d43ff0c18 | 1127 | #define BM_UART_S1_OR (0x08U) //!< Bit mask for UART_S1_OR. |
mbed_official | 146:f64d43ff0c18 | 1128 | #define BS_UART_S1_OR (1U) //!< Bit field size in bits for UART_S1_OR. |
mbed_official | 146:f64d43ff0c18 | 1129 | |
mbed_official | 146:f64d43ff0c18 | 1130 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1131 | //! @brief Read current value of the UART_S1_OR field. |
mbed_official | 146:f64d43ff0c18 | 1132 | #define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR)) |
mbed_official | 146:f64d43ff0c18 | 1133 | #endif |
mbed_official | 146:f64d43ff0c18 | 1134 | //@} |
mbed_official | 146:f64d43ff0c18 | 1135 | |
mbed_official | 146:f64d43ff0c18 | 1136 | /*! |
mbed_official | 146:f64d43ff0c18 | 1137 | * @name Register UART_S1, field IDLE[4] (RO) |
mbed_official | 146:f64d43ff0c18 | 1138 | * |
mbed_official | 146:f64d43ff0c18 | 1139 | * After the IDLE flag is cleared, a frame must be received (although not |
mbed_official | 146:f64d43ff0c18 | 1140 | * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN |
mbed_official | 146:f64d43ff0c18 | 1141 | * break character must set the S2[LBKDIF] flag before an idle condition can set the |
mbed_official | 146:f64d43ff0c18 | 1142 | * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D. |
mbed_official | 146:f64d43ff0c18 | 1143 | * IDLE is set when either of the following appear on the receiver input: 10 |
mbed_official | 146:f64d43ff0c18 | 1144 | * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10] |
mbed_official | 146:f64d43ff0c18 | 1145 | * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle |
mbed_official | 146:f64d43ff0c18 | 1146 | * detection is not supported when 7816E is set/enabled and hence this flag is |
mbed_official | 146:f64d43ff0c18 | 1147 | * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE |
mbed_official | 146:f64d43ff0c18 | 1148 | * flag if RWUID is set, else the IDLE flag does not become set. |
mbed_official | 146:f64d43ff0c18 | 1149 | * |
mbed_official | 146:f64d43ff0c18 | 1150 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1151 | * - 0 - Receiver input is either active now or has never become active since |
mbed_official | 146:f64d43ff0c18 | 1152 | * the IDLE flag was last cleared. |
mbed_official | 146:f64d43ff0c18 | 1153 | * - 1 - Receiver input has become idle or the flag has not been cleared since |
mbed_official | 146:f64d43ff0c18 | 1154 | * it last asserted. |
mbed_official | 146:f64d43ff0c18 | 1155 | */ |
mbed_official | 146:f64d43ff0c18 | 1156 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1157 | #define BP_UART_S1_IDLE (4U) //!< Bit position for UART_S1_IDLE. |
mbed_official | 146:f64d43ff0c18 | 1158 | #define BM_UART_S1_IDLE (0x10U) //!< Bit mask for UART_S1_IDLE. |
mbed_official | 146:f64d43ff0c18 | 1159 | #define BS_UART_S1_IDLE (1U) //!< Bit field size in bits for UART_S1_IDLE. |
mbed_official | 146:f64d43ff0c18 | 1160 | |
mbed_official | 146:f64d43ff0c18 | 1161 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1162 | //! @brief Read current value of the UART_S1_IDLE field. |
mbed_official | 146:f64d43ff0c18 | 1163 | #define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE)) |
mbed_official | 146:f64d43ff0c18 | 1164 | #endif |
mbed_official | 146:f64d43ff0c18 | 1165 | //@} |
mbed_official | 146:f64d43ff0c18 | 1166 | |
mbed_official | 146:f64d43ff0c18 | 1167 | /*! |
mbed_official | 146:f64d43ff0c18 | 1168 | * @name Register UART_S1, field RDRF[5] (RO) |
mbed_official | 146:f64d43ff0c18 | 1169 | * |
mbed_official | 146:f64d43ff0c18 | 1170 | * RDRF is set when the number of datawords in the receive buffer is equal to or |
mbed_official | 146:f64d43ff0c18 | 1171 | * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the |
mbed_official | 146:f64d43ff0c18 | 1172 | * process of being received is not included in the count. To clear RDRF, read S1 |
mbed_official | 146:f64d43ff0c18 | 1173 | * when RDRF is set and then read D. For more efficient interrupt and DMA |
mbed_official | 146:f64d43ff0c18 | 1174 | * operation, read all data except the final value from the buffer, using D/C3[T8]/ED. |
mbed_official | 146:f64d43ff0c18 | 1175 | * Then read S1 and the final data value, resulting in the clearing of the RDRF |
mbed_official | 146:f64d43ff0c18 | 1176 | * flag. Even if RDRF is set, data will continue to be received until an overrun |
mbed_official | 146:f64d43ff0c18 | 1177 | * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set. |
mbed_official | 146:f64d43ff0c18 | 1178 | * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive |
mbed_official | 146:f64d43ff0c18 | 1179 | * buffer but over-write each other. |
mbed_official | 146:f64d43ff0c18 | 1180 | * |
mbed_official | 146:f64d43ff0c18 | 1181 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1182 | * - 0 - The number of datawords in the receive buffer is less than the number |
mbed_official | 146:f64d43ff0c18 | 1183 | * indicated by RXWATER. |
mbed_official | 146:f64d43ff0c18 | 1184 | * - 1 - The number of datawords in the receive buffer is equal to or greater |
mbed_official | 146:f64d43ff0c18 | 1185 | * than the number indicated by RXWATER at some point in time since this flag |
mbed_official | 146:f64d43ff0c18 | 1186 | * was last cleared. |
mbed_official | 146:f64d43ff0c18 | 1187 | */ |
mbed_official | 146:f64d43ff0c18 | 1188 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1189 | #define BP_UART_S1_RDRF (5U) //!< Bit position for UART_S1_RDRF. |
mbed_official | 146:f64d43ff0c18 | 1190 | #define BM_UART_S1_RDRF (0x20U) //!< Bit mask for UART_S1_RDRF. |
mbed_official | 146:f64d43ff0c18 | 1191 | #define BS_UART_S1_RDRF (1U) //!< Bit field size in bits for UART_S1_RDRF. |
mbed_official | 146:f64d43ff0c18 | 1192 | |
mbed_official | 146:f64d43ff0c18 | 1193 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1194 | //! @brief Read current value of the UART_S1_RDRF field. |
mbed_official | 146:f64d43ff0c18 | 1195 | #define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF)) |
mbed_official | 146:f64d43ff0c18 | 1196 | #endif |
mbed_official | 146:f64d43ff0c18 | 1197 | //@} |
mbed_official | 146:f64d43ff0c18 | 1198 | |
mbed_official | 146:f64d43ff0c18 | 1199 | /*! |
mbed_official | 146:f64d43ff0c18 | 1200 | * @name Register UART_S1, field TC[6] (RO) |
mbed_official | 146:f64d43ff0c18 | 1201 | * |
mbed_official | 146:f64d43ff0c18 | 1202 | * TC is set when the transmit buffer is empty and no data, preamble, or break |
mbed_official | 146:f64d43ff0c18 | 1203 | * character is being transmitted. When TC is set, the transmit data output signal |
mbed_official | 146:f64d43ff0c18 | 1204 | * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then |
mbed_official | 146:f64d43ff0c18 | 1205 | * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is |
mbed_official | 146:f64d43ff0c18 | 1206 | * set after any NACK signal has been received, but prior to any corresponding |
mbed_official | 146:f64d43ff0c18 | 1207 | * guard times expiring. Writing to D to transmit new data. Queuing a preamble by |
mbed_official | 146:f64d43ff0c18 | 1208 | * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK |
mbed_official | 146:f64d43ff0c18 | 1209 | * in C2. |
mbed_official | 146:f64d43ff0c18 | 1210 | * |
mbed_official | 146:f64d43ff0c18 | 1211 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1212 | * - 0 - Transmitter active (sending data, a preamble, or a break). |
mbed_official | 146:f64d43ff0c18 | 1213 | * - 1 - Transmitter idle (transmission activity complete). |
mbed_official | 146:f64d43ff0c18 | 1214 | */ |
mbed_official | 146:f64d43ff0c18 | 1215 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1216 | #define BP_UART_S1_TC (6U) //!< Bit position for UART_S1_TC. |
mbed_official | 146:f64d43ff0c18 | 1217 | #define BM_UART_S1_TC (0x40U) //!< Bit mask for UART_S1_TC. |
mbed_official | 146:f64d43ff0c18 | 1218 | #define BS_UART_S1_TC (1U) //!< Bit field size in bits for UART_S1_TC. |
mbed_official | 146:f64d43ff0c18 | 1219 | |
mbed_official | 146:f64d43ff0c18 | 1220 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1221 | //! @brief Read current value of the UART_S1_TC field. |
mbed_official | 146:f64d43ff0c18 | 1222 | #define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC)) |
mbed_official | 146:f64d43ff0c18 | 1223 | #endif |
mbed_official | 146:f64d43ff0c18 | 1224 | //@} |
mbed_official | 146:f64d43ff0c18 | 1225 | |
mbed_official | 146:f64d43ff0c18 | 1226 | /*! |
mbed_official | 146:f64d43ff0c18 | 1227 | * @name Register UART_S1, field TDRE[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 1228 | * |
mbed_official | 146:f64d43ff0c18 | 1229 | * TDRE will set when the number of datawords in the transmit buffer (D and |
mbed_official | 146:f64d43ff0c18 | 1230 | * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A |
mbed_official | 146:f64d43ff0c18 | 1231 | * character that is in the process of being transmitted is not included in the count. |
mbed_official | 146:f64d43ff0c18 | 1232 | * To clear TDRE, read S1 when TDRE is set and then write to the UART data |
mbed_official | 146:f64d43ff0c18 | 1233 | * register (D). For more efficient interrupt servicing, all data except the final value |
mbed_official | 146:f64d43ff0c18 | 1234 | * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read |
mbed_official | 146:f64d43ff0c18 | 1235 | * before writing the final data value, resulting in the clearing of the TRDE |
mbed_official | 146:f64d43ff0c18 | 1236 | * flag. This is more efficient because the TDRE reasserts until the watermark has |
mbed_official | 146:f64d43ff0c18 | 1237 | * been exceeded. So, attempting to clear the TDRE with every write will be |
mbed_official | 146:f64d43ff0c18 | 1238 | * ineffective until sufficient data has been written. |
mbed_official | 146:f64d43ff0c18 | 1239 | * |
mbed_official | 146:f64d43ff0c18 | 1240 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1241 | * - 0 - The amount of data in the transmit buffer is greater than the value |
mbed_official | 146:f64d43ff0c18 | 1242 | * indicated by TWFIFO[TXWATER]. |
mbed_official | 146:f64d43ff0c18 | 1243 | * - 1 - The amount of data in the transmit buffer is less than or equal to the |
mbed_official | 146:f64d43ff0c18 | 1244 | * value indicated by TWFIFO[TXWATER] at some point in time since the flag |
mbed_official | 146:f64d43ff0c18 | 1245 | * has been cleared. |
mbed_official | 146:f64d43ff0c18 | 1246 | */ |
mbed_official | 146:f64d43ff0c18 | 1247 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1248 | #define BP_UART_S1_TDRE (7U) //!< Bit position for UART_S1_TDRE. |
mbed_official | 146:f64d43ff0c18 | 1249 | #define BM_UART_S1_TDRE (0x80U) //!< Bit mask for UART_S1_TDRE. |
mbed_official | 146:f64d43ff0c18 | 1250 | #define BS_UART_S1_TDRE (1U) //!< Bit field size in bits for UART_S1_TDRE. |
mbed_official | 146:f64d43ff0c18 | 1251 | |
mbed_official | 146:f64d43ff0c18 | 1252 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1253 | //! @brief Read current value of the UART_S1_TDRE field. |
mbed_official | 146:f64d43ff0c18 | 1254 | #define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE)) |
mbed_official | 146:f64d43ff0c18 | 1255 | #endif |
mbed_official | 146:f64d43ff0c18 | 1256 | //@} |
mbed_official | 146:f64d43ff0c18 | 1257 | |
mbed_official | 146:f64d43ff0c18 | 1258 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1259 | // HW_UART_S2 - UART Status Register 2 |
mbed_official | 146:f64d43ff0c18 | 1260 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1261 | |
mbed_official | 146:f64d43ff0c18 | 1262 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1263 | /*! |
mbed_official | 146:f64d43ff0c18 | 1264 | * @brief HW_UART_S2 - UART Status Register 2 (RW) |
mbed_official | 146:f64d43ff0c18 | 1265 | * |
mbed_official | 146:f64d43ff0c18 | 1266 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1267 | * |
mbed_official | 146:f64d43ff0c18 | 1268 | * The S2 register provides inputs to the MCU for generation of UART interrupts |
mbed_official | 146:f64d43ff0c18 | 1269 | * or DMA requests. Also, this register can be polled by the MCU to check the |
mbed_official | 146:f64d43ff0c18 | 1270 | * status of these bits. This register can be read or written at any time, with the |
mbed_official | 146:f64d43ff0c18 | 1271 | * exception of the MSBF and RXINV bits, which should be changed by the user only |
mbed_official | 146:f64d43ff0c18 | 1272 | * between transmit and receive packets. |
mbed_official | 146:f64d43ff0c18 | 1273 | */ |
mbed_official | 146:f64d43ff0c18 | 1274 | typedef union _hw_uart_s2 |
mbed_official | 146:f64d43ff0c18 | 1275 | { |
mbed_official | 146:f64d43ff0c18 | 1276 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1277 | struct _hw_uart_s2_bitfields |
mbed_official | 146:f64d43ff0c18 | 1278 | { |
mbed_official | 146:f64d43ff0c18 | 1279 | uint8_t RAF : 1; //!< [0] Receiver Active Flag |
mbed_official | 146:f64d43ff0c18 | 1280 | uint8_t LBKDE : 1; //!< [1] LIN Break Detection Enable |
mbed_official | 146:f64d43ff0c18 | 1281 | uint8_t BRK13 : 1; //!< [2] Break Transmit Character Length |
mbed_official | 146:f64d43ff0c18 | 1282 | uint8_t RWUID : 1; //!< [3] Receive Wakeup Idle Detect |
mbed_official | 146:f64d43ff0c18 | 1283 | uint8_t RXINV : 1; //!< [4] Receive Data Inversion |
mbed_official | 146:f64d43ff0c18 | 1284 | uint8_t MSBF : 1; //!< [5] Most Significant Bit First |
mbed_official | 146:f64d43ff0c18 | 1285 | uint8_t RXEDGIF : 1; //!< [6] RxD Pin Active Edge Interrupt Flag |
mbed_official | 146:f64d43ff0c18 | 1286 | uint8_t LBKDIF : 1; //!< [7] LIN Break Detect Interrupt Flag |
mbed_official | 146:f64d43ff0c18 | 1287 | } B; |
mbed_official | 146:f64d43ff0c18 | 1288 | } hw_uart_s2_t; |
mbed_official | 146:f64d43ff0c18 | 1289 | #endif |
mbed_official | 146:f64d43ff0c18 | 1290 | |
mbed_official | 146:f64d43ff0c18 | 1291 | /*! |
mbed_official | 146:f64d43ff0c18 | 1292 | * @name Constants and macros for entire UART_S2 register |
mbed_official | 146:f64d43ff0c18 | 1293 | */ |
mbed_official | 146:f64d43ff0c18 | 1294 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1295 | #define HW_UART_S2_ADDR(x) (REGS_UART_BASE(x) + 0x5U) |
mbed_official | 146:f64d43ff0c18 | 1296 | |
mbed_official | 146:f64d43ff0c18 | 1297 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1298 | #define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 1299 | #define HW_UART_S2_RD(x) (HW_UART_S2(x).U) |
mbed_official | 146:f64d43ff0c18 | 1300 | #define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1301 | #define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1302 | #define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1303 | #define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1304 | #endif |
mbed_official | 146:f64d43ff0c18 | 1305 | //@} |
mbed_official | 146:f64d43ff0c18 | 1306 | |
mbed_official | 146:f64d43ff0c18 | 1307 | /* |
mbed_official | 146:f64d43ff0c18 | 1308 | * Constants & macros for individual UART_S2 bitfields |
mbed_official | 146:f64d43ff0c18 | 1309 | */ |
mbed_official | 146:f64d43ff0c18 | 1310 | |
mbed_official | 146:f64d43ff0c18 | 1311 | /*! |
mbed_official | 146:f64d43ff0c18 | 1312 | * @name Register UART_S2, field RAF[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 1313 | * |
mbed_official | 146:f64d43ff0c18 | 1314 | * RAF is set when the UART receiver detects a logic 0 during the RT1 time |
mbed_official | 146:f64d43ff0c18 | 1315 | * period of the start bit search. RAF is cleared when the receiver detects an idle |
mbed_official | 146:f64d43ff0c18 | 1316 | * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is |
mbed_official | 146:f64d43ff0c18 | 1317 | * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] = |
mbed_official | 146:f64d43ff0c18 | 1318 | * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible |
mbed_official | 146:f64d43ff0c18 | 1319 | * to configure the guard time to 12. However, if a NACK is required to be |
mbed_official | 146:f64d43ff0c18 | 1320 | * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a |
mbed_official | 146:f64d43ff0c18 | 1321 | * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU |
mbed_official | 146:f64d43ff0c18 | 1322 | * prior to actually being inactive. |
mbed_official | 146:f64d43ff0c18 | 1323 | * |
mbed_official | 146:f64d43ff0c18 | 1324 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1325 | * - 0 - UART receiver idle/inactive waiting for a start bit. |
mbed_official | 146:f64d43ff0c18 | 1326 | * - 1 - UART receiver active, RxD input not idle. |
mbed_official | 146:f64d43ff0c18 | 1327 | */ |
mbed_official | 146:f64d43ff0c18 | 1328 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1329 | #define BP_UART_S2_RAF (0U) //!< Bit position for UART_S2_RAF. |
mbed_official | 146:f64d43ff0c18 | 1330 | #define BM_UART_S2_RAF (0x01U) //!< Bit mask for UART_S2_RAF. |
mbed_official | 146:f64d43ff0c18 | 1331 | #define BS_UART_S2_RAF (1U) //!< Bit field size in bits for UART_S2_RAF. |
mbed_official | 146:f64d43ff0c18 | 1332 | |
mbed_official | 146:f64d43ff0c18 | 1333 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1334 | //! @brief Read current value of the UART_S2_RAF field. |
mbed_official | 146:f64d43ff0c18 | 1335 | #define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF)) |
mbed_official | 146:f64d43ff0c18 | 1336 | #endif |
mbed_official | 146:f64d43ff0c18 | 1337 | //@} |
mbed_official | 146:f64d43ff0c18 | 1338 | |
mbed_official | 146:f64d43ff0c18 | 1339 | /*! |
mbed_official | 146:f64d43ff0c18 | 1340 | * @name Register UART_S2, field LBKDE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1341 | * |
mbed_official | 146:f64d43ff0c18 | 1342 | * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF], |
mbed_official | 146:f64d43ff0c18 | 1343 | * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see . |
mbed_official | 146:f64d43ff0c18 | 1344 | * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set. |
mbed_official | 146:f64d43ff0c18 | 1345 | * |
mbed_official | 146:f64d43ff0c18 | 1346 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1347 | * - 0 - Break character detection is disabled. |
mbed_official | 146:f64d43ff0c18 | 1348 | * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or |
mbed_official | 146:f64d43ff0c18 | 1349 | * 12 bits time if C1[M] = 1. |
mbed_official | 146:f64d43ff0c18 | 1350 | */ |
mbed_official | 146:f64d43ff0c18 | 1351 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1352 | #define BP_UART_S2_LBKDE (1U) //!< Bit position for UART_S2_LBKDE. |
mbed_official | 146:f64d43ff0c18 | 1353 | #define BM_UART_S2_LBKDE (0x02U) //!< Bit mask for UART_S2_LBKDE. |
mbed_official | 146:f64d43ff0c18 | 1354 | #define BS_UART_S2_LBKDE (1U) //!< Bit field size in bits for UART_S2_LBKDE. |
mbed_official | 146:f64d43ff0c18 | 1355 | |
mbed_official | 146:f64d43ff0c18 | 1356 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1357 | //! @brief Read current value of the UART_S2_LBKDE field. |
mbed_official | 146:f64d43ff0c18 | 1358 | #define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE)) |
mbed_official | 146:f64d43ff0c18 | 1359 | #endif |
mbed_official | 146:f64d43ff0c18 | 1360 | |
mbed_official | 146:f64d43ff0c18 | 1361 | //! @brief Format value for bitfield UART_S2_LBKDE. |
mbed_official | 146:f64d43ff0c18 | 1362 | #define BF_UART_S2_LBKDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDE), uint8_t) & BM_UART_S2_LBKDE) |
mbed_official | 146:f64d43ff0c18 | 1363 | |
mbed_official | 146:f64d43ff0c18 | 1364 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1365 | //! @brief Set the LBKDE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1366 | #define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1367 | #endif |
mbed_official | 146:f64d43ff0c18 | 1368 | //@} |
mbed_official | 146:f64d43ff0c18 | 1369 | |
mbed_official | 146:f64d43ff0c18 | 1370 | /*! |
mbed_official | 146:f64d43ff0c18 | 1371 | * @name Register UART_S2, field BRK13[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1372 | * |
mbed_official | 146:f64d43ff0c18 | 1373 | * Determines whether the transmit break character is 10, 11, or 12 bits long, |
mbed_official | 146:f64d43ff0c18 | 1374 | * or 13 or 14 bits long. See for the length of the break character for the |
mbed_official | 146:f64d43ff0c18 | 1375 | * different configurations. The detection of a framing error is not affected by this |
mbed_official | 146:f64d43ff0c18 | 1376 | * field. Transmitting break characters |
mbed_official | 146:f64d43ff0c18 | 1377 | * |
mbed_official | 146:f64d43ff0c18 | 1378 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1379 | * - 0 - Break character is 10, 11, or 12 bits long. |
mbed_official | 146:f64d43ff0c18 | 1380 | * - 1 - Break character is 13 or 14 bits long. |
mbed_official | 146:f64d43ff0c18 | 1381 | */ |
mbed_official | 146:f64d43ff0c18 | 1382 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1383 | #define BP_UART_S2_BRK13 (2U) //!< Bit position for UART_S2_BRK13. |
mbed_official | 146:f64d43ff0c18 | 1384 | #define BM_UART_S2_BRK13 (0x04U) //!< Bit mask for UART_S2_BRK13. |
mbed_official | 146:f64d43ff0c18 | 1385 | #define BS_UART_S2_BRK13 (1U) //!< Bit field size in bits for UART_S2_BRK13. |
mbed_official | 146:f64d43ff0c18 | 1386 | |
mbed_official | 146:f64d43ff0c18 | 1387 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1388 | //! @brief Read current value of the UART_S2_BRK13 field. |
mbed_official | 146:f64d43ff0c18 | 1389 | #define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13)) |
mbed_official | 146:f64d43ff0c18 | 1390 | #endif |
mbed_official | 146:f64d43ff0c18 | 1391 | |
mbed_official | 146:f64d43ff0c18 | 1392 | //! @brief Format value for bitfield UART_S2_BRK13. |
mbed_official | 146:f64d43ff0c18 | 1393 | #define BF_UART_S2_BRK13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_BRK13), uint8_t) & BM_UART_S2_BRK13) |
mbed_official | 146:f64d43ff0c18 | 1394 | |
mbed_official | 146:f64d43ff0c18 | 1395 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1396 | //! @brief Set the BRK13 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1397 | #define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1398 | #endif |
mbed_official | 146:f64d43ff0c18 | 1399 | //@} |
mbed_official | 146:f64d43ff0c18 | 1400 | |
mbed_official | 146:f64d43ff0c18 | 1401 | /*! |
mbed_official | 146:f64d43ff0c18 | 1402 | * @name Register UART_S2, field RWUID[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 1403 | * |
mbed_official | 146:f64d43ff0c18 | 1404 | * When RWU is set and WAKE is cleared, this field controls whether the idle |
mbed_official | 146:f64d43ff0c18 | 1405 | * character that wakes the receiver sets S1[IDLE]. This field must be cleared when |
mbed_official | 146:f64d43ff0c18 | 1406 | * C7816[ISO7816E] is set/enabled. |
mbed_official | 146:f64d43ff0c18 | 1407 | * |
mbed_official | 146:f64d43ff0c18 | 1408 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1409 | * - 0 - S1[IDLE] is not set upon detection of an idle character. |
mbed_official | 146:f64d43ff0c18 | 1410 | * - 1 - S1[IDLE] is set upon detection of an idle character. |
mbed_official | 146:f64d43ff0c18 | 1411 | */ |
mbed_official | 146:f64d43ff0c18 | 1412 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1413 | #define BP_UART_S2_RWUID (3U) //!< Bit position for UART_S2_RWUID. |
mbed_official | 146:f64d43ff0c18 | 1414 | #define BM_UART_S2_RWUID (0x08U) //!< Bit mask for UART_S2_RWUID. |
mbed_official | 146:f64d43ff0c18 | 1415 | #define BS_UART_S2_RWUID (1U) //!< Bit field size in bits for UART_S2_RWUID. |
mbed_official | 146:f64d43ff0c18 | 1416 | |
mbed_official | 146:f64d43ff0c18 | 1417 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1418 | //! @brief Read current value of the UART_S2_RWUID field. |
mbed_official | 146:f64d43ff0c18 | 1419 | #define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID)) |
mbed_official | 146:f64d43ff0c18 | 1420 | #endif |
mbed_official | 146:f64d43ff0c18 | 1421 | |
mbed_official | 146:f64d43ff0c18 | 1422 | //! @brief Format value for bitfield UART_S2_RWUID. |
mbed_official | 146:f64d43ff0c18 | 1423 | #define BF_UART_S2_RWUID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RWUID), uint8_t) & BM_UART_S2_RWUID) |
mbed_official | 146:f64d43ff0c18 | 1424 | |
mbed_official | 146:f64d43ff0c18 | 1425 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1426 | //! @brief Set the RWUID field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1427 | #define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1428 | #endif |
mbed_official | 146:f64d43ff0c18 | 1429 | //@} |
mbed_official | 146:f64d43ff0c18 | 1430 | |
mbed_official | 146:f64d43ff0c18 | 1431 | /*! |
mbed_official | 146:f64d43ff0c18 | 1432 | * @name Register UART_S2, field RXINV[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1433 | * |
mbed_official | 146:f64d43ff0c18 | 1434 | * Setting this field reverses the polarity of the received data input. In NRZ |
mbed_official | 146:f64d43ff0c18 | 1435 | * format, a one is represented by a mark and a zero is represented by a space for |
mbed_official | 146:f64d43ff0c18 | 1436 | * normal polarity, and the opposite for inverted polarity. In IrDA format, a |
mbed_official | 146:f64d43ff0c18 | 1437 | * zero is represented by short high pulse in the middle of a bit time remaining |
mbed_official | 146:f64d43ff0c18 | 1438 | * idle low for a one for normal polarity. A zero is represented by a short low |
mbed_official | 146:f64d43ff0c18 | 1439 | * pulse in the middle of a bit time remaining idle high for a one for inverted |
mbed_official | 146:f64d43ff0c18 | 1440 | * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are |
mbed_official | 146:f64d43ff0c18 | 1441 | * enabled and an initial character is detected in T = 0 protocol mode. Setting |
mbed_official | 146:f64d43ff0c18 | 1442 | * RXINV inverts the RxD input for data bits, start and stop bits, break, and |
mbed_official | 146:f64d43ff0c18 | 1443 | * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit |
mbed_official | 146:f64d43ff0c18 | 1444 | * are inverted. |
mbed_official | 146:f64d43ff0c18 | 1445 | * |
mbed_official | 146:f64d43ff0c18 | 1446 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1447 | * - 0 - Receive data is not inverted. |
mbed_official | 146:f64d43ff0c18 | 1448 | * - 1 - Receive data is inverted. |
mbed_official | 146:f64d43ff0c18 | 1449 | */ |
mbed_official | 146:f64d43ff0c18 | 1450 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1451 | #define BP_UART_S2_RXINV (4U) //!< Bit position for UART_S2_RXINV. |
mbed_official | 146:f64d43ff0c18 | 1452 | #define BM_UART_S2_RXINV (0x10U) //!< Bit mask for UART_S2_RXINV. |
mbed_official | 146:f64d43ff0c18 | 1453 | #define BS_UART_S2_RXINV (1U) //!< Bit field size in bits for UART_S2_RXINV. |
mbed_official | 146:f64d43ff0c18 | 1454 | |
mbed_official | 146:f64d43ff0c18 | 1455 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1456 | //! @brief Read current value of the UART_S2_RXINV field. |
mbed_official | 146:f64d43ff0c18 | 1457 | #define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV)) |
mbed_official | 146:f64d43ff0c18 | 1458 | #endif |
mbed_official | 146:f64d43ff0c18 | 1459 | |
mbed_official | 146:f64d43ff0c18 | 1460 | //! @brief Format value for bitfield UART_S2_RXINV. |
mbed_official | 146:f64d43ff0c18 | 1461 | #define BF_UART_S2_RXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXINV), uint8_t) & BM_UART_S2_RXINV) |
mbed_official | 146:f64d43ff0c18 | 1462 | |
mbed_official | 146:f64d43ff0c18 | 1463 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1464 | //! @brief Set the RXINV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1465 | #define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1466 | #endif |
mbed_official | 146:f64d43ff0c18 | 1467 | //@} |
mbed_official | 146:f64d43ff0c18 | 1468 | |
mbed_official | 146:f64d43ff0c18 | 1469 | /*! |
mbed_official | 146:f64d43ff0c18 | 1470 | * @name Register UART_S2, field MSBF[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1471 | * |
mbed_official | 146:f64d43ff0c18 | 1472 | * Setting this field reverses the order of the bits that are transmitted and |
mbed_official | 146:f64d43ff0c18 | 1473 | * received on the wire. This field does not affect the polarity of the bits, the |
mbed_official | 146:f64d43ff0c18 | 1474 | * location of the parity bit, or the location of the start or stop bits. This |
mbed_official | 146:f64d43ff0c18 | 1475 | * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and |
mbed_official | 146:f64d43ff0c18 | 1476 | * an initial character is detected in T = 0 protocol mode. |
mbed_official | 146:f64d43ff0c18 | 1477 | * |
mbed_official | 146:f64d43ff0c18 | 1478 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1479 | * - 0 - LSB (bit0) is the first bit that is transmitted following the start |
mbed_official | 146:f64d43ff0c18 | 1480 | * bit. Further, the first bit received after the start bit is identified as |
mbed_official | 146:f64d43ff0c18 | 1481 | * bit0. |
mbed_official | 146:f64d43ff0c18 | 1482 | * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following |
mbed_official | 146:f64d43ff0c18 | 1483 | * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the |
mbed_official | 146:f64d43ff0c18 | 1484 | * first bit received after the start bit is identified as bit8, bit7, or |
mbed_official | 146:f64d43ff0c18 | 1485 | * bit6, depending on the setting of C1[M] and C1[PE]. |
mbed_official | 146:f64d43ff0c18 | 1486 | */ |
mbed_official | 146:f64d43ff0c18 | 1487 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1488 | #define BP_UART_S2_MSBF (5U) //!< Bit position for UART_S2_MSBF. |
mbed_official | 146:f64d43ff0c18 | 1489 | #define BM_UART_S2_MSBF (0x20U) //!< Bit mask for UART_S2_MSBF. |
mbed_official | 146:f64d43ff0c18 | 1490 | #define BS_UART_S2_MSBF (1U) //!< Bit field size in bits for UART_S2_MSBF. |
mbed_official | 146:f64d43ff0c18 | 1491 | |
mbed_official | 146:f64d43ff0c18 | 1492 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1493 | //! @brief Read current value of the UART_S2_MSBF field. |
mbed_official | 146:f64d43ff0c18 | 1494 | #define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF)) |
mbed_official | 146:f64d43ff0c18 | 1495 | #endif |
mbed_official | 146:f64d43ff0c18 | 1496 | |
mbed_official | 146:f64d43ff0c18 | 1497 | //! @brief Format value for bitfield UART_S2_MSBF. |
mbed_official | 146:f64d43ff0c18 | 1498 | #define BF_UART_S2_MSBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_MSBF), uint8_t) & BM_UART_S2_MSBF) |
mbed_official | 146:f64d43ff0c18 | 1499 | |
mbed_official | 146:f64d43ff0c18 | 1500 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1501 | //! @brief Set the MSBF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1502 | #define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1503 | #endif |
mbed_official | 146:f64d43ff0c18 | 1504 | //@} |
mbed_official | 146:f64d43ff0c18 | 1505 | |
mbed_official | 146:f64d43ff0c18 | 1506 | /*! |
mbed_official | 146:f64d43ff0c18 | 1507 | * @name Register UART_S2, field RXEDGIF[6] (W1C) |
mbed_official | 146:f64d43ff0c18 | 1508 | * |
mbed_official | 146:f64d43ff0c18 | 1509 | * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is |
mbed_official | 146:f64d43ff0c18 | 1510 | * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1 |
mbed_official | 146:f64d43ff0c18 | 1511 | * to it. See for additional details. RXEDGIF description The active edge is |
mbed_official | 146:f64d43ff0c18 | 1512 | * detected only in two wire mode and on receiving data coming from the RxD pin. |
mbed_official | 146:f64d43ff0c18 | 1513 | * |
mbed_official | 146:f64d43ff0c18 | 1514 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1515 | * - 0 - No active edge on the receive pin has occurred. |
mbed_official | 146:f64d43ff0c18 | 1516 | * - 1 - An active edge on the receive pin has occurred. |
mbed_official | 146:f64d43ff0c18 | 1517 | */ |
mbed_official | 146:f64d43ff0c18 | 1518 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1519 | #define BP_UART_S2_RXEDGIF (6U) //!< Bit position for UART_S2_RXEDGIF. |
mbed_official | 146:f64d43ff0c18 | 1520 | #define BM_UART_S2_RXEDGIF (0x40U) //!< Bit mask for UART_S2_RXEDGIF. |
mbed_official | 146:f64d43ff0c18 | 1521 | #define BS_UART_S2_RXEDGIF (1U) //!< Bit field size in bits for UART_S2_RXEDGIF. |
mbed_official | 146:f64d43ff0c18 | 1522 | |
mbed_official | 146:f64d43ff0c18 | 1523 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1524 | //! @brief Read current value of the UART_S2_RXEDGIF field. |
mbed_official | 146:f64d43ff0c18 | 1525 | #define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF)) |
mbed_official | 146:f64d43ff0c18 | 1526 | #endif |
mbed_official | 146:f64d43ff0c18 | 1527 | |
mbed_official | 146:f64d43ff0c18 | 1528 | //! @brief Format value for bitfield UART_S2_RXEDGIF. |
mbed_official | 146:f64d43ff0c18 | 1529 | #define BF_UART_S2_RXEDGIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXEDGIF), uint8_t) & BM_UART_S2_RXEDGIF) |
mbed_official | 146:f64d43ff0c18 | 1530 | |
mbed_official | 146:f64d43ff0c18 | 1531 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1532 | //! @brief Set the RXEDGIF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1533 | #define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1534 | #endif |
mbed_official | 146:f64d43ff0c18 | 1535 | //@} |
mbed_official | 146:f64d43ff0c18 | 1536 | |
mbed_official | 146:f64d43ff0c18 | 1537 | /*! |
mbed_official | 146:f64d43ff0c18 | 1538 | * @name Register UART_S2, field LBKDIF[7] (W1C) |
mbed_official | 146:f64d43ff0c18 | 1539 | * |
mbed_official | 146:f64d43ff0c18 | 1540 | * LBKDIF is set when LBKDE is set and a LIN break character is detected on the |
mbed_official | 146:f64d43ff0c18 | 1541 | * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M] |
mbed_official | 146:f64d43ff0c18 | 1542 | * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the |
mbed_official | 146:f64d43ff0c18 | 1543 | * last LIN break character. LBKDIF is cleared by writing a 1 to it. |
mbed_official | 146:f64d43ff0c18 | 1544 | * |
mbed_official | 146:f64d43ff0c18 | 1545 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1546 | * - 0 - No LIN break character detected. |
mbed_official | 146:f64d43ff0c18 | 1547 | * - 1 - LIN break character detected. |
mbed_official | 146:f64d43ff0c18 | 1548 | */ |
mbed_official | 146:f64d43ff0c18 | 1549 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1550 | #define BP_UART_S2_LBKDIF (7U) //!< Bit position for UART_S2_LBKDIF. |
mbed_official | 146:f64d43ff0c18 | 1551 | #define BM_UART_S2_LBKDIF (0x80U) //!< Bit mask for UART_S2_LBKDIF. |
mbed_official | 146:f64d43ff0c18 | 1552 | #define BS_UART_S2_LBKDIF (1U) //!< Bit field size in bits for UART_S2_LBKDIF. |
mbed_official | 146:f64d43ff0c18 | 1553 | |
mbed_official | 146:f64d43ff0c18 | 1554 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1555 | //! @brief Read current value of the UART_S2_LBKDIF field. |
mbed_official | 146:f64d43ff0c18 | 1556 | #define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF)) |
mbed_official | 146:f64d43ff0c18 | 1557 | #endif |
mbed_official | 146:f64d43ff0c18 | 1558 | |
mbed_official | 146:f64d43ff0c18 | 1559 | //! @brief Format value for bitfield UART_S2_LBKDIF. |
mbed_official | 146:f64d43ff0c18 | 1560 | #define BF_UART_S2_LBKDIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDIF), uint8_t) & BM_UART_S2_LBKDIF) |
mbed_official | 146:f64d43ff0c18 | 1561 | |
mbed_official | 146:f64d43ff0c18 | 1562 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1563 | //! @brief Set the LBKDIF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1564 | #define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1565 | #endif |
mbed_official | 146:f64d43ff0c18 | 1566 | //@} |
mbed_official | 146:f64d43ff0c18 | 1567 | |
mbed_official | 146:f64d43ff0c18 | 1568 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1569 | // HW_UART_C3 - UART Control Register 3 |
mbed_official | 146:f64d43ff0c18 | 1570 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1571 | |
mbed_official | 146:f64d43ff0c18 | 1572 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1573 | /*! |
mbed_official | 146:f64d43ff0c18 | 1574 | * @brief HW_UART_C3 - UART Control Register 3 (RW) |
mbed_official | 146:f64d43ff0c18 | 1575 | * |
mbed_official | 146:f64d43ff0c18 | 1576 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1577 | * |
mbed_official | 146:f64d43ff0c18 | 1578 | * Writing R8 does not have any effect. TXDIR and TXINV can be changed only |
mbed_official | 146:f64d43ff0c18 | 1579 | * between transmit and receive packets. |
mbed_official | 146:f64d43ff0c18 | 1580 | */ |
mbed_official | 146:f64d43ff0c18 | 1581 | typedef union _hw_uart_c3 |
mbed_official | 146:f64d43ff0c18 | 1582 | { |
mbed_official | 146:f64d43ff0c18 | 1583 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1584 | struct _hw_uart_c3_bitfields |
mbed_official | 146:f64d43ff0c18 | 1585 | { |
mbed_official | 146:f64d43ff0c18 | 1586 | uint8_t PEIE : 1; //!< [0] Parity Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1587 | uint8_t FEIE : 1; //!< [1] Framing Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1588 | uint8_t NEIE : 1; //!< [2] Noise Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1589 | uint8_t ORIE : 1; //!< [3] Overrun Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 1590 | uint8_t TXINV : 1; //!< [4] Transmit Data Inversion. |
mbed_official | 146:f64d43ff0c18 | 1591 | uint8_t TXDIR : 1; //!< [5] Transmitter Pin Data Direction in |
mbed_official | 146:f64d43ff0c18 | 1592 | //! Single-Wire mode |
mbed_official | 146:f64d43ff0c18 | 1593 | uint8_t T8 : 1; //!< [6] Transmit Bit 8 |
mbed_official | 146:f64d43ff0c18 | 1594 | uint8_t R8 : 1; //!< [7] Received Bit 8 |
mbed_official | 146:f64d43ff0c18 | 1595 | } B; |
mbed_official | 146:f64d43ff0c18 | 1596 | } hw_uart_c3_t; |
mbed_official | 146:f64d43ff0c18 | 1597 | #endif |
mbed_official | 146:f64d43ff0c18 | 1598 | |
mbed_official | 146:f64d43ff0c18 | 1599 | /*! |
mbed_official | 146:f64d43ff0c18 | 1600 | * @name Constants and macros for entire UART_C3 register |
mbed_official | 146:f64d43ff0c18 | 1601 | */ |
mbed_official | 146:f64d43ff0c18 | 1602 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1603 | #define HW_UART_C3_ADDR(x) (REGS_UART_BASE(x) + 0x6U) |
mbed_official | 146:f64d43ff0c18 | 1604 | |
mbed_official | 146:f64d43ff0c18 | 1605 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1606 | #define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 1607 | #define HW_UART_C3_RD(x) (HW_UART_C3(x).U) |
mbed_official | 146:f64d43ff0c18 | 1608 | #define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1609 | #define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1610 | #define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1611 | #define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1612 | #endif |
mbed_official | 146:f64d43ff0c18 | 1613 | //@} |
mbed_official | 146:f64d43ff0c18 | 1614 | |
mbed_official | 146:f64d43ff0c18 | 1615 | /* |
mbed_official | 146:f64d43ff0c18 | 1616 | * Constants & macros for individual UART_C3 bitfields |
mbed_official | 146:f64d43ff0c18 | 1617 | */ |
mbed_official | 146:f64d43ff0c18 | 1618 | |
mbed_official | 146:f64d43ff0c18 | 1619 | /*! |
mbed_official | 146:f64d43ff0c18 | 1620 | * @name Register UART_C3, field PEIE[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1621 | * |
mbed_official | 146:f64d43ff0c18 | 1622 | * Enables the parity error flag, S1[PF], to generate interrupt requests. |
mbed_official | 146:f64d43ff0c18 | 1623 | * |
mbed_official | 146:f64d43ff0c18 | 1624 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1625 | * - 0 - PF interrupt requests are disabled. |
mbed_official | 146:f64d43ff0c18 | 1626 | * - 1 - PF interrupt requests are enabled. |
mbed_official | 146:f64d43ff0c18 | 1627 | */ |
mbed_official | 146:f64d43ff0c18 | 1628 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1629 | #define BP_UART_C3_PEIE (0U) //!< Bit position for UART_C3_PEIE. |
mbed_official | 146:f64d43ff0c18 | 1630 | #define BM_UART_C3_PEIE (0x01U) //!< Bit mask for UART_C3_PEIE. |
mbed_official | 146:f64d43ff0c18 | 1631 | #define BS_UART_C3_PEIE (1U) //!< Bit field size in bits for UART_C3_PEIE. |
mbed_official | 146:f64d43ff0c18 | 1632 | |
mbed_official | 146:f64d43ff0c18 | 1633 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1634 | //! @brief Read current value of the UART_C3_PEIE field. |
mbed_official | 146:f64d43ff0c18 | 1635 | #define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE)) |
mbed_official | 146:f64d43ff0c18 | 1636 | #endif |
mbed_official | 146:f64d43ff0c18 | 1637 | |
mbed_official | 146:f64d43ff0c18 | 1638 | //! @brief Format value for bitfield UART_C3_PEIE. |
mbed_official | 146:f64d43ff0c18 | 1639 | #define BF_UART_C3_PEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_PEIE), uint8_t) & BM_UART_C3_PEIE) |
mbed_official | 146:f64d43ff0c18 | 1640 | |
mbed_official | 146:f64d43ff0c18 | 1641 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1642 | //! @brief Set the PEIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1643 | #define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1644 | #endif |
mbed_official | 146:f64d43ff0c18 | 1645 | //@} |
mbed_official | 146:f64d43ff0c18 | 1646 | |
mbed_official | 146:f64d43ff0c18 | 1647 | /*! |
mbed_official | 146:f64d43ff0c18 | 1648 | * @name Register UART_C3, field FEIE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1649 | * |
mbed_official | 146:f64d43ff0c18 | 1650 | * Enables the framing error flag, S1[FE], to generate interrupt requests. |
mbed_official | 146:f64d43ff0c18 | 1651 | * |
mbed_official | 146:f64d43ff0c18 | 1652 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1653 | * - 0 - FE interrupt requests are disabled. |
mbed_official | 146:f64d43ff0c18 | 1654 | * - 1 - FE interrupt requests are enabled. |
mbed_official | 146:f64d43ff0c18 | 1655 | */ |
mbed_official | 146:f64d43ff0c18 | 1656 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1657 | #define BP_UART_C3_FEIE (1U) //!< Bit position for UART_C3_FEIE. |
mbed_official | 146:f64d43ff0c18 | 1658 | #define BM_UART_C3_FEIE (0x02U) //!< Bit mask for UART_C3_FEIE. |
mbed_official | 146:f64d43ff0c18 | 1659 | #define BS_UART_C3_FEIE (1U) //!< Bit field size in bits for UART_C3_FEIE. |
mbed_official | 146:f64d43ff0c18 | 1660 | |
mbed_official | 146:f64d43ff0c18 | 1661 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1662 | //! @brief Read current value of the UART_C3_FEIE field. |
mbed_official | 146:f64d43ff0c18 | 1663 | #define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE)) |
mbed_official | 146:f64d43ff0c18 | 1664 | #endif |
mbed_official | 146:f64d43ff0c18 | 1665 | |
mbed_official | 146:f64d43ff0c18 | 1666 | //! @brief Format value for bitfield UART_C3_FEIE. |
mbed_official | 146:f64d43ff0c18 | 1667 | #define BF_UART_C3_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_FEIE), uint8_t) & BM_UART_C3_FEIE) |
mbed_official | 146:f64d43ff0c18 | 1668 | |
mbed_official | 146:f64d43ff0c18 | 1669 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1670 | //! @brief Set the FEIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1671 | #define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1672 | #endif |
mbed_official | 146:f64d43ff0c18 | 1673 | //@} |
mbed_official | 146:f64d43ff0c18 | 1674 | |
mbed_official | 146:f64d43ff0c18 | 1675 | /*! |
mbed_official | 146:f64d43ff0c18 | 1676 | * @name Register UART_C3, field NEIE[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1677 | * |
mbed_official | 146:f64d43ff0c18 | 1678 | * Enables the noise flag, S1[NF], to generate interrupt requests. |
mbed_official | 146:f64d43ff0c18 | 1679 | * |
mbed_official | 146:f64d43ff0c18 | 1680 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1681 | * - 0 - NF interrupt requests are disabled. |
mbed_official | 146:f64d43ff0c18 | 1682 | * - 1 - NF interrupt requests are enabled. |
mbed_official | 146:f64d43ff0c18 | 1683 | */ |
mbed_official | 146:f64d43ff0c18 | 1684 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1685 | #define BP_UART_C3_NEIE (2U) //!< Bit position for UART_C3_NEIE. |
mbed_official | 146:f64d43ff0c18 | 1686 | #define BM_UART_C3_NEIE (0x04U) //!< Bit mask for UART_C3_NEIE. |
mbed_official | 146:f64d43ff0c18 | 1687 | #define BS_UART_C3_NEIE (1U) //!< Bit field size in bits for UART_C3_NEIE. |
mbed_official | 146:f64d43ff0c18 | 1688 | |
mbed_official | 146:f64d43ff0c18 | 1689 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1690 | //! @brief Read current value of the UART_C3_NEIE field. |
mbed_official | 146:f64d43ff0c18 | 1691 | #define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE)) |
mbed_official | 146:f64d43ff0c18 | 1692 | #endif |
mbed_official | 146:f64d43ff0c18 | 1693 | |
mbed_official | 146:f64d43ff0c18 | 1694 | //! @brief Format value for bitfield UART_C3_NEIE. |
mbed_official | 146:f64d43ff0c18 | 1695 | #define BF_UART_C3_NEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_NEIE), uint8_t) & BM_UART_C3_NEIE) |
mbed_official | 146:f64d43ff0c18 | 1696 | |
mbed_official | 146:f64d43ff0c18 | 1697 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1698 | //! @brief Set the NEIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1699 | #define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1700 | #endif |
mbed_official | 146:f64d43ff0c18 | 1701 | //@} |
mbed_official | 146:f64d43ff0c18 | 1702 | |
mbed_official | 146:f64d43ff0c18 | 1703 | /*! |
mbed_official | 146:f64d43ff0c18 | 1704 | * @name Register UART_C3, field ORIE[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 1705 | * |
mbed_official | 146:f64d43ff0c18 | 1706 | * Enables the overrun error flag, S1[OR], to generate interrupt requests. |
mbed_official | 146:f64d43ff0c18 | 1707 | * |
mbed_official | 146:f64d43ff0c18 | 1708 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1709 | * - 0 - OR interrupts are disabled. |
mbed_official | 146:f64d43ff0c18 | 1710 | * - 1 - OR interrupt requests are enabled. |
mbed_official | 146:f64d43ff0c18 | 1711 | */ |
mbed_official | 146:f64d43ff0c18 | 1712 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1713 | #define BP_UART_C3_ORIE (3U) //!< Bit position for UART_C3_ORIE. |
mbed_official | 146:f64d43ff0c18 | 1714 | #define BM_UART_C3_ORIE (0x08U) //!< Bit mask for UART_C3_ORIE. |
mbed_official | 146:f64d43ff0c18 | 1715 | #define BS_UART_C3_ORIE (1U) //!< Bit field size in bits for UART_C3_ORIE. |
mbed_official | 146:f64d43ff0c18 | 1716 | |
mbed_official | 146:f64d43ff0c18 | 1717 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1718 | //! @brief Read current value of the UART_C3_ORIE field. |
mbed_official | 146:f64d43ff0c18 | 1719 | #define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE)) |
mbed_official | 146:f64d43ff0c18 | 1720 | #endif |
mbed_official | 146:f64d43ff0c18 | 1721 | |
mbed_official | 146:f64d43ff0c18 | 1722 | //! @brief Format value for bitfield UART_C3_ORIE. |
mbed_official | 146:f64d43ff0c18 | 1723 | #define BF_UART_C3_ORIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_ORIE), uint8_t) & BM_UART_C3_ORIE) |
mbed_official | 146:f64d43ff0c18 | 1724 | |
mbed_official | 146:f64d43ff0c18 | 1725 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1726 | //! @brief Set the ORIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1727 | #define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1728 | #endif |
mbed_official | 146:f64d43ff0c18 | 1729 | //@} |
mbed_official | 146:f64d43ff0c18 | 1730 | |
mbed_official | 146:f64d43ff0c18 | 1731 | /*! |
mbed_official | 146:f64d43ff0c18 | 1732 | * @name Register UART_C3, field TXINV[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1733 | * |
mbed_official | 146:f64d43ff0c18 | 1734 | * Setting this field reverses the polarity of the transmitted data output. In |
mbed_official | 146:f64d43ff0c18 | 1735 | * NRZ format, a one is represented by a mark and a zero is represented by a space |
mbed_official | 146:f64d43ff0c18 | 1736 | * for normal polarity, and the opposite for inverted polarity. In IrDA format, |
mbed_official | 146:f64d43ff0c18 | 1737 | * a zero is represented by short high pulse in the middle of a bit time |
mbed_official | 146:f64d43ff0c18 | 1738 | * remaining idle low for a one for normal polarity, and a zero is represented by short |
mbed_official | 146:f64d43ff0c18 | 1739 | * low pulse in the middle of a bit time remaining idle high for a one for |
mbed_official | 146:f64d43ff0c18 | 1740 | * inverted polarity. This field is automatically set when C7816[INIT] and |
mbed_official | 146:f64d43ff0c18 | 1741 | * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode. |
mbed_official | 146:f64d43ff0c18 | 1742 | * Setting TXINV inverts all transmitted values, including idle, break, start, and |
mbed_official | 146:f64d43ff0c18 | 1743 | * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit |
mbed_official | 146:f64d43ff0c18 | 1744 | * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only |
mbed_official | 146:f64d43ff0c18 | 1745 | * the transmitted data bits and parity bit are inverted. |
mbed_official | 146:f64d43ff0c18 | 1746 | * |
mbed_official | 146:f64d43ff0c18 | 1747 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1748 | * - 0 - Transmit data is not inverted. |
mbed_official | 146:f64d43ff0c18 | 1749 | * - 1 - Transmit data is inverted. |
mbed_official | 146:f64d43ff0c18 | 1750 | */ |
mbed_official | 146:f64d43ff0c18 | 1751 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1752 | #define BP_UART_C3_TXINV (4U) //!< Bit position for UART_C3_TXINV. |
mbed_official | 146:f64d43ff0c18 | 1753 | #define BM_UART_C3_TXINV (0x10U) //!< Bit mask for UART_C3_TXINV. |
mbed_official | 146:f64d43ff0c18 | 1754 | #define BS_UART_C3_TXINV (1U) //!< Bit field size in bits for UART_C3_TXINV. |
mbed_official | 146:f64d43ff0c18 | 1755 | |
mbed_official | 146:f64d43ff0c18 | 1756 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1757 | //! @brief Read current value of the UART_C3_TXINV field. |
mbed_official | 146:f64d43ff0c18 | 1758 | #define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV)) |
mbed_official | 146:f64d43ff0c18 | 1759 | #endif |
mbed_official | 146:f64d43ff0c18 | 1760 | |
mbed_official | 146:f64d43ff0c18 | 1761 | //! @brief Format value for bitfield UART_C3_TXINV. |
mbed_official | 146:f64d43ff0c18 | 1762 | #define BF_UART_C3_TXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXINV), uint8_t) & BM_UART_C3_TXINV) |
mbed_official | 146:f64d43ff0c18 | 1763 | |
mbed_official | 146:f64d43ff0c18 | 1764 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1765 | //! @brief Set the TXINV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1766 | #define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1767 | #endif |
mbed_official | 146:f64d43ff0c18 | 1768 | //@} |
mbed_official | 146:f64d43ff0c18 | 1769 | |
mbed_official | 146:f64d43ff0c18 | 1770 | /*! |
mbed_official | 146:f64d43ff0c18 | 1771 | * @name Register UART_C3, field TXDIR[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1772 | * |
mbed_official | 146:f64d43ff0c18 | 1773 | * Determines whether the TXD pin is used as an input or output in the |
mbed_official | 146:f64d43ff0c18 | 1774 | * single-wire mode of operation. This field is relevant only to the single wire mode. |
mbed_official | 146:f64d43ff0c18 | 1775 | * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is |
mbed_official | 146:f64d43ff0c18 | 1776 | * automatically cleared after the requested block is transmitted. This condition is |
mbed_official | 146:f64d43ff0c18 | 1777 | * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted. |
mbed_official | 146:f64d43ff0c18 | 1778 | * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is |
mbed_official | 146:f64d43ff0c18 | 1779 | * being transmitted, the hardware automatically overrides this field as needed. In |
mbed_official | 146:f64d43ff0c18 | 1780 | * this situation, TXDIR does not reflect the temporary state associated with |
mbed_official | 146:f64d43ff0c18 | 1781 | * the NACK. |
mbed_official | 146:f64d43ff0c18 | 1782 | * |
mbed_official | 146:f64d43ff0c18 | 1783 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1784 | * - 0 - TXD pin is an input in single wire mode. |
mbed_official | 146:f64d43ff0c18 | 1785 | * - 1 - TXD pin is an output in single wire mode. |
mbed_official | 146:f64d43ff0c18 | 1786 | */ |
mbed_official | 146:f64d43ff0c18 | 1787 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1788 | #define BP_UART_C3_TXDIR (5U) //!< Bit position for UART_C3_TXDIR. |
mbed_official | 146:f64d43ff0c18 | 1789 | #define BM_UART_C3_TXDIR (0x20U) //!< Bit mask for UART_C3_TXDIR. |
mbed_official | 146:f64d43ff0c18 | 1790 | #define BS_UART_C3_TXDIR (1U) //!< Bit field size in bits for UART_C3_TXDIR. |
mbed_official | 146:f64d43ff0c18 | 1791 | |
mbed_official | 146:f64d43ff0c18 | 1792 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1793 | //! @brief Read current value of the UART_C3_TXDIR field. |
mbed_official | 146:f64d43ff0c18 | 1794 | #define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR)) |
mbed_official | 146:f64d43ff0c18 | 1795 | #endif |
mbed_official | 146:f64d43ff0c18 | 1796 | |
mbed_official | 146:f64d43ff0c18 | 1797 | //! @brief Format value for bitfield UART_C3_TXDIR. |
mbed_official | 146:f64d43ff0c18 | 1798 | #define BF_UART_C3_TXDIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXDIR), uint8_t) & BM_UART_C3_TXDIR) |
mbed_official | 146:f64d43ff0c18 | 1799 | |
mbed_official | 146:f64d43ff0c18 | 1800 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1801 | //! @brief Set the TXDIR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1802 | #define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1803 | #endif |
mbed_official | 146:f64d43ff0c18 | 1804 | //@} |
mbed_official | 146:f64d43ff0c18 | 1805 | |
mbed_official | 146:f64d43ff0c18 | 1806 | /*! |
mbed_official | 146:f64d43ff0c18 | 1807 | * @name Register UART_C3, field T8[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1808 | * |
mbed_official | 146:f64d43ff0c18 | 1809 | * T8 is the ninth data bit transmitted when the UART is configured for 9-bit |
mbed_official | 146:f64d43ff0c18 | 1810 | * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the |
mbed_official | 146:f64d43ff0c18 | 1811 | * same as in the previous transmission, T8 does not have to be rewritten. The same |
mbed_official | 146:f64d43ff0c18 | 1812 | * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit, |
mbed_official | 146:f64d43ff0c18 | 1813 | * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with |
mbed_official | 146:f64d43ff0c18 | 1814 | * the remaining data. |
mbed_official | 146:f64d43ff0c18 | 1815 | */ |
mbed_official | 146:f64d43ff0c18 | 1816 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1817 | #define BP_UART_C3_T8 (6U) //!< Bit position for UART_C3_T8. |
mbed_official | 146:f64d43ff0c18 | 1818 | #define BM_UART_C3_T8 (0x40U) //!< Bit mask for UART_C3_T8. |
mbed_official | 146:f64d43ff0c18 | 1819 | #define BS_UART_C3_T8 (1U) //!< Bit field size in bits for UART_C3_T8. |
mbed_official | 146:f64d43ff0c18 | 1820 | |
mbed_official | 146:f64d43ff0c18 | 1821 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1822 | //! @brief Read current value of the UART_C3_T8 field. |
mbed_official | 146:f64d43ff0c18 | 1823 | #define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8)) |
mbed_official | 146:f64d43ff0c18 | 1824 | #endif |
mbed_official | 146:f64d43ff0c18 | 1825 | |
mbed_official | 146:f64d43ff0c18 | 1826 | //! @brief Format value for bitfield UART_C3_T8. |
mbed_official | 146:f64d43ff0c18 | 1827 | #define BF_UART_C3_T8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_T8), uint8_t) & BM_UART_C3_T8) |
mbed_official | 146:f64d43ff0c18 | 1828 | |
mbed_official | 146:f64d43ff0c18 | 1829 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1830 | //! @brief Set the T8 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1831 | #define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1832 | #endif |
mbed_official | 146:f64d43ff0c18 | 1833 | //@} |
mbed_official | 146:f64d43ff0c18 | 1834 | |
mbed_official | 146:f64d43ff0c18 | 1835 | /*! |
mbed_official | 146:f64d43ff0c18 | 1836 | * @name Register UART_C3, field R8[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 1837 | * |
mbed_official | 146:f64d43ff0c18 | 1838 | * R8 is the ninth data bit received when the UART is configured for 9-bit data |
mbed_official | 146:f64d43ff0c18 | 1839 | * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the |
mbed_official | 146:f64d43ff0c18 | 1840 | * current data value in the UARTx_D register. To read the 9th bit, read the |
mbed_official | 146:f64d43ff0c18 | 1841 | * value of UARTx_C3[R8], then read the UARTx_D register. |
mbed_official | 146:f64d43ff0c18 | 1842 | */ |
mbed_official | 146:f64d43ff0c18 | 1843 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1844 | #define BP_UART_C3_R8 (7U) //!< Bit position for UART_C3_R8. |
mbed_official | 146:f64d43ff0c18 | 1845 | #define BM_UART_C3_R8 (0x80U) //!< Bit mask for UART_C3_R8. |
mbed_official | 146:f64d43ff0c18 | 1846 | #define BS_UART_C3_R8 (1U) //!< Bit field size in bits for UART_C3_R8. |
mbed_official | 146:f64d43ff0c18 | 1847 | |
mbed_official | 146:f64d43ff0c18 | 1848 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1849 | //! @brief Read current value of the UART_C3_R8 field. |
mbed_official | 146:f64d43ff0c18 | 1850 | #define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8)) |
mbed_official | 146:f64d43ff0c18 | 1851 | #endif |
mbed_official | 146:f64d43ff0c18 | 1852 | //@} |
mbed_official | 146:f64d43ff0c18 | 1853 | |
mbed_official | 146:f64d43ff0c18 | 1854 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1855 | // HW_UART_D - UART Data Register |
mbed_official | 146:f64d43ff0c18 | 1856 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1857 | |
mbed_official | 146:f64d43ff0c18 | 1858 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1859 | /*! |
mbed_official | 146:f64d43ff0c18 | 1860 | * @brief HW_UART_D - UART Data Register (RW) |
mbed_official | 146:f64d43ff0c18 | 1861 | * |
mbed_official | 146:f64d43ff0c18 | 1862 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1863 | * |
mbed_official | 146:f64d43ff0c18 | 1864 | * This register is actually two separate registers. Reads return the contents |
mbed_official | 146:f64d43ff0c18 | 1865 | * of the read-only receive data register and writes go to the write-only transmit |
mbed_official | 146:f64d43ff0c18 | 1866 | * data register. In 8-bit or 9-bit data format, only UART data register (D) |
mbed_official | 146:f64d43ff0c18 | 1867 | * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is |
mbed_official | 146:f64d43ff0c18 | 1868 | * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D |
mbed_official | 146:f64d43ff0c18 | 1869 | * register, only if the ninth bit of data needs to be captured. Similarly, the |
mbed_official | 146:f64d43ff0c18 | 1870 | * ED register needs to be read, prior to the D register, only if the additional |
mbed_official | 146:f64d43ff0c18 | 1871 | * flag data for the dataword needs to be captured. In the normal 8-bit mode (M |
mbed_official | 146:f64d43ff0c18 | 1872 | * bit cleared) if the parity is enabled, you get seven data bits and one parity |
mbed_official | 146:f64d43ff0c18 | 1873 | * bit. That one parity bit is loaded into the D register. So, for the data bits, |
mbed_official | 146:f64d43ff0c18 | 1874 | * mask off the parity bit from the value you read out of this register. When |
mbed_official | 146:f64d43ff0c18 | 1875 | * transmitting in 9-bit data format and using 8-bit write instructions, write first |
mbed_official | 146:f64d43ff0c18 | 1876 | * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to |
mbed_official | 146:f64d43ff0c18 | 1877 | * C3[T8] stores the data in a temporary register. If D register is written first, |
mbed_official | 146:f64d43ff0c18 | 1878 | * and then the new data on data bus is stored in D, the temporary value written by |
mbed_official | 146:f64d43ff0c18 | 1879 | * the last write to C3[T8] gets stored in the C3[T8] register. |
mbed_official | 146:f64d43ff0c18 | 1880 | */ |
mbed_official | 146:f64d43ff0c18 | 1881 | typedef union _hw_uart_d |
mbed_official | 146:f64d43ff0c18 | 1882 | { |
mbed_official | 146:f64d43ff0c18 | 1883 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1884 | struct _hw_uart_d_bitfields |
mbed_official | 146:f64d43ff0c18 | 1885 | { |
mbed_official | 146:f64d43ff0c18 | 1886 | uint8_t RT : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1887 | } B; |
mbed_official | 146:f64d43ff0c18 | 1888 | } hw_uart_d_t; |
mbed_official | 146:f64d43ff0c18 | 1889 | #endif |
mbed_official | 146:f64d43ff0c18 | 1890 | |
mbed_official | 146:f64d43ff0c18 | 1891 | /*! |
mbed_official | 146:f64d43ff0c18 | 1892 | * @name Constants and macros for entire UART_D register |
mbed_official | 146:f64d43ff0c18 | 1893 | */ |
mbed_official | 146:f64d43ff0c18 | 1894 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1895 | #define HW_UART_D_ADDR(x) (REGS_UART_BASE(x) + 0x7U) |
mbed_official | 146:f64d43ff0c18 | 1896 | |
mbed_official | 146:f64d43ff0c18 | 1897 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1898 | #define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 1899 | #define HW_UART_D_RD(x) (HW_UART_D(x).U) |
mbed_official | 146:f64d43ff0c18 | 1900 | #define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1901 | #define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1902 | #define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1903 | #define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1904 | #endif |
mbed_official | 146:f64d43ff0c18 | 1905 | //@} |
mbed_official | 146:f64d43ff0c18 | 1906 | |
mbed_official | 146:f64d43ff0c18 | 1907 | /* |
mbed_official | 146:f64d43ff0c18 | 1908 | * Constants & macros for individual UART_D bitfields |
mbed_official | 146:f64d43ff0c18 | 1909 | */ |
mbed_official | 146:f64d43ff0c18 | 1910 | |
mbed_official | 146:f64d43ff0c18 | 1911 | /*! |
mbed_official | 146:f64d43ff0c18 | 1912 | * @name Register UART_D, field RT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1913 | * |
mbed_official | 146:f64d43ff0c18 | 1914 | * Reads return the contents of the read-only receive data register and writes |
mbed_official | 146:f64d43ff0c18 | 1915 | * go to the write-only transmit data register. |
mbed_official | 146:f64d43ff0c18 | 1916 | */ |
mbed_official | 146:f64d43ff0c18 | 1917 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1918 | #define BP_UART_D_RT (0U) //!< Bit position for UART_D_RT. |
mbed_official | 146:f64d43ff0c18 | 1919 | #define BM_UART_D_RT (0xFFU) //!< Bit mask for UART_D_RT. |
mbed_official | 146:f64d43ff0c18 | 1920 | #define BS_UART_D_RT (8U) //!< Bit field size in bits for UART_D_RT. |
mbed_official | 146:f64d43ff0c18 | 1921 | |
mbed_official | 146:f64d43ff0c18 | 1922 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1923 | //! @brief Read current value of the UART_D_RT field. |
mbed_official | 146:f64d43ff0c18 | 1924 | #define BR_UART_D_RT(x) (HW_UART_D(x).U) |
mbed_official | 146:f64d43ff0c18 | 1925 | #endif |
mbed_official | 146:f64d43ff0c18 | 1926 | |
mbed_official | 146:f64d43ff0c18 | 1927 | //! @brief Format value for bitfield UART_D_RT. |
mbed_official | 146:f64d43ff0c18 | 1928 | #define BF_UART_D_RT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_D_RT), uint8_t) & BM_UART_D_RT) |
mbed_official | 146:f64d43ff0c18 | 1929 | |
mbed_official | 146:f64d43ff0c18 | 1930 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1931 | //! @brief Set the RT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1932 | #define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 1933 | #endif |
mbed_official | 146:f64d43ff0c18 | 1934 | //@} |
mbed_official | 146:f64d43ff0c18 | 1935 | |
mbed_official | 146:f64d43ff0c18 | 1936 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1937 | // HW_UART_MA1 - UART Match Address Registers 1 |
mbed_official | 146:f64d43ff0c18 | 1938 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1939 | |
mbed_official | 146:f64d43ff0c18 | 1940 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1941 | /*! |
mbed_official | 146:f64d43ff0c18 | 1942 | * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW) |
mbed_official | 146:f64d43ff0c18 | 1943 | * |
mbed_official | 146:f64d43ff0c18 | 1944 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1945 | * |
mbed_official | 146:f64d43ff0c18 | 1946 | * The MA1 and MA2 registers are compared to input data addresses when the most |
mbed_official | 146:f64d43ff0c18 | 1947 | * significant bit is set and the associated C4[MAEN] field is set. If a match |
mbed_official | 146:f64d43ff0c18 | 1948 | * occurs, the following data is transferred to the data register. If a match |
mbed_official | 146:f64d43ff0c18 | 1949 | * fails, the following data is discarded. These registers can be read and written at |
mbed_official | 146:f64d43ff0c18 | 1950 | * anytime. |
mbed_official | 146:f64d43ff0c18 | 1951 | */ |
mbed_official | 146:f64d43ff0c18 | 1952 | typedef union _hw_uart_ma1 |
mbed_official | 146:f64d43ff0c18 | 1953 | { |
mbed_official | 146:f64d43ff0c18 | 1954 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1955 | struct _hw_uart_ma1_bitfields |
mbed_official | 146:f64d43ff0c18 | 1956 | { |
mbed_official | 146:f64d43ff0c18 | 1957 | uint8_t MA : 8; //!< [7:0] Match Address |
mbed_official | 146:f64d43ff0c18 | 1958 | } B; |
mbed_official | 146:f64d43ff0c18 | 1959 | } hw_uart_ma1_t; |
mbed_official | 146:f64d43ff0c18 | 1960 | #endif |
mbed_official | 146:f64d43ff0c18 | 1961 | |
mbed_official | 146:f64d43ff0c18 | 1962 | /*! |
mbed_official | 146:f64d43ff0c18 | 1963 | * @name Constants and macros for entire UART_MA1 register |
mbed_official | 146:f64d43ff0c18 | 1964 | */ |
mbed_official | 146:f64d43ff0c18 | 1965 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1966 | #define HW_UART_MA1_ADDR(x) (REGS_UART_BASE(x) + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 1967 | |
mbed_official | 146:f64d43ff0c18 | 1968 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1969 | #define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 1970 | #define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U) |
mbed_official | 146:f64d43ff0c18 | 1971 | #define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1972 | #define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1973 | #define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1974 | #define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1975 | #endif |
mbed_official | 146:f64d43ff0c18 | 1976 | //@} |
mbed_official | 146:f64d43ff0c18 | 1977 | |
mbed_official | 146:f64d43ff0c18 | 1978 | /* |
mbed_official | 146:f64d43ff0c18 | 1979 | * Constants & macros for individual UART_MA1 bitfields |
mbed_official | 146:f64d43ff0c18 | 1980 | */ |
mbed_official | 146:f64d43ff0c18 | 1981 | |
mbed_official | 146:f64d43ff0c18 | 1982 | /*! |
mbed_official | 146:f64d43ff0c18 | 1983 | * @name Register UART_MA1, field MA[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1984 | */ |
mbed_official | 146:f64d43ff0c18 | 1985 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1986 | #define BP_UART_MA1_MA (0U) //!< Bit position for UART_MA1_MA. |
mbed_official | 146:f64d43ff0c18 | 1987 | #define BM_UART_MA1_MA (0xFFU) //!< Bit mask for UART_MA1_MA. |
mbed_official | 146:f64d43ff0c18 | 1988 | #define BS_UART_MA1_MA (8U) //!< Bit field size in bits for UART_MA1_MA. |
mbed_official | 146:f64d43ff0c18 | 1989 | |
mbed_official | 146:f64d43ff0c18 | 1990 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1991 | //! @brief Read current value of the UART_MA1_MA field. |
mbed_official | 146:f64d43ff0c18 | 1992 | #define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U) |
mbed_official | 146:f64d43ff0c18 | 1993 | #endif |
mbed_official | 146:f64d43ff0c18 | 1994 | |
mbed_official | 146:f64d43ff0c18 | 1995 | //! @brief Format value for bitfield UART_MA1_MA. |
mbed_official | 146:f64d43ff0c18 | 1996 | #define BF_UART_MA1_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA1_MA), uint8_t) & BM_UART_MA1_MA) |
mbed_official | 146:f64d43ff0c18 | 1997 | |
mbed_official | 146:f64d43ff0c18 | 1998 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1999 | //! @brief Set the MA field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2000 | #define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 2001 | #endif |
mbed_official | 146:f64d43ff0c18 | 2002 | //@} |
mbed_official | 146:f64d43ff0c18 | 2003 | |
mbed_official | 146:f64d43ff0c18 | 2004 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2005 | // HW_UART_MA2 - UART Match Address Registers 2 |
mbed_official | 146:f64d43ff0c18 | 2006 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2007 | |
mbed_official | 146:f64d43ff0c18 | 2008 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2009 | /*! |
mbed_official | 146:f64d43ff0c18 | 2010 | * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW) |
mbed_official | 146:f64d43ff0c18 | 2011 | * |
mbed_official | 146:f64d43ff0c18 | 2012 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2013 | * |
mbed_official | 146:f64d43ff0c18 | 2014 | * These registers can be read and written at anytime. The MA1 and MA2 registers |
mbed_official | 146:f64d43ff0c18 | 2015 | * are compared to input data addresses when the most significant bit is set and |
mbed_official | 146:f64d43ff0c18 | 2016 | * the associated C4[MAEN] field is set. If a match occurs, the following data |
mbed_official | 146:f64d43ff0c18 | 2017 | * is transferred to the data register. If a match fails, the following data is |
mbed_official | 146:f64d43ff0c18 | 2018 | * discarded. |
mbed_official | 146:f64d43ff0c18 | 2019 | */ |
mbed_official | 146:f64d43ff0c18 | 2020 | typedef union _hw_uart_ma2 |
mbed_official | 146:f64d43ff0c18 | 2021 | { |
mbed_official | 146:f64d43ff0c18 | 2022 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2023 | struct _hw_uart_ma2_bitfields |
mbed_official | 146:f64d43ff0c18 | 2024 | { |
mbed_official | 146:f64d43ff0c18 | 2025 | uint8_t MA : 8; //!< [7:0] Match Address |
mbed_official | 146:f64d43ff0c18 | 2026 | } B; |
mbed_official | 146:f64d43ff0c18 | 2027 | } hw_uart_ma2_t; |
mbed_official | 146:f64d43ff0c18 | 2028 | #endif |
mbed_official | 146:f64d43ff0c18 | 2029 | |
mbed_official | 146:f64d43ff0c18 | 2030 | /*! |
mbed_official | 146:f64d43ff0c18 | 2031 | * @name Constants and macros for entire UART_MA2 register |
mbed_official | 146:f64d43ff0c18 | 2032 | */ |
mbed_official | 146:f64d43ff0c18 | 2033 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2034 | #define HW_UART_MA2_ADDR(x) (REGS_UART_BASE(x) + 0x9U) |
mbed_official | 146:f64d43ff0c18 | 2035 | |
mbed_official | 146:f64d43ff0c18 | 2036 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2037 | #define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2038 | #define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U) |
mbed_official | 146:f64d43ff0c18 | 2039 | #define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2040 | #define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2041 | #define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2042 | #define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2043 | #endif |
mbed_official | 146:f64d43ff0c18 | 2044 | //@} |
mbed_official | 146:f64d43ff0c18 | 2045 | |
mbed_official | 146:f64d43ff0c18 | 2046 | /* |
mbed_official | 146:f64d43ff0c18 | 2047 | * Constants & macros for individual UART_MA2 bitfields |
mbed_official | 146:f64d43ff0c18 | 2048 | */ |
mbed_official | 146:f64d43ff0c18 | 2049 | |
mbed_official | 146:f64d43ff0c18 | 2050 | /*! |
mbed_official | 146:f64d43ff0c18 | 2051 | * @name Register UART_MA2, field MA[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2052 | */ |
mbed_official | 146:f64d43ff0c18 | 2053 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2054 | #define BP_UART_MA2_MA (0U) //!< Bit position for UART_MA2_MA. |
mbed_official | 146:f64d43ff0c18 | 2055 | #define BM_UART_MA2_MA (0xFFU) //!< Bit mask for UART_MA2_MA. |
mbed_official | 146:f64d43ff0c18 | 2056 | #define BS_UART_MA2_MA (8U) //!< Bit field size in bits for UART_MA2_MA. |
mbed_official | 146:f64d43ff0c18 | 2057 | |
mbed_official | 146:f64d43ff0c18 | 2058 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2059 | //! @brief Read current value of the UART_MA2_MA field. |
mbed_official | 146:f64d43ff0c18 | 2060 | #define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U) |
mbed_official | 146:f64d43ff0c18 | 2061 | #endif |
mbed_official | 146:f64d43ff0c18 | 2062 | |
mbed_official | 146:f64d43ff0c18 | 2063 | //! @brief Format value for bitfield UART_MA2_MA. |
mbed_official | 146:f64d43ff0c18 | 2064 | #define BF_UART_MA2_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA2_MA), uint8_t) & BM_UART_MA2_MA) |
mbed_official | 146:f64d43ff0c18 | 2065 | |
mbed_official | 146:f64d43ff0c18 | 2066 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2067 | //! @brief Set the MA field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2068 | #define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 2069 | #endif |
mbed_official | 146:f64d43ff0c18 | 2070 | //@} |
mbed_official | 146:f64d43ff0c18 | 2071 | |
mbed_official | 146:f64d43ff0c18 | 2072 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2073 | // HW_UART_C4 - UART Control Register 4 |
mbed_official | 146:f64d43ff0c18 | 2074 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2075 | |
mbed_official | 146:f64d43ff0c18 | 2076 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2077 | /*! |
mbed_official | 146:f64d43ff0c18 | 2078 | * @brief HW_UART_C4 - UART Control Register 4 (RW) |
mbed_official | 146:f64d43ff0c18 | 2079 | * |
mbed_official | 146:f64d43ff0c18 | 2080 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2081 | */ |
mbed_official | 146:f64d43ff0c18 | 2082 | typedef union _hw_uart_c4 |
mbed_official | 146:f64d43ff0c18 | 2083 | { |
mbed_official | 146:f64d43ff0c18 | 2084 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2085 | struct _hw_uart_c4_bitfields |
mbed_official | 146:f64d43ff0c18 | 2086 | { |
mbed_official | 146:f64d43ff0c18 | 2087 | uint8_t BRFA : 5; //!< [4:0] Baud Rate Fine Adjust |
mbed_official | 146:f64d43ff0c18 | 2088 | uint8_t M10 : 1; //!< [5] 10-bit Mode select |
mbed_official | 146:f64d43ff0c18 | 2089 | uint8_t MAEN2 : 1; //!< [6] Match Address Mode Enable 2 |
mbed_official | 146:f64d43ff0c18 | 2090 | uint8_t MAEN1 : 1; //!< [7] Match Address Mode Enable 1 |
mbed_official | 146:f64d43ff0c18 | 2091 | } B; |
mbed_official | 146:f64d43ff0c18 | 2092 | } hw_uart_c4_t; |
mbed_official | 146:f64d43ff0c18 | 2093 | #endif |
mbed_official | 146:f64d43ff0c18 | 2094 | |
mbed_official | 146:f64d43ff0c18 | 2095 | /*! |
mbed_official | 146:f64d43ff0c18 | 2096 | * @name Constants and macros for entire UART_C4 register |
mbed_official | 146:f64d43ff0c18 | 2097 | */ |
mbed_official | 146:f64d43ff0c18 | 2098 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2099 | #define HW_UART_C4_ADDR(x) (REGS_UART_BASE(x) + 0xAU) |
mbed_official | 146:f64d43ff0c18 | 2100 | |
mbed_official | 146:f64d43ff0c18 | 2101 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2102 | #define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2103 | #define HW_UART_C4_RD(x) (HW_UART_C4(x).U) |
mbed_official | 146:f64d43ff0c18 | 2104 | #define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2105 | #define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2106 | #define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2107 | #define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2108 | #endif |
mbed_official | 146:f64d43ff0c18 | 2109 | //@} |
mbed_official | 146:f64d43ff0c18 | 2110 | |
mbed_official | 146:f64d43ff0c18 | 2111 | /* |
mbed_official | 146:f64d43ff0c18 | 2112 | * Constants & macros for individual UART_C4 bitfields |
mbed_official | 146:f64d43ff0c18 | 2113 | */ |
mbed_official | 146:f64d43ff0c18 | 2114 | |
mbed_official | 146:f64d43ff0c18 | 2115 | /*! |
mbed_official | 146:f64d43ff0c18 | 2116 | * @name Register UART_C4, field BRFA[4:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2117 | * |
mbed_official | 146:f64d43ff0c18 | 2118 | * This bit field is used to add more timing resolution to the average baud |
mbed_official | 146:f64d43ff0c18 | 2119 | * frequency, in increments of 1/32. See Baud rate generation for more information. |
mbed_official | 146:f64d43ff0c18 | 2120 | */ |
mbed_official | 146:f64d43ff0c18 | 2121 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2122 | #define BP_UART_C4_BRFA (0U) //!< Bit position for UART_C4_BRFA. |
mbed_official | 146:f64d43ff0c18 | 2123 | #define BM_UART_C4_BRFA (0x1FU) //!< Bit mask for UART_C4_BRFA. |
mbed_official | 146:f64d43ff0c18 | 2124 | #define BS_UART_C4_BRFA (5U) //!< Bit field size in bits for UART_C4_BRFA. |
mbed_official | 146:f64d43ff0c18 | 2125 | |
mbed_official | 146:f64d43ff0c18 | 2126 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2127 | //! @brief Read current value of the UART_C4_BRFA field. |
mbed_official | 146:f64d43ff0c18 | 2128 | #define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA) |
mbed_official | 146:f64d43ff0c18 | 2129 | #endif |
mbed_official | 146:f64d43ff0c18 | 2130 | |
mbed_official | 146:f64d43ff0c18 | 2131 | //! @brief Format value for bitfield UART_C4_BRFA. |
mbed_official | 146:f64d43ff0c18 | 2132 | #define BF_UART_C4_BRFA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_BRFA), uint8_t) & BM_UART_C4_BRFA) |
mbed_official | 146:f64d43ff0c18 | 2133 | |
mbed_official | 146:f64d43ff0c18 | 2134 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2135 | //! @brief Set the BRFA field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2136 | #define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v))) |
mbed_official | 146:f64d43ff0c18 | 2137 | #endif |
mbed_official | 146:f64d43ff0c18 | 2138 | //@} |
mbed_official | 146:f64d43ff0c18 | 2139 | |
mbed_official | 146:f64d43ff0c18 | 2140 | /*! |
mbed_official | 146:f64d43ff0c18 | 2141 | * @name Register UART_C4, field M10[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 2142 | * |
mbed_official | 146:f64d43ff0c18 | 2143 | * Causes a tenth, non-memory mapped bit to be part of the serial transmission. |
mbed_official | 146:f64d43ff0c18 | 2144 | * This tenth bit is generated and interpreted as a parity bit. The M10 field |
mbed_official | 146:f64d43ff0c18 | 2145 | * does not affect the LIN send or detect break behavior. If M10 is set, then both |
mbed_official | 146:f64d43ff0c18 | 2146 | * C1[M] and C1[PE] must also be set. This field must be cleared when |
mbed_official | 146:f64d43ff0c18 | 2147 | * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information. |
mbed_official | 146:f64d43ff0c18 | 2148 | * |
mbed_official | 146:f64d43ff0c18 | 2149 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2150 | * - 0 - The parity bit is the ninth bit in the serial transmission. |
mbed_official | 146:f64d43ff0c18 | 2151 | * - 1 - The parity bit is the tenth bit in the serial transmission. |
mbed_official | 146:f64d43ff0c18 | 2152 | */ |
mbed_official | 146:f64d43ff0c18 | 2153 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2154 | #define BP_UART_C4_M10 (5U) //!< Bit position for UART_C4_M10. |
mbed_official | 146:f64d43ff0c18 | 2155 | #define BM_UART_C4_M10 (0x20U) //!< Bit mask for UART_C4_M10. |
mbed_official | 146:f64d43ff0c18 | 2156 | #define BS_UART_C4_M10 (1U) //!< Bit field size in bits for UART_C4_M10. |
mbed_official | 146:f64d43ff0c18 | 2157 | |
mbed_official | 146:f64d43ff0c18 | 2158 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2159 | //! @brief Read current value of the UART_C4_M10 field. |
mbed_official | 146:f64d43ff0c18 | 2160 | #define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10)) |
mbed_official | 146:f64d43ff0c18 | 2161 | #endif |
mbed_official | 146:f64d43ff0c18 | 2162 | |
mbed_official | 146:f64d43ff0c18 | 2163 | //! @brief Format value for bitfield UART_C4_M10. |
mbed_official | 146:f64d43ff0c18 | 2164 | #define BF_UART_C4_M10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_M10), uint8_t) & BM_UART_C4_M10) |
mbed_official | 146:f64d43ff0c18 | 2165 | |
mbed_official | 146:f64d43ff0c18 | 2166 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2167 | //! @brief Set the M10 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2168 | #define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2169 | #endif |
mbed_official | 146:f64d43ff0c18 | 2170 | //@} |
mbed_official | 146:f64d43ff0c18 | 2171 | |
mbed_official | 146:f64d43ff0c18 | 2172 | /*! |
mbed_official | 146:f64d43ff0c18 | 2173 | * @name Register UART_C4, field MAEN2[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 2174 | * |
mbed_official | 146:f64d43ff0c18 | 2175 | * See Match address operation for more information. |
mbed_official | 146:f64d43ff0c18 | 2176 | * |
mbed_official | 146:f64d43ff0c18 | 2177 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2178 | * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared. |
mbed_official | 146:f64d43ff0c18 | 2179 | * - 1 - All data received with the most significant bit cleared, is discarded. |
mbed_official | 146:f64d43ff0c18 | 2180 | * All data received with the most significant bit set, is compared with |
mbed_official | 146:f64d43ff0c18 | 2181 | * contents of MA2 register. If no match occurs, the data is discarded. If a |
mbed_official | 146:f64d43ff0c18 | 2182 | * match occurs, data is transferred to the data buffer. This field must be |
mbed_official | 146:f64d43ff0c18 | 2183 | * cleared when C7816[ISO7816E] is set/enabled. |
mbed_official | 146:f64d43ff0c18 | 2184 | */ |
mbed_official | 146:f64d43ff0c18 | 2185 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2186 | #define BP_UART_C4_MAEN2 (6U) //!< Bit position for UART_C4_MAEN2. |
mbed_official | 146:f64d43ff0c18 | 2187 | #define BM_UART_C4_MAEN2 (0x40U) //!< Bit mask for UART_C4_MAEN2. |
mbed_official | 146:f64d43ff0c18 | 2188 | #define BS_UART_C4_MAEN2 (1U) //!< Bit field size in bits for UART_C4_MAEN2. |
mbed_official | 146:f64d43ff0c18 | 2189 | |
mbed_official | 146:f64d43ff0c18 | 2190 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2191 | //! @brief Read current value of the UART_C4_MAEN2 field. |
mbed_official | 146:f64d43ff0c18 | 2192 | #define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2)) |
mbed_official | 146:f64d43ff0c18 | 2193 | #endif |
mbed_official | 146:f64d43ff0c18 | 2194 | |
mbed_official | 146:f64d43ff0c18 | 2195 | //! @brief Format value for bitfield UART_C4_MAEN2. |
mbed_official | 146:f64d43ff0c18 | 2196 | #define BF_UART_C4_MAEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN2), uint8_t) & BM_UART_C4_MAEN2) |
mbed_official | 146:f64d43ff0c18 | 2197 | |
mbed_official | 146:f64d43ff0c18 | 2198 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2199 | //! @brief Set the MAEN2 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2200 | #define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2201 | #endif |
mbed_official | 146:f64d43ff0c18 | 2202 | //@} |
mbed_official | 146:f64d43ff0c18 | 2203 | |
mbed_official | 146:f64d43ff0c18 | 2204 | /*! |
mbed_official | 146:f64d43ff0c18 | 2205 | * @name Register UART_C4, field MAEN1[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 2206 | * |
mbed_official | 146:f64d43ff0c18 | 2207 | * See Match address operation for more information. |
mbed_official | 146:f64d43ff0c18 | 2208 | * |
mbed_official | 146:f64d43ff0c18 | 2209 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2210 | * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared. |
mbed_official | 146:f64d43ff0c18 | 2211 | * - 1 - All data received with the most significant bit cleared, is discarded. |
mbed_official | 146:f64d43ff0c18 | 2212 | * All data received with the most significant bit set, is compared with |
mbed_official | 146:f64d43ff0c18 | 2213 | * contents of MA1 register. If no match occurs, the data is discarded. If match |
mbed_official | 146:f64d43ff0c18 | 2214 | * occurs, data is transferred to the data buffer. This field must be cleared |
mbed_official | 146:f64d43ff0c18 | 2215 | * when C7816[ISO7816E] is set/enabled. |
mbed_official | 146:f64d43ff0c18 | 2216 | */ |
mbed_official | 146:f64d43ff0c18 | 2217 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2218 | #define BP_UART_C4_MAEN1 (7U) //!< Bit position for UART_C4_MAEN1. |
mbed_official | 146:f64d43ff0c18 | 2219 | #define BM_UART_C4_MAEN1 (0x80U) //!< Bit mask for UART_C4_MAEN1. |
mbed_official | 146:f64d43ff0c18 | 2220 | #define BS_UART_C4_MAEN1 (1U) //!< Bit field size in bits for UART_C4_MAEN1. |
mbed_official | 146:f64d43ff0c18 | 2221 | |
mbed_official | 146:f64d43ff0c18 | 2222 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2223 | //! @brief Read current value of the UART_C4_MAEN1 field. |
mbed_official | 146:f64d43ff0c18 | 2224 | #define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1)) |
mbed_official | 146:f64d43ff0c18 | 2225 | #endif |
mbed_official | 146:f64d43ff0c18 | 2226 | |
mbed_official | 146:f64d43ff0c18 | 2227 | //! @brief Format value for bitfield UART_C4_MAEN1. |
mbed_official | 146:f64d43ff0c18 | 2228 | #define BF_UART_C4_MAEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN1), uint8_t) & BM_UART_C4_MAEN1) |
mbed_official | 146:f64d43ff0c18 | 2229 | |
mbed_official | 146:f64d43ff0c18 | 2230 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2231 | //! @brief Set the MAEN1 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2232 | #define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2233 | #endif |
mbed_official | 146:f64d43ff0c18 | 2234 | //@} |
mbed_official | 146:f64d43ff0c18 | 2235 | |
mbed_official | 146:f64d43ff0c18 | 2236 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2237 | // HW_UART_C5 - UART Control Register 5 |
mbed_official | 146:f64d43ff0c18 | 2238 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2239 | |
mbed_official | 146:f64d43ff0c18 | 2240 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2241 | /*! |
mbed_official | 146:f64d43ff0c18 | 2242 | * @brief HW_UART_C5 - UART Control Register 5 (RW) |
mbed_official | 146:f64d43ff0c18 | 2243 | * |
mbed_official | 146:f64d43ff0c18 | 2244 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2245 | */ |
mbed_official | 146:f64d43ff0c18 | 2246 | typedef union _hw_uart_c5 |
mbed_official | 146:f64d43ff0c18 | 2247 | { |
mbed_official | 146:f64d43ff0c18 | 2248 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2249 | struct _hw_uart_c5_bitfields |
mbed_official | 146:f64d43ff0c18 | 2250 | { |
mbed_official | 146:f64d43ff0c18 | 2251 | uint8_t RESERVED0 : 3; //!< [2:0] |
mbed_official | 146:f64d43ff0c18 | 2252 | uint8_t LBKDDMAS : 1; //!< [3] LIN Break Detect DMA Select Bit |
mbed_official | 146:f64d43ff0c18 | 2253 | uint8_t ILDMAS : 1; //!< [4] Idle Line DMA Select |
mbed_official | 146:f64d43ff0c18 | 2254 | uint8_t RDMAS : 1; //!< [5] Receiver Full DMA Select |
mbed_official | 146:f64d43ff0c18 | 2255 | uint8_t TCDMAS : 1; //!< [6] Transmission Complete DMA Select |
mbed_official | 146:f64d43ff0c18 | 2256 | uint8_t TDMAS : 1; //!< [7] Transmitter DMA Select |
mbed_official | 146:f64d43ff0c18 | 2257 | } B; |
mbed_official | 146:f64d43ff0c18 | 2258 | } hw_uart_c5_t; |
mbed_official | 146:f64d43ff0c18 | 2259 | #endif |
mbed_official | 146:f64d43ff0c18 | 2260 | |
mbed_official | 146:f64d43ff0c18 | 2261 | /*! |
mbed_official | 146:f64d43ff0c18 | 2262 | * @name Constants and macros for entire UART_C5 register |
mbed_official | 146:f64d43ff0c18 | 2263 | */ |
mbed_official | 146:f64d43ff0c18 | 2264 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2265 | #define HW_UART_C5_ADDR(x) (REGS_UART_BASE(x) + 0xBU) |
mbed_official | 146:f64d43ff0c18 | 2266 | |
mbed_official | 146:f64d43ff0c18 | 2267 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2268 | #define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2269 | #define HW_UART_C5_RD(x) (HW_UART_C5(x).U) |
mbed_official | 146:f64d43ff0c18 | 2270 | #define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2271 | #define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2272 | #define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2273 | #define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2274 | #endif |
mbed_official | 146:f64d43ff0c18 | 2275 | //@} |
mbed_official | 146:f64d43ff0c18 | 2276 | |
mbed_official | 146:f64d43ff0c18 | 2277 | /* |
mbed_official | 146:f64d43ff0c18 | 2278 | * Constants & macros for individual UART_C5 bitfields |
mbed_official | 146:f64d43ff0c18 | 2279 | */ |
mbed_official | 146:f64d43ff0c18 | 2280 | |
mbed_official | 146:f64d43ff0c18 | 2281 | /*! |
mbed_official | 146:f64d43ff0c18 | 2282 | * @name Register UART_C5, field LBKDDMAS[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 2283 | * |
mbed_official | 146:f64d43ff0c18 | 2284 | * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or |
mbed_official | 146:f64d43ff0c18 | 2285 | * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is |
mbed_official | 146:f64d43ff0c18 | 2286 | * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless |
mbed_official | 146:f64d43ff0c18 | 2287 | * of the state of LBKDDMAS. |
mbed_official | 146:f64d43ff0c18 | 2288 | * |
mbed_official | 146:f64d43ff0c18 | 2289 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2290 | * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is |
mbed_official | 146:f64d43ff0c18 | 2291 | * asserted to request an interrupt service. |
mbed_official | 146:f64d43ff0c18 | 2292 | * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is |
mbed_official | 146:f64d43ff0c18 | 2293 | * asserted to request a DMA transfer. |
mbed_official | 146:f64d43ff0c18 | 2294 | */ |
mbed_official | 146:f64d43ff0c18 | 2295 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2296 | #define BP_UART_C5_LBKDDMAS (3U) //!< Bit position for UART_C5_LBKDDMAS. |
mbed_official | 146:f64d43ff0c18 | 2297 | #define BM_UART_C5_LBKDDMAS (0x08U) //!< Bit mask for UART_C5_LBKDDMAS. |
mbed_official | 146:f64d43ff0c18 | 2298 | #define BS_UART_C5_LBKDDMAS (1U) //!< Bit field size in bits for UART_C5_LBKDDMAS. |
mbed_official | 146:f64d43ff0c18 | 2299 | |
mbed_official | 146:f64d43ff0c18 | 2300 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2301 | //! @brief Read current value of the UART_C5_LBKDDMAS field. |
mbed_official | 146:f64d43ff0c18 | 2302 | #define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS)) |
mbed_official | 146:f64d43ff0c18 | 2303 | #endif |
mbed_official | 146:f64d43ff0c18 | 2304 | |
mbed_official | 146:f64d43ff0c18 | 2305 | //! @brief Format value for bitfield UART_C5_LBKDDMAS. |
mbed_official | 146:f64d43ff0c18 | 2306 | #define BF_UART_C5_LBKDDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_LBKDDMAS), uint8_t) & BM_UART_C5_LBKDDMAS) |
mbed_official | 146:f64d43ff0c18 | 2307 | |
mbed_official | 146:f64d43ff0c18 | 2308 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2309 | //! @brief Set the LBKDDMAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2310 | #define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2311 | #endif |
mbed_official | 146:f64d43ff0c18 | 2312 | //@} |
mbed_official | 146:f64d43ff0c18 | 2313 | |
mbed_official | 146:f64d43ff0c18 | 2314 | /*! |
mbed_official | 146:f64d43ff0c18 | 2315 | * @name Register UART_C5, field ILDMAS[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 2316 | * |
mbed_official | 146:f64d43ff0c18 | 2317 | * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA |
mbed_official | 146:f64d43ff0c18 | 2318 | * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE |
mbed_official | 146:f64d43ff0c18 | 2319 | * DMA and IDLE interrupt request signals are not asserted, regardless of the state |
mbed_official | 146:f64d43ff0c18 | 2320 | * of ILDMAS. |
mbed_official | 146:f64d43ff0c18 | 2321 | * |
mbed_official | 146:f64d43ff0c18 | 2322 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2323 | * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is |
mbed_official | 146:f64d43ff0c18 | 2324 | * asserted to request an interrupt service. |
mbed_official | 146:f64d43ff0c18 | 2325 | * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is |
mbed_official | 146:f64d43ff0c18 | 2326 | * asserted to request a DMA transfer. |
mbed_official | 146:f64d43ff0c18 | 2327 | */ |
mbed_official | 146:f64d43ff0c18 | 2328 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2329 | #define BP_UART_C5_ILDMAS (4U) //!< Bit position for UART_C5_ILDMAS. |
mbed_official | 146:f64d43ff0c18 | 2330 | #define BM_UART_C5_ILDMAS (0x10U) //!< Bit mask for UART_C5_ILDMAS. |
mbed_official | 146:f64d43ff0c18 | 2331 | #define BS_UART_C5_ILDMAS (1U) //!< Bit field size in bits for UART_C5_ILDMAS. |
mbed_official | 146:f64d43ff0c18 | 2332 | |
mbed_official | 146:f64d43ff0c18 | 2333 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2334 | //! @brief Read current value of the UART_C5_ILDMAS field. |
mbed_official | 146:f64d43ff0c18 | 2335 | #define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS)) |
mbed_official | 146:f64d43ff0c18 | 2336 | #endif |
mbed_official | 146:f64d43ff0c18 | 2337 | |
mbed_official | 146:f64d43ff0c18 | 2338 | //! @brief Format value for bitfield UART_C5_ILDMAS. |
mbed_official | 146:f64d43ff0c18 | 2339 | #define BF_UART_C5_ILDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_ILDMAS), uint8_t) & BM_UART_C5_ILDMAS) |
mbed_official | 146:f64d43ff0c18 | 2340 | |
mbed_official | 146:f64d43ff0c18 | 2341 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2342 | //! @brief Set the ILDMAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2343 | #define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2344 | #endif |
mbed_official | 146:f64d43ff0c18 | 2345 | //@} |
mbed_official | 146:f64d43ff0c18 | 2346 | |
mbed_official | 146:f64d43ff0c18 | 2347 | /*! |
mbed_official | 146:f64d43ff0c18 | 2348 | * @name Register UART_C5, field RDMAS[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 2349 | * |
mbed_official | 146:f64d43ff0c18 | 2350 | * Configures the receiver data register full flag, S1[RDRF], to generate |
mbed_official | 146:f64d43ff0c18 | 2351 | * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is |
mbed_official | 146:f64d43ff0c18 | 2352 | * set, the RDRF DMA and RDFR interrupt request signals are not asserted, |
mbed_official | 146:f64d43ff0c18 | 2353 | * regardless of the state of RDMAS. |
mbed_official | 146:f64d43ff0c18 | 2354 | * |
mbed_official | 146:f64d43ff0c18 | 2355 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2356 | * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is |
mbed_official | 146:f64d43ff0c18 | 2357 | * asserted to request an interrupt service. |
mbed_official | 146:f64d43ff0c18 | 2358 | * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is |
mbed_official | 146:f64d43ff0c18 | 2359 | * asserted to request a DMA transfer. |
mbed_official | 146:f64d43ff0c18 | 2360 | */ |
mbed_official | 146:f64d43ff0c18 | 2361 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2362 | #define BP_UART_C5_RDMAS (5U) //!< Bit position for UART_C5_RDMAS. |
mbed_official | 146:f64d43ff0c18 | 2363 | #define BM_UART_C5_RDMAS (0x20U) //!< Bit mask for UART_C5_RDMAS. |
mbed_official | 146:f64d43ff0c18 | 2364 | #define BS_UART_C5_RDMAS (1U) //!< Bit field size in bits for UART_C5_RDMAS. |
mbed_official | 146:f64d43ff0c18 | 2365 | |
mbed_official | 146:f64d43ff0c18 | 2366 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2367 | //! @brief Read current value of the UART_C5_RDMAS field. |
mbed_official | 146:f64d43ff0c18 | 2368 | #define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS)) |
mbed_official | 146:f64d43ff0c18 | 2369 | #endif |
mbed_official | 146:f64d43ff0c18 | 2370 | |
mbed_official | 146:f64d43ff0c18 | 2371 | //! @brief Format value for bitfield UART_C5_RDMAS. |
mbed_official | 146:f64d43ff0c18 | 2372 | #define BF_UART_C5_RDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_RDMAS), uint8_t) & BM_UART_C5_RDMAS) |
mbed_official | 146:f64d43ff0c18 | 2373 | |
mbed_official | 146:f64d43ff0c18 | 2374 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2375 | //! @brief Set the RDMAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2376 | #define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2377 | #endif |
mbed_official | 146:f64d43ff0c18 | 2378 | //@} |
mbed_official | 146:f64d43ff0c18 | 2379 | |
mbed_official | 146:f64d43ff0c18 | 2380 | /*! |
mbed_official | 146:f64d43ff0c18 | 2381 | * @name Register UART_C5, field TCDMAS[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 2382 | * |
mbed_official | 146:f64d43ff0c18 | 2383 | * Configures the transmission complete flag, S1[TC], to generate interrupt or |
mbed_official | 146:f64d43ff0c18 | 2384 | * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC |
mbed_official | 146:f64d43ff0c18 | 2385 | * interrupt request signals are not asserted when the S1[TC] flag is set, regardless |
mbed_official | 146:f64d43ff0c18 | 2386 | * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE] |
mbed_official | 146:f64d43ff0c18 | 2387 | * must be cleared, and D must not be written unless a DMA request is being serviced. |
mbed_official | 146:f64d43ff0c18 | 2388 | * |
mbed_official | 146:f64d43ff0c18 | 2389 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2390 | * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request |
mbed_official | 146:f64d43ff0c18 | 2391 | * signal is asserted to request an interrupt service. |
mbed_official | 146:f64d43ff0c18 | 2392 | * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request |
mbed_official | 146:f64d43ff0c18 | 2393 | * signal is asserted to request a DMA transfer. |
mbed_official | 146:f64d43ff0c18 | 2394 | */ |
mbed_official | 146:f64d43ff0c18 | 2395 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2396 | #define BP_UART_C5_TCDMAS (6U) //!< Bit position for UART_C5_TCDMAS. |
mbed_official | 146:f64d43ff0c18 | 2397 | #define BM_UART_C5_TCDMAS (0x40U) //!< Bit mask for UART_C5_TCDMAS. |
mbed_official | 146:f64d43ff0c18 | 2398 | #define BS_UART_C5_TCDMAS (1U) //!< Bit field size in bits for UART_C5_TCDMAS. |
mbed_official | 146:f64d43ff0c18 | 2399 | |
mbed_official | 146:f64d43ff0c18 | 2400 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2401 | //! @brief Read current value of the UART_C5_TCDMAS field. |
mbed_official | 146:f64d43ff0c18 | 2402 | #define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS)) |
mbed_official | 146:f64d43ff0c18 | 2403 | #endif |
mbed_official | 146:f64d43ff0c18 | 2404 | |
mbed_official | 146:f64d43ff0c18 | 2405 | //! @brief Format value for bitfield UART_C5_TCDMAS. |
mbed_official | 146:f64d43ff0c18 | 2406 | #define BF_UART_C5_TCDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TCDMAS), uint8_t) & BM_UART_C5_TCDMAS) |
mbed_official | 146:f64d43ff0c18 | 2407 | |
mbed_official | 146:f64d43ff0c18 | 2408 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2409 | //! @brief Set the TCDMAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2410 | #define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2411 | #endif |
mbed_official | 146:f64d43ff0c18 | 2412 | //@} |
mbed_official | 146:f64d43ff0c18 | 2413 | |
mbed_official | 146:f64d43ff0c18 | 2414 | /*! |
mbed_official | 146:f64d43ff0c18 | 2415 | * @name Register UART_C5, field TDMAS[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 2416 | * |
mbed_official | 146:f64d43ff0c18 | 2417 | * Configures the transmit data register empty flag, S1[TDRE], to generate |
mbed_official | 146:f64d43ff0c18 | 2418 | * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and |
mbed_official | 146:f64d43ff0c18 | 2419 | * TDRE interrupt request signals are not asserted when the TDRE flag is set, |
mbed_official | 146:f64d43ff0c18 | 2420 | * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE] |
mbed_official | 146:f64d43ff0c18 | 2421 | * must be cleared, and D must not be written unless a DMA request is being |
mbed_official | 146:f64d43ff0c18 | 2422 | * serviced. |
mbed_official | 146:f64d43ff0c18 | 2423 | * |
mbed_official | 146:f64d43ff0c18 | 2424 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2425 | * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt |
mbed_official | 146:f64d43ff0c18 | 2426 | * request signal is asserted to request interrupt service. |
mbed_official | 146:f64d43ff0c18 | 2427 | * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request |
mbed_official | 146:f64d43ff0c18 | 2428 | * signal is asserted to request a DMA transfer. |
mbed_official | 146:f64d43ff0c18 | 2429 | */ |
mbed_official | 146:f64d43ff0c18 | 2430 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2431 | #define BP_UART_C5_TDMAS (7U) //!< Bit position for UART_C5_TDMAS. |
mbed_official | 146:f64d43ff0c18 | 2432 | #define BM_UART_C5_TDMAS (0x80U) //!< Bit mask for UART_C5_TDMAS. |
mbed_official | 146:f64d43ff0c18 | 2433 | #define BS_UART_C5_TDMAS (1U) //!< Bit field size in bits for UART_C5_TDMAS. |
mbed_official | 146:f64d43ff0c18 | 2434 | |
mbed_official | 146:f64d43ff0c18 | 2435 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2436 | //! @brief Read current value of the UART_C5_TDMAS field. |
mbed_official | 146:f64d43ff0c18 | 2437 | #define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS)) |
mbed_official | 146:f64d43ff0c18 | 2438 | #endif |
mbed_official | 146:f64d43ff0c18 | 2439 | |
mbed_official | 146:f64d43ff0c18 | 2440 | //! @brief Format value for bitfield UART_C5_TDMAS. |
mbed_official | 146:f64d43ff0c18 | 2441 | #define BF_UART_C5_TDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TDMAS), uint8_t) & BM_UART_C5_TDMAS) |
mbed_official | 146:f64d43ff0c18 | 2442 | |
mbed_official | 146:f64d43ff0c18 | 2443 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2444 | //! @brief Set the TDMAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2445 | #define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2446 | #endif |
mbed_official | 146:f64d43ff0c18 | 2447 | //@} |
mbed_official | 146:f64d43ff0c18 | 2448 | |
mbed_official | 146:f64d43ff0c18 | 2449 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2450 | // HW_UART_ED - UART Extended Data Register |
mbed_official | 146:f64d43ff0c18 | 2451 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2452 | |
mbed_official | 146:f64d43ff0c18 | 2453 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2454 | /*! |
mbed_official | 146:f64d43ff0c18 | 2455 | * @brief HW_UART_ED - UART Extended Data Register (RO) |
mbed_official | 146:f64d43ff0c18 | 2456 | * |
mbed_official | 146:f64d43ff0c18 | 2457 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2458 | * |
mbed_official | 146:f64d43ff0c18 | 2459 | * This register contains additional information flags that are stored with a |
mbed_official | 146:f64d43ff0c18 | 2460 | * received dataword. This register may be read at any time but contains valid data |
mbed_official | 146:f64d43ff0c18 | 2461 | * only if there is a dataword in the receive FIFO. The data contained in this |
mbed_official | 146:f64d43ff0c18 | 2462 | * register represents additional information regarding the conditions on which a |
mbed_official | 146:f64d43ff0c18 | 2463 | * dataword was received. The importance of this data varies with the |
mbed_official | 146:f64d43ff0c18 | 2464 | * application, and in some cases maybe completely optional. These fields automatically |
mbed_official | 146:f64d43ff0c18 | 2465 | * update to reflect the conditions of the next dataword whenever D is read. If |
mbed_official | 146:f64d43ff0c18 | 2466 | * S1[NF] and S1[PF] have not been set since the last time the receive buffer was |
mbed_official | 146:f64d43ff0c18 | 2467 | * empty, the NOISY and PARITYE fields will be zero. |
mbed_official | 146:f64d43ff0c18 | 2468 | */ |
mbed_official | 146:f64d43ff0c18 | 2469 | typedef union _hw_uart_ed |
mbed_official | 146:f64d43ff0c18 | 2470 | { |
mbed_official | 146:f64d43ff0c18 | 2471 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2472 | struct _hw_uart_ed_bitfields |
mbed_official | 146:f64d43ff0c18 | 2473 | { |
mbed_official | 146:f64d43ff0c18 | 2474 | uint8_t RESERVED0 : 6; //!< [5:0] |
mbed_official | 146:f64d43ff0c18 | 2475 | uint8_t PARITYE : 1; //!< [6] |
mbed_official | 146:f64d43ff0c18 | 2476 | uint8_t NOISY : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 2477 | } B; |
mbed_official | 146:f64d43ff0c18 | 2478 | } hw_uart_ed_t; |
mbed_official | 146:f64d43ff0c18 | 2479 | #endif |
mbed_official | 146:f64d43ff0c18 | 2480 | |
mbed_official | 146:f64d43ff0c18 | 2481 | /*! |
mbed_official | 146:f64d43ff0c18 | 2482 | * @name Constants and macros for entire UART_ED register |
mbed_official | 146:f64d43ff0c18 | 2483 | */ |
mbed_official | 146:f64d43ff0c18 | 2484 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2485 | #define HW_UART_ED_ADDR(x) (REGS_UART_BASE(x) + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 2486 | |
mbed_official | 146:f64d43ff0c18 | 2487 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2488 | #define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2489 | #define HW_UART_ED_RD(x) (HW_UART_ED(x).U) |
mbed_official | 146:f64d43ff0c18 | 2490 | #endif |
mbed_official | 146:f64d43ff0c18 | 2491 | //@} |
mbed_official | 146:f64d43ff0c18 | 2492 | |
mbed_official | 146:f64d43ff0c18 | 2493 | /* |
mbed_official | 146:f64d43ff0c18 | 2494 | * Constants & macros for individual UART_ED bitfields |
mbed_official | 146:f64d43ff0c18 | 2495 | */ |
mbed_official | 146:f64d43ff0c18 | 2496 | |
mbed_official | 146:f64d43ff0c18 | 2497 | /*! |
mbed_official | 146:f64d43ff0c18 | 2498 | * @name Register UART_ED, field PARITYE[6] (RO) |
mbed_official | 146:f64d43ff0c18 | 2499 | * |
mbed_official | 146:f64d43ff0c18 | 2500 | * The current received dataword contained in D and C3[R8] was received with a |
mbed_official | 146:f64d43ff0c18 | 2501 | * parity error. |
mbed_official | 146:f64d43ff0c18 | 2502 | * |
mbed_official | 146:f64d43ff0c18 | 2503 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2504 | * - 0 - The dataword was received without a parity error. |
mbed_official | 146:f64d43ff0c18 | 2505 | * - 1 - The dataword was received with a parity error. |
mbed_official | 146:f64d43ff0c18 | 2506 | */ |
mbed_official | 146:f64d43ff0c18 | 2507 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2508 | #define BP_UART_ED_PARITYE (6U) //!< Bit position for UART_ED_PARITYE. |
mbed_official | 146:f64d43ff0c18 | 2509 | #define BM_UART_ED_PARITYE (0x40U) //!< Bit mask for UART_ED_PARITYE. |
mbed_official | 146:f64d43ff0c18 | 2510 | #define BS_UART_ED_PARITYE (1U) //!< Bit field size in bits for UART_ED_PARITYE. |
mbed_official | 146:f64d43ff0c18 | 2511 | |
mbed_official | 146:f64d43ff0c18 | 2512 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2513 | //! @brief Read current value of the UART_ED_PARITYE field. |
mbed_official | 146:f64d43ff0c18 | 2514 | #define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE)) |
mbed_official | 146:f64d43ff0c18 | 2515 | #endif |
mbed_official | 146:f64d43ff0c18 | 2516 | //@} |
mbed_official | 146:f64d43ff0c18 | 2517 | |
mbed_official | 146:f64d43ff0c18 | 2518 | /*! |
mbed_official | 146:f64d43ff0c18 | 2519 | * @name Register UART_ED, field NOISY[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 2520 | * |
mbed_official | 146:f64d43ff0c18 | 2521 | * The current received dataword contained in D and C3[R8] was received with |
mbed_official | 146:f64d43ff0c18 | 2522 | * noise. |
mbed_official | 146:f64d43ff0c18 | 2523 | * |
mbed_official | 146:f64d43ff0c18 | 2524 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2525 | * - 0 - The dataword was received without noise. |
mbed_official | 146:f64d43ff0c18 | 2526 | * - 1 - The data was received with noise. |
mbed_official | 146:f64d43ff0c18 | 2527 | */ |
mbed_official | 146:f64d43ff0c18 | 2528 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2529 | #define BP_UART_ED_NOISY (7U) //!< Bit position for UART_ED_NOISY. |
mbed_official | 146:f64d43ff0c18 | 2530 | #define BM_UART_ED_NOISY (0x80U) //!< Bit mask for UART_ED_NOISY. |
mbed_official | 146:f64d43ff0c18 | 2531 | #define BS_UART_ED_NOISY (1U) //!< Bit field size in bits for UART_ED_NOISY. |
mbed_official | 146:f64d43ff0c18 | 2532 | |
mbed_official | 146:f64d43ff0c18 | 2533 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2534 | //! @brief Read current value of the UART_ED_NOISY field. |
mbed_official | 146:f64d43ff0c18 | 2535 | #define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY)) |
mbed_official | 146:f64d43ff0c18 | 2536 | #endif |
mbed_official | 146:f64d43ff0c18 | 2537 | //@} |
mbed_official | 146:f64d43ff0c18 | 2538 | |
mbed_official | 146:f64d43ff0c18 | 2539 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2540 | // HW_UART_MODEM - UART Modem Register |
mbed_official | 146:f64d43ff0c18 | 2541 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2542 | |
mbed_official | 146:f64d43ff0c18 | 2543 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2544 | /*! |
mbed_official | 146:f64d43ff0c18 | 2545 | * @brief HW_UART_MODEM - UART Modem Register (RW) |
mbed_official | 146:f64d43ff0c18 | 2546 | * |
mbed_official | 146:f64d43ff0c18 | 2547 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2548 | * |
mbed_official | 146:f64d43ff0c18 | 2549 | * The MODEM register controls options for setting the modem configuration. |
mbed_official | 146:f64d43ff0c18 | 2550 | * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is |
mbed_official | 146:f64d43ff0c18 | 2551 | * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The |
mbed_official | 146:f64d43ff0c18 | 2552 | * ISO-7816 protocol does not use the RTS and CTS signals. |
mbed_official | 146:f64d43ff0c18 | 2553 | */ |
mbed_official | 146:f64d43ff0c18 | 2554 | typedef union _hw_uart_modem |
mbed_official | 146:f64d43ff0c18 | 2555 | { |
mbed_official | 146:f64d43ff0c18 | 2556 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2557 | struct _hw_uart_modem_bitfields |
mbed_official | 146:f64d43ff0c18 | 2558 | { |
mbed_official | 146:f64d43ff0c18 | 2559 | uint8_t TXCTSE : 1; //!< [0] Transmitter clear-to-send enable |
mbed_official | 146:f64d43ff0c18 | 2560 | uint8_t TXRTSE : 1; //!< [1] Transmitter request-to-send enable |
mbed_official | 146:f64d43ff0c18 | 2561 | uint8_t TXRTSPOL : 1; //!< [2] Transmitter request-to-send polarity |
mbed_official | 146:f64d43ff0c18 | 2562 | uint8_t RXRTSE : 1; //!< [3] Receiver request-to-send enable |
mbed_official | 146:f64d43ff0c18 | 2563 | uint8_t RESERVED0 : 4; //!< [7:4] |
mbed_official | 146:f64d43ff0c18 | 2564 | } B; |
mbed_official | 146:f64d43ff0c18 | 2565 | } hw_uart_modem_t; |
mbed_official | 146:f64d43ff0c18 | 2566 | #endif |
mbed_official | 146:f64d43ff0c18 | 2567 | |
mbed_official | 146:f64d43ff0c18 | 2568 | /*! |
mbed_official | 146:f64d43ff0c18 | 2569 | * @name Constants and macros for entire UART_MODEM register |
mbed_official | 146:f64d43ff0c18 | 2570 | */ |
mbed_official | 146:f64d43ff0c18 | 2571 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2572 | #define HW_UART_MODEM_ADDR(x) (REGS_UART_BASE(x) + 0xDU) |
mbed_official | 146:f64d43ff0c18 | 2573 | |
mbed_official | 146:f64d43ff0c18 | 2574 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2575 | #define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2576 | #define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U) |
mbed_official | 146:f64d43ff0c18 | 2577 | #define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2578 | #define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2579 | #define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2580 | #define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2581 | #endif |
mbed_official | 146:f64d43ff0c18 | 2582 | //@} |
mbed_official | 146:f64d43ff0c18 | 2583 | |
mbed_official | 146:f64d43ff0c18 | 2584 | /* |
mbed_official | 146:f64d43ff0c18 | 2585 | * Constants & macros for individual UART_MODEM bitfields |
mbed_official | 146:f64d43ff0c18 | 2586 | */ |
mbed_official | 146:f64d43ff0c18 | 2587 | |
mbed_official | 146:f64d43ff0c18 | 2588 | /*! |
mbed_official | 146:f64d43ff0c18 | 2589 | * @name Register UART_MODEM, field TXCTSE[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2590 | * |
mbed_official | 146:f64d43ff0c18 | 2591 | * TXCTSE controls the operation of the transmitter. TXCTSE can be set |
mbed_official | 146:f64d43ff0c18 | 2592 | * independently from the state of TXRTSE and RXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2593 | * |
mbed_official | 146:f64d43ff0c18 | 2594 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2595 | * - 0 - CTS has no effect on the transmitter. |
mbed_official | 146:f64d43ff0c18 | 2596 | * - 1 - Enables clear-to-send operation. The transmitter checks the state of |
mbed_official | 146:f64d43ff0c18 | 2597 | * CTS each time it is ready to send a character. If CTS is asserted, the |
mbed_official | 146:f64d43ff0c18 | 2598 | * character is sent. If CTS is deasserted, the signal TXD remains in the mark |
mbed_official | 146:f64d43ff0c18 | 2599 | * state and transmission is delayed until CTS is asserted. Changes in CTS as a |
mbed_official | 146:f64d43ff0c18 | 2600 | * character is being sent do not affect its transmission. |
mbed_official | 146:f64d43ff0c18 | 2601 | */ |
mbed_official | 146:f64d43ff0c18 | 2602 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2603 | #define BP_UART_MODEM_TXCTSE (0U) //!< Bit position for UART_MODEM_TXCTSE. |
mbed_official | 146:f64d43ff0c18 | 2604 | #define BM_UART_MODEM_TXCTSE (0x01U) //!< Bit mask for UART_MODEM_TXCTSE. |
mbed_official | 146:f64d43ff0c18 | 2605 | #define BS_UART_MODEM_TXCTSE (1U) //!< Bit field size in bits for UART_MODEM_TXCTSE. |
mbed_official | 146:f64d43ff0c18 | 2606 | |
mbed_official | 146:f64d43ff0c18 | 2607 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2608 | //! @brief Read current value of the UART_MODEM_TXCTSE field. |
mbed_official | 146:f64d43ff0c18 | 2609 | #define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE)) |
mbed_official | 146:f64d43ff0c18 | 2610 | #endif |
mbed_official | 146:f64d43ff0c18 | 2611 | |
mbed_official | 146:f64d43ff0c18 | 2612 | //! @brief Format value for bitfield UART_MODEM_TXCTSE. |
mbed_official | 146:f64d43ff0c18 | 2613 | #define BF_UART_MODEM_TXCTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXCTSE), uint8_t) & BM_UART_MODEM_TXCTSE) |
mbed_official | 146:f64d43ff0c18 | 2614 | |
mbed_official | 146:f64d43ff0c18 | 2615 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2616 | //! @brief Set the TXCTSE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2617 | #define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2618 | #endif |
mbed_official | 146:f64d43ff0c18 | 2619 | //@} |
mbed_official | 146:f64d43ff0c18 | 2620 | |
mbed_official | 146:f64d43ff0c18 | 2621 | /*! |
mbed_official | 146:f64d43ff0c18 | 2622 | * @name Register UART_MODEM, field TXRTSE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 2623 | * |
mbed_official | 146:f64d43ff0c18 | 2624 | * Controls RTS before and after a transmission. |
mbed_official | 146:f64d43ff0c18 | 2625 | * |
mbed_official | 146:f64d43ff0c18 | 2626 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2627 | * - 0 - The transmitter has no effect on RTS. |
mbed_official | 146:f64d43ff0c18 | 2628 | * - 1 - When a character is placed into an empty transmitter data buffer , RTS |
mbed_official | 146:f64d43ff0c18 | 2629 | * asserts one bit time before the start bit is transmitted. RTS deasserts |
mbed_official | 146:f64d43ff0c18 | 2630 | * one bit time after all characters in the transmitter data buffer and shift |
mbed_official | 146:f64d43ff0c18 | 2631 | * register are completely sent, including the last stop bit. (FIFO) (FIFO) |
mbed_official | 146:f64d43ff0c18 | 2632 | */ |
mbed_official | 146:f64d43ff0c18 | 2633 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2634 | #define BP_UART_MODEM_TXRTSE (1U) //!< Bit position for UART_MODEM_TXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2635 | #define BM_UART_MODEM_TXRTSE (0x02U) //!< Bit mask for UART_MODEM_TXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2636 | #define BS_UART_MODEM_TXRTSE (1U) //!< Bit field size in bits for UART_MODEM_TXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2637 | |
mbed_official | 146:f64d43ff0c18 | 2638 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2639 | //! @brief Read current value of the UART_MODEM_TXRTSE field. |
mbed_official | 146:f64d43ff0c18 | 2640 | #define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE)) |
mbed_official | 146:f64d43ff0c18 | 2641 | #endif |
mbed_official | 146:f64d43ff0c18 | 2642 | |
mbed_official | 146:f64d43ff0c18 | 2643 | //! @brief Format value for bitfield UART_MODEM_TXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2644 | #define BF_UART_MODEM_TXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSE), uint8_t) & BM_UART_MODEM_TXRTSE) |
mbed_official | 146:f64d43ff0c18 | 2645 | |
mbed_official | 146:f64d43ff0c18 | 2646 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2647 | //! @brief Set the TXRTSE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2648 | #define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2649 | #endif |
mbed_official | 146:f64d43ff0c18 | 2650 | //@} |
mbed_official | 146:f64d43ff0c18 | 2651 | |
mbed_official | 146:f64d43ff0c18 | 2652 | /*! |
mbed_official | 146:f64d43ff0c18 | 2653 | * @name Register UART_MODEM, field TXRTSPOL[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 2654 | * |
mbed_official | 146:f64d43ff0c18 | 2655 | * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the |
mbed_official | 146:f64d43ff0c18 | 2656 | * polarity of the receiver RTS. RTS will remain negated in the active low state |
mbed_official | 146:f64d43ff0c18 | 2657 | * unless TXRTSE is set. |
mbed_official | 146:f64d43ff0c18 | 2658 | * |
mbed_official | 146:f64d43ff0c18 | 2659 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2660 | * - 0 - Transmitter RTS is active low. |
mbed_official | 146:f64d43ff0c18 | 2661 | * - 1 - Transmitter RTS is active high. |
mbed_official | 146:f64d43ff0c18 | 2662 | */ |
mbed_official | 146:f64d43ff0c18 | 2663 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2664 | #define BP_UART_MODEM_TXRTSPOL (2U) //!< Bit position for UART_MODEM_TXRTSPOL. |
mbed_official | 146:f64d43ff0c18 | 2665 | #define BM_UART_MODEM_TXRTSPOL (0x04U) //!< Bit mask for UART_MODEM_TXRTSPOL. |
mbed_official | 146:f64d43ff0c18 | 2666 | #define BS_UART_MODEM_TXRTSPOL (1U) //!< Bit field size in bits for UART_MODEM_TXRTSPOL. |
mbed_official | 146:f64d43ff0c18 | 2667 | |
mbed_official | 146:f64d43ff0c18 | 2668 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2669 | //! @brief Read current value of the UART_MODEM_TXRTSPOL field. |
mbed_official | 146:f64d43ff0c18 | 2670 | #define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL)) |
mbed_official | 146:f64d43ff0c18 | 2671 | #endif |
mbed_official | 146:f64d43ff0c18 | 2672 | |
mbed_official | 146:f64d43ff0c18 | 2673 | //! @brief Format value for bitfield UART_MODEM_TXRTSPOL. |
mbed_official | 146:f64d43ff0c18 | 2674 | #define BF_UART_MODEM_TXRTSPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSPOL), uint8_t) & BM_UART_MODEM_TXRTSPOL) |
mbed_official | 146:f64d43ff0c18 | 2675 | |
mbed_official | 146:f64d43ff0c18 | 2676 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2677 | //! @brief Set the TXRTSPOL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2678 | #define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2679 | #endif |
mbed_official | 146:f64d43ff0c18 | 2680 | //@} |
mbed_official | 146:f64d43ff0c18 | 2681 | |
mbed_official | 146:f64d43ff0c18 | 2682 | /*! |
mbed_official | 146:f64d43ff0c18 | 2683 | * @name Register UART_MODEM, field RXRTSE[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 2684 | * |
mbed_official | 146:f64d43ff0c18 | 2685 | * Allows the RTS output to control the CTS input of the transmitting device to |
mbed_official | 146:f64d43ff0c18 | 2686 | * prevent receiver overrun. Do not set both RXRTSE and TXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2687 | * |
mbed_official | 146:f64d43ff0c18 | 2688 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2689 | * - 0 - The receiver has no effect on RTS. |
mbed_official | 146:f64d43ff0c18 | 2690 | * - 1 - RTS is deasserted if the number of characters in the receiver data |
mbed_official | 146:f64d43ff0c18 | 2691 | * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted |
mbed_official | 146:f64d43ff0c18 | 2692 | * when the number of characters in the receiver data register (FIFO) is less |
mbed_official | 146:f64d43ff0c18 | 2693 | * than RWFIFO[RXWATER]. |
mbed_official | 146:f64d43ff0c18 | 2694 | */ |
mbed_official | 146:f64d43ff0c18 | 2695 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2696 | #define BP_UART_MODEM_RXRTSE (3U) //!< Bit position for UART_MODEM_RXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2697 | #define BM_UART_MODEM_RXRTSE (0x08U) //!< Bit mask for UART_MODEM_RXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2698 | #define BS_UART_MODEM_RXRTSE (1U) //!< Bit field size in bits for UART_MODEM_RXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2699 | |
mbed_official | 146:f64d43ff0c18 | 2700 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2701 | //! @brief Read current value of the UART_MODEM_RXRTSE field. |
mbed_official | 146:f64d43ff0c18 | 2702 | #define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE)) |
mbed_official | 146:f64d43ff0c18 | 2703 | #endif |
mbed_official | 146:f64d43ff0c18 | 2704 | |
mbed_official | 146:f64d43ff0c18 | 2705 | //! @brief Format value for bitfield UART_MODEM_RXRTSE. |
mbed_official | 146:f64d43ff0c18 | 2706 | #define BF_UART_MODEM_RXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_RXRTSE), uint8_t) & BM_UART_MODEM_RXRTSE) |
mbed_official | 146:f64d43ff0c18 | 2707 | |
mbed_official | 146:f64d43ff0c18 | 2708 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2709 | //! @brief Set the RXRTSE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2710 | #define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2711 | #endif |
mbed_official | 146:f64d43ff0c18 | 2712 | //@} |
mbed_official | 146:f64d43ff0c18 | 2713 | |
mbed_official | 146:f64d43ff0c18 | 2714 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2715 | // HW_UART_IR - UART Infrared Register |
mbed_official | 146:f64d43ff0c18 | 2716 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2717 | |
mbed_official | 146:f64d43ff0c18 | 2718 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2719 | /*! |
mbed_official | 146:f64d43ff0c18 | 2720 | * @brief HW_UART_IR - UART Infrared Register (RW) |
mbed_official | 146:f64d43ff0c18 | 2721 | * |
mbed_official | 146:f64d43ff0c18 | 2722 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2723 | * |
mbed_official | 146:f64d43ff0c18 | 2724 | * The IR register controls options for setting the infrared configuration. |
mbed_official | 146:f64d43ff0c18 | 2725 | */ |
mbed_official | 146:f64d43ff0c18 | 2726 | typedef union _hw_uart_ir |
mbed_official | 146:f64d43ff0c18 | 2727 | { |
mbed_official | 146:f64d43ff0c18 | 2728 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2729 | struct _hw_uart_ir_bitfields |
mbed_official | 146:f64d43ff0c18 | 2730 | { |
mbed_official | 146:f64d43ff0c18 | 2731 | uint8_t TNP : 2; //!< [1:0] Transmitter narrow pulse |
mbed_official | 146:f64d43ff0c18 | 2732 | uint8_t IREN : 1; //!< [2] Infrared enable |
mbed_official | 146:f64d43ff0c18 | 2733 | uint8_t RESERVED0 : 5; //!< [7:3] |
mbed_official | 146:f64d43ff0c18 | 2734 | } B; |
mbed_official | 146:f64d43ff0c18 | 2735 | } hw_uart_ir_t; |
mbed_official | 146:f64d43ff0c18 | 2736 | #endif |
mbed_official | 146:f64d43ff0c18 | 2737 | |
mbed_official | 146:f64d43ff0c18 | 2738 | /*! |
mbed_official | 146:f64d43ff0c18 | 2739 | * @name Constants and macros for entire UART_IR register |
mbed_official | 146:f64d43ff0c18 | 2740 | */ |
mbed_official | 146:f64d43ff0c18 | 2741 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2742 | #define HW_UART_IR_ADDR(x) (REGS_UART_BASE(x) + 0xEU) |
mbed_official | 146:f64d43ff0c18 | 2743 | |
mbed_official | 146:f64d43ff0c18 | 2744 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2745 | #define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2746 | #define HW_UART_IR_RD(x) (HW_UART_IR(x).U) |
mbed_official | 146:f64d43ff0c18 | 2747 | #define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2748 | #define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2749 | #define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2750 | #define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2751 | #endif |
mbed_official | 146:f64d43ff0c18 | 2752 | //@} |
mbed_official | 146:f64d43ff0c18 | 2753 | |
mbed_official | 146:f64d43ff0c18 | 2754 | /* |
mbed_official | 146:f64d43ff0c18 | 2755 | * Constants & macros for individual UART_IR bitfields |
mbed_official | 146:f64d43ff0c18 | 2756 | */ |
mbed_official | 146:f64d43ff0c18 | 2757 | |
mbed_official | 146:f64d43ff0c18 | 2758 | /*! |
mbed_official | 146:f64d43ff0c18 | 2759 | * @name Register UART_IR, field TNP[1:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2760 | * |
mbed_official | 146:f64d43ff0c18 | 2761 | * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse. |
mbed_official | 146:f64d43ff0c18 | 2762 | * |
mbed_official | 146:f64d43ff0c18 | 2763 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2764 | * - 00 - 3/16. |
mbed_official | 146:f64d43ff0c18 | 2765 | * - 01 - 1/16. |
mbed_official | 146:f64d43ff0c18 | 2766 | * - 10 - 1/32. |
mbed_official | 146:f64d43ff0c18 | 2767 | * - 11 - 1/4. |
mbed_official | 146:f64d43ff0c18 | 2768 | */ |
mbed_official | 146:f64d43ff0c18 | 2769 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2770 | #define BP_UART_IR_TNP (0U) //!< Bit position for UART_IR_TNP. |
mbed_official | 146:f64d43ff0c18 | 2771 | #define BM_UART_IR_TNP (0x03U) //!< Bit mask for UART_IR_TNP. |
mbed_official | 146:f64d43ff0c18 | 2772 | #define BS_UART_IR_TNP (2U) //!< Bit field size in bits for UART_IR_TNP. |
mbed_official | 146:f64d43ff0c18 | 2773 | |
mbed_official | 146:f64d43ff0c18 | 2774 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2775 | //! @brief Read current value of the UART_IR_TNP field. |
mbed_official | 146:f64d43ff0c18 | 2776 | #define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP) |
mbed_official | 146:f64d43ff0c18 | 2777 | #endif |
mbed_official | 146:f64d43ff0c18 | 2778 | |
mbed_official | 146:f64d43ff0c18 | 2779 | //! @brief Format value for bitfield UART_IR_TNP. |
mbed_official | 146:f64d43ff0c18 | 2780 | #define BF_UART_IR_TNP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_TNP), uint8_t) & BM_UART_IR_TNP) |
mbed_official | 146:f64d43ff0c18 | 2781 | |
mbed_official | 146:f64d43ff0c18 | 2782 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2783 | //! @brief Set the TNP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2784 | #define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v))) |
mbed_official | 146:f64d43ff0c18 | 2785 | #endif |
mbed_official | 146:f64d43ff0c18 | 2786 | //@} |
mbed_official | 146:f64d43ff0c18 | 2787 | |
mbed_official | 146:f64d43ff0c18 | 2788 | /*! |
mbed_official | 146:f64d43ff0c18 | 2789 | * @name Register UART_IR, field IREN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 2790 | * |
mbed_official | 146:f64d43ff0c18 | 2791 | * Enables/disables the infrared modulation/demodulation. |
mbed_official | 146:f64d43ff0c18 | 2792 | * |
mbed_official | 146:f64d43ff0c18 | 2793 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2794 | * - 0 - IR disabled. |
mbed_official | 146:f64d43ff0c18 | 2795 | * - 1 - IR enabled. |
mbed_official | 146:f64d43ff0c18 | 2796 | */ |
mbed_official | 146:f64d43ff0c18 | 2797 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2798 | #define BP_UART_IR_IREN (2U) //!< Bit position for UART_IR_IREN. |
mbed_official | 146:f64d43ff0c18 | 2799 | #define BM_UART_IR_IREN (0x04U) //!< Bit mask for UART_IR_IREN. |
mbed_official | 146:f64d43ff0c18 | 2800 | #define BS_UART_IR_IREN (1U) //!< Bit field size in bits for UART_IR_IREN. |
mbed_official | 146:f64d43ff0c18 | 2801 | |
mbed_official | 146:f64d43ff0c18 | 2802 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2803 | //! @brief Read current value of the UART_IR_IREN field. |
mbed_official | 146:f64d43ff0c18 | 2804 | #define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN)) |
mbed_official | 146:f64d43ff0c18 | 2805 | #endif |
mbed_official | 146:f64d43ff0c18 | 2806 | |
mbed_official | 146:f64d43ff0c18 | 2807 | //! @brief Format value for bitfield UART_IR_IREN. |
mbed_official | 146:f64d43ff0c18 | 2808 | #define BF_UART_IR_IREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_IREN), uint8_t) & BM_UART_IR_IREN) |
mbed_official | 146:f64d43ff0c18 | 2809 | |
mbed_official | 146:f64d43ff0c18 | 2810 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2811 | //! @brief Set the IREN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2812 | #define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2813 | #endif |
mbed_official | 146:f64d43ff0c18 | 2814 | //@} |
mbed_official | 146:f64d43ff0c18 | 2815 | |
mbed_official | 146:f64d43ff0c18 | 2816 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2817 | // HW_UART_PFIFO - UART FIFO Parameters |
mbed_official | 146:f64d43ff0c18 | 2818 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2819 | |
mbed_official | 146:f64d43ff0c18 | 2820 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2821 | /*! |
mbed_official | 146:f64d43ff0c18 | 2822 | * @brief HW_UART_PFIFO - UART FIFO Parameters (RW) |
mbed_official | 146:f64d43ff0c18 | 2823 | * |
mbed_official | 146:f64d43ff0c18 | 2824 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2825 | * |
mbed_official | 146:f64d43ff0c18 | 2826 | * This register provides the ability for the programmer to turn on and off FIFO |
mbed_official | 146:f64d43ff0c18 | 2827 | * functionality. It also provides the size of the FIFO that has been |
mbed_official | 146:f64d43ff0c18 | 2828 | * implemented. This register may be read at any time. This register must be written only |
mbed_official | 146:f64d43ff0c18 | 2829 | * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is |
mbed_official | 146:f64d43ff0c18 | 2830 | * empty. |
mbed_official | 146:f64d43ff0c18 | 2831 | */ |
mbed_official | 146:f64d43ff0c18 | 2832 | typedef union _hw_uart_pfifo |
mbed_official | 146:f64d43ff0c18 | 2833 | { |
mbed_official | 146:f64d43ff0c18 | 2834 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2835 | struct _hw_uart_pfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 2836 | { |
mbed_official | 146:f64d43ff0c18 | 2837 | uint8_t RXFIFOSIZE : 3; //!< [2:0] Receive FIFO. Buffer Depth |
mbed_official | 146:f64d43ff0c18 | 2838 | uint8_t RXFE : 1; //!< [3] Receive FIFO Enable |
mbed_official | 146:f64d43ff0c18 | 2839 | uint8_t TXFIFOSIZE : 3; //!< [6:4] Transmit FIFO. Buffer Depth |
mbed_official | 146:f64d43ff0c18 | 2840 | uint8_t TXFE : 1; //!< [7] Transmit FIFO Enable |
mbed_official | 146:f64d43ff0c18 | 2841 | } B; |
mbed_official | 146:f64d43ff0c18 | 2842 | } hw_uart_pfifo_t; |
mbed_official | 146:f64d43ff0c18 | 2843 | #endif |
mbed_official | 146:f64d43ff0c18 | 2844 | |
mbed_official | 146:f64d43ff0c18 | 2845 | /*! |
mbed_official | 146:f64d43ff0c18 | 2846 | * @name Constants and macros for entire UART_PFIFO register |
mbed_official | 146:f64d43ff0c18 | 2847 | */ |
mbed_official | 146:f64d43ff0c18 | 2848 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2849 | #define HW_UART_PFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x10U) |
mbed_official | 146:f64d43ff0c18 | 2850 | |
mbed_official | 146:f64d43ff0c18 | 2851 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2852 | #define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 2853 | #define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 2854 | #define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2855 | #define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 2856 | #define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2857 | #define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2858 | #endif |
mbed_official | 146:f64d43ff0c18 | 2859 | //@} |
mbed_official | 146:f64d43ff0c18 | 2860 | |
mbed_official | 146:f64d43ff0c18 | 2861 | /* |
mbed_official | 146:f64d43ff0c18 | 2862 | * Constants & macros for individual UART_PFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 2863 | */ |
mbed_official | 146:f64d43ff0c18 | 2864 | |
mbed_official | 146:f64d43ff0c18 | 2865 | /*! |
mbed_official | 146:f64d43ff0c18 | 2866 | * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 2867 | * |
mbed_official | 146:f64d43ff0c18 | 2868 | * The maximum number of receive datawords that can be stored in the receive |
mbed_official | 146:f64d43ff0c18 | 2869 | * buffer before an overrun occurs. This field is read only. |
mbed_official | 146:f64d43ff0c18 | 2870 | * |
mbed_official | 146:f64d43ff0c18 | 2871 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2872 | * - 000 - Receive FIFO/Buffer depth = 1 dataword. |
mbed_official | 146:f64d43ff0c18 | 2873 | * - 001 - Receive FIFO/Buffer depth = 4 datawords. |
mbed_official | 146:f64d43ff0c18 | 2874 | * - 010 - Receive FIFO/Buffer depth = 8 datawords. |
mbed_official | 146:f64d43ff0c18 | 2875 | * - 011 - Receive FIFO/Buffer depth = 16 datawords. |
mbed_official | 146:f64d43ff0c18 | 2876 | * - 100 - Receive FIFO/Buffer depth = 32 datawords. |
mbed_official | 146:f64d43ff0c18 | 2877 | * - 101 - Receive FIFO/Buffer depth = 64 datawords. |
mbed_official | 146:f64d43ff0c18 | 2878 | * - 110 - Receive FIFO/Buffer depth = 128 datawords. |
mbed_official | 146:f64d43ff0c18 | 2879 | * - 111 - Reserved. |
mbed_official | 146:f64d43ff0c18 | 2880 | */ |
mbed_official | 146:f64d43ff0c18 | 2881 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2882 | #define BP_UART_PFIFO_RXFIFOSIZE (0U) //!< Bit position for UART_PFIFO_RXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2883 | #define BM_UART_PFIFO_RXFIFOSIZE (0x07U) //!< Bit mask for UART_PFIFO_RXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2884 | #define BS_UART_PFIFO_RXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2885 | |
mbed_official | 146:f64d43ff0c18 | 2886 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2887 | //! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. |
mbed_official | 146:f64d43ff0c18 | 2888 | #define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE) |
mbed_official | 146:f64d43ff0c18 | 2889 | #endif |
mbed_official | 146:f64d43ff0c18 | 2890 | //@} |
mbed_official | 146:f64d43ff0c18 | 2891 | |
mbed_official | 146:f64d43ff0c18 | 2892 | /*! |
mbed_official | 146:f64d43ff0c18 | 2893 | * @name Register UART_PFIFO, field RXFE[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 2894 | * |
mbed_official | 146:f64d43ff0c18 | 2895 | * When this field is set, the built in FIFO structure for the receive buffer is |
mbed_official | 146:f64d43ff0c18 | 2896 | * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field. |
mbed_official | 146:f64d43ff0c18 | 2897 | * If this field is not set, the receive buffer operates as a FIFO of depth one |
mbed_official | 146:f64d43ff0c18 | 2898 | * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be |
mbed_official | 146:f64d43ff0c18 | 2899 | * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH |
mbed_official | 146:f64d43ff0c18 | 2900 | * commands must be issued immediately after changing this field. |
mbed_official | 146:f64d43ff0c18 | 2901 | * |
mbed_official | 146:f64d43ff0c18 | 2902 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2903 | * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) |
mbed_official | 146:f64d43ff0c18 | 2904 | * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2905 | */ |
mbed_official | 146:f64d43ff0c18 | 2906 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2907 | #define BP_UART_PFIFO_RXFE (3U) //!< Bit position for UART_PFIFO_RXFE. |
mbed_official | 146:f64d43ff0c18 | 2908 | #define BM_UART_PFIFO_RXFE (0x08U) //!< Bit mask for UART_PFIFO_RXFE. |
mbed_official | 146:f64d43ff0c18 | 2909 | #define BS_UART_PFIFO_RXFE (1U) //!< Bit field size in bits for UART_PFIFO_RXFE. |
mbed_official | 146:f64d43ff0c18 | 2910 | |
mbed_official | 146:f64d43ff0c18 | 2911 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2912 | //! @brief Read current value of the UART_PFIFO_RXFE field. |
mbed_official | 146:f64d43ff0c18 | 2913 | #define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE)) |
mbed_official | 146:f64d43ff0c18 | 2914 | #endif |
mbed_official | 146:f64d43ff0c18 | 2915 | |
mbed_official | 146:f64d43ff0c18 | 2916 | //! @brief Format value for bitfield UART_PFIFO_RXFE. |
mbed_official | 146:f64d43ff0c18 | 2917 | #define BF_UART_PFIFO_RXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_RXFE), uint8_t) & BM_UART_PFIFO_RXFE) |
mbed_official | 146:f64d43ff0c18 | 2918 | |
mbed_official | 146:f64d43ff0c18 | 2919 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2920 | //! @brief Set the RXFE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2921 | #define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2922 | #endif |
mbed_official | 146:f64d43ff0c18 | 2923 | //@} |
mbed_official | 146:f64d43ff0c18 | 2924 | |
mbed_official | 146:f64d43ff0c18 | 2925 | /*! |
mbed_official | 146:f64d43ff0c18 | 2926 | * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO) |
mbed_official | 146:f64d43ff0c18 | 2927 | * |
mbed_official | 146:f64d43ff0c18 | 2928 | * The maximum number of transmit datawords that can be stored in the transmit |
mbed_official | 146:f64d43ff0c18 | 2929 | * buffer. This field is read only. |
mbed_official | 146:f64d43ff0c18 | 2930 | * |
mbed_official | 146:f64d43ff0c18 | 2931 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2932 | * - 000 - Transmit FIFO/Buffer depth = 1 dataword. |
mbed_official | 146:f64d43ff0c18 | 2933 | * - 001 - Transmit FIFO/Buffer depth = 4 datawords. |
mbed_official | 146:f64d43ff0c18 | 2934 | * - 010 - Transmit FIFO/Buffer depth = 8 datawords. |
mbed_official | 146:f64d43ff0c18 | 2935 | * - 011 - Transmit FIFO/Buffer depth = 16 datawords. |
mbed_official | 146:f64d43ff0c18 | 2936 | * - 100 - Transmit FIFO/Buffer depth = 32 datawords. |
mbed_official | 146:f64d43ff0c18 | 2937 | * - 101 - Transmit FIFO/Buffer depth = 64 datawords. |
mbed_official | 146:f64d43ff0c18 | 2938 | * - 110 - Transmit FIFO/Buffer depth = 128 datawords. |
mbed_official | 146:f64d43ff0c18 | 2939 | * - 111 - Reserved. |
mbed_official | 146:f64d43ff0c18 | 2940 | */ |
mbed_official | 146:f64d43ff0c18 | 2941 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2942 | #define BP_UART_PFIFO_TXFIFOSIZE (4U) //!< Bit position for UART_PFIFO_TXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2943 | #define BM_UART_PFIFO_TXFIFOSIZE (0x70U) //!< Bit mask for UART_PFIFO_TXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2944 | #define BS_UART_PFIFO_TXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2945 | |
mbed_official | 146:f64d43ff0c18 | 2946 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2947 | //! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. |
mbed_official | 146:f64d43ff0c18 | 2948 | #define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE) |
mbed_official | 146:f64d43ff0c18 | 2949 | #endif |
mbed_official | 146:f64d43ff0c18 | 2950 | //@} |
mbed_official | 146:f64d43ff0c18 | 2951 | |
mbed_official | 146:f64d43ff0c18 | 2952 | /*! |
mbed_official | 146:f64d43ff0c18 | 2953 | * @name Register UART_PFIFO, field TXFE[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 2954 | * |
mbed_official | 146:f64d43ff0c18 | 2955 | * When this field is set, the built in FIFO structure for the transmit buffer |
mbed_official | 146:f64d43ff0c18 | 2956 | * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this |
mbed_official | 146:f64d43ff0c18 | 2957 | * field is not set, the transmit buffer operates as a FIFO of depth one dataword |
mbed_official | 146:f64d43ff0c18 | 2958 | * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared |
mbed_official | 146:f64d43ff0c18 | 2959 | * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must |
mbed_official | 146:f64d43ff0c18 | 2960 | * be issued immediately after changing this field. |
mbed_official | 146:f64d43ff0c18 | 2961 | * |
mbed_official | 146:f64d43ff0c18 | 2962 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2963 | * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). |
mbed_official | 146:f64d43ff0c18 | 2964 | * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. |
mbed_official | 146:f64d43ff0c18 | 2965 | */ |
mbed_official | 146:f64d43ff0c18 | 2966 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2967 | #define BP_UART_PFIFO_TXFE (7U) //!< Bit position for UART_PFIFO_TXFE. |
mbed_official | 146:f64d43ff0c18 | 2968 | #define BM_UART_PFIFO_TXFE (0x80U) //!< Bit mask for UART_PFIFO_TXFE. |
mbed_official | 146:f64d43ff0c18 | 2969 | #define BS_UART_PFIFO_TXFE (1U) //!< Bit field size in bits for UART_PFIFO_TXFE. |
mbed_official | 146:f64d43ff0c18 | 2970 | |
mbed_official | 146:f64d43ff0c18 | 2971 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2972 | //! @brief Read current value of the UART_PFIFO_TXFE field. |
mbed_official | 146:f64d43ff0c18 | 2973 | #define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE)) |
mbed_official | 146:f64d43ff0c18 | 2974 | #endif |
mbed_official | 146:f64d43ff0c18 | 2975 | |
mbed_official | 146:f64d43ff0c18 | 2976 | //! @brief Format value for bitfield UART_PFIFO_TXFE. |
mbed_official | 146:f64d43ff0c18 | 2977 | #define BF_UART_PFIFO_TXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_TXFE), uint8_t) & BM_UART_PFIFO_TXFE) |
mbed_official | 146:f64d43ff0c18 | 2978 | |
mbed_official | 146:f64d43ff0c18 | 2979 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2980 | //! @brief Set the TXFE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2981 | #define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 2982 | #endif |
mbed_official | 146:f64d43ff0c18 | 2983 | //@} |
mbed_official | 146:f64d43ff0c18 | 2984 | |
mbed_official | 146:f64d43ff0c18 | 2985 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2986 | // HW_UART_CFIFO - UART FIFO Control Register |
mbed_official | 146:f64d43ff0c18 | 2987 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2988 | |
mbed_official | 146:f64d43ff0c18 | 2989 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2990 | /*! |
mbed_official | 146:f64d43ff0c18 | 2991 | * @brief HW_UART_CFIFO - UART FIFO Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 2992 | * |
mbed_official | 146:f64d43ff0c18 | 2993 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2994 | * |
mbed_official | 146:f64d43ff0c18 | 2995 | * This register provides the ability to program various control fields for FIFO |
mbed_official | 146:f64d43ff0c18 | 2996 | * operation. This register may be read or written at any time. Note that |
mbed_official | 146:f64d43ff0c18 | 2997 | * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action |
mbed_official | 146:f64d43ff0c18 | 2998 | * to prevent unintended/unpredictable behavior. Therefore, it is recommended that |
mbed_official | 146:f64d43ff0c18 | 2999 | * TE and RE be cleared prior to flushing the corresponding FIFO. |
mbed_official | 146:f64d43ff0c18 | 3000 | */ |
mbed_official | 146:f64d43ff0c18 | 3001 | typedef union _hw_uart_cfifo |
mbed_official | 146:f64d43ff0c18 | 3002 | { |
mbed_official | 146:f64d43ff0c18 | 3003 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3004 | struct _hw_uart_cfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 3005 | { |
mbed_official | 146:f64d43ff0c18 | 3006 | uint8_t RXUFE : 1; //!< [0] Receive FIFO Underflow Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3007 | uint8_t TXOFE : 1; //!< [1] Transmit FIFO Overflow Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3008 | uint8_t RXOFE : 1; //!< [2] Receive FIFO Overflow Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3009 | uint8_t RESERVED0 : 3; //!< [5:3] |
mbed_official | 146:f64d43ff0c18 | 3010 | uint8_t RXFLUSH : 1; //!< [6] Receive FIFO/Buffer Flush |
mbed_official | 146:f64d43ff0c18 | 3011 | uint8_t TXFLUSH : 1; //!< [7] Transmit FIFO/Buffer Flush |
mbed_official | 146:f64d43ff0c18 | 3012 | } B; |
mbed_official | 146:f64d43ff0c18 | 3013 | } hw_uart_cfifo_t; |
mbed_official | 146:f64d43ff0c18 | 3014 | #endif |
mbed_official | 146:f64d43ff0c18 | 3015 | |
mbed_official | 146:f64d43ff0c18 | 3016 | /*! |
mbed_official | 146:f64d43ff0c18 | 3017 | * @name Constants and macros for entire UART_CFIFO register |
mbed_official | 146:f64d43ff0c18 | 3018 | */ |
mbed_official | 146:f64d43ff0c18 | 3019 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3020 | #define HW_UART_CFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x11U) |
mbed_official | 146:f64d43ff0c18 | 3021 | |
mbed_official | 146:f64d43ff0c18 | 3022 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3023 | #define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3024 | #define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3025 | #define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3026 | #define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3027 | #define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3028 | #define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3029 | #endif |
mbed_official | 146:f64d43ff0c18 | 3030 | //@} |
mbed_official | 146:f64d43ff0c18 | 3031 | |
mbed_official | 146:f64d43ff0c18 | 3032 | /* |
mbed_official | 146:f64d43ff0c18 | 3033 | * Constants & macros for individual UART_CFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 3034 | */ |
mbed_official | 146:f64d43ff0c18 | 3035 | |
mbed_official | 146:f64d43ff0c18 | 3036 | /*! |
mbed_official | 146:f64d43ff0c18 | 3037 | * @name Register UART_CFIFO, field RXUFE[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3038 | * |
mbed_official | 146:f64d43ff0c18 | 3039 | * When this field is set, the RXUF flag generates an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3040 | * |
mbed_official | 146:f64d43ff0c18 | 3041 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3042 | * - 0 - RXUF flag does not generate an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3043 | * - 1 - RXUF flag generates an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3044 | */ |
mbed_official | 146:f64d43ff0c18 | 3045 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3046 | #define BP_UART_CFIFO_RXUFE (0U) //!< Bit position for UART_CFIFO_RXUFE. |
mbed_official | 146:f64d43ff0c18 | 3047 | #define BM_UART_CFIFO_RXUFE (0x01U) //!< Bit mask for UART_CFIFO_RXUFE. |
mbed_official | 146:f64d43ff0c18 | 3048 | #define BS_UART_CFIFO_RXUFE (1U) //!< Bit field size in bits for UART_CFIFO_RXUFE. |
mbed_official | 146:f64d43ff0c18 | 3049 | |
mbed_official | 146:f64d43ff0c18 | 3050 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3051 | //! @brief Read current value of the UART_CFIFO_RXUFE field. |
mbed_official | 146:f64d43ff0c18 | 3052 | #define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE)) |
mbed_official | 146:f64d43ff0c18 | 3053 | #endif |
mbed_official | 146:f64d43ff0c18 | 3054 | |
mbed_official | 146:f64d43ff0c18 | 3055 | //! @brief Format value for bitfield UART_CFIFO_RXUFE. |
mbed_official | 146:f64d43ff0c18 | 3056 | #define BF_UART_CFIFO_RXUFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXUFE), uint8_t) & BM_UART_CFIFO_RXUFE) |
mbed_official | 146:f64d43ff0c18 | 3057 | |
mbed_official | 146:f64d43ff0c18 | 3058 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3059 | //! @brief Set the RXUFE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3060 | #define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3061 | #endif |
mbed_official | 146:f64d43ff0c18 | 3062 | //@} |
mbed_official | 146:f64d43ff0c18 | 3063 | |
mbed_official | 146:f64d43ff0c18 | 3064 | /*! |
mbed_official | 146:f64d43ff0c18 | 3065 | * @name Register UART_CFIFO, field TXOFE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 3066 | * |
mbed_official | 146:f64d43ff0c18 | 3067 | * When this field is set, the TXOF flag generates an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3068 | * |
mbed_official | 146:f64d43ff0c18 | 3069 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3070 | * - 0 - TXOF flag does not generate an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3071 | * - 1 - TXOF flag generates an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3072 | */ |
mbed_official | 146:f64d43ff0c18 | 3073 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3074 | #define BP_UART_CFIFO_TXOFE (1U) //!< Bit position for UART_CFIFO_TXOFE. |
mbed_official | 146:f64d43ff0c18 | 3075 | #define BM_UART_CFIFO_TXOFE (0x02U) //!< Bit mask for UART_CFIFO_TXOFE. |
mbed_official | 146:f64d43ff0c18 | 3076 | #define BS_UART_CFIFO_TXOFE (1U) //!< Bit field size in bits for UART_CFIFO_TXOFE. |
mbed_official | 146:f64d43ff0c18 | 3077 | |
mbed_official | 146:f64d43ff0c18 | 3078 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3079 | //! @brief Read current value of the UART_CFIFO_TXOFE field. |
mbed_official | 146:f64d43ff0c18 | 3080 | #define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE)) |
mbed_official | 146:f64d43ff0c18 | 3081 | #endif |
mbed_official | 146:f64d43ff0c18 | 3082 | |
mbed_official | 146:f64d43ff0c18 | 3083 | //! @brief Format value for bitfield UART_CFIFO_TXOFE. |
mbed_official | 146:f64d43ff0c18 | 3084 | #define BF_UART_CFIFO_TXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXOFE), uint8_t) & BM_UART_CFIFO_TXOFE) |
mbed_official | 146:f64d43ff0c18 | 3085 | |
mbed_official | 146:f64d43ff0c18 | 3086 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3087 | //! @brief Set the TXOFE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3088 | #define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3089 | #endif |
mbed_official | 146:f64d43ff0c18 | 3090 | //@} |
mbed_official | 146:f64d43ff0c18 | 3091 | |
mbed_official | 146:f64d43ff0c18 | 3092 | /*! |
mbed_official | 146:f64d43ff0c18 | 3093 | * @name Register UART_CFIFO, field RXOFE[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 3094 | * |
mbed_official | 146:f64d43ff0c18 | 3095 | * When this field is set, the RXOF flag generates an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3096 | * |
mbed_official | 146:f64d43ff0c18 | 3097 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3098 | * - 0 - RXOF flag does not generate an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3099 | * - 1 - RXOF flag generates an interrupt to the host. |
mbed_official | 146:f64d43ff0c18 | 3100 | */ |
mbed_official | 146:f64d43ff0c18 | 3101 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3102 | #define BP_UART_CFIFO_RXOFE (2U) //!< Bit position for UART_CFIFO_RXOFE. |
mbed_official | 146:f64d43ff0c18 | 3103 | #define BM_UART_CFIFO_RXOFE (0x04U) //!< Bit mask for UART_CFIFO_RXOFE. |
mbed_official | 146:f64d43ff0c18 | 3104 | #define BS_UART_CFIFO_RXOFE (1U) //!< Bit field size in bits for UART_CFIFO_RXOFE. |
mbed_official | 146:f64d43ff0c18 | 3105 | |
mbed_official | 146:f64d43ff0c18 | 3106 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3107 | //! @brief Read current value of the UART_CFIFO_RXOFE field. |
mbed_official | 146:f64d43ff0c18 | 3108 | #define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE)) |
mbed_official | 146:f64d43ff0c18 | 3109 | #endif |
mbed_official | 146:f64d43ff0c18 | 3110 | |
mbed_official | 146:f64d43ff0c18 | 3111 | //! @brief Format value for bitfield UART_CFIFO_RXOFE. |
mbed_official | 146:f64d43ff0c18 | 3112 | #define BF_UART_CFIFO_RXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXOFE), uint8_t) & BM_UART_CFIFO_RXOFE) |
mbed_official | 146:f64d43ff0c18 | 3113 | |
mbed_official | 146:f64d43ff0c18 | 3114 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3115 | //! @brief Set the RXOFE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3116 | #define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3117 | #endif |
mbed_official | 146:f64d43ff0c18 | 3118 | //@} |
mbed_official | 146:f64d43ff0c18 | 3119 | |
mbed_official | 146:f64d43ff0c18 | 3120 | /*! |
mbed_official | 146:f64d43ff0c18 | 3121 | * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 3122 | * |
mbed_official | 146:f64d43ff0c18 | 3123 | * Writing to this field causes all data that is stored in the receive |
mbed_official | 146:f64d43ff0c18 | 3124 | * FIFO/buffer to be flushed. This does not affect data that is in the receive shift |
mbed_official | 146:f64d43ff0c18 | 3125 | * register. |
mbed_official | 146:f64d43ff0c18 | 3126 | * |
mbed_official | 146:f64d43ff0c18 | 3127 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3128 | * - 0 - No flush operation occurs. |
mbed_official | 146:f64d43ff0c18 | 3129 | * - 1 - All data in the receive FIFO/buffer is cleared out. |
mbed_official | 146:f64d43ff0c18 | 3130 | */ |
mbed_official | 146:f64d43ff0c18 | 3131 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3132 | #define BP_UART_CFIFO_RXFLUSH (6U) //!< Bit position for UART_CFIFO_RXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3133 | #define BM_UART_CFIFO_RXFLUSH (0x40U) //!< Bit mask for UART_CFIFO_RXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3134 | #define BS_UART_CFIFO_RXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_RXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3135 | |
mbed_official | 146:f64d43ff0c18 | 3136 | //! @brief Format value for bitfield UART_CFIFO_RXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3137 | #define BF_UART_CFIFO_RXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXFLUSH), uint8_t) & BM_UART_CFIFO_RXFLUSH) |
mbed_official | 146:f64d43ff0c18 | 3138 | |
mbed_official | 146:f64d43ff0c18 | 3139 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3140 | //! @brief Set the RXFLUSH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3141 | #define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3142 | #endif |
mbed_official | 146:f64d43ff0c18 | 3143 | //@} |
mbed_official | 146:f64d43ff0c18 | 3144 | |
mbed_official | 146:f64d43ff0c18 | 3145 | /*! |
mbed_official | 146:f64d43ff0c18 | 3146 | * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 3147 | * |
mbed_official | 146:f64d43ff0c18 | 3148 | * Writing to this field causes all data that is stored in the transmit |
mbed_official | 146:f64d43ff0c18 | 3149 | * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift |
mbed_official | 146:f64d43ff0c18 | 3150 | * register. |
mbed_official | 146:f64d43ff0c18 | 3151 | * |
mbed_official | 146:f64d43ff0c18 | 3152 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3153 | * - 0 - No flush operation occurs. |
mbed_official | 146:f64d43ff0c18 | 3154 | * - 1 - All data in the transmit FIFO/Buffer is cleared out. |
mbed_official | 146:f64d43ff0c18 | 3155 | */ |
mbed_official | 146:f64d43ff0c18 | 3156 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3157 | #define BP_UART_CFIFO_TXFLUSH (7U) //!< Bit position for UART_CFIFO_TXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3158 | #define BM_UART_CFIFO_TXFLUSH (0x80U) //!< Bit mask for UART_CFIFO_TXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3159 | #define BS_UART_CFIFO_TXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_TXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3160 | |
mbed_official | 146:f64d43ff0c18 | 3161 | //! @brief Format value for bitfield UART_CFIFO_TXFLUSH. |
mbed_official | 146:f64d43ff0c18 | 3162 | #define BF_UART_CFIFO_TXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXFLUSH), uint8_t) & BM_UART_CFIFO_TXFLUSH) |
mbed_official | 146:f64d43ff0c18 | 3163 | |
mbed_official | 146:f64d43ff0c18 | 3164 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3165 | //! @brief Set the TXFLUSH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3166 | #define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3167 | #endif |
mbed_official | 146:f64d43ff0c18 | 3168 | //@} |
mbed_official | 146:f64d43ff0c18 | 3169 | |
mbed_official | 146:f64d43ff0c18 | 3170 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3171 | // HW_UART_SFIFO - UART FIFO Status Register |
mbed_official | 146:f64d43ff0c18 | 3172 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3173 | |
mbed_official | 146:f64d43ff0c18 | 3174 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3175 | /*! |
mbed_official | 146:f64d43ff0c18 | 3176 | * @brief HW_UART_SFIFO - UART FIFO Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 3177 | * |
mbed_official | 146:f64d43ff0c18 | 3178 | * Reset value: 0xC0U |
mbed_official | 146:f64d43ff0c18 | 3179 | * |
mbed_official | 146:f64d43ff0c18 | 3180 | * This register provides status information regarding the transmit and receiver |
mbed_official | 146:f64d43ff0c18 | 3181 | * buffers/FIFOs, including interrupt information. This register may be written |
mbed_official | 146:f64d43ff0c18 | 3182 | * to or read at any time. |
mbed_official | 146:f64d43ff0c18 | 3183 | */ |
mbed_official | 146:f64d43ff0c18 | 3184 | typedef union _hw_uart_sfifo |
mbed_official | 146:f64d43ff0c18 | 3185 | { |
mbed_official | 146:f64d43ff0c18 | 3186 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3187 | struct _hw_uart_sfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 3188 | { |
mbed_official | 146:f64d43ff0c18 | 3189 | uint8_t RXUF : 1; //!< [0] Receiver Buffer Underflow Flag |
mbed_official | 146:f64d43ff0c18 | 3190 | uint8_t TXOF : 1; //!< [1] Transmitter Buffer Overflow Flag |
mbed_official | 146:f64d43ff0c18 | 3191 | uint8_t RXOF : 1; //!< [2] Receiver Buffer Overflow Flag |
mbed_official | 146:f64d43ff0c18 | 3192 | uint8_t RESERVED0 : 3; //!< [5:3] |
mbed_official | 146:f64d43ff0c18 | 3193 | uint8_t RXEMPT : 1; //!< [6] Receive Buffer/FIFO Empty |
mbed_official | 146:f64d43ff0c18 | 3194 | uint8_t TXEMPT : 1; //!< [7] Transmit Buffer/FIFO Empty |
mbed_official | 146:f64d43ff0c18 | 3195 | } B; |
mbed_official | 146:f64d43ff0c18 | 3196 | } hw_uart_sfifo_t; |
mbed_official | 146:f64d43ff0c18 | 3197 | #endif |
mbed_official | 146:f64d43ff0c18 | 3198 | |
mbed_official | 146:f64d43ff0c18 | 3199 | /*! |
mbed_official | 146:f64d43ff0c18 | 3200 | * @name Constants and macros for entire UART_SFIFO register |
mbed_official | 146:f64d43ff0c18 | 3201 | */ |
mbed_official | 146:f64d43ff0c18 | 3202 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3203 | #define HW_UART_SFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x12U) |
mbed_official | 146:f64d43ff0c18 | 3204 | |
mbed_official | 146:f64d43ff0c18 | 3205 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3206 | #define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3207 | #define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3208 | #define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3209 | #define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3210 | #define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3211 | #define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3212 | #endif |
mbed_official | 146:f64d43ff0c18 | 3213 | //@} |
mbed_official | 146:f64d43ff0c18 | 3214 | |
mbed_official | 146:f64d43ff0c18 | 3215 | /* |
mbed_official | 146:f64d43ff0c18 | 3216 | * Constants & macros for individual UART_SFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 3217 | */ |
mbed_official | 146:f64d43ff0c18 | 3218 | |
mbed_official | 146:f64d43ff0c18 | 3219 | /*! |
mbed_official | 146:f64d43ff0c18 | 3220 | * @name Register UART_SFIFO, field RXUF[0] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3221 | * |
mbed_official | 146:f64d43ff0c18 | 3222 | * Indicates that more data has been read from the receive buffer than was |
mbed_official | 146:f64d43ff0c18 | 3223 | * present. This field will assert regardless of the value of CFIFO[RXUFE]. However, |
mbed_official | 146:f64d43ff0c18 | 3224 | * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag |
mbed_official | 146:f64d43ff0c18 | 3225 | * is cleared by writing a 1. |
mbed_official | 146:f64d43ff0c18 | 3226 | * |
mbed_official | 146:f64d43ff0c18 | 3227 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3228 | * - 0 - No receive buffer underflow has occurred since the last time the flag |
mbed_official | 146:f64d43ff0c18 | 3229 | * was cleared. |
mbed_official | 146:f64d43ff0c18 | 3230 | * - 1 - At least one receive buffer underflow has occurred since the last time |
mbed_official | 146:f64d43ff0c18 | 3231 | * the flag was cleared. |
mbed_official | 146:f64d43ff0c18 | 3232 | */ |
mbed_official | 146:f64d43ff0c18 | 3233 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3234 | #define BP_UART_SFIFO_RXUF (0U) //!< Bit position for UART_SFIFO_RXUF. |
mbed_official | 146:f64d43ff0c18 | 3235 | #define BM_UART_SFIFO_RXUF (0x01U) //!< Bit mask for UART_SFIFO_RXUF. |
mbed_official | 146:f64d43ff0c18 | 3236 | #define BS_UART_SFIFO_RXUF (1U) //!< Bit field size in bits for UART_SFIFO_RXUF. |
mbed_official | 146:f64d43ff0c18 | 3237 | |
mbed_official | 146:f64d43ff0c18 | 3238 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3239 | //! @brief Read current value of the UART_SFIFO_RXUF field. |
mbed_official | 146:f64d43ff0c18 | 3240 | #define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF)) |
mbed_official | 146:f64d43ff0c18 | 3241 | #endif |
mbed_official | 146:f64d43ff0c18 | 3242 | |
mbed_official | 146:f64d43ff0c18 | 3243 | //! @brief Format value for bitfield UART_SFIFO_RXUF. |
mbed_official | 146:f64d43ff0c18 | 3244 | #define BF_UART_SFIFO_RXUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXUF), uint8_t) & BM_UART_SFIFO_RXUF) |
mbed_official | 146:f64d43ff0c18 | 3245 | |
mbed_official | 146:f64d43ff0c18 | 3246 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3247 | //! @brief Set the RXUF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3248 | #define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3249 | #endif |
mbed_official | 146:f64d43ff0c18 | 3250 | //@} |
mbed_official | 146:f64d43ff0c18 | 3251 | |
mbed_official | 146:f64d43ff0c18 | 3252 | /*! |
mbed_official | 146:f64d43ff0c18 | 3253 | * @name Register UART_SFIFO, field TXOF[1] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3254 | * |
mbed_official | 146:f64d43ff0c18 | 3255 | * Indicates that more data has been written to the transmit buffer than it can |
mbed_official | 146:f64d43ff0c18 | 3256 | * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However, |
mbed_official | 146:f64d43ff0c18 | 3257 | * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This |
mbed_official | 146:f64d43ff0c18 | 3258 | * flag is cleared by writing a 1. |
mbed_official | 146:f64d43ff0c18 | 3259 | * |
mbed_official | 146:f64d43ff0c18 | 3260 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3261 | * - 0 - No transmit buffer overflow has occurred since the last time the flag |
mbed_official | 146:f64d43ff0c18 | 3262 | * was cleared. |
mbed_official | 146:f64d43ff0c18 | 3263 | * - 1 - At least one transmit buffer overflow has occurred since the last time |
mbed_official | 146:f64d43ff0c18 | 3264 | * the flag was cleared. |
mbed_official | 146:f64d43ff0c18 | 3265 | */ |
mbed_official | 146:f64d43ff0c18 | 3266 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3267 | #define BP_UART_SFIFO_TXOF (1U) //!< Bit position for UART_SFIFO_TXOF. |
mbed_official | 146:f64d43ff0c18 | 3268 | #define BM_UART_SFIFO_TXOF (0x02U) //!< Bit mask for UART_SFIFO_TXOF. |
mbed_official | 146:f64d43ff0c18 | 3269 | #define BS_UART_SFIFO_TXOF (1U) //!< Bit field size in bits for UART_SFIFO_TXOF. |
mbed_official | 146:f64d43ff0c18 | 3270 | |
mbed_official | 146:f64d43ff0c18 | 3271 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3272 | //! @brief Read current value of the UART_SFIFO_TXOF field. |
mbed_official | 146:f64d43ff0c18 | 3273 | #define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF)) |
mbed_official | 146:f64d43ff0c18 | 3274 | #endif |
mbed_official | 146:f64d43ff0c18 | 3275 | |
mbed_official | 146:f64d43ff0c18 | 3276 | //! @brief Format value for bitfield UART_SFIFO_TXOF. |
mbed_official | 146:f64d43ff0c18 | 3277 | #define BF_UART_SFIFO_TXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_TXOF), uint8_t) & BM_UART_SFIFO_TXOF) |
mbed_official | 146:f64d43ff0c18 | 3278 | |
mbed_official | 146:f64d43ff0c18 | 3279 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3280 | //! @brief Set the TXOF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3281 | #define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3282 | #endif |
mbed_official | 146:f64d43ff0c18 | 3283 | //@} |
mbed_official | 146:f64d43ff0c18 | 3284 | |
mbed_official | 146:f64d43ff0c18 | 3285 | /*! |
mbed_official | 146:f64d43ff0c18 | 3286 | * @name Register UART_SFIFO, field RXOF[2] (W1C) |
mbed_official | 146:f64d43ff0c18 | 3287 | * |
mbed_official | 146:f64d43ff0c18 | 3288 | * Indicates that more data has been written to the receive buffer than it can |
mbed_official | 146:f64d43ff0c18 | 3289 | * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However, |
mbed_official | 146:f64d43ff0c18 | 3290 | * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag |
mbed_official | 146:f64d43ff0c18 | 3291 | * is cleared by writing a 1. |
mbed_official | 146:f64d43ff0c18 | 3292 | * |
mbed_official | 146:f64d43ff0c18 | 3293 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3294 | * - 0 - No receive buffer overflow has occurred since the last time the flag |
mbed_official | 146:f64d43ff0c18 | 3295 | * was cleared. |
mbed_official | 146:f64d43ff0c18 | 3296 | * - 1 - At least one receive buffer overflow has occurred since the last time |
mbed_official | 146:f64d43ff0c18 | 3297 | * the flag was cleared. |
mbed_official | 146:f64d43ff0c18 | 3298 | */ |
mbed_official | 146:f64d43ff0c18 | 3299 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3300 | #define BP_UART_SFIFO_RXOF (2U) //!< Bit position for UART_SFIFO_RXOF. |
mbed_official | 146:f64d43ff0c18 | 3301 | #define BM_UART_SFIFO_RXOF (0x04U) //!< Bit mask for UART_SFIFO_RXOF. |
mbed_official | 146:f64d43ff0c18 | 3302 | #define BS_UART_SFIFO_RXOF (1U) //!< Bit field size in bits for UART_SFIFO_RXOF. |
mbed_official | 146:f64d43ff0c18 | 3303 | |
mbed_official | 146:f64d43ff0c18 | 3304 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3305 | //! @brief Read current value of the UART_SFIFO_RXOF field. |
mbed_official | 146:f64d43ff0c18 | 3306 | #define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF)) |
mbed_official | 146:f64d43ff0c18 | 3307 | #endif |
mbed_official | 146:f64d43ff0c18 | 3308 | |
mbed_official | 146:f64d43ff0c18 | 3309 | //! @brief Format value for bitfield UART_SFIFO_RXOF. |
mbed_official | 146:f64d43ff0c18 | 3310 | #define BF_UART_SFIFO_RXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXOF), uint8_t) & BM_UART_SFIFO_RXOF) |
mbed_official | 146:f64d43ff0c18 | 3311 | |
mbed_official | 146:f64d43ff0c18 | 3312 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3313 | //! @brief Set the RXOF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3314 | #define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3315 | #endif |
mbed_official | 146:f64d43ff0c18 | 3316 | //@} |
mbed_official | 146:f64d43ff0c18 | 3317 | |
mbed_official | 146:f64d43ff0c18 | 3318 | /*! |
mbed_official | 146:f64d43ff0c18 | 3319 | * @name Register UART_SFIFO, field RXEMPT[6] (RO) |
mbed_official | 146:f64d43ff0c18 | 3320 | * |
mbed_official | 146:f64d43ff0c18 | 3321 | * Asserts when there is no data in the receive FIFO/Buffer. This field does not |
mbed_official | 146:f64d43ff0c18 | 3322 | * take into account data that is in the receive shift register. |
mbed_official | 146:f64d43ff0c18 | 3323 | * |
mbed_official | 146:f64d43ff0c18 | 3324 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3325 | * - 0 - Receive buffer is not empty. |
mbed_official | 146:f64d43ff0c18 | 3326 | * - 1 - Receive buffer is empty. |
mbed_official | 146:f64d43ff0c18 | 3327 | */ |
mbed_official | 146:f64d43ff0c18 | 3328 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3329 | #define BP_UART_SFIFO_RXEMPT (6U) //!< Bit position for UART_SFIFO_RXEMPT. |
mbed_official | 146:f64d43ff0c18 | 3330 | #define BM_UART_SFIFO_RXEMPT (0x40U) //!< Bit mask for UART_SFIFO_RXEMPT. |
mbed_official | 146:f64d43ff0c18 | 3331 | #define BS_UART_SFIFO_RXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_RXEMPT. |
mbed_official | 146:f64d43ff0c18 | 3332 | |
mbed_official | 146:f64d43ff0c18 | 3333 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3334 | //! @brief Read current value of the UART_SFIFO_RXEMPT field. |
mbed_official | 146:f64d43ff0c18 | 3335 | #define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT)) |
mbed_official | 146:f64d43ff0c18 | 3336 | #endif |
mbed_official | 146:f64d43ff0c18 | 3337 | //@} |
mbed_official | 146:f64d43ff0c18 | 3338 | |
mbed_official | 146:f64d43ff0c18 | 3339 | /*! |
mbed_official | 146:f64d43ff0c18 | 3340 | * @name Register UART_SFIFO, field TXEMPT[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 3341 | * |
mbed_official | 146:f64d43ff0c18 | 3342 | * Asserts when there is no data in the Transmit FIFO/buffer. This field does |
mbed_official | 146:f64d43ff0c18 | 3343 | * not take into account data that is in the transmit shift register. |
mbed_official | 146:f64d43ff0c18 | 3344 | * |
mbed_official | 146:f64d43ff0c18 | 3345 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3346 | * - 0 - Transmit buffer is not empty. |
mbed_official | 146:f64d43ff0c18 | 3347 | * - 1 - Transmit buffer is empty. |
mbed_official | 146:f64d43ff0c18 | 3348 | */ |
mbed_official | 146:f64d43ff0c18 | 3349 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3350 | #define BP_UART_SFIFO_TXEMPT (7U) //!< Bit position for UART_SFIFO_TXEMPT. |
mbed_official | 146:f64d43ff0c18 | 3351 | #define BM_UART_SFIFO_TXEMPT (0x80U) //!< Bit mask for UART_SFIFO_TXEMPT. |
mbed_official | 146:f64d43ff0c18 | 3352 | #define BS_UART_SFIFO_TXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_TXEMPT. |
mbed_official | 146:f64d43ff0c18 | 3353 | |
mbed_official | 146:f64d43ff0c18 | 3354 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3355 | //! @brief Read current value of the UART_SFIFO_TXEMPT field. |
mbed_official | 146:f64d43ff0c18 | 3356 | #define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT)) |
mbed_official | 146:f64d43ff0c18 | 3357 | #endif |
mbed_official | 146:f64d43ff0c18 | 3358 | //@} |
mbed_official | 146:f64d43ff0c18 | 3359 | |
mbed_official | 146:f64d43ff0c18 | 3360 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3361 | // HW_UART_TWFIFO - UART FIFO Transmit Watermark |
mbed_official | 146:f64d43ff0c18 | 3362 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3363 | |
mbed_official | 146:f64d43ff0c18 | 3364 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3365 | /*! |
mbed_official | 146:f64d43ff0c18 | 3366 | * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW) |
mbed_official | 146:f64d43ff0c18 | 3367 | * |
mbed_official | 146:f64d43ff0c18 | 3368 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 3369 | * |
mbed_official | 146:f64d43ff0c18 | 3370 | * This register provides the ability to set a programmable threshold for |
mbed_official | 146:f64d43ff0c18 | 3371 | * notification of needing additional transmit data. This register may be read at any |
mbed_official | 146:f64d43ff0c18 | 3372 | * time but must be written only when C2[TE] is not set. Changing the value of the |
mbed_official | 146:f64d43ff0c18 | 3373 | * watermark will not clear the S1[TDRE] flag. |
mbed_official | 146:f64d43ff0c18 | 3374 | */ |
mbed_official | 146:f64d43ff0c18 | 3375 | typedef union _hw_uart_twfifo |
mbed_official | 146:f64d43ff0c18 | 3376 | { |
mbed_official | 146:f64d43ff0c18 | 3377 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3378 | struct _hw_uart_twfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 3379 | { |
mbed_official | 146:f64d43ff0c18 | 3380 | uint8_t TXWATER : 8; //!< [7:0] Transmit Watermark |
mbed_official | 146:f64d43ff0c18 | 3381 | } B; |
mbed_official | 146:f64d43ff0c18 | 3382 | } hw_uart_twfifo_t; |
mbed_official | 146:f64d43ff0c18 | 3383 | #endif |
mbed_official | 146:f64d43ff0c18 | 3384 | |
mbed_official | 146:f64d43ff0c18 | 3385 | /*! |
mbed_official | 146:f64d43ff0c18 | 3386 | * @name Constants and macros for entire UART_TWFIFO register |
mbed_official | 146:f64d43ff0c18 | 3387 | */ |
mbed_official | 146:f64d43ff0c18 | 3388 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3389 | #define HW_UART_TWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x13U) |
mbed_official | 146:f64d43ff0c18 | 3390 | |
mbed_official | 146:f64d43ff0c18 | 3391 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3392 | #define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3393 | #define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3394 | #define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3395 | #define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3396 | #define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3397 | #define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3398 | #endif |
mbed_official | 146:f64d43ff0c18 | 3399 | //@} |
mbed_official | 146:f64d43ff0c18 | 3400 | |
mbed_official | 146:f64d43ff0c18 | 3401 | /* |
mbed_official | 146:f64d43ff0c18 | 3402 | * Constants & macros for individual UART_TWFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 3403 | */ |
mbed_official | 146:f64d43ff0c18 | 3404 | |
mbed_official | 146:f64d43ff0c18 | 3405 | /*! |
mbed_official | 146:f64d43ff0c18 | 3406 | * @name Register UART_TWFIFO, field TXWATER[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3407 | * |
mbed_official | 146:f64d43ff0c18 | 3408 | * When the number of datawords in the transmit FIFO/buffer is equal to or less |
mbed_official | 146:f64d43ff0c18 | 3409 | * than the value in this register field, an interrupt via S1[TDRE] or a DMA |
mbed_official | 146:f64d43ff0c18 | 3410 | * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For |
mbed_official | 146:f64d43ff0c18 | 3411 | * proper operation, the value in TXWATER must be set to be less than the size of |
mbed_official | 146:f64d43ff0c18 | 3412 | * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE]. |
mbed_official | 146:f64d43ff0c18 | 3413 | */ |
mbed_official | 146:f64d43ff0c18 | 3414 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3415 | #define BP_UART_TWFIFO_TXWATER (0U) //!< Bit position for UART_TWFIFO_TXWATER. |
mbed_official | 146:f64d43ff0c18 | 3416 | #define BM_UART_TWFIFO_TXWATER (0xFFU) //!< Bit mask for UART_TWFIFO_TXWATER. |
mbed_official | 146:f64d43ff0c18 | 3417 | #define BS_UART_TWFIFO_TXWATER (8U) //!< Bit field size in bits for UART_TWFIFO_TXWATER. |
mbed_official | 146:f64d43ff0c18 | 3418 | |
mbed_official | 146:f64d43ff0c18 | 3419 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3420 | //! @brief Read current value of the UART_TWFIFO_TXWATER field. |
mbed_official | 146:f64d43ff0c18 | 3421 | #define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3422 | #endif |
mbed_official | 146:f64d43ff0c18 | 3423 | |
mbed_official | 146:f64d43ff0c18 | 3424 | //! @brief Format value for bitfield UART_TWFIFO_TXWATER. |
mbed_official | 146:f64d43ff0c18 | 3425 | #define BF_UART_TWFIFO_TXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TWFIFO_TXWATER), uint8_t) & BM_UART_TWFIFO_TXWATER) |
mbed_official | 146:f64d43ff0c18 | 3426 | |
mbed_official | 146:f64d43ff0c18 | 3427 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3428 | //! @brief Set the TXWATER field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3429 | #define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 3430 | #endif |
mbed_official | 146:f64d43ff0c18 | 3431 | //@} |
mbed_official | 146:f64d43ff0c18 | 3432 | |
mbed_official | 146:f64d43ff0c18 | 3433 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3434 | // HW_UART_TCFIFO - UART FIFO Transmit Count |
mbed_official | 146:f64d43ff0c18 | 3435 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3436 | |
mbed_official | 146:f64d43ff0c18 | 3437 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3438 | /*! |
mbed_official | 146:f64d43ff0c18 | 3439 | * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO) |
mbed_official | 146:f64d43ff0c18 | 3440 | * |
mbed_official | 146:f64d43ff0c18 | 3441 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 3442 | * |
mbed_official | 146:f64d43ff0c18 | 3443 | * This is a read only register that indicates how many datawords are currently |
mbed_official | 146:f64d43ff0c18 | 3444 | * in the transmit buffer/FIFO. It may be read at any time. |
mbed_official | 146:f64d43ff0c18 | 3445 | */ |
mbed_official | 146:f64d43ff0c18 | 3446 | typedef union _hw_uart_tcfifo |
mbed_official | 146:f64d43ff0c18 | 3447 | { |
mbed_official | 146:f64d43ff0c18 | 3448 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3449 | struct _hw_uart_tcfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 3450 | { |
mbed_official | 146:f64d43ff0c18 | 3451 | uint8_t TXCOUNT : 8; //!< [7:0] Transmit Counter |
mbed_official | 146:f64d43ff0c18 | 3452 | } B; |
mbed_official | 146:f64d43ff0c18 | 3453 | } hw_uart_tcfifo_t; |
mbed_official | 146:f64d43ff0c18 | 3454 | #endif |
mbed_official | 146:f64d43ff0c18 | 3455 | |
mbed_official | 146:f64d43ff0c18 | 3456 | /*! |
mbed_official | 146:f64d43ff0c18 | 3457 | * @name Constants and macros for entire UART_TCFIFO register |
mbed_official | 146:f64d43ff0c18 | 3458 | */ |
mbed_official | 146:f64d43ff0c18 | 3459 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3460 | #define HW_UART_TCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x14U) |
mbed_official | 146:f64d43ff0c18 | 3461 | |
mbed_official | 146:f64d43ff0c18 | 3462 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3463 | #define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3464 | #define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3465 | #endif |
mbed_official | 146:f64d43ff0c18 | 3466 | //@} |
mbed_official | 146:f64d43ff0c18 | 3467 | |
mbed_official | 146:f64d43ff0c18 | 3468 | /* |
mbed_official | 146:f64d43ff0c18 | 3469 | * Constants & macros for individual UART_TCFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 3470 | */ |
mbed_official | 146:f64d43ff0c18 | 3471 | |
mbed_official | 146:f64d43ff0c18 | 3472 | /*! |
mbed_official | 146:f64d43ff0c18 | 3473 | * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 3474 | * |
mbed_official | 146:f64d43ff0c18 | 3475 | * The value in this register indicates the number of datawords that are in the |
mbed_official | 146:f64d43ff0c18 | 3476 | * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the |
mbed_official | 146:f64d43ff0c18 | 3477 | * transmit shift register, it is not included in the count. This value may be used |
mbed_official | 146:f64d43ff0c18 | 3478 | * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the |
mbed_official | 146:f64d43ff0c18 | 3479 | * transmit FIFO/buffer. |
mbed_official | 146:f64d43ff0c18 | 3480 | */ |
mbed_official | 146:f64d43ff0c18 | 3481 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3482 | #define BP_UART_TCFIFO_TXCOUNT (0U) //!< Bit position for UART_TCFIFO_TXCOUNT. |
mbed_official | 146:f64d43ff0c18 | 3483 | #define BM_UART_TCFIFO_TXCOUNT (0xFFU) //!< Bit mask for UART_TCFIFO_TXCOUNT. |
mbed_official | 146:f64d43ff0c18 | 3484 | #define BS_UART_TCFIFO_TXCOUNT (8U) //!< Bit field size in bits for UART_TCFIFO_TXCOUNT. |
mbed_official | 146:f64d43ff0c18 | 3485 | |
mbed_official | 146:f64d43ff0c18 | 3486 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3487 | //! @brief Read current value of the UART_TCFIFO_TXCOUNT field. |
mbed_official | 146:f64d43ff0c18 | 3488 | #define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3489 | #endif |
mbed_official | 146:f64d43ff0c18 | 3490 | //@} |
mbed_official | 146:f64d43ff0c18 | 3491 | |
mbed_official | 146:f64d43ff0c18 | 3492 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3493 | // HW_UART_RWFIFO - UART FIFO Receive Watermark |
mbed_official | 146:f64d43ff0c18 | 3494 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3495 | |
mbed_official | 146:f64d43ff0c18 | 3496 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3497 | /*! |
mbed_official | 146:f64d43ff0c18 | 3498 | * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW) |
mbed_official | 146:f64d43ff0c18 | 3499 | * |
mbed_official | 146:f64d43ff0c18 | 3500 | * Reset value: 0x01U |
mbed_official | 146:f64d43ff0c18 | 3501 | * |
mbed_official | 146:f64d43ff0c18 | 3502 | * This register provides the ability to set a programmable threshold for |
mbed_official | 146:f64d43ff0c18 | 3503 | * notification of the need to remove data from the receiver FIFO/buffer. This register |
mbed_official | 146:f64d43ff0c18 | 3504 | * may be read at any time but must be written only when C2[RE] is not asserted. |
mbed_official | 146:f64d43ff0c18 | 3505 | * Changing the value in this register will not clear S1[RDRF]. |
mbed_official | 146:f64d43ff0c18 | 3506 | */ |
mbed_official | 146:f64d43ff0c18 | 3507 | typedef union _hw_uart_rwfifo |
mbed_official | 146:f64d43ff0c18 | 3508 | { |
mbed_official | 146:f64d43ff0c18 | 3509 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3510 | struct _hw_uart_rwfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 3511 | { |
mbed_official | 146:f64d43ff0c18 | 3512 | uint8_t RXWATER : 8; //!< [7:0] Receive Watermark |
mbed_official | 146:f64d43ff0c18 | 3513 | } B; |
mbed_official | 146:f64d43ff0c18 | 3514 | } hw_uart_rwfifo_t; |
mbed_official | 146:f64d43ff0c18 | 3515 | #endif |
mbed_official | 146:f64d43ff0c18 | 3516 | |
mbed_official | 146:f64d43ff0c18 | 3517 | /*! |
mbed_official | 146:f64d43ff0c18 | 3518 | * @name Constants and macros for entire UART_RWFIFO register |
mbed_official | 146:f64d43ff0c18 | 3519 | */ |
mbed_official | 146:f64d43ff0c18 | 3520 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3521 | #define HW_UART_RWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x15U) |
mbed_official | 146:f64d43ff0c18 | 3522 | |
mbed_official | 146:f64d43ff0c18 | 3523 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3524 | #define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3525 | #define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3526 | #define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3527 | #define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3528 | #define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3529 | #define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3530 | #endif |
mbed_official | 146:f64d43ff0c18 | 3531 | //@} |
mbed_official | 146:f64d43ff0c18 | 3532 | |
mbed_official | 146:f64d43ff0c18 | 3533 | /* |
mbed_official | 146:f64d43ff0c18 | 3534 | * Constants & macros for individual UART_RWFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 3535 | */ |
mbed_official | 146:f64d43ff0c18 | 3536 | |
mbed_official | 146:f64d43ff0c18 | 3537 | /*! |
mbed_official | 146:f64d43ff0c18 | 3538 | * @name Register UART_RWFIFO, field RXWATER[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3539 | * |
mbed_official | 146:f64d43ff0c18 | 3540 | * When the number of datawords in the receive FIFO/buffer is equal to or |
mbed_official | 146:f64d43ff0c18 | 3541 | * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA |
mbed_official | 146:f64d43ff0c18 | 3542 | * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For |
mbed_official | 146:f64d43ff0c18 | 3543 | * proper operation, the value in RXWATER must be set to be less than the receive |
mbed_official | 146:f64d43ff0c18 | 3544 | * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be |
mbed_official | 146:f64d43ff0c18 | 3545 | * greater than 0. |
mbed_official | 146:f64d43ff0c18 | 3546 | */ |
mbed_official | 146:f64d43ff0c18 | 3547 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3548 | #define BP_UART_RWFIFO_RXWATER (0U) //!< Bit position for UART_RWFIFO_RXWATER. |
mbed_official | 146:f64d43ff0c18 | 3549 | #define BM_UART_RWFIFO_RXWATER (0xFFU) //!< Bit mask for UART_RWFIFO_RXWATER. |
mbed_official | 146:f64d43ff0c18 | 3550 | #define BS_UART_RWFIFO_RXWATER (8U) //!< Bit field size in bits for UART_RWFIFO_RXWATER. |
mbed_official | 146:f64d43ff0c18 | 3551 | |
mbed_official | 146:f64d43ff0c18 | 3552 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3553 | //! @brief Read current value of the UART_RWFIFO_RXWATER field. |
mbed_official | 146:f64d43ff0c18 | 3554 | #define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3555 | #endif |
mbed_official | 146:f64d43ff0c18 | 3556 | |
mbed_official | 146:f64d43ff0c18 | 3557 | //! @brief Format value for bitfield UART_RWFIFO_RXWATER. |
mbed_official | 146:f64d43ff0c18 | 3558 | #define BF_UART_RWFIFO_RXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_RWFIFO_RXWATER), uint8_t) & BM_UART_RWFIFO_RXWATER) |
mbed_official | 146:f64d43ff0c18 | 3559 | |
mbed_official | 146:f64d43ff0c18 | 3560 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3561 | //! @brief Set the RXWATER field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3562 | #define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 3563 | #endif |
mbed_official | 146:f64d43ff0c18 | 3564 | //@} |
mbed_official | 146:f64d43ff0c18 | 3565 | |
mbed_official | 146:f64d43ff0c18 | 3566 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3567 | // HW_UART_RCFIFO - UART FIFO Receive Count |
mbed_official | 146:f64d43ff0c18 | 3568 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3569 | |
mbed_official | 146:f64d43ff0c18 | 3570 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3571 | /*! |
mbed_official | 146:f64d43ff0c18 | 3572 | * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO) |
mbed_official | 146:f64d43ff0c18 | 3573 | * |
mbed_official | 146:f64d43ff0c18 | 3574 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 3575 | * |
mbed_official | 146:f64d43ff0c18 | 3576 | * This is a read only register that indicates how many datawords are currently |
mbed_official | 146:f64d43ff0c18 | 3577 | * in the receive FIFO/buffer. It may be read at any time. |
mbed_official | 146:f64d43ff0c18 | 3578 | */ |
mbed_official | 146:f64d43ff0c18 | 3579 | typedef union _hw_uart_rcfifo |
mbed_official | 146:f64d43ff0c18 | 3580 | { |
mbed_official | 146:f64d43ff0c18 | 3581 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3582 | struct _hw_uart_rcfifo_bitfields |
mbed_official | 146:f64d43ff0c18 | 3583 | { |
mbed_official | 146:f64d43ff0c18 | 3584 | uint8_t RXCOUNT : 8; //!< [7:0] Receive Counter |
mbed_official | 146:f64d43ff0c18 | 3585 | } B; |
mbed_official | 146:f64d43ff0c18 | 3586 | } hw_uart_rcfifo_t; |
mbed_official | 146:f64d43ff0c18 | 3587 | #endif |
mbed_official | 146:f64d43ff0c18 | 3588 | |
mbed_official | 146:f64d43ff0c18 | 3589 | /*! |
mbed_official | 146:f64d43ff0c18 | 3590 | * @name Constants and macros for entire UART_RCFIFO register |
mbed_official | 146:f64d43ff0c18 | 3591 | */ |
mbed_official | 146:f64d43ff0c18 | 3592 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3593 | #define HW_UART_RCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x16U) |
mbed_official | 146:f64d43ff0c18 | 3594 | |
mbed_official | 146:f64d43ff0c18 | 3595 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3596 | #define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3597 | #define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3598 | #endif |
mbed_official | 146:f64d43ff0c18 | 3599 | //@} |
mbed_official | 146:f64d43ff0c18 | 3600 | |
mbed_official | 146:f64d43ff0c18 | 3601 | /* |
mbed_official | 146:f64d43ff0c18 | 3602 | * Constants & macros for individual UART_RCFIFO bitfields |
mbed_official | 146:f64d43ff0c18 | 3603 | */ |
mbed_official | 146:f64d43ff0c18 | 3604 | |
mbed_official | 146:f64d43ff0c18 | 3605 | /*! |
mbed_official | 146:f64d43ff0c18 | 3606 | * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 3607 | * |
mbed_official | 146:f64d43ff0c18 | 3608 | * The value in this register indicates the number of datawords that are in the |
mbed_official | 146:f64d43ff0c18 | 3609 | * receive FIFO/buffer. If a dataword is being received, that is, in the receive |
mbed_official | 146:f64d43ff0c18 | 3610 | * shift register, it is not included in the count. This value may be used in |
mbed_official | 146:f64d43ff0c18 | 3611 | * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the |
mbed_official | 146:f64d43ff0c18 | 3612 | * receive FIFO/buffer. |
mbed_official | 146:f64d43ff0c18 | 3613 | */ |
mbed_official | 146:f64d43ff0c18 | 3614 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3615 | #define BP_UART_RCFIFO_RXCOUNT (0U) //!< Bit position for UART_RCFIFO_RXCOUNT. |
mbed_official | 146:f64d43ff0c18 | 3616 | #define BM_UART_RCFIFO_RXCOUNT (0xFFU) //!< Bit mask for UART_RCFIFO_RXCOUNT. |
mbed_official | 146:f64d43ff0c18 | 3617 | #define BS_UART_RCFIFO_RXCOUNT (8U) //!< Bit field size in bits for UART_RCFIFO_RXCOUNT. |
mbed_official | 146:f64d43ff0c18 | 3618 | |
mbed_official | 146:f64d43ff0c18 | 3619 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3620 | //! @brief Read current value of the UART_RCFIFO_RXCOUNT field. |
mbed_official | 146:f64d43ff0c18 | 3621 | #define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U) |
mbed_official | 146:f64d43ff0c18 | 3622 | #endif |
mbed_official | 146:f64d43ff0c18 | 3623 | //@} |
mbed_official | 146:f64d43ff0c18 | 3624 | |
mbed_official | 146:f64d43ff0c18 | 3625 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3626 | // HW_UART_C7816 - UART 7816 Control Register |
mbed_official | 146:f64d43ff0c18 | 3627 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3628 | |
mbed_official | 146:f64d43ff0c18 | 3629 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3630 | /*! |
mbed_official | 146:f64d43ff0c18 | 3631 | * @brief HW_UART_C7816 - UART 7816 Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 3632 | * |
mbed_official | 146:f64d43ff0c18 | 3633 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 3634 | * |
mbed_official | 146:f64d43ff0c18 | 3635 | * The C7816 register is the primary control register for ISO-7816 specific |
mbed_official | 146:f64d43ff0c18 | 3636 | * functionality. This register is specific to 7816 functionality and the values in |
mbed_official | 146:f64d43ff0c18 | 3637 | * this register have no effect on UART operation and should be ignored if |
mbed_official | 146:f64d43ff0c18 | 3638 | * ISO_7816E is not set/enabled. This register may be read at any time but values must |
mbed_official | 146:f64d43ff0c18 | 3639 | * be changed only when ISO_7816E is not set. |
mbed_official | 146:f64d43ff0c18 | 3640 | */ |
mbed_official | 146:f64d43ff0c18 | 3641 | typedef union _hw_uart_c7816 |
mbed_official | 146:f64d43ff0c18 | 3642 | { |
mbed_official | 146:f64d43ff0c18 | 3643 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3644 | struct _hw_uart_c7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 3645 | { |
mbed_official | 146:f64d43ff0c18 | 3646 | uint8_t ISO_7816E : 1; //!< [0] ISO-7816 Functionality Enabled |
mbed_official | 146:f64d43ff0c18 | 3647 | uint8_t TTYPE : 1; //!< [1] Transfer Type |
mbed_official | 146:f64d43ff0c18 | 3648 | uint8_t INIT : 1; //!< [2] Detect Initial Character |
mbed_official | 146:f64d43ff0c18 | 3649 | uint8_t ANACK : 1; //!< [3] Generate NACK on Error |
mbed_official | 146:f64d43ff0c18 | 3650 | uint8_t ONACK : 1; //!< [4] Generate NACK on Overflow |
mbed_official | 146:f64d43ff0c18 | 3651 | uint8_t RESERVED0 : 3; //!< [7:5] |
mbed_official | 146:f64d43ff0c18 | 3652 | } B; |
mbed_official | 146:f64d43ff0c18 | 3653 | } hw_uart_c7816_t; |
mbed_official | 146:f64d43ff0c18 | 3654 | #endif |
mbed_official | 146:f64d43ff0c18 | 3655 | |
mbed_official | 146:f64d43ff0c18 | 3656 | /*! |
mbed_official | 146:f64d43ff0c18 | 3657 | * @name Constants and macros for entire UART_C7816 register |
mbed_official | 146:f64d43ff0c18 | 3658 | */ |
mbed_official | 146:f64d43ff0c18 | 3659 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3660 | #define HW_UART_C7816_ADDR(x) (REGS_UART_BASE(x) + 0x18U) |
mbed_official | 146:f64d43ff0c18 | 3661 | |
mbed_official | 146:f64d43ff0c18 | 3662 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3663 | #define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3664 | #define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 3665 | #define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3666 | #define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3667 | #define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3668 | #define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3669 | #endif |
mbed_official | 146:f64d43ff0c18 | 3670 | //@} |
mbed_official | 146:f64d43ff0c18 | 3671 | |
mbed_official | 146:f64d43ff0c18 | 3672 | /* |
mbed_official | 146:f64d43ff0c18 | 3673 | * Constants & macros for individual UART_C7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 3674 | */ |
mbed_official | 146:f64d43ff0c18 | 3675 | |
mbed_official | 146:f64d43ff0c18 | 3676 | /*! |
mbed_official | 146:f64d43ff0c18 | 3677 | * @name Register UART_C7816, field ISO_7816E[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3678 | * |
mbed_official | 146:f64d43ff0c18 | 3679 | * Indicates that the UART is operating according to the ISO-7816 protocol. This |
mbed_official | 146:f64d43ff0c18 | 3680 | * field must be modified only when no transmit or receive is occurring. If this |
mbed_official | 146:f64d43ff0c18 | 3681 | * field is changed during a data transfer, the data being transmitted or |
mbed_official | 146:f64d43ff0c18 | 3682 | * received may be transferred incorrectly. |
mbed_official | 146:f64d43ff0c18 | 3683 | * |
mbed_official | 146:f64d43ff0c18 | 3684 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3685 | * - 0 - ISO-7816 functionality is turned off/not enabled. |
mbed_official | 146:f64d43ff0c18 | 3686 | * - 1 - ISO-7816 functionality is turned on/enabled. |
mbed_official | 146:f64d43ff0c18 | 3687 | */ |
mbed_official | 146:f64d43ff0c18 | 3688 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3689 | #define BP_UART_C7816_ISO_7816E (0U) //!< Bit position for UART_C7816_ISO_7816E. |
mbed_official | 146:f64d43ff0c18 | 3690 | #define BM_UART_C7816_ISO_7816E (0x01U) //!< Bit mask for UART_C7816_ISO_7816E. |
mbed_official | 146:f64d43ff0c18 | 3691 | #define BS_UART_C7816_ISO_7816E (1U) //!< Bit field size in bits for UART_C7816_ISO_7816E. |
mbed_official | 146:f64d43ff0c18 | 3692 | |
mbed_official | 146:f64d43ff0c18 | 3693 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3694 | //! @brief Read current value of the UART_C7816_ISO_7816E field. |
mbed_official | 146:f64d43ff0c18 | 3695 | #define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E)) |
mbed_official | 146:f64d43ff0c18 | 3696 | #endif |
mbed_official | 146:f64d43ff0c18 | 3697 | |
mbed_official | 146:f64d43ff0c18 | 3698 | //! @brief Format value for bitfield UART_C7816_ISO_7816E. |
mbed_official | 146:f64d43ff0c18 | 3699 | #define BF_UART_C7816_ISO_7816E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ISO_7816E), uint8_t) & BM_UART_C7816_ISO_7816E) |
mbed_official | 146:f64d43ff0c18 | 3700 | |
mbed_official | 146:f64d43ff0c18 | 3701 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3702 | //! @brief Set the ISO_7816E field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3703 | #define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3704 | #endif |
mbed_official | 146:f64d43ff0c18 | 3705 | //@} |
mbed_official | 146:f64d43ff0c18 | 3706 | |
mbed_official | 146:f64d43ff0c18 | 3707 | /*! |
mbed_official | 146:f64d43ff0c18 | 3708 | * @name Register UART_C7816, field TTYPE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 3709 | * |
mbed_official | 146:f64d43ff0c18 | 3710 | * Indicates the transfer protocol being used. See ISO-7816 / smartcard support |
mbed_official | 146:f64d43ff0c18 | 3711 | * for more details. |
mbed_official | 146:f64d43ff0c18 | 3712 | * |
mbed_official | 146:f64d43ff0c18 | 3713 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3714 | * - 0 - T = 0 per the ISO-7816 specification. |
mbed_official | 146:f64d43ff0c18 | 3715 | * - 1 - T = 1 per the ISO-7816 specification. |
mbed_official | 146:f64d43ff0c18 | 3716 | */ |
mbed_official | 146:f64d43ff0c18 | 3717 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3718 | #define BP_UART_C7816_TTYPE (1U) //!< Bit position for UART_C7816_TTYPE. |
mbed_official | 146:f64d43ff0c18 | 3719 | #define BM_UART_C7816_TTYPE (0x02U) //!< Bit mask for UART_C7816_TTYPE. |
mbed_official | 146:f64d43ff0c18 | 3720 | #define BS_UART_C7816_TTYPE (1U) //!< Bit field size in bits for UART_C7816_TTYPE. |
mbed_official | 146:f64d43ff0c18 | 3721 | |
mbed_official | 146:f64d43ff0c18 | 3722 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3723 | //! @brief Read current value of the UART_C7816_TTYPE field. |
mbed_official | 146:f64d43ff0c18 | 3724 | #define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE)) |
mbed_official | 146:f64d43ff0c18 | 3725 | #endif |
mbed_official | 146:f64d43ff0c18 | 3726 | |
mbed_official | 146:f64d43ff0c18 | 3727 | //! @brief Format value for bitfield UART_C7816_TTYPE. |
mbed_official | 146:f64d43ff0c18 | 3728 | #define BF_UART_C7816_TTYPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_TTYPE), uint8_t) & BM_UART_C7816_TTYPE) |
mbed_official | 146:f64d43ff0c18 | 3729 | |
mbed_official | 146:f64d43ff0c18 | 3730 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3731 | //! @brief Set the TTYPE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3732 | #define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3733 | #endif |
mbed_official | 146:f64d43ff0c18 | 3734 | //@} |
mbed_official | 146:f64d43ff0c18 | 3735 | |
mbed_official | 146:f64d43ff0c18 | 3736 | /*! |
mbed_official | 146:f64d43ff0c18 | 3737 | * @name Register UART_C7816, field INIT[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 3738 | * |
mbed_official | 146:f64d43ff0c18 | 3739 | * When this field is set, all received characters are searched for a valid |
mbed_official | 146:f64d43ff0c18 | 3740 | * initial character. If an invalid initial character is identified, and ANACK is |
mbed_official | 146:f64d43ff0c18 | 3741 | * set, a NACK is sent. All received data is discarded and error flags blocked |
mbed_official | 146:f64d43ff0c18 | 3742 | * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV]) |
mbed_official | 146:f64d43ff0c18 | 3743 | * until a valid initial character is detected. Upon detecting a valid initial |
mbed_official | 146:f64d43ff0c18 | 3744 | * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are |
mbed_official | 146:f64d43ff0c18 | 3745 | * automatically updated to reflect the initial character that was received. The |
mbed_official | 146:f64d43ff0c18 | 3746 | * actual INIT data value is not stored in the receive buffer. Additionally, upon |
mbed_official | 146:f64d43ff0c18 | 3747 | * detection of a valid initial character, IS7816[INITD] is set and an interrupt |
mbed_official | 146:f64d43ff0c18 | 3748 | * issued as programmed by IE7816[INITDE]. When a valid initial character is |
mbed_official | 146:f64d43ff0c18 | 3749 | * detected, INIT is automatically cleared. This Initial Character Detect feature is |
mbed_official | 146:f64d43ff0c18 | 3750 | * supported only in T = 0 protocol mode. |
mbed_official | 146:f64d43ff0c18 | 3751 | * |
mbed_official | 146:f64d43ff0c18 | 3752 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3753 | * - 0 - Normal operating mode. Receiver does not seek to identify initial |
mbed_official | 146:f64d43ff0c18 | 3754 | * character. |
mbed_official | 146:f64d43ff0c18 | 3755 | * - 1 - Receiver searches for initial character. |
mbed_official | 146:f64d43ff0c18 | 3756 | */ |
mbed_official | 146:f64d43ff0c18 | 3757 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3758 | #define BP_UART_C7816_INIT (2U) //!< Bit position for UART_C7816_INIT. |
mbed_official | 146:f64d43ff0c18 | 3759 | #define BM_UART_C7816_INIT (0x04U) //!< Bit mask for UART_C7816_INIT. |
mbed_official | 146:f64d43ff0c18 | 3760 | #define BS_UART_C7816_INIT (1U) //!< Bit field size in bits for UART_C7816_INIT. |
mbed_official | 146:f64d43ff0c18 | 3761 | |
mbed_official | 146:f64d43ff0c18 | 3762 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3763 | //! @brief Read current value of the UART_C7816_INIT field. |
mbed_official | 146:f64d43ff0c18 | 3764 | #define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT)) |
mbed_official | 146:f64d43ff0c18 | 3765 | #endif |
mbed_official | 146:f64d43ff0c18 | 3766 | |
mbed_official | 146:f64d43ff0c18 | 3767 | //! @brief Format value for bitfield UART_C7816_INIT. |
mbed_official | 146:f64d43ff0c18 | 3768 | #define BF_UART_C7816_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_INIT), uint8_t) & BM_UART_C7816_INIT) |
mbed_official | 146:f64d43ff0c18 | 3769 | |
mbed_official | 146:f64d43ff0c18 | 3770 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3771 | //! @brief Set the INIT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3772 | #define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3773 | #endif |
mbed_official | 146:f64d43ff0c18 | 3774 | //@} |
mbed_official | 146:f64d43ff0c18 | 3775 | |
mbed_official | 146:f64d43ff0c18 | 3776 | /*! |
mbed_official | 146:f64d43ff0c18 | 3777 | * @name Register UART_C7816, field ANACK[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 3778 | * |
mbed_official | 146:f64d43ff0c18 | 3779 | * When this field is set, the receiver automatically generates a NACK response |
mbed_official | 146:f64d43ff0c18 | 3780 | * if a parity error occurs or if INIT is set and an invalid initial character is |
mbed_official | 146:f64d43ff0c18 | 3781 | * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART |
mbed_official | 146:f64d43ff0c18 | 3782 | * attempts to retransmit the data indefinitely. To stop retransmission attempts, |
mbed_official | 146:f64d43ff0c18 | 3783 | * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again. |
mbed_official | 146:f64d43ff0c18 | 3784 | * |
mbed_official | 146:f64d43ff0c18 | 3785 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3786 | * - 0 - No NACK is automatically generated. |
mbed_official | 146:f64d43ff0c18 | 3787 | * - 1 - A NACK is automatically generated if a parity error is detected or if |
mbed_official | 146:f64d43ff0c18 | 3788 | * an invalid initial character is detected. |
mbed_official | 146:f64d43ff0c18 | 3789 | */ |
mbed_official | 146:f64d43ff0c18 | 3790 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3791 | #define BP_UART_C7816_ANACK (3U) //!< Bit position for UART_C7816_ANACK. |
mbed_official | 146:f64d43ff0c18 | 3792 | #define BM_UART_C7816_ANACK (0x08U) //!< Bit mask for UART_C7816_ANACK. |
mbed_official | 146:f64d43ff0c18 | 3793 | #define BS_UART_C7816_ANACK (1U) //!< Bit field size in bits for UART_C7816_ANACK. |
mbed_official | 146:f64d43ff0c18 | 3794 | |
mbed_official | 146:f64d43ff0c18 | 3795 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3796 | //! @brief Read current value of the UART_C7816_ANACK field. |
mbed_official | 146:f64d43ff0c18 | 3797 | #define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK)) |
mbed_official | 146:f64d43ff0c18 | 3798 | #endif |
mbed_official | 146:f64d43ff0c18 | 3799 | |
mbed_official | 146:f64d43ff0c18 | 3800 | //! @brief Format value for bitfield UART_C7816_ANACK. |
mbed_official | 146:f64d43ff0c18 | 3801 | #define BF_UART_C7816_ANACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ANACK), uint8_t) & BM_UART_C7816_ANACK) |
mbed_official | 146:f64d43ff0c18 | 3802 | |
mbed_official | 146:f64d43ff0c18 | 3803 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3804 | //! @brief Set the ANACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3805 | #define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3806 | #endif |
mbed_official | 146:f64d43ff0c18 | 3807 | //@} |
mbed_official | 146:f64d43ff0c18 | 3808 | |
mbed_official | 146:f64d43ff0c18 | 3809 | /*! |
mbed_official | 146:f64d43ff0c18 | 3810 | * @name Register UART_C7816, field ONACK[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 3811 | * |
mbed_official | 146:f64d43ff0c18 | 3812 | * When this field is set, the receiver automatically generates a NACK response |
mbed_official | 146:f64d43ff0c18 | 3813 | * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems, |
mbed_official | 146:f64d43ff0c18 | 3814 | * this results in the transmitter resending the packet that overflowed until the |
mbed_official | 146:f64d43ff0c18 | 3815 | * retransmit threshold for that transmitter is reached. A NACK is generated only |
mbed_official | 146:f64d43ff0c18 | 3816 | * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK |
mbed_official | 146:f64d43ff0c18 | 3817 | * considerations |
mbed_official | 146:f64d43ff0c18 | 3818 | * |
mbed_official | 146:f64d43ff0c18 | 3819 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3820 | * - 0 - The received data does not generate a NACK when the receipt of the data |
mbed_official | 146:f64d43ff0c18 | 3821 | * results in an overflow event. |
mbed_official | 146:f64d43ff0c18 | 3822 | * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a |
mbed_official | 146:f64d43ff0c18 | 3823 | * received character. |
mbed_official | 146:f64d43ff0c18 | 3824 | */ |
mbed_official | 146:f64d43ff0c18 | 3825 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3826 | #define BP_UART_C7816_ONACK (4U) //!< Bit position for UART_C7816_ONACK. |
mbed_official | 146:f64d43ff0c18 | 3827 | #define BM_UART_C7816_ONACK (0x10U) //!< Bit mask for UART_C7816_ONACK. |
mbed_official | 146:f64d43ff0c18 | 3828 | #define BS_UART_C7816_ONACK (1U) //!< Bit field size in bits for UART_C7816_ONACK. |
mbed_official | 146:f64d43ff0c18 | 3829 | |
mbed_official | 146:f64d43ff0c18 | 3830 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3831 | //! @brief Read current value of the UART_C7816_ONACK field. |
mbed_official | 146:f64d43ff0c18 | 3832 | #define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK)) |
mbed_official | 146:f64d43ff0c18 | 3833 | #endif |
mbed_official | 146:f64d43ff0c18 | 3834 | |
mbed_official | 146:f64d43ff0c18 | 3835 | //! @brief Format value for bitfield UART_C7816_ONACK. |
mbed_official | 146:f64d43ff0c18 | 3836 | #define BF_UART_C7816_ONACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ONACK), uint8_t) & BM_UART_C7816_ONACK) |
mbed_official | 146:f64d43ff0c18 | 3837 | |
mbed_official | 146:f64d43ff0c18 | 3838 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3839 | //! @brief Set the ONACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3840 | #define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3841 | #endif |
mbed_official | 146:f64d43ff0c18 | 3842 | //@} |
mbed_official | 146:f64d43ff0c18 | 3843 | |
mbed_official | 146:f64d43ff0c18 | 3844 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3845 | // HW_UART_IE7816 - UART 7816 Interrupt Enable Register |
mbed_official | 146:f64d43ff0c18 | 3846 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 3847 | |
mbed_official | 146:f64d43ff0c18 | 3848 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3849 | /*! |
mbed_official | 146:f64d43ff0c18 | 3850 | * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW) |
mbed_official | 146:f64d43ff0c18 | 3851 | * |
mbed_official | 146:f64d43ff0c18 | 3852 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 3853 | * |
mbed_official | 146:f64d43ff0c18 | 3854 | * The IE7816 register controls which flags result in an interrupt being issued. |
mbed_official | 146:f64d43ff0c18 | 3855 | * This register is specific to 7816 functionality, the corresponding flags that |
mbed_official | 146:f64d43ff0c18 | 3856 | * drive the interrupts are not asserted when 7816E is not set/enabled. However, |
mbed_official | 146:f64d43ff0c18 | 3857 | * these flags may remain set if they are asserted while 7816E was set and not |
mbed_official | 146:f64d43ff0c18 | 3858 | * subsequently cleared. This register may be read or written to at any time. |
mbed_official | 146:f64d43ff0c18 | 3859 | */ |
mbed_official | 146:f64d43ff0c18 | 3860 | typedef union _hw_uart_ie7816 |
mbed_official | 146:f64d43ff0c18 | 3861 | { |
mbed_official | 146:f64d43ff0c18 | 3862 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 3863 | struct _hw_uart_ie7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 3864 | { |
mbed_official | 146:f64d43ff0c18 | 3865 | uint8_t RXTE : 1; //!< [0] Receive Threshold Exceeded Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3866 | uint8_t TXTE : 1; //!< [1] Transmit Threshold Exceeded Interrupt |
mbed_official | 146:f64d43ff0c18 | 3867 | //! Enable |
mbed_official | 146:f64d43ff0c18 | 3868 | uint8_t GTVE : 1; //!< [2] Guard Timer Violated Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3869 | uint8_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 3870 | uint8_t INITDE : 1; //!< [4] Initial Character Detected Interrupt |
mbed_official | 146:f64d43ff0c18 | 3871 | //! Enable |
mbed_official | 146:f64d43ff0c18 | 3872 | uint8_t BWTE : 1; //!< [5] Block Wait Timer Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3873 | uint8_t CWTE : 1; //!< [6] Character Wait Timer Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3874 | uint8_t WTE : 1; //!< [7] Wait Timer Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 3875 | } B; |
mbed_official | 146:f64d43ff0c18 | 3876 | } hw_uart_ie7816_t; |
mbed_official | 146:f64d43ff0c18 | 3877 | #endif |
mbed_official | 146:f64d43ff0c18 | 3878 | |
mbed_official | 146:f64d43ff0c18 | 3879 | /*! |
mbed_official | 146:f64d43ff0c18 | 3880 | * @name Constants and macros for entire UART_IE7816 register |
mbed_official | 146:f64d43ff0c18 | 3881 | */ |
mbed_official | 146:f64d43ff0c18 | 3882 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3883 | #define HW_UART_IE7816_ADDR(x) (REGS_UART_BASE(x) + 0x19U) |
mbed_official | 146:f64d43ff0c18 | 3884 | |
mbed_official | 146:f64d43ff0c18 | 3885 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3886 | #define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 3887 | #define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 3888 | #define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 3889 | #define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 3890 | #define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 3891 | #define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 3892 | #endif |
mbed_official | 146:f64d43ff0c18 | 3893 | //@} |
mbed_official | 146:f64d43ff0c18 | 3894 | |
mbed_official | 146:f64d43ff0c18 | 3895 | /* |
mbed_official | 146:f64d43ff0c18 | 3896 | * Constants & macros for individual UART_IE7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 3897 | */ |
mbed_official | 146:f64d43ff0c18 | 3898 | |
mbed_official | 146:f64d43ff0c18 | 3899 | /*! |
mbed_official | 146:f64d43ff0c18 | 3900 | * @name Register UART_IE7816, field RXTE[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 3901 | * |
mbed_official | 146:f64d43ff0c18 | 3902 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3903 | * - 0 - The assertion of IS7816[RXT] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 3904 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 3905 | * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt. |
mbed_official | 146:f64d43ff0c18 | 3906 | */ |
mbed_official | 146:f64d43ff0c18 | 3907 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3908 | #define BP_UART_IE7816_RXTE (0U) //!< Bit position for UART_IE7816_RXTE. |
mbed_official | 146:f64d43ff0c18 | 3909 | #define BM_UART_IE7816_RXTE (0x01U) //!< Bit mask for UART_IE7816_RXTE. |
mbed_official | 146:f64d43ff0c18 | 3910 | #define BS_UART_IE7816_RXTE (1U) //!< Bit field size in bits for UART_IE7816_RXTE. |
mbed_official | 146:f64d43ff0c18 | 3911 | |
mbed_official | 146:f64d43ff0c18 | 3912 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3913 | //! @brief Read current value of the UART_IE7816_RXTE field. |
mbed_official | 146:f64d43ff0c18 | 3914 | #define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE)) |
mbed_official | 146:f64d43ff0c18 | 3915 | #endif |
mbed_official | 146:f64d43ff0c18 | 3916 | |
mbed_official | 146:f64d43ff0c18 | 3917 | //! @brief Format value for bitfield UART_IE7816_RXTE. |
mbed_official | 146:f64d43ff0c18 | 3918 | #define BF_UART_IE7816_RXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_RXTE), uint8_t) & BM_UART_IE7816_RXTE) |
mbed_official | 146:f64d43ff0c18 | 3919 | |
mbed_official | 146:f64d43ff0c18 | 3920 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3921 | //! @brief Set the RXTE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3922 | #define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3923 | #endif |
mbed_official | 146:f64d43ff0c18 | 3924 | //@} |
mbed_official | 146:f64d43ff0c18 | 3925 | |
mbed_official | 146:f64d43ff0c18 | 3926 | /*! |
mbed_official | 146:f64d43ff0c18 | 3927 | * @name Register UART_IE7816, field TXTE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 3928 | * |
mbed_official | 146:f64d43ff0c18 | 3929 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3930 | * - 0 - The assertion of IS7816[TXT] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 3931 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 3932 | * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt. |
mbed_official | 146:f64d43ff0c18 | 3933 | */ |
mbed_official | 146:f64d43ff0c18 | 3934 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3935 | #define BP_UART_IE7816_TXTE (1U) //!< Bit position for UART_IE7816_TXTE. |
mbed_official | 146:f64d43ff0c18 | 3936 | #define BM_UART_IE7816_TXTE (0x02U) //!< Bit mask for UART_IE7816_TXTE. |
mbed_official | 146:f64d43ff0c18 | 3937 | #define BS_UART_IE7816_TXTE (1U) //!< Bit field size in bits for UART_IE7816_TXTE. |
mbed_official | 146:f64d43ff0c18 | 3938 | |
mbed_official | 146:f64d43ff0c18 | 3939 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3940 | //! @brief Read current value of the UART_IE7816_TXTE field. |
mbed_official | 146:f64d43ff0c18 | 3941 | #define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE)) |
mbed_official | 146:f64d43ff0c18 | 3942 | #endif |
mbed_official | 146:f64d43ff0c18 | 3943 | |
mbed_official | 146:f64d43ff0c18 | 3944 | //! @brief Format value for bitfield UART_IE7816_TXTE. |
mbed_official | 146:f64d43ff0c18 | 3945 | #define BF_UART_IE7816_TXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_TXTE), uint8_t) & BM_UART_IE7816_TXTE) |
mbed_official | 146:f64d43ff0c18 | 3946 | |
mbed_official | 146:f64d43ff0c18 | 3947 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3948 | //! @brief Set the TXTE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3949 | #define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3950 | #endif |
mbed_official | 146:f64d43ff0c18 | 3951 | //@} |
mbed_official | 146:f64d43ff0c18 | 3952 | |
mbed_official | 146:f64d43ff0c18 | 3953 | /*! |
mbed_official | 146:f64d43ff0c18 | 3954 | * @name Register UART_IE7816, field GTVE[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 3955 | * |
mbed_official | 146:f64d43ff0c18 | 3956 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3957 | * - 0 - The assertion of IS7816[GTV] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 3958 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 3959 | * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt. |
mbed_official | 146:f64d43ff0c18 | 3960 | */ |
mbed_official | 146:f64d43ff0c18 | 3961 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3962 | #define BP_UART_IE7816_GTVE (2U) //!< Bit position for UART_IE7816_GTVE. |
mbed_official | 146:f64d43ff0c18 | 3963 | #define BM_UART_IE7816_GTVE (0x04U) //!< Bit mask for UART_IE7816_GTVE. |
mbed_official | 146:f64d43ff0c18 | 3964 | #define BS_UART_IE7816_GTVE (1U) //!< Bit field size in bits for UART_IE7816_GTVE. |
mbed_official | 146:f64d43ff0c18 | 3965 | |
mbed_official | 146:f64d43ff0c18 | 3966 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3967 | //! @brief Read current value of the UART_IE7816_GTVE field. |
mbed_official | 146:f64d43ff0c18 | 3968 | #define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE)) |
mbed_official | 146:f64d43ff0c18 | 3969 | #endif |
mbed_official | 146:f64d43ff0c18 | 3970 | |
mbed_official | 146:f64d43ff0c18 | 3971 | //! @brief Format value for bitfield UART_IE7816_GTVE. |
mbed_official | 146:f64d43ff0c18 | 3972 | #define BF_UART_IE7816_GTVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_GTVE), uint8_t) & BM_UART_IE7816_GTVE) |
mbed_official | 146:f64d43ff0c18 | 3973 | |
mbed_official | 146:f64d43ff0c18 | 3974 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3975 | //! @brief Set the GTVE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 3976 | #define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 3977 | #endif |
mbed_official | 146:f64d43ff0c18 | 3978 | //@} |
mbed_official | 146:f64d43ff0c18 | 3979 | |
mbed_official | 146:f64d43ff0c18 | 3980 | /*! |
mbed_official | 146:f64d43ff0c18 | 3981 | * @name Register UART_IE7816, field INITDE[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 3982 | * |
mbed_official | 146:f64d43ff0c18 | 3983 | * Values: |
mbed_official | 146:f64d43ff0c18 | 3984 | * - 0 - The assertion of IS7816[INITD] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 3985 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 3986 | * - 1 - The assertion of IS7816[INITD] results in the generation of an |
mbed_official | 146:f64d43ff0c18 | 3987 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 3988 | */ |
mbed_official | 146:f64d43ff0c18 | 3989 | //@{ |
mbed_official | 146:f64d43ff0c18 | 3990 | #define BP_UART_IE7816_INITDE (4U) //!< Bit position for UART_IE7816_INITDE. |
mbed_official | 146:f64d43ff0c18 | 3991 | #define BM_UART_IE7816_INITDE (0x10U) //!< Bit mask for UART_IE7816_INITDE. |
mbed_official | 146:f64d43ff0c18 | 3992 | #define BS_UART_IE7816_INITDE (1U) //!< Bit field size in bits for UART_IE7816_INITDE. |
mbed_official | 146:f64d43ff0c18 | 3993 | |
mbed_official | 146:f64d43ff0c18 | 3994 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 3995 | //! @brief Read current value of the UART_IE7816_INITDE field. |
mbed_official | 146:f64d43ff0c18 | 3996 | #define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE)) |
mbed_official | 146:f64d43ff0c18 | 3997 | #endif |
mbed_official | 146:f64d43ff0c18 | 3998 | |
mbed_official | 146:f64d43ff0c18 | 3999 | //! @brief Format value for bitfield UART_IE7816_INITDE. |
mbed_official | 146:f64d43ff0c18 | 4000 | #define BF_UART_IE7816_INITDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_INITDE), uint8_t) & BM_UART_IE7816_INITDE) |
mbed_official | 146:f64d43ff0c18 | 4001 | |
mbed_official | 146:f64d43ff0c18 | 4002 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4003 | //! @brief Set the INITDE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4004 | #define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4005 | #endif |
mbed_official | 146:f64d43ff0c18 | 4006 | //@} |
mbed_official | 146:f64d43ff0c18 | 4007 | |
mbed_official | 146:f64d43ff0c18 | 4008 | /*! |
mbed_official | 146:f64d43ff0c18 | 4009 | * @name Register UART_IE7816, field BWTE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 4010 | * |
mbed_official | 146:f64d43ff0c18 | 4011 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4012 | * - 0 - The assertion of IS7816[BWT] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 4013 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 4014 | * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt. |
mbed_official | 146:f64d43ff0c18 | 4015 | */ |
mbed_official | 146:f64d43ff0c18 | 4016 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4017 | #define BP_UART_IE7816_BWTE (5U) //!< Bit position for UART_IE7816_BWTE. |
mbed_official | 146:f64d43ff0c18 | 4018 | #define BM_UART_IE7816_BWTE (0x20U) //!< Bit mask for UART_IE7816_BWTE. |
mbed_official | 146:f64d43ff0c18 | 4019 | #define BS_UART_IE7816_BWTE (1U) //!< Bit field size in bits for UART_IE7816_BWTE. |
mbed_official | 146:f64d43ff0c18 | 4020 | |
mbed_official | 146:f64d43ff0c18 | 4021 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4022 | //! @brief Read current value of the UART_IE7816_BWTE field. |
mbed_official | 146:f64d43ff0c18 | 4023 | #define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE)) |
mbed_official | 146:f64d43ff0c18 | 4024 | #endif |
mbed_official | 146:f64d43ff0c18 | 4025 | |
mbed_official | 146:f64d43ff0c18 | 4026 | //! @brief Format value for bitfield UART_IE7816_BWTE. |
mbed_official | 146:f64d43ff0c18 | 4027 | #define BF_UART_IE7816_BWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_BWTE), uint8_t) & BM_UART_IE7816_BWTE) |
mbed_official | 146:f64d43ff0c18 | 4028 | |
mbed_official | 146:f64d43ff0c18 | 4029 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4030 | //! @brief Set the BWTE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4031 | #define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4032 | #endif |
mbed_official | 146:f64d43ff0c18 | 4033 | //@} |
mbed_official | 146:f64d43ff0c18 | 4034 | |
mbed_official | 146:f64d43ff0c18 | 4035 | /*! |
mbed_official | 146:f64d43ff0c18 | 4036 | * @name Register UART_IE7816, field CWTE[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 4037 | * |
mbed_official | 146:f64d43ff0c18 | 4038 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4039 | * - 0 - The assertion of IS7816[CWT] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 4040 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 4041 | * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt. |
mbed_official | 146:f64d43ff0c18 | 4042 | */ |
mbed_official | 146:f64d43ff0c18 | 4043 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4044 | #define BP_UART_IE7816_CWTE (6U) //!< Bit position for UART_IE7816_CWTE. |
mbed_official | 146:f64d43ff0c18 | 4045 | #define BM_UART_IE7816_CWTE (0x40U) //!< Bit mask for UART_IE7816_CWTE. |
mbed_official | 146:f64d43ff0c18 | 4046 | #define BS_UART_IE7816_CWTE (1U) //!< Bit field size in bits for UART_IE7816_CWTE. |
mbed_official | 146:f64d43ff0c18 | 4047 | |
mbed_official | 146:f64d43ff0c18 | 4048 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4049 | //! @brief Read current value of the UART_IE7816_CWTE field. |
mbed_official | 146:f64d43ff0c18 | 4050 | #define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE)) |
mbed_official | 146:f64d43ff0c18 | 4051 | #endif |
mbed_official | 146:f64d43ff0c18 | 4052 | |
mbed_official | 146:f64d43ff0c18 | 4053 | //! @brief Format value for bitfield UART_IE7816_CWTE. |
mbed_official | 146:f64d43ff0c18 | 4054 | #define BF_UART_IE7816_CWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_CWTE), uint8_t) & BM_UART_IE7816_CWTE) |
mbed_official | 146:f64d43ff0c18 | 4055 | |
mbed_official | 146:f64d43ff0c18 | 4056 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4057 | //! @brief Set the CWTE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4058 | #define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4059 | #endif |
mbed_official | 146:f64d43ff0c18 | 4060 | //@} |
mbed_official | 146:f64d43ff0c18 | 4061 | |
mbed_official | 146:f64d43ff0c18 | 4062 | /*! |
mbed_official | 146:f64d43ff0c18 | 4063 | * @name Register UART_IE7816, field WTE[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 4064 | * |
mbed_official | 146:f64d43ff0c18 | 4065 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4066 | * - 0 - The assertion of IS7816[WT] does not result in the generation of an |
mbed_official | 146:f64d43ff0c18 | 4067 | * interrupt. |
mbed_official | 146:f64d43ff0c18 | 4068 | * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt. |
mbed_official | 146:f64d43ff0c18 | 4069 | */ |
mbed_official | 146:f64d43ff0c18 | 4070 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4071 | #define BP_UART_IE7816_WTE (7U) //!< Bit position for UART_IE7816_WTE. |
mbed_official | 146:f64d43ff0c18 | 4072 | #define BM_UART_IE7816_WTE (0x80U) //!< Bit mask for UART_IE7816_WTE. |
mbed_official | 146:f64d43ff0c18 | 4073 | #define BS_UART_IE7816_WTE (1U) //!< Bit field size in bits for UART_IE7816_WTE. |
mbed_official | 146:f64d43ff0c18 | 4074 | |
mbed_official | 146:f64d43ff0c18 | 4075 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4076 | //! @brief Read current value of the UART_IE7816_WTE field. |
mbed_official | 146:f64d43ff0c18 | 4077 | #define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE)) |
mbed_official | 146:f64d43ff0c18 | 4078 | #endif |
mbed_official | 146:f64d43ff0c18 | 4079 | |
mbed_official | 146:f64d43ff0c18 | 4080 | //! @brief Format value for bitfield UART_IE7816_WTE. |
mbed_official | 146:f64d43ff0c18 | 4081 | #define BF_UART_IE7816_WTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_WTE), uint8_t) & BM_UART_IE7816_WTE) |
mbed_official | 146:f64d43ff0c18 | 4082 | |
mbed_official | 146:f64d43ff0c18 | 4083 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4084 | //! @brief Set the WTE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4085 | #define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4086 | #endif |
mbed_official | 146:f64d43ff0c18 | 4087 | //@} |
mbed_official | 146:f64d43ff0c18 | 4088 | |
mbed_official | 146:f64d43ff0c18 | 4089 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4090 | // HW_UART_IS7816 - UART 7816 Interrupt Status Register |
mbed_official | 146:f64d43ff0c18 | 4091 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4092 | |
mbed_official | 146:f64d43ff0c18 | 4093 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4094 | /*! |
mbed_official | 146:f64d43ff0c18 | 4095 | * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4096 | * |
mbed_official | 146:f64d43ff0c18 | 4097 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 4098 | * |
mbed_official | 146:f64d43ff0c18 | 4099 | * The IS7816 register provides a mechanism to read and clear the interrupt |
mbed_official | 146:f64d43ff0c18 | 4100 | * flags. All flags/interrupts are cleared by writing a 1 to the field location. |
mbed_official | 146:f64d43ff0c18 | 4101 | * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only |
mbed_official | 146:f64d43ff0c18 | 4102 | * the flag condition that occurred since the last time the bit was cleared, not |
mbed_official | 146:f64d43ff0c18 | 4103 | * that the condition currently exists. The status flags are set regardless of |
mbed_official | 146:f64d43ff0c18 | 4104 | * whether the corresponding field in the IE7816 is set or cleared. The IE7816 |
mbed_official | 146:f64d43ff0c18 | 4105 | * controls only if an interrupt is issued to the host processor. This register is |
mbed_official | 146:f64d43ff0c18 | 4106 | * specific to 7816 functionality and the values in this register have no affect on |
mbed_official | 146:f64d43ff0c18 | 4107 | * UART operation and should be ignored if 7816E is not set/enabled. This |
mbed_official | 146:f64d43ff0c18 | 4108 | * register may be read or written at anytime. |
mbed_official | 146:f64d43ff0c18 | 4109 | */ |
mbed_official | 146:f64d43ff0c18 | 4110 | typedef union _hw_uart_is7816 |
mbed_official | 146:f64d43ff0c18 | 4111 | { |
mbed_official | 146:f64d43ff0c18 | 4112 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4113 | struct _hw_uart_is7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 4114 | { |
mbed_official | 146:f64d43ff0c18 | 4115 | uint8_t RXT : 1; //!< [0] Receive Threshold Exceeded Interrupt |
mbed_official | 146:f64d43ff0c18 | 4116 | uint8_t TXT : 1; //!< [1] Transmit Threshold Exceeded Interrupt |
mbed_official | 146:f64d43ff0c18 | 4117 | uint8_t GTV : 1; //!< [2] Guard Timer Violated Interrupt |
mbed_official | 146:f64d43ff0c18 | 4118 | uint8_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 4119 | uint8_t INITD : 1; //!< [4] Initial Character Detected Interrupt |
mbed_official | 146:f64d43ff0c18 | 4120 | uint8_t BWT : 1; //!< [5] Block Wait Timer Interrupt |
mbed_official | 146:f64d43ff0c18 | 4121 | uint8_t CWT : 1; //!< [6] Character Wait Timer Interrupt |
mbed_official | 146:f64d43ff0c18 | 4122 | uint8_t WT : 1; //!< [7] Wait Timer Interrupt |
mbed_official | 146:f64d43ff0c18 | 4123 | } B; |
mbed_official | 146:f64d43ff0c18 | 4124 | } hw_uart_is7816_t; |
mbed_official | 146:f64d43ff0c18 | 4125 | #endif |
mbed_official | 146:f64d43ff0c18 | 4126 | |
mbed_official | 146:f64d43ff0c18 | 4127 | /*! |
mbed_official | 146:f64d43ff0c18 | 4128 | * @name Constants and macros for entire UART_IS7816 register |
mbed_official | 146:f64d43ff0c18 | 4129 | */ |
mbed_official | 146:f64d43ff0c18 | 4130 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4131 | #define HW_UART_IS7816_ADDR(x) (REGS_UART_BASE(x) + 0x1AU) |
mbed_official | 146:f64d43ff0c18 | 4132 | |
mbed_official | 146:f64d43ff0c18 | 4133 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4134 | #define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4135 | #define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4136 | #define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4137 | #define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4138 | #define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4139 | #define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4140 | #endif |
mbed_official | 146:f64d43ff0c18 | 4141 | //@} |
mbed_official | 146:f64d43ff0c18 | 4142 | |
mbed_official | 146:f64d43ff0c18 | 4143 | /* |
mbed_official | 146:f64d43ff0c18 | 4144 | * Constants & macros for individual UART_IS7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 4145 | */ |
mbed_official | 146:f64d43ff0c18 | 4146 | |
mbed_official | 146:f64d43ff0c18 | 4147 | /*! |
mbed_official | 146:f64d43ff0c18 | 4148 | * @name Register UART_IS7816, field RXT[0] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4149 | * |
mbed_official | 146:f64d43ff0c18 | 4150 | * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS |
mbed_official | 146:f64d43ff0c18 | 4151 | * generated in response to parity errors on received data. This flag requires ANACK |
mbed_official | 146:f64d43ff0c18 | 4152 | * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0. |
mbed_official | 146:f64d43ff0c18 | 4153 | * Clearing this field also resets the counter keeping track of consecutive NACKS. The |
mbed_official | 146:f64d43ff0c18 | 4154 | * UART will continue to attempt to receive data regardless of whether this flag |
mbed_official | 146:f64d43ff0c18 | 4155 | * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1, |
mbed_official | 146:f64d43ff0c18 | 4156 | * or packet is received without needing to issue a NACK, the internal NACK |
mbed_official | 146:f64d43ff0c18 | 4157 | * detection counter is cleared and the count restarts from zero on the next |
mbed_official | 146:f64d43ff0c18 | 4158 | * transmitted NACK. This interrupt is cleared by writing 1. |
mbed_official | 146:f64d43ff0c18 | 4159 | * |
mbed_official | 146:f64d43ff0c18 | 4160 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4161 | * - 0 - The number of consecutive NACKS generated as a result of parity errors |
mbed_official | 146:f64d43ff0c18 | 4162 | * and buffer overruns is less than or equal to the value in |
mbed_official | 146:f64d43ff0c18 | 4163 | * ET7816[RXTHRESHOLD]. |
mbed_official | 146:f64d43ff0c18 | 4164 | * - 1 - The number of consecutive NACKS generated as a result of parity errors |
mbed_official | 146:f64d43ff0c18 | 4165 | * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. |
mbed_official | 146:f64d43ff0c18 | 4166 | */ |
mbed_official | 146:f64d43ff0c18 | 4167 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4168 | #define BP_UART_IS7816_RXT (0U) //!< Bit position for UART_IS7816_RXT. |
mbed_official | 146:f64d43ff0c18 | 4169 | #define BM_UART_IS7816_RXT (0x01U) //!< Bit mask for UART_IS7816_RXT. |
mbed_official | 146:f64d43ff0c18 | 4170 | #define BS_UART_IS7816_RXT (1U) //!< Bit field size in bits for UART_IS7816_RXT. |
mbed_official | 146:f64d43ff0c18 | 4171 | |
mbed_official | 146:f64d43ff0c18 | 4172 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4173 | //! @brief Read current value of the UART_IS7816_RXT field. |
mbed_official | 146:f64d43ff0c18 | 4174 | #define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT)) |
mbed_official | 146:f64d43ff0c18 | 4175 | #endif |
mbed_official | 146:f64d43ff0c18 | 4176 | |
mbed_official | 146:f64d43ff0c18 | 4177 | //! @brief Format value for bitfield UART_IS7816_RXT. |
mbed_official | 146:f64d43ff0c18 | 4178 | #define BF_UART_IS7816_RXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_RXT), uint8_t) & BM_UART_IS7816_RXT) |
mbed_official | 146:f64d43ff0c18 | 4179 | |
mbed_official | 146:f64d43ff0c18 | 4180 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4181 | //! @brief Set the RXT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4182 | #define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4183 | #endif |
mbed_official | 146:f64d43ff0c18 | 4184 | //@} |
mbed_official | 146:f64d43ff0c18 | 4185 | |
mbed_official | 146:f64d43ff0c18 | 4186 | /*! |
mbed_official | 146:f64d43ff0c18 | 4187 | * @name Register UART_IS7816, field TXT[1] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4188 | * |
mbed_official | 146:f64d43ff0c18 | 4189 | * Indicates that the transmit NACK threshold has been exceeded as indicated by |
mbed_official | 146:f64d43ff0c18 | 4190 | * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART |
mbed_official | 146:f64d43ff0c18 | 4191 | * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If |
mbed_official | 146:f64d43ff0c18 | 4192 | * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is |
mbed_official | 146:f64d43ff0c18 | 4193 | * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the |
mbed_official | 146:f64d43ff0c18 | 4194 | * internal NACK detection counter is cleared and the count restarts from zero on |
mbed_official | 146:f64d43ff0c18 | 4195 | * the next received NACK. This interrupt is cleared by writing 1. |
mbed_official | 146:f64d43ff0c18 | 4196 | * |
mbed_official | 146:f64d43ff0c18 | 4197 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4198 | * - 0 - The number of retries and corresponding NACKS does not exceed the value |
mbed_official | 146:f64d43ff0c18 | 4199 | * in ET7816[TXTHRESHOLD]. |
mbed_official | 146:f64d43ff0c18 | 4200 | * - 1 - The number of retries and corresponding NACKS exceeds the value in |
mbed_official | 146:f64d43ff0c18 | 4201 | * ET7816[TXTHRESHOLD]. |
mbed_official | 146:f64d43ff0c18 | 4202 | */ |
mbed_official | 146:f64d43ff0c18 | 4203 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4204 | #define BP_UART_IS7816_TXT (1U) //!< Bit position for UART_IS7816_TXT. |
mbed_official | 146:f64d43ff0c18 | 4205 | #define BM_UART_IS7816_TXT (0x02U) //!< Bit mask for UART_IS7816_TXT. |
mbed_official | 146:f64d43ff0c18 | 4206 | #define BS_UART_IS7816_TXT (1U) //!< Bit field size in bits for UART_IS7816_TXT. |
mbed_official | 146:f64d43ff0c18 | 4207 | |
mbed_official | 146:f64d43ff0c18 | 4208 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4209 | //! @brief Read current value of the UART_IS7816_TXT field. |
mbed_official | 146:f64d43ff0c18 | 4210 | #define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT)) |
mbed_official | 146:f64d43ff0c18 | 4211 | #endif |
mbed_official | 146:f64d43ff0c18 | 4212 | |
mbed_official | 146:f64d43ff0c18 | 4213 | //! @brief Format value for bitfield UART_IS7816_TXT. |
mbed_official | 146:f64d43ff0c18 | 4214 | #define BF_UART_IS7816_TXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_TXT), uint8_t) & BM_UART_IS7816_TXT) |
mbed_official | 146:f64d43ff0c18 | 4215 | |
mbed_official | 146:f64d43ff0c18 | 4216 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4217 | //! @brief Set the TXT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4218 | #define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4219 | #endif |
mbed_official | 146:f64d43ff0c18 | 4220 | //@} |
mbed_official | 146:f64d43ff0c18 | 4221 | |
mbed_official | 146:f64d43ff0c18 | 4222 | /*! |
mbed_official | 146:f64d43ff0c18 | 4223 | * @name Register UART_IS7816, field GTV[2] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4224 | * |
mbed_official | 146:f64d43ff0c18 | 4225 | * Indicates that one or more of the character guard time, block guard time, or |
mbed_official | 146:f64d43ff0c18 | 4226 | * guard time are violated. This interrupt is cleared by writing 1. |
mbed_official | 146:f64d43ff0c18 | 4227 | * |
mbed_official | 146:f64d43ff0c18 | 4228 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4229 | * - 0 - A guard time (GT, CGT, or BGT) has not been violated. |
mbed_official | 146:f64d43ff0c18 | 4230 | * - 1 - A guard time (GT, CGT, or BGT) has been violated. |
mbed_official | 146:f64d43ff0c18 | 4231 | */ |
mbed_official | 146:f64d43ff0c18 | 4232 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4233 | #define BP_UART_IS7816_GTV (2U) //!< Bit position for UART_IS7816_GTV. |
mbed_official | 146:f64d43ff0c18 | 4234 | #define BM_UART_IS7816_GTV (0x04U) //!< Bit mask for UART_IS7816_GTV. |
mbed_official | 146:f64d43ff0c18 | 4235 | #define BS_UART_IS7816_GTV (1U) //!< Bit field size in bits for UART_IS7816_GTV. |
mbed_official | 146:f64d43ff0c18 | 4236 | |
mbed_official | 146:f64d43ff0c18 | 4237 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4238 | //! @brief Read current value of the UART_IS7816_GTV field. |
mbed_official | 146:f64d43ff0c18 | 4239 | #define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV)) |
mbed_official | 146:f64d43ff0c18 | 4240 | #endif |
mbed_official | 146:f64d43ff0c18 | 4241 | |
mbed_official | 146:f64d43ff0c18 | 4242 | //! @brief Format value for bitfield UART_IS7816_GTV. |
mbed_official | 146:f64d43ff0c18 | 4243 | #define BF_UART_IS7816_GTV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_GTV), uint8_t) & BM_UART_IS7816_GTV) |
mbed_official | 146:f64d43ff0c18 | 4244 | |
mbed_official | 146:f64d43ff0c18 | 4245 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4246 | //! @brief Set the GTV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4247 | #define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4248 | #endif |
mbed_official | 146:f64d43ff0c18 | 4249 | //@} |
mbed_official | 146:f64d43ff0c18 | 4250 | |
mbed_official | 146:f64d43ff0c18 | 4251 | /*! |
mbed_official | 146:f64d43ff0c18 | 4252 | * @name Register UART_IS7816, field INITD[4] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4253 | * |
mbed_official | 146:f64d43ff0c18 | 4254 | * Indicates that a valid initial character is received. This interrupt is |
mbed_official | 146:f64d43ff0c18 | 4255 | * cleared by writing 1. |
mbed_official | 146:f64d43ff0c18 | 4256 | * |
mbed_official | 146:f64d43ff0c18 | 4257 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4258 | * - 0 - A valid initial character has not been received. |
mbed_official | 146:f64d43ff0c18 | 4259 | * - 1 - A valid initial character has been received. |
mbed_official | 146:f64d43ff0c18 | 4260 | */ |
mbed_official | 146:f64d43ff0c18 | 4261 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4262 | #define BP_UART_IS7816_INITD (4U) //!< Bit position for UART_IS7816_INITD. |
mbed_official | 146:f64d43ff0c18 | 4263 | #define BM_UART_IS7816_INITD (0x10U) //!< Bit mask for UART_IS7816_INITD. |
mbed_official | 146:f64d43ff0c18 | 4264 | #define BS_UART_IS7816_INITD (1U) //!< Bit field size in bits for UART_IS7816_INITD. |
mbed_official | 146:f64d43ff0c18 | 4265 | |
mbed_official | 146:f64d43ff0c18 | 4266 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4267 | //! @brief Read current value of the UART_IS7816_INITD field. |
mbed_official | 146:f64d43ff0c18 | 4268 | #define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD)) |
mbed_official | 146:f64d43ff0c18 | 4269 | #endif |
mbed_official | 146:f64d43ff0c18 | 4270 | |
mbed_official | 146:f64d43ff0c18 | 4271 | //! @brief Format value for bitfield UART_IS7816_INITD. |
mbed_official | 146:f64d43ff0c18 | 4272 | #define BF_UART_IS7816_INITD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_INITD), uint8_t) & BM_UART_IS7816_INITD) |
mbed_official | 146:f64d43ff0c18 | 4273 | |
mbed_official | 146:f64d43ff0c18 | 4274 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4275 | //! @brief Set the INITD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4276 | #define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4277 | #endif |
mbed_official | 146:f64d43ff0c18 | 4278 | //@} |
mbed_official | 146:f64d43ff0c18 | 4279 | |
mbed_official | 146:f64d43ff0c18 | 4280 | /*! |
mbed_official | 146:f64d43ff0c18 | 4281 | * @name Register UART_IS7816, field BWT[5] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4282 | * |
mbed_official | 146:f64d43ff0c18 | 4283 | * Indicates that the block wait time, the time between the leading edge of |
mbed_official | 146:f64d43ff0c18 | 4284 | * first received character of a block and the leading edge of the last character the |
mbed_official | 146:f64d43ff0c18 | 4285 | * previously transmitted block, has exceeded the programmed value. This flag |
mbed_official | 146:f64d43ff0c18 | 4286 | * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1. |
mbed_official | 146:f64d43ff0c18 | 4287 | * |
mbed_official | 146:f64d43ff0c18 | 4288 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4289 | * - 0 - Block wait time (BWT) has not been violated. |
mbed_official | 146:f64d43ff0c18 | 4290 | * - 1 - Block wait time (BWT) has been violated. |
mbed_official | 146:f64d43ff0c18 | 4291 | */ |
mbed_official | 146:f64d43ff0c18 | 4292 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4293 | #define BP_UART_IS7816_BWT (5U) //!< Bit position for UART_IS7816_BWT. |
mbed_official | 146:f64d43ff0c18 | 4294 | #define BM_UART_IS7816_BWT (0x20U) //!< Bit mask for UART_IS7816_BWT. |
mbed_official | 146:f64d43ff0c18 | 4295 | #define BS_UART_IS7816_BWT (1U) //!< Bit field size in bits for UART_IS7816_BWT. |
mbed_official | 146:f64d43ff0c18 | 4296 | |
mbed_official | 146:f64d43ff0c18 | 4297 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4298 | //! @brief Read current value of the UART_IS7816_BWT field. |
mbed_official | 146:f64d43ff0c18 | 4299 | #define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT)) |
mbed_official | 146:f64d43ff0c18 | 4300 | #endif |
mbed_official | 146:f64d43ff0c18 | 4301 | |
mbed_official | 146:f64d43ff0c18 | 4302 | //! @brief Format value for bitfield UART_IS7816_BWT. |
mbed_official | 146:f64d43ff0c18 | 4303 | #define BF_UART_IS7816_BWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_BWT), uint8_t) & BM_UART_IS7816_BWT) |
mbed_official | 146:f64d43ff0c18 | 4304 | |
mbed_official | 146:f64d43ff0c18 | 4305 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4306 | //! @brief Set the BWT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4307 | #define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4308 | #endif |
mbed_official | 146:f64d43ff0c18 | 4309 | //@} |
mbed_official | 146:f64d43ff0c18 | 4310 | |
mbed_official | 146:f64d43ff0c18 | 4311 | /*! |
mbed_official | 146:f64d43ff0c18 | 4312 | * @name Register UART_IS7816, field CWT[6] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4313 | * |
mbed_official | 146:f64d43ff0c18 | 4314 | * Indicates that the character wait time, the time between the leading edges of |
mbed_official | 146:f64d43ff0c18 | 4315 | * two consecutive characters in a block, has exceeded the programmed value. |
mbed_official | 146:f64d43ff0c18 | 4316 | * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by |
mbed_official | 146:f64d43ff0c18 | 4317 | * writing 1. |
mbed_official | 146:f64d43ff0c18 | 4318 | * |
mbed_official | 146:f64d43ff0c18 | 4319 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4320 | * - 0 - Character wait time (CWT) has not been violated. |
mbed_official | 146:f64d43ff0c18 | 4321 | * - 1 - Character wait time (CWT) has been violated. |
mbed_official | 146:f64d43ff0c18 | 4322 | */ |
mbed_official | 146:f64d43ff0c18 | 4323 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4324 | #define BP_UART_IS7816_CWT (6U) //!< Bit position for UART_IS7816_CWT. |
mbed_official | 146:f64d43ff0c18 | 4325 | #define BM_UART_IS7816_CWT (0x40U) //!< Bit mask for UART_IS7816_CWT. |
mbed_official | 146:f64d43ff0c18 | 4326 | #define BS_UART_IS7816_CWT (1U) //!< Bit field size in bits for UART_IS7816_CWT. |
mbed_official | 146:f64d43ff0c18 | 4327 | |
mbed_official | 146:f64d43ff0c18 | 4328 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4329 | //! @brief Read current value of the UART_IS7816_CWT field. |
mbed_official | 146:f64d43ff0c18 | 4330 | #define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT)) |
mbed_official | 146:f64d43ff0c18 | 4331 | #endif |
mbed_official | 146:f64d43ff0c18 | 4332 | |
mbed_official | 146:f64d43ff0c18 | 4333 | //! @brief Format value for bitfield UART_IS7816_CWT. |
mbed_official | 146:f64d43ff0c18 | 4334 | #define BF_UART_IS7816_CWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_CWT), uint8_t) & BM_UART_IS7816_CWT) |
mbed_official | 146:f64d43ff0c18 | 4335 | |
mbed_official | 146:f64d43ff0c18 | 4336 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4337 | //! @brief Set the CWT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4338 | #define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4339 | #endif |
mbed_official | 146:f64d43ff0c18 | 4340 | //@} |
mbed_official | 146:f64d43ff0c18 | 4341 | |
mbed_official | 146:f64d43ff0c18 | 4342 | /*! |
mbed_official | 146:f64d43ff0c18 | 4343 | * @name Register UART_IS7816, field WT[7] (W1C) |
mbed_official | 146:f64d43ff0c18 | 4344 | * |
mbed_official | 146:f64d43ff0c18 | 4345 | * Indicates that the wait time, the time between the leading edge of a |
mbed_official | 146:f64d43ff0c18 | 4346 | * character being transmitted and the leading edge of the next response character, has |
mbed_official | 146:f64d43ff0c18 | 4347 | * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0. |
mbed_official | 146:f64d43ff0c18 | 4348 | * This interrupt is cleared by writing 1. |
mbed_official | 146:f64d43ff0c18 | 4349 | * |
mbed_official | 146:f64d43ff0c18 | 4350 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4351 | * - 0 - Wait time (WT) has not been violated. |
mbed_official | 146:f64d43ff0c18 | 4352 | * - 1 - Wait time (WT) has been violated. |
mbed_official | 146:f64d43ff0c18 | 4353 | */ |
mbed_official | 146:f64d43ff0c18 | 4354 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4355 | #define BP_UART_IS7816_WT (7U) //!< Bit position for UART_IS7816_WT. |
mbed_official | 146:f64d43ff0c18 | 4356 | #define BM_UART_IS7816_WT (0x80U) //!< Bit mask for UART_IS7816_WT. |
mbed_official | 146:f64d43ff0c18 | 4357 | #define BS_UART_IS7816_WT (1U) //!< Bit field size in bits for UART_IS7816_WT. |
mbed_official | 146:f64d43ff0c18 | 4358 | |
mbed_official | 146:f64d43ff0c18 | 4359 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4360 | //! @brief Read current value of the UART_IS7816_WT field. |
mbed_official | 146:f64d43ff0c18 | 4361 | #define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT)) |
mbed_official | 146:f64d43ff0c18 | 4362 | #endif |
mbed_official | 146:f64d43ff0c18 | 4363 | |
mbed_official | 146:f64d43ff0c18 | 4364 | //! @brief Format value for bitfield UART_IS7816_WT. |
mbed_official | 146:f64d43ff0c18 | 4365 | #define BF_UART_IS7816_WT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_WT), uint8_t) & BM_UART_IS7816_WT) |
mbed_official | 146:f64d43ff0c18 | 4366 | |
mbed_official | 146:f64d43ff0c18 | 4367 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4368 | //! @brief Set the WT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4369 | #define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 4370 | #endif |
mbed_official | 146:f64d43ff0c18 | 4371 | //@} |
mbed_official | 146:f64d43ff0c18 | 4372 | |
mbed_official | 146:f64d43ff0c18 | 4373 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4374 | // HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register |
mbed_official | 146:f64d43ff0c18 | 4375 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4376 | |
mbed_official | 146:f64d43ff0c18 | 4377 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4378 | /*! |
mbed_official | 146:f64d43ff0c18 | 4379 | * @brief HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4380 | * |
mbed_official | 146:f64d43ff0c18 | 4381 | * Reset value: 0x0AU |
mbed_official | 146:f64d43ff0c18 | 4382 | * |
mbed_official | 146:f64d43ff0c18 | 4383 | * The WP7816 register contains constants used in the generation of various wait |
mbed_official | 146:f64d43ff0c18 | 4384 | * timer counters. To save register space, this register is used differently |
mbed_official | 146:f64d43ff0c18 | 4385 | * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any |
mbed_official | 146:f64d43ff0c18 | 4386 | * time. This register must be written to only when C7816[ISO_7816E] is not set. |
mbed_official | 146:f64d43ff0c18 | 4387 | */ |
mbed_official | 146:f64d43ff0c18 | 4388 | typedef union _hw_uart_wp7816_t_type0 |
mbed_official | 146:f64d43ff0c18 | 4389 | { |
mbed_official | 146:f64d43ff0c18 | 4390 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4391 | struct _hw_uart_wp7816_t_type0_bitfields |
mbed_official | 146:f64d43ff0c18 | 4392 | { |
mbed_official | 146:f64d43ff0c18 | 4393 | uint8_t WI : 8; //!< [7:0] Wait Time Integer (C7816[TTYPE] = 0) |
mbed_official | 146:f64d43ff0c18 | 4394 | } B; |
mbed_official | 146:f64d43ff0c18 | 4395 | } hw_uart_wp7816_t_type0_t; |
mbed_official | 146:f64d43ff0c18 | 4396 | #endif |
mbed_official | 146:f64d43ff0c18 | 4397 | |
mbed_official | 146:f64d43ff0c18 | 4398 | /*! |
mbed_official | 146:f64d43ff0c18 | 4399 | * @name Constants and macros for entire UART_WP7816_T_TYPE0 register |
mbed_official | 146:f64d43ff0c18 | 4400 | */ |
mbed_official | 146:f64d43ff0c18 | 4401 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4402 | #define HW_UART_WP7816_T_TYPE0_ADDR(x) (REGS_UART_BASE(x) + 0x1BU) |
mbed_official | 146:f64d43ff0c18 | 4403 | |
mbed_official | 146:f64d43ff0c18 | 4404 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4405 | #define HW_UART_WP7816_T_TYPE0(x) (*(__IO hw_uart_wp7816_t_type0_t *) HW_UART_WP7816_T_TYPE0_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4406 | #define HW_UART_WP7816_T_TYPE0_RD(x) (HW_UART_WP7816_T_TYPE0(x).U) |
mbed_official | 146:f64d43ff0c18 | 4407 | #define HW_UART_WP7816_T_TYPE0_WR(x, v) (HW_UART_WP7816_T_TYPE0(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4408 | #define HW_UART_WP7816_T_TYPE0_SET(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4409 | #define HW_UART_WP7816_T_TYPE0_CLR(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4410 | #define HW_UART_WP7816_T_TYPE0_TOG(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4411 | #endif |
mbed_official | 146:f64d43ff0c18 | 4412 | //@} |
mbed_official | 146:f64d43ff0c18 | 4413 | |
mbed_official | 146:f64d43ff0c18 | 4414 | /* |
mbed_official | 146:f64d43ff0c18 | 4415 | * Constants & macros for individual UART_WP7816_T_TYPE0 bitfields |
mbed_official | 146:f64d43ff0c18 | 4416 | */ |
mbed_official | 146:f64d43ff0c18 | 4417 | |
mbed_official | 146:f64d43ff0c18 | 4418 | /*! |
mbed_official | 146:f64d43ff0c18 | 4419 | * @name Register UART_WP7816_T_TYPE0, field WI[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4420 | * |
mbed_official | 146:f64d43ff0c18 | 4421 | * Used to calculate the value used for the WT counter. It represents a value |
mbed_official | 146:f64d43ff0c18 | 4422 | * between 1 and 255. The value of zero is not valid. This value is used only when |
mbed_official | 146:f64d43ff0c18 | 4423 | * C7816[TTYPE] = 0. See Wait time and guard time parameters. |
mbed_official | 146:f64d43ff0c18 | 4424 | */ |
mbed_official | 146:f64d43ff0c18 | 4425 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4426 | #define BP_UART_WP7816_T_TYPE0_WI (0U) //!< Bit position for UART_WP7816_T_TYPE0_WI. |
mbed_official | 146:f64d43ff0c18 | 4427 | #define BM_UART_WP7816_T_TYPE0_WI (0xFFU) //!< Bit mask for UART_WP7816_T_TYPE0_WI. |
mbed_official | 146:f64d43ff0c18 | 4428 | #define BS_UART_WP7816_T_TYPE0_WI (8U) //!< Bit field size in bits for UART_WP7816_T_TYPE0_WI. |
mbed_official | 146:f64d43ff0c18 | 4429 | |
mbed_official | 146:f64d43ff0c18 | 4430 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4431 | //! @brief Read current value of the UART_WP7816_T_TYPE0_WI field. |
mbed_official | 146:f64d43ff0c18 | 4432 | #define BR_UART_WP7816_T_TYPE0_WI(x) (HW_UART_WP7816_T_TYPE0(x).U) |
mbed_official | 146:f64d43ff0c18 | 4433 | #endif |
mbed_official | 146:f64d43ff0c18 | 4434 | |
mbed_official | 146:f64d43ff0c18 | 4435 | //! @brief Format value for bitfield UART_WP7816_T_TYPE0_WI. |
mbed_official | 146:f64d43ff0c18 | 4436 | #define BF_UART_WP7816_T_TYPE0_WI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE0_WI), uint8_t) & BM_UART_WP7816_T_TYPE0_WI) |
mbed_official | 146:f64d43ff0c18 | 4437 | |
mbed_official | 146:f64d43ff0c18 | 4438 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4439 | //! @brief Set the WI field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4440 | #define BW_UART_WP7816_T_TYPE0_WI(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 4441 | #endif |
mbed_official | 146:f64d43ff0c18 | 4442 | //@} |
mbed_official | 146:f64d43ff0c18 | 4443 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4444 | // HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register |
mbed_official | 146:f64d43ff0c18 | 4445 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4446 | |
mbed_official | 146:f64d43ff0c18 | 4447 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4448 | /*! |
mbed_official | 146:f64d43ff0c18 | 4449 | * @brief HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4450 | * |
mbed_official | 146:f64d43ff0c18 | 4451 | * Reset value: 0x0AU |
mbed_official | 146:f64d43ff0c18 | 4452 | * |
mbed_official | 146:f64d43ff0c18 | 4453 | * The WP7816 register contains constants used in the generation of various wait |
mbed_official | 146:f64d43ff0c18 | 4454 | * timer counters. To save register space, this register is used differently |
mbed_official | 146:f64d43ff0c18 | 4455 | * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any |
mbed_official | 146:f64d43ff0c18 | 4456 | * time. This register must be written to only when C7816[ISO_7816E] is not set. |
mbed_official | 146:f64d43ff0c18 | 4457 | */ |
mbed_official | 146:f64d43ff0c18 | 4458 | typedef union _hw_uart_wp7816_t_type1 |
mbed_official | 146:f64d43ff0c18 | 4459 | { |
mbed_official | 146:f64d43ff0c18 | 4460 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4461 | struct _hw_uart_wp7816_t_type1_bitfields |
mbed_official | 146:f64d43ff0c18 | 4462 | { |
mbed_official | 146:f64d43ff0c18 | 4463 | uint8_t BWI : 4; //!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1) |
mbed_official | 146:f64d43ff0c18 | 4464 | uint8_t CWI : 4; //!< [7:4] Character Wait Time Integer (C7816[TTYPE] |
mbed_official | 146:f64d43ff0c18 | 4465 | //! = 1) |
mbed_official | 146:f64d43ff0c18 | 4466 | } B; |
mbed_official | 146:f64d43ff0c18 | 4467 | } hw_uart_wp7816_t_type1_t; |
mbed_official | 146:f64d43ff0c18 | 4468 | #endif |
mbed_official | 146:f64d43ff0c18 | 4469 | |
mbed_official | 146:f64d43ff0c18 | 4470 | /*! |
mbed_official | 146:f64d43ff0c18 | 4471 | * @name Constants and macros for entire UART_WP7816_T_TYPE1 register |
mbed_official | 146:f64d43ff0c18 | 4472 | */ |
mbed_official | 146:f64d43ff0c18 | 4473 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4474 | #define HW_UART_WP7816_T_TYPE1_ADDR(x) (REGS_UART_BASE(x) + 0x1BU) |
mbed_official | 146:f64d43ff0c18 | 4475 | |
mbed_official | 146:f64d43ff0c18 | 4476 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4477 | #define HW_UART_WP7816_T_TYPE1(x) (*(__IO hw_uart_wp7816_t_type1_t *) HW_UART_WP7816_T_TYPE1_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4478 | #define HW_UART_WP7816_T_TYPE1_RD(x) (HW_UART_WP7816_T_TYPE1(x).U) |
mbed_official | 146:f64d43ff0c18 | 4479 | #define HW_UART_WP7816_T_TYPE1_WR(x, v) (HW_UART_WP7816_T_TYPE1(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4480 | #define HW_UART_WP7816_T_TYPE1_SET(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4481 | #define HW_UART_WP7816_T_TYPE1_CLR(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4482 | #define HW_UART_WP7816_T_TYPE1_TOG(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4483 | #endif |
mbed_official | 146:f64d43ff0c18 | 4484 | //@} |
mbed_official | 146:f64d43ff0c18 | 4485 | |
mbed_official | 146:f64d43ff0c18 | 4486 | /* |
mbed_official | 146:f64d43ff0c18 | 4487 | * Constants & macros for individual UART_WP7816_T_TYPE1 bitfields |
mbed_official | 146:f64d43ff0c18 | 4488 | */ |
mbed_official | 146:f64d43ff0c18 | 4489 | |
mbed_official | 146:f64d43ff0c18 | 4490 | /*! |
mbed_official | 146:f64d43ff0c18 | 4491 | * @name Register UART_WP7816_T_TYPE1, field BWI[3:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4492 | * |
mbed_official | 146:f64d43ff0c18 | 4493 | * Used to calculate the value used for the BWT counter. It represent a value |
mbed_official | 146:f64d43ff0c18 | 4494 | * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time |
mbed_official | 146:f64d43ff0c18 | 4495 | * and guard time parameters . |
mbed_official | 146:f64d43ff0c18 | 4496 | */ |
mbed_official | 146:f64d43ff0c18 | 4497 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4498 | #define BP_UART_WP7816_T_TYPE1_BWI (0U) //!< Bit position for UART_WP7816_T_TYPE1_BWI. |
mbed_official | 146:f64d43ff0c18 | 4499 | #define BM_UART_WP7816_T_TYPE1_BWI (0x0FU) //!< Bit mask for UART_WP7816_T_TYPE1_BWI. |
mbed_official | 146:f64d43ff0c18 | 4500 | #define BS_UART_WP7816_T_TYPE1_BWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_BWI. |
mbed_official | 146:f64d43ff0c18 | 4501 | |
mbed_official | 146:f64d43ff0c18 | 4502 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4503 | //! @brief Read current value of the UART_WP7816_T_TYPE1_BWI field. |
mbed_official | 146:f64d43ff0c18 | 4504 | #define BR_UART_WP7816_T_TYPE1_BWI(x) (HW_UART_WP7816_T_TYPE1(x).B.BWI) |
mbed_official | 146:f64d43ff0c18 | 4505 | #endif |
mbed_official | 146:f64d43ff0c18 | 4506 | |
mbed_official | 146:f64d43ff0c18 | 4507 | //! @brief Format value for bitfield UART_WP7816_T_TYPE1_BWI. |
mbed_official | 146:f64d43ff0c18 | 4508 | #define BF_UART_WP7816_T_TYPE1_BWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_BWI), uint8_t) & BM_UART_WP7816_T_TYPE1_BWI) |
mbed_official | 146:f64d43ff0c18 | 4509 | |
mbed_official | 146:f64d43ff0c18 | 4510 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4511 | //! @brief Set the BWI field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4512 | #define BW_UART_WP7816_T_TYPE1_BWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_BWI) | BF_UART_WP7816_T_TYPE1_BWI(v))) |
mbed_official | 146:f64d43ff0c18 | 4513 | #endif |
mbed_official | 146:f64d43ff0c18 | 4514 | //@} |
mbed_official | 146:f64d43ff0c18 | 4515 | |
mbed_official | 146:f64d43ff0c18 | 4516 | /*! |
mbed_official | 146:f64d43ff0c18 | 4517 | * @name Register UART_WP7816_T_TYPE1, field CWI[7:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 4518 | * |
mbed_official | 146:f64d43ff0c18 | 4519 | * Used to calculate the value used for the CWT counter. It represents a value |
mbed_official | 146:f64d43ff0c18 | 4520 | * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time |
mbed_official | 146:f64d43ff0c18 | 4521 | * and guard time parameters . |
mbed_official | 146:f64d43ff0c18 | 4522 | */ |
mbed_official | 146:f64d43ff0c18 | 4523 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4524 | #define BP_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit position for UART_WP7816_T_TYPE1_CWI. |
mbed_official | 146:f64d43ff0c18 | 4525 | #define BM_UART_WP7816_T_TYPE1_CWI (0xF0U) //!< Bit mask for UART_WP7816_T_TYPE1_CWI. |
mbed_official | 146:f64d43ff0c18 | 4526 | #define BS_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_CWI. |
mbed_official | 146:f64d43ff0c18 | 4527 | |
mbed_official | 146:f64d43ff0c18 | 4528 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4529 | //! @brief Read current value of the UART_WP7816_T_TYPE1_CWI field. |
mbed_official | 146:f64d43ff0c18 | 4530 | #define BR_UART_WP7816_T_TYPE1_CWI(x) (HW_UART_WP7816_T_TYPE1(x).B.CWI) |
mbed_official | 146:f64d43ff0c18 | 4531 | #endif |
mbed_official | 146:f64d43ff0c18 | 4532 | |
mbed_official | 146:f64d43ff0c18 | 4533 | //! @brief Format value for bitfield UART_WP7816_T_TYPE1_CWI. |
mbed_official | 146:f64d43ff0c18 | 4534 | #define BF_UART_WP7816_T_TYPE1_CWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_CWI), uint8_t) & BM_UART_WP7816_T_TYPE1_CWI) |
mbed_official | 146:f64d43ff0c18 | 4535 | |
mbed_official | 146:f64d43ff0c18 | 4536 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4537 | //! @brief Set the CWI field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4538 | #define BW_UART_WP7816_T_TYPE1_CWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_CWI) | BF_UART_WP7816_T_TYPE1_CWI(v))) |
mbed_official | 146:f64d43ff0c18 | 4539 | #endif |
mbed_official | 146:f64d43ff0c18 | 4540 | //@} |
mbed_official | 146:f64d43ff0c18 | 4541 | |
mbed_official | 146:f64d43ff0c18 | 4542 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4543 | // HW_UART_WN7816 - UART 7816 Wait N Register |
mbed_official | 146:f64d43ff0c18 | 4544 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4545 | |
mbed_official | 146:f64d43ff0c18 | 4546 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4547 | /*! |
mbed_official | 146:f64d43ff0c18 | 4548 | * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4549 | * |
mbed_official | 146:f64d43ff0c18 | 4550 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 4551 | * |
mbed_official | 146:f64d43ff0c18 | 4552 | * The WN7816 register contains a parameter that is used in the calculation of |
mbed_official | 146:f64d43ff0c18 | 4553 | * the guard time counter. This register may be read at any time. This register |
mbed_official | 146:f64d43ff0c18 | 4554 | * must be written to only when C7816[ISO_7816E] is not set. |
mbed_official | 146:f64d43ff0c18 | 4555 | */ |
mbed_official | 146:f64d43ff0c18 | 4556 | typedef union _hw_uart_wn7816 |
mbed_official | 146:f64d43ff0c18 | 4557 | { |
mbed_official | 146:f64d43ff0c18 | 4558 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4559 | struct _hw_uart_wn7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 4560 | { |
mbed_official | 146:f64d43ff0c18 | 4561 | uint8_t GTN : 8; //!< [7:0] Guard Band N |
mbed_official | 146:f64d43ff0c18 | 4562 | } B; |
mbed_official | 146:f64d43ff0c18 | 4563 | } hw_uart_wn7816_t; |
mbed_official | 146:f64d43ff0c18 | 4564 | #endif |
mbed_official | 146:f64d43ff0c18 | 4565 | |
mbed_official | 146:f64d43ff0c18 | 4566 | /*! |
mbed_official | 146:f64d43ff0c18 | 4567 | * @name Constants and macros for entire UART_WN7816 register |
mbed_official | 146:f64d43ff0c18 | 4568 | */ |
mbed_official | 146:f64d43ff0c18 | 4569 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4570 | #define HW_UART_WN7816_ADDR(x) (REGS_UART_BASE(x) + 0x1CU) |
mbed_official | 146:f64d43ff0c18 | 4571 | |
mbed_official | 146:f64d43ff0c18 | 4572 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4573 | #define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4574 | #define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4575 | #define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4576 | #define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4577 | #define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4578 | #define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4579 | #endif |
mbed_official | 146:f64d43ff0c18 | 4580 | //@} |
mbed_official | 146:f64d43ff0c18 | 4581 | |
mbed_official | 146:f64d43ff0c18 | 4582 | /* |
mbed_official | 146:f64d43ff0c18 | 4583 | * Constants & macros for individual UART_WN7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 4584 | */ |
mbed_official | 146:f64d43ff0c18 | 4585 | |
mbed_official | 146:f64d43ff0c18 | 4586 | /*! |
mbed_official | 146:f64d43ff0c18 | 4587 | * @name Register UART_WN7816, field GTN[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4588 | * |
mbed_official | 146:f64d43ff0c18 | 4589 | * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The |
mbed_official | 146:f64d43ff0c18 | 4590 | * value represents an integer number between 0 and 255. See Wait time and guard |
mbed_official | 146:f64d43ff0c18 | 4591 | * time parameters . |
mbed_official | 146:f64d43ff0c18 | 4592 | */ |
mbed_official | 146:f64d43ff0c18 | 4593 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4594 | #define BP_UART_WN7816_GTN (0U) //!< Bit position for UART_WN7816_GTN. |
mbed_official | 146:f64d43ff0c18 | 4595 | #define BM_UART_WN7816_GTN (0xFFU) //!< Bit mask for UART_WN7816_GTN. |
mbed_official | 146:f64d43ff0c18 | 4596 | #define BS_UART_WN7816_GTN (8U) //!< Bit field size in bits for UART_WN7816_GTN. |
mbed_official | 146:f64d43ff0c18 | 4597 | |
mbed_official | 146:f64d43ff0c18 | 4598 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4599 | //! @brief Read current value of the UART_WN7816_GTN field. |
mbed_official | 146:f64d43ff0c18 | 4600 | #define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4601 | #endif |
mbed_official | 146:f64d43ff0c18 | 4602 | |
mbed_official | 146:f64d43ff0c18 | 4603 | //! @brief Format value for bitfield UART_WN7816_GTN. |
mbed_official | 146:f64d43ff0c18 | 4604 | #define BF_UART_WN7816_GTN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WN7816_GTN), uint8_t) & BM_UART_WN7816_GTN) |
mbed_official | 146:f64d43ff0c18 | 4605 | |
mbed_official | 146:f64d43ff0c18 | 4606 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4607 | //! @brief Set the GTN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4608 | #define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 4609 | #endif |
mbed_official | 146:f64d43ff0c18 | 4610 | //@} |
mbed_official | 146:f64d43ff0c18 | 4611 | |
mbed_official | 146:f64d43ff0c18 | 4612 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4613 | // HW_UART_WF7816 - UART 7816 Wait FD Register |
mbed_official | 146:f64d43ff0c18 | 4614 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4615 | |
mbed_official | 146:f64d43ff0c18 | 4616 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4617 | /*! |
mbed_official | 146:f64d43ff0c18 | 4618 | * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4619 | * |
mbed_official | 146:f64d43ff0c18 | 4620 | * Reset value: 0x01U |
mbed_official | 146:f64d43ff0c18 | 4621 | * |
mbed_official | 146:f64d43ff0c18 | 4622 | * The WF7816 contains parameters that are used in the generation of various |
mbed_official | 146:f64d43ff0c18 | 4623 | * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any |
mbed_official | 146:f64d43ff0c18 | 4624 | * time. This register must be written to only when C7816[ISO_7816E] is not set. |
mbed_official | 146:f64d43ff0c18 | 4625 | */ |
mbed_official | 146:f64d43ff0c18 | 4626 | typedef union _hw_uart_wf7816 |
mbed_official | 146:f64d43ff0c18 | 4627 | { |
mbed_official | 146:f64d43ff0c18 | 4628 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4629 | struct _hw_uart_wf7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 4630 | { |
mbed_official | 146:f64d43ff0c18 | 4631 | uint8_t GTFD : 8; //!< [7:0] FD Multiplier |
mbed_official | 146:f64d43ff0c18 | 4632 | } B; |
mbed_official | 146:f64d43ff0c18 | 4633 | } hw_uart_wf7816_t; |
mbed_official | 146:f64d43ff0c18 | 4634 | #endif |
mbed_official | 146:f64d43ff0c18 | 4635 | |
mbed_official | 146:f64d43ff0c18 | 4636 | /*! |
mbed_official | 146:f64d43ff0c18 | 4637 | * @name Constants and macros for entire UART_WF7816 register |
mbed_official | 146:f64d43ff0c18 | 4638 | */ |
mbed_official | 146:f64d43ff0c18 | 4639 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4640 | #define HW_UART_WF7816_ADDR(x) (REGS_UART_BASE(x) + 0x1DU) |
mbed_official | 146:f64d43ff0c18 | 4641 | |
mbed_official | 146:f64d43ff0c18 | 4642 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4643 | #define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4644 | #define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4645 | #define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4646 | #define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4647 | #define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4648 | #define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4649 | #endif |
mbed_official | 146:f64d43ff0c18 | 4650 | //@} |
mbed_official | 146:f64d43ff0c18 | 4651 | |
mbed_official | 146:f64d43ff0c18 | 4652 | /* |
mbed_official | 146:f64d43ff0c18 | 4653 | * Constants & macros for individual UART_WF7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 4654 | */ |
mbed_official | 146:f64d43ff0c18 | 4655 | |
mbed_official | 146:f64d43ff0c18 | 4656 | /*! |
mbed_official | 146:f64d43ff0c18 | 4657 | * @name Register UART_WF7816, field GTFD[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4658 | * |
mbed_official | 146:f64d43ff0c18 | 4659 | * Used as another multiplier in the calculation of WT and BWT. This value |
mbed_official | 146:f64d43ff0c18 | 4660 | * represents a number between 1 and 255. The value of 0 is invalid. This value is not |
mbed_official | 146:f64d43ff0c18 | 4661 | * used in baud rate generation. See Wait time and guard time parameters and |
mbed_official | 146:f64d43ff0c18 | 4662 | * Baud rate generation . |
mbed_official | 146:f64d43ff0c18 | 4663 | */ |
mbed_official | 146:f64d43ff0c18 | 4664 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4665 | #define BP_UART_WF7816_GTFD (0U) //!< Bit position for UART_WF7816_GTFD. |
mbed_official | 146:f64d43ff0c18 | 4666 | #define BM_UART_WF7816_GTFD (0xFFU) //!< Bit mask for UART_WF7816_GTFD. |
mbed_official | 146:f64d43ff0c18 | 4667 | #define BS_UART_WF7816_GTFD (8U) //!< Bit field size in bits for UART_WF7816_GTFD. |
mbed_official | 146:f64d43ff0c18 | 4668 | |
mbed_official | 146:f64d43ff0c18 | 4669 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4670 | //! @brief Read current value of the UART_WF7816_GTFD field. |
mbed_official | 146:f64d43ff0c18 | 4671 | #define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4672 | #endif |
mbed_official | 146:f64d43ff0c18 | 4673 | |
mbed_official | 146:f64d43ff0c18 | 4674 | //! @brief Format value for bitfield UART_WF7816_GTFD. |
mbed_official | 146:f64d43ff0c18 | 4675 | #define BF_UART_WF7816_GTFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WF7816_GTFD), uint8_t) & BM_UART_WF7816_GTFD) |
mbed_official | 146:f64d43ff0c18 | 4676 | |
mbed_official | 146:f64d43ff0c18 | 4677 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4678 | //! @brief Set the GTFD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4679 | #define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 4680 | #endif |
mbed_official | 146:f64d43ff0c18 | 4681 | //@} |
mbed_official | 146:f64d43ff0c18 | 4682 | |
mbed_official | 146:f64d43ff0c18 | 4683 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4684 | // HW_UART_ET7816 - UART 7816 Error Threshold Register |
mbed_official | 146:f64d43ff0c18 | 4685 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4686 | |
mbed_official | 146:f64d43ff0c18 | 4687 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4688 | /*! |
mbed_official | 146:f64d43ff0c18 | 4689 | * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4690 | * |
mbed_official | 146:f64d43ff0c18 | 4691 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 4692 | * |
mbed_official | 146:f64d43ff0c18 | 4693 | * The ET7816 register contains fields that determine the number of NACKs that |
mbed_official | 146:f64d43ff0c18 | 4694 | * must be received or transmitted before the host processor is notified. This |
mbed_official | 146:f64d43ff0c18 | 4695 | * register may be read at anytime. This register must be written to only when |
mbed_official | 146:f64d43ff0c18 | 4696 | * C7816[ISO_7816E] is not set. |
mbed_official | 146:f64d43ff0c18 | 4697 | */ |
mbed_official | 146:f64d43ff0c18 | 4698 | typedef union _hw_uart_et7816 |
mbed_official | 146:f64d43ff0c18 | 4699 | { |
mbed_official | 146:f64d43ff0c18 | 4700 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4701 | struct _hw_uart_et7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 4702 | { |
mbed_official | 146:f64d43ff0c18 | 4703 | uint8_t RXTHRESHOLD : 4; //!< [3:0] Receive NACK Threshold |
mbed_official | 146:f64d43ff0c18 | 4704 | uint8_t TXTHRESHOLD : 4; //!< [7:4] Transmit NACK Threshold |
mbed_official | 146:f64d43ff0c18 | 4705 | } B; |
mbed_official | 146:f64d43ff0c18 | 4706 | } hw_uart_et7816_t; |
mbed_official | 146:f64d43ff0c18 | 4707 | #endif |
mbed_official | 146:f64d43ff0c18 | 4708 | |
mbed_official | 146:f64d43ff0c18 | 4709 | /*! |
mbed_official | 146:f64d43ff0c18 | 4710 | * @name Constants and macros for entire UART_ET7816 register |
mbed_official | 146:f64d43ff0c18 | 4711 | */ |
mbed_official | 146:f64d43ff0c18 | 4712 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4713 | #define HW_UART_ET7816_ADDR(x) (REGS_UART_BASE(x) + 0x1EU) |
mbed_official | 146:f64d43ff0c18 | 4714 | |
mbed_official | 146:f64d43ff0c18 | 4715 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4716 | #define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4717 | #define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4718 | #define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4719 | #define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4720 | #define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4721 | #define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4722 | #endif |
mbed_official | 146:f64d43ff0c18 | 4723 | //@} |
mbed_official | 146:f64d43ff0c18 | 4724 | |
mbed_official | 146:f64d43ff0c18 | 4725 | /* |
mbed_official | 146:f64d43ff0c18 | 4726 | * Constants & macros for individual UART_ET7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 4727 | */ |
mbed_official | 146:f64d43ff0c18 | 4728 | |
mbed_official | 146:f64d43ff0c18 | 4729 | /*! |
mbed_official | 146:f64d43ff0c18 | 4730 | * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4731 | * |
mbed_official | 146:f64d43ff0c18 | 4732 | * The value written to this field indicates the maximum number of consecutive |
mbed_official | 146:f64d43ff0c18 | 4733 | * NACKs generated as a result of a parity error or receiver buffer overruns |
mbed_official | 146:f64d43ff0c18 | 4734 | * before the host processor is notified. After the counter exceeds that value in the |
mbed_official | 146:f64d43ff0c18 | 4735 | * field, the IS7816[RXT] is asserted. This field is meaningful only when |
mbed_official | 146:f64d43ff0c18 | 4736 | * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive |
mbed_official | 146:f64d43ff0c18 | 4737 | * NACKs that have been transmitted since the last successful reception. This |
mbed_official | 146:f64d43ff0c18 | 4738 | * counter saturates at 4'hF and does not wrap around. Regardless of the number of |
mbed_official | 146:f64d43ff0c18 | 4739 | * NACKs sent, the UART continues to receive valid packets indefinitely. For |
mbed_official | 146:f64d43ff0c18 | 4740 | * additional information, see IS7816[RXT] field description. |
mbed_official | 146:f64d43ff0c18 | 4741 | */ |
mbed_official | 146:f64d43ff0c18 | 4742 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4743 | #define BP_UART_ET7816_RXTHRESHOLD (0U) //!< Bit position for UART_ET7816_RXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4744 | #define BM_UART_ET7816_RXTHRESHOLD (0x0FU) //!< Bit mask for UART_ET7816_RXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4745 | #define BS_UART_ET7816_RXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4746 | |
mbed_official | 146:f64d43ff0c18 | 4747 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4748 | //! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. |
mbed_official | 146:f64d43ff0c18 | 4749 | #define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD) |
mbed_official | 146:f64d43ff0c18 | 4750 | #endif |
mbed_official | 146:f64d43ff0c18 | 4751 | |
mbed_official | 146:f64d43ff0c18 | 4752 | //! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4753 | #define BF_UART_ET7816_RXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_RXTHRESHOLD), uint8_t) & BM_UART_ET7816_RXTHRESHOLD) |
mbed_official | 146:f64d43ff0c18 | 4754 | |
mbed_official | 146:f64d43ff0c18 | 4755 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4756 | //! @brief Set the RXTHRESHOLD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4757 | #define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v))) |
mbed_official | 146:f64d43ff0c18 | 4758 | #endif |
mbed_official | 146:f64d43ff0c18 | 4759 | //@} |
mbed_official | 146:f64d43ff0c18 | 4760 | |
mbed_official | 146:f64d43ff0c18 | 4761 | /*! |
mbed_official | 146:f64d43ff0c18 | 4762 | * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 4763 | * |
mbed_official | 146:f64d43ff0c18 | 4764 | * The value written to this field indicates the maximum number of failed |
mbed_official | 146:f64d43ff0c18 | 4765 | * attempts (NACKs) a transmitted character can have before the host processor is |
mbed_official | 146:f64d43ff0c18 | 4766 | * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1. |
mbed_official | 146:f64d43ff0c18 | 4767 | * The value read from this field represents the number of consecutive NACKs |
mbed_official | 146:f64d43ff0c18 | 4768 | * that have been received since the last successful transmission. This counter |
mbed_official | 146:f64d43ff0c18 | 4769 | * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are |
mbed_official | 146:f64d43ff0c18 | 4770 | * received, the UART continues to retransmit indefinitely. This flag only |
mbed_official | 146:f64d43ff0c18 | 4771 | * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field |
mbed_official | 146:f64d43ff0c18 | 4772 | * description. |
mbed_official | 146:f64d43ff0c18 | 4773 | * |
mbed_official | 146:f64d43ff0c18 | 4774 | * Values: |
mbed_official | 146:f64d43ff0c18 | 4775 | * - 0 - TXT asserts on the first NACK that is received. |
mbed_official | 146:f64d43ff0c18 | 4776 | * - 1 - TXT asserts on the second NACK that is received. |
mbed_official | 146:f64d43ff0c18 | 4777 | */ |
mbed_official | 146:f64d43ff0c18 | 4778 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4779 | #define BP_UART_ET7816_TXTHRESHOLD (4U) //!< Bit position for UART_ET7816_TXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4780 | #define BM_UART_ET7816_TXTHRESHOLD (0xF0U) //!< Bit mask for UART_ET7816_TXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4781 | #define BS_UART_ET7816_TXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4782 | |
mbed_official | 146:f64d43ff0c18 | 4783 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4784 | //! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. |
mbed_official | 146:f64d43ff0c18 | 4785 | #define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD) |
mbed_official | 146:f64d43ff0c18 | 4786 | #endif |
mbed_official | 146:f64d43ff0c18 | 4787 | |
mbed_official | 146:f64d43ff0c18 | 4788 | //! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. |
mbed_official | 146:f64d43ff0c18 | 4789 | #define BF_UART_ET7816_TXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_TXTHRESHOLD), uint8_t) & BM_UART_ET7816_TXTHRESHOLD) |
mbed_official | 146:f64d43ff0c18 | 4790 | |
mbed_official | 146:f64d43ff0c18 | 4791 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4792 | //! @brief Set the TXTHRESHOLD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4793 | #define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v))) |
mbed_official | 146:f64d43ff0c18 | 4794 | #endif |
mbed_official | 146:f64d43ff0c18 | 4795 | //@} |
mbed_official | 146:f64d43ff0c18 | 4796 | |
mbed_official | 146:f64d43ff0c18 | 4797 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4798 | // HW_UART_TL7816 - UART 7816 Transmit Length Register |
mbed_official | 146:f64d43ff0c18 | 4799 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4800 | |
mbed_official | 146:f64d43ff0c18 | 4801 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4802 | /*! |
mbed_official | 146:f64d43ff0c18 | 4803 | * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW) |
mbed_official | 146:f64d43ff0c18 | 4804 | * |
mbed_official | 146:f64d43ff0c18 | 4805 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 4806 | * |
mbed_official | 146:f64d43ff0c18 | 4807 | * The TL7816 register is used to indicate the number of characters contained in |
mbed_official | 146:f64d43ff0c18 | 4808 | * the block being transmitted. This register is used only when C7816[TTYPE] = |
mbed_official | 146:f64d43ff0c18 | 4809 | * 1. This register may be read at anytime. This register must be written only |
mbed_official | 146:f64d43ff0c18 | 4810 | * when C2[TE] is not enabled. |
mbed_official | 146:f64d43ff0c18 | 4811 | */ |
mbed_official | 146:f64d43ff0c18 | 4812 | typedef union _hw_uart_tl7816 |
mbed_official | 146:f64d43ff0c18 | 4813 | { |
mbed_official | 146:f64d43ff0c18 | 4814 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 4815 | struct _hw_uart_tl7816_bitfields |
mbed_official | 146:f64d43ff0c18 | 4816 | { |
mbed_official | 146:f64d43ff0c18 | 4817 | uint8_t TLEN : 8; //!< [7:0] Transmit Length |
mbed_official | 146:f64d43ff0c18 | 4818 | } B; |
mbed_official | 146:f64d43ff0c18 | 4819 | } hw_uart_tl7816_t; |
mbed_official | 146:f64d43ff0c18 | 4820 | #endif |
mbed_official | 146:f64d43ff0c18 | 4821 | |
mbed_official | 146:f64d43ff0c18 | 4822 | /*! |
mbed_official | 146:f64d43ff0c18 | 4823 | * @name Constants and macros for entire UART_TL7816 register |
mbed_official | 146:f64d43ff0c18 | 4824 | */ |
mbed_official | 146:f64d43ff0c18 | 4825 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4826 | #define HW_UART_TL7816_ADDR(x) (REGS_UART_BASE(x) + 0x1FU) |
mbed_official | 146:f64d43ff0c18 | 4827 | |
mbed_official | 146:f64d43ff0c18 | 4828 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4829 | #define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 4830 | #define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4831 | #define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 4832 | #define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 4833 | #define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 4834 | #define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 4835 | #endif |
mbed_official | 146:f64d43ff0c18 | 4836 | //@} |
mbed_official | 146:f64d43ff0c18 | 4837 | |
mbed_official | 146:f64d43ff0c18 | 4838 | /* |
mbed_official | 146:f64d43ff0c18 | 4839 | * Constants & macros for individual UART_TL7816 bitfields |
mbed_official | 146:f64d43ff0c18 | 4840 | */ |
mbed_official | 146:f64d43ff0c18 | 4841 | |
mbed_official | 146:f64d43ff0c18 | 4842 | /*! |
mbed_official | 146:f64d43ff0c18 | 4843 | * @name Register UART_TL7816, field TLEN[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 4844 | * |
mbed_official | 146:f64d43ff0c18 | 4845 | * This value plus four indicates the number of characters contained in the |
mbed_official | 146:f64d43ff0c18 | 4846 | * block being transmitted. This register is automatically decremented by 1 for each |
mbed_official | 146:f64d43ff0c18 | 4847 | * character in the information field portion of the block. Additionally, this |
mbed_official | 146:f64d43ff0c18 | 4848 | * register is automatically decremented by 1 for the first character of a CRC in |
mbed_official | 146:f64d43ff0c18 | 4849 | * the epilogue field. Therefore, this register must be programmed with the number |
mbed_official | 146:f64d43ff0c18 | 4850 | * of bytes in the data packet if an LRC is being transmitted, and the number of |
mbed_official | 146:f64d43ff0c18 | 4851 | * bytes + 1 if a CRC is being transmitted. This register is not decremented for |
mbed_official | 146:f64d43ff0c18 | 4852 | * characters that are assumed to be part of the Prologue field, that is, the |
mbed_official | 146:f64d43ff0c18 | 4853 | * first three characters transmitted in a block, or the LRC or last CRC character |
mbed_official | 146:f64d43ff0c18 | 4854 | * in the Epilogue field, that is, the last character transmitted. This field |
mbed_official | 146:f64d43ff0c18 | 4855 | * must be programed or adjusted only when C2[TE] is cleared. |
mbed_official | 146:f64d43ff0c18 | 4856 | */ |
mbed_official | 146:f64d43ff0c18 | 4857 | //@{ |
mbed_official | 146:f64d43ff0c18 | 4858 | #define BP_UART_TL7816_TLEN (0U) //!< Bit position for UART_TL7816_TLEN. |
mbed_official | 146:f64d43ff0c18 | 4859 | #define BM_UART_TL7816_TLEN (0xFFU) //!< Bit mask for UART_TL7816_TLEN. |
mbed_official | 146:f64d43ff0c18 | 4860 | #define BS_UART_TL7816_TLEN (8U) //!< Bit field size in bits for UART_TL7816_TLEN. |
mbed_official | 146:f64d43ff0c18 | 4861 | |
mbed_official | 146:f64d43ff0c18 | 4862 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4863 | //! @brief Read current value of the UART_TL7816_TLEN field. |
mbed_official | 146:f64d43ff0c18 | 4864 | #define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U) |
mbed_official | 146:f64d43ff0c18 | 4865 | #endif |
mbed_official | 146:f64d43ff0c18 | 4866 | |
mbed_official | 146:f64d43ff0c18 | 4867 | //! @brief Format value for bitfield UART_TL7816_TLEN. |
mbed_official | 146:f64d43ff0c18 | 4868 | #define BF_UART_TL7816_TLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TL7816_TLEN), uint8_t) & BM_UART_TL7816_TLEN) |
mbed_official | 146:f64d43ff0c18 | 4869 | |
mbed_official | 146:f64d43ff0c18 | 4870 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4871 | //! @brief Set the TLEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 4872 | #define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v)) |
mbed_official | 146:f64d43ff0c18 | 4873 | #endif |
mbed_official | 146:f64d43ff0c18 | 4874 | //@} |
mbed_official | 146:f64d43ff0c18 | 4875 | |
mbed_official | 146:f64d43ff0c18 | 4876 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4877 | // hw_uart_t - module struct |
mbed_official | 146:f64d43ff0c18 | 4878 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 4879 | /*! |
mbed_official | 146:f64d43ff0c18 | 4880 | * @brief All UART module registers. |
mbed_official | 146:f64d43ff0c18 | 4881 | */ |
mbed_official | 146:f64d43ff0c18 | 4882 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 4883 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 4884 | typedef struct _hw_uart |
mbed_official | 146:f64d43ff0c18 | 4885 | { |
mbed_official | 146:f64d43ff0c18 | 4886 | __IO hw_uart_bdh_t BDH; //!< [0x0] UART Baud Rate Registers: High |
mbed_official | 146:f64d43ff0c18 | 4887 | __IO hw_uart_bdl_t BDL; //!< [0x1] UART Baud Rate Registers: Low |
mbed_official | 146:f64d43ff0c18 | 4888 | __IO hw_uart_c1_t C1; //!< [0x2] UART Control Register 1 |
mbed_official | 146:f64d43ff0c18 | 4889 | __IO hw_uart_c2_t C2; //!< [0x3] UART Control Register 2 |
mbed_official | 146:f64d43ff0c18 | 4890 | __I hw_uart_s1_t S1; //!< [0x4] UART Status Register 1 |
mbed_official | 146:f64d43ff0c18 | 4891 | __IO hw_uart_s2_t S2; //!< [0x5] UART Status Register 2 |
mbed_official | 146:f64d43ff0c18 | 4892 | __IO hw_uart_c3_t C3; //!< [0x6] UART Control Register 3 |
mbed_official | 146:f64d43ff0c18 | 4893 | __IO hw_uart_d_t D; //!< [0x7] UART Data Register |
mbed_official | 146:f64d43ff0c18 | 4894 | __IO hw_uart_ma1_t MA1; //!< [0x8] UART Match Address Registers 1 |
mbed_official | 146:f64d43ff0c18 | 4895 | __IO hw_uart_ma2_t MA2; //!< [0x9] UART Match Address Registers 2 |
mbed_official | 146:f64d43ff0c18 | 4896 | __IO hw_uart_c4_t C4; //!< [0xA] UART Control Register 4 |
mbed_official | 146:f64d43ff0c18 | 4897 | __IO hw_uart_c5_t C5; //!< [0xB] UART Control Register 5 |
mbed_official | 146:f64d43ff0c18 | 4898 | __I hw_uart_ed_t ED; //!< [0xC] UART Extended Data Register |
mbed_official | 146:f64d43ff0c18 | 4899 | __IO hw_uart_modem_t MODEM; //!< [0xD] UART Modem Register |
mbed_official | 146:f64d43ff0c18 | 4900 | __IO hw_uart_ir_t IR; //!< [0xE] UART Infrared Register |
mbed_official | 146:f64d43ff0c18 | 4901 | uint8_t _reserved0[1]; |
mbed_official | 146:f64d43ff0c18 | 4902 | __IO hw_uart_pfifo_t PFIFO; //!< [0x10] UART FIFO Parameters |
mbed_official | 146:f64d43ff0c18 | 4903 | __IO hw_uart_cfifo_t CFIFO; //!< [0x11] UART FIFO Control Register |
mbed_official | 146:f64d43ff0c18 | 4904 | __IO hw_uart_sfifo_t SFIFO; //!< [0x12] UART FIFO Status Register |
mbed_official | 146:f64d43ff0c18 | 4905 | __IO hw_uart_twfifo_t TWFIFO; //!< [0x13] UART FIFO Transmit Watermark |
mbed_official | 146:f64d43ff0c18 | 4906 | __I hw_uart_tcfifo_t TCFIFO; //!< [0x14] UART FIFO Transmit Count |
mbed_official | 146:f64d43ff0c18 | 4907 | __IO hw_uart_rwfifo_t RWFIFO; //!< [0x15] UART FIFO Receive Watermark |
mbed_official | 146:f64d43ff0c18 | 4908 | __I hw_uart_rcfifo_t RCFIFO; //!< [0x16] UART FIFO Receive Count |
mbed_official | 146:f64d43ff0c18 | 4909 | uint8_t _reserved1[1]; |
mbed_official | 146:f64d43ff0c18 | 4910 | __IO hw_uart_c7816_t C7816; //!< [0x18] UART 7816 Control Register |
mbed_official | 146:f64d43ff0c18 | 4911 | __IO hw_uart_ie7816_t IE7816; //!< [0x19] UART 7816 Interrupt Enable Register |
mbed_official | 146:f64d43ff0c18 | 4912 | __IO hw_uart_is7816_t IS7816; //!< [0x1A] UART 7816 Interrupt Status Register |
mbed_official | 146:f64d43ff0c18 | 4913 | union { |
mbed_official | 146:f64d43ff0c18 | 4914 | __IO hw_uart_wp7816_t_type0_t WP7816_T_TYPE0; //!< [0x1B] UART 7816 Wait Parameter Register |
mbed_official | 146:f64d43ff0c18 | 4915 | __IO hw_uart_wp7816_t_type1_t WP7816_T_TYPE1; //!< [0x1B] UART 7816 Wait Parameter Register |
mbed_official | 146:f64d43ff0c18 | 4916 | }; |
mbed_official | 146:f64d43ff0c18 | 4917 | __IO hw_uart_wn7816_t WN7816; //!< [0x1C] UART 7816 Wait N Register |
mbed_official | 146:f64d43ff0c18 | 4918 | __IO hw_uart_wf7816_t WF7816; //!< [0x1D] UART 7816 Wait FD Register |
mbed_official | 146:f64d43ff0c18 | 4919 | __IO hw_uart_et7816_t ET7816; //!< [0x1E] UART 7816 Error Threshold Register |
mbed_official | 146:f64d43ff0c18 | 4920 | __IO hw_uart_tl7816_t TL7816; //!< [0x1F] UART 7816 Transmit Length Register |
mbed_official | 146:f64d43ff0c18 | 4921 | } hw_uart_t; |
mbed_official | 146:f64d43ff0c18 | 4922 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 4923 | |
mbed_official | 146:f64d43ff0c18 | 4924 | //! @brief Macro to access all UART registers. |
mbed_official | 146:f64d43ff0c18 | 4925 | //! @param x UART instance number. |
mbed_official | 146:f64d43ff0c18 | 4926 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 4927 | //! use the '&' operator, like <code>&HW_UART(0)</code>. |
mbed_official | 146:f64d43ff0c18 | 4928 | #define HW_UART(x) (*(hw_uart_t *) REGS_UART_BASE(x)) |
mbed_official | 146:f64d43ff0c18 | 4929 | #endif |
mbed_official | 146:f64d43ff0c18 | 4930 | |
mbed_official | 146:f64d43ff0c18 | 4931 | #endif // __HW_UART_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 4932 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 4933 | // EOF |