mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pmc.h@146:f64d43ff0c18, 2014-04-02 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Apr 02 21:00:08 2014 +0100
- Revision:
- 146:f64d43ff0c18
Synchronized with git revision d537c51d26da35e031d537f7fc90380fc74cb207
Full URL: https://github.com/mbedmicro/mbed/commit/d537c51d26da35e031d537f7fc90380fc74cb207/
target K64F
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_PMC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_PMC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 PMC |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Power Management Controller |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_PMC_REGSC - Regulator Status And Control register |
mbed_official | 146:f64d43ff0c18 | 35 | * |
mbed_official | 146:f64d43ff0c18 | 36 | * - hw_pmc_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 37 | */ |
mbed_official | 146:f64d43ff0c18 | 38 | |
mbed_official | 146:f64d43ff0c18 | 39 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 40 | //@{ |
mbed_official | 146:f64d43ff0c18 | 41 | #ifndef REGS_PMC_BASE |
mbed_official | 146:f64d43ff0c18 | 42 | #define HW_PMC_INSTANCE_COUNT (1U) //!< Number of instances of the PMC module. |
mbed_official | 146:f64d43ff0c18 | 43 | #define REGS_PMC_BASE (0x4007D000U) //!< Base address for PMC. |
mbed_official | 146:f64d43ff0c18 | 44 | #endif |
mbed_official | 146:f64d43ff0c18 | 45 | //@} |
mbed_official | 146:f64d43ff0c18 | 46 | |
mbed_official | 146:f64d43ff0c18 | 47 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 48 | // HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register |
mbed_official | 146:f64d43ff0c18 | 49 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 50 | |
mbed_official | 146:f64d43ff0c18 | 51 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 52 | /*! |
mbed_official | 146:f64d43ff0c18 | 53 | * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW) |
mbed_official | 146:f64d43ff0c18 | 54 | * |
mbed_official | 146:f64d43ff0c18 | 55 | * Reset value: 0x10U |
mbed_official | 146:f64d43ff0c18 | 56 | * |
mbed_official | 146:f64d43ff0c18 | 57 | * This register contains status and control bits to support the low voltage |
mbed_official | 146:f64d43ff0c18 | 58 | * detect function. This register should be written during the reset initialization |
mbed_official | 146:f64d43ff0c18 | 59 | * program to set the desired controls even if the desired settings are the same |
mbed_official | 146:f64d43ff0c18 | 60 | * as the reset settings. While the device is in the very low power or low |
mbed_official | 146:f64d43ff0c18 | 61 | * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect |
mbed_official | 146:f64d43ff0c18 | 62 | * systems that must have LVD always on, configure the Power Mode Protection |
mbed_official | 146:f64d43ff0c18 | 63 | * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or |
mbed_official | 146:f64d43ff0c18 | 64 | * low leakage modes from being enabled. See the device's data sheet for the |
mbed_official | 146:f64d43ff0c18 | 65 | * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The |
mbed_official | 146:f64d43ff0c18 | 66 | * register's other bits are reset on Chip Reset Not VLLS. For more information |
mbed_official | 146:f64d43ff0c18 | 67 | * about these reset types, refer to the Reset section details. |
mbed_official | 146:f64d43ff0c18 | 68 | */ |
mbed_official | 146:f64d43ff0c18 | 69 | typedef union _hw_pmc_lvdsc1 |
mbed_official | 146:f64d43ff0c18 | 70 | { |
mbed_official | 146:f64d43ff0c18 | 71 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 72 | struct _hw_pmc_lvdsc1_bitfields |
mbed_official | 146:f64d43ff0c18 | 73 | { |
mbed_official | 146:f64d43ff0c18 | 74 | uint8_t LVDV : 2; //!< [1:0] Low-Voltage Detect Voltage Select |
mbed_official | 146:f64d43ff0c18 | 75 | uint8_t RESERVED0 : 2; //!< [3:2] |
mbed_official | 146:f64d43ff0c18 | 76 | uint8_t LVDRE : 1; //!< [4] Low-Voltage Detect Reset Enable |
mbed_official | 146:f64d43ff0c18 | 77 | uint8_t LVDIE : 1; //!< [5] Low-Voltage Detect Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 78 | uint8_t LVDACK : 1; //!< [6] Low-Voltage Detect Acknowledge |
mbed_official | 146:f64d43ff0c18 | 79 | uint8_t LVDF : 1; //!< [7] Low-Voltage Detect Flag |
mbed_official | 146:f64d43ff0c18 | 80 | } B; |
mbed_official | 146:f64d43ff0c18 | 81 | } hw_pmc_lvdsc1_t; |
mbed_official | 146:f64d43ff0c18 | 82 | #endif |
mbed_official | 146:f64d43ff0c18 | 83 | |
mbed_official | 146:f64d43ff0c18 | 84 | /*! |
mbed_official | 146:f64d43ff0c18 | 85 | * @name Constants and macros for entire PMC_LVDSC1 register |
mbed_official | 146:f64d43ff0c18 | 86 | */ |
mbed_official | 146:f64d43ff0c18 | 87 | //@{ |
mbed_official | 146:f64d43ff0c18 | 88 | #define HW_PMC_LVDSC1_ADDR (REGS_PMC_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 89 | |
mbed_official | 146:f64d43ff0c18 | 90 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 91 | #define HW_PMC_LVDSC1 (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR) |
mbed_official | 146:f64d43ff0c18 | 92 | #define HW_PMC_LVDSC1_RD() (HW_PMC_LVDSC1.U) |
mbed_official | 146:f64d43ff0c18 | 93 | #define HW_PMC_LVDSC1_WR(v) (HW_PMC_LVDSC1.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 94 | #define HW_PMC_LVDSC1_SET(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 95 | #define HW_PMC_LVDSC1_CLR(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 96 | #define HW_PMC_LVDSC1_TOG(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 97 | #endif |
mbed_official | 146:f64d43ff0c18 | 98 | //@} |
mbed_official | 146:f64d43ff0c18 | 99 | |
mbed_official | 146:f64d43ff0c18 | 100 | /* |
mbed_official | 146:f64d43ff0c18 | 101 | * Constants & macros for individual PMC_LVDSC1 bitfields |
mbed_official | 146:f64d43ff0c18 | 102 | */ |
mbed_official | 146:f64d43ff0c18 | 103 | |
mbed_official | 146:f64d43ff0c18 | 104 | /*! |
mbed_official | 146:f64d43ff0c18 | 105 | * @name Register PMC_LVDSC1, field LVDV[1:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 106 | * |
mbed_official | 146:f64d43ff0c18 | 107 | * Selects the LVD trip point voltage (V LVD ). |
mbed_official | 146:f64d43ff0c18 | 108 | * |
mbed_official | 146:f64d43ff0c18 | 109 | * Values: |
mbed_official | 146:f64d43ff0c18 | 110 | * - 00 - Low trip point selected (V LVD = V LVDL ) |
mbed_official | 146:f64d43ff0c18 | 111 | * - 01 - High trip point selected (V LVD = V LVDH ) |
mbed_official | 146:f64d43ff0c18 | 112 | * - 10 - Reserved |
mbed_official | 146:f64d43ff0c18 | 113 | * - 11 - Reserved |
mbed_official | 146:f64d43ff0c18 | 114 | */ |
mbed_official | 146:f64d43ff0c18 | 115 | //@{ |
mbed_official | 146:f64d43ff0c18 | 116 | #define BP_PMC_LVDSC1_LVDV (0U) //!< Bit position for PMC_LVDSC1_LVDV. |
mbed_official | 146:f64d43ff0c18 | 117 | #define BM_PMC_LVDSC1_LVDV (0x03U) //!< Bit mask for PMC_LVDSC1_LVDV. |
mbed_official | 146:f64d43ff0c18 | 118 | #define BS_PMC_LVDSC1_LVDV (2U) //!< Bit field size in bits for PMC_LVDSC1_LVDV. |
mbed_official | 146:f64d43ff0c18 | 119 | |
mbed_official | 146:f64d43ff0c18 | 120 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 121 | //! @brief Read current value of the PMC_LVDSC1_LVDV field. |
mbed_official | 146:f64d43ff0c18 | 122 | #define BR_PMC_LVDSC1_LVDV (HW_PMC_LVDSC1.B.LVDV) |
mbed_official | 146:f64d43ff0c18 | 123 | #endif |
mbed_official | 146:f64d43ff0c18 | 124 | |
mbed_official | 146:f64d43ff0c18 | 125 | //! @brief Format value for bitfield PMC_LVDSC1_LVDV. |
mbed_official | 146:f64d43ff0c18 | 126 | #define BF_PMC_LVDSC1_LVDV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDV), uint8_t) & BM_PMC_LVDSC1_LVDV) |
mbed_official | 146:f64d43ff0c18 | 127 | |
mbed_official | 146:f64d43ff0c18 | 128 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 129 | //! @brief Set the LVDV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 130 | #define BW_PMC_LVDSC1_LVDV(v) (HW_PMC_LVDSC1_WR((HW_PMC_LVDSC1_RD() & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v))) |
mbed_official | 146:f64d43ff0c18 | 131 | #endif |
mbed_official | 146:f64d43ff0c18 | 132 | //@} |
mbed_official | 146:f64d43ff0c18 | 133 | |
mbed_official | 146:f64d43ff0c18 | 134 | /*! |
mbed_official | 146:f64d43ff0c18 | 135 | * @name Register PMC_LVDSC1, field LVDRE[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 136 | * |
mbed_official | 146:f64d43ff0c18 | 137 | * This write-once bit enables LVDF events to generate a hardware reset. |
mbed_official | 146:f64d43ff0c18 | 138 | * Additional writes are ignored. |
mbed_official | 146:f64d43ff0c18 | 139 | * |
mbed_official | 146:f64d43ff0c18 | 140 | * Values: |
mbed_official | 146:f64d43ff0c18 | 141 | * - 0 - LVDF does not generate hardware resets |
mbed_official | 146:f64d43ff0c18 | 142 | * - 1 - Force an MCU reset when LVDF = 1 |
mbed_official | 146:f64d43ff0c18 | 143 | */ |
mbed_official | 146:f64d43ff0c18 | 144 | //@{ |
mbed_official | 146:f64d43ff0c18 | 145 | #define BP_PMC_LVDSC1_LVDRE (4U) //!< Bit position for PMC_LVDSC1_LVDRE. |
mbed_official | 146:f64d43ff0c18 | 146 | #define BM_PMC_LVDSC1_LVDRE (0x10U) //!< Bit mask for PMC_LVDSC1_LVDRE. |
mbed_official | 146:f64d43ff0c18 | 147 | #define BS_PMC_LVDSC1_LVDRE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDRE. |
mbed_official | 146:f64d43ff0c18 | 148 | |
mbed_official | 146:f64d43ff0c18 | 149 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 150 | //! @brief Read current value of the PMC_LVDSC1_LVDRE field. |
mbed_official | 146:f64d43ff0c18 | 151 | #define BR_PMC_LVDSC1_LVDRE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE)) |
mbed_official | 146:f64d43ff0c18 | 152 | #endif |
mbed_official | 146:f64d43ff0c18 | 153 | |
mbed_official | 146:f64d43ff0c18 | 154 | //! @brief Format value for bitfield PMC_LVDSC1_LVDRE. |
mbed_official | 146:f64d43ff0c18 | 155 | #define BF_PMC_LVDSC1_LVDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDRE), uint8_t) & BM_PMC_LVDSC1_LVDRE) |
mbed_official | 146:f64d43ff0c18 | 156 | |
mbed_official | 146:f64d43ff0c18 | 157 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 158 | //! @brief Set the LVDRE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 159 | #define BW_PMC_LVDSC1_LVDRE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 160 | #endif |
mbed_official | 146:f64d43ff0c18 | 161 | //@} |
mbed_official | 146:f64d43ff0c18 | 162 | |
mbed_official | 146:f64d43ff0c18 | 163 | /*! |
mbed_official | 146:f64d43ff0c18 | 164 | * @name Register PMC_LVDSC1, field LVDIE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 165 | * |
mbed_official | 146:f64d43ff0c18 | 166 | * Enables hardware interrupt requests for LVDF. |
mbed_official | 146:f64d43ff0c18 | 167 | * |
mbed_official | 146:f64d43ff0c18 | 168 | * Values: |
mbed_official | 146:f64d43ff0c18 | 169 | * - 0 - Hardware interrupt disabled (use polling) |
mbed_official | 146:f64d43ff0c18 | 170 | * - 1 - Request a hardware interrupt when LVDF = 1 |
mbed_official | 146:f64d43ff0c18 | 171 | */ |
mbed_official | 146:f64d43ff0c18 | 172 | //@{ |
mbed_official | 146:f64d43ff0c18 | 173 | #define BP_PMC_LVDSC1_LVDIE (5U) //!< Bit position for PMC_LVDSC1_LVDIE. |
mbed_official | 146:f64d43ff0c18 | 174 | #define BM_PMC_LVDSC1_LVDIE (0x20U) //!< Bit mask for PMC_LVDSC1_LVDIE. |
mbed_official | 146:f64d43ff0c18 | 175 | #define BS_PMC_LVDSC1_LVDIE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDIE. |
mbed_official | 146:f64d43ff0c18 | 176 | |
mbed_official | 146:f64d43ff0c18 | 177 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 178 | //! @brief Read current value of the PMC_LVDSC1_LVDIE field. |
mbed_official | 146:f64d43ff0c18 | 179 | #define BR_PMC_LVDSC1_LVDIE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE)) |
mbed_official | 146:f64d43ff0c18 | 180 | #endif |
mbed_official | 146:f64d43ff0c18 | 181 | |
mbed_official | 146:f64d43ff0c18 | 182 | //! @brief Format value for bitfield PMC_LVDSC1_LVDIE. |
mbed_official | 146:f64d43ff0c18 | 183 | #define BF_PMC_LVDSC1_LVDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDIE), uint8_t) & BM_PMC_LVDSC1_LVDIE) |
mbed_official | 146:f64d43ff0c18 | 184 | |
mbed_official | 146:f64d43ff0c18 | 185 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 186 | //! @brief Set the LVDIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 187 | #define BW_PMC_LVDSC1_LVDIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 188 | #endif |
mbed_official | 146:f64d43ff0c18 | 189 | //@} |
mbed_official | 146:f64d43ff0c18 | 190 | |
mbed_official | 146:f64d43ff0c18 | 191 | /*! |
mbed_official | 146:f64d43ff0c18 | 192 | * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 193 | * |
mbed_official | 146:f64d43ff0c18 | 194 | * This write-only field is used to acknowledge low voltage detection errors. |
mbed_official | 146:f64d43ff0c18 | 195 | * Write 1 to clear LVDF. Reads always return 0. |
mbed_official | 146:f64d43ff0c18 | 196 | */ |
mbed_official | 146:f64d43ff0c18 | 197 | //@{ |
mbed_official | 146:f64d43ff0c18 | 198 | #define BP_PMC_LVDSC1_LVDACK (6U) //!< Bit position for PMC_LVDSC1_LVDACK. |
mbed_official | 146:f64d43ff0c18 | 199 | #define BM_PMC_LVDSC1_LVDACK (0x40U) //!< Bit mask for PMC_LVDSC1_LVDACK. |
mbed_official | 146:f64d43ff0c18 | 200 | #define BS_PMC_LVDSC1_LVDACK (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDACK. |
mbed_official | 146:f64d43ff0c18 | 201 | |
mbed_official | 146:f64d43ff0c18 | 202 | //! @brief Format value for bitfield PMC_LVDSC1_LVDACK. |
mbed_official | 146:f64d43ff0c18 | 203 | #define BF_PMC_LVDSC1_LVDACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDACK), uint8_t) & BM_PMC_LVDSC1_LVDACK) |
mbed_official | 146:f64d43ff0c18 | 204 | |
mbed_official | 146:f64d43ff0c18 | 205 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 206 | //! @brief Set the LVDACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 207 | #define BW_PMC_LVDSC1_LVDACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDACK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 208 | #endif |
mbed_official | 146:f64d43ff0c18 | 209 | //@} |
mbed_official | 146:f64d43ff0c18 | 210 | |
mbed_official | 146:f64d43ff0c18 | 211 | /*! |
mbed_official | 146:f64d43ff0c18 | 212 | * @name Register PMC_LVDSC1, field LVDF[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 213 | * |
mbed_official | 146:f64d43ff0c18 | 214 | * This read-only status field indicates a low-voltage detect event. |
mbed_official | 146:f64d43ff0c18 | 215 | * |
mbed_official | 146:f64d43ff0c18 | 216 | * Values: |
mbed_official | 146:f64d43ff0c18 | 217 | * - 0 - Low-voltage event not detected |
mbed_official | 146:f64d43ff0c18 | 218 | * - 1 - Low-voltage event detected |
mbed_official | 146:f64d43ff0c18 | 219 | */ |
mbed_official | 146:f64d43ff0c18 | 220 | //@{ |
mbed_official | 146:f64d43ff0c18 | 221 | #define BP_PMC_LVDSC1_LVDF (7U) //!< Bit position for PMC_LVDSC1_LVDF. |
mbed_official | 146:f64d43ff0c18 | 222 | #define BM_PMC_LVDSC1_LVDF (0x80U) //!< Bit mask for PMC_LVDSC1_LVDF. |
mbed_official | 146:f64d43ff0c18 | 223 | #define BS_PMC_LVDSC1_LVDF (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDF. |
mbed_official | 146:f64d43ff0c18 | 224 | |
mbed_official | 146:f64d43ff0c18 | 225 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 226 | //! @brief Read current value of the PMC_LVDSC1_LVDF field. |
mbed_official | 146:f64d43ff0c18 | 227 | #define BR_PMC_LVDSC1_LVDF (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDF)) |
mbed_official | 146:f64d43ff0c18 | 228 | #endif |
mbed_official | 146:f64d43ff0c18 | 229 | //@} |
mbed_official | 146:f64d43ff0c18 | 230 | |
mbed_official | 146:f64d43ff0c18 | 231 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 232 | // HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register |
mbed_official | 146:f64d43ff0c18 | 233 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 234 | |
mbed_official | 146:f64d43ff0c18 | 235 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 236 | /*! |
mbed_official | 146:f64d43ff0c18 | 237 | * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW) |
mbed_official | 146:f64d43ff0c18 | 238 | * |
mbed_official | 146:f64d43ff0c18 | 239 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 240 | * |
mbed_official | 146:f64d43ff0c18 | 241 | * This register contains status and control bits to support the low voltage |
mbed_official | 146:f64d43ff0c18 | 242 | * warning function. While the device is in the very low power or low leakage modes, |
mbed_official | 146:f64d43ff0c18 | 243 | * the LVD system is disabled regardless of LVDSC2 settings. See the device's |
mbed_official | 146:f64d43ff0c18 | 244 | * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV |
mbed_official | 146:f64d43ff0c18 | 245 | * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the |
mbed_official | 146:f64d43ff0c18 | 246 | * register are reset on Chip Reset Not VLLS. For more information about these |
mbed_official | 146:f64d43ff0c18 | 247 | * reset types, refer to the Reset section details. |
mbed_official | 146:f64d43ff0c18 | 248 | */ |
mbed_official | 146:f64d43ff0c18 | 249 | typedef union _hw_pmc_lvdsc2 |
mbed_official | 146:f64d43ff0c18 | 250 | { |
mbed_official | 146:f64d43ff0c18 | 251 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 252 | struct _hw_pmc_lvdsc2_bitfields |
mbed_official | 146:f64d43ff0c18 | 253 | { |
mbed_official | 146:f64d43ff0c18 | 254 | uint8_t LVWV : 2; //!< [1:0] Low-Voltage Warning Voltage Select |
mbed_official | 146:f64d43ff0c18 | 255 | uint8_t RESERVED0 : 3; //!< [4:2] |
mbed_official | 146:f64d43ff0c18 | 256 | uint8_t LVWIE : 1; //!< [5] Low-Voltage Warning Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 257 | uint8_t LVWACK : 1; //!< [6] Low-Voltage Warning Acknowledge |
mbed_official | 146:f64d43ff0c18 | 258 | uint8_t LVWF : 1; //!< [7] Low-Voltage Warning Flag |
mbed_official | 146:f64d43ff0c18 | 259 | } B; |
mbed_official | 146:f64d43ff0c18 | 260 | } hw_pmc_lvdsc2_t; |
mbed_official | 146:f64d43ff0c18 | 261 | #endif |
mbed_official | 146:f64d43ff0c18 | 262 | |
mbed_official | 146:f64d43ff0c18 | 263 | /*! |
mbed_official | 146:f64d43ff0c18 | 264 | * @name Constants and macros for entire PMC_LVDSC2 register |
mbed_official | 146:f64d43ff0c18 | 265 | */ |
mbed_official | 146:f64d43ff0c18 | 266 | //@{ |
mbed_official | 146:f64d43ff0c18 | 267 | #define HW_PMC_LVDSC2_ADDR (REGS_PMC_BASE + 0x1U) |
mbed_official | 146:f64d43ff0c18 | 268 | |
mbed_official | 146:f64d43ff0c18 | 269 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 270 | #define HW_PMC_LVDSC2 (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR) |
mbed_official | 146:f64d43ff0c18 | 271 | #define HW_PMC_LVDSC2_RD() (HW_PMC_LVDSC2.U) |
mbed_official | 146:f64d43ff0c18 | 272 | #define HW_PMC_LVDSC2_WR(v) (HW_PMC_LVDSC2.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 273 | #define HW_PMC_LVDSC2_SET(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 274 | #define HW_PMC_LVDSC2_CLR(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 275 | #define HW_PMC_LVDSC2_TOG(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 276 | #endif |
mbed_official | 146:f64d43ff0c18 | 277 | //@} |
mbed_official | 146:f64d43ff0c18 | 278 | |
mbed_official | 146:f64d43ff0c18 | 279 | /* |
mbed_official | 146:f64d43ff0c18 | 280 | * Constants & macros for individual PMC_LVDSC2 bitfields |
mbed_official | 146:f64d43ff0c18 | 281 | */ |
mbed_official | 146:f64d43ff0c18 | 282 | |
mbed_official | 146:f64d43ff0c18 | 283 | /*! |
mbed_official | 146:f64d43ff0c18 | 284 | * @name Register PMC_LVDSC2, field LVWV[1:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 285 | * |
mbed_official | 146:f64d43ff0c18 | 286 | * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning |
mbed_official | 146:f64d43ff0c18 | 287 | * depends on LVDSC1[LVDV]. |
mbed_official | 146:f64d43ff0c18 | 288 | * |
mbed_official | 146:f64d43ff0c18 | 289 | * Values: |
mbed_official | 146:f64d43ff0c18 | 290 | * - 00 - Low trip point selected (VLVW = VLVW1) |
mbed_official | 146:f64d43ff0c18 | 291 | * - 01 - Mid 1 trip point selected (VLVW = VLVW2) |
mbed_official | 146:f64d43ff0c18 | 292 | * - 10 - Mid 2 trip point selected (VLVW = VLVW3) |
mbed_official | 146:f64d43ff0c18 | 293 | * - 11 - High trip point selected (VLVW = VLVW4) |
mbed_official | 146:f64d43ff0c18 | 294 | */ |
mbed_official | 146:f64d43ff0c18 | 295 | //@{ |
mbed_official | 146:f64d43ff0c18 | 296 | #define BP_PMC_LVDSC2_LVWV (0U) //!< Bit position for PMC_LVDSC2_LVWV. |
mbed_official | 146:f64d43ff0c18 | 297 | #define BM_PMC_LVDSC2_LVWV (0x03U) //!< Bit mask for PMC_LVDSC2_LVWV. |
mbed_official | 146:f64d43ff0c18 | 298 | #define BS_PMC_LVDSC2_LVWV (2U) //!< Bit field size in bits for PMC_LVDSC2_LVWV. |
mbed_official | 146:f64d43ff0c18 | 299 | |
mbed_official | 146:f64d43ff0c18 | 300 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 301 | //! @brief Read current value of the PMC_LVDSC2_LVWV field. |
mbed_official | 146:f64d43ff0c18 | 302 | #define BR_PMC_LVDSC2_LVWV (HW_PMC_LVDSC2.B.LVWV) |
mbed_official | 146:f64d43ff0c18 | 303 | #endif |
mbed_official | 146:f64d43ff0c18 | 304 | |
mbed_official | 146:f64d43ff0c18 | 305 | //! @brief Format value for bitfield PMC_LVDSC2_LVWV. |
mbed_official | 146:f64d43ff0c18 | 306 | #define BF_PMC_LVDSC2_LVWV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWV), uint8_t) & BM_PMC_LVDSC2_LVWV) |
mbed_official | 146:f64d43ff0c18 | 307 | |
mbed_official | 146:f64d43ff0c18 | 308 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 309 | //! @brief Set the LVWV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 310 | #define BW_PMC_LVDSC2_LVWV(v) (HW_PMC_LVDSC2_WR((HW_PMC_LVDSC2_RD() & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v))) |
mbed_official | 146:f64d43ff0c18 | 311 | #endif |
mbed_official | 146:f64d43ff0c18 | 312 | //@} |
mbed_official | 146:f64d43ff0c18 | 313 | |
mbed_official | 146:f64d43ff0c18 | 314 | /*! |
mbed_official | 146:f64d43ff0c18 | 315 | * @name Register PMC_LVDSC2, field LVWIE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 316 | * |
mbed_official | 146:f64d43ff0c18 | 317 | * Enables hardware interrupt requests for LVWF. |
mbed_official | 146:f64d43ff0c18 | 318 | * |
mbed_official | 146:f64d43ff0c18 | 319 | * Values: |
mbed_official | 146:f64d43ff0c18 | 320 | * - 0 - Hardware interrupt disabled (use polling) |
mbed_official | 146:f64d43ff0c18 | 321 | * - 1 - Request a hardware interrupt when LVWF = 1 |
mbed_official | 146:f64d43ff0c18 | 322 | */ |
mbed_official | 146:f64d43ff0c18 | 323 | //@{ |
mbed_official | 146:f64d43ff0c18 | 324 | #define BP_PMC_LVDSC2_LVWIE (5U) //!< Bit position for PMC_LVDSC2_LVWIE. |
mbed_official | 146:f64d43ff0c18 | 325 | #define BM_PMC_LVDSC2_LVWIE (0x20U) //!< Bit mask for PMC_LVDSC2_LVWIE. |
mbed_official | 146:f64d43ff0c18 | 326 | #define BS_PMC_LVDSC2_LVWIE (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWIE. |
mbed_official | 146:f64d43ff0c18 | 327 | |
mbed_official | 146:f64d43ff0c18 | 328 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 329 | //! @brief Read current value of the PMC_LVDSC2_LVWIE field. |
mbed_official | 146:f64d43ff0c18 | 330 | #define BR_PMC_LVDSC2_LVWIE (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE)) |
mbed_official | 146:f64d43ff0c18 | 331 | #endif |
mbed_official | 146:f64d43ff0c18 | 332 | |
mbed_official | 146:f64d43ff0c18 | 333 | //! @brief Format value for bitfield PMC_LVDSC2_LVWIE. |
mbed_official | 146:f64d43ff0c18 | 334 | #define BF_PMC_LVDSC2_LVWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWIE), uint8_t) & BM_PMC_LVDSC2_LVWIE) |
mbed_official | 146:f64d43ff0c18 | 335 | |
mbed_official | 146:f64d43ff0c18 | 336 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 337 | //! @brief Set the LVWIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 338 | #define BW_PMC_LVDSC2_LVWIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 339 | #endif |
mbed_official | 146:f64d43ff0c18 | 340 | //@} |
mbed_official | 146:f64d43ff0c18 | 341 | |
mbed_official | 146:f64d43ff0c18 | 342 | /*! |
mbed_official | 146:f64d43ff0c18 | 343 | * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 344 | * |
mbed_official | 146:f64d43ff0c18 | 345 | * This write-only field is used to acknowledge low voltage warning errors. |
mbed_official | 146:f64d43ff0c18 | 346 | * Write 1 to clear LVWF. Reads always return 0. |
mbed_official | 146:f64d43ff0c18 | 347 | */ |
mbed_official | 146:f64d43ff0c18 | 348 | //@{ |
mbed_official | 146:f64d43ff0c18 | 349 | #define BP_PMC_LVDSC2_LVWACK (6U) //!< Bit position for PMC_LVDSC2_LVWACK. |
mbed_official | 146:f64d43ff0c18 | 350 | #define BM_PMC_LVDSC2_LVWACK (0x40U) //!< Bit mask for PMC_LVDSC2_LVWACK. |
mbed_official | 146:f64d43ff0c18 | 351 | #define BS_PMC_LVDSC2_LVWACK (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWACK. |
mbed_official | 146:f64d43ff0c18 | 352 | |
mbed_official | 146:f64d43ff0c18 | 353 | //! @brief Format value for bitfield PMC_LVDSC2_LVWACK. |
mbed_official | 146:f64d43ff0c18 | 354 | #define BF_PMC_LVDSC2_LVWACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWACK), uint8_t) & BM_PMC_LVDSC2_LVWACK) |
mbed_official | 146:f64d43ff0c18 | 355 | |
mbed_official | 146:f64d43ff0c18 | 356 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 357 | //! @brief Set the LVWACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 358 | #define BW_PMC_LVDSC2_LVWACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWACK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 359 | #endif |
mbed_official | 146:f64d43ff0c18 | 360 | //@} |
mbed_official | 146:f64d43ff0c18 | 361 | |
mbed_official | 146:f64d43ff0c18 | 362 | /*! |
mbed_official | 146:f64d43ff0c18 | 363 | * @name Register PMC_LVDSC2, field LVWF[7] (RO) |
mbed_official | 146:f64d43ff0c18 | 364 | * |
mbed_official | 146:f64d43ff0c18 | 365 | * This read-only status field indicates a low-voltage warning event. LVWF is |
mbed_official | 146:f64d43ff0c18 | 366 | * set when VSupply transitions below the trip point, or after reset and VSupply is |
mbed_official | 146:f64d43ff0c18 | 367 | * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW |
mbed_official | 146:f64d43ff0c18 | 368 | * interrupt function, before enabling LVWIE, LVWF must be cleared by writing |
mbed_official | 146:f64d43ff0c18 | 369 | * LVWACK first. |
mbed_official | 146:f64d43ff0c18 | 370 | * |
mbed_official | 146:f64d43ff0c18 | 371 | * Values: |
mbed_official | 146:f64d43ff0c18 | 372 | * - 0 - Low-voltage warning event not detected |
mbed_official | 146:f64d43ff0c18 | 373 | * - 1 - Low-voltage warning event detected |
mbed_official | 146:f64d43ff0c18 | 374 | */ |
mbed_official | 146:f64d43ff0c18 | 375 | //@{ |
mbed_official | 146:f64d43ff0c18 | 376 | #define BP_PMC_LVDSC2_LVWF (7U) //!< Bit position for PMC_LVDSC2_LVWF. |
mbed_official | 146:f64d43ff0c18 | 377 | #define BM_PMC_LVDSC2_LVWF (0x80U) //!< Bit mask for PMC_LVDSC2_LVWF. |
mbed_official | 146:f64d43ff0c18 | 378 | #define BS_PMC_LVDSC2_LVWF (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWF. |
mbed_official | 146:f64d43ff0c18 | 379 | |
mbed_official | 146:f64d43ff0c18 | 380 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 381 | //! @brief Read current value of the PMC_LVDSC2_LVWF field. |
mbed_official | 146:f64d43ff0c18 | 382 | #define BR_PMC_LVDSC2_LVWF (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWF)) |
mbed_official | 146:f64d43ff0c18 | 383 | #endif |
mbed_official | 146:f64d43ff0c18 | 384 | //@} |
mbed_official | 146:f64d43ff0c18 | 385 | |
mbed_official | 146:f64d43ff0c18 | 386 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 387 | // HW_PMC_REGSC - Regulator Status And Control register |
mbed_official | 146:f64d43ff0c18 | 388 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 389 | |
mbed_official | 146:f64d43ff0c18 | 390 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 391 | /*! |
mbed_official | 146:f64d43ff0c18 | 392 | * @brief HW_PMC_REGSC - Regulator Status And Control register (RW) |
mbed_official | 146:f64d43ff0c18 | 393 | * |
mbed_official | 146:f64d43ff0c18 | 394 | * Reset value: 0x04U |
mbed_official | 146:f64d43ff0c18 | 395 | * |
mbed_official | 146:f64d43ff0c18 | 396 | * The PMC contains an internal voltage regulator. The voltage regulator design |
mbed_official | 146:f64d43ff0c18 | 397 | * uses a bandgap reference that is also available through a buffer as input to |
mbed_official | 146:f64d43ff0c18 | 398 | * certain internal peripherals, such as the CMP and ADC. The internal regulator |
mbed_official | 146:f64d43ff0c18 | 399 | * provides a status bit (REGONS) indicating the regulator is in run regulation. |
mbed_official | 146:f64d43ff0c18 | 400 | * This register is reset on Chip Reset Not VLLS and by reset types that trigger |
mbed_official | 146:f64d43ff0c18 | 401 | * Chip Reset not VLLS. See the Reset section details for more information. |
mbed_official | 146:f64d43ff0c18 | 402 | */ |
mbed_official | 146:f64d43ff0c18 | 403 | typedef union _hw_pmc_regsc |
mbed_official | 146:f64d43ff0c18 | 404 | { |
mbed_official | 146:f64d43ff0c18 | 405 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 406 | struct _hw_pmc_regsc_bitfields |
mbed_official | 146:f64d43ff0c18 | 407 | { |
mbed_official | 146:f64d43ff0c18 | 408 | uint8_t BGBE : 1; //!< [0] Bandgap Buffer Enable |
mbed_official | 146:f64d43ff0c18 | 409 | uint8_t RESERVED0 : 1; //!< [1] |
mbed_official | 146:f64d43ff0c18 | 410 | uint8_t REGONS : 1; //!< [2] Regulator In Run Regulation Status |
mbed_official | 146:f64d43ff0c18 | 411 | uint8_t ACKISO : 1; //!< [3] Acknowledge Isolation |
mbed_official | 146:f64d43ff0c18 | 412 | uint8_t BGEN : 1; //!< [4] Bandgap Enable In VLPx Operation |
mbed_official | 146:f64d43ff0c18 | 413 | uint8_t RESERVED1 : 3; //!< [7:5] |
mbed_official | 146:f64d43ff0c18 | 414 | } B; |
mbed_official | 146:f64d43ff0c18 | 415 | } hw_pmc_regsc_t; |
mbed_official | 146:f64d43ff0c18 | 416 | #endif |
mbed_official | 146:f64d43ff0c18 | 417 | |
mbed_official | 146:f64d43ff0c18 | 418 | /*! |
mbed_official | 146:f64d43ff0c18 | 419 | * @name Constants and macros for entire PMC_REGSC register |
mbed_official | 146:f64d43ff0c18 | 420 | */ |
mbed_official | 146:f64d43ff0c18 | 421 | //@{ |
mbed_official | 146:f64d43ff0c18 | 422 | #define HW_PMC_REGSC_ADDR (REGS_PMC_BASE + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 423 | |
mbed_official | 146:f64d43ff0c18 | 424 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 425 | #define HW_PMC_REGSC (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR) |
mbed_official | 146:f64d43ff0c18 | 426 | #define HW_PMC_REGSC_RD() (HW_PMC_REGSC.U) |
mbed_official | 146:f64d43ff0c18 | 427 | #define HW_PMC_REGSC_WR(v) (HW_PMC_REGSC.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 428 | #define HW_PMC_REGSC_SET(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 429 | #define HW_PMC_REGSC_CLR(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 430 | #define HW_PMC_REGSC_TOG(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 431 | #endif |
mbed_official | 146:f64d43ff0c18 | 432 | //@} |
mbed_official | 146:f64d43ff0c18 | 433 | |
mbed_official | 146:f64d43ff0c18 | 434 | /* |
mbed_official | 146:f64d43ff0c18 | 435 | * Constants & macros for individual PMC_REGSC bitfields |
mbed_official | 146:f64d43ff0c18 | 436 | */ |
mbed_official | 146:f64d43ff0c18 | 437 | |
mbed_official | 146:f64d43ff0c18 | 438 | /*! |
mbed_official | 146:f64d43ff0c18 | 439 | * @name Register PMC_REGSC, field BGBE[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 440 | * |
mbed_official | 146:f64d43ff0c18 | 441 | * Enables the bandgap buffer. |
mbed_official | 146:f64d43ff0c18 | 442 | * |
mbed_official | 146:f64d43ff0c18 | 443 | * Values: |
mbed_official | 146:f64d43ff0c18 | 444 | * - 0 - Bandgap buffer not enabled |
mbed_official | 146:f64d43ff0c18 | 445 | * - 1 - Bandgap buffer enabled |
mbed_official | 146:f64d43ff0c18 | 446 | */ |
mbed_official | 146:f64d43ff0c18 | 447 | //@{ |
mbed_official | 146:f64d43ff0c18 | 448 | #define BP_PMC_REGSC_BGBE (0U) //!< Bit position for PMC_REGSC_BGBE. |
mbed_official | 146:f64d43ff0c18 | 449 | #define BM_PMC_REGSC_BGBE (0x01U) //!< Bit mask for PMC_REGSC_BGBE. |
mbed_official | 146:f64d43ff0c18 | 450 | #define BS_PMC_REGSC_BGBE (1U) //!< Bit field size in bits for PMC_REGSC_BGBE. |
mbed_official | 146:f64d43ff0c18 | 451 | |
mbed_official | 146:f64d43ff0c18 | 452 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 453 | //! @brief Read current value of the PMC_REGSC_BGBE field. |
mbed_official | 146:f64d43ff0c18 | 454 | #define BR_PMC_REGSC_BGBE (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE)) |
mbed_official | 146:f64d43ff0c18 | 455 | #endif |
mbed_official | 146:f64d43ff0c18 | 456 | |
mbed_official | 146:f64d43ff0c18 | 457 | //! @brief Format value for bitfield PMC_REGSC_BGBE. |
mbed_official | 146:f64d43ff0c18 | 458 | #define BF_PMC_REGSC_BGBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGBE), uint8_t) & BM_PMC_REGSC_BGBE) |
mbed_official | 146:f64d43ff0c18 | 459 | |
mbed_official | 146:f64d43ff0c18 | 460 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 461 | //! @brief Set the BGBE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 462 | #define BW_PMC_REGSC_BGBE(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 463 | #endif |
mbed_official | 146:f64d43ff0c18 | 464 | //@} |
mbed_official | 146:f64d43ff0c18 | 465 | |
mbed_official | 146:f64d43ff0c18 | 466 | /*! |
mbed_official | 146:f64d43ff0c18 | 467 | * @name Register PMC_REGSC, field REGONS[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 468 | * |
mbed_official | 146:f64d43ff0c18 | 469 | * This read-only field provides the current status of the internal voltage |
mbed_official | 146:f64d43ff0c18 | 470 | * regulator. |
mbed_official | 146:f64d43ff0c18 | 471 | * |
mbed_official | 146:f64d43ff0c18 | 472 | * Values: |
mbed_official | 146:f64d43ff0c18 | 473 | * - 0 - Regulator is in stop regulation or in transition to/from it |
mbed_official | 146:f64d43ff0c18 | 474 | * - 1 - Regulator is in run regulation |
mbed_official | 146:f64d43ff0c18 | 475 | */ |
mbed_official | 146:f64d43ff0c18 | 476 | //@{ |
mbed_official | 146:f64d43ff0c18 | 477 | #define BP_PMC_REGSC_REGONS (2U) //!< Bit position for PMC_REGSC_REGONS. |
mbed_official | 146:f64d43ff0c18 | 478 | #define BM_PMC_REGSC_REGONS (0x04U) //!< Bit mask for PMC_REGSC_REGONS. |
mbed_official | 146:f64d43ff0c18 | 479 | #define BS_PMC_REGSC_REGONS (1U) //!< Bit field size in bits for PMC_REGSC_REGONS. |
mbed_official | 146:f64d43ff0c18 | 480 | |
mbed_official | 146:f64d43ff0c18 | 481 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 482 | //! @brief Read current value of the PMC_REGSC_REGONS field. |
mbed_official | 146:f64d43ff0c18 | 483 | #define BR_PMC_REGSC_REGONS (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_REGONS)) |
mbed_official | 146:f64d43ff0c18 | 484 | #endif |
mbed_official | 146:f64d43ff0c18 | 485 | //@} |
mbed_official | 146:f64d43ff0c18 | 486 | |
mbed_official | 146:f64d43ff0c18 | 487 | /*! |
mbed_official | 146:f64d43ff0c18 | 488 | * @name Register PMC_REGSC, field ACKISO[3] (W1C) |
mbed_official | 146:f64d43ff0c18 | 489 | * |
mbed_official | 146:f64d43ff0c18 | 490 | * Reading this field indicates whether certain peripherals and the I/O pads are |
mbed_official | 146:f64d43ff0c18 | 491 | * in a latched state as a result of having been in a VLLS mode. Writing 1 to |
mbed_official | 146:f64d43ff0c18 | 492 | * this field when it is set releases the I/O pads and certain peripherals to their |
mbed_official | 146:f64d43ff0c18 | 493 | * normal run mode state. After recovering from a VLLS mode, user should restore |
mbed_official | 146:f64d43ff0c18 | 494 | * chip configuration before clearing ACKISO. In particular, pin configuration |
mbed_official | 146:f64d43ff0c18 | 495 | * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from |
mbed_official | 146:f64d43ff0c18 | 496 | * being falsely set when ACKISO is cleared. |
mbed_official | 146:f64d43ff0c18 | 497 | * |
mbed_official | 146:f64d43ff0c18 | 498 | * Values: |
mbed_official | 146:f64d43ff0c18 | 499 | * - 0 - Peripherals and I/O pads are in normal run state. |
mbed_official | 146:f64d43ff0c18 | 500 | * - 1 - Certain peripherals and I/O pads are in an isolated and latched state. |
mbed_official | 146:f64d43ff0c18 | 501 | */ |
mbed_official | 146:f64d43ff0c18 | 502 | //@{ |
mbed_official | 146:f64d43ff0c18 | 503 | #define BP_PMC_REGSC_ACKISO (3U) //!< Bit position for PMC_REGSC_ACKISO. |
mbed_official | 146:f64d43ff0c18 | 504 | #define BM_PMC_REGSC_ACKISO (0x08U) //!< Bit mask for PMC_REGSC_ACKISO. |
mbed_official | 146:f64d43ff0c18 | 505 | #define BS_PMC_REGSC_ACKISO (1U) //!< Bit field size in bits for PMC_REGSC_ACKISO. |
mbed_official | 146:f64d43ff0c18 | 506 | |
mbed_official | 146:f64d43ff0c18 | 507 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 508 | //! @brief Read current value of the PMC_REGSC_ACKISO field. |
mbed_official | 146:f64d43ff0c18 | 509 | #define BR_PMC_REGSC_ACKISO (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO)) |
mbed_official | 146:f64d43ff0c18 | 510 | #endif |
mbed_official | 146:f64d43ff0c18 | 511 | |
mbed_official | 146:f64d43ff0c18 | 512 | //! @brief Format value for bitfield PMC_REGSC_ACKISO. |
mbed_official | 146:f64d43ff0c18 | 513 | #define BF_PMC_REGSC_ACKISO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_ACKISO), uint8_t) & BM_PMC_REGSC_ACKISO) |
mbed_official | 146:f64d43ff0c18 | 514 | |
mbed_official | 146:f64d43ff0c18 | 515 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 516 | //! @brief Set the ACKISO field to a new value. |
mbed_official | 146:f64d43ff0c18 | 517 | #define BW_PMC_REGSC_ACKISO(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO) = (v)) |
mbed_official | 146:f64d43ff0c18 | 518 | #endif |
mbed_official | 146:f64d43ff0c18 | 519 | //@} |
mbed_official | 146:f64d43ff0c18 | 520 | |
mbed_official | 146:f64d43ff0c18 | 521 | /*! |
mbed_official | 146:f64d43ff0c18 | 522 | * @name Register PMC_REGSC, field BGEN[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 523 | * |
mbed_official | 146:f64d43ff0c18 | 524 | * BGEN controls whether the bandgap is enabled in lower power modes of |
mbed_official | 146:f64d43ff0c18 | 525 | * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage |
mbed_official | 146:f64d43ff0c18 | 526 | * reference in low power modes of operation, set BGEN to continue to enable the |
mbed_official | 146:f64d43ff0c18 | 527 | * bandgap operation. When the bandgap voltage reference is not needed in low |
mbed_official | 146:f64d43ff0c18 | 528 | * power modes, clear BGEN to avoid excess power consumption. |
mbed_official | 146:f64d43ff0c18 | 529 | * |
mbed_official | 146:f64d43ff0c18 | 530 | * Values: |
mbed_official | 146:f64d43ff0c18 | 531 | * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. |
mbed_official | 146:f64d43ff0c18 | 532 | * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. |
mbed_official | 146:f64d43ff0c18 | 533 | */ |
mbed_official | 146:f64d43ff0c18 | 534 | //@{ |
mbed_official | 146:f64d43ff0c18 | 535 | #define BP_PMC_REGSC_BGEN (4U) //!< Bit position for PMC_REGSC_BGEN. |
mbed_official | 146:f64d43ff0c18 | 536 | #define BM_PMC_REGSC_BGEN (0x10U) //!< Bit mask for PMC_REGSC_BGEN. |
mbed_official | 146:f64d43ff0c18 | 537 | #define BS_PMC_REGSC_BGEN (1U) //!< Bit field size in bits for PMC_REGSC_BGEN. |
mbed_official | 146:f64d43ff0c18 | 538 | |
mbed_official | 146:f64d43ff0c18 | 539 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 540 | //! @brief Read current value of the PMC_REGSC_BGEN field. |
mbed_official | 146:f64d43ff0c18 | 541 | #define BR_PMC_REGSC_BGEN (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN)) |
mbed_official | 146:f64d43ff0c18 | 542 | #endif |
mbed_official | 146:f64d43ff0c18 | 543 | |
mbed_official | 146:f64d43ff0c18 | 544 | //! @brief Format value for bitfield PMC_REGSC_BGEN. |
mbed_official | 146:f64d43ff0c18 | 545 | #define BF_PMC_REGSC_BGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGEN), uint8_t) & BM_PMC_REGSC_BGEN) |
mbed_official | 146:f64d43ff0c18 | 546 | |
mbed_official | 146:f64d43ff0c18 | 547 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 548 | //! @brief Set the BGEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 549 | #define BW_PMC_REGSC_BGEN(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 550 | #endif |
mbed_official | 146:f64d43ff0c18 | 551 | //@} |
mbed_official | 146:f64d43ff0c18 | 552 | |
mbed_official | 146:f64d43ff0c18 | 553 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 554 | // hw_pmc_t - module struct |
mbed_official | 146:f64d43ff0c18 | 555 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 556 | /*! |
mbed_official | 146:f64d43ff0c18 | 557 | * @brief All PMC module registers. |
mbed_official | 146:f64d43ff0c18 | 558 | */ |
mbed_official | 146:f64d43ff0c18 | 559 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 560 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 561 | typedef struct _hw_pmc |
mbed_official | 146:f64d43ff0c18 | 562 | { |
mbed_official | 146:f64d43ff0c18 | 563 | __IO hw_pmc_lvdsc1_t LVDSC1; //!< [0x0] Low Voltage Detect Status And Control 1 register |
mbed_official | 146:f64d43ff0c18 | 564 | __IO hw_pmc_lvdsc2_t LVDSC2; //!< [0x1] Low Voltage Detect Status And Control 2 register |
mbed_official | 146:f64d43ff0c18 | 565 | __IO hw_pmc_regsc_t REGSC; //!< [0x2] Regulator Status And Control register |
mbed_official | 146:f64d43ff0c18 | 566 | } hw_pmc_t; |
mbed_official | 146:f64d43ff0c18 | 567 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 568 | |
mbed_official | 146:f64d43ff0c18 | 569 | //! @brief Macro to access all PMC registers. |
mbed_official | 146:f64d43ff0c18 | 570 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 571 | //! use the '&' operator, like <code>&HW_PMC</code>. |
mbed_official | 146:f64d43ff0c18 | 572 | #define HW_PMC (*(hw_pmc_t *) REGS_PMC_BASE) |
mbed_official | 146:f64d43ff0c18 | 573 | #endif |
mbed_official | 146:f64d43ff0c18 | 574 | |
mbed_official | 146:f64d43ff0c18 | 575 | #endif // __HW_PMC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 576 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 577 | // EOF |