shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/stm32f3xx_hal_spi.c@237:f3da66175598, 2014-06-24 (annotated)

Committer:
mbed_official
Date:
Tue Jun 24 14:45:08 2014 +0100
Revision:
237:f3da66175598
Synchronized with git revision 8ef659bca81f12dfc896b5a7af7c2abbd1a1b8b7



Full URL: https://github.com/mbedmicro/mbed/commit/8ef659bca81f12dfc896b5a7af7c2abbd1a1b8b7/



[NUCLEO_F334R8] Add platform files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 237:f3da66175598 1 /**
mbed_official 237:f3da66175598 2 ******************************************************************************
mbed_official 237:f3da66175598 3 * @file stm32f3xx_hal_spi.c
mbed_official 237:f3da66175598 4 * @author MCD Application Team
mbed_official 237:f3da66175598 5 * @version V1.0.1
mbed_official 237:f3da66175598 6 * @date 18-June-2014
mbed_official 237:f3da66175598 7 * @brief SPI HAL module driver.
mbed_official 237:f3da66175598 8 *
mbed_official 237:f3da66175598 9 * This file provides firmware functions to manage the following
mbed_official 237:f3da66175598 10 * functionalities of the SPI peripheral:
mbed_official 237:f3da66175598 11 * + Initialization/de-initialization functions
mbed_official 237:f3da66175598 12 * + I/O operation functions
mbed_official 237:f3da66175598 13 * + Peripheral Control functions
mbed_official 237:f3da66175598 14 * + Peripheral State functions
mbed_official 237:f3da66175598 15 *
mbed_official 237:f3da66175598 16 @verbatim
mbed_official 237:f3da66175598 17 ===============================================================================
mbed_official 237:f3da66175598 18 ##### How to use this driver #####
mbed_official 237:f3da66175598 19 ===============================================================================
mbed_official 237:f3da66175598 20 [..]
mbed_official 237:f3da66175598 21 The SPI HAL driver can be used as follows:
mbed_official 237:f3da66175598 22
mbed_official 237:f3da66175598 23 (#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official 237:f3da66175598 24 SPI_HandleTypeDef hspi;
mbed_official 237:f3da66175598 25
mbed_official 237:f3da66175598 26 (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official 237:f3da66175598 27 (##) Enable the SPIx interface clock
mbed_official 237:f3da66175598 28 (##) SPI pins configuration
mbed_official 237:f3da66175598 29 (+) Enable the clock for the SPI GPIOs
mbed_official 237:f3da66175598 30 (+) Configure these SPI pins as alternate function push-pull
mbed_official 237:f3da66175598 31 (##) NVIC configuration if you need to use interrupt process
mbed_official 237:f3da66175598 32 (+) Configure the SPIx interrupt priority
mbed_official 237:f3da66175598 33 (+) Enable the NVIC SPI IRQ handle
mbed_official 237:f3da66175598 34 (##) DMA Configuration if you need to use DMA process
mbed_official 237:f3da66175598 35 (+) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
mbed_official 237:f3da66175598 36 (+) Enable the DMAx interface clock using
mbed_official 237:f3da66175598 37 (+) Configure the DMA handle parameters
mbed_official 237:f3da66175598 38 (+) Configure the DMA Tx or Rx channel
mbed_official 237:f3da66175598 39 (+) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official 237:f3da66175598 40 (+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
mbed_official 237:f3da66175598 41
mbed_official 237:f3da66175598 42 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
mbed_official 237:f3da66175598 43 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official 237:f3da66175598 44
mbed_official 237:f3da66175598 45 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official 237:f3da66175598 46 (+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official 237:f3da66175598 47 by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official 237:f3da66175598 48
mbed_official 237:f3da66175598 49 [..]
mbed_official 237:f3da66175598 50 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
mbed_official 237:f3da66175598 51 the following table resume the max SPI frequency reached with data size 8bits/16bits:
mbed_official 237:f3da66175598 52 +-----------------------------------------------------------------------------------------+
mbed_official 237:f3da66175598 53 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
mbed_official 237:f3da66175598 54 | Process | Tranfert mode |--------------------|--------------------|--------------------|
mbed_official 237:f3da66175598 55 | | | Master | Slave | Master | Slave | Master | Slave |
mbed_official 237:f3da66175598 56 |=========================================================================================|
mbed_official 237:f3da66175598 57 | T | Polling | Fcpu/4 | Fcpu/8 | NA | NA | NA | NA |
mbed_official 237:f3da66175598 58 | X |----------------|----------|---------|----------|---------|----------|---------|
mbed_official 237:f3da66175598 59 | / | Interrupt | Fcpu/4 | Fcpu/16 | NA | NA | NA | NA |
mbed_official 237:f3da66175598 60 | R |----------------|----------|---------|----------|---------|----------|---------|
mbed_official 237:f3da66175598 61 | X | DMA | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA |
mbed_official 237:f3da66175598 62 |=========|================|==========|=========|==========|=========|==========|=========|
mbed_official 237:f3da66175598 63 | | Polling | Fcpu/4 | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 |
mbed_official 237:f3da66175598 64 | |----------------|----------|---------|----------|---------|----------|---------|
mbed_official 237:f3da66175598 65 | R | Interrupt | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | Fcpu/4 |
mbed_official 237:f3da66175598 66 | X |----------------|----------|---------|----------|---------|----------|---------|
mbed_official 237:f3da66175598 67 | | DMA | Fcpu/4 | Fcpu/2 | Fcpu/2 | Fcpu/16 | Fcpu/2 | Fcpu/16 |
mbed_official 237:f3da66175598 68 |=========|================|==========|=========|==========|=========|==========|=========|
mbed_official 237:f3da66175598 69 | | Polling | Fcpu/8 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/8 |
mbed_official 237:f3da66175598 70 | |----------------|----------|---------|----------|---------|----------|---------|
mbed_official 237:f3da66175598 71 | T | Interrupt | Fcpu/2 | Fcpu/4 | NA | NA | Fcpu/16 | Fcpu/8 |
mbed_official 237:f3da66175598 72 | X |----------------|----------|---------|----------|---------|----------|---------|
mbed_official 237:f3da66175598 73 | | DMA | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/16 |
mbed_official 237:f3da66175598 74 +-----------------------------------------------------------------------------------------+
mbed_official 237:f3da66175598 75 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
mbed_official 237:f3da66175598 76 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
mbed_official 237:f3da66175598 77 @note
mbed_official 237:f3da66175598 78 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official 237:f3da66175598 79 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official 237:f3da66175598 80 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official 237:f3da66175598 81
mbed_official 237:f3da66175598 82 @endverbatim
mbed_official 237:f3da66175598 83 ******************************************************************************
mbed_official 237:f3da66175598 84 * @attention
mbed_official 237:f3da66175598 85 *
mbed_official 237:f3da66175598 86 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 237:f3da66175598 87 *
mbed_official 237:f3da66175598 88 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 237:f3da66175598 89 * are permitted provided that the following conditions are met:
mbed_official 237:f3da66175598 90 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 237:f3da66175598 91 * this list of conditions and the following disclaimer.
mbed_official 237:f3da66175598 92 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 237:f3da66175598 93 * this list of conditions and the following disclaimer in the documentation
mbed_official 237:f3da66175598 94 * and/or other materials provided with the distribution.
mbed_official 237:f3da66175598 95 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 237:f3da66175598 96 * may be used to endorse or promote products derived from this software
mbed_official 237:f3da66175598 97 * without specific prior written permission.
mbed_official 237:f3da66175598 98 *
mbed_official 237:f3da66175598 99 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 237:f3da66175598 100 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 237:f3da66175598 101 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 237:f3da66175598 102 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 237:f3da66175598 103 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 237:f3da66175598 104 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 237:f3da66175598 105 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 237:f3da66175598 106 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 237:f3da66175598 107 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 237:f3da66175598 108 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 237:f3da66175598 109 *
mbed_official 237:f3da66175598 110 ******************************************************************************
mbed_official 237:f3da66175598 111 */
mbed_official 237:f3da66175598 112
mbed_official 237:f3da66175598 113 /* Includes ------------------------------------------------------------------*/
mbed_official 237:f3da66175598 114 #include "stm32f3xx_hal.h"
mbed_official 237:f3da66175598 115
mbed_official 237:f3da66175598 116 /** @addtogroup STM32F3xx_HAL_Driver
mbed_official 237:f3da66175598 117 * @{
mbed_official 237:f3da66175598 118 */
mbed_official 237:f3da66175598 119
mbed_official 237:f3da66175598 120 /** @defgroup SPI
mbed_official 237:f3da66175598 121 * @brief SPI HAL module driver
mbed_official 237:f3da66175598 122 * @{
mbed_official 237:f3da66175598 123 */
mbed_official 237:f3da66175598 124 #ifdef HAL_SPI_MODULE_ENABLED
mbed_official 237:f3da66175598 125
mbed_official 237:f3da66175598 126 /* Private typedef -----------------------------------------------------------*/
mbed_official 237:f3da66175598 127 /* Private define ------------------------------------------------------------*/
mbed_official 237:f3da66175598 128 #define SPI_DEFAULT_TIMEOUT 50
mbed_official 237:f3da66175598 129 /* Private macro -------------------------------------------------------------*/
mbed_official 237:f3da66175598 130 /* Private variables ---------------------------------------------------------*/
mbed_official 237:f3da66175598 131 /* Private function prototypes -----------------------------------------------*/
mbed_official 237:f3da66175598 132 static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 237:f3da66175598 133 static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 237:f3da66175598 134 static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 237:f3da66175598 135 static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 237:f3da66175598 136 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official 237:f3da66175598 137 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official 237:f3da66175598 138 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 139 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 140 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 141 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 142 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 143 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 144 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 145 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 146 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 147 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 148 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 149 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 150 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 151 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 152 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 237:f3da66175598 153 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 237:f3da66175598 154 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 237:f3da66175598 155
mbed_official 237:f3da66175598 156 /* Private functions ---------------------------------------------------------*/
mbed_official 237:f3da66175598 157
mbed_official 237:f3da66175598 158 /** @defgroup SPI_Private_Functions
mbed_official 237:f3da66175598 159 * @{
mbed_official 237:f3da66175598 160 */
mbed_official 237:f3da66175598 161
mbed_official 237:f3da66175598 162 /** @defgroup HAL_SPI_Group1 Initialization/de-initialization functions
mbed_official 237:f3da66175598 163 * @brief Initialization and Configuration functions
mbed_official 237:f3da66175598 164 *
mbed_official 237:f3da66175598 165 @verbatim
mbed_official 237:f3da66175598 166 ===============================================================================
mbed_official 237:f3da66175598 167 ##### Initialization/de-initialization functions #####
mbed_official 237:f3da66175598 168 ===============================================================================
mbed_official 237:f3da66175598 169 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 237:f3da66175598 170 de-initialiaze the SPIx peripheral:
mbed_official 237:f3da66175598 171
mbed_official 237:f3da66175598 172 (+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official 237:f3da66175598 173 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 237:f3da66175598 174
mbed_official 237:f3da66175598 175 (+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official 237:f3da66175598 176 the selected configuration:
mbed_official 237:f3da66175598 177 (++) Mode
mbed_official 237:f3da66175598 178 (++) Direction
mbed_official 237:f3da66175598 179 (++) Data Size
mbed_official 237:f3da66175598 180 (++) Clock Polarity and Phase
mbed_official 237:f3da66175598 181 (++) NSS Management
mbed_official 237:f3da66175598 182 (++) BaudRate Prescaler
mbed_official 237:f3da66175598 183 (++) FirstBit
mbed_official 237:f3da66175598 184 (++) TIMode
mbed_official 237:f3da66175598 185 (++) CRC Calculation
mbed_official 237:f3da66175598 186 (++) CRC Polynomial if CRC enabled
mbed_official 237:f3da66175598 187 (++) CRC Length, used only with Data8 and Data16
mbed_official 237:f3da66175598 188 (++) FIFO reception threshold
mbed_official 237:f3da66175598 189
mbed_official 237:f3da66175598 190 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official 237:f3da66175598 191 of the selected SPIx periperal.
mbed_official 237:f3da66175598 192
mbed_official 237:f3da66175598 193 @endverbatim
mbed_official 237:f3da66175598 194 * @{
mbed_official 237:f3da66175598 195 */
mbed_official 237:f3da66175598 196
mbed_official 237:f3da66175598 197 /**
mbed_official 237:f3da66175598 198 * @brief Initializes the SPI according to the specified parameters
mbed_official 237:f3da66175598 199 * in the SPI_InitTypeDef and create the associated handle.
mbed_official 237:f3da66175598 200 * @param hspi: SPI handle
mbed_official 237:f3da66175598 201 * @retval HAL status
mbed_official 237:f3da66175598 202 */
mbed_official 237:f3da66175598 203 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 204 {
mbed_official 237:f3da66175598 205 uint32_t frxth;
mbed_official 237:f3da66175598 206
mbed_official 237:f3da66175598 207 /* Check the SPI handle allocation */
mbed_official 237:f3da66175598 208 if(hspi == NULL)
mbed_official 237:f3da66175598 209 {
mbed_official 237:f3da66175598 210 return HAL_ERROR;
mbed_official 237:f3da66175598 211 }
mbed_official 237:f3da66175598 212
mbed_official 237:f3da66175598 213 /* Check the parameters */
mbed_official 237:f3da66175598 214 assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official 237:f3da66175598 215 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
mbed_official 237:f3da66175598 216 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official 237:f3da66175598 217 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official 237:f3da66175598 218 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official 237:f3da66175598 219 assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official 237:f3da66175598 220 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
mbed_official 237:f3da66175598 221 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official 237:f3da66175598 222 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official 237:f3da66175598 223 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official 237:f3da66175598 224 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official 237:f3da66175598 225 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official 237:f3da66175598 226 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
mbed_official 237:f3da66175598 227
mbed_official 237:f3da66175598 228 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 237:f3da66175598 229
mbed_official 237:f3da66175598 230 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official 237:f3da66175598 231 HAL_SPI_MspInit(hspi);
mbed_official 237:f3da66175598 232
mbed_official 237:f3da66175598 233 /* Disable the selected SPI peripheral */
mbed_official 237:f3da66175598 234 __HAL_SPI_DISABLE(hspi);
mbed_official 237:f3da66175598 235
mbed_official 237:f3da66175598 236 /* Align by default the rs fifo threshold on the data size */
mbed_official 237:f3da66175598 237 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 238 {
mbed_official 237:f3da66175598 239 frxth = SPI_RXFIFO_THRESHOLD_HF;
mbed_official 237:f3da66175598 240 }
mbed_official 237:f3da66175598 241 else
mbed_official 237:f3da66175598 242 {
mbed_official 237:f3da66175598 243 frxth = SPI_RXFIFO_THRESHOLD_QF;
mbed_official 237:f3da66175598 244 }
mbed_official 237:f3da66175598 245
mbed_official 237:f3da66175598 246 /* CRC calculation is valid only for 16Bit and 8 Bit */
mbed_official 237:f3da66175598 247 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
mbed_official 237:f3da66175598 248 {
mbed_official 237:f3da66175598 249 /* CRC must be disabled */
mbed_official 237:f3da66175598 250 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
mbed_official 237:f3da66175598 251 }
mbed_official 237:f3da66175598 252
mbed_official 237:f3da66175598 253 /* Align the CRC Length on the data size */
mbed_official 237:f3da66175598 254 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
mbed_official 237:f3da66175598 255 {
mbed_official 237:f3da66175598 256 /* CRC Lengtht aligned on the data size : value set by default */
mbed_official 237:f3da66175598 257 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 258 {
mbed_official 237:f3da66175598 259 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
mbed_official 237:f3da66175598 260 }
mbed_official 237:f3da66175598 261 else
mbed_official 237:f3da66175598 262 {
mbed_official 237:f3da66175598 263 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
mbed_official 237:f3da66175598 264 }
mbed_official 237:f3da66175598 265 }
mbed_official 237:f3da66175598 266
mbed_official 237:f3da66175598 267 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
mbed_official 237:f3da66175598 268 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
mbed_official 237:f3da66175598 269 Communication speed, First bit, CRC calculation state, CRC Length */
mbed_official 237:f3da66175598 270 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
mbed_official 237:f3da66175598 271 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
mbed_official 237:f3da66175598 272 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
mbed_official 237:f3da66175598 273
mbed_official 237:f3da66175598 274 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 237:f3da66175598 275 {
mbed_official 237:f3da66175598 276 hspi->Instance->CR1|= SPI_CR1_CRCL;
mbed_official 237:f3da66175598 277 }
mbed_official 237:f3da66175598 278
mbed_official 237:f3da66175598 279 /* Configure : NSS management */
mbed_official 237:f3da66175598 280 /* Configure : Rx Fifo Threshold */
mbed_official 237:f3da66175598 281 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
mbed_official 237:f3da66175598 282 hspi->Init.DataSize ) | frxth;
mbed_official 237:f3da66175598 283
mbed_official 237:f3da66175598 284 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
mbed_official 237:f3da66175598 285 /* Configure : CRC Polynomial */
mbed_official 237:f3da66175598 286 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official 237:f3da66175598 287
mbed_official 237:f3da66175598 288 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 289 hspi->State= HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 290
mbed_official 237:f3da66175598 291 return HAL_OK;
mbed_official 237:f3da66175598 292 }
mbed_official 237:f3da66175598 293
mbed_official 237:f3da66175598 294 /**
mbed_official 237:f3da66175598 295 * @brief DeInitializes the SPI peripheral
mbed_official 237:f3da66175598 296 * @param hspi: SPI handle
mbed_official 237:f3da66175598 297 * @retval HAL status
mbed_official 237:f3da66175598 298 */
mbed_official 237:f3da66175598 299 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 300 {
mbed_official 237:f3da66175598 301 /* Check the SPI handle allocation */
mbed_official 237:f3da66175598 302 if(hspi == NULL)
mbed_official 237:f3da66175598 303 {
mbed_official 237:f3da66175598 304 return HAL_ERROR;
mbed_official 237:f3da66175598 305 }
mbed_official 237:f3da66175598 306
mbed_official 237:f3da66175598 307 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 237:f3da66175598 308
mbed_official 237:f3da66175598 309 /* Disable the SPI Peripheral Clock */
mbed_official 237:f3da66175598 310 __HAL_SPI_DISABLE(hspi);
mbed_official 237:f3da66175598 311
mbed_official 237:f3da66175598 312 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 237:f3da66175598 313 HAL_SPI_MspDeInit(hspi);
mbed_official 237:f3da66175598 314
mbed_official 237:f3da66175598 315 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 316 hspi->State = HAL_SPI_STATE_RESET;
mbed_official 237:f3da66175598 317
mbed_official 237:f3da66175598 318 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 319
mbed_official 237:f3da66175598 320 return HAL_OK;
mbed_official 237:f3da66175598 321 }
mbed_official 237:f3da66175598 322
mbed_official 237:f3da66175598 323 /**
mbed_official 237:f3da66175598 324 * @brief SPI MSP Init
mbed_official 237:f3da66175598 325 * @param hspi: SPI handle
mbed_official 237:f3da66175598 326 * @retval None
mbed_official 237:f3da66175598 327 */
mbed_official 237:f3da66175598 328 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 329 {
mbed_official 237:f3da66175598 330 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 237:f3da66175598 331 the HAL_SPI_MspInit could be implenetd in the user file
mbed_official 237:f3da66175598 332 */
mbed_official 237:f3da66175598 333 }
mbed_official 237:f3da66175598 334
mbed_official 237:f3da66175598 335 /**
mbed_official 237:f3da66175598 336 * @brief SPI MSP DeInit
mbed_official 237:f3da66175598 337 * @param hspi: SPI handle
mbed_official 237:f3da66175598 338 * @retval None
mbed_official 237:f3da66175598 339 */
mbed_official 237:f3da66175598 340 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 341 {
mbed_official 237:f3da66175598 342 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 237:f3da66175598 343 the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official 237:f3da66175598 344 */
mbed_official 237:f3da66175598 345 }
mbed_official 237:f3da66175598 346
mbed_official 237:f3da66175598 347 /**
mbed_official 237:f3da66175598 348 * @}
mbed_official 237:f3da66175598 349 */
mbed_official 237:f3da66175598 350
mbed_official 237:f3da66175598 351 /** @defgroup HAL_SPI_Group2 I/O operation functions
mbed_official 237:f3da66175598 352 * @brief Data transfers functions
mbed_official 237:f3da66175598 353 *
mbed_official 237:f3da66175598 354 @verbatim
mbed_official 237:f3da66175598 355 ===============================================================================
mbed_official 237:f3da66175598 356 ##### I/O operation functions #####
mbed_official 237:f3da66175598 357 ===============================================================================
mbed_official 237:f3da66175598 358 This subsection provides a set of functions allowing to manage the SPI
mbed_official 237:f3da66175598 359 data transfers.
mbed_official 237:f3da66175598 360
mbed_official 237:f3da66175598 361 [..] The SPI supports master and slave mode :
mbed_official 237:f3da66175598 362
mbed_official 237:f3da66175598 363 (#) There are two mode of transfer:
mbed_official 237:f3da66175598 364 (+) Blocking mode: The communication is performed in polling mode.
mbed_official 237:f3da66175598 365 The HAL status of all data processing is returned by the same function
mbed_official 237:f3da66175598 366 after finishing transfer.
mbed_official 237:f3da66175598 367 (+) No-Blocking mode: The communication is performed using Interrupts
mbed_official 237:f3da66175598 368 or DMA, These API's return the HAL status.
mbed_official 237:f3da66175598 369 The end of the data processing will be indicated through the
mbed_official 237:f3da66175598 370 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 237:f3da66175598 371 using DMA mode.
mbed_official 237:f3da66175598 372 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official 237:f3da66175598 373 will be executed respectivelly at the end of the transmit or Receive process
mbed_official 237:f3da66175598 374 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official 237:f3da66175598 375
mbed_official 237:f3da66175598 376 (#) Blocking mode API's are :
mbed_official 237:f3da66175598 377 (+) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 237:f3da66175598 378 (+) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 237:f3da66175598 379 (+) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official 237:f3da66175598 380
mbed_official 237:f3da66175598 381 (#) Non-Blocking mode API's with Interrupt are :
mbed_official 237:f3da66175598 382 (+) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 237:f3da66175598 383 (+) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 237:f3da66175598 384 (+) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official 237:f3da66175598 385 (+) HAL_SPI_IRQHandler()
mbed_official 237:f3da66175598 386
mbed_official 237:f3da66175598 387 (#) No-Blocking mode functions with DMA are :
mbed_official 237:f3da66175598 388 (+) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 237:f3da66175598 389 (+) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 237:f3da66175598 390 (+) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official 237:f3da66175598 391
mbed_official 237:f3da66175598 392 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official 237:f3da66175598 393 (+) HAL_SPI_TxCpltCallback()
mbed_official 237:f3da66175598 394 (+) HAL_SPI_RxCpltCallback()
mbed_official 237:f3da66175598 395 (+) HAL_SPI_ErrorCallback()
mbed_official 237:f3da66175598 396 (+) HAL_SPI_TxRxCpltCallback()
mbed_official 237:f3da66175598 397
mbed_official 237:f3da66175598 398 @endverbatim
mbed_official 237:f3da66175598 399 * @{
mbed_official 237:f3da66175598 400 */
mbed_official 237:f3da66175598 401
mbed_official 237:f3da66175598 402 /**
mbed_official 237:f3da66175598 403 * @brief Transmit an amount of data in blocking mode
mbed_official 237:f3da66175598 404 * @param hspi: SPI handle
mbed_official 237:f3da66175598 405 * @param pData: pointer to data buffer
mbed_official 237:f3da66175598 406 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 407 * @param Timeout: Timeout duration
mbed_official 237:f3da66175598 408 * @retval HAL status
mbed_official 237:f3da66175598 409 */
mbed_official 237:f3da66175598 410 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 237:f3da66175598 411 {
mbed_official 237:f3da66175598 412 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 237:f3da66175598 413
mbed_official 237:f3da66175598 414 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 415 {
mbed_official 237:f3da66175598 416 return HAL_BUSY;
mbed_official 237:f3da66175598 417 }
mbed_official 237:f3da66175598 418
mbed_official 237:f3da66175598 419 if((pData == NULL ) || (Size == 0))
mbed_official 237:f3da66175598 420 {
mbed_official 237:f3da66175598 421 return HAL_ERROR;
mbed_official 237:f3da66175598 422 }
mbed_official 237:f3da66175598 423
mbed_official 237:f3da66175598 424 /* Process Locked */
mbed_official 237:f3da66175598 425 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 426
mbed_official 237:f3da66175598 427 /* Set the transaction information */
mbed_official 237:f3da66175598 428 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 237:f3da66175598 429 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 430 hspi->pTxBuffPtr = pData;
mbed_official 237:f3da66175598 431 hspi->TxXferSize = Size;
mbed_official 237:f3da66175598 432 hspi->TxXferCount = Size;
mbed_official 237:f3da66175598 433 hspi->pRxBuffPtr = NULL;
mbed_official 237:f3da66175598 434 hspi->RxXferSize = 0;
mbed_official 237:f3da66175598 435 hspi->RxXferCount = 0;
mbed_official 237:f3da66175598 436
mbed_official 237:f3da66175598 437 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 438 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 439 {
mbed_official 237:f3da66175598 440 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 441 }
mbed_official 237:f3da66175598 442
mbed_official 237:f3da66175598 443 /* Configure communication direction : 1Line */
mbed_official 237:f3da66175598 444 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 237:f3da66175598 445 {
mbed_official 237:f3da66175598 446 __HAL_SPI_1LINE_TX(hspi);
mbed_official 237:f3da66175598 447 }
mbed_official 237:f3da66175598 448
mbed_official 237:f3da66175598 449 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 450 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 451 {
mbed_official 237:f3da66175598 452 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 453 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 454 }
mbed_official 237:f3da66175598 455
mbed_official 237:f3da66175598 456 /* Transmit data in 16 Bit mode */
mbed_official 237:f3da66175598 457 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 458 {
mbed_official 237:f3da66175598 459 while (hspi->TxXferCount > 0)
mbed_official 237:f3da66175598 460 {
mbed_official 237:f3da66175598 461 /* Wait until TXE flag is set to send data */
mbed_official 237:f3da66175598 462 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 237:f3da66175598 463 {
mbed_official 237:f3da66175598 464 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 465 }
mbed_official 237:f3da66175598 466 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 467 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 468 hspi->TxXferCount--;
mbed_official 237:f3da66175598 469 }
mbed_official 237:f3da66175598 470 }
mbed_official 237:f3da66175598 471 /* Transmit data in 8 Bit mode */
mbed_official 237:f3da66175598 472 else
mbed_official 237:f3da66175598 473 {
mbed_official 237:f3da66175598 474 while (hspi->TxXferCount > 0)
mbed_official 237:f3da66175598 475 {
mbed_official 237:f3da66175598 476 if(hspi->TxXferCount != 0x1)
mbed_official 237:f3da66175598 477 {
mbed_official 237:f3da66175598 478 /* Wait until TXE flag is set to send data */
mbed_official 237:f3da66175598 479 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 237:f3da66175598 480 {
mbed_official 237:f3da66175598 481 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 482 }
mbed_official 237:f3da66175598 483 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 484 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 485 hspi->TxXferCount -= 2;
mbed_official 237:f3da66175598 486 }
mbed_official 237:f3da66175598 487 else
mbed_official 237:f3da66175598 488 {
mbed_official 237:f3da66175598 489 /* Wait until TXE flag is set to send data */
mbed_official 237:f3da66175598 490 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 237:f3da66175598 491 {
mbed_official 237:f3da66175598 492 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 493 }
mbed_official 237:f3da66175598 494 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
mbed_official 237:f3da66175598 495 hspi->TxXferCount--;
mbed_official 237:f3da66175598 496 }
mbed_official 237:f3da66175598 497 }
mbed_official 237:f3da66175598 498 }
mbed_official 237:f3da66175598 499
mbed_official 237:f3da66175598 500 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 501 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 502 {
mbed_official 237:f3da66175598 503 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 504 }
mbed_official 237:f3da66175598 505
mbed_official 237:f3da66175598 506 /* Check the end of the transaction */
mbed_official 237:f3da66175598 507 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 237:f3da66175598 508 {
mbed_official 237:f3da66175598 509 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 510 }
mbed_official 237:f3da66175598 511
mbed_official 237:f3da66175598 512 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 237:f3da66175598 513 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 237:f3da66175598 514 {
mbed_official 237:f3da66175598 515 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 237:f3da66175598 516 }
mbed_official 237:f3da66175598 517
mbed_official 237:f3da66175598 518 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 519
mbed_official 237:f3da66175598 520 /* Process Unlocked */
mbed_official 237:f3da66175598 521 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 522
mbed_official 237:f3da66175598 523 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 524 {
mbed_official 237:f3da66175598 525 return HAL_ERROR;
mbed_official 237:f3da66175598 526 }
mbed_official 237:f3da66175598 527 else
mbed_official 237:f3da66175598 528 {
mbed_official 237:f3da66175598 529 return HAL_OK;
mbed_official 237:f3da66175598 530 }
mbed_official 237:f3da66175598 531 }
mbed_official 237:f3da66175598 532
mbed_official 237:f3da66175598 533 /**
mbed_official 237:f3da66175598 534 * @brief Receive an amount of data in blocking mode
mbed_official 237:f3da66175598 535 * @param hspi: SPI handle
mbed_official 237:f3da66175598 536 * @param pData: pointer to data buffer
mbed_official 237:f3da66175598 537 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 538 * @param Timeout: Timeout duration
mbed_official 237:f3da66175598 539 * @retval HAL status
mbed_official 237:f3da66175598 540 */
mbed_official 237:f3da66175598 541 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 237:f3da66175598 542 {
mbed_official 237:f3da66175598 543 __IO uint16_t tmpreg;
mbed_official 237:f3da66175598 544
mbed_official 237:f3da66175598 545 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 546 {
mbed_official 237:f3da66175598 547 return HAL_BUSY;
mbed_official 237:f3da66175598 548 }
mbed_official 237:f3da66175598 549
mbed_official 237:f3da66175598 550 if((pData == NULL ) || (Size == 0))
mbed_official 237:f3da66175598 551 {
mbed_official 237:f3da66175598 552 return HAL_ERROR;
mbed_official 237:f3da66175598 553 }
mbed_official 237:f3da66175598 554
mbed_official 237:f3da66175598 555 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 237:f3da66175598 556 {
mbed_official 237:f3da66175598 557 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 237:f3da66175598 558 /* in this case we call the transmitReceive process */
mbed_official 237:f3da66175598 559 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
mbed_official 237:f3da66175598 560 }
mbed_official 237:f3da66175598 561
mbed_official 237:f3da66175598 562 /* Process Locked */
mbed_official 237:f3da66175598 563 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 564
mbed_official 237:f3da66175598 565 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 237:f3da66175598 566 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 567 hspi->pRxBuffPtr = pData;
mbed_official 237:f3da66175598 568 hspi->RxXferSize = Size;
mbed_official 237:f3da66175598 569 hspi->RxXferCount = Size;
mbed_official 237:f3da66175598 570 hspi->pTxBuffPtr = NULL;
mbed_official 237:f3da66175598 571 hspi->TxXferSize = 0;
mbed_official 237:f3da66175598 572 hspi->TxXferCount = 0;
mbed_official 237:f3da66175598 573
mbed_official 237:f3da66175598 574 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 575 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 576 {
mbed_official 237:f3da66175598 577 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 578 }
mbed_official 237:f3da66175598 579
mbed_official 237:f3da66175598 580 /* Set the Rx Fido thresold */
mbed_official 237:f3da66175598 581 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 582 {
mbed_official 237:f3da66175598 583 /* set fiforxthresold according the reception data lenght: 16bit */
mbed_official 237:f3da66175598 584 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 585 }
mbed_official 237:f3da66175598 586 else
mbed_official 237:f3da66175598 587 {
mbed_official 237:f3da66175598 588 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 237:f3da66175598 589 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 590 }
mbed_official 237:f3da66175598 591
mbed_official 237:f3da66175598 592 /* Configure communication direction 1Line and enabled SPI if needed */
mbed_official 237:f3da66175598 593 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 237:f3da66175598 594 {
mbed_official 237:f3da66175598 595 __HAL_SPI_1LINE_RX(hspi);
mbed_official 237:f3da66175598 596 }
mbed_official 237:f3da66175598 597
mbed_official 237:f3da66175598 598 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 599 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 600 {
mbed_official 237:f3da66175598 601 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 602 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 603 }
mbed_official 237:f3da66175598 604
mbed_official 237:f3da66175598 605 /* Receive data in 8 Bit mode */
mbed_official 237:f3da66175598 606 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 607 {
mbed_official 237:f3da66175598 608 while(hspi->RxXferCount > 1)
mbed_official 237:f3da66175598 609 {
mbed_official 237:f3da66175598 610 /* Wait until the RXNE flag */
mbed_official 237:f3da66175598 611 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 612 {
mbed_official 237:f3da66175598 613 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 614 }
mbed_official 237:f3da66175598 615 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 616 hspi->RxXferCount--;
mbed_official 237:f3da66175598 617 }
mbed_official 237:f3da66175598 618 }
mbed_official 237:f3da66175598 619 else /* Receive data in 16 Bit mode */
mbed_official 237:f3da66175598 620 {
mbed_official 237:f3da66175598 621 while(hspi->RxXferCount > 1 )
mbed_official 237:f3da66175598 622 {
mbed_official 237:f3da66175598 623 /* Wait until RXNE flag is reset to read data */
mbed_official 237:f3da66175598 624 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 625 {
mbed_official 237:f3da66175598 626 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 627 }
mbed_official 237:f3da66175598 628 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 629 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 630 hspi->RxXferCount--;
mbed_official 237:f3da66175598 631 }
mbed_official 237:f3da66175598 632 }
mbed_official 237:f3da66175598 633
mbed_official 237:f3da66175598 634 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 635 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 636 {
mbed_official 237:f3da66175598 637 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 638 }
mbed_official 237:f3da66175598 639
mbed_official 237:f3da66175598 640 /* Wait until RXNE flag is set */
mbed_official 237:f3da66175598 641 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 642 {
mbed_official 237:f3da66175598 643 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 644 }
mbed_official 237:f3da66175598 645
mbed_official 237:f3da66175598 646 /* Receive last data in 16 Bit mode */
mbed_official 237:f3da66175598 647 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 648 {
mbed_official 237:f3da66175598 649 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 650 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 651 }
mbed_official 237:f3da66175598 652 /* Receive last data in 8 Bit mode */
mbed_official 237:f3da66175598 653 else
mbed_official 237:f3da66175598 654 {
mbed_official 237:f3da66175598 655 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 656 }
mbed_official 237:f3da66175598 657 hspi->RxXferCount--;
mbed_official 237:f3da66175598 658
mbed_official 237:f3da66175598 659 /* Read CRC from DR to close CRC calculation process */
mbed_official 237:f3da66175598 660 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 661 {
mbed_official 237:f3da66175598 662 /* Wait until TXE flag */
mbed_official 237:f3da66175598 663 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 664 {
mbed_official 237:f3da66175598 665 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 666 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 667 }
mbed_official 237:f3da66175598 668 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 669 {
mbed_official 237:f3da66175598 670 tmpreg = hspi->Instance->DR;
mbed_official 237:f3da66175598 671 }
mbed_official 237:f3da66175598 672 else
mbed_official 237:f3da66175598 673 {
mbed_official 237:f3da66175598 674 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 675 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 237:f3da66175598 676 {
mbed_official 237:f3da66175598 677 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 678 {
mbed_official 237:f3da66175598 679 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 680 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 681 }
mbed_official 237:f3da66175598 682 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 683 }
mbed_official 237:f3da66175598 684 }
mbed_official 237:f3da66175598 685 }
mbed_official 237:f3da66175598 686
mbed_official 237:f3da66175598 687 /* Check the end of the transaction */
mbed_official 237:f3da66175598 688 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 237:f3da66175598 689 {
mbed_official 237:f3da66175598 690 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 691 }
mbed_official 237:f3da66175598 692
mbed_official 237:f3da66175598 693 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 694
mbed_official 237:f3da66175598 695 /* Check if CRC error occurred */
mbed_official 237:f3da66175598 696 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 697 {
mbed_official 237:f3da66175598 698 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 699 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 700
mbed_official 237:f3da66175598 701 /* Process Unlocked */
mbed_official 237:f3da66175598 702 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 703 return HAL_ERROR;
mbed_official 237:f3da66175598 704 }
mbed_official 237:f3da66175598 705
mbed_official 237:f3da66175598 706 /* Process Unlocked */
mbed_official 237:f3da66175598 707 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 708
mbed_official 237:f3da66175598 709 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 710 {
mbed_official 237:f3da66175598 711 return HAL_ERROR;
mbed_official 237:f3da66175598 712 }
mbed_official 237:f3da66175598 713 else
mbed_official 237:f3da66175598 714 {
mbed_official 237:f3da66175598 715 return HAL_OK;
mbed_official 237:f3da66175598 716 }
mbed_official 237:f3da66175598 717 }
mbed_official 237:f3da66175598 718
mbed_official 237:f3da66175598 719 /**
mbed_official 237:f3da66175598 720 * @brief Transmit and Receive an amount of data in blocking mode
mbed_official 237:f3da66175598 721 * @param hspi: SPI handle
mbed_official 237:f3da66175598 722 * @param pTxData: pointer to transmission data buffer
mbed_official 237:f3da66175598 723 * @param pRxData: pointer to reception data buffer to be
mbed_official 237:f3da66175598 724 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 725 * @param Timeout: Timeout duration
mbed_official 237:f3da66175598 726 * @retval HAL status
mbed_official 237:f3da66175598 727 */
mbed_official 237:f3da66175598 728 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 237:f3da66175598 729 {
mbed_official 237:f3da66175598 730 __IO uint16_t tmpreg = 0;
mbed_official 237:f3da66175598 731 uint32_t tickstart = 0;
mbed_official 237:f3da66175598 732
mbed_official 237:f3da66175598 733 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 237:f3da66175598 734
mbed_official 237:f3da66175598 735 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 736 {
mbed_official 237:f3da66175598 737 return HAL_BUSY;
mbed_official 237:f3da66175598 738 }
mbed_official 237:f3da66175598 739
mbed_official 237:f3da66175598 740 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
mbed_official 237:f3da66175598 741 {
mbed_official 237:f3da66175598 742 return HAL_ERROR;
mbed_official 237:f3da66175598 743 }
mbed_official 237:f3da66175598 744
mbed_official 237:f3da66175598 745 tickstart = HAL_GetTick();
mbed_official 237:f3da66175598 746
mbed_official 237:f3da66175598 747 /* Process Locked */
mbed_official 237:f3da66175598 748 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 749
mbed_official 237:f3da66175598 750 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 237:f3da66175598 751 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 752 hspi->pRxBuffPtr = pRxData;
mbed_official 237:f3da66175598 753 hspi->RxXferCount = Size;
mbed_official 237:f3da66175598 754 hspi->RxXferSize = Size;
mbed_official 237:f3da66175598 755 hspi->pTxBuffPtr = pTxData;
mbed_official 237:f3da66175598 756 hspi->TxXferCount = Size;
mbed_official 237:f3da66175598 757 hspi->TxXferSize = Size;
mbed_official 237:f3da66175598 758
mbed_official 237:f3da66175598 759 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 760 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 761 {
mbed_official 237:f3da66175598 762 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 763 }
mbed_official 237:f3da66175598 764
mbed_official 237:f3da66175598 765 /* Set the Rx Fido threshold */
mbed_official 237:f3da66175598 766 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
mbed_official 237:f3da66175598 767 {
mbed_official 237:f3da66175598 768 /* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official 237:f3da66175598 769 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 770 }
mbed_official 237:f3da66175598 771 else
mbed_official 237:f3da66175598 772 {
mbed_official 237:f3da66175598 773 /* set fiforxthreshold according the reception data lenght: 8bit */
mbed_official 237:f3da66175598 774 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 775 }
mbed_official 237:f3da66175598 776
mbed_official 237:f3da66175598 777 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 778 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 779 {
mbed_official 237:f3da66175598 780 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 781 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 782 }
mbed_official 237:f3da66175598 783
mbed_official 237:f3da66175598 784 /* Transmit and Receive data in 16 Bit mode */
mbed_official 237:f3da66175598 785 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 786 {
mbed_official 237:f3da66175598 787 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
mbed_official 237:f3da66175598 788 {
mbed_official 237:f3da66175598 789 /* Wait until TXE flag */
mbed_official 237:f3da66175598 790 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 237:f3da66175598 791 {
mbed_official 237:f3da66175598 792 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 793 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 794 hspi->TxXferCount--;
mbed_official 237:f3da66175598 795
mbed_official 237:f3da66175598 796 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 797 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 237:f3da66175598 798 {
mbed_official 237:f3da66175598 799 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official 237:f3da66175598 800 }
mbed_official 237:f3da66175598 801 }
mbed_official 237:f3da66175598 802
mbed_official 237:f3da66175598 803 /* Wait until RXNE flag */
mbed_official 237:f3da66175598 804 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 237:f3da66175598 805 {
mbed_official 237:f3da66175598 806 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 807 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 808 hspi->RxXferCount--;
mbed_official 237:f3da66175598 809 }
mbed_official 237:f3da66175598 810 if(Timeout != HAL_MAX_DELAY)
mbed_official 237:f3da66175598 811 {
mbed_official 237:f3da66175598 812 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
mbed_official 237:f3da66175598 813 {
mbed_official 237:f3da66175598 814 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 815 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 816 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 817 }
mbed_official 237:f3da66175598 818 }
mbed_official 237:f3da66175598 819 }
mbed_official 237:f3da66175598 820 }
mbed_official 237:f3da66175598 821 /* Transmit and Receive data in 8 Bit mode */
mbed_official 237:f3da66175598 822 else
mbed_official 237:f3da66175598 823 {
mbed_official 237:f3da66175598 824 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
mbed_official 237:f3da66175598 825 {
mbed_official 237:f3da66175598 826 /* check if TXE flag is set to send data */
mbed_official 237:f3da66175598 827 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 237:f3da66175598 828 {
mbed_official 237:f3da66175598 829 if(hspi->TxXferCount > 2)
mbed_official 237:f3da66175598 830 {
mbed_official 237:f3da66175598 831 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 832 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 833 hspi->TxXferCount -= 2;
mbed_official 237:f3da66175598 834 }
mbed_official 237:f3da66175598 835 else
mbed_official 237:f3da66175598 836 {
mbed_official 237:f3da66175598 837 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 237:f3da66175598 838 hspi->TxXferCount--;
mbed_official 237:f3da66175598 839 }
mbed_official 237:f3da66175598 840
mbed_official 237:f3da66175598 841 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 842 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 237:f3da66175598 843 {
mbed_official 237:f3da66175598 844 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official 237:f3da66175598 845 }
mbed_official 237:f3da66175598 846 }
mbed_official 237:f3da66175598 847
mbed_official 237:f3da66175598 848 /* Wait until RXNE flag is reset */
mbed_official 237:f3da66175598 849 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 237:f3da66175598 850 {
mbed_official 237:f3da66175598 851 if(hspi->RxXferCount > 1)
mbed_official 237:f3da66175598 852 {
mbed_official 237:f3da66175598 853 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 854 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 855 hspi->RxXferCount -= 2;
mbed_official 237:f3da66175598 856 if(hspi->RxXferCount <= 1)
mbed_official 237:f3da66175598 857 {
mbed_official 237:f3da66175598 858 /* set fiforxthresold before to switch on 8 bit data size */
mbed_official 237:f3da66175598 859 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 860 }
mbed_official 237:f3da66175598 861 }
mbed_official 237:f3da66175598 862 else
mbed_official 237:f3da66175598 863 {
mbed_official 237:f3da66175598 864 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 865 hspi->RxXferCount--;
mbed_official 237:f3da66175598 866 }
mbed_official 237:f3da66175598 867 }
mbed_official 237:f3da66175598 868 if(Timeout != HAL_MAX_DELAY)
mbed_official 237:f3da66175598 869 {
mbed_official 237:f3da66175598 870 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
mbed_official 237:f3da66175598 871 {
mbed_official 237:f3da66175598 872 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 873 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 874 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 875 }
mbed_official 237:f3da66175598 876 }
mbed_official 237:f3da66175598 877 }
mbed_official 237:f3da66175598 878 }
mbed_official 237:f3da66175598 879
mbed_official 237:f3da66175598 880 /* Read CRC from DR to close CRC calculation process */
mbed_official 237:f3da66175598 881 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 882 {
mbed_official 237:f3da66175598 883 /* Wait until TXE flag */
mbed_official 237:f3da66175598 884 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SPI_FLAG_TXE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 885 {
mbed_official 237:f3da66175598 886 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 887 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 888 }
mbed_official 237:f3da66175598 889
mbed_official 237:f3da66175598 890 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 237:f3da66175598 891 {
mbed_official 237:f3da66175598 892 tmpreg = hspi->Instance->DR;
mbed_official 237:f3da66175598 893 }
mbed_official 237:f3da66175598 894 else
mbed_official 237:f3da66175598 895 {
mbed_official 237:f3da66175598 896 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 897 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 237:f3da66175598 898 {
mbed_official 237:f3da66175598 899 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SPI_FLAG_TXE, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 900 {
mbed_official 237:f3da66175598 901 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 902 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 903 }
mbed_official 237:f3da66175598 904 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 905 }
mbed_official 237:f3da66175598 906 }
mbed_official 237:f3da66175598 907 }
mbed_official 237:f3da66175598 908
mbed_official 237:f3da66175598 909 /* Check the end of the transaction */
mbed_official 237:f3da66175598 910 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 237:f3da66175598 911 {
mbed_official 237:f3da66175598 912 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 913 }
mbed_official 237:f3da66175598 914
mbed_official 237:f3da66175598 915 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 916
mbed_official 237:f3da66175598 917 /* Check if CRC error occurred */
mbed_official 237:f3da66175598 918 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 919 {
mbed_official 237:f3da66175598 920 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 921 /* Clear CRC Flag */
mbed_official 237:f3da66175598 922 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 923
mbed_official 237:f3da66175598 924 /* Process Unlocked */
mbed_official 237:f3da66175598 925 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 926
mbed_official 237:f3da66175598 927 return HAL_ERROR;
mbed_official 237:f3da66175598 928 }
mbed_official 237:f3da66175598 929
mbed_official 237:f3da66175598 930 /* Process Unlocked */
mbed_official 237:f3da66175598 931 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 932
mbed_official 237:f3da66175598 933 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 934 {
mbed_official 237:f3da66175598 935 return HAL_ERROR;
mbed_official 237:f3da66175598 936 }
mbed_official 237:f3da66175598 937 else
mbed_official 237:f3da66175598 938 {
mbed_official 237:f3da66175598 939 return HAL_OK;
mbed_official 237:f3da66175598 940 }
mbed_official 237:f3da66175598 941 }
mbed_official 237:f3da66175598 942
mbed_official 237:f3da66175598 943 /**
mbed_official 237:f3da66175598 944 * @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official 237:f3da66175598 945 * @param hspi: SPI handle
mbed_official 237:f3da66175598 946 * @param pData: pointer to data buffer
mbed_official 237:f3da66175598 947 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 948 * @retval HAL status
mbed_official 237:f3da66175598 949 */
mbed_official 237:f3da66175598 950 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 237:f3da66175598 951 {
mbed_official 237:f3da66175598 952 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 237:f3da66175598 953
mbed_official 237:f3da66175598 954 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 955 {
mbed_official 237:f3da66175598 956 if((pData == NULL) || (Size == 0))
mbed_official 237:f3da66175598 957 {
mbed_official 237:f3da66175598 958 return HAL_ERROR;
mbed_official 237:f3da66175598 959 }
mbed_official 237:f3da66175598 960
mbed_official 237:f3da66175598 961 /* Process Locked */
mbed_official 237:f3da66175598 962 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 963
mbed_official 237:f3da66175598 964 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 237:f3da66175598 965 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 966 hspi->pTxBuffPtr = pData;
mbed_official 237:f3da66175598 967 hspi->TxXferSize = Size;
mbed_official 237:f3da66175598 968 hspi->TxXferCount = Size;
mbed_official 237:f3da66175598 969 hspi->pRxBuffPtr = NULL;
mbed_official 237:f3da66175598 970 hspi->RxXferSize = 0;
mbed_official 237:f3da66175598 971 hspi->RxXferCount = 0;
mbed_official 237:f3da66175598 972
mbed_official 237:f3da66175598 973 /* Set the function for IT treatement */
mbed_official 237:f3da66175598 974 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 237:f3da66175598 975 {
mbed_official 237:f3da66175598 976 hspi->RxISR = NULL;
mbed_official 237:f3da66175598 977 hspi->TxISR = SPI_TxISR_16BIT;
mbed_official 237:f3da66175598 978 }
mbed_official 237:f3da66175598 979 else
mbed_official 237:f3da66175598 980 {
mbed_official 237:f3da66175598 981 hspi->RxISR = NULL;
mbed_official 237:f3da66175598 982 hspi->TxISR = SPI_TxISR_8BIT;
mbed_official 237:f3da66175598 983 }
mbed_official 237:f3da66175598 984
mbed_official 237:f3da66175598 985 /* Configure communication direction : 1Line */
mbed_official 237:f3da66175598 986 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 237:f3da66175598 987 {
mbed_official 237:f3da66175598 988 __HAL_SPI_1LINE_TX(hspi);
mbed_official 237:f3da66175598 989 }
mbed_official 237:f3da66175598 990
mbed_official 237:f3da66175598 991 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 992 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 993 {
mbed_official 237:f3da66175598 994 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 995 }
mbed_official 237:f3da66175598 996
mbed_official 237:f3da66175598 997 /* Enable TXE and ERR interrupt */
mbed_official 237:f3da66175598 998 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
mbed_official 237:f3da66175598 999
mbed_official 237:f3da66175598 1000 /* Process Unlocked */
mbed_official 237:f3da66175598 1001 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1002
mbed_official 237:f3da66175598 1003 /* Note : The SPI must be enabled after unlocking current process
mbed_official 237:f3da66175598 1004 to avoid the risk of SPI interrupt handle execution before current
mbed_official 237:f3da66175598 1005 process unlock */
mbed_official 237:f3da66175598 1006
mbed_official 237:f3da66175598 1007 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 1008 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 1009 {
mbed_official 237:f3da66175598 1010 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 1011 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 1012 }
mbed_official 237:f3da66175598 1013
mbed_official 237:f3da66175598 1014 return HAL_OK;
mbed_official 237:f3da66175598 1015 }
mbed_official 237:f3da66175598 1016 else
mbed_official 237:f3da66175598 1017 {
mbed_official 237:f3da66175598 1018 return HAL_BUSY;
mbed_official 237:f3da66175598 1019 }
mbed_official 237:f3da66175598 1020 }
mbed_official 237:f3da66175598 1021
mbed_official 237:f3da66175598 1022 /**
mbed_official 237:f3da66175598 1023 * @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official 237:f3da66175598 1024 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1025 * @param pData: pointer to data buffer
mbed_official 237:f3da66175598 1026 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 1027 * @retval HAL status
mbed_official 237:f3da66175598 1028 */
mbed_official 237:f3da66175598 1029 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 237:f3da66175598 1030 {
mbed_official 237:f3da66175598 1031 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 1032 {
mbed_official 237:f3da66175598 1033 if((pData == NULL) || (Size == 0))
mbed_official 237:f3da66175598 1034 {
mbed_official 237:f3da66175598 1035 return HAL_ERROR;
mbed_official 237:f3da66175598 1036 }
mbed_official 237:f3da66175598 1037
mbed_official 237:f3da66175598 1038 /* Process Locked */
mbed_official 237:f3da66175598 1039 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 1040
mbed_official 237:f3da66175598 1041 /* Configure communication */
mbed_official 237:f3da66175598 1042 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 237:f3da66175598 1043 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 1044 hspi->pRxBuffPtr = pData;
mbed_official 237:f3da66175598 1045 hspi->RxXferSize = Size;
mbed_official 237:f3da66175598 1046 hspi->RxXferCount = Size;
mbed_official 237:f3da66175598 1047 hspi->pTxBuffPtr = NULL;
mbed_official 237:f3da66175598 1048 hspi->TxXferSize = 0;
mbed_official 237:f3da66175598 1049 hspi->TxXferCount = 0;
mbed_official 237:f3da66175598 1050
mbed_official 237:f3da66175598 1051 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 237:f3da66175598 1052 {
mbed_official 237:f3da66175598 1053 /* Process Unlocked */
mbed_official 237:f3da66175598 1054 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1055 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 237:f3da66175598 1056 /* in this we call the transmitReceive process */
mbed_official 237:f3da66175598 1057 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
mbed_official 237:f3da66175598 1058 }
mbed_official 237:f3da66175598 1059
mbed_official 237:f3da66175598 1060 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1061 {
mbed_official 237:f3da66175598 1062 hspi->CRCSize = 1;
mbed_official 237:f3da66175598 1063 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 237:f3da66175598 1064 {
mbed_official 237:f3da66175598 1065 hspi->CRCSize = 2;
mbed_official 237:f3da66175598 1066 }
mbed_official 237:f3da66175598 1067 }
mbed_official 237:f3da66175598 1068 else
mbed_official 237:f3da66175598 1069 {
mbed_official 237:f3da66175598 1070 hspi->CRCSize = 0;
mbed_official 237:f3da66175598 1071 }
mbed_official 237:f3da66175598 1072
mbed_official 237:f3da66175598 1073 /* check the data size to adapt Rx threshold and the set the function for IT treatement */
mbed_official 237:f3da66175598 1074 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 237:f3da66175598 1075 {
mbed_official 237:f3da66175598 1076 /* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official 237:f3da66175598 1077 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1078 hspi->RxISR = SPI_RxISR_16BIT;
mbed_official 237:f3da66175598 1079 hspi->TxISR = NULL;
mbed_official 237:f3da66175598 1080 }
mbed_official 237:f3da66175598 1081 else
mbed_official 237:f3da66175598 1082 {
mbed_official 237:f3da66175598 1083 /* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official 237:f3da66175598 1084 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1085 hspi->RxISR = SPI_RxISR_8BIT;
mbed_official 237:f3da66175598 1086 hspi->TxISR = NULL;
mbed_official 237:f3da66175598 1087 }
mbed_official 237:f3da66175598 1088
mbed_official 237:f3da66175598 1089 /* Configure communication direction : 1Line */
mbed_official 237:f3da66175598 1090 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 237:f3da66175598 1091 {
mbed_official 237:f3da66175598 1092 __HAL_SPI_1LINE_RX(hspi);
mbed_official 237:f3da66175598 1093 }
mbed_official 237:f3da66175598 1094
mbed_official 237:f3da66175598 1095 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 1096 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1097 {
mbed_official 237:f3da66175598 1098 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 1099 }
mbed_official 237:f3da66175598 1100
mbed_official 237:f3da66175598 1101 /* Enable TXE and ERR interrupt */
mbed_official 237:f3da66175598 1102 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 237:f3da66175598 1103
mbed_official 237:f3da66175598 1104 /* Process Unlocked */
mbed_official 237:f3da66175598 1105 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1106
mbed_official 237:f3da66175598 1107 /* Note : The SPI must be enabled after unlocking current process
mbed_official 237:f3da66175598 1108 to avoid the risk of SPI interrupt handle execution before current
mbed_official 237:f3da66175598 1109 process unlock */
mbed_official 237:f3da66175598 1110
mbed_official 237:f3da66175598 1111 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 1112 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 1113 {
mbed_official 237:f3da66175598 1114 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 1115 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 1116 }
mbed_official 237:f3da66175598 1117
mbed_official 237:f3da66175598 1118 return HAL_OK;
mbed_official 237:f3da66175598 1119 }
mbed_official 237:f3da66175598 1120 else
mbed_official 237:f3da66175598 1121 {
mbed_official 237:f3da66175598 1122 return HAL_BUSY;
mbed_official 237:f3da66175598 1123 }
mbed_official 237:f3da66175598 1124 }
mbed_official 237:f3da66175598 1125
mbed_official 237:f3da66175598 1126 /**
mbed_official 237:f3da66175598 1127 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official 237:f3da66175598 1128 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1129 * @param pTxData: pointer to transmission data buffer
mbed_official 237:f3da66175598 1130 * @param pRxData: pointer to reception data buffer to be
mbed_official 237:f3da66175598 1131 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 1132 * @retval HAL status
mbed_official 237:f3da66175598 1133 */
mbed_official 237:f3da66175598 1134 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 237:f3da66175598 1135 {
mbed_official 237:f3da66175598 1136 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 237:f3da66175598 1137
mbed_official 237:f3da66175598 1138 if((hspi->State == HAL_SPI_STATE_READY) || \
mbed_official 237:f3da66175598 1139 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official 237:f3da66175598 1140 {
mbed_official 237:f3da66175598 1141 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 237:f3da66175598 1142 {
mbed_official 237:f3da66175598 1143 return HAL_ERROR;
mbed_official 237:f3da66175598 1144 }
mbed_official 237:f3da66175598 1145
mbed_official 237:f3da66175598 1146 /* Process locked */
mbed_official 237:f3da66175598 1147 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 1148
mbed_official 237:f3da66175598 1149 hspi->CRCSize = 0;
mbed_official 237:f3da66175598 1150 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1151 {
mbed_official 237:f3da66175598 1152 hspi->CRCSize = 1;
mbed_official 237:f3da66175598 1153 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 237:f3da66175598 1154 {
mbed_official 237:f3da66175598 1155 hspi->CRCSize = 2;
mbed_official 237:f3da66175598 1156 }
mbed_official 237:f3da66175598 1157 }
mbed_official 237:f3da66175598 1158
mbed_official 237:f3da66175598 1159 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 237:f3da66175598 1160 {
mbed_official 237:f3da66175598 1161 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 237:f3da66175598 1162 }
mbed_official 237:f3da66175598 1163
mbed_official 237:f3da66175598 1164 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 1165 hspi->pTxBuffPtr = pTxData;
mbed_official 237:f3da66175598 1166 hspi->TxXferSize = Size;
mbed_official 237:f3da66175598 1167 hspi->TxXferCount = Size;
mbed_official 237:f3da66175598 1168 hspi->pRxBuffPtr = pRxData;
mbed_official 237:f3da66175598 1169 hspi->RxXferSize = Size;
mbed_official 237:f3da66175598 1170 hspi->RxXferCount = Size;
mbed_official 237:f3da66175598 1171
mbed_official 237:f3da66175598 1172 /* Set the function for IT treatement */
mbed_official 237:f3da66175598 1173 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 237:f3da66175598 1174 {
mbed_official 237:f3da66175598 1175 hspi->RxISR = SPI_2linesRxISR_16BIT;
mbed_official 237:f3da66175598 1176 hspi->TxISR = SPI_2linesTxISR_16BIT;
mbed_official 237:f3da66175598 1177 }
mbed_official 237:f3da66175598 1178 else
mbed_official 237:f3da66175598 1179 {
mbed_official 237:f3da66175598 1180 hspi->RxISR = SPI_2linesRxISR_8BIT;
mbed_official 237:f3da66175598 1181 hspi->TxISR = SPI_2linesTxISR_8BIT;
mbed_official 237:f3da66175598 1182 }
mbed_official 237:f3da66175598 1183
mbed_official 237:f3da66175598 1184 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 1185 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1186 {
mbed_official 237:f3da66175598 1187 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 1188 }
mbed_official 237:f3da66175598 1189
mbed_official 237:f3da66175598 1190 /* check if packing mode is enabled and if there is more than 2 data to receive */
mbed_official 237:f3da66175598 1191 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
mbed_official 237:f3da66175598 1192 {
mbed_official 237:f3da66175598 1193 /* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official 237:f3da66175598 1194 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1195 }
mbed_official 237:f3da66175598 1196 else
mbed_official 237:f3da66175598 1197 {
mbed_official 237:f3da66175598 1198 /* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official 237:f3da66175598 1199 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1200 }
mbed_official 237:f3da66175598 1201
mbed_official 237:f3da66175598 1202 /* Enable TXE, RXNE and ERR interrupt */
mbed_official 237:f3da66175598 1203 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 237:f3da66175598 1204
mbed_official 237:f3da66175598 1205 /* Process Unlocked */
mbed_official 237:f3da66175598 1206 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1207
mbed_official 237:f3da66175598 1208 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 1209 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 1210 {
mbed_official 237:f3da66175598 1211 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 1212 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 1213 }
mbed_official 237:f3da66175598 1214
mbed_official 237:f3da66175598 1215 return HAL_OK;
mbed_official 237:f3da66175598 1216 }
mbed_official 237:f3da66175598 1217 else
mbed_official 237:f3da66175598 1218 {
mbed_official 237:f3da66175598 1219 return HAL_BUSY;
mbed_official 237:f3da66175598 1220 }
mbed_official 237:f3da66175598 1221 }
mbed_official 237:f3da66175598 1222
mbed_official 237:f3da66175598 1223 /**
mbed_official 237:f3da66175598 1224 * @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official 237:f3da66175598 1225 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1226 * @param pData: pointer to data buffer
mbed_official 237:f3da66175598 1227 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 1228 * @retval HAL status
mbed_official 237:f3da66175598 1229 */
mbed_official 237:f3da66175598 1230 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 237:f3da66175598 1231 {
mbed_official 237:f3da66175598 1232 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 237:f3da66175598 1233
mbed_official 237:f3da66175598 1234 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 1235 {
mbed_official 237:f3da66175598 1236 return HAL_BUSY;
mbed_official 237:f3da66175598 1237 }
mbed_official 237:f3da66175598 1238
mbed_official 237:f3da66175598 1239 if((pData == NULL) || (Size == 0))
mbed_official 237:f3da66175598 1240 {
mbed_official 237:f3da66175598 1241 return HAL_ERROR;
mbed_official 237:f3da66175598 1242 }
mbed_official 237:f3da66175598 1243
mbed_official 237:f3da66175598 1244 /* Process Locked */
mbed_official 237:f3da66175598 1245 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 1246
mbed_official 237:f3da66175598 1247 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 237:f3da66175598 1248 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 1249 hspi->pTxBuffPtr = pData;
mbed_official 237:f3da66175598 1250 hspi->TxXferSize = Size;
mbed_official 237:f3da66175598 1251 hspi->TxXferCount = Size;
mbed_official 237:f3da66175598 1252 hspi->pRxBuffPtr = NULL;
mbed_official 237:f3da66175598 1253 hspi->RxXferSize = 0;
mbed_official 237:f3da66175598 1254 hspi->RxXferCount = 0;
mbed_official 237:f3da66175598 1255
mbed_official 237:f3da66175598 1256 /* Configure communication direction : 1Line */
mbed_official 237:f3da66175598 1257 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 237:f3da66175598 1258 {
mbed_official 237:f3da66175598 1259 __HAL_SPI_1LINE_TX(hspi);
mbed_official 237:f3da66175598 1260 }
mbed_official 237:f3da66175598 1261
mbed_official 237:f3da66175598 1262 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 1263 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1264 {
mbed_official 237:f3da66175598 1265 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 1266 }
mbed_official 237:f3da66175598 1267
mbed_official 237:f3da66175598 1268 /* Set the SPI TxDMA transfer complete callback */
mbed_official 237:f3da66175598 1269 hspi->hdmatx->XferCpltCallback = HAL_SPI_DMATransmitCplt;
mbed_official 237:f3da66175598 1270
mbed_official 237:f3da66175598 1271 /* Set the DMA error callback */
mbed_official 237:f3da66175598 1272 hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 237:f3da66175598 1273
mbed_official 237:f3da66175598 1274 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 237:f3da66175598 1275 /* packing mode is enabled only if the DMA setting is HALWORD */
mbed_official 237:f3da66175598 1276 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 237:f3da66175598 1277 {
mbed_official 237:f3da66175598 1278 /* Check the even/odd of the data size + crc if enabled */
mbed_official 237:f3da66175598 1279 if((hspi->TxXferCount & 0x1) == 0)
mbed_official 237:f3da66175598 1280 {
mbed_official 237:f3da66175598 1281 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 237:f3da66175598 1282 hspi->TxXferCount = (hspi->TxXferCount >> 1);
mbed_official 237:f3da66175598 1283 }
mbed_official 237:f3da66175598 1284 else
mbed_official 237:f3da66175598 1285 {
mbed_official 237:f3da66175598 1286 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 237:f3da66175598 1287 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 237:f3da66175598 1288 }
mbed_official 237:f3da66175598 1289 }
mbed_official 237:f3da66175598 1290
mbed_official 237:f3da66175598 1291 /* Enable the Tx DMA channel */
mbed_official 237:f3da66175598 1292 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 237:f3da66175598 1293
mbed_official 237:f3da66175598 1294 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 1295 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 1296 {
mbed_official 237:f3da66175598 1297 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 1298 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 1299 }
mbed_official 237:f3da66175598 1300
mbed_official 237:f3da66175598 1301 /* Enable Tx DMA Request */
mbed_official 237:f3da66175598 1302 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 237:f3da66175598 1303
mbed_official 237:f3da66175598 1304 /* Process Unlocked */
mbed_official 237:f3da66175598 1305 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1306
mbed_official 237:f3da66175598 1307 return HAL_OK;
mbed_official 237:f3da66175598 1308 }
mbed_official 237:f3da66175598 1309
mbed_official 237:f3da66175598 1310 /**
mbed_official 237:f3da66175598 1311 * @brief Receive an amount of data in no-blocking mode with DMA
mbed_official 237:f3da66175598 1312 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1313 * @param pData: pointer to data buffer
mbed_official 237:f3da66175598 1314 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 1315 * @retval HAL status
mbed_official 237:f3da66175598 1316 */
mbed_official 237:f3da66175598 1317 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 237:f3da66175598 1318 {
mbed_official 237:f3da66175598 1319 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 237:f3da66175598 1320 {
mbed_official 237:f3da66175598 1321 return HAL_BUSY;
mbed_official 237:f3da66175598 1322 }
mbed_official 237:f3da66175598 1323
mbed_official 237:f3da66175598 1324 if((pData == NULL) || (Size == 0))
mbed_official 237:f3da66175598 1325 {
mbed_official 237:f3da66175598 1326 return HAL_ERROR;
mbed_official 237:f3da66175598 1327 }
mbed_official 237:f3da66175598 1328
mbed_official 237:f3da66175598 1329 /* Process Locked */
mbed_official 237:f3da66175598 1330 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 1331
mbed_official 237:f3da66175598 1332 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 237:f3da66175598 1333 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 1334 hspi->pRxBuffPtr = pData;
mbed_official 237:f3da66175598 1335 hspi->RxXferSize = Size;
mbed_official 237:f3da66175598 1336 hspi->RxXferCount = Size;
mbed_official 237:f3da66175598 1337 hspi->pTxBuffPtr = NULL;
mbed_official 237:f3da66175598 1338 hspi->TxXferSize = 0;
mbed_official 237:f3da66175598 1339 hspi->TxXferCount = 0;
mbed_official 237:f3da66175598 1340
mbed_official 237:f3da66175598 1341 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 237:f3da66175598 1342 {
mbed_official 237:f3da66175598 1343 /* Process Unlocked */
mbed_official 237:f3da66175598 1344 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1345 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 237:f3da66175598 1346 /* in this case we call the transmitReceive process */
mbed_official 237:f3da66175598 1347 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
mbed_official 237:f3da66175598 1348 }
mbed_official 237:f3da66175598 1349
mbed_official 237:f3da66175598 1350 /* Configure communication direction : 1Line */
mbed_official 237:f3da66175598 1351 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 237:f3da66175598 1352 {
mbed_official 237:f3da66175598 1353 __HAL_SPI_1LINE_RX(hspi);
mbed_official 237:f3da66175598 1354 }
mbed_official 237:f3da66175598 1355
mbed_official 237:f3da66175598 1356 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 1357 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1358 {
mbed_official 237:f3da66175598 1359 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 1360 }
mbed_official 237:f3da66175598 1361
mbed_official 237:f3da66175598 1362 /* packing mode management is enabled by the DMA settings */
mbed_official 237:f3da66175598 1363 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 237:f3da66175598 1364 {
mbed_official 237:f3da66175598 1365 /* Process Locked */
mbed_official 237:f3da66175598 1366 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1367 /* Restriction the DMA data received is not allowed in this mode */
mbed_official 237:f3da66175598 1368 return HAL_ERROR;
mbed_official 237:f3da66175598 1369 }
mbed_official 237:f3da66175598 1370
mbed_official 237:f3da66175598 1371 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 237:f3da66175598 1372 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 1373 {
mbed_official 237:f3da66175598 1374 /* set fiforxthresold according the reception data lenght: 16bit */
mbed_official 237:f3da66175598 1375 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1376 }
mbed_official 237:f3da66175598 1377 else
mbed_official 237:f3da66175598 1378 {
mbed_official 237:f3da66175598 1379 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 237:f3da66175598 1380 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1381 }
mbed_official 237:f3da66175598 1382
mbed_official 237:f3da66175598 1383 /* Set the SPI Rx DMA transfer complete callback */
mbed_official 237:f3da66175598 1384 hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
mbed_official 237:f3da66175598 1385
mbed_official 237:f3da66175598 1386 /* Set the DMA error callback */
mbed_official 237:f3da66175598 1387 hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 237:f3da66175598 1388
mbed_official 237:f3da66175598 1389 /* Enable Rx DMA Request */
mbed_official 237:f3da66175598 1390 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 237:f3da66175598 1391
mbed_official 237:f3da66175598 1392 /* Enable the Rx DMA channel */
mbed_official 237:f3da66175598 1393 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 237:f3da66175598 1394
mbed_official 237:f3da66175598 1395 /* Process Unlocked */
mbed_official 237:f3da66175598 1396 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1397
mbed_official 237:f3da66175598 1398 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 1399 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 1400 {
mbed_official 237:f3da66175598 1401 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 1402 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 1403 }
mbed_official 237:f3da66175598 1404
mbed_official 237:f3da66175598 1405 return HAL_OK;
mbed_official 237:f3da66175598 1406 }
mbed_official 237:f3da66175598 1407
mbed_official 237:f3da66175598 1408 /**
mbed_official 237:f3da66175598 1409 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official 237:f3da66175598 1410 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1411 * @param pTxData: pointer to transmission data buffer
mbed_official 237:f3da66175598 1412 * @param pRxData: pointer to reception data buffer to be
mbed_official 237:f3da66175598 1413 * @param Size: amount of data to be sent
mbed_official 237:f3da66175598 1414 * @retval HAL status
mbed_official 237:f3da66175598 1415 */
mbed_official 237:f3da66175598 1416 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 237:f3da66175598 1417 {
mbed_official 237:f3da66175598 1418 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 237:f3da66175598 1419
mbed_official 237:f3da66175598 1420 if((hspi->State == HAL_SPI_STATE_READY) ||
mbed_official 237:f3da66175598 1421 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official 237:f3da66175598 1422 {
mbed_official 237:f3da66175598 1423 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 237:f3da66175598 1424 {
mbed_official 237:f3da66175598 1425 return HAL_ERROR;
mbed_official 237:f3da66175598 1426 }
mbed_official 237:f3da66175598 1427
mbed_official 237:f3da66175598 1428 /* Process locked */
mbed_official 237:f3da66175598 1429 __HAL_LOCK(hspi);
mbed_official 237:f3da66175598 1430
mbed_official 237:f3da66175598 1431 /* check if the transmit Receive function is not called by a receive master */
mbed_official 237:f3da66175598 1432 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 237:f3da66175598 1433 {
mbed_official 237:f3da66175598 1434 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 237:f3da66175598 1435 }
mbed_official 237:f3da66175598 1436
mbed_official 237:f3da66175598 1437 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 237:f3da66175598 1438 hspi->pTxBuffPtr = (uint8_t *)pTxData;
mbed_official 237:f3da66175598 1439 hspi->TxXferSize = Size;
mbed_official 237:f3da66175598 1440 hspi->TxXferCount = Size;
mbed_official 237:f3da66175598 1441 hspi->pRxBuffPtr = (uint8_t *)pRxData;
mbed_official 237:f3da66175598 1442 hspi->RxXferSize = Size;
mbed_official 237:f3da66175598 1443 hspi->RxXferCount = Size;
mbed_official 237:f3da66175598 1444
mbed_official 237:f3da66175598 1445 /* Reset CRC Calculation + increase the rxsize */
mbed_official 237:f3da66175598 1446 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1447 {
mbed_official 237:f3da66175598 1448 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 1449 }
mbed_official 237:f3da66175598 1450
mbed_official 237:f3da66175598 1451 /* Reset the threshold bit */
mbed_official 237:f3da66175598 1452 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 237:f3da66175598 1453 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 237:f3da66175598 1454
mbed_official 237:f3da66175598 1455 /* the packing mode management is enabled by the DMA settings according the spi data size */
mbed_official 237:f3da66175598 1456 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 1457 {
mbed_official 237:f3da66175598 1458 /* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official 237:f3da66175598 1459 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1460 }
mbed_official 237:f3da66175598 1461 else
mbed_official 237:f3da66175598 1462 {
mbed_official 237:f3da66175598 1463 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 237:f3da66175598 1464 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1465
mbed_official 237:f3da66175598 1466 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 237:f3da66175598 1467 {
mbed_official 237:f3da66175598 1468 if((hspi->TxXferSize & 0x1) == 0x0 )
mbed_official 237:f3da66175598 1469 {
mbed_official 237:f3da66175598 1470 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 237:f3da66175598 1471 hspi->TxXferCount = hspi->TxXferCount >> 1;
mbed_official 237:f3da66175598 1472 }
mbed_official 237:f3da66175598 1473 else
mbed_official 237:f3da66175598 1474 {
mbed_official 237:f3da66175598 1475 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 237:f3da66175598 1476 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 237:f3da66175598 1477 }
mbed_official 237:f3da66175598 1478 }
mbed_official 237:f3da66175598 1479
mbed_official 237:f3da66175598 1480 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 237:f3da66175598 1481 {
mbed_official 237:f3da66175598 1482 /* set fiforxthresold according the reception data lenght: 16bit */
mbed_official 237:f3da66175598 1483 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1484
mbed_official 237:f3da66175598 1485 /* Size must include the CRC lenght */
mbed_official 237:f3da66175598 1486 if((hspi->RxXferCount & 0x1) == 0x0 )
mbed_official 237:f3da66175598 1487 {
mbed_official 237:f3da66175598 1488 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 237:f3da66175598 1489 hspi->RxXferCount = hspi->RxXferCount >> 1;
mbed_official 237:f3da66175598 1490 }
mbed_official 237:f3da66175598 1491 else
mbed_official 237:f3da66175598 1492 {
mbed_official 237:f3da66175598 1493 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 237:f3da66175598 1494 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
mbed_official 237:f3da66175598 1495 }
mbed_official 237:f3da66175598 1496 }
mbed_official 237:f3da66175598 1497 }
mbed_official 237:f3da66175598 1498
mbed_official 237:f3da66175598 1499 /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
mbed_official 237:f3da66175598 1500 the reception request (RXNE) */
mbed_official 237:f3da66175598 1501 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 237:f3da66175598 1502 {
mbed_official 237:f3da66175598 1503 hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
mbed_official 237:f3da66175598 1504 }
mbed_official 237:f3da66175598 1505 else
mbed_official 237:f3da66175598 1506 {
mbed_official 237:f3da66175598 1507 hspi->hdmarx->XferCpltCallback = HAL_SPI_DMATransmitReceiveCplt;
mbed_official 237:f3da66175598 1508 }
mbed_official 237:f3da66175598 1509 /* Set the DMA error callback */
mbed_official 237:f3da66175598 1510 hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 237:f3da66175598 1511
mbed_official 237:f3da66175598 1512 /* Enable Rx DMA Request */
mbed_official 237:f3da66175598 1513 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 237:f3da66175598 1514
mbed_official 237:f3da66175598 1515 /* Enable the Rx DMA channel */
mbed_official 237:f3da66175598 1516 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 237:f3da66175598 1517
mbed_official 237:f3da66175598 1518 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official 237:f3da66175598 1519 is performed in DMA reception complete callback */
mbed_official 237:f3da66175598 1520 hspi->hdmatx->XferCpltCallback = NULL;
mbed_official 237:f3da66175598 1521
mbed_official 237:f3da66175598 1522 /* Set the DMA error callback */
mbed_official 237:f3da66175598 1523 hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 237:f3da66175598 1524
mbed_official 237:f3da66175598 1525 /* Enable the Tx DMA channel */
mbed_official 237:f3da66175598 1526 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 237:f3da66175598 1527
mbed_official 237:f3da66175598 1528 /* Check if the SPI is already enabled */
mbed_official 237:f3da66175598 1529 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 237:f3da66175598 1530 {
mbed_official 237:f3da66175598 1531 /* Enable SPI peripheral */
mbed_official 237:f3da66175598 1532 __HAL_SPI_ENABLE(hspi);
mbed_official 237:f3da66175598 1533 }
mbed_official 237:f3da66175598 1534
mbed_official 237:f3da66175598 1535 /* Enable Tx DMA Request */
mbed_official 237:f3da66175598 1536 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 237:f3da66175598 1537
mbed_official 237:f3da66175598 1538 /* Process Unlocked */
mbed_official 237:f3da66175598 1539 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 1540
mbed_official 237:f3da66175598 1541 return HAL_OK;
mbed_official 237:f3da66175598 1542 }
mbed_official 237:f3da66175598 1543 else
mbed_official 237:f3da66175598 1544 {
mbed_official 237:f3da66175598 1545 return HAL_BUSY;
mbed_official 237:f3da66175598 1546 }
mbed_official 237:f3da66175598 1547 }
mbed_official 237:f3da66175598 1548
mbed_official 237:f3da66175598 1549 /**
mbed_official 237:f3da66175598 1550 * @brief This function handles SPI interrupt request.
mbed_official 237:f3da66175598 1551 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1552 * @retval HAL status
mbed_official 237:f3da66175598 1553 */
mbed_official 237:f3da66175598 1554 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1555 {
mbed_official 237:f3da66175598 1556 /* SPI in mode Receiver ----------------------------------------------------*/
mbed_official 237:f3da66175598 1557 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
mbed_official 237:f3da66175598 1558 (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
mbed_official 237:f3da66175598 1559 {
mbed_official 237:f3da66175598 1560 hspi->RxISR(hspi);
mbed_official 237:f3da66175598 1561 return;
mbed_official 237:f3da66175598 1562 }
mbed_official 237:f3da66175598 1563
mbed_official 237:f3da66175598 1564 /* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official 237:f3da66175598 1565 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
mbed_official 237:f3da66175598 1566 {
mbed_official 237:f3da66175598 1567 hspi->TxISR(hspi);
mbed_official 237:f3da66175598 1568 return;
mbed_official 237:f3da66175598 1569 }
mbed_official 237:f3da66175598 1570
mbed_official 237:f3da66175598 1571 /* SPI in Erreur Treatment ---------------------------------------------------*/
mbed_official 237:f3da66175598 1572 if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
mbed_official 237:f3da66175598 1573 {
mbed_official 237:f3da66175598 1574 /* SPI Overrun error interrupt occured -------------------------------------*/
mbed_official 237:f3da66175598 1575 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official 237:f3da66175598 1576 {
mbed_official 237:f3da66175598 1577 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official 237:f3da66175598 1578 {
mbed_official 237:f3da66175598 1579 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
mbed_official 237:f3da66175598 1580 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 237:f3da66175598 1581 }
mbed_official 237:f3da66175598 1582 else
mbed_official 237:f3da66175598 1583 {
mbed_official 237:f3da66175598 1584 return;
mbed_official 237:f3da66175598 1585 }
mbed_official 237:f3da66175598 1586 }
mbed_official 237:f3da66175598 1587
mbed_official 237:f3da66175598 1588 /* SPI Mode Fault error interrupt occured -------------------------------------*/
mbed_official 237:f3da66175598 1589 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official 237:f3da66175598 1590 {
mbed_official 237:f3da66175598 1591 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
mbed_official 237:f3da66175598 1592 __HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official 237:f3da66175598 1593 }
mbed_official 237:f3da66175598 1594
mbed_official 237:f3da66175598 1595 /* SPI Frame error interrupt occured ----------------------------------------*/
mbed_official 237:f3da66175598 1596 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official 237:f3da66175598 1597 {
mbed_official 237:f3da66175598 1598 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
mbed_official 237:f3da66175598 1599 __HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official 237:f3da66175598 1600 }
mbed_official 237:f3da66175598 1601
mbed_official 237:f3da66175598 1602 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
mbed_official 237:f3da66175598 1603 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1604
mbed_official 237:f3da66175598 1605 return;
mbed_official 237:f3da66175598 1606 }
mbed_official 237:f3da66175598 1607 }
mbed_official 237:f3da66175598 1608
mbed_official 237:f3da66175598 1609 /**
mbed_official 237:f3da66175598 1610 * @brief DMA SPI transmit process complete callback
mbed_official 237:f3da66175598 1611 * @param hdma : DMA handle
mbed_official 237:f3da66175598 1612 * @retval None
mbed_official 237:f3da66175598 1613 */
mbed_official 237:f3da66175598 1614 static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 237:f3da66175598 1615 {
mbed_official 237:f3da66175598 1616 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 237:f3da66175598 1617
mbed_official 237:f3da66175598 1618 /* Disable Tx DMA Request */
mbed_official 237:f3da66175598 1619 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 237:f3da66175598 1620
mbed_official 237:f3da66175598 1621 /* Check the end of the transaction */
mbed_official 237:f3da66175598 1622 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 237:f3da66175598 1623
mbed_official 237:f3da66175598 1624 /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
mbed_official 237:f3da66175598 1625 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 237:f3da66175598 1626 {
mbed_official 237:f3da66175598 1627 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 237:f3da66175598 1628 }
mbed_official 237:f3da66175598 1629
mbed_official 237:f3da66175598 1630 hspi->TxXferCount = 0;
mbed_official 237:f3da66175598 1631 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 1632
mbed_official 237:f3da66175598 1633 /* Check if CRC error occurred or Error code */
mbed_official 237:f3da66175598 1634 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 1635 {
mbed_official 237:f3da66175598 1636 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1637 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 1638 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1639 }
mbed_official 237:f3da66175598 1640 else
mbed_official 237:f3da66175598 1641 {
mbed_official 237:f3da66175598 1642 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 1643 {
mbed_official 237:f3da66175598 1644 HAL_SPI_TxCpltCallback(hspi);
mbed_official 237:f3da66175598 1645 }
mbed_official 237:f3da66175598 1646 else
mbed_official 237:f3da66175598 1647 {
mbed_official 237:f3da66175598 1648 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1649 }
mbed_official 237:f3da66175598 1650 }
mbed_official 237:f3da66175598 1651 }
mbed_official 237:f3da66175598 1652
mbed_official 237:f3da66175598 1653 /**
mbed_official 237:f3da66175598 1654 * @brief DMA SPI receive process complete callback
mbed_official 237:f3da66175598 1655 * @param hdma : DMA handle
mbed_official 237:f3da66175598 1656 * @retval None
mbed_official 237:f3da66175598 1657 */
mbed_official 237:f3da66175598 1658 static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 237:f3da66175598 1659 {
mbed_official 237:f3da66175598 1660 __IO uint16_t tmpreg;
mbed_official 237:f3da66175598 1661 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 237:f3da66175598 1662
mbed_official 237:f3da66175598 1663 /* CRC handling */
mbed_official 237:f3da66175598 1664 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1665 {
mbed_official 237:f3da66175598 1666 /* Wait until TXE flag */
mbed_official 237:f3da66175598 1667 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 237:f3da66175598 1668 {
mbed_official 237:f3da66175598 1669 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 1670 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1671 }
mbed_official 237:f3da66175598 1672 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 237:f3da66175598 1673 {
mbed_official 237:f3da66175598 1674 tmpreg = hspi->Instance->DR;
mbed_official 237:f3da66175598 1675 }
mbed_official 237:f3da66175598 1676 else
mbed_official 237:f3da66175598 1677 {
mbed_official 237:f3da66175598 1678 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 1679 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 237:f3da66175598 1680 {
mbed_official 237:f3da66175598 1681 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 237:f3da66175598 1682 {
mbed_official 237:f3da66175598 1683 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 1684 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1685 }
mbed_official 237:f3da66175598 1686 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 1687 }
mbed_official 237:f3da66175598 1688 }
mbed_official 237:f3da66175598 1689 }
mbed_official 237:f3da66175598 1690
mbed_official 237:f3da66175598 1691 /* Disable Rx DMA Request */
mbed_official 237:f3da66175598 1692 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 237:f3da66175598 1693 /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
mbed_official 237:f3da66175598 1694 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 237:f3da66175598 1695
mbed_official 237:f3da66175598 1696 /* Check the end of the transaction */
mbed_official 237:f3da66175598 1697 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 237:f3da66175598 1698
mbed_official 237:f3da66175598 1699 hspi->RxXferCount = 0;
mbed_official 237:f3da66175598 1700 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 1701
mbed_official 237:f3da66175598 1702 /* Check if CRC error occurred */
mbed_official 237:f3da66175598 1703 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 1704 {
mbed_official 237:f3da66175598 1705 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1706 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 1707 HAL_SPI_RxCpltCallback(hspi);
mbed_official 237:f3da66175598 1708 }
mbed_official 237:f3da66175598 1709 else
mbed_official 237:f3da66175598 1710 {
mbed_official 237:f3da66175598 1711 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 1712 {
mbed_official 237:f3da66175598 1713 HAL_SPI_RxCpltCallback(hspi);
mbed_official 237:f3da66175598 1714 }
mbed_official 237:f3da66175598 1715 else
mbed_official 237:f3da66175598 1716 {
mbed_official 237:f3da66175598 1717 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1718 }
mbed_official 237:f3da66175598 1719 }
mbed_official 237:f3da66175598 1720 }
mbed_official 237:f3da66175598 1721
mbed_official 237:f3da66175598 1722 /**
mbed_official 237:f3da66175598 1723 * @brief DMA SPI transmit receive process complete callback
mbed_official 237:f3da66175598 1724 * @param hdma : DMA handle
mbed_official 237:f3da66175598 1725 * @retval None
mbed_official 237:f3da66175598 1726 */
mbed_official 237:f3da66175598 1727
mbed_official 237:f3da66175598 1728 static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 237:f3da66175598 1729 {
mbed_official 237:f3da66175598 1730 __IO int16_t tmpreg;
mbed_official 237:f3da66175598 1731 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 237:f3da66175598 1732
mbed_official 237:f3da66175598 1733 /* CRC handling */
mbed_official 237:f3da66175598 1734 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1735 {
mbed_official 237:f3da66175598 1736 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
mbed_official 237:f3da66175598 1737 {
mbed_official 237:f3da66175598 1738 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 237:f3da66175598 1739 {
mbed_official 237:f3da66175598 1740 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 1741 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1742 }
mbed_official 237:f3da66175598 1743 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 237:f3da66175598 1744 }
mbed_official 237:f3da66175598 1745 else
mbed_official 237:f3da66175598 1746 {
mbed_official 237:f3da66175598 1747 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 237:f3da66175598 1748 {
mbed_official 237:f3da66175598 1749 /* Erreur on the CRC reception */
mbed_official 237:f3da66175598 1750 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1751 }
mbed_official 237:f3da66175598 1752 tmpreg = hspi->Instance->DR;
mbed_official 237:f3da66175598 1753 }
mbed_official 237:f3da66175598 1754 }
mbed_official 237:f3da66175598 1755
mbed_official 237:f3da66175598 1756 /* Check the end of the transaction */
mbed_official 237:f3da66175598 1757 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 237:f3da66175598 1758
mbed_official 237:f3da66175598 1759 /* Disable Tx DMA Request */
mbed_official 237:f3da66175598 1760 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 237:f3da66175598 1761
mbed_official 237:f3da66175598 1762 /* Disable Rx DMA Request */
mbed_official 237:f3da66175598 1763 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official 237:f3da66175598 1764
mbed_official 237:f3da66175598 1765 hspi->TxXferCount = 0;
mbed_official 237:f3da66175598 1766 hspi->RxXferCount = 0;
mbed_official 237:f3da66175598 1767 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 1768
mbed_official 237:f3da66175598 1769 /* Check if CRC error occurred */
mbed_official 237:f3da66175598 1770 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 1771 {
mbed_official 237:f3da66175598 1772 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 1773 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 1774 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1775 }
mbed_official 237:f3da66175598 1776 else
mbed_official 237:f3da66175598 1777 {
mbed_official 237:f3da66175598 1778 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 1779 {
mbed_official 237:f3da66175598 1780 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 237:f3da66175598 1781 }
mbed_official 237:f3da66175598 1782 else
mbed_official 237:f3da66175598 1783 {
mbed_official 237:f3da66175598 1784 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1785 }
mbed_official 237:f3da66175598 1786 }
mbed_official 237:f3da66175598 1787 }
mbed_official 237:f3da66175598 1788
mbed_official 237:f3da66175598 1789 /**
mbed_official 237:f3da66175598 1790 * @brief DMA SPI communication error callback
mbed_official 237:f3da66175598 1791 * @param hdma : DMA handle
mbed_official 237:f3da66175598 1792 * @retval None
mbed_official 237:f3da66175598 1793 */
mbed_official 237:f3da66175598 1794 static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 237:f3da66175598 1795 {
mbed_official 237:f3da66175598 1796 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 237:f3da66175598 1797 hspi->TxXferCount = 0;
mbed_official 237:f3da66175598 1798 hspi->RxXferCount = 0;
mbed_official 237:f3da66175598 1799 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
mbed_official 237:f3da66175598 1800 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 1801 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 1802 }
mbed_official 237:f3da66175598 1803
mbed_official 237:f3da66175598 1804 /**
mbed_official 237:f3da66175598 1805 * @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official 237:f3da66175598 1806 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1807 */
mbed_official 237:f3da66175598 1808 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1809 {
mbed_official 237:f3da66175598 1810 /* Receive data in packing mode */
mbed_official 237:f3da66175598 1811 if(hspi->RxXferCount > 1)
mbed_official 237:f3da66175598 1812 {
mbed_official 237:f3da66175598 1813 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 1814 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 1815 hspi->RxXferCount -= 2;
mbed_official 237:f3da66175598 1816 if(hspi->RxXferCount == 1)
mbed_official 237:f3da66175598 1817 {
mbed_official 237:f3da66175598 1818 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 237:f3da66175598 1819 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 237:f3da66175598 1820 }
mbed_official 237:f3da66175598 1821 }
mbed_official 237:f3da66175598 1822 /* Receive data in 8 Bit mode */
mbed_official 237:f3da66175598 1823 else
mbed_official 237:f3da66175598 1824 {
mbed_official 237:f3da66175598 1825 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 237:f3da66175598 1826 hspi->RxXferCount--;
mbed_official 237:f3da66175598 1827 }
mbed_official 237:f3da66175598 1828
mbed_official 237:f3da66175598 1829 /* check end of the reception */
mbed_official 237:f3da66175598 1830 if(hspi->RxXferCount == 0)
mbed_official 237:f3da66175598 1831 {
mbed_official 237:f3da66175598 1832 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1833 {
mbed_official 237:f3da66175598 1834 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
mbed_official 237:f3da66175598 1835 return;
mbed_official 237:f3da66175598 1836 }
mbed_official 237:f3da66175598 1837
mbed_official 237:f3da66175598 1838 /* Disable RXNE interrupt */
mbed_official 237:f3da66175598 1839 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 237:f3da66175598 1840
mbed_official 237:f3da66175598 1841 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 1842 {
mbed_official 237:f3da66175598 1843 SPI_CloseRxTx_ISR(hspi);
mbed_official 237:f3da66175598 1844 }
mbed_official 237:f3da66175598 1845 }
mbed_official 237:f3da66175598 1846 }
mbed_official 237:f3da66175598 1847
mbed_official 237:f3da66175598 1848 /**
mbed_official 237:f3da66175598 1849 * @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official 237:f3da66175598 1850 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1851 */
mbed_official 237:f3da66175598 1852 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1853 {
mbed_official 237:f3da66175598 1854 __IO uint8_t tmpreg;
mbed_official 237:f3da66175598 1855
mbed_official 237:f3da66175598 1856 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 237:f3da66175598 1857 hspi->CRCSize--;
mbed_official 237:f3da66175598 1858
mbed_official 237:f3da66175598 1859 /* check end of the reception */
mbed_official 237:f3da66175598 1860 if(hspi->CRCSize == 0)
mbed_official 237:f3da66175598 1861 {
mbed_official 237:f3da66175598 1862 /* Disable RXNE interrupt */
mbed_official 237:f3da66175598 1863 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 237:f3da66175598 1864
mbed_official 237:f3da66175598 1865 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 1866 {
mbed_official 237:f3da66175598 1867 SPI_CloseRxTx_ISR(hspi);
mbed_official 237:f3da66175598 1868 }
mbed_official 237:f3da66175598 1869 }
mbed_official 237:f3da66175598 1870 }
mbed_official 237:f3da66175598 1871
mbed_official 237:f3da66175598 1872 /**
mbed_official 237:f3da66175598 1873 * @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official 237:f3da66175598 1874 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1875 */
mbed_official 237:f3da66175598 1876 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1877 {
mbed_official 237:f3da66175598 1878 /* Transmit data in packing Bit mode */
mbed_official 237:f3da66175598 1879 if(hspi->TxXferCount >= 2)
mbed_official 237:f3da66175598 1880 {
mbed_official 237:f3da66175598 1881 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 1882 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 1883 hspi->TxXferCount -= 2;
mbed_official 237:f3da66175598 1884 }
mbed_official 237:f3da66175598 1885 /* Transmit data in 8 Bit mode */
mbed_official 237:f3da66175598 1886 else
mbed_official 237:f3da66175598 1887 {
mbed_official 237:f3da66175598 1888 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 237:f3da66175598 1889 hspi->TxXferCount--;
mbed_official 237:f3da66175598 1890 }
mbed_official 237:f3da66175598 1891
mbed_official 237:f3da66175598 1892 /* check the end of the transmission */
mbed_official 237:f3da66175598 1893 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 1894 {
mbed_official 237:f3da66175598 1895 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1896 {
mbed_official 237:f3da66175598 1897 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 1898 }
mbed_official 237:f3da66175598 1899 /* Disable TXE interrupt */
mbed_official 237:f3da66175598 1900 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 237:f3da66175598 1901
mbed_official 237:f3da66175598 1902 if(hspi->RxXferCount == 0)
mbed_official 237:f3da66175598 1903 {
mbed_official 237:f3da66175598 1904 SPI_CloseRxTx_ISR(hspi);
mbed_official 237:f3da66175598 1905 }
mbed_official 237:f3da66175598 1906 }
mbed_official 237:f3da66175598 1907 }
mbed_official 237:f3da66175598 1908
mbed_official 237:f3da66175598 1909 /**
mbed_official 237:f3da66175598 1910 * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
mbed_official 237:f3da66175598 1911 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1912 */
mbed_official 237:f3da66175598 1913 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1914 {
mbed_official 237:f3da66175598 1915 /* Receive data in 16 Bit mode */
mbed_official 237:f3da66175598 1916 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 1917 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 1918 hspi->RxXferCount--;
mbed_official 237:f3da66175598 1919
mbed_official 237:f3da66175598 1920 if(hspi->RxXferCount == 0)
mbed_official 237:f3da66175598 1921 {
mbed_official 237:f3da66175598 1922 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1923 {
mbed_official 237:f3da66175598 1924 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
mbed_official 237:f3da66175598 1925 return;
mbed_official 237:f3da66175598 1926 }
mbed_official 237:f3da66175598 1927
mbed_official 237:f3da66175598 1928 /* Disable RXNE interrupt */
mbed_official 237:f3da66175598 1929 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 237:f3da66175598 1930
mbed_official 237:f3da66175598 1931 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 1932 {
mbed_official 237:f3da66175598 1933 SPI_CloseRxTx_ISR(hspi);
mbed_official 237:f3da66175598 1934 }
mbed_official 237:f3da66175598 1935 }
mbed_official 237:f3da66175598 1936 }
mbed_official 237:f3da66175598 1937
mbed_official 237:f3da66175598 1938 /**
mbed_official 237:f3da66175598 1939 * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
mbed_official 237:f3da66175598 1940 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1941 */
mbed_official 237:f3da66175598 1942 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1943 {
mbed_official 237:f3da66175598 1944 __IO uint16_t tmpreg;
mbed_official 237:f3da66175598 1945 /* Receive data in 16 Bit mode */
mbed_official 237:f3da66175598 1946 tmpreg = hspi->Instance->DR;
mbed_official 237:f3da66175598 1947
mbed_official 237:f3da66175598 1948 /* Disable RXNE interrupt */
mbed_official 237:f3da66175598 1949 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 237:f3da66175598 1950
mbed_official 237:f3da66175598 1951 SPI_CloseRxTx_ISR(hspi);
mbed_official 237:f3da66175598 1952 }
mbed_official 237:f3da66175598 1953
mbed_official 237:f3da66175598 1954 /**
mbed_official 237:f3da66175598 1955 * @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official 237:f3da66175598 1956 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1957 */
mbed_official 237:f3da66175598 1958 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1959 {
mbed_official 237:f3da66175598 1960 /* Transmit data in 16 Bit mode */
mbed_official 237:f3da66175598 1961 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 1962 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 1963 hspi->TxXferCount--;
mbed_official 237:f3da66175598 1964
mbed_official 237:f3da66175598 1965 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 1966 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 1967 {
mbed_official 237:f3da66175598 1968 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 1969 {
mbed_official 237:f3da66175598 1970 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 1971 }
mbed_official 237:f3da66175598 1972 /* Disable TXE interrupt */
mbed_official 237:f3da66175598 1973 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 237:f3da66175598 1974
mbed_official 237:f3da66175598 1975 if(hspi->RxXferCount == 0)
mbed_official 237:f3da66175598 1976 {
mbed_official 237:f3da66175598 1977 SPI_CloseRxTx_ISR(hspi);
mbed_official 237:f3da66175598 1978 }
mbed_official 237:f3da66175598 1979 }
mbed_official 237:f3da66175598 1980 }
mbed_official 237:f3da66175598 1981
mbed_official 237:f3da66175598 1982 /**
mbed_official 237:f3da66175598 1983 * @brief Manage the CRC receive in Interrupt context
mbed_official 237:f3da66175598 1984 * @param hspi: SPI handle
mbed_official 237:f3da66175598 1985 */
mbed_official 237:f3da66175598 1986 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 1987 {
mbed_official 237:f3da66175598 1988 __IO uint8_t tmpreg;
mbed_official 237:f3da66175598 1989 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 237:f3da66175598 1990 hspi->CRCSize--;
mbed_official 237:f3da66175598 1991
mbed_official 237:f3da66175598 1992 if(hspi->CRCSize == 0)
mbed_official 237:f3da66175598 1993 {
mbed_official 237:f3da66175598 1994 SPI_CloseRx_ISR(hspi);
mbed_official 237:f3da66175598 1995 }
mbed_official 237:f3da66175598 1996 }
mbed_official 237:f3da66175598 1997
mbed_official 237:f3da66175598 1998 /**
mbed_official 237:f3da66175598 1999 * @brief Manage the recieve in Interrupt context
mbed_official 237:f3da66175598 2000 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2001 */
mbed_official 237:f3da66175598 2002 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2003 {
mbed_official 237:f3da66175598 2004 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
mbed_official 237:f3da66175598 2005 hspi->RxXferCount--;
mbed_official 237:f3da66175598 2006
mbed_official 237:f3da66175598 2007 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 2008 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 237:f3da66175598 2009 {
mbed_official 237:f3da66175598 2010 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 2011 }
mbed_official 237:f3da66175598 2012
mbed_official 237:f3da66175598 2013 if(hspi->RxXferCount == 0)
mbed_official 237:f3da66175598 2014 {
mbed_official 237:f3da66175598 2015 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 2016 {
mbed_official 237:f3da66175598 2017 hspi->RxISR = SPI_RxISR_8BITCRC;
mbed_official 237:f3da66175598 2018 return;
mbed_official 237:f3da66175598 2019 }
mbed_official 237:f3da66175598 2020 SPI_CloseRx_ISR(hspi);
mbed_official 237:f3da66175598 2021 }
mbed_official 237:f3da66175598 2022 }
mbed_official 237:f3da66175598 2023
mbed_official 237:f3da66175598 2024 /**
mbed_official 237:f3da66175598 2025 * @brief Manage the CRC 16bit recieve in Interrupt context
mbed_official 237:f3da66175598 2026 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2027 */
mbed_official 237:f3da66175598 2028 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2029 {
mbed_official 237:f3da66175598 2030 __IO uint16_t tmpreg;
mbed_official 237:f3da66175598 2031
mbed_official 237:f3da66175598 2032 tmpreg = hspi->Instance->DR;
mbed_official 237:f3da66175598 2033
mbed_official 237:f3da66175598 2034 /* Disable RXNE and ERR interrupt */
mbed_official 237:f3da66175598 2035 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 237:f3da66175598 2036
mbed_official 237:f3da66175598 2037 SPI_CloseRx_ISR(hspi);
mbed_official 237:f3da66175598 2038 }
mbed_official 237:f3da66175598 2039
mbed_official 237:f3da66175598 2040 /**
mbed_official 237:f3da66175598 2041 * @brief Manage the 16Bit recieve in Interrupt context
mbed_official 237:f3da66175598 2042 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2043 */
mbed_official 237:f3da66175598 2044 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2045 {
mbed_official 237:f3da66175598 2046 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 237:f3da66175598 2047 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 2048 hspi->RxXferCount--;
mbed_official 237:f3da66175598 2049
mbed_official 237:f3da66175598 2050 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 2051 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 237:f3da66175598 2052 {
mbed_official 237:f3da66175598 2053 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 2054 }
mbed_official 237:f3da66175598 2055
mbed_official 237:f3da66175598 2056 if(hspi->RxXferCount == 0)
mbed_official 237:f3da66175598 2057 {
mbed_official 237:f3da66175598 2058 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 2059 {
mbed_official 237:f3da66175598 2060 hspi->RxISR = SPI_RxISR_16BITCRC;
mbed_official 237:f3da66175598 2061 return;
mbed_official 237:f3da66175598 2062 }
mbed_official 237:f3da66175598 2063 SPI_CloseRx_ISR(hspi);
mbed_official 237:f3da66175598 2064 }
mbed_official 237:f3da66175598 2065 }
mbed_official 237:f3da66175598 2066
mbed_official 237:f3da66175598 2067 /**
mbed_official 237:f3da66175598 2068 * @brief Handle the data 8Bit transmit in Interrupt mode
mbed_official 237:f3da66175598 2069 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2070 */
mbed_official 237:f3da66175598 2071 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2072 {
mbed_official 237:f3da66175598 2073 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 237:f3da66175598 2074 hspi->TxXferCount--;
mbed_official 237:f3da66175598 2075
mbed_official 237:f3da66175598 2076 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 2077 {
mbed_official 237:f3da66175598 2078 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 2079 {
mbed_official 237:f3da66175598 2080 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 2081 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 2082 }
mbed_official 237:f3da66175598 2083 SPI_CloseTx_ISR(hspi);
mbed_official 237:f3da66175598 2084 }
mbed_official 237:f3da66175598 2085 }
mbed_official 237:f3da66175598 2086
mbed_official 237:f3da66175598 2087 /**
mbed_official 237:f3da66175598 2088 * @brief Handle the data 16Bit transmit in Interrupt mode
mbed_official 237:f3da66175598 2089 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2090 */
mbed_official 237:f3da66175598 2091 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2092 {
mbed_official 237:f3da66175598 2093 /* Transmit data in 16 Bit mode */
mbed_official 237:f3da66175598 2094 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 237:f3da66175598 2095 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 237:f3da66175598 2096 hspi->TxXferCount--;
mbed_official 237:f3da66175598 2097
mbed_official 237:f3da66175598 2098 if(hspi->TxXferCount == 0)
mbed_official 237:f3da66175598 2099 {
mbed_official 237:f3da66175598 2100 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 2101 {
mbed_official 237:f3da66175598 2102 /* Enable CRC Transmission */
mbed_official 237:f3da66175598 2103 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 237:f3da66175598 2104 }
mbed_official 237:f3da66175598 2105 SPI_CloseTx_ISR(hspi);
mbed_official 237:f3da66175598 2106 }
mbed_official 237:f3da66175598 2107 }
mbed_official 237:f3da66175598 2108
mbed_official 237:f3da66175598 2109 /**
mbed_official 237:f3da66175598 2110 * @brief This function handles SPI Communication Timeout.
mbed_official 237:f3da66175598 2111 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2112 * @param Flag : SPI flag to check
mbed_official 237:f3da66175598 2113 * @param State : flag state to check
mbed_official 237:f3da66175598 2114 * @param Timeout : Timeout duration
mbed_official 237:f3da66175598 2115 * @retval HAL status
mbed_official 237:f3da66175598 2116 */
mbed_official 237:f3da66175598 2117 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official 237:f3da66175598 2118 {
mbed_official 237:f3da66175598 2119 uint32_t tickstart = HAL_GetTick();
mbed_official 237:f3da66175598 2120
mbed_official 237:f3da66175598 2121 while((hspi->Instance->SR & Flag) != State)
mbed_official 237:f3da66175598 2122 {
mbed_official 237:f3da66175598 2123 if(Timeout != HAL_MAX_DELAY)
mbed_official 237:f3da66175598 2124 {
mbed_official 237:f3da66175598 2125 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
mbed_official 237:f3da66175598 2126 {
mbed_official 237:f3da66175598 2127 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 237:f3da66175598 2128 on both master and slave sides in order to resynchronize the master
mbed_official 237:f3da66175598 2129 and slave for their respective CRC calculation */
mbed_official 237:f3da66175598 2130
mbed_official 237:f3da66175598 2131 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 237:f3da66175598 2132 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 237:f3da66175598 2133
mbed_official 237:f3da66175598 2134 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 237:f3da66175598 2135 {
mbed_official 237:f3da66175598 2136 /* Disable SPI peripheral */
mbed_official 237:f3da66175598 2137 __HAL_SPI_DISABLE(hspi);
mbed_official 237:f3da66175598 2138 }
mbed_official 237:f3da66175598 2139
mbed_official 237:f3da66175598 2140 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 2141 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 2142 {
mbed_official 237:f3da66175598 2143 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 2144 }
mbed_official 237:f3da66175598 2145
mbed_official 237:f3da66175598 2146 hspi->State= HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 2147
mbed_official 237:f3da66175598 2148 /* Process Unlocked */
mbed_official 237:f3da66175598 2149 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 2150
mbed_official 237:f3da66175598 2151 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2152 }
mbed_official 237:f3da66175598 2153 }
mbed_official 237:f3da66175598 2154 }
mbed_official 237:f3da66175598 2155
mbed_official 237:f3da66175598 2156 return HAL_OK;
mbed_official 237:f3da66175598 2157 }
mbed_official 237:f3da66175598 2158
mbed_official 237:f3da66175598 2159 /**
mbed_official 237:f3da66175598 2160 * @brief This function handles SPI Communication Timeout.
mbed_official 237:f3da66175598 2161 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2162 * @param Flag: Fifo flag to check
mbed_official 237:f3da66175598 2163 * @param State: Fifo state to check
mbed_official 237:f3da66175598 2164 * @param Timeout : Timeout duration
mbed_official 237:f3da66175598 2165 * @retval HAL status
mbed_official 237:f3da66175598 2166 */
mbed_official 237:f3da66175598 2167 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official 237:f3da66175598 2168 {
mbed_official 237:f3da66175598 2169 __IO uint8_t tmpreg;
mbed_official 237:f3da66175598 2170 uint32_t tickstart = HAL_GetTick();
mbed_official 237:f3da66175598 2171
mbed_official 237:f3da66175598 2172 while((hspi->Instance->SR & Flag) != State)
mbed_official 237:f3da66175598 2173 {
mbed_official 237:f3da66175598 2174 if((Flag == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
mbed_official 237:f3da66175598 2175 {
mbed_official 237:f3da66175598 2176 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 237:f3da66175598 2177 }
mbed_official 237:f3da66175598 2178 if(Timeout != HAL_MAX_DELAY)
mbed_official 237:f3da66175598 2179 {
mbed_official 237:f3da66175598 2180 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
mbed_official 237:f3da66175598 2181 {
mbed_official 237:f3da66175598 2182 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 237:f3da66175598 2183 on both master and slave sides in order to resynchronize the master
mbed_official 237:f3da66175598 2184 and slave for their respective CRC calculation */
mbed_official 237:f3da66175598 2185
mbed_official 237:f3da66175598 2186 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 237:f3da66175598 2187 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 237:f3da66175598 2188
mbed_official 237:f3da66175598 2189 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 237:f3da66175598 2190 {
mbed_official 237:f3da66175598 2191 /* Disable SPI peripheral */
mbed_official 237:f3da66175598 2192 __HAL_SPI_DISABLE(hspi);
mbed_official 237:f3da66175598 2193 }
mbed_official 237:f3da66175598 2194
mbed_official 237:f3da66175598 2195 /* Reset CRC Calculation */
mbed_official 237:f3da66175598 2196 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 237:f3da66175598 2197 {
mbed_official 237:f3da66175598 2198 __HAL_SPI_RESET_CRC(hspi);
mbed_official 237:f3da66175598 2199 }
mbed_official 237:f3da66175598 2200
mbed_official 237:f3da66175598 2201 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 2202
mbed_official 237:f3da66175598 2203 /* Process Unlocked */
mbed_official 237:f3da66175598 2204 __HAL_UNLOCK(hspi);
mbed_official 237:f3da66175598 2205
mbed_official 237:f3da66175598 2206 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2207 }
mbed_official 237:f3da66175598 2208 }
mbed_official 237:f3da66175598 2209 }
mbed_official 237:f3da66175598 2210
mbed_official 237:f3da66175598 2211 return HAL_OK;
mbed_official 237:f3da66175598 2212 }
mbed_official 237:f3da66175598 2213
mbed_official 237:f3da66175598 2214 /**
mbed_official 237:f3da66175598 2215 * @brief This function handles the check of the RX transaction complete.
mbed_official 237:f3da66175598 2216 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2217 * @param Timeout : Timeout duration
mbed_official 237:f3da66175598 2218 */
mbed_official 237:f3da66175598 2219 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 237:f3da66175598 2220 {
mbed_official 237:f3da66175598 2221 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 237:f3da66175598 2222 {
mbed_official 237:f3da66175598 2223 /* Disable SPI peripheral */
mbed_official 237:f3da66175598 2224 __HAL_SPI_DISABLE(hspi);
mbed_official 237:f3da66175598 2225 }
mbed_official 237:f3da66175598 2226 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 2227 {
mbed_official 237:f3da66175598 2228 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 237:f3da66175598 2229 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2230 }
mbed_official 237:f3da66175598 2231 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 2232 {
mbed_official 237:f3da66175598 2233 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 237:f3da66175598 2234 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2235 }
mbed_official 237:f3da66175598 2236
mbed_official 237:f3da66175598 2237 return HAL_OK;
mbed_official 237:f3da66175598 2238 }
mbed_official 237:f3da66175598 2239
mbed_official 237:f3da66175598 2240 /**
mbed_official 237:f3da66175598 2241 * @brief This function handles the check of the RXTX or TX transaction complete.
mbed_official 237:f3da66175598 2242 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2243 * @param Timeout : Timeout duration
mbed_official 237:f3da66175598 2244 */
mbed_official 237:f3da66175598 2245 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 237:f3da66175598 2246 {
mbed_official 237:f3da66175598 2247 /* Procedure to check the transaction complete */
mbed_official 237:f3da66175598 2248 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 2249 {
mbed_official 237:f3da66175598 2250 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 237:f3da66175598 2251 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2252 }
mbed_official 237:f3da66175598 2253 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 2254 {
mbed_official 237:f3da66175598 2255 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 237:f3da66175598 2256 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2257 }
mbed_official 237:f3da66175598 2258 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 237:f3da66175598 2259 {
mbed_official 237:f3da66175598 2260 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 237:f3da66175598 2261 return HAL_TIMEOUT;
mbed_official 237:f3da66175598 2262 }
mbed_official 237:f3da66175598 2263 return HAL_OK;
mbed_official 237:f3da66175598 2264 }
mbed_official 237:f3da66175598 2265
mbed_official 237:f3da66175598 2266 /**
mbed_official 237:f3da66175598 2267 * @brief This function handles the close of the RXTX transaction.
mbed_official 237:f3da66175598 2268 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2269 */
mbed_official 237:f3da66175598 2270 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2271 {
mbed_official 237:f3da66175598 2272 /* Disable ERR interrupt */
mbed_official 237:f3da66175598 2273 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
mbed_official 237:f3da66175598 2274
mbed_official 237:f3da66175598 2275 /* Check the end of the transaction */
mbed_official 237:f3da66175598 2276 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 237:f3da66175598 2277
mbed_official 237:f3da66175598 2278 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 2279
mbed_official 237:f3da66175598 2280 /* Check if CRC error occurred */
mbed_official 237:f3da66175598 2281 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 2282 {
mbed_official 237:f3da66175598 2283 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 2284 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 2285 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 2286 }
mbed_official 237:f3da66175598 2287 else
mbed_official 237:f3da66175598 2288 {
mbed_official 237:f3da66175598 2289 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 2290 {
mbed_official 237:f3da66175598 2291 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 237:f3da66175598 2292 {
mbed_official 237:f3da66175598 2293 HAL_SPI_RxCpltCallback(hspi);
mbed_official 237:f3da66175598 2294 }
mbed_official 237:f3da66175598 2295 else
mbed_official 237:f3da66175598 2296 {
mbed_official 237:f3da66175598 2297 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 237:f3da66175598 2298 }
mbed_official 237:f3da66175598 2299 }
mbed_official 237:f3da66175598 2300 else
mbed_official 237:f3da66175598 2301 {
mbed_official 237:f3da66175598 2302 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 2303 }
mbed_official 237:f3da66175598 2304 }
mbed_official 237:f3da66175598 2305 }
mbed_official 237:f3da66175598 2306
mbed_official 237:f3da66175598 2307 /**
mbed_official 237:f3da66175598 2308 * @brief This function handles the close of the RX transaction.
mbed_official 237:f3da66175598 2309 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2310 */
mbed_official 237:f3da66175598 2311 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2312 {
mbed_official 237:f3da66175598 2313 /* Disable RXNE and ERR interrupt */
mbed_official 237:f3da66175598 2314 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 237:f3da66175598 2315
mbed_official 237:f3da66175598 2316 /* Check the end of the transaction */
mbed_official 237:f3da66175598 2317 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 237:f3da66175598 2318
mbed_official 237:f3da66175598 2319 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 2320
mbed_official 237:f3da66175598 2321 /* Check if CRC error occurred */
mbed_official 237:f3da66175598 2322 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 237:f3da66175598 2323 {
mbed_official 237:f3da66175598 2324 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 237:f3da66175598 2325 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 237:f3da66175598 2326 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 2327 }
mbed_official 237:f3da66175598 2328 else
mbed_official 237:f3da66175598 2329 {
mbed_official 237:f3da66175598 2330 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 2331 {
mbed_official 237:f3da66175598 2332 HAL_SPI_RxCpltCallback(hspi);
mbed_official 237:f3da66175598 2333 }
mbed_official 237:f3da66175598 2334 else
mbed_official 237:f3da66175598 2335 {
mbed_official 237:f3da66175598 2336 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 2337 }
mbed_official 237:f3da66175598 2338 }
mbed_official 237:f3da66175598 2339 }
mbed_official 237:f3da66175598 2340
mbed_official 237:f3da66175598 2341 /**
mbed_official 237:f3da66175598 2342 * @brief This function handles the close of the TX transaction.
mbed_official 237:f3da66175598 2343 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2344 */
mbed_official 237:f3da66175598 2345 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2346 {
mbed_official 237:f3da66175598 2347 /* Disable TXE and ERR interrupt */
mbed_official 237:f3da66175598 2348 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
mbed_official 237:f3da66175598 2349
mbed_official 237:f3da66175598 2350 /* Check the end of the transaction */
mbed_official 237:f3da66175598 2351 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 237:f3da66175598 2352
mbed_official 237:f3da66175598 2353 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 237:f3da66175598 2354 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 237:f3da66175598 2355 {
mbed_official 237:f3da66175598 2356 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 237:f3da66175598 2357 }
mbed_official 237:f3da66175598 2358
mbed_official 237:f3da66175598 2359 hspi->State = HAL_SPI_STATE_READY;
mbed_official 237:f3da66175598 2360 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 237:f3da66175598 2361 {
mbed_official 237:f3da66175598 2362 HAL_SPI_ErrorCallback(hspi);
mbed_official 237:f3da66175598 2363 }
mbed_official 237:f3da66175598 2364 else
mbed_official 237:f3da66175598 2365 {
mbed_official 237:f3da66175598 2366 HAL_SPI_TxCpltCallback(hspi);
mbed_official 237:f3da66175598 2367 }
mbed_official 237:f3da66175598 2368 }
mbed_official 237:f3da66175598 2369
mbed_official 237:f3da66175598 2370 /**
mbed_official 237:f3da66175598 2371 * @brief Tx Transfer completed callbacks
mbed_official 237:f3da66175598 2372 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2373 * @retval None
mbed_official 237:f3da66175598 2374 */
mbed_official 237:f3da66175598 2375 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2376 {
mbed_official 237:f3da66175598 2377 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 237:f3da66175598 2378 the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official 237:f3da66175598 2379 */
mbed_official 237:f3da66175598 2380 }
mbed_official 237:f3da66175598 2381
mbed_official 237:f3da66175598 2382 /**
mbed_official 237:f3da66175598 2383 * @brief Rx Transfer completed callbacks
mbed_official 237:f3da66175598 2384 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2385 * @retval None
mbed_official 237:f3da66175598 2386 */
mbed_official 237:f3da66175598 2387 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2388 {
mbed_official 237:f3da66175598 2389 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 237:f3da66175598 2390 the HAL_SPI_RxCpltCallback could be implenetd in the user file
mbed_official 237:f3da66175598 2391 */
mbed_official 237:f3da66175598 2392 }
mbed_official 237:f3da66175598 2393
mbed_official 237:f3da66175598 2394 /**
mbed_official 237:f3da66175598 2395 * @brief Tx and Rx Transfer completed callbacks
mbed_official 237:f3da66175598 2396 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2397 * @retval None
mbed_official 237:f3da66175598 2398 */
mbed_official 237:f3da66175598 2399 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2400 {
mbed_official 237:f3da66175598 2401 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 237:f3da66175598 2402 the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
mbed_official 237:f3da66175598 2403 */
mbed_official 237:f3da66175598 2404 }
mbed_official 237:f3da66175598 2405
mbed_official 237:f3da66175598 2406 /**
mbed_official 237:f3da66175598 2407 * @brief SPI error callbacks
mbed_official 237:f3da66175598 2408 * @param hspi: SPI handle
mbed_official 237:f3da66175598 2409 * @retval None
mbed_official 237:f3da66175598 2410 */
mbed_official 237:f3da66175598 2411 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2412 {
mbed_official 237:f3da66175598 2413 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 237:f3da66175598 2414 the HAL_SPI_ErrorCallback could be implenetd in the user file
mbed_official 237:f3da66175598 2415 */
mbed_official 237:f3da66175598 2416 }
mbed_official 237:f3da66175598 2417
mbed_official 237:f3da66175598 2418 /**
mbed_official 237:f3da66175598 2419 * @}
mbed_official 237:f3da66175598 2420 */
mbed_official 237:f3da66175598 2421
mbed_official 237:f3da66175598 2422 /** @defgroup HAL_SPI_Group3 Peripheral Control functions
mbed_official 237:f3da66175598 2423 * @brief SPI control functions
mbed_official 237:f3da66175598 2424 *
mbed_official 237:f3da66175598 2425 @verbatim
mbed_official 237:f3da66175598 2426 ===============================================================================
mbed_official 237:f3da66175598 2427 ##### Peripheral Control functions #####
mbed_official 237:f3da66175598 2428 ===============================================================================
mbed_official 237:f3da66175598 2429 [..]
mbed_official 237:f3da66175598 2430 This subsection provides a set of functions allowing to control the SPI.
mbed_official 237:f3da66175598 2431 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
mbed_official 237:f3da66175598 2432 (+) HAL_SPI_Ctl() API can be used to update the spi configuration (only one parameter)
mbed_official 237:f3da66175598 2433 without calling the HAL_SPI_Init() API
mbed_official 237:f3da66175598 2434 @endverbatim
mbed_official 237:f3da66175598 2435 * @{
mbed_official 237:f3da66175598 2436 */
mbed_official 237:f3da66175598 2437
mbed_official 237:f3da66175598 2438 /**
mbed_official 237:f3da66175598 2439 * @brief Return the SPI state
mbed_official 237:f3da66175598 2440 * @param hspi : SPI handle
mbed_official 237:f3da66175598 2441 * @retval HAL state
mbed_official 237:f3da66175598 2442 */
mbed_official 237:f3da66175598 2443 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official 237:f3da66175598 2444 {
mbed_official 237:f3da66175598 2445 return hspi->State;
mbed_official 237:f3da66175598 2446 }
mbed_official 237:f3da66175598 2447 /**
mbed_official 237:f3da66175598 2448 * @}
mbed_official 237:f3da66175598 2449 */
mbed_official 237:f3da66175598 2450
mbed_official 237:f3da66175598 2451 /**
mbed_official 237:f3da66175598 2452 * @}
mbed_official 237:f3da66175598 2453 */
mbed_official 237:f3da66175598 2454
mbed_official 237:f3da66175598 2455
mbed_official 237:f3da66175598 2456 #endif /* HAL_SPI_MODULE_ENABLED */
mbed_official 237:f3da66175598 2457 /**
mbed_official 237:f3da66175598 2458 * @}
mbed_official 237:f3da66175598 2459 */
mbed_official 237:f3da66175598 2460
mbed_official 237:f3da66175598 2461 /**
mbed_official 237:f3da66175598 2462 * @}
mbed_official 237:f3da66175598 2463 */
mbed_official 237:f3da66175598 2464
mbed_official 237:f3da66175598 2465 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/