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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_spi.h@296:ec1b66a3d094, 2014-08-21 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Aug 21 15:00:08 2014 +0100
- Revision:
- 296:ec1b66a3d094
- Parent:
- targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_spi.h@242:7074e42da0b2
Synchronized with git revision bbc120c4786e99dfa586e7a13f8638064f1e5938
Full URL: https://github.com/mbedmicro/mbed/commit/bbc120c4786e99dfa586e7a13f8638064f1e5938/
DISCO_F407VG - add USBDevice support and a variant - ARCH_MAX
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 133:d4dda5c437f0 | 1 | /** |
| mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_spi.h |
| mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
| mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
| mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
| mbed_official | 133:d4dda5c437f0 | 7 | * @brief Header file of SPI HAL module. |
| mbed_official | 133:d4dda5c437f0 | 8 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 9 | * @attention |
| mbed_official | 133:d4dda5c437f0 | 10 | * |
| mbed_official | 133:d4dda5c437f0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 133:d4dda5c437f0 | 12 | * |
| mbed_official | 133:d4dda5c437f0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 133:d4dda5c437f0 | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 133:d4dda5c437f0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 133:d4dda5c437f0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 133:d4dda5c437f0 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 133:d4dda5c437f0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 133:d4dda5c437f0 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 133:d4dda5c437f0 | 22 | * without specific prior written permission. |
| mbed_official | 133:d4dda5c437f0 | 23 | * |
| mbed_official | 133:d4dda5c437f0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 133:d4dda5c437f0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 133:d4dda5c437f0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 133:d4dda5c437f0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 133:d4dda5c437f0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 133:d4dda5c437f0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 133:d4dda5c437f0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 133:d4dda5c437f0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 133:d4dda5c437f0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 133:d4dda5c437f0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 133:d4dda5c437f0 | 34 | * |
| mbed_official | 133:d4dda5c437f0 | 35 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 36 | */ |
| mbed_official | 133:d4dda5c437f0 | 37 | |
| mbed_official | 133:d4dda5c437f0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 39 | #ifndef __STM32F4xx_HAL_SPI_H |
| mbed_official | 133:d4dda5c437f0 | 40 | #define __STM32F4xx_HAL_SPI_H |
| mbed_official | 133:d4dda5c437f0 | 41 | |
| mbed_official | 133:d4dda5c437f0 | 42 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 43 | extern "C" { |
| mbed_official | 133:d4dda5c437f0 | 44 | #endif |
| mbed_official | 133:d4dda5c437f0 | 45 | |
| mbed_official | 133:d4dda5c437f0 | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 47 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 133:d4dda5c437f0 | 48 | |
| mbed_official | 133:d4dda5c437f0 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 133:d4dda5c437f0 | 50 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 51 | */ |
| mbed_official | 133:d4dda5c437f0 | 52 | |
| mbed_official | 133:d4dda5c437f0 | 53 | /** @addtogroup SPI |
| mbed_official | 133:d4dda5c437f0 | 54 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 55 | */ |
| mbed_official | 133:d4dda5c437f0 | 56 | |
| mbed_official | 133:d4dda5c437f0 | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 58 | |
| mbed_official | 133:d4dda5c437f0 | 59 | /** |
| mbed_official | 133:d4dda5c437f0 | 60 | * @brief SPI Configuration Structure definition |
| mbed_official | 133:d4dda5c437f0 | 61 | */ |
| mbed_official | 133:d4dda5c437f0 | 62 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 63 | { |
| mbed_official | 133:d4dda5c437f0 | 64 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| mbed_official | 133:d4dda5c437f0 | 65 | This parameter can be a value of @ref SPI_mode */ |
| mbed_official | 133:d4dda5c437f0 | 66 | |
| mbed_official | 133:d4dda5c437f0 | 67 | uint32_t Direction; /*!< Specifies the SPI Directional mode state. |
| mbed_official | 133:d4dda5c437f0 | 68 | This parameter can be a value of @ref SPI_Direction_mode */ |
| mbed_official | 133:d4dda5c437f0 | 69 | |
| mbed_official | 133:d4dda5c437f0 | 70 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| mbed_official | 133:d4dda5c437f0 | 71 | This parameter can be a value of @ref SPI_data_size */ |
| mbed_official | 133:d4dda5c437f0 | 72 | |
| mbed_official | 133:d4dda5c437f0 | 73 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| mbed_official | 133:d4dda5c437f0 | 74 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 75 | |
| mbed_official | 133:d4dda5c437f0 | 76 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| mbed_official | 133:d4dda5c437f0 | 77 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| mbed_official | 133:d4dda5c437f0 | 78 | |
| mbed_official | 133:d4dda5c437f0 | 79 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| mbed_official | 133:d4dda5c437f0 | 80 | hardware (NSS pin) or by software using the SSI bit. |
| mbed_official | 133:d4dda5c437f0 | 81 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| mbed_official | 133:d4dda5c437f0 | 82 | |
| mbed_official | 133:d4dda5c437f0 | 83 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| mbed_official | 133:d4dda5c437f0 | 84 | used to configure the transmit and receive SCK clock. |
| mbed_official | 133:d4dda5c437f0 | 85 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| mbed_official | 133:d4dda5c437f0 | 86 | @note The communication clock is derived from the master |
| mbed_official | 133:d4dda5c437f0 | 87 | clock. The slave clock does not need to be set */ |
| mbed_official | 133:d4dda5c437f0 | 88 | |
| mbed_official | 133:d4dda5c437f0 | 89 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| mbed_official | 133:d4dda5c437f0 | 90 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| mbed_official | 133:d4dda5c437f0 | 91 | |
| mbed_official | 133:d4dda5c437f0 | 92 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| mbed_official | 133:d4dda5c437f0 | 93 | This parameter can be a value of @ref SPI_TI_mode */ |
| mbed_official | 133:d4dda5c437f0 | 94 | |
| mbed_official | 133:d4dda5c437f0 | 95 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| mbed_official | 133:d4dda5c437f0 | 96 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| mbed_official | 133:d4dda5c437f0 | 97 | |
| mbed_official | 133:d4dda5c437f0 | 98 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| mbed_official | 133:d4dda5c437f0 | 99 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
| mbed_official | 133:d4dda5c437f0 | 100 | |
| mbed_official | 133:d4dda5c437f0 | 101 | }SPI_InitTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 102 | |
| mbed_official | 133:d4dda5c437f0 | 103 | /** |
| mbed_official | 133:d4dda5c437f0 | 104 | * @brief HAL SPI State structure definition |
| mbed_official | 133:d4dda5c437f0 | 105 | */ |
| mbed_official | 133:d4dda5c437f0 | 106 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 107 | { |
| mbed_official | 133:d4dda5c437f0 | 108 | HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ |
| mbed_official | 133:d4dda5c437f0 | 109 | HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ |
| mbed_official | 133:d4dda5c437f0 | 110 | HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 111 | HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 112 | HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 113 | HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 114 | HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ |
| mbed_official | 133:d4dda5c437f0 | 115 | |
| mbed_official | 133:d4dda5c437f0 | 116 | }HAL_SPI_StateTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 117 | |
| mbed_official | 133:d4dda5c437f0 | 118 | /** |
| mbed_official | 133:d4dda5c437f0 | 119 | * @brief HAL SPI Error Code structure definition |
| mbed_official | 133:d4dda5c437f0 | 120 | */ |
| mbed_official | 133:d4dda5c437f0 | 121 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 122 | { |
| mbed_official | 133:d4dda5c437f0 | 123 | HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ |
| mbed_official | 133:d4dda5c437f0 | 124 | HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ |
| mbed_official | 133:d4dda5c437f0 | 125 | HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ |
| mbed_official | 133:d4dda5c437f0 | 126 | HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ |
| mbed_official | 133:d4dda5c437f0 | 127 | HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ |
| mbed_official | 133:d4dda5c437f0 | 128 | HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ |
| mbed_official | 133:d4dda5c437f0 | 129 | HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */ |
| mbed_official | 133:d4dda5c437f0 | 130 | |
| mbed_official | 133:d4dda5c437f0 | 131 | }HAL_SPI_ErrorTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 132 | |
| mbed_official | 133:d4dda5c437f0 | 133 | /** |
| mbed_official | 133:d4dda5c437f0 | 134 | * @brief SPI handle Structure definition |
| mbed_official | 133:d4dda5c437f0 | 135 | */ |
| mbed_official | 133:d4dda5c437f0 | 136 | typedef struct __SPI_HandleTypeDef |
| mbed_official | 133:d4dda5c437f0 | 137 | { |
| mbed_official | 133:d4dda5c437f0 | 138 | SPI_TypeDef *Instance; /* SPI registers base address */ |
| mbed_official | 133:d4dda5c437f0 | 139 | |
| mbed_official | 133:d4dda5c437f0 | 140 | SPI_InitTypeDef Init; /* SPI communication parameters */ |
| mbed_official | 133:d4dda5c437f0 | 141 | |
| mbed_official | 133:d4dda5c437f0 | 142 | uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ |
| mbed_official | 133:d4dda5c437f0 | 143 | |
| mbed_official | 133:d4dda5c437f0 | 144 | uint16_t TxXferSize; /* SPI Tx transfer size */ |
| mbed_official | 133:d4dda5c437f0 | 145 | |
| mbed_official | 133:d4dda5c437f0 | 146 | uint16_t TxXferCount; /* SPI Tx Transfer Counter */ |
| mbed_official | 133:d4dda5c437f0 | 147 | |
| mbed_official | 133:d4dda5c437f0 | 148 | uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ |
| mbed_official | 133:d4dda5c437f0 | 149 | |
| mbed_official | 133:d4dda5c437f0 | 150 | uint16_t RxXferSize; /* SPI Rx transfer size */ |
| mbed_official | 133:d4dda5c437f0 | 151 | |
| mbed_official | 133:d4dda5c437f0 | 152 | uint16_t RxXferCount; /* SPI Rx Transfer Counter */ |
| mbed_official | 133:d4dda5c437f0 | 153 | |
| mbed_official | 133:d4dda5c437f0 | 154 | DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */ |
| mbed_official | 133:d4dda5c437f0 | 155 | |
| mbed_official | 133:d4dda5c437f0 | 156 | DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */ |
| mbed_official | 133:d4dda5c437f0 | 157 | |
| mbed_official | 133:d4dda5c437f0 | 158 | void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */ |
| mbed_official | 133:d4dda5c437f0 | 159 | |
| mbed_official | 133:d4dda5c437f0 | 160 | void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */ |
| mbed_official | 133:d4dda5c437f0 | 161 | |
| mbed_official | 133:d4dda5c437f0 | 162 | HAL_LockTypeDef Lock; /* SPI locking object */ |
| mbed_official | 133:d4dda5c437f0 | 163 | |
| mbed_official | 133:d4dda5c437f0 | 164 | __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ |
| mbed_official | 133:d4dda5c437f0 | 165 | |
| mbed_official | 133:d4dda5c437f0 | 166 | __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ |
| mbed_official | 133:d4dda5c437f0 | 167 | |
| mbed_official | 133:d4dda5c437f0 | 168 | }SPI_HandleTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 169 | |
| mbed_official | 133:d4dda5c437f0 | 170 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 171 | |
| mbed_official | 133:d4dda5c437f0 | 172 | /** @defgroup SPI_Exported_Constants |
| mbed_official | 133:d4dda5c437f0 | 173 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 174 | */ |
| mbed_official | 133:d4dda5c437f0 | 175 | |
| mbed_official | 133:d4dda5c437f0 | 176 | /** @defgroup SPI_mode |
| mbed_official | 133:d4dda5c437f0 | 177 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 178 | */ |
| mbed_official | 133:d4dda5c437f0 | 179 | #define SPI_MODE_SLAVE ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 180 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| mbed_official | 133:d4dda5c437f0 | 181 | |
| mbed_official | 133:d4dda5c437f0 | 182 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ |
| mbed_official | 133:d4dda5c437f0 | 183 | ((MODE) == SPI_MODE_MASTER)) |
| mbed_official | 133:d4dda5c437f0 | 184 | /** |
| mbed_official | 133:d4dda5c437f0 | 185 | * @} |
| mbed_official | 133:d4dda5c437f0 | 186 | */ |
| mbed_official | 133:d4dda5c437f0 | 187 | |
| mbed_official | 133:d4dda5c437f0 | 188 | /** @defgroup SPI_Direction_mode |
| mbed_official | 133:d4dda5c437f0 | 189 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 190 | */ |
| mbed_official | 133:d4dda5c437f0 | 191 | #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 192 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| mbed_official | 133:d4dda5c437f0 | 193 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| mbed_official | 133:d4dda5c437f0 | 194 | |
| mbed_official | 133:d4dda5c437f0 | 195 | #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| mbed_official | 133:d4dda5c437f0 | 196 | ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| mbed_official | 133:d4dda5c437f0 | 197 | ((MODE) == SPI_DIRECTION_1LINE)) |
| mbed_official | 133:d4dda5c437f0 | 198 | |
| mbed_official | 133:d4dda5c437f0 | 199 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| mbed_official | 133:d4dda5c437f0 | 200 | ((MODE) == SPI_DIRECTION_1LINE)) |
| mbed_official | 133:d4dda5c437f0 | 201 | |
| mbed_official | 133:d4dda5c437f0 | 202 | #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) |
| mbed_official | 133:d4dda5c437f0 | 203 | |
| mbed_official | 133:d4dda5c437f0 | 204 | /** |
| mbed_official | 133:d4dda5c437f0 | 205 | * @} |
| mbed_official | 133:d4dda5c437f0 | 206 | */ |
| mbed_official | 133:d4dda5c437f0 | 207 | |
| mbed_official | 133:d4dda5c437f0 | 208 | /** @defgroup SPI_data_size |
| mbed_official | 133:d4dda5c437f0 | 209 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 210 | */ |
| mbed_official | 133:d4dda5c437f0 | 211 | #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 212 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
| mbed_official | 133:d4dda5c437f0 | 213 | |
| mbed_official | 133:d4dda5c437f0 | 214 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ |
| mbed_official | 133:d4dda5c437f0 | 215 | ((DATASIZE) == SPI_DATASIZE_8BIT)) |
| mbed_official | 133:d4dda5c437f0 | 216 | /** |
| mbed_official | 133:d4dda5c437f0 | 217 | * @} |
| mbed_official | 133:d4dda5c437f0 | 218 | */ |
| mbed_official | 133:d4dda5c437f0 | 219 | |
| mbed_official | 133:d4dda5c437f0 | 220 | /** @defgroup SPI_Clock_Polarity |
| mbed_official | 133:d4dda5c437f0 | 221 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 222 | */ |
| mbed_official | 133:d4dda5c437f0 | 223 | #define SPI_POLARITY_LOW ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 224 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| mbed_official | 133:d4dda5c437f0 | 225 | |
| mbed_official | 133:d4dda5c437f0 | 226 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ |
| mbed_official | 133:d4dda5c437f0 | 227 | ((CPOL) == SPI_POLARITY_HIGH)) |
| mbed_official | 133:d4dda5c437f0 | 228 | /** |
| mbed_official | 133:d4dda5c437f0 | 229 | * @} |
| mbed_official | 133:d4dda5c437f0 | 230 | */ |
| mbed_official | 133:d4dda5c437f0 | 231 | |
| mbed_official | 133:d4dda5c437f0 | 232 | /** @defgroup SPI_Clock_Phase |
| mbed_official | 133:d4dda5c437f0 | 233 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 234 | */ |
| mbed_official | 133:d4dda5c437f0 | 235 | #define SPI_PHASE_1EDGE ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 236 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| mbed_official | 133:d4dda5c437f0 | 237 | |
| mbed_official | 133:d4dda5c437f0 | 238 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ |
| mbed_official | 133:d4dda5c437f0 | 239 | ((CPHA) == SPI_PHASE_2EDGE)) |
| mbed_official | 133:d4dda5c437f0 | 240 | /** |
| mbed_official | 133:d4dda5c437f0 | 241 | * @} |
| mbed_official | 133:d4dda5c437f0 | 242 | */ |
| mbed_official | 133:d4dda5c437f0 | 243 | |
| mbed_official | 133:d4dda5c437f0 | 244 | /** @defgroup SPI_Slave_Select_management |
| mbed_official | 133:d4dda5c437f0 | 245 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 246 | */ |
| mbed_official | 133:d4dda5c437f0 | 247 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| mbed_official | 133:d4dda5c437f0 | 248 | #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 249 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) |
| mbed_official | 133:d4dda5c437f0 | 250 | |
| mbed_official | 133:d4dda5c437f0 | 251 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ |
| mbed_official | 133:d4dda5c437f0 | 252 | ((NSS) == SPI_NSS_HARD_INPUT) || \ |
| mbed_official | 133:d4dda5c437f0 | 253 | ((NSS) == SPI_NSS_HARD_OUTPUT)) |
| mbed_official | 133:d4dda5c437f0 | 254 | /** |
| mbed_official | 133:d4dda5c437f0 | 255 | * @} |
| mbed_official | 133:d4dda5c437f0 | 256 | */ |
| mbed_official | 133:d4dda5c437f0 | 257 | |
| mbed_official | 133:d4dda5c437f0 | 258 | /** @defgroup SPI_BaudRate_Prescaler |
| mbed_official | 133:d4dda5c437f0 | 259 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 260 | */ |
| mbed_official | 133:d4dda5c437f0 | 261 | #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 262 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) |
| mbed_official | 133:d4dda5c437f0 | 263 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) |
| mbed_official | 133:d4dda5c437f0 | 264 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) |
| mbed_official | 133:d4dda5c437f0 | 265 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) |
| mbed_official | 133:d4dda5c437f0 | 266 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) |
| mbed_official | 133:d4dda5c437f0 | 267 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) |
| mbed_official | 133:d4dda5c437f0 | 268 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) |
| mbed_official | 133:d4dda5c437f0 | 269 | |
| mbed_official | 133:d4dda5c437f0 | 270 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ |
| mbed_official | 133:d4dda5c437f0 | 271 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ |
| mbed_official | 133:d4dda5c437f0 | 272 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ |
| mbed_official | 133:d4dda5c437f0 | 273 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ |
| mbed_official | 133:d4dda5c437f0 | 274 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ |
| mbed_official | 133:d4dda5c437f0 | 275 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ |
| mbed_official | 133:d4dda5c437f0 | 276 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ |
| mbed_official | 133:d4dda5c437f0 | 277 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) |
| mbed_official | 133:d4dda5c437f0 | 278 | /** |
| mbed_official | 133:d4dda5c437f0 | 279 | * @} |
| mbed_official | 133:d4dda5c437f0 | 280 | */ |
| mbed_official | 133:d4dda5c437f0 | 281 | |
| mbed_official | 133:d4dda5c437f0 | 282 | /** @defgroup SPI_MSB_LSB_transmission |
| mbed_official | 133:d4dda5c437f0 | 283 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 284 | */ |
| mbed_official | 133:d4dda5c437f0 | 285 | #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 286 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| mbed_official | 133:d4dda5c437f0 | 287 | |
| mbed_official | 133:d4dda5c437f0 | 288 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ |
| mbed_official | 133:d4dda5c437f0 | 289 | ((BIT) == SPI_FIRSTBIT_LSB)) |
| mbed_official | 133:d4dda5c437f0 | 290 | /** |
| mbed_official | 133:d4dda5c437f0 | 291 | * @} |
| mbed_official | 133:d4dda5c437f0 | 292 | */ |
| mbed_official | 133:d4dda5c437f0 | 293 | |
| mbed_official | 133:d4dda5c437f0 | 294 | /** @defgroup SPI_TI_mode |
| mbed_official | 133:d4dda5c437f0 | 295 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 296 | */ |
| mbed_official | 133:d4dda5c437f0 | 297 | #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 298 | #define SPI_TIMODE_ENABLED SPI_CR2_FRF |
| mbed_official | 133:d4dda5c437f0 | 299 | |
| mbed_official | 133:d4dda5c437f0 | 300 | #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ |
| mbed_official | 133:d4dda5c437f0 | 301 | ((MODE) == SPI_TIMODE_ENABLED)) |
| mbed_official | 133:d4dda5c437f0 | 302 | /** |
| mbed_official | 133:d4dda5c437f0 | 303 | * @} |
| mbed_official | 133:d4dda5c437f0 | 304 | */ |
| mbed_official | 133:d4dda5c437f0 | 305 | |
| mbed_official | 133:d4dda5c437f0 | 306 | /** @defgroup SPI_CRC_Calculation |
| mbed_official | 133:d4dda5c437f0 | 307 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 308 | */ |
| mbed_official | 133:d4dda5c437f0 | 309 | #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 310 | #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN |
| mbed_official | 133:d4dda5c437f0 | 311 | |
| mbed_official | 133:d4dda5c437f0 | 312 | #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ |
| mbed_official | 133:d4dda5c437f0 | 313 | ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) |
| mbed_official | 133:d4dda5c437f0 | 314 | /** |
| mbed_official | 133:d4dda5c437f0 | 315 | * @} |
| mbed_official | 133:d4dda5c437f0 | 316 | */ |
| mbed_official | 133:d4dda5c437f0 | 317 | |
| mbed_official | 133:d4dda5c437f0 | 318 | /** @defgroup SPI_Interrupt_configuration_definition |
| mbed_official | 133:d4dda5c437f0 | 319 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 320 | */ |
| mbed_official | 133:d4dda5c437f0 | 321 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| mbed_official | 133:d4dda5c437f0 | 322 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| mbed_official | 133:d4dda5c437f0 | 323 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| mbed_official | 133:d4dda5c437f0 | 324 | /** |
| mbed_official | 133:d4dda5c437f0 | 325 | * @} |
| mbed_official | 133:d4dda5c437f0 | 326 | */ |
| mbed_official | 133:d4dda5c437f0 | 327 | |
| mbed_official | 133:d4dda5c437f0 | 328 | /** @defgroup SPI_Flag_definition |
| mbed_official | 133:d4dda5c437f0 | 329 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 330 | */ |
| mbed_official | 133:d4dda5c437f0 | 331 | #define SPI_FLAG_RXNE SPI_SR_RXNE |
| mbed_official | 133:d4dda5c437f0 | 332 | #define SPI_FLAG_TXE SPI_SR_TXE |
| mbed_official | 133:d4dda5c437f0 | 333 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR |
| mbed_official | 133:d4dda5c437f0 | 334 | #define SPI_FLAG_MODF SPI_SR_MODF |
| mbed_official | 133:d4dda5c437f0 | 335 | #define SPI_FLAG_OVR SPI_SR_OVR |
| mbed_official | 133:d4dda5c437f0 | 336 | #define SPI_FLAG_BSY SPI_SR_BSY |
| mbed_official | 133:d4dda5c437f0 | 337 | #define SPI_FLAG_FRE SPI_SR_FRE |
| mbed_official | 133:d4dda5c437f0 | 338 | |
| mbed_official | 133:d4dda5c437f0 | 339 | /** |
| mbed_official | 133:d4dda5c437f0 | 340 | * @} |
| mbed_official | 133:d4dda5c437f0 | 341 | */ |
| mbed_official | 133:d4dda5c437f0 | 342 | |
| mbed_official | 133:d4dda5c437f0 | 343 | /** |
| mbed_official | 133:d4dda5c437f0 | 344 | * @} |
| mbed_official | 133:d4dda5c437f0 | 345 | */ |
| mbed_official | 133:d4dda5c437f0 | 346 | |
| mbed_official | 133:d4dda5c437f0 | 347 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 348 | |
| mbed_official | 242:7074e42da0b2 | 349 | /** @brief Reset SPI handle state |
| mbed_official | 242:7074e42da0b2 | 350 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 242:7074e42da0b2 | 351 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 242:7074e42da0b2 | 352 | * @retval None |
| mbed_official | 242:7074e42da0b2 | 353 | */ |
| mbed_official | 242:7074e42da0b2 | 354 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| mbed_official | 242:7074e42da0b2 | 355 | |
| mbed_official | 133:d4dda5c437f0 | 356 | /** @brief Enable or disable the specified SPI interrupts. |
| mbed_official | 133:d4dda5c437f0 | 357 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 358 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 359 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| mbed_official | 133:d4dda5c437f0 | 360 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 361 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 362 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 363 | * @arg SPI_IT_ERR: Error interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 364 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 365 | */ |
| mbed_official | 133:d4dda5c437f0 | 366 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 367 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) |
| mbed_official | 133:d4dda5c437f0 | 368 | |
| mbed_official | 133:d4dda5c437f0 | 369 | /** @brief Check if the specified SPI interrupt source is enabled or disabled. |
| mbed_official | 133:d4dda5c437f0 | 370 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 371 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 372 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
| mbed_official | 133:d4dda5c437f0 | 373 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 374 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 375 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 376 | * @arg SPI_IT_ERR: Error interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 377 | * @retval The new state of __IT__ (TRUE or FALSE). |
| mbed_official | 133:d4dda5c437f0 | 378 | */ |
| mbed_official | 133:d4dda5c437f0 | 379 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| mbed_official | 133:d4dda5c437f0 | 380 | |
| mbed_official | 133:d4dda5c437f0 | 381 | /** @brief Check whether the specified SPI flag is set or not. |
| mbed_official | 133:d4dda5c437f0 | 382 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 383 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 384 | * @param __FLAG__: specifies the flag to check. |
| mbed_official | 133:d4dda5c437f0 | 385 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 386 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| mbed_official | 133:d4dda5c437f0 | 387 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| mbed_official | 133:d4dda5c437f0 | 388 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| mbed_official | 133:d4dda5c437f0 | 389 | * @arg SPI_FLAG_MODF: Mode fault flag |
| mbed_official | 133:d4dda5c437f0 | 390 | * @arg SPI_FLAG_OVR: Overrun flag |
| mbed_official | 133:d4dda5c437f0 | 391 | * @arg SPI_FLAG_BSY: Busy flag |
| mbed_official | 133:d4dda5c437f0 | 392 | * @arg SPI_FLAG_FRE: Frame format error flag |
| mbed_official | 133:d4dda5c437f0 | 393 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| mbed_official | 133:d4dda5c437f0 | 394 | */ |
| mbed_official | 133:d4dda5c437f0 | 395 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| mbed_official | 133:d4dda5c437f0 | 396 | |
| mbed_official | 133:d4dda5c437f0 | 397 | /** @brief Clear the SPI CRCERR pending flag. |
| mbed_official | 133:d4dda5c437f0 | 398 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 399 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 400 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 401 | */ |
| mbed_official | 133:d4dda5c437f0 | 402 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR)) |
| mbed_official | 133:d4dda5c437f0 | 403 | |
| mbed_official | 133:d4dda5c437f0 | 404 | /** @brief Clear the SPI MODF pending flag. |
| mbed_official | 133:d4dda5c437f0 | 405 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 406 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 407 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 408 | */ |
| mbed_official | 133:d4dda5c437f0 | 409 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ |
| mbed_official | 133:d4dda5c437f0 | 410 | (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0) |
| mbed_official | 133:d4dda5c437f0 | 411 | |
| mbed_official | 133:d4dda5c437f0 | 412 | /** @brief Clear the SPI OVR pending flag. |
| mbed_official | 133:d4dda5c437f0 | 413 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 414 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 415 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 416 | */ |
| mbed_official | 133:d4dda5c437f0 | 417 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ |
| mbed_official | 133:d4dda5c437f0 | 418 | (__HANDLE__)->Instance->SR;}while(0) |
| mbed_official | 133:d4dda5c437f0 | 419 | |
| mbed_official | 133:d4dda5c437f0 | 420 | /** @brief Clear the SPI FRE pending flag. |
| mbed_official | 133:d4dda5c437f0 | 421 | * @param __HANDLE__: specifies the SPI handle. |
| mbed_official | 133:d4dda5c437f0 | 422 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 133:d4dda5c437f0 | 423 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 424 | */ |
| mbed_official | 133:d4dda5c437f0 | 425 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) |
| mbed_official | 133:d4dda5c437f0 | 426 | |
| mbed_official | 133:d4dda5c437f0 | 427 | #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) |
| mbed_official | 133:d4dda5c437f0 | 428 | #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE) |
| mbed_official | 133:d4dda5c437f0 | 429 | |
| mbed_official | 133:d4dda5c437f0 | 430 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) |
| mbed_official | 133:d4dda5c437f0 | 431 | |
| mbed_official | 133:d4dda5c437f0 | 432 | #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) |
| mbed_official | 133:d4dda5c437f0 | 433 | |
| mbed_official | 133:d4dda5c437f0 | 434 | #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE) |
| mbed_official | 133:d4dda5c437f0 | 435 | |
| mbed_official | 133:d4dda5c437f0 | 436 | #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\ |
| mbed_official | 133:d4dda5c437f0 | 437 | (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) |
| mbed_official | 133:d4dda5c437f0 | 438 | |
| mbed_official | 133:d4dda5c437f0 | 439 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 440 | |
| mbed_official | 133:d4dda5c437f0 | 441 | /* Initialization/de-initialization functions **********************************/ |
| mbed_official | 133:d4dda5c437f0 | 442 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 443 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 444 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 445 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 446 | |
| mbed_official | 133:d4dda5c437f0 | 447 | /* I/O operation functions *****************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 448 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 449 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 450 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 451 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 452 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 453 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 454 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 455 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 456 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 457 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 458 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 459 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 460 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 461 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 462 | |
| mbed_official | 133:d4dda5c437f0 | 463 | /* Peripheral State and Control functions **************************************/ |
| mbed_official | 133:d4dda5c437f0 | 464 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 465 | HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| mbed_official | 133:d4dda5c437f0 | 466 | |
| mbed_official | 133:d4dda5c437f0 | 467 | /** |
| mbed_official | 133:d4dda5c437f0 | 468 | * @} |
| mbed_official | 133:d4dda5c437f0 | 469 | */ |
| mbed_official | 133:d4dda5c437f0 | 470 | |
| mbed_official | 133:d4dda5c437f0 | 471 | /** |
| mbed_official | 133:d4dda5c437f0 | 472 | * @} |
| mbed_official | 133:d4dda5c437f0 | 473 | */ |
| mbed_official | 133:d4dda5c437f0 | 474 | |
| mbed_official | 133:d4dda5c437f0 | 475 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 476 | } |
| mbed_official | 133:d4dda5c437f0 | 477 | #endif |
| mbed_official | 133:d4dda5c437f0 | 478 | |
| mbed_official | 133:d4dda5c437f0 | 479 | #endif /* __STM32F4xx_HAL_SPI_H */ |
| mbed_official | 133:d4dda5c437f0 | 480 | |
| mbed_official | 133:d4dda5c437f0 | 481 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |