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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_eth.h@296:ec1b66a3d094, 2014-08-21 (annotated)

Committer:: mbed_official
Date:: Thu Aug 21 15:00:08 2014 +0100
Revision:: 296:ec1b66a3d094
Parent:: targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.h@242:7074e42da0b2

Synchronized with git revision bbc120c4786e99dfa586e7a13f8638064f1e5938

Full URL: https://github.com/mbedmicro/mbed/commit/bbc120c4786e99dfa586e7a13f8638064f1e5938/

DISCO_F407VG - add USBDevice support and a variant - ARCH_MAX

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_hal_eth.h
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	242:7074e42da0b2	5	* @version V1.1.0RC2
mbed_official	242:7074e42da0b2	6	* @date 14-May-2014
mbed_official	133:d4dda5c437f0	7	* @brief Header file of ETH HAL module.
mbed_official	133:d4dda5c437f0	8	******************************************************************************
mbed_official	133:d4dda5c437f0	9	* @attention
mbed_official	133:d4dda5c437f0	10	*
mbed_official	133:d4dda5c437f0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	12	*
mbed_official	133:d4dda5c437f0	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	14	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	16	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	19	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	21	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	22	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	23	*
mbed_official	133:d4dda5c437f0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	34	*
mbed_official	133:d4dda5c437f0	35	******************************************************************************
mbed_official	133:d4dda5c437f0	36	*/
mbed_official	133:d4dda5c437f0	37
mbed_official	133:d4dda5c437f0	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	133:d4dda5c437f0	39	#ifndef __STM32F4xx_HAL_ETH_H
mbed_official	133:d4dda5c437f0	40	#define __STM32F4xx_HAL_ETH_H
mbed_official	133:d4dda5c437f0	41
mbed_official	133:d4dda5c437f0	42	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	43	extern "C" {
mbed_official	133:d4dda5c437f0	44	#endif
mbed_official	133:d4dda5c437f0	45
mbed_official	133:d4dda5c437f0	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	47	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	48	#include "stm32f4xx_hal_def.h"
mbed_official	133:d4dda5c437f0	49
mbed_official	133:d4dda5c437f0	50	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	133:d4dda5c437f0	51	* @{
mbed_official	133:d4dda5c437f0	52	*/
mbed_official	133:d4dda5c437f0	53
mbed_official	133:d4dda5c437f0	54	/** @addtogroup ETH
mbed_official	133:d4dda5c437f0	55	* @{
mbed_official	133:d4dda5c437f0	56	*/
mbed_official	133:d4dda5c437f0	57
mbed_official	133:d4dda5c437f0	58	/* Exported types ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	59
mbed_official	133:d4dda5c437f0	60	/**
mbed_official	133:d4dda5c437f0	61	* @brief HAL State structures definition
mbed_official	133:d4dda5c437f0	62	*/
mbed_official	133:d4dda5c437f0	63	typedef enum
mbed_official	133:d4dda5c437f0	64	{
mbed_official	133:d4dda5c437f0	65	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
mbed_official	133:d4dda5c437f0	66	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	133:d4dda5c437f0	67	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
mbed_official	133:d4dda5c437f0	68	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
mbed_official	133:d4dda5c437f0	69	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
mbed_official	133:d4dda5c437f0	70	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
mbed_official	133:d4dda5c437f0	71	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
mbed_official	133:d4dda5c437f0	72	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
mbed_official	133:d4dda5c437f0	73	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	133:d4dda5c437f0	74	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	133:d4dda5c437f0	75	}HAL_ETH_StateTypeDef;
mbed_official	133:d4dda5c437f0	76
mbed_official	133:d4dda5c437f0	77	/**
mbed_official	133:d4dda5c437f0	78	* @brief ETH Init Structure definition
mbed_official	133:d4dda5c437f0	79	*/
mbed_official	133:d4dda5c437f0	80
mbed_official	133:d4dda5c437f0	81	typedef struct
mbed_official	133:d4dda5c437f0	82	{
mbed_official	133:d4dda5c437f0	83	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
mbed_official	133:d4dda5c437f0	84	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
mbed_official	133:d4dda5c437f0	85	and the mode (half/full-duplex).
mbed_official	133:d4dda5c437f0	86	This parameter can be a value of @ref ETH_AutoNegotiation */
mbed_official	133:d4dda5c437f0	87
mbed_official	242:7074e42da0b2	88	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
mbed_official	133:d4dda5c437f0	89	This parameter can be a value of @ref ETH_Speed */
mbed_official	133:d4dda5c437f0	90
mbed_official	133:d4dda5c437f0	91	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
mbed_official	133:d4dda5c437f0	92	This parameter can be a value of @ref ETH_Duplex_Mode */
mbed_official	133:d4dda5c437f0	93
mbed_official	242:7074e42da0b2	94	uint16_t PhyAddress; /*!< Ethernet PHY address.
mbed_official	133:d4dda5c437f0	95	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official	133:d4dda5c437f0	96
mbed_official	133:d4dda5c437f0	97	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
mbed_official	133:d4dda5c437f0	98
mbed_official	242:7074e42da0b2	99	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
mbed_official	133:d4dda5c437f0	100	This parameter can be a value of @ref ETH_Rx_Mode */
mbed_official	133:d4dda5c437f0	101
mbed_official	242:7074e42da0b2	102	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
mbed_official	133:d4dda5c437f0	103	This parameter can be a value of @ref ETH_Checksum_Mode */
mbed_official	133:d4dda5c437f0	104
mbed_official	242:7074e42da0b2	105	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
mbed_official	133:d4dda5c437f0	106	This parameter can be a value of @ref ETH_Media_Interface */
mbed_official	133:d4dda5c437f0	107
mbed_official	133:d4dda5c437f0	108	} ETH_InitTypeDef;
mbed_official	133:d4dda5c437f0	109
mbed_official	133:d4dda5c437f0	110
mbed_official	133:d4dda5c437f0	111	/**
mbed_official	133:d4dda5c437f0	112	* @brief ETH MAC Configuration Structure definition
mbed_official	133:d4dda5c437f0	113	*/
mbed_official	133:d4dda5c437f0	114
mbed_official	133:d4dda5c437f0	115	typedef struct
mbed_official	133:d4dda5c437f0	116	{
mbed_official	133:d4dda5c437f0	117	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
mbed_official	133:d4dda5c437f0	118	When enabled, the MAC allows no more then 2048 bytes to be received.
mbed_official	133:d4dda5c437f0	119	When disabled, the MAC can receive up to 16384 bytes.
mbed_official	133:d4dda5c437f0	120	This parameter can be a value of @ref ETH_watchdog */
mbed_official	133:d4dda5c437f0	121
mbed_official	133:d4dda5c437f0	122	uint32_t Jabber; /*!< Selects or not Jabber timer
mbed_official	133:d4dda5c437f0	123	When enabled, the MAC allows no more then 2048 bytes to be sent.
mbed_official	133:d4dda5c437f0	124	When disabled, the MAC can send up to 16384 bytes.
mbed_official	133:d4dda5c437f0	125	This parameter can be a value of @ref ETH_Jabber */
mbed_official	133:d4dda5c437f0	126
mbed_official	242:7074e42da0b2	127	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
mbed_official	133:d4dda5c437f0	128	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
mbed_official	133:d4dda5c437f0	129
mbed_official	242:7074e42da0b2	130	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
mbed_official	133:d4dda5c437f0	131	This parameter can be a value of @ref ETH_Carrier_Sense */
mbed_official	133:d4dda5c437f0	132
mbed_official	242:7074e42da0b2	133	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
mbed_official	133:d4dda5c437f0	134	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
mbed_official	242:7074e42da0b2	135	in Half-Duplex mode.
mbed_official	133:d4dda5c437f0	136	This parameter can be a value of @ref ETH_Receive_Own */
mbed_official	133:d4dda5c437f0	137
mbed_official	242:7074e42da0b2	138	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
mbed_official	133:d4dda5c437f0	139	This parameter can be a value of @ref ETH_Loop_Back_Mode */
mbed_official	133:d4dda5c437f0	140
mbed_official	133:d4dda5c437f0	141	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
mbed_official	133:d4dda5c437f0	142	This parameter can be a value of @ref ETH_Checksum_Offload */
mbed_official	133:d4dda5c437f0	143
mbed_official	133:d4dda5c437f0	144	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
mbed_official	242:7074e42da0b2	145	when a collision occurs (Half-Duplex mode).
mbed_official	133:d4dda5c437f0	146	This parameter can be a value of @ref ETH_Retry_Transmission */
mbed_official	133:d4dda5c437f0	147
mbed_official	242:7074e42da0b2	148	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
mbed_official	133:d4dda5c437f0	149	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
mbed_official	133:d4dda5c437f0	150
mbed_official	242:7074e42da0b2	151	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
mbed_official	133:d4dda5c437f0	152	This parameter can be a value of @ref ETH_Back_Off_Limit */
mbed_official	133:d4dda5c437f0	153
mbed_official	242:7074e42da0b2	154	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
mbed_official	133:d4dda5c437f0	155	This parameter can be a value of @ref ETH_Deferral_Check */
mbed_official	133:d4dda5c437f0	156
mbed_official	242:7074e42da0b2	157	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
mbed_official	133:d4dda5c437f0	158	This parameter can be a value of @ref ETH_Receive_All */
mbed_official	133:d4dda5c437f0	159
mbed_official	242:7074e42da0b2	160	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
mbed_official	133:d4dda5c437f0	161	This parameter can be a value of @ref ETH_Source_Addr_Filter */
mbed_official	133:d4dda5c437f0	162
mbed_official	133:d4dda5c437f0	163	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
mbed_official	133:d4dda5c437f0	164	This parameter can be a value of @ref ETH_Pass_Control_Frames */
mbed_official	133:d4dda5c437f0	165
mbed_official	242:7074e42da0b2	166	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
mbed_official	133:d4dda5c437f0	167	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
mbed_official	133:d4dda5c437f0	168
mbed_official	242:7074e42da0b2	169	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
mbed_official	133:d4dda5c437f0	170	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
mbed_official	133:d4dda5c437f0	171
mbed_official	133:d4dda5c437f0	172	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
mbed_official	133:d4dda5c437f0	173	This parameter can be a value of @ref ETH_Promiscuous_Mode */
mbed_official	133:d4dda5c437f0	174
mbed_official	242:7074e42da0b2	175	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official	133:d4dda5c437f0	176	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
mbed_official	133:d4dda5c437f0	177
mbed_official	242:7074e42da0b2	178	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official	133:d4dda5c437f0	179	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
mbed_official	133:d4dda5c437f0	180
mbed_official	242:7074e42da0b2	181	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
mbed_official	133:d4dda5c437f0	182	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official	133:d4dda5c437f0	183
mbed_official	242:7074e42da0b2	184	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
mbed_official	133:d4dda5c437f0	185	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official	133:d4dda5c437f0	186
mbed_official	242:7074e42da0b2	187	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
mbed_official	133:d4dda5c437f0	188	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
mbed_official	133:d4dda5c437f0	189
mbed_official	242:7074e42da0b2	190	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
mbed_official	133:d4dda5c437f0	191	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
mbed_official	133:d4dda5c437f0	192
mbed_official	133:d4dda5c437f0	193	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
mbed_official	242:7074e42da0b2	194	automatic retransmission of PAUSE Frame.
mbed_official	133:d4dda5c437f0	195	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
mbed_official	133:d4dda5c437f0	196
mbed_official	133:d4dda5c437f0	197	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
mbed_official	242:7074e42da0b2	198	unicast address and unique multicast address).
mbed_official	133:d4dda5c437f0	199	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
mbed_official	133:d4dda5c437f0	200
mbed_official	133:d4dda5c437f0	201	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
mbed_official	133:d4dda5c437f0	202	disable its transmitter for a specified time (Pause Time)
mbed_official	133:d4dda5c437f0	203	This parameter can be a value of @ref ETH_Receive_Flow_Control */
mbed_official	133:d4dda5c437f0	204
mbed_official	133:d4dda5c437f0	205	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
mbed_official	133:d4dda5c437f0	206	or the MAC back-pressure operation (Half-Duplex mode)
mbed_official	133:d4dda5c437f0	207	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
mbed_official	133:d4dda5c437f0	208
mbed_official	133:d4dda5c437f0	209	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
mbed_official	242:7074e42da0b2	210	comparison and filtering.
mbed_official	133:d4dda5c437f0	211	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
mbed_official	133:d4dda5c437f0	212
mbed_official	133:d4dda5c437f0	213	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
mbed_official	133:d4dda5c437f0	214
mbed_official	133:d4dda5c437f0	215	} ETH_MACInitTypeDef;
mbed_official	133:d4dda5c437f0	216
mbed_official	133:d4dda5c437f0	217
mbed_official	133:d4dda5c437f0	218	/**
mbed_official	133:d4dda5c437f0	219	* @brief ETH DMA Configuration Structure definition
mbed_official	133:d4dda5c437f0	220	*/
mbed_official	133:d4dda5c437f0	221
mbed_official	133:d4dda5c437f0	222	typedef struct
mbed_official	133:d4dda5c437f0	223	{
mbed_official	242:7074e42da0b2	224	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
mbed_official	133:d4dda5c437f0	225	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
mbed_official	133:d4dda5c437f0	226
mbed_official	242:7074e42da0b2	227	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
mbed_official	133:d4dda5c437f0	228	This parameter can be a value of @ref ETH_Receive_Store_Forward */
mbed_official	133:d4dda5c437f0	229
mbed_official	242:7074e42da0b2	230	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
mbed_official	133:d4dda5c437f0	231	This parameter can be a value of @ref ETH_Flush_Received_Frame */
mbed_official	133:d4dda5c437f0	232
mbed_official	242:7074e42da0b2	233	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
mbed_official	133:d4dda5c437f0	234	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
mbed_official	133:d4dda5c437f0	235
mbed_official	242:7074e42da0b2	236	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
mbed_official	133:d4dda5c437f0	237	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
mbed_official	133:d4dda5c437f0	238
mbed_official	242:7074e42da0b2	239	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
mbed_official	133:d4dda5c437f0	240	This parameter can be a value of @ref ETH_Forward_Error_Frames */
mbed_official	133:d4dda5c437f0	241
mbed_official	133:d4dda5c437f0	242	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
mbed_official	133:d4dda5c437f0	243	and length less than 64 bytes) including pad-bytes and CRC)
mbed_official	133:d4dda5c437f0	244	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
mbed_official	133:d4dda5c437f0	245
mbed_official	242:7074e42da0b2	246	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
mbed_official	133:d4dda5c437f0	247	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
mbed_official	133:d4dda5c437f0	248
mbed_official	133:d4dda5c437f0	249	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
mbed_official	133:d4dda5c437f0	250	frame of Transmit data even before obtaining the status for the first frame.
mbed_official	133:d4dda5c437f0	251	This parameter can be a value of @ref ETH_Second_Frame_Operate */
mbed_official	133:d4dda5c437f0	252
mbed_official	242:7074e42da0b2	253	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
mbed_official	133:d4dda5c437f0	254	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
mbed_official	133:d4dda5c437f0	255
mbed_official	242:7074e42da0b2	256	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
mbed_official	133:d4dda5c437f0	257	This parameter can be a value of @ref ETH_Fixed_Burst */
mbed_official	133:d4dda5c437f0	258
mbed_official	242:7074e42da0b2	259	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
mbed_official	133:d4dda5c437f0	260	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
mbed_official	133:d4dda5c437f0	261
mbed_official	242:7074e42da0b2	262	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
mbed_official	133:d4dda5c437f0	263	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
mbed_official	133:d4dda5c437f0	264
mbed_official	242:7074e42da0b2	265	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
mbed_official	133:d4dda5c437f0	266	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
mbed_official	133:d4dda5c437f0	267
mbed_official	133:d4dda5c437f0	268	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
mbed_official	133:d4dda5c437f0	269	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official	133:d4dda5c437f0	270
mbed_official	242:7074e42da0b2	271	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
mbed_official	133:d4dda5c437f0	272	This parameter can be a value of @ref ETH_DMA_Arbitration */
mbed_official	133:d4dda5c437f0	273	} ETH_DMAInitTypeDef;
mbed_official	133:d4dda5c437f0	274
mbed_official	133:d4dda5c437f0	275
mbed_official	133:d4dda5c437f0	276	/**
mbed_official	133:d4dda5c437f0	277	* @brief ETH DMA Descriptors data structure definition
mbed_official	133:d4dda5c437f0	278	*/
mbed_official	133:d4dda5c437f0	279
mbed_official	133:d4dda5c437f0	280	typedef struct
mbed_official	133:d4dda5c437f0	281	{
mbed_official	133:d4dda5c437f0	282	__IO uint32_t Status; /!< Status /
mbed_official	133:d4dda5c437f0	283
mbed_official	133:d4dda5c437f0	284	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
mbed_official	133:d4dda5c437f0	285
mbed_official	133:d4dda5c437f0	286	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
mbed_official	133:d4dda5c437f0	287
mbed_official	133:d4dda5c437f0	288	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
mbed_official	133:d4dda5c437f0	289
mbed_official	133:d4dda5c437f0	290	/!< Enhanced ETHERNET DMA PTP Descriptors /
mbed_official	133:d4dda5c437f0	291	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
mbed_official	133:d4dda5c437f0	292
mbed_official	133:d4dda5c437f0	293	uint32_t Reserved1; /!< Reserved /
mbed_official	133:d4dda5c437f0	294
mbed_official	133:d4dda5c437f0	295	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
mbed_official	133:d4dda5c437f0	296
mbed_official	133:d4dda5c437f0	297	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
mbed_official	133:d4dda5c437f0	298
mbed_official	133:d4dda5c437f0	299	} ETH_DMADescTypeDef;
mbed_official	133:d4dda5c437f0	300
mbed_official	133:d4dda5c437f0	301
mbed_official	133:d4dda5c437f0	302	/**
mbed_official	133:d4dda5c437f0	303	* @brief Received Frame Informations structure definition
mbed_official	133:d4dda5c437f0	304	*/
mbed_official	133:d4dda5c437f0	305	typedef struct
mbed_official	133:d4dda5c437f0	306	{
mbed_official	133:d4dda5c437f0	307	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
mbed_official	133:d4dda5c437f0	308
mbed_official	133:d4dda5c437f0	309	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
mbed_official	133:d4dda5c437f0	310
mbed_official	133:d4dda5c437f0	311	uint32_t SegCount; /!< Segment count /
mbed_official	133:d4dda5c437f0	312
mbed_official	133:d4dda5c437f0	313	uint32_t length; /!< Frame length /
mbed_official	133:d4dda5c437f0	314
mbed_official	133:d4dda5c437f0	315	uint32_t buffer; /!< Frame buffer /
mbed_official	133:d4dda5c437f0	316
mbed_official	133:d4dda5c437f0	317	} ETH_DMARxFrameInfos;
mbed_official	133:d4dda5c437f0	318
mbed_official	133:d4dda5c437f0	319
mbed_official	133:d4dda5c437f0	320	/**
mbed_official	133:d4dda5c437f0	321	* @brief ETH Handle Structure definition
mbed_official	133:d4dda5c437f0	322	*/
mbed_official	133:d4dda5c437f0	323
mbed_official	133:d4dda5c437f0	324	typedef struct
mbed_official	133:d4dda5c437f0	325	{
mbed_official	133:d4dda5c437f0	326	ETH_TypeDef Instance; /!< Register base address */
mbed_official	133:d4dda5c437f0	327
mbed_official	133:d4dda5c437f0	328	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
mbed_official	133:d4dda5c437f0	329
mbed_official	133:d4dda5c437f0	330	uint32_t LinkStatus; /!< Ethernet link status /
mbed_official	133:d4dda5c437f0	331
mbed_official	133:d4dda5c437f0	332	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
mbed_official	133:d4dda5c437f0	333
mbed_official	133:d4dda5c437f0	334	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
mbed_official	133:d4dda5c437f0	335
mbed_official	133:d4dda5c437f0	336	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
mbed_official	133:d4dda5c437f0	337
mbed_official	133:d4dda5c437f0	338	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
mbed_official	133:d4dda5c437f0	339
mbed_official	133:d4dda5c437f0	340	HAL_LockTypeDef Lock; /!< ETH Lock /
mbed_official	133:d4dda5c437f0	341
mbed_official	133:d4dda5c437f0	342	} ETH_HandleTypeDef;
mbed_official	133:d4dda5c437f0	343
mbed_official	133:d4dda5c437f0	344	/* Exported constants --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	345
mbed_official	133:d4dda5c437f0	346	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
mbed_official	133:d4dda5c437f0	347
mbed_official	133:d4dda5c437f0	348	/* Delay to wait when writing to some Ethernet registers */
mbed_official	133:d4dda5c437f0	349	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	350
mbed_official	133:d4dda5c437f0	351
mbed_official	133:d4dda5c437f0	352	/* ETHERNET Errors */
mbed_official	133:d4dda5c437f0	353	#define ETH_SUCCESS ((uint32_t)0)
mbed_official	133:d4dda5c437f0	354	#define ETH_ERROR ((uint32_t)1)
mbed_official	133:d4dda5c437f0	355
mbed_official	133:d4dda5c437f0	356	/** @defgroup ETH_Buffers_setting
mbed_official	133:d4dda5c437f0	357	* @{
mbed_official	133:d4dda5c437f0	358	*/
mbed_official	133:d4dda5c437f0	359	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC /
mbed_official	133:d4dda5c437f0	360	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
mbed_official	133:d4dda5c437f0	361	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
mbed_official	133:d4dda5c437f0	362	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
mbed_official	133:d4dda5c437f0	363	#define VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
mbed_official	133:d4dda5c437f0	364	#define MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
mbed_official	133:d4dda5c437f0	365	#define MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
mbed_official	133:d4dda5c437f0	366	#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
mbed_official	133:d4dda5c437f0	367
mbed_official	133:d4dda5c437f0	368	/* Ethernet driver receive buffers are organized in a chained linked-list, when
mbed_official	133:d4dda5c437f0	369	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
mbed_official	133:d4dda5c437f0	370	to the driver receive buffers memory.
mbed_official	133:d4dda5c437f0	371
mbed_official	133:d4dda5c437f0	372	Depending on the size of the received ethernet packet and the size of
mbed_official	133:d4dda5c437f0	373	each ethernet driver receive buffer, the received packet can take one or more
mbed_official	133:d4dda5c437f0	374	ethernet driver receive buffer.
mbed_official	133:d4dda5c437f0	375
mbed_official	133:d4dda5c437f0	376	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
mbed_official	133:d4dda5c437f0	377	and the total count of the driver receive buffers ETH_RXBUFNB.
mbed_official	133:d4dda5c437f0	378
mbed_official	133:d4dda5c437f0	379	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
mbed_official	133:d4dda5c437f0	380	example, they can be reconfigured in the application layer to fit the application
mbed_official	133:d4dda5c437f0	381	needs */
mbed_official	133:d4dda5c437f0	382
mbed_official	133:d4dda5c437f0	383	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
mbed_official	133:d4dda5c437f0	384	packet */
mbed_official	133:d4dda5c437f0	385	#ifndef ETH_RX_BUF_SIZE
mbed_official	133:d4dda5c437f0	386	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official	133:d4dda5c437f0	387	#endif
mbed_official	133:d4dda5c437f0	388
mbed_official	133:d4dda5c437f0	389	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
mbed_official	133:d4dda5c437f0	390	#ifndef ETH_RXBUFNB
mbed_official	133:d4dda5c437f0	391	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
mbed_official	133:d4dda5c437f0	392	#endif
mbed_official	133:d4dda5c437f0	393
mbed_official	133:d4dda5c437f0	394
mbed_official	133:d4dda5c437f0	395	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
mbed_official	133:d4dda5c437f0	396	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
mbed_official	133:d4dda5c437f0	397	driver transmit buffers memory to the TxFIFO.
mbed_official	133:d4dda5c437f0	398
mbed_official	133:d4dda5c437f0	399	Depending on the size of the Ethernet packet to be transmitted and the size of
mbed_official	133:d4dda5c437f0	400	each ethernet driver transmit buffer, the packet to be transmitted can take
mbed_official	133:d4dda5c437f0	401	one or more ethernet driver transmit buffer.
mbed_official	133:d4dda5c437f0	402
mbed_official	133:d4dda5c437f0	403	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
mbed_official	133:d4dda5c437f0	404	and the total count of the driver transmit buffers ETH_TXBUFNB.
mbed_official	133:d4dda5c437f0	405
mbed_official	133:d4dda5c437f0	406	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
mbed_official	133:d4dda5c437f0	407	example, they can be reconfigured in the application layer to fit the application
mbed_official	133:d4dda5c437f0	408	needs */
mbed_official	133:d4dda5c437f0	409
mbed_official	133:d4dda5c437f0	410	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
mbed_official	133:d4dda5c437f0	411	packet */
mbed_official	133:d4dda5c437f0	412	#ifndef ETH_TX_BUF_SIZE
mbed_official	133:d4dda5c437f0	413	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official	133:d4dda5c437f0	414	#endif
mbed_official	133:d4dda5c437f0	415
mbed_official	133:d4dda5c437f0	416	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
mbed_official	133:d4dda5c437f0	417	#ifndef ETH_TXBUFNB
mbed_official	133:d4dda5c437f0	418	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
mbed_official	133:d4dda5c437f0	419	#endif
mbed_official	133:d4dda5c437f0	420
mbed_official	133:d4dda5c437f0	421
mbed_official	133:d4dda5c437f0	422	/*
mbed_official	133:d4dda5c437f0	423	DMA Tx Desciptor
mbed_official	133:d4dda5c437f0	424	-----------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	425	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
mbed_official	133:d4dda5c437f0	426	-----------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	427	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
mbed_official	133:d4dda5c437f0	428	-----------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	429	TDES2 \| Buffer1 Address [31:0] \|
mbed_official	133:d4dda5c437f0	430	-----------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	431	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
mbed_official	133:d4dda5c437f0	432	-----------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	433	*/
mbed_official	133:d4dda5c437f0	434
mbed_official	133:d4dda5c437f0	435	/**
mbed_official	133:d4dda5c437f0	436	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
mbed_official	133:d4dda5c437f0	437	*/
mbed_official	133:d4dda5c437f0	438	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
mbed_official	133:d4dda5c437f0	439	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
mbed_official	133:d4dda5c437f0	440	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
mbed_official	133:d4dda5c437f0	441	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
mbed_official	133:d4dda5c437f0	442	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
mbed_official	133:d4dda5c437f0	443	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
mbed_official	133:d4dda5c437f0	444	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
mbed_official	133:d4dda5c437f0	445	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
mbed_official	133:d4dda5c437f0	446	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
mbed_official	133:d4dda5c437f0	447	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
mbed_official	133:d4dda5c437f0	448	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
mbed_official	133:d4dda5c437f0	449	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
mbed_official	133:d4dda5c437f0	450	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
mbed_official	133:d4dda5c437f0	451	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
mbed_official	133:d4dda5c437f0	452	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
mbed_official	133:d4dda5c437f0	453	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
mbed_official	133:d4dda5c437f0	454	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
mbed_official	133:d4dda5c437f0	455	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
mbed_official	133:d4dda5c437f0	456	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
mbed_official	133:d4dda5c437f0	457	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
mbed_official	133:d4dda5c437f0	458	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
mbed_official	133:d4dda5c437f0	459	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
mbed_official	133:d4dda5c437f0	460	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
mbed_official	133:d4dda5c437f0	461	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
mbed_official	133:d4dda5c437f0	462	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
mbed_official	133:d4dda5c437f0	463	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
mbed_official	133:d4dda5c437f0	464	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
mbed_official	133:d4dda5c437f0	465	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
mbed_official	133:d4dda5c437f0	466	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
mbed_official	133:d4dda5c437f0	467
mbed_official	133:d4dda5c437f0	468	/**
mbed_official	133:d4dda5c437f0	469	* @brief Bit definition of TDES1 register
mbed_official	133:d4dda5c437f0	470	*/
mbed_official	133:d4dda5c437f0	471	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
mbed_official	133:d4dda5c437f0	472	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
mbed_official	133:d4dda5c437f0	473
mbed_official	133:d4dda5c437f0	474	/**
mbed_official	133:d4dda5c437f0	475	* @brief Bit definition of TDES2 register
mbed_official	133:d4dda5c437f0	476	*/
mbed_official	133:d4dda5c437f0	477	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
mbed_official	133:d4dda5c437f0	478
mbed_official	133:d4dda5c437f0	479	/**
mbed_official	133:d4dda5c437f0	480	* @brief Bit definition of TDES3 register
mbed_official	133:d4dda5c437f0	481	*/
mbed_official	133:d4dda5c437f0	482	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
mbed_official	133:d4dda5c437f0	483
mbed_official	133:d4dda5c437f0	484	/*---------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	485	TDES6 \| Transmit Time Stamp Low [31:0] \|
mbed_official	133:d4dda5c437f0	486	-----------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	487	TDES7 \| Transmit Time Stamp High [31:0] \|
mbed_official	133:d4dda5c437f0	488	----------------------------------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	489
mbed_official	133:d4dda5c437f0	490	/* Bit definition of TDES6 register */
mbed_official	133:d4dda5c437f0	491	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
mbed_official	133:d4dda5c437f0	492
mbed_official	133:d4dda5c437f0	493	/* Bit definition of TDES7 register */
mbed_official	133:d4dda5c437f0	494	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
mbed_official	133:d4dda5c437f0	495
mbed_official	133:d4dda5c437f0	496	/**
mbed_official	133:d4dda5c437f0	497	* @}
mbed_official	133:d4dda5c437f0	498	*/
mbed_official	133:d4dda5c437f0	499
mbed_official	133:d4dda5c437f0	500
mbed_official	133:d4dda5c437f0	501	/** @defgroup ETH_DMA_Rx_descriptor
mbed_official	133:d4dda5c437f0	502	* @{
mbed_official	133:d4dda5c437f0	503	*/
mbed_official	133:d4dda5c437f0	504
mbed_official	133:d4dda5c437f0	505	/*
mbed_official	133:d4dda5c437f0	506	DMA Rx Descriptor
mbed_official	133:d4dda5c437f0	507	--------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	508	RDES0 \| OWN(31) \| Status [30:0] \|
mbed_official	133:d4dda5c437f0	509	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	510	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
mbed_official	133:d4dda5c437f0	511	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	512	RDES2 \| Buffer1 Address [31:0] \|
mbed_official	133:d4dda5c437f0	513	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	514	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
mbed_official	133:d4dda5c437f0	515	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	516	*/
mbed_official	133:d4dda5c437f0	517
mbed_official	133:d4dda5c437f0	518	/**
mbed_official	133:d4dda5c437f0	519	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
mbed_official	133:d4dda5c437f0	520	*/
mbed_official	133:d4dda5c437f0	521	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
mbed_official	133:d4dda5c437f0	522	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
mbed_official	133:d4dda5c437f0	523	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
mbed_official	133:d4dda5c437f0	524	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
mbed_official	133:d4dda5c437f0	525	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
mbed_official	133:d4dda5c437f0	526	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
mbed_official	133:d4dda5c437f0	527	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
mbed_official	133:d4dda5c437f0	528	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
mbed_official	133:d4dda5c437f0	529	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
mbed_official	133:d4dda5c437f0	530	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
mbed_official	133:d4dda5c437f0	531	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
mbed_official	133:d4dda5c437f0	532	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
mbed_official	133:d4dda5c437f0	533	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
mbed_official	133:d4dda5c437f0	534	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
mbed_official	133:d4dda5c437f0	535	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
mbed_official	133:d4dda5c437f0	536	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
mbed_official	133:d4dda5c437f0	537	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
mbed_official	133:d4dda5c437f0	538	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
mbed_official	133:d4dda5c437f0	539	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
mbed_official	133:d4dda5c437f0	540
mbed_official	133:d4dda5c437f0	541	/**
mbed_official	133:d4dda5c437f0	542	* @brief Bit definition of RDES1 register
mbed_official	133:d4dda5c437f0	543	*/
mbed_official	133:d4dda5c437f0	544	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
mbed_official	133:d4dda5c437f0	545	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
mbed_official	133:d4dda5c437f0	546	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
mbed_official	133:d4dda5c437f0	547	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
mbed_official	133:d4dda5c437f0	548	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
mbed_official	133:d4dda5c437f0	549
mbed_official	133:d4dda5c437f0	550	/**
mbed_official	133:d4dda5c437f0	551	* @brief Bit definition of RDES2 register
mbed_official	133:d4dda5c437f0	552	*/
mbed_official	133:d4dda5c437f0	553	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
mbed_official	133:d4dda5c437f0	554
mbed_official	133:d4dda5c437f0	555	/**
mbed_official	133:d4dda5c437f0	556	* @brief Bit definition of RDES3 register
mbed_official	133:d4dda5c437f0	557	*/
mbed_official	133:d4dda5c437f0	558	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
mbed_official	133:d4dda5c437f0	559
mbed_official	133:d4dda5c437f0	560	/*---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	561	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
mbed_official	133:d4dda5c437f0	562	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	563	RDES5 \| Reserved[31:0] \|
mbed_official	133:d4dda5c437f0	564	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	565	RDES6 \| Receive Time Stamp Low [31:0] \|
mbed_official	133:d4dda5c437f0	566	---------------------------------------------------------------------------------------------------------------------
mbed_official	133:d4dda5c437f0	567	RDES7 \| Receive Time Stamp High [31:0] \|
mbed_official	133:d4dda5c437f0	568	--------------------------------------------------------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	569
mbed_official	133:d4dda5c437f0	570	/* Bit definition of RDES4 register */
mbed_official	133:d4dda5c437f0	571	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
mbed_official	133:d4dda5c437f0	572	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
mbed_official	133:d4dda5c437f0	573	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
mbed_official	133:d4dda5c437f0	574	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
mbed_official	133:d4dda5c437f0	575	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
mbed_official	133:d4dda5c437f0	576	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
mbed_official	133:d4dda5c437f0	577	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
mbed_official	133:d4dda5c437f0	578	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
mbed_official	133:d4dda5c437f0	579	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
mbed_official	133:d4dda5c437f0	580	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
mbed_official	133:d4dda5c437f0	581	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
mbed_official	133:d4dda5c437f0	582	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
mbed_official	133:d4dda5c437f0	583	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
mbed_official	133:d4dda5c437f0	584	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
mbed_official	133:d4dda5c437f0	585	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
mbed_official	133:d4dda5c437f0	586	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
mbed_official	133:d4dda5c437f0	587	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
mbed_official	133:d4dda5c437f0	588	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
mbed_official	133:d4dda5c437f0	589	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
mbed_official	133:d4dda5c437f0	590
mbed_official	133:d4dda5c437f0	591	/* Bit definition of RDES6 register */
mbed_official	133:d4dda5c437f0	592	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
mbed_official	133:d4dda5c437f0	593
mbed_official	133:d4dda5c437f0	594	/* Bit definition of RDES7 register */
mbed_official	133:d4dda5c437f0	595	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
mbed_official	133:d4dda5c437f0	596
mbed_official	133:d4dda5c437f0	597
mbed_official	133:d4dda5c437f0	598	/** @defgroup ETH_AutoNegotiation
mbed_official	133:d4dda5c437f0	599	* @{
mbed_official	133:d4dda5c437f0	600	*/
mbed_official	133:d4dda5c437f0	601	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	602	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	603	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	604	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
mbed_official	133:d4dda5c437f0	605	/**
mbed_official	133:d4dda5c437f0	606	* @}
mbed_official	133:d4dda5c437f0	607	*/
mbed_official	133:d4dda5c437f0	608	/** @defgroup ETH_Speed
mbed_official	133:d4dda5c437f0	609	* @{
mbed_official	133:d4dda5c437f0	610	*/
mbed_official	133:d4dda5c437f0	611	#define ETH_SPEED_10M ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	612	#define ETH_SPEED_100M ((uint32_t)0x00004000)
mbed_official	133:d4dda5c437f0	613	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
mbed_official	133:d4dda5c437f0	614	((SPEED) == ETH_SPEED_100M))
mbed_official	133:d4dda5c437f0	615	/**
mbed_official	133:d4dda5c437f0	616	* @}
mbed_official	133:d4dda5c437f0	617	*/
mbed_official	133:d4dda5c437f0	618	/** @defgroup ETH_Duplex_Mode
mbed_official	133:d4dda5c437f0	619	* @{
mbed_official	133:d4dda5c437f0	620	*/
mbed_official	133:d4dda5c437f0	621	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
mbed_official	133:d4dda5c437f0	622	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	623	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
mbed_official	133:d4dda5c437f0	624	((MODE) == ETH_MODE_HALFDUPLEX))
mbed_official	133:d4dda5c437f0	625	/**
mbed_official	133:d4dda5c437f0	626	* @}
mbed_official	133:d4dda5c437f0	627	*/
mbed_official	133:d4dda5c437f0	628	/** @defgroup ETH_Rx_Mode
mbed_official	133:d4dda5c437f0	629	* @{
mbed_official	133:d4dda5c437f0	630	*/
mbed_official	133:d4dda5c437f0	631	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	632	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	633	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
mbed_official	133:d4dda5c437f0	634	((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official	133:d4dda5c437f0	635	/**
mbed_official	133:d4dda5c437f0	636	* @}
mbed_official	133:d4dda5c437f0	637	*/
mbed_official	133:d4dda5c437f0	638
mbed_official	133:d4dda5c437f0	639	/** @defgroup ETH_Checksum_Mode
mbed_official	133:d4dda5c437f0	640	* @{
mbed_official	133:d4dda5c437f0	641	*/
mbed_official	133:d4dda5c437f0	642	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	643	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	644	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
mbed_official	133:d4dda5c437f0	645	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
mbed_official	133:d4dda5c437f0	646	/**
mbed_official	133:d4dda5c437f0	647	* @}
mbed_official	133:d4dda5c437f0	648	*/
mbed_official	133:d4dda5c437f0	649
mbed_official	133:d4dda5c437f0	650	/** @defgroup ETH_Media_Interface
mbed_official	133:d4dda5c437f0	651	* @{
mbed_official	133:d4dda5c437f0	652	*/
mbed_official	133:d4dda5c437f0	653	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	654	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
mbed_official	133:d4dda5c437f0	655	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
mbed_official	133:d4dda5c437f0	656	((MODE) == ETH_MEDIA_INTERFACE_RMII))
mbed_official	133:d4dda5c437f0	657
mbed_official	133:d4dda5c437f0	658	/**
mbed_official	133:d4dda5c437f0	659	* @}
mbed_official	133:d4dda5c437f0	660	*/
mbed_official	133:d4dda5c437f0	661
mbed_official	133:d4dda5c437f0	662	/** @defgroup ETH_watchdog
mbed_official	133:d4dda5c437f0	663	* @{
mbed_official	133:d4dda5c437f0	664	*/
mbed_official	133:d4dda5c437f0	665	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	666	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
mbed_official	133:d4dda5c437f0	667	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	668	((CMD) == ETH_WATCHDOG_DISABLE))
mbed_official	133:d4dda5c437f0	669
mbed_official	133:d4dda5c437f0	670	/**
mbed_official	133:d4dda5c437f0	671	* @}
mbed_official	133:d4dda5c437f0	672	*/
mbed_official	133:d4dda5c437f0	673
mbed_official	133:d4dda5c437f0	674	/** @defgroup ETH_Jabber
mbed_official	133:d4dda5c437f0	675	* @{
mbed_official	133:d4dda5c437f0	676	*/
mbed_official	133:d4dda5c437f0	677	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	678	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
mbed_official	133:d4dda5c437f0	679	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	680	((CMD) == ETH_JABBER_DISABLE))
mbed_official	133:d4dda5c437f0	681
mbed_official	133:d4dda5c437f0	682	/**
mbed_official	133:d4dda5c437f0	683	* @}
mbed_official	133:d4dda5c437f0	684	*/
mbed_official	133:d4dda5c437f0	685
mbed_official	133:d4dda5c437f0	686	/** @defgroup ETH_Inter_Frame_Gap
mbed_official	133:d4dda5c437f0	687	* @{
mbed_official	133:d4dda5c437f0	688	*/
mbed_official	133:d4dda5c437f0	689	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
mbed_official	133:d4dda5c437f0	690	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
mbed_official	133:d4dda5c437f0	691	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
mbed_official	133:d4dda5c437f0	692	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
mbed_official	133:d4dda5c437f0	693	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
mbed_official	133:d4dda5c437f0	694	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
mbed_official	133:d4dda5c437f0	695	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
mbed_official	133:d4dda5c437f0	696	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
mbed_official	133:d4dda5c437f0	697	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
mbed_official	133:d4dda5c437f0	698	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
mbed_official	133:d4dda5c437f0	699	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
mbed_official	133:d4dda5c437f0	700	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
mbed_official	133:d4dda5c437f0	701	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
mbed_official	133:d4dda5c437f0	702	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
mbed_official	133:d4dda5c437f0	703	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
mbed_official	133:d4dda5c437f0	704	((GAP) == ETH_INTERFRAMEGAP_40BIT))
mbed_official	133:d4dda5c437f0	705
mbed_official	133:d4dda5c437f0	706	/**
mbed_official	133:d4dda5c437f0	707	* @}
mbed_official	133:d4dda5c437f0	708	*/
mbed_official	133:d4dda5c437f0	709
mbed_official	133:d4dda5c437f0	710	/** @defgroup ETH_Carrier_Sense
mbed_official	133:d4dda5c437f0	711	* @{
mbed_official	133:d4dda5c437f0	712	*/
mbed_official	133:d4dda5c437f0	713	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	714	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
mbed_official	133:d4dda5c437f0	715	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	716	((CMD) == ETH_CARRIERSENCE_DISABLE))
mbed_official	133:d4dda5c437f0	717
mbed_official	133:d4dda5c437f0	718	/**
mbed_official	133:d4dda5c437f0	719	* @}
mbed_official	133:d4dda5c437f0	720	*/
mbed_official	133:d4dda5c437f0	721
mbed_official	133:d4dda5c437f0	722	/** @defgroup ETH_Receive_Own
mbed_official	133:d4dda5c437f0	723	* @{
mbed_official	133:d4dda5c437f0	724	*/
mbed_official	133:d4dda5c437f0	725	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	726	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
mbed_official	133:d4dda5c437f0	727	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	728	((CMD) == ETH_RECEIVEOWN_DISABLE))
mbed_official	133:d4dda5c437f0	729
mbed_official	133:d4dda5c437f0	730	/**
mbed_official	133:d4dda5c437f0	731	* @}
mbed_official	133:d4dda5c437f0	732	*/
mbed_official	133:d4dda5c437f0	733
mbed_official	133:d4dda5c437f0	734	/** @defgroup ETH_Loop_Back_Mode
mbed_official	133:d4dda5c437f0	735	* @{
mbed_official	133:d4dda5c437f0	736	*/
mbed_official	133:d4dda5c437f0	737	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
mbed_official	133:d4dda5c437f0	738	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	739	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	740	((CMD) == ETH_LOOPBACKMODE_DISABLE))
mbed_official	133:d4dda5c437f0	741
mbed_official	133:d4dda5c437f0	742	/**
mbed_official	133:d4dda5c437f0	743	* @}
mbed_official	133:d4dda5c437f0	744	*/
mbed_official	133:d4dda5c437f0	745
mbed_official	133:d4dda5c437f0	746	/** @defgroup ETH_Checksum_Offload
mbed_official	133:d4dda5c437f0	747	* @{
mbed_official	133:d4dda5c437f0	748	*/
mbed_official	133:d4dda5c437f0	749	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
mbed_official	133:d4dda5c437f0	750	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	751	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	752	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
mbed_official	133:d4dda5c437f0	753
mbed_official	133:d4dda5c437f0	754	/**
mbed_official	133:d4dda5c437f0	755	* @}
mbed_official	133:d4dda5c437f0	756	*/
mbed_official	133:d4dda5c437f0	757
mbed_official	133:d4dda5c437f0	758	/** @defgroup ETH_Retry_Transmission
mbed_official	133:d4dda5c437f0	759	* @{
mbed_official	133:d4dda5c437f0	760	*/
mbed_official	133:d4dda5c437f0	761	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	762	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
mbed_official	133:d4dda5c437f0	763	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	764	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
mbed_official	133:d4dda5c437f0	765
mbed_official	133:d4dda5c437f0	766	/**
mbed_official	133:d4dda5c437f0	767	* @}
mbed_official	133:d4dda5c437f0	768	*/
mbed_official	133:d4dda5c437f0	769
mbed_official	133:d4dda5c437f0	770	/** @defgroup ETH_Automatic_Pad_CRC_Strip
mbed_official	133:d4dda5c437f0	771	* @{
mbed_official	133:d4dda5c437f0	772	*/
mbed_official	133:d4dda5c437f0	773	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
mbed_official	133:d4dda5c437f0	774	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	775	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	776	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
mbed_official	133:d4dda5c437f0	777
mbed_official	133:d4dda5c437f0	778	/**
mbed_official	133:d4dda5c437f0	779	* @}
mbed_official	133:d4dda5c437f0	780	*/
mbed_official	133:d4dda5c437f0	781
mbed_official	133:d4dda5c437f0	782	/** @defgroup ETH_Back_Off_Limit
mbed_official	133:d4dda5c437f0	783	* @{
mbed_official	133:d4dda5c437f0	784	*/
mbed_official	133:d4dda5c437f0	785	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	786	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
mbed_official	133:d4dda5c437f0	787	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
mbed_official	133:d4dda5c437f0	788	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
mbed_official	133:d4dda5c437f0	789	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
mbed_official	133:d4dda5c437f0	790	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
mbed_official	133:d4dda5c437f0	791	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
mbed_official	133:d4dda5c437f0	792	((LIMIT) == ETH_BACKOFFLIMIT_1))
mbed_official	133:d4dda5c437f0	793
mbed_official	133:d4dda5c437f0	794	/**
mbed_official	133:d4dda5c437f0	795	* @}
mbed_official	133:d4dda5c437f0	796	*/
mbed_official	133:d4dda5c437f0	797
mbed_official	133:d4dda5c437f0	798	/** @defgroup ETH_Deferral_Check
mbed_official	133:d4dda5c437f0	799	* @{
mbed_official	133:d4dda5c437f0	800	*/
mbed_official	133:d4dda5c437f0	801	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	802	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	803	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	804	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
mbed_official	133:d4dda5c437f0	805
mbed_official	133:d4dda5c437f0	806	/**
mbed_official	133:d4dda5c437f0	807	* @}
mbed_official	133:d4dda5c437f0	808	*/
mbed_official	133:d4dda5c437f0	809
mbed_official	133:d4dda5c437f0	810	/** @defgroup ETH_Receive_All
mbed_official	133:d4dda5c437f0	811	* @{
mbed_official	133:d4dda5c437f0	812	*/
mbed_official	133:d4dda5c437f0	813	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
mbed_official	133:d4dda5c437f0	814	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	815	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	816	((CMD) == ETH_RECEIVEAll_DISABLE))
mbed_official	133:d4dda5c437f0	817
mbed_official	133:d4dda5c437f0	818	/**
mbed_official	133:d4dda5c437f0	819	* @}
mbed_official	133:d4dda5c437f0	820	*/
mbed_official	133:d4dda5c437f0	821
mbed_official	133:d4dda5c437f0	822	/** @defgroup ETH_Source_Addr_Filter
mbed_official	133:d4dda5c437f0	823	* @{
mbed_official	133:d4dda5c437f0	824	*/
mbed_official	133:d4dda5c437f0	825	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
mbed_official	133:d4dda5c437f0	826	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
mbed_official	133:d4dda5c437f0	827	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	828	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	829	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	830	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
mbed_official	133:d4dda5c437f0	831
mbed_official	133:d4dda5c437f0	832	/**
mbed_official	133:d4dda5c437f0	833	* @}
mbed_official	133:d4dda5c437f0	834	*/
mbed_official	133:d4dda5c437f0	835
mbed_official	133:d4dda5c437f0	836	/** @defgroup ETH_Pass_Control_Frames
mbed_official	133:d4dda5c437f0	837	* @{
mbed_official	133:d4dda5c437f0	838	*/
mbed_official	133:d4dda5c437f0	839	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
mbed_official	133:d4dda5c437f0	840	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
mbed_official	133:d4dda5c437f0	841	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
mbed_official	133:d4dda5c437f0	842	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
mbed_official	133:d4dda5c437f0	843	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
mbed_official	133:d4dda5c437f0	844	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
mbed_official	133:d4dda5c437f0	845
mbed_official	133:d4dda5c437f0	846	/**
mbed_official	133:d4dda5c437f0	847	* @}
mbed_official	133:d4dda5c437f0	848	*/
mbed_official	133:d4dda5c437f0	849
mbed_official	133:d4dda5c437f0	850	/** @defgroup ETH_Broadcast_Frames_Reception
mbed_official	133:d4dda5c437f0	851	* @{
mbed_official	133:d4dda5c437f0	852	*/
mbed_official	133:d4dda5c437f0	853	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	854	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
mbed_official	133:d4dda5c437f0	855	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	856	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
mbed_official	133:d4dda5c437f0	857
mbed_official	133:d4dda5c437f0	858	/**
mbed_official	133:d4dda5c437f0	859	* @}
mbed_official	133:d4dda5c437f0	860	*/
mbed_official	133:d4dda5c437f0	861
mbed_official	133:d4dda5c437f0	862	/** @defgroup ETH_Destination_Addr_Filter
mbed_official	133:d4dda5c437f0	863	* @{
mbed_official	133:d4dda5c437f0	864	*/
mbed_official	133:d4dda5c437f0	865	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	866	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	867	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
mbed_official	133:d4dda5c437f0	868	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
mbed_official	133:d4dda5c437f0	869
mbed_official	133:d4dda5c437f0	870	/**
mbed_official	133:d4dda5c437f0	871	* @}
mbed_official	133:d4dda5c437f0	872	*/
mbed_official	133:d4dda5c437f0	873
mbed_official	133:d4dda5c437f0	874	/** @defgroup ETH_Promiscuous_Mode
mbed_official	133:d4dda5c437f0	875	* @{
mbed_official	133:d4dda5c437f0	876	*/
mbed_official	133:d4dda5c437f0	877	#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	878	#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	879	#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	880	((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
mbed_official	133:d4dda5c437f0	881
mbed_official	133:d4dda5c437f0	882	/**
mbed_official	133:d4dda5c437f0	883	* @}
mbed_official	133:d4dda5c437f0	884	*/
mbed_official	133:d4dda5c437f0	885
mbed_official	133:d4dda5c437f0	886	/** @defgroup ETH_Multicast_Frames_Filter
mbed_official	133:d4dda5c437f0	887	* @{
mbed_official	133:d4dda5c437f0	888	*/
mbed_official	133:d4dda5c437f0	889	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
mbed_official	133:d4dda5c437f0	890	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	891	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	892	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	893	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
mbed_official	133:d4dda5c437f0	894	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
mbed_official	133:d4dda5c437f0	895	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
mbed_official	133:d4dda5c437f0	896	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
mbed_official	133:d4dda5c437f0	897	/**
mbed_official	133:d4dda5c437f0	898	* @}
mbed_official	133:d4dda5c437f0	899	*/
mbed_official	133:d4dda5c437f0	900
mbed_official	133:d4dda5c437f0	901	/** @defgroup ETH_Unicast_Frames_Filter
mbed_official	133:d4dda5c437f0	902	* @{
mbed_official	133:d4dda5c437f0	903	*/
mbed_official	133:d4dda5c437f0	904	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
mbed_official	133:d4dda5c437f0	905	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	906	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	907	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
mbed_official	133:d4dda5c437f0	908	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
mbed_official	133:d4dda5c437f0	909	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
mbed_official	133:d4dda5c437f0	910	/**
mbed_official	133:d4dda5c437f0	911	* @}
mbed_official	133:d4dda5c437f0	912	*/
mbed_official	133:d4dda5c437f0	913
mbed_official	133:d4dda5c437f0	914	/** @defgroup ETH_Pause_Time
mbed_official	133:d4dda5c437f0	915	* @{
mbed_official	133:d4dda5c437f0	916	*/
mbed_official	133:d4dda5c437f0	917	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
mbed_official	133:d4dda5c437f0	918
mbed_official	133:d4dda5c437f0	919	/**
mbed_official	133:d4dda5c437f0	920	* @}
mbed_official	133:d4dda5c437f0	921	*/
mbed_official	133:d4dda5c437f0	922
mbed_official	133:d4dda5c437f0	923	/** @defgroup ETH_Zero_Quanta_Pause
mbed_official	133:d4dda5c437f0	924	* @{
mbed_official	133:d4dda5c437f0	925	*/
mbed_official	133:d4dda5c437f0	926	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	927	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
mbed_official	133:d4dda5c437f0	928	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	929	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
mbed_official	133:d4dda5c437f0	930	/**
mbed_official	133:d4dda5c437f0	931	* @}
mbed_official	133:d4dda5c437f0	932	*/
mbed_official	133:d4dda5c437f0	933
mbed_official	133:d4dda5c437f0	934	/** @defgroup ETH_Pause_Low_Threshold
mbed_official	133:d4dda5c437f0	935	* @{
mbed_official	133:d4dda5c437f0	936	*/
mbed_official	133:d4dda5c437f0	937	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
mbed_official	133:d4dda5c437f0	938	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
mbed_official	133:d4dda5c437f0	939	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
mbed_official	133:d4dda5c437f0	940	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
mbed_official	133:d4dda5c437f0	941	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
mbed_official	133:d4dda5c437f0	942	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
mbed_official	133:d4dda5c437f0	943	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
mbed_official	133:d4dda5c437f0	944	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
mbed_official	133:d4dda5c437f0	945	/**
mbed_official	133:d4dda5c437f0	946	* @}
mbed_official	133:d4dda5c437f0	947	*/
mbed_official	133:d4dda5c437f0	948
mbed_official	133:d4dda5c437f0	949	/** @defgroup ETH_Unicast_Pause_Frame_Detect
mbed_official	133:d4dda5c437f0	950	* @{
mbed_official	133:d4dda5c437f0	951	*/
mbed_official	133:d4dda5c437f0	952	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	953	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	954	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	955	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
mbed_official	133:d4dda5c437f0	956	/**
mbed_official	133:d4dda5c437f0	957	* @}
mbed_official	133:d4dda5c437f0	958	*/
mbed_official	133:d4dda5c437f0	959
mbed_official	133:d4dda5c437f0	960	/** @defgroup ETH_Receive_Flow_Control
mbed_official	133:d4dda5c437f0	961	* @{
mbed_official	133:d4dda5c437f0	962	*/
mbed_official	133:d4dda5c437f0	963	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	964	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	965	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	966	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
mbed_official	133:d4dda5c437f0	967	/**
mbed_official	133:d4dda5c437f0	968	* @}
mbed_official	133:d4dda5c437f0	969	*/
mbed_official	133:d4dda5c437f0	970
mbed_official	133:d4dda5c437f0	971	/** @defgroup ETH_Transmit_Flow_Control
mbed_official	133:d4dda5c437f0	972	* @{
mbed_official	133:d4dda5c437f0	973	*/
mbed_official	133:d4dda5c437f0	974	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	975	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	976	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	977	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
mbed_official	133:d4dda5c437f0	978	/**
mbed_official	133:d4dda5c437f0	979	* @}
mbed_official	133:d4dda5c437f0	980	*/
mbed_official	133:d4dda5c437f0	981
mbed_official	133:d4dda5c437f0	982	/** @defgroup ETH_VLAN_Tag_Comparison
mbed_official	133:d4dda5c437f0	983	* @{
mbed_official	133:d4dda5c437f0	984	*/
mbed_official	133:d4dda5c437f0	985	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
mbed_official	133:d4dda5c437f0	986	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	987	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
mbed_official	133:d4dda5c437f0	988	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
mbed_official	133:d4dda5c437f0	989	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
mbed_official	133:d4dda5c437f0	990
mbed_official	133:d4dda5c437f0	991	/**
mbed_official	133:d4dda5c437f0	992	* @}
mbed_official	133:d4dda5c437f0	993	*/
mbed_official	133:d4dda5c437f0	994
mbed_official	133:d4dda5c437f0	995	/** @defgroup ETH_MAC_addresses
mbed_official	133:d4dda5c437f0	996	* @{
mbed_official	133:d4dda5c437f0	997	*/
mbed_official	133:d4dda5c437f0	998	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	999	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	1000	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	1001	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
mbed_official	133:d4dda5c437f0	1002	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
mbed_official	133:d4dda5c437f0	1003	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
mbed_official	133:d4dda5c437f0	1004	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
mbed_official	133:d4dda5c437f0	1005	((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official	133:d4dda5c437f0	1006	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
mbed_official	133:d4dda5c437f0	1007	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
mbed_official	133:d4dda5c437f0	1008	((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official	133:d4dda5c437f0	1009	/**
mbed_official	133:d4dda5c437f0	1010	* @}
mbed_official	133:d4dda5c437f0	1011	*/
mbed_official	133:d4dda5c437f0	1012
mbed_official	133:d4dda5c437f0	1013	/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
mbed_official	133:d4dda5c437f0	1014	* @{
mbed_official	133:d4dda5c437f0	1015	*/
mbed_official	133:d4dda5c437f0	1016	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1017	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	1018	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
mbed_official	133:d4dda5c437f0	1019	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
mbed_official	133:d4dda5c437f0	1020	/**
mbed_official	133:d4dda5c437f0	1021	* @}
mbed_official	133:d4dda5c437f0	1022	*/
mbed_official	133:d4dda5c437f0	1023
mbed_official	133:d4dda5c437f0	1024	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
mbed_official	133:d4dda5c437f0	1025	* @{
mbed_official	133:d4dda5c437f0	1026	*/
mbed_official	133:d4dda5c437f0	1027	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
mbed_official	133:d4dda5c437f0	1028	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
mbed_official	133:d4dda5c437f0	1029	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
mbed_official	133:d4dda5c437f0	1030	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
mbed_official	133:d4dda5c437f0	1031	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
mbed_official	133:d4dda5c437f0	1032	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
mbed_official	133:d4dda5c437f0	1033	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
mbed_official	133:d4dda5c437f0	1034	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
mbed_official	133:d4dda5c437f0	1035	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
mbed_official	133:d4dda5c437f0	1036	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
mbed_official	133:d4dda5c437f0	1037	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
mbed_official	133:d4dda5c437f0	1038	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
mbed_official	133:d4dda5c437f0	1039
mbed_official	133:d4dda5c437f0	1040	/**
mbed_official	133:d4dda5c437f0	1041	* @}
mbed_official	133:d4dda5c437f0	1042	*/
mbed_official	133:d4dda5c437f0	1043
mbed_official	133:d4dda5c437f0	1044	/** @defgroup ETH_MAC_Debug_flags
mbed_official	133:d4dda5c437f0	1045	* @{
mbed_official	133:d4dda5c437f0	1046	*/
mbed_official	133:d4dda5c437f0	1047	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
mbed_official	133:d4dda5c437f0	1048
mbed_official	133:d4dda5c437f0	1049	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
mbed_official	133:d4dda5c437f0	1050
mbed_official	133:d4dda5c437f0	1051	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
mbed_official	133:d4dda5c437f0	1052
mbed_official	133:d4dda5c437f0	1053	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
mbed_official	133:d4dda5c437f0	1054	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
mbed_official	133:d4dda5c437f0	1055	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
mbed_official	133:d4dda5c437f0	1056	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
mbed_official	133:d4dda5c437f0	1057
mbed_official	133:d4dda5c437f0	1058	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
mbed_official	133:d4dda5c437f0	1059
mbed_official	133:d4dda5c437f0	1060	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
mbed_official	133:d4dda5c437f0	1061	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
mbed_official	133:d4dda5c437f0	1062	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
mbed_official	133:d4dda5c437f0	1063	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
mbed_official	133:d4dda5c437f0	1064
mbed_official	133:d4dda5c437f0	1065	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
mbed_official	133:d4dda5c437f0	1066
mbed_official	133:d4dda5c437f0	1067	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
mbed_official	133:d4dda5c437f0	1068	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
mbed_official	133:d4dda5c437f0	1069	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
mbed_official	133:d4dda5c437f0	1070	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
mbed_official	133:d4dda5c437f0	1071
mbed_official	133:d4dda5c437f0	1072	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
mbed_official	133:d4dda5c437f0	1073	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
mbed_official	133:d4dda5c437f0	1074	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
mbed_official	133:d4dda5c437f0	1075	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
mbed_official	133:d4dda5c437f0	1076
mbed_official	133:d4dda5c437f0	1077	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
mbed_official	133:d4dda5c437f0	1078
mbed_official	133:d4dda5c437f0	1079	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
mbed_official	133:d4dda5c437f0	1080	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
mbed_official	133:d4dda5c437f0	1081	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
mbed_official	133:d4dda5c437f0	1082	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
mbed_official	133:d4dda5c437f0	1083
mbed_official	133:d4dda5c437f0	1084	#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
mbed_official	133:d4dda5c437f0	1085
mbed_official	133:d4dda5c437f0	1086	/**
mbed_official	133:d4dda5c437f0	1087	* @}
mbed_official	133:d4dda5c437f0	1088	*/
mbed_official	133:d4dda5c437f0	1089
mbed_official	133:d4dda5c437f0	1090	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
mbed_official	133:d4dda5c437f0	1091	* @{
mbed_official	133:d4dda5c437f0	1092	*/
mbed_official	133:d4dda5c437f0	1093	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1094	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
mbed_official	133:d4dda5c437f0	1095	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1096	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
mbed_official	133:d4dda5c437f0	1097	/**
mbed_official	133:d4dda5c437f0	1098	* @}
mbed_official	133:d4dda5c437f0	1099	*/
mbed_official	133:d4dda5c437f0	1100
mbed_official	133:d4dda5c437f0	1101	/** @defgroup ETH_Receive_Store_Forward
mbed_official	133:d4dda5c437f0	1102	* @{
mbed_official	133:d4dda5c437f0	1103	*/
mbed_official	133:d4dda5c437f0	1104	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
mbed_official	133:d4dda5c437f0	1105	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1106	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1107	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
mbed_official	133:d4dda5c437f0	1108	/**
mbed_official	133:d4dda5c437f0	1109	* @}
mbed_official	133:d4dda5c437f0	1110	*/
mbed_official	133:d4dda5c437f0	1111
mbed_official	133:d4dda5c437f0	1112	/** @defgroup ETH_Flush_Received_Frame
mbed_official	133:d4dda5c437f0	1113	* @{
mbed_official	133:d4dda5c437f0	1114	*/
mbed_official	133:d4dda5c437f0	1115	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1116	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
mbed_official	133:d4dda5c437f0	1117	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1118	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
mbed_official	133:d4dda5c437f0	1119	/**
mbed_official	133:d4dda5c437f0	1120	* @}
mbed_official	133:d4dda5c437f0	1121	*/
mbed_official	133:d4dda5c437f0	1122
mbed_official	133:d4dda5c437f0	1123	/** @defgroup ETH_Transmit_Store_Forward
mbed_official	133:d4dda5c437f0	1124	* @{
mbed_official	133:d4dda5c437f0	1125	*/
mbed_official	133:d4dda5c437f0	1126	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
mbed_official	133:d4dda5c437f0	1127	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1128	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1129	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
mbed_official	133:d4dda5c437f0	1130	/**
mbed_official	133:d4dda5c437f0	1131	* @}
mbed_official	133:d4dda5c437f0	1132	*/
mbed_official	133:d4dda5c437f0	1133
mbed_official	133:d4dda5c437f0	1134	/** @defgroup ETH_Transmit_Threshold_Control
mbed_official	133:d4dda5c437f0	1135	* @{
mbed_official	133:d4dda5c437f0	1136	*/
mbed_official	133:d4dda5c437f0	1137	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
mbed_official	133:d4dda5c437f0	1138	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
mbed_official	133:d4dda5c437f0	1139	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
mbed_official	133:d4dda5c437f0	1140	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
mbed_official	133:d4dda5c437f0	1141	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
mbed_official	133:d4dda5c437f0	1142	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
mbed_official	133:d4dda5c437f0	1143	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
mbed_official	133:d4dda5c437f0	1144	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
mbed_official	133:d4dda5c437f0	1145	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1146	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1147	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1148	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1149	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1150	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1151	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1152	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
mbed_official	133:d4dda5c437f0	1153	/**
mbed_official	133:d4dda5c437f0	1154	* @}
mbed_official	133:d4dda5c437f0	1155	*/
mbed_official	133:d4dda5c437f0	1156
mbed_official	133:d4dda5c437f0	1157	/** @defgroup ETH_Forward_Error_Frames
mbed_official	133:d4dda5c437f0	1158	* @{
mbed_official	133:d4dda5c437f0	1159	*/
mbed_official	133:d4dda5c437f0	1160	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
mbed_official	133:d4dda5c437f0	1161	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1162	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1163	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
mbed_official	133:d4dda5c437f0	1164	/**
mbed_official	133:d4dda5c437f0	1165	* @}
mbed_official	133:d4dda5c437f0	1166	*/
mbed_official	133:d4dda5c437f0	1167
mbed_official	133:d4dda5c437f0	1168	/** @defgroup ETH_Forward_Undersized_Good_Frames
mbed_official	133:d4dda5c437f0	1169	* @{
mbed_official	133:d4dda5c437f0	1170	*/
mbed_official	133:d4dda5c437f0	1171	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
mbed_official	133:d4dda5c437f0	1172	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
mbed_official	133:d4dda5c437f0	1175
mbed_official	133:d4dda5c437f0	1176	/**
mbed_official	133:d4dda5c437f0	1177	* @}
mbed_official	133:d4dda5c437f0	1178	*/
mbed_official	133:d4dda5c437f0	1179
mbed_official	133:d4dda5c437f0	1180	/** @defgroup ETH_Receive_Threshold_Control
mbed_official	133:d4dda5c437f0	1181	* @{
mbed_official	133:d4dda5c437f0	1182	*/
mbed_official	133:d4dda5c437f0	1183	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
mbed_official	133:d4dda5c437f0	1184	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
mbed_official	133:d4dda5c437f0	1185	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
mbed_official	133:d4dda5c437f0	1186	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
mbed_official	133:d4dda5c437f0	1187	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1188	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1189	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
mbed_official	133:d4dda5c437f0	1190	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
mbed_official	133:d4dda5c437f0	1191	/**
mbed_official	133:d4dda5c437f0	1192	* @}
mbed_official	133:d4dda5c437f0	1193	*/
mbed_official	133:d4dda5c437f0	1194
mbed_official	133:d4dda5c437f0	1195	/** @defgroup ETH_Second_Frame_Operate
mbed_official	133:d4dda5c437f0	1196	* @{
mbed_official	133:d4dda5c437f0	1197	*/
mbed_official	133:d4dda5c437f0	1198	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	1199	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1200	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1201	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
mbed_official	133:d4dda5c437f0	1202
mbed_official	133:d4dda5c437f0	1203	/**
mbed_official	133:d4dda5c437f0	1204	* @}
mbed_official	133:d4dda5c437f0	1205	*/
mbed_official	133:d4dda5c437f0	1206
mbed_official	133:d4dda5c437f0	1207	/** @defgroup ETH_Address_Aligned_Beats
mbed_official	133:d4dda5c437f0	1208	* @{
mbed_official	133:d4dda5c437f0	1209	*/
mbed_official	133:d4dda5c437f0	1210	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
mbed_official	133:d4dda5c437f0	1211	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1212	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1213	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
mbed_official	133:d4dda5c437f0	1214
mbed_official	133:d4dda5c437f0	1215	/**
mbed_official	133:d4dda5c437f0	1216	* @}
mbed_official	133:d4dda5c437f0	1217	*/
mbed_official	133:d4dda5c437f0	1218
mbed_official	133:d4dda5c437f0	1219	/** @defgroup ETH_Fixed_Burst
mbed_official	133:d4dda5c437f0	1220	* @{
mbed_official	133:d4dda5c437f0	1221	*/
mbed_official	133:d4dda5c437f0	1222	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
mbed_official	133:d4dda5c437f0	1223	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1224	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1225	((CMD) == ETH_FIXEDBURST_DISABLE))
mbed_official	133:d4dda5c437f0	1226
mbed_official	133:d4dda5c437f0	1227	/**
mbed_official	133:d4dda5c437f0	1228	* @}
mbed_official	133:d4dda5c437f0	1229	*/
mbed_official	133:d4dda5c437f0	1230
mbed_official	133:d4dda5c437f0	1231	/** @defgroup ETH_Rx_DMA_Burst_Length
mbed_official	133:d4dda5c437f0	1232	* @{
mbed_official	133:d4dda5c437f0	1233	*/
mbed_official	133:d4dda5c437f0	1234	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
mbed_official	133:d4dda5c437f0	1235	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
mbed_official	133:d4dda5c437f0	1236	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
mbed_official	133:d4dda5c437f0	1237	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
mbed_official	133:d4dda5c437f0	1238	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
mbed_official	133:d4dda5c437f0	1239	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
mbed_official	133:d4dda5c437f0	1240	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
mbed_official	133:d4dda5c437f0	1241	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
mbed_official	133:d4dda5c437f0	1242	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
mbed_official	133:d4dda5c437f0	1243	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
mbed_official	133:d4dda5c437f0	1244	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
mbed_official	133:d4dda5c437f0	1245	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
mbed_official	133:d4dda5c437f0	1246
mbed_official	133:d4dda5c437f0	1247	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1248	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1249	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1250	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1251	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1252	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1253	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1254	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1255	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1256	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1257	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1258	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official	133:d4dda5c437f0	1259
mbed_official	133:d4dda5c437f0	1260	/**
mbed_official	133:d4dda5c437f0	1261	* @}
mbed_official	133:d4dda5c437f0	1262	*/
mbed_official	133:d4dda5c437f0	1263
mbed_official	133:d4dda5c437f0	1264	/** @defgroup ETH_Tx_DMA_Burst_Length
mbed_official	133:d4dda5c437f0	1265	* @{
mbed_official	133:d4dda5c437f0	1266	*/
mbed_official	133:d4dda5c437f0	1267	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
mbed_official	133:d4dda5c437f0	1268	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
mbed_official	133:d4dda5c437f0	1269	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
mbed_official	133:d4dda5c437f0	1270	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
mbed_official	133:d4dda5c437f0	1271	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
mbed_official	133:d4dda5c437f0	1272	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
mbed_official	133:d4dda5c437f0	1273	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
mbed_official	133:d4dda5c437f0	1274	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
mbed_official	133:d4dda5c437f0	1275	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
mbed_official	133:d4dda5c437f0	1276	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
mbed_official	133:d4dda5c437f0	1277	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
mbed_official	133:d4dda5c437f0	1278	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
mbed_official	133:d4dda5c437f0	1279
mbed_official	133:d4dda5c437f0	1280	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1281	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1282	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1283	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1284	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1285	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1286	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1287	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1288	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1289	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1290	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
mbed_official	133:d4dda5c437f0	1291	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official	133:d4dda5c437f0	1292
mbed_official	242:7074e42da0b2	1293	/** @defgroup ETH_DMA_Enhanced_descriptor_format
mbed_official	242:7074e42da0b2	1294	* @{
mbed_official	242:7074e42da0b2	1295	*/
mbed_official	133:d4dda5c437f0	1296	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
mbed_official	133:d4dda5c437f0	1297	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1298
mbed_official	133:d4dda5c437f0	1299	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	1300	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
mbed_official	133:d4dda5c437f0	1301
mbed_official	133:d4dda5c437f0	1302	/**
mbed_official	133:d4dda5c437f0	1303	* @}
mbed_official	133:d4dda5c437f0	1304	*/
mbed_official	133:d4dda5c437f0	1305
mbed_official	133:d4dda5c437f0	1306	/**
mbed_official	133:d4dda5c437f0	1307	* @brief ETH DMA Descriptor SkipLength
mbed_official	133:d4dda5c437f0	1308	*/
mbed_official	133:d4dda5c437f0	1309	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
mbed_official	133:d4dda5c437f0	1310
mbed_official	133:d4dda5c437f0	1311
mbed_official	133:d4dda5c437f0	1312	/** @defgroup ETH_DMA_Arbitration
mbed_official	133:d4dda5c437f0	1313	* @{
mbed_official	133:d4dda5c437f0	1314	*/
mbed_official	133:d4dda5c437f0	1315	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1316	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
mbed_official	133:d4dda5c437f0	1317	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
mbed_official	133:d4dda5c437f0	1318	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
mbed_official	133:d4dda5c437f0	1319	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	1320	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
mbed_official	133:d4dda5c437f0	1321	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
mbed_official	133:d4dda5c437f0	1322	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
mbed_official	133:d4dda5c437f0	1323	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
mbed_official	133:d4dda5c437f0	1324	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
mbed_official	133:d4dda5c437f0	1325	/**
mbed_official	133:d4dda5c437f0	1326	* @}
mbed_official	133:d4dda5c437f0	1327	*/
mbed_official	133:d4dda5c437f0	1328
mbed_official	133:d4dda5c437f0	1329	/** @defgroup ETH_DMA_Tx_descriptor_flags
mbed_official	133:d4dda5c437f0	1330	* @{
mbed_official	133:d4dda5c437f0	1331	*/
mbed_official	133:d4dda5c437f0	1332	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
mbed_official	133:d4dda5c437f0	1333	((FLAG) == ETH_DMATXDESC_IC) \|\| \
mbed_official	133:d4dda5c437f0	1334	((FLAG) == ETH_DMATXDESC_LS) \|\| \
mbed_official	133:d4dda5c437f0	1335	((FLAG) == ETH_DMATXDESC_FS) \|\| \
mbed_official	133:d4dda5c437f0	1336	((FLAG) == ETH_DMATXDESC_DC) \|\| \
mbed_official	133:d4dda5c437f0	1337	((FLAG) == ETH_DMATXDESC_DP) \|\| \
mbed_official	133:d4dda5c437f0	1338	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
mbed_official	133:d4dda5c437f0	1339	((FLAG) == ETH_DMATXDESC_TER) \|\| \
mbed_official	133:d4dda5c437f0	1340	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
mbed_official	133:d4dda5c437f0	1341	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
mbed_official	133:d4dda5c437f0	1342	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
mbed_official	133:d4dda5c437f0	1343	((FLAG) == ETH_DMATXDESC_ES) \|\| \
mbed_official	133:d4dda5c437f0	1344	((FLAG) == ETH_DMATXDESC_JT) \|\| \
mbed_official	133:d4dda5c437f0	1345	((FLAG) == ETH_DMATXDESC_FF) \|\| \
mbed_official	133:d4dda5c437f0	1346	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
mbed_official	133:d4dda5c437f0	1347	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
mbed_official	133:d4dda5c437f0	1348	((FLAG) == ETH_DMATXDESC_NC) \|\| \
mbed_official	133:d4dda5c437f0	1349	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
mbed_official	133:d4dda5c437f0	1350	((FLAG) == ETH_DMATXDESC_EC) \|\| \
mbed_official	133:d4dda5c437f0	1351	((FLAG) == ETH_DMATXDESC_VF) \|\| \
mbed_official	133:d4dda5c437f0	1352	((FLAG) == ETH_DMATXDESC_CC) \|\| \
mbed_official	133:d4dda5c437f0	1353	((FLAG) == ETH_DMATXDESC_ED) \|\| \
mbed_official	133:d4dda5c437f0	1354	((FLAG) == ETH_DMATXDESC_UF) \|\| \
mbed_official	133:d4dda5c437f0	1355	((FLAG) == ETH_DMATXDESC_DB))
mbed_official	133:d4dda5c437f0	1356
mbed_official	133:d4dda5c437f0	1357	/**
mbed_official	133:d4dda5c437f0	1358	* @}
mbed_official	133:d4dda5c437f0	1359	*/
mbed_official	133:d4dda5c437f0	1360
mbed_official	133:d4dda5c437f0	1361	/** @defgroup ETH_DMA_Tx_descriptor_segment
mbed_official	133:d4dda5c437f0	1362	* @{
mbed_official	133:d4dda5c437f0	1363	*/
mbed_official	133:d4dda5c437f0	1364	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
mbed_official	133:d4dda5c437f0	1365	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
mbed_official	133:d4dda5c437f0	1366	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
mbed_official	133:d4dda5c437f0	1367	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
mbed_official	133:d4dda5c437f0	1368
mbed_official	133:d4dda5c437f0	1369	/**
mbed_official	133:d4dda5c437f0	1370	* @}
mbed_official	133:d4dda5c437f0	1371	*/
mbed_official	133:d4dda5c437f0	1372
mbed_official	133:d4dda5c437f0	1373	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
mbed_official	133:d4dda5c437f0	1374	* @{
mbed_official	133:d4dda5c437f0	1375	*/
mbed_official	133:d4dda5c437f0	1376	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
mbed_official	133:d4dda5c437f0	1377	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
mbed_official	133:d4dda5c437f0	1378	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
mbed_official	133:d4dda5c437f0	1379	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
mbed_official	133:d4dda5c437f0	1380	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
mbed_official	133:d4dda5c437f0	1381	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
mbed_official	133:d4dda5c437f0	1382	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
mbed_official	133:d4dda5c437f0	1383	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
mbed_official	133:d4dda5c437f0	1384	/**
mbed_official	133:d4dda5c437f0	1385	* @brief ETH DMA Tx Desciptor buffer size
mbed_official	133:d4dda5c437f0	1386	*/
mbed_official	133:d4dda5c437f0	1387	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
mbed_official	133:d4dda5c437f0	1388
mbed_official	133:d4dda5c437f0	1389	/**
mbed_official	133:d4dda5c437f0	1390	* @}
mbed_official	133:d4dda5c437f0	1391	*/
mbed_official	133:d4dda5c437f0	1392
mbed_official	133:d4dda5c437f0	1393	/** @defgroup ETH_DMA_Rx_descriptor_flags
mbed_official	133:d4dda5c437f0	1394	* @{
mbed_official	133:d4dda5c437f0	1395	*/
mbed_official	133:d4dda5c437f0	1396	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
mbed_official	133:d4dda5c437f0	1397	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
mbed_official	133:d4dda5c437f0	1398	((FLAG) == ETH_DMARXDESC_ES) \|\| \
mbed_official	133:d4dda5c437f0	1399	((FLAG) == ETH_DMARXDESC_DE) \|\| \
mbed_official	133:d4dda5c437f0	1400	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
mbed_official	133:d4dda5c437f0	1401	((FLAG) == ETH_DMARXDESC_LE) \|\| \
mbed_official	133:d4dda5c437f0	1402	((FLAG) == ETH_DMARXDESC_OE) \|\| \
mbed_official	133:d4dda5c437f0	1403	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
mbed_official	133:d4dda5c437f0	1404	((FLAG) == ETH_DMARXDESC_FS) \|\| \
mbed_official	133:d4dda5c437f0	1405	((FLAG) == ETH_DMARXDESC_LS) \|\| \
mbed_official	133:d4dda5c437f0	1406	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
mbed_official	133:d4dda5c437f0	1407	((FLAG) == ETH_DMARXDESC_LC) \|\| \
mbed_official	133:d4dda5c437f0	1408	((FLAG) == ETH_DMARXDESC_FT) \|\| \
mbed_official	133:d4dda5c437f0	1409	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
mbed_official	133:d4dda5c437f0	1410	((FLAG) == ETH_DMARXDESC_RE) \|\| \
mbed_official	133:d4dda5c437f0	1411	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
mbed_official	133:d4dda5c437f0	1412	((FLAG) == ETH_DMARXDESC_CE) \|\| \
mbed_official	133:d4dda5c437f0	1413	((FLAG) == ETH_DMARXDESC_MAMPCE))
mbed_official	133:d4dda5c437f0	1414
mbed_official	133:d4dda5c437f0	1415	/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
mbed_official	133:d4dda5c437f0	1416	#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) \|\| \
mbed_official	133:d4dda5c437f0	1417	((FLAG) == ETH_DMAPTPRXDESC_PTPFT) \|\| \
mbed_official	133:d4dda5c437f0	1418	((FLAG) == ETH_DMAPTPRXDESC_PTPMT) \|\| \
mbed_official	133:d4dda5c437f0	1419	((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) \|\| \
mbed_official	133:d4dda5c437f0	1420	((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) \|\| \
mbed_official	133:d4dda5c437f0	1421	((FLAG) == ETH_DMAPTPRXDESC_IPCB) \|\| \
mbed_official	133:d4dda5c437f0	1422	((FLAG) == ETH_DMAPTPRXDESC_IPPE) \|\| \
mbed_official	133:d4dda5c437f0	1423	((FLAG) == ETH_DMAPTPRXDESC_IPHE) \|\| \
mbed_official	133:d4dda5c437f0	1424	((FLAG) == ETH_DMAPTPRXDESC_IPPT))
mbed_official	133:d4dda5c437f0	1425
mbed_official	133:d4dda5c437f0	1426	/**
mbed_official	133:d4dda5c437f0	1427	* @}
mbed_official	133:d4dda5c437f0	1428	*/
mbed_official	133:d4dda5c437f0	1429
mbed_official	133:d4dda5c437f0	1430	/** @defgroup ETH_DMA_Rx_descriptor_buffers_
mbed_official	133:d4dda5c437f0	1431	* @{
mbed_official	133:d4dda5c437f0	1432	*/
mbed_official	133:d4dda5c437f0	1433	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
mbed_official	133:d4dda5c437f0	1434	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
mbed_official	133:d4dda5c437f0	1435	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
mbed_official	133:d4dda5c437f0	1436	((BUFFER) == ETH_DMARXDESC_BUFFER2))
mbed_official	133:d4dda5c437f0	1437
mbed_official	133:d4dda5c437f0	1438
mbed_official	133:d4dda5c437f0	1439	/* ETHERNET DMA Tx descriptors Collision Count Shift */
mbed_official	133:d4dda5c437f0	1440	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
mbed_official	133:d4dda5c437f0	1441
mbed_official	133:d4dda5c437f0	1442	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
mbed_official	133:d4dda5c437f0	1443	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official	133:d4dda5c437f0	1444
mbed_official	133:d4dda5c437f0	1445	/* ETHERNET DMA Rx descriptors Frame Length Shift */
mbed_official	133:d4dda5c437f0	1446	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
mbed_official	133:d4dda5c437f0	1447
mbed_official	133:d4dda5c437f0	1448	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
mbed_official	133:d4dda5c437f0	1449	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official	133:d4dda5c437f0	1450
mbed_official	133:d4dda5c437f0	1451	/* ETHERNET DMA Rx descriptors Frame length Shift */
mbed_official	133:d4dda5c437f0	1452	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
mbed_official	133:d4dda5c437f0	1453
mbed_official	133:d4dda5c437f0	1454	/**
mbed_official	133:d4dda5c437f0	1455	* @}
mbed_official	133:d4dda5c437f0	1456	*/
mbed_official	133:d4dda5c437f0	1457
mbed_official	133:d4dda5c437f0	1458	/** @defgroup ETH_PMT_Flags
mbed_official	133:d4dda5c437f0	1459	* @{
mbed_official	133:d4dda5c437f0	1460	*/
mbed_official	133:d4dda5c437f0	1461	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
mbed_official	133:d4dda5c437f0	1462	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
mbed_official	133:d4dda5c437f0	1463	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
mbed_official	133:d4dda5c437f0	1464	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
mbed_official	133:d4dda5c437f0	1465	((FLAG) == ETH_PMT_FLAG_MPR))
mbed_official	133:d4dda5c437f0	1466	/**
mbed_official	133:d4dda5c437f0	1467	* @}
mbed_official	133:d4dda5c437f0	1468	*/
mbed_official	133:d4dda5c437f0	1469
mbed_official	133:d4dda5c437f0	1470	/** @defgroup ETH_MMC_Tx_Interrupts
mbed_official	133:d4dda5c437f0	1471	* @{
mbed_official	133:d4dda5c437f0	1472	*/
mbed_official	133:d4dda5c437f0	1473	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
mbed_official	133:d4dda5c437f0	1474	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
mbed_official	133:d4dda5c437f0	1475	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
mbed_official	133:d4dda5c437f0	1476
mbed_official	133:d4dda5c437f0	1477	/**
mbed_official	133:d4dda5c437f0	1478	* @}
mbed_official	133:d4dda5c437f0	1479	*/
mbed_official	133:d4dda5c437f0	1480
mbed_official	133:d4dda5c437f0	1481	/** @defgroup ETH_MMC_Rx_Interrupts
mbed_official	133:d4dda5c437f0	1482	* @{
mbed_official	133:d4dda5c437f0	1483	*/
mbed_official	133:d4dda5c437f0	1484	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
mbed_official	133:d4dda5c437f0	1485	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
mbed_official	133:d4dda5c437f0	1486	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
mbed_official	133:d4dda5c437f0	1487	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
mbed_official	133:d4dda5c437f0	1488	((IT) != 0x00))
mbed_official	133:d4dda5c437f0	1489	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
mbed_official	133:d4dda5c437f0	1490	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
mbed_official	133:d4dda5c437f0	1491	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
mbed_official	133:d4dda5c437f0	1492	/**
mbed_official	133:d4dda5c437f0	1493	* @}
mbed_official	133:d4dda5c437f0	1494	*/
mbed_official	133:d4dda5c437f0	1495
mbed_official	133:d4dda5c437f0	1496	/** @defgroup ETH_MMC_Registers
mbed_official	133:d4dda5c437f0	1497	* @{
mbed_official	133:d4dda5c437f0	1498	*/
mbed_official	133:d4dda5c437f0	1499	#define ETH_MMCCR ((uint32_t)0x00000100) /!< MMC CR register /
mbed_official	133:d4dda5c437f0	1500	#define ETH_MMCRIR ((uint32_t)0x00000104) /!< MMC RIR register /
mbed_official	133:d4dda5c437f0	1501	#define ETH_MMCTIR ((uint32_t)0x00000108) /!< MMC TIR register /
mbed_official	133:d4dda5c437f0	1502	#define ETH_MMCRIMR ((uint32_t)0x0000010C) /!< MMC RIMR register /
mbed_official	133:d4dda5c437f0	1503	#define ETH_MMCTIMR ((uint32_t)0x00000110) /!< MMC TIMR register /
mbed_official	133:d4dda5c437f0	1504	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /!< MMC TGFSCCR register /
mbed_official	133:d4dda5c437f0	1505	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /!< MMC TGFMSCCR register /
mbed_official	133:d4dda5c437f0	1506	#define ETH_MMCTGFCR ((uint32_t)0x00000168) /!< MMC TGFCR register /
mbed_official	133:d4dda5c437f0	1507	#define ETH_MMCRFCECR ((uint32_t)0x00000194) /!< MMC RFCECR register /
mbed_official	133:d4dda5c437f0	1508	#define ETH_MMCRFAECR ((uint32_t)0x00000198) /!< MMC RFAECR register /
mbed_official	133:d4dda5c437f0	1509	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /!< MMC RGUFCR register /
mbed_official	133:d4dda5c437f0	1510
mbed_official	133:d4dda5c437f0	1511	/**
mbed_official	133:d4dda5c437f0	1512	* @brief ETH MMC registers
mbed_official	133:d4dda5c437f0	1513	*/
mbed_official	133:d4dda5c437f0	1514	#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) \|\| ((REG) == ETH_MMCRIR) \|\| \
mbed_official	133:d4dda5c437f0	1515	((REG) == ETH_MMCTIR) \|\| ((REG) == ETH_MMCRIMR) \|\| \
mbed_official	133:d4dda5c437f0	1516	((REG) == ETH_MMCTIMR) \|\| ((REG) == ETH_MMCTGFSCCR) \|\| \
mbed_official	133:d4dda5c437f0	1517	((REG) == ETH_MMCTGFMSCCR) \|\| ((REG) == ETH_MMCTGFCR) \|\| \
mbed_official	133:d4dda5c437f0	1518	((REG) == ETH_MMCRFCECR) \|\| ((REG) == ETH_MMCRFAECR) \|\| \
mbed_official	133:d4dda5c437f0	1519	((REG) == ETH_MMCRGUFCR))
mbed_official	133:d4dda5c437f0	1520	/**
mbed_official	133:d4dda5c437f0	1521	* @}
mbed_official	133:d4dda5c437f0	1522	*/
mbed_official	133:d4dda5c437f0	1523
mbed_official	133:d4dda5c437f0	1524	/** @defgroup ETH_MAC_Flags
mbed_official	133:d4dda5c437f0	1525	* @{
mbed_official	133:d4dda5c437f0	1526	*/
mbed_official	133:d4dda5c437f0	1527	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
mbed_official	133:d4dda5c437f0	1528	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
mbed_official	133:d4dda5c437f0	1529	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
mbed_official	133:d4dda5c437f0	1530	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
mbed_official	133:d4dda5c437f0	1531	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
mbed_official	133:d4dda5c437f0	1532	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
mbed_official	133:d4dda5c437f0	1533	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
mbed_official	133:d4dda5c437f0	1534	((FLAG) == ETH_MAC_FLAG_PMT))
mbed_official	133:d4dda5c437f0	1535	/**
mbed_official	133:d4dda5c437f0	1536	* @}
mbed_official	133:d4dda5c437f0	1537	*/
mbed_official	133:d4dda5c437f0	1538
mbed_official	133:d4dda5c437f0	1539	/** @defgroup ETH_DMA_Flags
mbed_official	133:d4dda5c437f0	1540	* @{
mbed_official	133:d4dda5c437f0	1541	*/
mbed_official	133:d4dda5c437f0	1542	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
mbed_official	133:d4dda5c437f0	1543	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
mbed_official	133:d4dda5c437f0	1544	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
mbed_official	133:d4dda5c437f0	1545	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
mbed_official	133:d4dda5c437f0	1546	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
mbed_official	133:d4dda5c437f0	1547	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
mbed_official	133:d4dda5c437f0	1548	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
mbed_official	133:d4dda5c437f0	1549	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
mbed_official	133:d4dda5c437f0	1550	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
mbed_official	133:d4dda5c437f0	1551	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
mbed_official	133:d4dda5c437f0	1552	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
mbed_official	133:d4dda5c437f0	1553	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
mbed_official	133:d4dda5c437f0	1554	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
mbed_official	133:d4dda5c437f0	1555	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
mbed_official	133:d4dda5c437f0	1556	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
mbed_official	133:d4dda5c437f0	1557	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
mbed_official	133:d4dda5c437f0	1558	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
mbed_official	133:d4dda5c437f0	1559	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
mbed_official	133:d4dda5c437f0	1560	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
mbed_official	133:d4dda5c437f0	1561	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
mbed_official	133:d4dda5c437f0	1562	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
mbed_official	133:d4dda5c437f0	1563
mbed_official	133:d4dda5c437f0	1564	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
mbed_official	133:d4dda5c437f0	1565	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
mbed_official	133:d4dda5c437f0	1566	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
mbed_official	133:d4dda5c437f0	1567	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
mbed_official	133:d4dda5c437f0	1568	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
mbed_official	133:d4dda5c437f0	1569	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
mbed_official	133:d4dda5c437f0	1570	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
mbed_official	133:d4dda5c437f0	1571	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
mbed_official	133:d4dda5c437f0	1572	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
mbed_official	133:d4dda5c437f0	1573	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
mbed_official	133:d4dda5c437f0	1574	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
mbed_official	133:d4dda5c437f0	1575	((FLAG) == ETH_DMA_FLAG_T))
mbed_official	133:d4dda5c437f0	1576	/**
mbed_official	133:d4dda5c437f0	1577	* @}
mbed_official	133:d4dda5c437f0	1578	*/
mbed_official	133:d4dda5c437f0	1579
mbed_official	133:d4dda5c437f0	1580	/** @defgroup ETH_MAC_Interrupts
mbed_official	133:d4dda5c437f0	1581	* @{
mbed_official	133:d4dda5c437f0	1582	*/
mbed_official	133:d4dda5c437f0	1583	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
mbed_official	133:d4dda5c437f0	1584	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
mbed_official	133:d4dda5c437f0	1585	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
mbed_official	133:d4dda5c437f0	1586	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
mbed_official	133:d4dda5c437f0	1587	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
mbed_official	133:d4dda5c437f0	1588	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
mbed_official	133:d4dda5c437f0	1589	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
mbed_official	133:d4dda5c437f0	1590	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
mbed_official	133:d4dda5c437f0	1591	((IT) == ETH_MAC_IT_PMT))
mbed_official	133:d4dda5c437f0	1592	/**
mbed_official	133:d4dda5c437f0	1593	* @}
mbed_official	133:d4dda5c437f0	1594	*/
mbed_official	133:d4dda5c437f0	1595
mbed_official	133:d4dda5c437f0	1596	/** @defgroup ETH_DMA_Interrupts
mbed_official	133:d4dda5c437f0	1597	* @{
mbed_official	133:d4dda5c437f0	1598	*/
mbed_official	133:d4dda5c437f0	1599	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
mbed_official	133:d4dda5c437f0	1600	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
mbed_official	133:d4dda5c437f0	1601	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
mbed_official	133:d4dda5c437f0	1602	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
mbed_official	133:d4dda5c437f0	1603	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
mbed_official	133:d4dda5c437f0	1604	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
mbed_official	133:d4dda5c437f0	1605	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
mbed_official	133:d4dda5c437f0	1606	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
mbed_official	133:d4dda5c437f0	1607	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
mbed_official	133:d4dda5c437f0	1608	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
mbed_official	133:d4dda5c437f0	1609	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
mbed_official	133:d4dda5c437f0	1610	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
mbed_official	133:d4dda5c437f0	1611	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
mbed_official	133:d4dda5c437f0	1612	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
mbed_official	133:d4dda5c437f0	1613	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
mbed_official	133:d4dda5c437f0	1614	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
mbed_official	133:d4dda5c437f0	1615	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
mbed_official	133:d4dda5c437f0	1616	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
mbed_official	133:d4dda5c437f0	1617
mbed_official	133:d4dda5c437f0	1618	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
mbed_official	133:d4dda5c437f0	1619	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
mbed_official	133:d4dda5c437f0	1620	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
mbed_official	133:d4dda5c437f0	1621	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
mbed_official	133:d4dda5c437f0	1622	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
mbed_official	133:d4dda5c437f0	1623	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
mbed_official	133:d4dda5c437f0	1624	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
mbed_official	133:d4dda5c437f0	1625	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
mbed_official	133:d4dda5c437f0	1626	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
mbed_official	133:d4dda5c437f0	1627	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
mbed_official	133:d4dda5c437f0	1628
mbed_official	133:d4dda5c437f0	1629	/**
mbed_official	133:d4dda5c437f0	1630	* @}
mbed_official	133:d4dda5c437f0	1631	*/
mbed_official	133:d4dda5c437f0	1632
mbed_official	133:d4dda5c437f0	1633	/** @defgroup ETH_DMA_transmit_process_state_
mbed_official	133:d4dda5c437f0	1634	* @{
mbed_official	133:d4dda5c437f0	1635	*/
mbed_official	133:d4dda5c437f0	1636	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
mbed_official	133:d4dda5c437f0	1637	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
mbed_official	133:d4dda5c437f0	1638	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
mbed_official	133:d4dda5c437f0	1639	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
mbed_official	133:d4dda5c437f0	1640	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
mbed_official	133:d4dda5c437f0	1641	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
mbed_official	133:d4dda5c437f0	1642
mbed_official	133:d4dda5c437f0	1643	/**
mbed_official	133:d4dda5c437f0	1644	* @}
mbed_official	133:d4dda5c437f0	1645	*/
mbed_official	133:d4dda5c437f0	1646
mbed_official	133:d4dda5c437f0	1647
mbed_official	133:d4dda5c437f0	1648	/** @defgroup ETH_DMA_receive_process_state_
mbed_official	133:d4dda5c437f0	1649	* @{
mbed_official	133:d4dda5c437f0	1650	*/
mbed_official	133:d4dda5c437f0	1651	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
mbed_official	133:d4dda5c437f0	1652	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
mbed_official	133:d4dda5c437f0	1653	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
mbed_official	133:d4dda5c437f0	1654	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
mbed_official	133:d4dda5c437f0	1655	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
mbed_official	133:d4dda5c437f0	1656	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
mbed_official	133:d4dda5c437f0	1657
mbed_official	133:d4dda5c437f0	1658	/**
mbed_official	133:d4dda5c437f0	1659	* @}
mbed_official	133:d4dda5c437f0	1660	*/
mbed_official	133:d4dda5c437f0	1661
mbed_official	133:d4dda5c437f0	1662	/** @defgroup ETH_DMA_overflow_
mbed_official	133:d4dda5c437f0	1663	* @{
mbed_official	133:d4dda5c437f0	1664	*/
mbed_official	133:d4dda5c437f0	1665	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
mbed_official	133:d4dda5c437f0	1666	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
mbed_official	133:d4dda5c437f0	1667	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
mbed_official	133:d4dda5c437f0	1668	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
mbed_official	133:d4dda5c437f0	1669	/**
mbed_official	133:d4dda5c437f0	1670	* @}
mbed_official	133:d4dda5c437f0	1671	*/
mbed_official	133:d4dda5c437f0	1672
mbed_official	133:d4dda5c437f0	1673	/* ETHERNET MAC address offsets */
mbed_official	133:d4dda5c437f0	1674	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
mbed_official	133:d4dda5c437f0	1675	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
mbed_official	133:d4dda5c437f0	1676
mbed_official	133:d4dda5c437f0	1677	/* ETHERNET MACMIIAR register Mask */
mbed_official	133:d4dda5c437f0	1678	#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
mbed_official	133:d4dda5c437f0	1679
mbed_official	133:d4dda5c437f0	1680	/* ETHERNET MACCR register Mask */
mbed_official	133:d4dda5c437f0	1681	#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
mbed_official	133:d4dda5c437f0	1682
mbed_official	133:d4dda5c437f0	1683	/* ETHERNET MACFCR register Mask */
mbed_official	133:d4dda5c437f0	1684	#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
mbed_official	133:d4dda5c437f0	1685
mbed_official	133:d4dda5c437f0	1686
mbed_official	133:d4dda5c437f0	1687	/* ETHERNET DMAOMR register Mask */
mbed_official	133:d4dda5c437f0	1688	#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
mbed_official	133:d4dda5c437f0	1689
mbed_official	133:d4dda5c437f0	1690
mbed_official	133:d4dda5c437f0	1691	/* ETHERNET Remote Wake-up frame register length */
mbed_official	133:d4dda5c437f0	1692	#define ETH_WAKEUP_REGISTER_LENGTH 8
mbed_official	133:d4dda5c437f0	1693
mbed_official	133:d4dda5c437f0	1694	/* ETHERNET Missed frames counter Shift */
mbed_official	133:d4dda5c437f0	1695	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
mbed_official	133:d4dda5c437f0	1696
mbed_official	133:d4dda5c437f0	1697	/**
mbed_official	133:d4dda5c437f0	1698	* @}
mbed_official	133:d4dda5c437f0	1699	*/
mbed_official	133:d4dda5c437f0	1700
mbed_official	133:d4dda5c437f0	1701	/* Exported macro ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	1702
mbed_official	242:7074e42da0b2	1703	/** @brief Reset ETH handle state
mbed_official	242:7074e42da0b2	1704	* @param __HANDLE__: specifies the ETH handle.
mbed_official	242:7074e42da0b2	1705	* @retval None
mbed_official	242:7074e42da0b2	1706	*/
mbed_official	242:7074e42da0b2	1707	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
mbed_official	242:7074e42da0b2	1708
mbed_official	133:d4dda5c437f0	1709	/**
mbed_official	133:d4dda5c437f0	1710	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
mbed_official	133:d4dda5c437f0	1711	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1712	* @param __FLAG__: specifies the flag to check.
mbed_official	133:d4dda5c437f0	1713	* @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official	133:d4dda5c437f0	1714	*/
mbed_official	133:d4dda5c437f0	1715	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official	133:d4dda5c437f0	1716
mbed_official	133:d4dda5c437f0	1717	/**
mbed_official	133:d4dda5c437f0	1718	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
mbed_official	133:d4dda5c437f0	1719	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1720	* @param __FLAG__: specifies the flag to check.
mbed_official	133:d4dda5c437f0	1721	* @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official	133:d4dda5c437f0	1722	*/
mbed_official	133:d4dda5c437f0	1723	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official	133:d4dda5c437f0	1724
mbed_official	133:d4dda5c437f0	1725	/**
mbed_official	133:d4dda5c437f0	1726	* @brief Enables the specified DMA Rx Desc receive interrupt.
mbed_official	133:d4dda5c437f0	1727	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1728	* @retval None
mbed_official	133:d4dda5c437f0	1729	*/
mbed_official	133:d4dda5c437f0	1730	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
mbed_official	133:d4dda5c437f0	1731
mbed_official	133:d4dda5c437f0	1732	/**
mbed_official	133:d4dda5c437f0	1733	* @brief Disables the specified DMA Rx Desc receive interrupt.
mbed_official	133:d4dda5c437f0	1734	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1735	* @retval None
mbed_official	133:d4dda5c437f0	1736	*/
mbed_official	133:d4dda5c437f0	1737	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
mbed_official	133:d4dda5c437f0	1738
mbed_official	133:d4dda5c437f0	1739	/**
mbed_official	133:d4dda5c437f0	1740	* @brief Set the specified DMA Rx Desc Own bit.
mbed_official	133:d4dda5c437f0	1741	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1742	* @retval None
mbed_official	133:d4dda5c437f0	1743	*/
mbed_official	133:d4dda5c437f0	1744	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
mbed_official	133:d4dda5c437f0	1745
mbed_official	133:d4dda5c437f0	1746	/**
mbed_official	133:d4dda5c437f0	1747	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
mbed_official	133:d4dda5c437f0	1748	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1749	* @retval The Transmit descriptor collision counter value.
mbed_official	133:d4dda5c437f0	1750	*/
mbed_official	133:d4dda5c437f0	1751	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
mbed_official	133:d4dda5c437f0	1752
mbed_official	133:d4dda5c437f0	1753	/**
mbed_official	133:d4dda5c437f0	1754	* @brief Set the specified DMA Tx Desc Own bit.
mbed_official	133:d4dda5c437f0	1755	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1756	* @retval None
mbed_official	133:d4dda5c437f0	1757	*/
mbed_official	133:d4dda5c437f0	1758	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
mbed_official	133:d4dda5c437f0	1759
mbed_official	133:d4dda5c437f0	1760	/**
mbed_official	133:d4dda5c437f0	1761	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
mbed_official	133:d4dda5c437f0	1762	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1763	* @retval None
mbed_official	133:d4dda5c437f0	1764	*/
mbed_official	133:d4dda5c437f0	1765	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
mbed_official	133:d4dda5c437f0	1766
mbed_official	133:d4dda5c437f0	1767	/**
mbed_official	133:d4dda5c437f0	1768	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
mbed_official	133:d4dda5c437f0	1769	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1770	* @retval None
mbed_official	133:d4dda5c437f0	1771	*/
mbed_official	133:d4dda5c437f0	1772	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
mbed_official	133:d4dda5c437f0	1773
mbed_official	133:d4dda5c437f0	1774	/**
mbed_official	133:d4dda5c437f0	1775	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
mbed_official	133:d4dda5c437f0	1776	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1777	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
mbed_official	133:d4dda5c437f0	1778	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1779	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
mbed_official	133:d4dda5c437f0	1780	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
mbed_official	133:d4dda5c437f0	1781	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
mbed_official	133:d4dda5c437f0	1782	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
mbed_official	133:d4dda5c437f0	1783	* @retval None
mbed_official	133:d4dda5c437f0	1784	*/
mbed_official	133:d4dda5c437f0	1785	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
mbed_official	133:d4dda5c437f0	1786
mbed_official	133:d4dda5c437f0	1787	/**
mbed_official	133:d4dda5c437f0	1788	* @brief Enables the DMA Tx Desc CRC.
mbed_official	133:d4dda5c437f0	1789	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1790	* @retval None
mbed_official	133:d4dda5c437f0	1791	*/
mbed_official	133:d4dda5c437f0	1792	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
mbed_official	133:d4dda5c437f0	1793
mbed_official	133:d4dda5c437f0	1794	/**
mbed_official	133:d4dda5c437f0	1795	* @brief Disables the DMA Tx Desc CRC.
mbed_official	133:d4dda5c437f0	1796	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1797	* @retval None
mbed_official	133:d4dda5c437f0	1798	*/
mbed_official	133:d4dda5c437f0	1799	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
mbed_official	133:d4dda5c437f0	1800
mbed_official	133:d4dda5c437f0	1801	/**
mbed_official	133:d4dda5c437f0	1802	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official	133:d4dda5c437f0	1803	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1804	* @retval None
mbed_official	133:d4dda5c437f0	1805	*/
mbed_official	133:d4dda5c437f0	1806	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
mbed_official	133:d4dda5c437f0	1807
mbed_official	133:d4dda5c437f0	1808	/**
mbed_official	133:d4dda5c437f0	1809	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official	133:d4dda5c437f0	1810	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1811	* @retval None
mbed_official	133:d4dda5c437f0	1812	*/
mbed_official	133:d4dda5c437f0	1813	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
mbed_official	133:d4dda5c437f0	1814
mbed_official	133:d4dda5c437f0	1815	/**
mbed_official	133:d4dda5c437f0	1816	* @brief Enables the specified ETHERNET MAC interrupts.
mbed_official	133:d4dda5c437f0	1817	* @param __HANDLE__ : ETH Handle
mbed_official	133:d4dda5c437f0	1818	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official	133:d4dda5c437f0	1819	* enabled or disabled.
mbed_official	133:d4dda5c437f0	1820	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1821	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official	133:d4dda5c437f0	1822	* @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official	133:d4dda5c437f0	1823	* @retval None
mbed_official	133:d4dda5c437f0	1824	*/
mbed_official	133:d4dda5c437f0	1825	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1826
mbed_official	133:d4dda5c437f0	1827	/**
mbed_official	133:d4dda5c437f0	1828	* @brief Disables the specified ETHERNET MAC interrupts.
mbed_official	133:d4dda5c437f0	1829	* @param __HANDLE__ : ETH Handle
mbed_official	133:d4dda5c437f0	1830	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official	133:d4dda5c437f0	1831	* enabled or disabled.
mbed_official	133:d4dda5c437f0	1832	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1833	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official	133:d4dda5c437f0	1834	* @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official	133:d4dda5c437f0	1835	* @retval None
mbed_official	133:d4dda5c437f0	1836	*/
mbed_official	133:d4dda5c437f0	1837	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1838
mbed_official	133:d4dda5c437f0	1839	/**
mbed_official	133:d4dda5c437f0	1840	* @brief Initiate a Pause Control Frame (Full-duplex only).
mbed_official	133:d4dda5c437f0	1841	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1842	* @retval None
mbed_official	133:d4dda5c437f0	1843	*/
mbed_official	133:d4dda5c437f0	1844	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
mbed_official	133:d4dda5c437f0	1845
mbed_official	133:d4dda5c437f0	1846	/**
mbed_official	133:d4dda5c437f0	1847	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
mbed_official	133:d4dda5c437f0	1848	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1849	* @retval The new state of flow control busy status bit (SET or RESET).
mbed_official	133:d4dda5c437f0	1850	*/
mbed_official	133:d4dda5c437f0	1851	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
mbed_official	133:d4dda5c437f0	1852
mbed_official	133:d4dda5c437f0	1853	/**
mbed_official	133:d4dda5c437f0	1854	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
mbed_official	133:d4dda5c437f0	1855	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1856	* @retval None
mbed_official	133:d4dda5c437f0	1857	*/
mbed_official	133:d4dda5c437f0	1858	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
mbed_official	133:d4dda5c437f0	1859
mbed_official	133:d4dda5c437f0	1860	/**
mbed_official	133:d4dda5c437f0	1861	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
mbed_official	133:d4dda5c437f0	1862	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1863	* @retval None
mbed_official	133:d4dda5c437f0	1864	*/
mbed_official	133:d4dda5c437f0	1865	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
mbed_official	133:d4dda5c437f0	1866
mbed_official	133:d4dda5c437f0	1867	/**
mbed_official	133:d4dda5c437f0	1868	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
mbed_official	133:d4dda5c437f0	1869	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1870	* @param __FLAG__: specifies the flag to check.
mbed_official	133:d4dda5c437f0	1871	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1872	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
mbed_official	133:d4dda5c437f0	1873	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
mbed_official	133:d4dda5c437f0	1874	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
mbed_official	133:d4dda5c437f0	1875	* @arg ETH_MAC_FLAG_MMC : MMC flag
mbed_official	133:d4dda5c437f0	1876	* @arg ETH_MAC_FLAG_PMT : PMT flag
mbed_official	133:d4dda5c437f0	1877	* @retval The state of ETHERNET MAC flag.
mbed_official	133:d4dda5c437f0	1878	*/
mbed_official	133:d4dda5c437f0	1879	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
mbed_official	133:d4dda5c437f0	1880
mbed_official	133:d4dda5c437f0	1881	/**
mbed_official	133:d4dda5c437f0	1882	* @brief Clears the specified ETHERNET MAC flag.
mbed_official	133:d4dda5c437f0	1883	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1884	* @param __FLAG__: specifies the flag to clear.
mbed_official	133:d4dda5c437f0	1885	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1886	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
mbed_official	133:d4dda5c437f0	1887	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
mbed_official	133:d4dda5c437f0	1888	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
mbed_official	133:d4dda5c437f0	1889	* @arg ETH_MAC_FLAG_MMC : MMC flag
mbed_official	133:d4dda5c437f0	1890	* @arg ETH_MAC_FLAG_PMT : PMT flag
mbed_official	133:d4dda5c437f0	1891	* @retval None.
mbed_official	133:d4dda5c437f0	1892	*/
mbed_official	133:d4dda5c437f0	1893	#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__))
mbed_official	133:d4dda5c437f0	1894
mbed_official	133:d4dda5c437f0	1895	/**
mbed_official	133:d4dda5c437f0	1896	* @brief Enables the specified ETHERNET DMA interrupts.
mbed_official	133:d4dda5c437f0	1897	* @param __HANDLE__ : ETH Handle
mbed_official	133:d4dda5c437f0	1898	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official	133:d4dda5c437f0	1899	* enabled @defgroup ETH_DMA_Interrupts
mbed_official	133:d4dda5c437f0	1900	* @retval None
mbed_official	133:d4dda5c437f0	1901	*/
mbed_official	133:d4dda5c437f0	1902	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1903
mbed_official	133:d4dda5c437f0	1904	/**
mbed_official	133:d4dda5c437f0	1905	* @brief Disables the specified ETHERNET DMA interrupts.
mbed_official	133:d4dda5c437f0	1906	* @param __HANDLE__ : ETH Handle
mbed_official	133:d4dda5c437f0	1907	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official	133:d4dda5c437f0	1908	* disabled. @defgroup ETH_DMA_Interrupts
mbed_official	133:d4dda5c437f0	1909	* @retval None
mbed_official	133:d4dda5c437f0	1910	*/
mbed_official	133:d4dda5c437f0	1911	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1912
mbed_official	133:d4dda5c437f0	1913	/**
mbed_official	133:d4dda5c437f0	1914	* @brief Clears the ETHERNET DMA IT pending bit.
mbed_official	133:d4dda5c437f0	1915	* @param __HANDLE__ : ETH Handle
mbed_official	133:d4dda5c437f0	1916	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
mbed_official	133:d4dda5c437f0	1917	* @retval None
mbed_official	133:d4dda5c437f0	1918	*/
mbed_official	133:d4dda5c437f0	1919	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1920
mbed_official	133:d4dda5c437f0	1921	/**
mbed_official	133:d4dda5c437f0	1922	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official	133:d4dda5c437f0	1923	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1924	* @param __FLAG__: specifies the flag to check.
mbed_official	133:d4dda5c437f0	1925	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official	133:d4dda5c437f0	1926	*/
mbed_official	133:d4dda5c437f0	1927	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
mbed_official	133:d4dda5c437f0	1928
mbed_official	133:d4dda5c437f0	1929	/**
mbed_official	133:d4dda5c437f0	1930	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official	133:d4dda5c437f0	1931	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1932	* @param __FLAG__: specifies the flag to clear.
mbed_official	133:d4dda5c437f0	1933	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official	133:d4dda5c437f0	1934	*/
mbed_official	133:d4dda5c437f0	1935	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__))
mbed_official	133:d4dda5c437f0	1936
mbed_official	133:d4dda5c437f0	1937	/**
mbed_official	133:d4dda5c437f0	1938	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
mbed_official	133:d4dda5c437f0	1939	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1940	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
mbed_official	133:d4dda5c437f0	1941	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1942	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
mbed_official	133:d4dda5c437f0	1943	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
mbed_official	133:d4dda5c437f0	1944	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
mbed_official	133:d4dda5c437f0	1945	*/
mbed_official	133:d4dda5c437f0	1946	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
mbed_official	133:d4dda5c437f0	1947
mbed_official	133:d4dda5c437f0	1948	/**
mbed_official	133:d4dda5c437f0	1949	* @brief Set the DMA Receive status watchdog timer register value
mbed_official	133:d4dda5c437f0	1950	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	1951	* @param __VALUE__: DMA Receive status watchdog timer register value
mbed_official	133:d4dda5c437f0	1952	* @retval None
mbed_official	133:d4dda5c437f0	1953	*/
mbed_official	133:d4dda5c437f0	1954	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
mbed_official	133:d4dda5c437f0	1955
mbed_official	133:d4dda5c437f0	1956	/**
mbed_official	133:d4dda5c437f0	1957	* @brief Enables any unicast packet filtered by the MAC address
mbed_official	133:d4dda5c437f0	1958	* recognition to be a wake-up frame.
mbed_official	133:d4dda5c437f0	1959	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	1960	* @retval None
mbed_official	133:d4dda5c437f0	1961	*/
mbed_official	133:d4dda5c437f0	1962	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
mbed_official	133:d4dda5c437f0	1963
mbed_official	133:d4dda5c437f0	1964	/**
mbed_official	133:d4dda5c437f0	1965	* @brief Disables any unicast packet filtered by the MAC address
mbed_official	133:d4dda5c437f0	1966	* recognition to be a wake-up frame.
mbed_official	133:d4dda5c437f0	1967	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	1968	* @retval None
mbed_official	133:d4dda5c437f0	1969	*/
mbed_official	133:d4dda5c437f0	1970	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
mbed_official	133:d4dda5c437f0	1971
mbed_official	133:d4dda5c437f0	1972	/**
mbed_official	133:d4dda5c437f0	1973	* @brief Enables the MAC Wake-Up Frame Detection.
mbed_official	133:d4dda5c437f0	1974	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	1975	* @retval None
mbed_official	133:d4dda5c437f0	1976	*/
mbed_official	133:d4dda5c437f0	1977	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
mbed_official	133:d4dda5c437f0	1978
mbed_official	133:d4dda5c437f0	1979	/**
mbed_official	133:d4dda5c437f0	1980	* @brief Disables the MAC Wake-Up Frame Detection.
mbed_official	133:d4dda5c437f0	1981	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	1982	* @retval None
mbed_official	133:d4dda5c437f0	1983	*/
mbed_official	133:d4dda5c437f0	1984	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official	133:d4dda5c437f0	1985
mbed_official	133:d4dda5c437f0	1986	/**
mbed_official	133:d4dda5c437f0	1987	* @brief Enables the MAC Magic Packet Detection.
mbed_official	133:d4dda5c437f0	1988	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	1989	* @retval None
mbed_official	133:d4dda5c437f0	1990	*/
mbed_official	133:d4dda5c437f0	1991	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
mbed_official	133:d4dda5c437f0	1992
mbed_official	133:d4dda5c437f0	1993	/**
mbed_official	133:d4dda5c437f0	1994	* @brief Disables the MAC Magic Packet Detection.
mbed_official	133:d4dda5c437f0	1995	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	1996	* @retval None
mbed_official	133:d4dda5c437f0	1997	*/
mbed_official	133:d4dda5c437f0	1998	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official	133:d4dda5c437f0	1999
mbed_official	133:d4dda5c437f0	2000	/**
mbed_official	133:d4dda5c437f0	2001	* @brief Enables the MAC Power Down.
mbed_official	133:d4dda5c437f0	2002	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	2003	* @retval None
mbed_official	133:d4dda5c437f0	2004	*/
mbed_official	133:d4dda5c437f0	2005	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
mbed_official	133:d4dda5c437f0	2006
mbed_official	133:d4dda5c437f0	2007	/**
mbed_official	133:d4dda5c437f0	2008	* @brief Disables the MAC Power Down.
mbed_official	133:d4dda5c437f0	2009	* @param __HANDLE__: ETH Handle
mbed_official	133:d4dda5c437f0	2010	* @retval None
mbed_official	133:d4dda5c437f0	2011	*/
mbed_official	133:d4dda5c437f0	2012	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
mbed_official	133:d4dda5c437f0	2013
mbed_official	133:d4dda5c437f0	2014	/**
mbed_official	133:d4dda5c437f0	2015	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
mbed_official	133:d4dda5c437f0	2016	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2017	* @param __FLAG__: specifies the flag to check.
mbed_official	133:d4dda5c437f0	2018	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	2019	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
mbed_official	133:d4dda5c437f0	2020	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
mbed_official	133:d4dda5c437f0	2021	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
mbed_official	133:d4dda5c437f0	2022	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
mbed_official	133:d4dda5c437f0	2023	*/
mbed_official	133:d4dda5c437f0	2024	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
mbed_official	133:d4dda5c437f0	2025
mbed_official	133:d4dda5c437f0	2026	/**
mbed_official	133:d4dda5c437f0	2027	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
mbed_official	133:d4dda5c437f0	2028	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2029	* @retval None
mbed_official	133:d4dda5c437f0	2030	*/
mbed_official	133:d4dda5c437f0	2031	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
mbed_official	133:d4dda5c437f0	2032
mbed_official	133:d4dda5c437f0	2033	/**
mbed_official	133:d4dda5c437f0	2034	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
mbed_official	133:d4dda5c437f0	2035	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2036	* @retval None
mbed_official	133:d4dda5c437f0	2037	*/
mbed_official	133:d4dda5c437f0	2038	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
mbed_official	133:d4dda5c437f0	2039	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
mbed_official	133:d4dda5c437f0	2040
mbed_official	133:d4dda5c437f0	2041	/**
mbed_official	133:d4dda5c437f0	2042	* @brief Enables the MMC Counter Freeze.
mbed_official	133:d4dda5c437f0	2043	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2044	* @retval None
mbed_official	133:d4dda5c437f0	2045	*/
mbed_official	133:d4dda5c437f0	2046	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
mbed_official	133:d4dda5c437f0	2047
mbed_official	133:d4dda5c437f0	2048	/**
mbed_official	133:d4dda5c437f0	2049	* @brief Disables the MMC Counter Freeze.
mbed_official	133:d4dda5c437f0	2050	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2051	* @retval None
mbed_official	133:d4dda5c437f0	2052	*/
mbed_official	133:d4dda5c437f0	2053	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
mbed_official	133:d4dda5c437f0	2054
mbed_official	133:d4dda5c437f0	2055	/**
mbed_official	133:d4dda5c437f0	2056	* @brief Enables the MMC Reset On Read.
mbed_official	133:d4dda5c437f0	2057	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2058	* @retval None
mbed_official	133:d4dda5c437f0	2059	*/
mbed_official	133:d4dda5c437f0	2060	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
mbed_official	133:d4dda5c437f0	2061
mbed_official	133:d4dda5c437f0	2062	/**
mbed_official	133:d4dda5c437f0	2063	* @brief Disables the MMC Reset On Read.
mbed_official	133:d4dda5c437f0	2064	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2065	* @retval None
mbed_official	133:d4dda5c437f0	2066	*/
mbed_official	133:d4dda5c437f0	2067	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
mbed_official	133:d4dda5c437f0	2068
mbed_official	133:d4dda5c437f0	2069	/**
mbed_official	133:d4dda5c437f0	2070	* @brief Enables the MMC Counter Stop Rollover.
mbed_official	133:d4dda5c437f0	2071	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2072	* @retval None
mbed_official	133:d4dda5c437f0	2073	*/
mbed_official	133:d4dda5c437f0	2074	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
mbed_official	133:d4dda5c437f0	2075
mbed_official	133:d4dda5c437f0	2076	/**
mbed_official	133:d4dda5c437f0	2077	* @brief Disables the MMC Counter Stop Rollover.
mbed_official	133:d4dda5c437f0	2078	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2079	* @retval None
mbed_official	133:d4dda5c437f0	2080	*/
mbed_official	133:d4dda5c437f0	2081	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
mbed_official	133:d4dda5c437f0	2082
mbed_official	133:d4dda5c437f0	2083	/**
mbed_official	133:d4dda5c437f0	2084	* @brief Resets the MMC Counters.
mbed_official	133:d4dda5c437f0	2085	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2086	* @retval None
mbed_official	133:d4dda5c437f0	2087	*/
mbed_official	133:d4dda5c437f0	2088	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
mbed_official	133:d4dda5c437f0	2089
mbed_official	133:d4dda5c437f0	2090	/**
mbed_official	133:d4dda5c437f0	2091	* @brief Enables the specified ETHERNET MMC Rx interrupts.
mbed_official	133:d4dda5c437f0	2092	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2093	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official	133:d4dda5c437f0	2094	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	2095	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2096	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2097	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2098	* @retval None
mbed_official	133:d4dda5c437f0	2099	*/
mbed_official	133:d4dda5c437f0	2100	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official	133:d4dda5c437f0	2101	/**
mbed_official	133:d4dda5c437f0	2102	* @brief Disables the specified ETHERNET MMC Rx interrupts.
mbed_official	133:d4dda5c437f0	2103	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2104	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official	133:d4dda5c437f0	2105	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	2106	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2107	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2108	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2109	* @retval None
mbed_official	133:d4dda5c437f0	2110	*/
mbed_official	133:d4dda5c437f0	2111	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official	133:d4dda5c437f0	2112	/**
mbed_official	133:d4dda5c437f0	2113	* @brief Enables the specified ETHERNET MMC Tx interrupts.
mbed_official	133:d4dda5c437f0	2114	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2115	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official	133:d4dda5c437f0	2116	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	2117	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2118	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2119	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2120	* @retval None
mbed_official	133:d4dda5c437f0	2121	*/
mbed_official	133:d4dda5c437f0	2122	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	2123
mbed_official	133:d4dda5c437f0	2124	/**
mbed_official	133:d4dda5c437f0	2125	* @brief Disables the specified ETHERNET MMC Tx interrupts.
mbed_official	133:d4dda5c437f0	2126	* @param __HANDLE__: ETH Handle.
mbed_official	133:d4dda5c437f0	2127	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official	133:d4dda5c437f0	2128	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	2129	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2130	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2131	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official	133:d4dda5c437f0	2132	* @retval None
mbed_official	133:d4dda5c437f0	2133	*/
mbed_official	133:d4dda5c437f0	2134	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	2135
mbed_official	133:d4dda5c437f0	2136
mbed_official	133:d4dda5c437f0	2137
mbed_official	133:d4dda5c437f0	2138	/* Exported functions --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	2139
mbed_official	133:d4dda5c437f0	2140	/* Initialization and de-initialization functions ****************************/
mbed_official	133:d4dda5c437f0	2141	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2142	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2143	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2144	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2145	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
mbed_official	133:d4dda5c437f0	2146	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
mbed_official	133:d4dda5c437f0	2147
mbed_official	133:d4dda5c437f0	2148	/* IO operation functions ****************************************************/
mbed_official	133:d4dda5c437f0	2149	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
mbed_official	133:d4dda5c437f0	2150	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2151
mbed_official	133:d4dda5c437f0	2152	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	2153	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2154	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2155
mbed_official	133:d4dda5c437f0	2156	/* Callback in non blocking modes (Interrupt) */
mbed_official	133:d4dda5c437f0	2157	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2158	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2159	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2160
mbed_official	133:d4dda5c437f0	2161	/* Cmmunication with PHY functions*/
mbed_official	133:d4dda5c437f0	2162	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
mbed_official	133:d4dda5c437f0	2163	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
mbed_official	133:d4dda5c437f0	2164
mbed_official	133:d4dda5c437f0	2165	/* Peripheral Control functions **********************************************/
mbed_official	133:d4dda5c437f0	2166	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2167	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2168
mbed_official	133:d4dda5c437f0	2169	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
mbed_official	133:d4dda5c437f0	2170	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
mbed_official	133:d4dda5c437f0	2171
mbed_official	133:d4dda5c437f0	2172	/* Peripheral State functions ************************************************/
mbed_official	133:d4dda5c437f0	2173	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
mbed_official	133:d4dda5c437f0	2174
mbed_official	133:d4dda5c437f0	2175	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	2176	/**
mbed_official	133:d4dda5c437f0	2177	* @}
mbed_official	133:d4dda5c437f0	2178	*/
mbed_official	133:d4dda5c437f0	2179
mbed_official	133:d4dda5c437f0	2180	/**
mbed_official	133:d4dda5c437f0	2181	* @}
mbed_official	133:d4dda5c437f0	2182	*/
mbed_official	133:d4dda5c437f0	2183
mbed_official	133:d4dda5c437f0	2184	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	2185	}
mbed_official	133:d4dda5c437f0	2186	#endif
mbed_official	133:d4dda5c437f0	2187
mbed_official	133:d4dda5c437f0	2188	#endif /* __STM32F4xx_HAL_ETH_H */
mbed_official	133:d4dda5c437f0	2189
mbed_official	133:d4dda5c437f0	2190
mbed_official	133:d4dda5c437f0	2191
mbed_official	133:d4dda5c437f0	2192	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_eth.h@296:ec1b66a3d094, 2014-08-21 (annotated)

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