shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_eth.c@296:ec1b66a3d094, 2014-08-21 (annotated)

Committer:
mbed_official
Date:
Thu Aug 21 15:00:08 2014 +0100
Revision:
296:ec1b66a3d094
Parent:
targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.c@242:7074e42da0b2 
Synchronized with git revision bbc120c4786e99dfa586e7a13f8638064f1e5938



Full URL: https://github.com/mbedmicro/mbed/commit/bbc120c4786e99dfa586e7a13f8638064f1e5938/



DISCO_F407VG - add USBDevice support and a variant - ARCH_MAX

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_eth.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief ETH HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 133:d4dda5c437f0 10 * + Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 11 * + IO operation functions
mbed_official 133:d4dda5c437f0 12 * + Peripheral Control functions
mbed_official 133:d4dda5c437f0 13 * + Peripheral State and Errors functions
mbed_official 133:d4dda5c437f0 14 *
mbed_official 133:d4dda5c437f0 15 @verbatim
mbed_official 133:d4dda5c437f0 16 ==============================================================================
mbed_official 133:d4dda5c437f0 17 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 18 ==============================================================================
mbed_official 133:d4dda5c437f0 19 [..]
mbed_official 133:d4dda5c437f0 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 133:d4dda5c437f0 21 ETH_HandleTypeDef heth;
mbed_official 133:d4dda5c437f0 22
mbed_official 133:d4dda5c437f0 23 (#)Fill parameters of Init structure in heth handle
mbed_official 133:d4dda5c437f0 24
mbed_official 133:d4dda5c437f0 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 133:d4dda5c437f0 26
mbed_official 133:d4dda5c437f0 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 133:d4dda5c437f0 28 (##) Enable the Ethernet interface clock using
mbed_official 133:d4dda5c437f0 29 (+++) __ETHMAC_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 30 (+++) __ETHMACTX_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 31 (+++) __ETHMACRX_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 32
mbed_official 133:d4dda5c437f0 33 (##) Initialize the related GPIO clocks
mbed_official 133:d4dda5c437f0 34 (##) Configure Ethernet pin-out
mbed_official 133:d4dda5c437f0 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 133:d4dda5c437f0 36
mbed_official 133:d4dda5c437f0 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 133:d4dda5c437f0 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 133:d4dda5c437f0 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 133:d4dda5c437f0 40
mbed_official 133:d4dda5c437f0 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 133:d4dda5c437f0 42 (##) HAL_ETH_Start();
mbed_official 133:d4dda5c437f0 43
mbed_official 133:d4dda5c437f0 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 133:d4dda5c437f0 45 the frame to MAC TX FIFO:
mbed_official 133:d4dda5c437f0 46 (##) HAL_ETH_TransmitFrame();
mbed_official 133:d4dda5c437f0 47
mbed_official 133:d4dda5c437f0 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 133:d4dda5c437f0 49 frame parameters
mbed_official 133:d4dda5c437f0 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 133:d4dda5c437f0 51
mbed_official 133:d4dda5c437f0 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 133:d4dda5c437f0 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 133:d4dda5c437f0 54
mbed_official 133:d4dda5c437f0 55 (#) Communicate with external PHY device:
mbed_official 133:d4dda5c437f0 56 (##) Read a specific register from the PHY
mbed_official 133:d4dda5c437f0 57 HAL_ETH_ReadPHYRegister();
mbed_official 133:d4dda5c437f0 58 (##) Write data to a specific RHY register:
mbed_official 133:d4dda5c437f0 59 HAL_ETH_WritePHYRegister();
mbed_official 133:d4dda5c437f0 60
mbed_official 133:d4dda5c437f0 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 133:d4dda5c437f0 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 133:d4dda5c437f0 63
mbed_official 133:d4dda5c437f0 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 133:d4dda5c437f0 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 133:d4dda5c437f0 66
mbed_official 133:d4dda5c437f0 67 @endverbatim
mbed_official 133:d4dda5c437f0 68 ******************************************************************************
mbed_official 133:d4dda5c437f0 69 * @attention
mbed_official 133:d4dda5c437f0 70 *
mbed_official 133:d4dda5c437f0 71 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 72 *
mbed_official 133:d4dda5c437f0 73 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 74 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 75 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 76 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 78 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 79 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 81 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 82 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 83 *
mbed_official 133:d4dda5c437f0 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 94 *
mbed_official 133:d4dda5c437f0 95 ******************************************************************************
mbed_official 133:d4dda5c437f0 96 */
mbed_official 133:d4dda5c437f0 97
mbed_official 133:d4dda5c437f0 98 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 99 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 100
mbed_official 133:d4dda5c437f0 101 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 102 * @{
mbed_official 133:d4dda5c437f0 103 */
mbed_official 133:d4dda5c437f0 104
mbed_official 133:d4dda5c437f0 105 /** @defgroup ETH
mbed_official 133:d4dda5c437f0 106 * @brief ETH HAL module driver
mbed_official 133:d4dda5c437f0 107 * @{
mbed_official 133:d4dda5c437f0 108 */
mbed_official 133:d4dda5c437f0 109
mbed_official 133:d4dda5c437f0 110 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 111
mbed_official 133:d4dda5c437f0 112 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 113
mbed_official 133:d4dda5c437f0 114 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 115 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 116 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 117 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 118 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 119 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 133:d4dda5c437f0 120 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 133:d4dda5c437f0 121 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 122 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 123 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 124 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 125 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 126 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 127 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 128 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 129 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 133:d4dda5c437f0 130
mbed_official 133:d4dda5c437f0 131 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 132
mbed_official 133:d4dda5c437f0 133 /** @defgroup ETH_Private_Functions
mbed_official 133:d4dda5c437f0 134 * @{
mbed_official 133:d4dda5c437f0 135 */
mbed_official 133:d4dda5c437f0 136
mbed_official 133:d4dda5c437f0 137 /** @defgroup ETH_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 138 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 139 *
mbed_official 133:d4dda5c437f0 140 @verbatim
mbed_official 133:d4dda5c437f0 141 ===============================================================================
mbed_official 133:d4dda5c437f0 142 ##### Initialization and de-initialization functions #####
mbed_official 133:d4dda5c437f0 143 ===============================================================================
mbed_official 133:d4dda5c437f0 144 [..] This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 145 (+) Initialize and configure the Ethernet peripheral
mbed_official 133:d4dda5c437f0 146 (+) De-initialize the Ethernet peripheral
mbed_official 133:d4dda5c437f0 147
mbed_official 133:d4dda5c437f0 148 @endverbatim
mbed_official 133:d4dda5c437f0 149 * @{
mbed_official 133:d4dda5c437f0 150 */
mbed_official 133:d4dda5c437f0 151
mbed_official 133:d4dda5c437f0 152 /**
mbed_official 133:d4dda5c437f0 153 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 133:d4dda5c437f0 154 * parameters.
mbed_official 242:7074e42da0b2 155 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 156 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 157 * @retval HAL status
mbed_official 133:d4dda5c437f0 158 */
mbed_official 133:d4dda5c437f0 159 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 160 {
mbed_official 133:d4dda5c437f0 161 uint32_t tmpreg = 0, phyreg = 0;
mbed_official 133:d4dda5c437f0 162 uint32_t hclk = 60000000;
mbed_official 133:d4dda5c437f0 163 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 164 uint32_t err = ETH_SUCCESS;
mbed_official 133:d4dda5c437f0 165
mbed_official 133:d4dda5c437f0 166 /* Check the ETH peripheral state */
mbed_official 133:d4dda5c437f0 167 if(heth == NULL)
mbed_official 133:d4dda5c437f0 168 {
mbed_official 133:d4dda5c437f0 169 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 170 }
mbed_official 133:d4dda5c437f0 171
mbed_official 133:d4dda5c437f0 172 /* Check parameters */
mbed_official 133:d4dda5c437f0 173 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 133:d4dda5c437f0 174 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 133:d4dda5c437f0 175 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 133:d4dda5c437f0 176 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 133:d4dda5c437f0 177
mbed_official 133:d4dda5c437f0 178 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 133:d4dda5c437f0 179 {
mbed_official 133:d4dda5c437f0 180 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 133:d4dda5c437f0 181 HAL_ETH_MspInit(heth);
mbed_official 133:d4dda5c437f0 182 }
mbed_official 133:d4dda5c437f0 183
mbed_official 133:d4dda5c437f0 184 /* Enable SYSCFG Clock */
mbed_official 133:d4dda5c437f0 185 __SYSCFG_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 186
mbed_official 133:d4dda5c437f0 187 /* Select MII or RMII Mode*/
mbed_official 133:d4dda5c437f0 188 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 133:d4dda5c437f0 189 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 133:d4dda5c437f0 190
mbed_official 133:d4dda5c437f0 191 /* Ethernet Software reset */
mbed_official 133:d4dda5c437f0 192 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 133:d4dda5c437f0 193 /* After reset all the registers holds their respective reset values */
mbed_official 133:d4dda5c437f0 194 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 133:d4dda5c437f0 195
mbed_official 133:d4dda5c437f0 196 /* Wait for software reset */
mbed_official 133:d4dda5c437f0 197 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 133:d4dda5c437f0 198 {
mbed_official 133:d4dda5c437f0 199 }
mbed_official 133:d4dda5c437f0 200
mbed_official 133:d4dda5c437f0 201 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 133:d4dda5c437f0 202 /* Get the ETHERNET MACMIIAR value */
mbed_official 133:d4dda5c437f0 203 tmpreg = (heth->Instance)->MACMIIAR;
mbed_official 133:d4dda5c437f0 204 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 133:d4dda5c437f0 205 tmpreg &= MACMIIAR_CR_MASK;
mbed_official 133:d4dda5c437f0 206
mbed_official 133:d4dda5c437f0 207 /* Get hclk frequency value */
mbed_official 133:d4dda5c437f0 208 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 133:d4dda5c437f0 209
mbed_official 133:d4dda5c437f0 210 /* Set CR bits depending on hclk value */
mbed_official 133:d4dda5c437f0 211 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 133:d4dda5c437f0 212 {
mbed_official 133:d4dda5c437f0 213 /* CSR Clock Range between 20-35 MHz */
mbed_official 133:d4dda5c437f0 214 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 133:d4dda5c437f0 215 }
mbed_official 133:d4dda5c437f0 216 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 133:d4dda5c437f0 217 {
mbed_official 133:d4dda5c437f0 218 /* CSR Clock Range between 35-60 MHz */
mbed_official 133:d4dda5c437f0 219 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 133:d4dda5c437f0 220 }
mbed_official 133:d4dda5c437f0 221 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 133:d4dda5c437f0 222 {
mbed_official 133:d4dda5c437f0 223 /* CSR Clock Range between 60-100 MHz */
mbed_official 133:d4dda5c437f0 224 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 133:d4dda5c437f0 225 }
mbed_official 133:d4dda5c437f0 226 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 133:d4dda5c437f0 227 {
mbed_official 133:d4dda5c437f0 228 /* CSR Clock Range between 100-150 MHz */
mbed_official 133:d4dda5c437f0 229 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 133:d4dda5c437f0 230 }
mbed_official 133:d4dda5c437f0 231 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official 133:d4dda5c437f0 232 {
mbed_official 133:d4dda5c437f0 233 /* CSR Clock Range between 150-168 MHz */
mbed_official 133:d4dda5c437f0 234 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 133:d4dda5c437f0 235 }
mbed_official 133:d4dda5c437f0 236
mbed_official 133:d4dda5c437f0 237 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 133:d4dda5c437f0 238 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 239
mbed_official 133:d4dda5c437f0 240 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 133:d4dda5c437f0 241 /* Put the PHY in reset mode */
mbed_official 133:d4dda5c437f0 242 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 133:d4dda5c437f0 243 {
mbed_official 133:d4dda5c437f0 244 /* In case of write timeout */
mbed_official 133:d4dda5c437f0 245 err = ETH_ERROR;
mbed_official 133:d4dda5c437f0 246
mbed_official 133:d4dda5c437f0 247 /* Config MAC and DMA */
mbed_official 133:d4dda5c437f0 248 ETH_MACDMAConfig(heth, err);
mbed_official 133:d4dda5c437f0 249
mbed_official 133:d4dda5c437f0 250 /* Set the ETH peripheral state to READY */
mbed_official 133:d4dda5c437f0 251 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 /* Return HAL_ERROR */
mbed_official 133:d4dda5c437f0 254 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 255 }
mbed_official 133:d4dda5c437f0 256
mbed_official 133:d4dda5c437f0 257 /* Delay to assure PHY reset */
mbed_official 133:d4dda5c437f0 258 HAL_Delay(PHY_RESET_DELAY);
mbed_official 133:d4dda5c437f0 259
mbed_official 133:d4dda5c437f0 260 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 133:d4dda5c437f0 261 {
mbed_official 133:d4dda5c437f0 262 /* We wait for linked status */
mbed_official 133:d4dda5c437f0 263 do
mbed_official 133:d4dda5c437f0 264 {
mbed_official 133:d4dda5c437f0 265 timeout++;
mbed_official 133:d4dda5c437f0 266 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 133:d4dda5c437f0 267 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
mbed_official 133:d4dda5c437f0 268
mbed_official 133:d4dda5c437f0 269 if(timeout == PHY_READ_TO)
mbed_official 133:d4dda5c437f0 270 {
mbed_official 133:d4dda5c437f0 271 /* In case of write timeout */
mbed_official 133:d4dda5c437f0 272 err = ETH_ERROR;
mbed_official 133:d4dda5c437f0 273
mbed_official 133:d4dda5c437f0 274 /* Config MAC and DMA */
mbed_official 133:d4dda5c437f0 275 ETH_MACDMAConfig(heth, err);
mbed_official 133:d4dda5c437f0 276
mbed_official 133:d4dda5c437f0 277 /* Set the ETH peripheral state to READY */
mbed_official 133:d4dda5c437f0 278 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 279
mbed_official 133:d4dda5c437f0 280 /* Return HAL_ERROR */
mbed_official 133:d4dda5c437f0 281 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 282 }
mbed_official 133:d4dda5c437f0 283
mbed_official 133:d4dda5c437f0 284 /* Reset Timeout counter */
mbed_official 133:d4dda5c437f0 285 timeout = 0;
mbed_official 133:d4dda5c437f0 286
mbed_official 133:d4dda5c437f0 287 /* Enable Auto-Negotiation */
mbed_official 133:d4dda5c437f0 288 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 133:d4dda5c437f0 289 {
mbed_official 133:d4dda5c437f0 290 /* In case of write timeout */
mbed_official 133:d4dda5c437f0 291 err = ETH_ERROR;
mbed_official 133:d4dda5c437f0 292
mbed_official 133:d4dda5c437f0 293 /* Config MAC and DMA */
mbed_official 133:d4dda5c437f0 294 ETH_MACDMAConfig(heth, err);
mbed_official 133:d4dda5c437f0 295
mbed_official 133:d4dda5c437f0 296 /* Set the ETH peripheral state to READY */
mbed_official 133:d4dda5c437f0 297 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 298
mbed_official 133:d4dda5c437f0 299 /* Return HAL_ERROR */
mbed_official 133:d4dda5c437f0 300 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 301 }
mbed_official 133:d4dda5c437f0 302
mbed_official 133:d4dda5c437f0 303 /* Wait until the auto-negotiation will be completed */
mbed_official 133:d4dda5c437f0 304 do
mbed_official 133:d4dda5c437f0 305 {
mbed_official 133:d4dda5c437f0 306 timeout++;
mbed_official 133:d4dda5c437f0 307 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 133:d4dda5c437f0 308 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO));
mbed_official 133:d4dda5c437f0 309
mbed_official 133:d4dda5c437f0 310 if(timeout == PHY_READ_TO)
mbed_official 133:d4dda5c437f0 311 {
mbed_official 133:d4dda5c437f0 312 /* In case of timeout */
mbed_official 133:d4dda5c437f0 313 err = ETH_ERROR;
mbed_official 133:d4dda5c437f0 314
mbed_official 133:d4dda5c437f0 315 /* Config MAC and DMA */
mbed_official 133:d4dda5c437f0 316 ETH_MACDMAConfig(heth, err);
mbed_official 133:d4dda5c437f0 317
mbed_official 133:d4dda5c437f0 318 /* Set the ETH peripheral state to READY */
mbed_official 133:d4dda5c437f0 319 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 320
mbed_official 133:d4dda5c437f0 321 /* Return HAL_ERROR */
mbed_official 133:d4dda5c437f0 322 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 323 }
mbed_official 133:d4dda5c437f0 324
mbed_official 133:d4dda5c437f0 325 /* Reset Timeout counter */
mbed_official 133:d4dda5c437f0 326 timeout = 0;
mbed_official 133:d4dda5c437f0 327
mbed_official 133:d4dda5c437f0 328 /* Read the result of the auto-negotiation */
mbed_official 133:d4dda5c437f0 329 HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg);
mbed_official 133:d4dda5c437f0 330
mbed_official 133:d4dda5c437f0 331 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 133:d4dda5c437f0 332 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 133:d4dda5c437f0 333 {
mbed_official 133:d4dda5c437f0 334 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 133:d4dda5c437f0 335 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 133:d4dda5c437f0 336 }
mbed_official 133:d4dda5c437f0 337 else
mbed_official 133:d4dda5c437f0 338 {
mbed_official 133:d4dda5c437f0 339 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 133:d4dda5c437f0 340 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 133:d4dda5c437f0 341 }
mbed_official 133:d4dda5c437f0 342 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 133:d4dda5c437f0 343 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 133:d4dda5c437f0 344 {
mbed_official 133:d4dda5c437f0 345 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 133:d4dda5c437f0 346 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 133:d4dda5c437f0 347 }
mbed_official 133:d4dda5c437f0 348 else
mbed_official 133:d4dda5c437f0 349 {
mbed_official 133:d4dda5c437f0 350 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 133:d4dda5c437f0 351 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 133:d4dda5c437f0 352 }
mbed_official 133:d4dda5c437f0 353 }
mbed_official 133:d4dda5c437f0 354 else /* AutoNegotiation Disable */
mbed_official 133:d4dda5c437f0 355 {
mbed_official 133:d4dda5c437f0 356 /* Check parameters */
mbed_official 133:d4dda5c437f0 357 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 133:d4dda5c437f0 358 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 133:d4dda5c437f0 359
mbed_official 133:d4dda5c437f0 360 /* Set MAC Speed and Duplex Mode */
mbed_official 133:d4dda5c437f0 361 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 133:d4dda5c437f0 362 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 133:d4dda5c437f0 363 {
mbed_official 133:d4dda5c437f0 364 /* In case of write timeout */
mbed_official 133:d4dda5c437f0 365 err = ETH_ERROR;
mbed_official 133:d4dda5c437f0 366
mbed_official 133:d4dda5c437f0 367 /* Config MAC and DMA */
mbed_official 133:d4dda5c437f0 368 ETH_MACDMAConfig(heth, err);
mbed_official 133:d4dda5c437f0 369
mbed_official 133:d4dda5c437f0 370 /* Set the ETH peripheral state to READY */
mbed_official 133:d4dda5c437f0 371 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 372
mbed_official 133:d4dda5c437f0 373 /* Return HAL_ERROR */
mbed_official 133:d4dda5c437f0 374 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 375 }
mbed_official 133:d4dda5c437f0 376
mbed_official 133:d4dda5c437f0 377 /* Delay to assure PHY configuration */
mbed_official 133:d4dda5c437f0 378 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 133:d4dda5c437f0 379 }
mbed_official 133:d4dda5c437f0 380
mbed_official 133:d4dda5c437f0 381 /* Config MAC and DMA */
mbed_official 133:d4dda5c437f0 382 ETH_MACDMAConfig(heth, err);
mbed_official 133:d4dda5c437f0 383
mbed_official 133:d4dda5c437f0 384 /* Set ETH HAL State to Ready */
mbed_official 133:d4dda5c437f0 385 heth->State= HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 386
mbed_official 133:d4dda5c437f0 387 /* Return function status */
mbed_official 133:d4dda5c437f0 388 return HAL_OK;
mbed_official 133:d4dda5c437f0 389 }
mbed_official 133:d4dda5c437f0 390
mbed_official 133:d4dda5c437f0 391 /**
mbed_official 133:d4dda5c437f0 392 * @brief De-Initializes the ETH peripheral.
mbed_official 242:7074e42da0b2 393 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 394 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 395 * @retval HAL status
mbed_official 133:d4dda5c437f0 396 */
mbed_official 133:d4dda5c437f0 397 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 398 {
mbed_official 133:d4dda5c437f0 399 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 400 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 401
mbed_official 133:d4dda5c437f0 402 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 133:d4dda5c437f0 403 HAL_ETH_MspDeInit(heth);
mbed_official 133:d4dda5c437f0 404
mbed_official 133:d4dda5c437f0 405 /* Set ETH HAL state to Disabled */
mbed_official 133:d4dda5c437f0 406 heth->State= HAL_ETH_STATE_RESET;
mbed_official 133:d4dda5c437f0 407
mbed_official 133:d4dda5c437f0 408 /* Release Lock */
mbed_official 133:d4dda5c437f0 409 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 410
mbed_official 133:d4dda5c437f0 411 /* Return function status */
mbed_official 133:d4dda5c437f0 412 return HAL_OK;
mbed_official 133:d4dda5c437f0 413 }
mbed_official 133:d4dda5c437f0 414
mbed_official 133:d4dda5c437f0 415 /**
mbed_official 133:d4dda5c437f0 416 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 242:7074e42da0b2 417 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 418 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 419 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 133:d4dda5c437f0 420 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 133:d4dda5c437f0 421 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 133:d4dda5c437f0 422 * @retval HAL status
mbed_official 133:d4dda5c437f0 423 */
mbed_official 133:d4dda5c437f0 424 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 133:d4dda5c437f0 425 {
mbed_official 133:d4dda5c437f0 426 uint32_t i = 0;
mbed_official 133:d4dda5c437f0 427 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 133:d4dda5c437f0 428
mbed_official 133:d4dda5c437f0 429 /* Process Locked */
mbed_official 133:d4dda5c437f0 430 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 431
mbed_official 133:d4dda5c437f0 432 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 433 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 434
mbed_official 133:d4dda5c437f0 435 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 133:d4dda5c437f0 436 heth->TxDesc = DMATxDescTab;
mbed_official 133:d4dda5c437f0 437
mbed_official 133:d4dda5c437f0 438 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 133:d4dda5c437f0 439 for(i=0; i < TxBuffCount; i++)
mbed_official 133:d4dda5c437f0 440 {
mbed_official 133:d4dda5c437f0 441 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 133:d4dda5c437f0 442 dmatxdesc = DMATxDescTab + i;
mbed_official 133:d4dda5c437f0 443
mbed_official 133:d4dda5c437f0 444 /* Set Second Address Chained bit */
mbed_official 133:d4dda5c437f0 445 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 133:d4dda5c437f0 446
mbed_official 133:d4dda5c437f0 447 /* Set Buffer1 address pointer */
mbed_official 133:d4dda5c437f0 448 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 133:d4dda5c437f0 449
mbed_official 133:d4dda5c437f0 450 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 133:d4dda5c437f0 451 {
mbed_official 133:d4dda5c437f0 452 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 133:d4dda5c437f0 453 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 133:d4dda5c437f0 454 }
mbed_official 133:d4dda5c437f0 455
mbed_official 133:d4dda5c437f0 456 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 133:d4dda5c437f0 457 if(i < (TxBuffCount-1))
mbed_official 133:d4dda5c437f0 458 {
mbed_official 133:d4dda5c437f0 459 /* Set next descriptor address register with next descriptor base address */
mbed_official 133:d4dda5c437f0 460 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 133:d4dda5c437f0 461 }
mbed_official 133:d4dda5c437f0 462 else
mbed_official 133:d4dda5c437f0 463 {
mbed_official 133:d4dda5c437f0 464 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 133:d4dda5c437f0 465 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 133:d4dda5c437f0 466 }
mbed_official 133:d4dda5c437f0 467 }
mbed_official 133:d4dda5c437f0 468
mbed_official 133:d4dda5c437f0 469 /* Set Transmit Descriptor List Address Register */
mbed_official 133:d4dda5c437f0 470 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 133:d4dda5c437f0 471
mbed_official 133:d4dda5c437f0 472 /* Set ETH HAL State to Ready */
mbed_official 133:d4dda5c437f0 473 heth->State= HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 474
mbed_official 133:d4dda5c437f0 475 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 476 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 477
mbed_official 133:d4dda5c437f0 478 /* Return function status */
mbed_official 133:d4dda5c437f0 479 return HAL_OK;
mbed_official 133:d4dda5c437f0 480 }
mbed_official 133:d4dda5c437f0 481
mbed_official 133:d4dda5c437f0 482 /**
mbed_official 133:d4dda5c437f0 483 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 242:7074e42da0b2 484 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 485 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 486 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 133:d4dda5c437f0 487 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 133:d4dda5c437f0 488 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 133:d4dda5c437f0 489 * @retval HAL status
mbed_official 133:d4dda5c437f0 490 */
mbed_official 133:d4dda5c437f0 491 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 133:d4dda5c437f0 492 {
mbed_official 133:d4dda5c437f0 493 uint32_t i = 0;
mbed_official 133:d4dda5c437f0 494 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 133:d4dda5c437f0 495
mbed_official 133:d4dda5c437f0 496 /* Process Locked */
mbed_official 133:d4dda5c437f0 497 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 498
mbed_official 133:d4dda5c437f0 499 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 500 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 501
mbed_official 133:d4dda5c437f0 502 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 133:d4dda5c437f0 503 heth->RxDesc = DMARxDescTab;
mbed_official 133:d4dda5c437f0 504
mbed_official 133:d4dda5c437f0 505 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 133:d4dda5c437f0 506 for(i=0; i < RxBuffCount; i++)
mbed_official 133:d4dda5c437f0 507 {
mbed_official 133:d4dda5c437f0 508 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 133:d4dda5c437f0 509 DMARxDesc = DMARxDescTab+i;
mbed_official 133:d4dda5c437f0 510
mbed_official 133:d4dda5c437f0 511 /* Set Own bit of the Rx descriptor Status */
mbed_official 133:d4dda5c437f0 512 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 133:d4dda5c437f0 513
mbed_official 133:d4dda5c437f0 514 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 133:d4dda5c437f0 515 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 133:d4dda5c437f0 516
mbed_official 133:d4dda5c437f0 517 /* Set Buffer1 address pointer */
mbed_official 133:d4dda5c437f0 518 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 133:d4dda5c437f0 519
mbed_official 133:d4dda5c437f0 520 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 133:d4dda5c437f0 521 {
mbed_official 133:d4dda5c437f0 522 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 133:d4dda5c437f0 523 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 133:d4dda5c437f0 524 }
mbed_official 133:d4dda5c437f0 525
mbed_official 133:d4dda5c437f0 526 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 133:d4dda5c437f0 527 if(i < (RxBuffCount-1))
mbed_official 133:d4dda5c437f0 528 {
mbed_official 133:d4dda5c437f0 529 /* Set next descriptor address register with next descriptor base address */
mbed_official 133:d4dda5c437f0 530 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 133:d4dda5c437f0 531 }
mbed_official 133:d4dda5c437f0 532 else
mbed_official 133:d4dda5c437f0 533 {
mbed_official 133:d4dda5c437f0 534 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 133:d4dda5c437f0 535 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 133:d4dda5c437f0 536 }
mbed_official 133:d4dda5c437f0 537 }
mbed_official 133:d4dda5c437f0 538
mbed_official 133:d4dda5c437f0 539 /* Set Receive Descriptor List Address Register */
mbed_official 133:d4dda5c437f0 540 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 133:d4dda5c437f0 541
mbed_official 133:d4dda5c437f0 542 /* Set ETH HAL State to Ready */
mbed_official 133:d4dda5c437f0 543 heth->State= HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 544
mbed_official 133:d4dda5c437f0 545 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 546 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 547
mbed_official 133:d4dda5c437f0 548 /* Return function status */
mbed_official 133:d4dda5c437f0 549 return HAL_OK;
mbed_official 133:d4dda5c437f0 550 }
mbed_official 133:d4dda5c437f0 551
mbed_official 133:d4dda5c437f0 552 /**
mbed_official 133:d4dda5c437f0 553 * @brief Initializes the ETH MSP.
mbed_official 242:7074e42da0b2 554 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 555 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 556 * @retval None
mbed_official 133:d4dda5c437f0 557 */
mbed_official 133:d4dda5c437f0 558 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 559 {
mbed_official 133:d4dda5c437f0 560 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 561 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 562 */
mbed_official 133:d4dda5c437f0 563 }
mbed_official 133:d4dda5c437f0 564
mbed_official 133:d4dda5c437f0 565 /**
mbed_official 133:d4dda5c437f0 566 * @brief DeInitializes ETH MSP.
mbed_official 242:7074e42da0b2 567 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 568 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 569 * @retval None
mbed_official 133:d4dda5c437f0 570 */
mbed_official 133:d4dda5c437f0 571 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 572 {
mbed_official 133:d4dda5c437f0 573 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 574 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 575 */
mbed_official 133:d4dda5c437f0 576 }
mbed_official 133:d4dda5c437f0 577
mbed_official 133:d4dda5c437f0 578 /**
mbed_official 133:d4dda5c437f0 579 * @}
mbed_official 133:d4dda5c437f0 580 */
mbed_official 133:d4dda5c437f0 581
mbed_official 133:d4dda5c437f0 582 /** @defgroup ETH_Group2 IO operation functions
mbed_official 133:d4dda5c437f0 583 * @brief Data transfers functions
mbed_official 133:d4dda5c437f0 584 *
mbed_official 133:d4dda5c437f0 585 @verbatim
mbed_official 133:d4dda5c437f0 586 ==============================================================================
mbed_official 133:d4dda5c437f0 587 ##### IO operation functions #####
mbed_official 133:d4dda5c437f0 588 ==============================================================================
mbed_official 133:d4dda5c437f0 589 [..] This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 590 (+) Transmit a frame
mbed_official 133:d4dda5c437f0 591 HAL_ETH_TransmitFrame();
mbed_official 133:d4dda5c437f0 592 (+) Receive a frame
mbed_official 133:d4dda5c437f0 593 HAL_ETH_GetReceivedFrame();
mbed_official 133:d4dda5c437f0 594 HAL_ETH_GetReceivedFrame_IT();
mbed_official 133:d4dda5c437f0 595 (+) Read from an External PHY register
mbed_official 133:d4dda5c437f0 596 HAL_ETH_ReadPHYRegister();
mbed_official 242:7074e42da0b2 597 (+) Write to an External PHY register
mbed_official 133:d4dda5c437f0 598 HAL_ETH_WritePHYRegister();
mbed_official 133:d4dda5c437f0 599
mbed_official 133:d4dda5c437f0 600 @endverbatim
mbed_official 133:d4dda5c437f0 601
mbed_official 133:d4dda5c437f0 602 * @{
mbed_official 133:d4dda5c437f0 603 */
mbed_official 133:d4dda5c437f0 604
mbed_official 133:d4dda5c437f0 605 /**
mbed_official 133:d4dda5c437f0 606 * @brief Sends an Ethernet frame.
mbed_official 242:7074e42da0b2 607 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 608 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 609 * @param FrameLength: Amount of data to be sent
mbed_official 133:d4dda5c437f0 610 * @retval HAL status
mbed_official 133:d4dda5c437f0 611 */
mbed_official 133:d4dda5c437f0 612 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 133:d4dda5c437f0 613 {
mbed_official 133:d4dda5c437f0 614 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 133:d4dda5c437f0 615
mbed_official 133:d4dda5c437f0 616 /* Process Locked */
mbed_official 133:d4dda5c437f0 617 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 618
mbed_official 133:d4dda5c437f0 619 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 620 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 621
mbed_official 133:d4dda5c437f0 622 if (FrameLength == 0)
mbed_official 133:d4dda5c437f0 623 {
mbed_official 133:d4dda5c437f0 624 /* Set ETH HAL state to READY */
mbed_official 133:d4dda5c437f0 625 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 626
mbed_official 133:d4dda5c437f0 627 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 628 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 629
mbed_official 133:d4dda5c437f0 630 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 631 }
mbed_official 133:d4dda5c437f0 632
mbed_official 133:d4dda5c437f0 633 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 133:d4dda5c437f0 634 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 133:d4dda5c437f0 635 {
mbed_official 133:d4dda5c437f0 636 /* OWN bit set */
mbed_official 133:d4dda5c437f0 637 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 638
mbed_official 133:d4dda5c437f0 639 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 640 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 641
mbed_official 133:d4dda5c437f0 642 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 643 }
mbed_official 133:d4dda5c437f0 644
mbed_official 133:d4dda5c437f0 645 /* Get the number of needed Tx buffers for the current frame */
mbed_official 133:d4dda5c437f0 646 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 133:d4dda5c437f0 647 {
mbed_official 133:d4dda5c437f0 648 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 133:d4dda5c437f0 649 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 133:d4dda5c437f0 650 {
mbed_official 133:d4dda5c437f0 651 bufcount++;
mbed_official 133:d4dda5c437f0 652 }
mbed_official 133:d4dda5c437f0 653 }
mbed_official 133:d4dda5c437f0 654 else
mbed_official 133:d4dda5c437f0 655 {
mbed_official 133:d4dda5c437f0 656 bufcount = 1;
mbed_official 133:d4dda5c437f0 657 }
mbed_official 133:d4dda5c437f0 658 if (bufcount == 1)
mbed_official 133:d4dda5c437f0 659 {
mbed_official 133:d4dda5c437f0 660 /* Set LAST and FIRST segment */
mbed_official 133:d4dda5c437f0 661 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 133:d4dda5c437f0 662 /* Set frame size */
mbed_official 133:d4dda5c437f0 663 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 133:d4dda5c437f0 664 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 133:d4dda5c437f0 665 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 133:d4dda5c437f0 666 /* Point to next descriptor */
mbed_official 133:d4dda5c437f0 667 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 668 }
mbed_official 133:d4dda5c437f0 669 else
mbed_official 133:d4dda5c437f0 670 {
mbed_official 133:d4dda5c437f0 671 for (i=0; i< bufcount; i++)
mbed_official 133:d4dda5c437f0 672 {
mbed_official 133:d4dda5c437f0 673 /* Clear FIRST and LAST segment bits */
mbed_official 133:d4dda5c437f0 674 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 133:d4dda5c437f0 675
mbed_official 133:d4dda5c437f0 676 if (i == 0)
mbed_official 133:d4dda5c437f0 677 {
mbed_official 133:d4dda5c437f0 678 /* Setting the first segment bit */
mbed_official 133:d4dda5c437f0 679 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 133:d4dda5c437f0 680 }
mbed_official 133:d4dda5c437f0 681
mbed_official 133:d4dda5c437f0 682 /* Program size */
mbed_official 133:d4dda5c437f0 683 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 133:d4dda5c437f0 684
mbed_official 133:d4dda5c437f0 685 if (i == (bufcount-1))
mbed_official 133:d4dda5c437f0 686 {
mbed_official 133:d4dda5c437f0 687 /* Setting the last segment bit */
mbed_official 133:d4dda5c437f0 688 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 133:d4dda5c437f0 689 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 133:d4dda5c437f0 690 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 133:d4dda5c437f0 691 }
mbed_official 133:d4dda5c437f0 692
mbed_official 133:d4dda5c437f0 693 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 133:d4dda5c437f0 694 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 133:d4dda5c437f0 695 /* point to next descriptor */
mbed_official 133:d4dda5c437f0 696 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 697 }
mbed_official 133:d4dda5c437f0 698 }
mbed_official 133:d4dda5c437f0 699
mbed_official 133:d4dda5c437f0 700 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 133:d4dda5c437f0 701 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 133:d4dda5c437f0 702 {
mbed_official 133:d4dda5c437f0 703 /* Clear TBUS ETHERNET DMA flag */
mbed_official 133:d4dda5c437f0 704 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 133:d4dda5c437f0 705 /* Resume DMA transmission*/
mbed_official 133:d4dda5c437f0 706 (heth->Instance)->DMATPDR = 0;
mbed_official 133:d4dda5c437f0 707 }
mbed_official 133:d4dda5c437f0 708
mbed_official 133:d4dda5c437f0 709 /* Set ETH HAL State to Ready */
mbed_official 133:d4dda5c437f0 710 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 711
mbed_official 133:d4dda5c437f0 712 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 713 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 714
mbed_official 133:d4dda5c437f0 715 /* Return function status */
mbed_official 133:d4dda5c437f0 716 return HAL_OK;
mbed_official 133:d4dda5c437f0 717 }
mbed_official 133:d4dda5c437f0 718
mbed_official 133:d4dda5c437f0 719 /**
mbed_official 133:d4dda5c437f0 720 * @brief Checks for received frames.
mbed_official 242:7074e42da0b2 721 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 722 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 723 * @retval HAL status
mbed_official 133:d4dda5c437f0 724 */
mbed_official 133:d4dda5c437f0 725 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 726 {
mbed_official 133:d4dda5c437f0 727 uint32_t framelength = 0;
mbed_official 133:d4dda5c437f0 728
mbed_official 133:d4dda5c437f0 729 /* Process Locked */
mbed_official 133:d4dda5c437f0 730 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 731
mbed_official 133:d4dda5c437f0 732 /* Check the ETH state to BUSY */
mbed_official 133:d4dda5c437f0 733 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 734
mbed_official 133:d4dda5c437f0 735 /* Check if segment is not owned by DMA */
mbed_official 133:d4dda5c437f0 736 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 133:d4dda5c437f0 737 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 133:d4dda5c437f0 738 {
mbed_official 133:d4dda5c437f0 739 /* Check if last segment */
mbed_official 133:d4dda5c437f0 740 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 133:d4dda5c437f0 741 {
mbed_official 133:d4dda5c437f0 742 /* increment segment count */
mbed_official 133:d4dda5c437f0 743 (heth->RxFrameInfos).SegCount++;
mbed_official 133:d4dda5c437f0 744
mbed_official 133:d4dda5c437f0 745 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 133:d4dda5c437f0 746 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 133:d4dda5c437f0 747 {
mbed_official 133:d4dda5c437f0 748 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 133:d4dda5c437f0 749 }
mbed_official 133:d4dda5c437f0 750
mbed_official 133:d4dda5c437f0 751 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 133:d4dda5c437f0 752
mbed_official 133:d4dda5c437f0 753 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 133:d4dda5c437f0 754 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 133:d4dda5c437f0 755 heth->RxFrameInfos.length = framelength;
mbed_official 133:d4dda5c437f0 756
mbed_official 133:d4dda5c437f0 757 /* Get the address of the buffer start address */
mbed_official 133:d4dda5c437f0 758 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 133:d4dda5c437f0 759 /* point to next descriptor */
mbed_official 133:d4dda5c437f0 760 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 761
mbed_official 133:d4dda5c437f0 762 /* Set HAL State to Ready */
mbed_official 133:d4dda5c437f0 763 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 764
mbed_official 133:d4dda5c437f0 765 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 766 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 767
mbed_official 133:d4dda5c437f0 768 /* Return function status */
mbed_official 133:d4dda5c437f0 769 return HAL_OK;
mbed_official 133:d4dda5c437f0 770 }
mbed_official 133:d4dda5c437f0 771 /* Check if first segment */
mbed_official 133:d4dda5c437f0 772 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 133:d4dda5c437f0 773 {
mbed_official 133:d4dda5c437f0 774 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 133:d4dda5c437f0 775 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 133:d4dda5c437f0 776 (heth->RxFrameInfos).SegCount = 1;
mbed_official 133:d4dda5c437f0 777 /* Point to next descriptor */
mbed_official 133:d4dda5c437f0 778 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 779 }
mbed_official 133:d4dda5c437f0 780 /* Check if intermediate segment */
mbed_official 133:d4dda5c437f0 781 else
mbed_official 133:d4dda5c437f0 782 {
mbed_official 133:d4dda5c437f0 783 (heth->RxFrameInfos).SegCount++;
mbed_official 133:d4dda5c437f0 784 /* Point to next descriptor */
mbed_official 133:d4dda5c437f0 785 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 786 }
mbed_official 133:d4dda5c437f0 787 }
mbed_official 133:d4dda5c437f0 788
mbed_official 133:d4dda5c437f0 789 /* Set ETH HAL State to Ready */
mbed_official 133:d4dda5c437f0 790 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 791
mbed_official 133:d4dda5c437f0 792 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 793 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 794
mbed_official 133:d4dda5c437f0 795 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 796 }
mbed_official 133:d4dda5c437f0 797
mbed_official 133:d4dda5c437f0 798 /**
mbed_official 133:d4dda5c437f0 799 * @brief Gets the Received frame in interrupt mode.
mbed_official 242:7074e42da0b2 800 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 801 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 802 * @retval HAL status
mbed_official 133:d4dda5c437f0 803 */
mbed_official 133:d4dda5c437f0 804 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 805 {
mbed_official 133:d4dda5c437f0 806 uint32_t descriptorscancounter = 0;
mbed_official 133:d4dda5c437f0 807
mbed_official 133:d4dda5c437f0 808 /* Process Locked */
mbed_official 133:d4dda5c437f0 809 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 810
mbed_official 133:d4dda5c437f0 811 /* Set ETH HAL State to BUSY */
mbed_official 133:d4dda5c437f0 812 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 813
mbed_official 133:d4dda5c437f0 814 /* Scan descriptors owned by CPU */
mbed_official 133:d4dda5c437f0 815 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 133:d4dda5c437f0 816 {
mbed_official 133:d4dda5c437f0 817 /* Just for security */
mbed_official 133:d4dda5c437f0 818 descriptorscancounter++;
mbed_official 133:d4dda5c437f0 819
mbed_official 133:d4dda5c437f0 820 /* Check if first segment in frame */
mbed_official 133:d4dda5c437f0 821 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 133:d4dda5c437f0 822 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 133:d4dda5c437f0 823 {
mbed_official 133:d4dda5c437f0 824 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 133:d4dda5c437f0 825 heth->RxFrameInfos.SegCount = 1;
mbed_official 133:d4dda5c437f0 826 /* Point to next descriptor */
mbed_official 133:d4dda5c437f0 827 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 828 }
mbed_official 133:d4dda5c437f0 829 /* Check if intermediate segment */
mbed_official 133:d4dda5c437f0 830 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 133:d4dda5c437f0 831 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 133:d4dda5c437f0 832 {
mbed_official 133:d4dda5c437f0 833 /* Increment segment count */
mbed_official 133:d4dda5c437f0 834 (heth->RxFrameInfos.SegCount)++;
mbed_official 133:d4dda5c437f0 835 /* Point to next descriptor */
mbed_official 133:d4dda5c437f0 836 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 837 }
mbed_official 133:d4dda5c437f0 838 /* Should be last segment */
mbed_official 133:d4dda5c437f0 839 else
mbed_official 133:d4dda5c437f0 840 {
mbed_official 133:d4dda5c437f0 841 /* Last segment */
mbed_official 133:d4dda5c437f0 842 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 133:d4dda5c437f0 843
mbed_official 133:d4dda5c437f0 844 /* Increment segment count */
mbed_official 133:d4dda5c437f0 845 (heth->RxFrameInfos.SegCount)++;
mbed_official 133:d4dda5c437f0 846
mbed_official 133:d4dda5c437f0 847 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 133:d4dda5c437f0 848 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 133:d4dda5c437f0 849 {
mbed_official 133:d4dda5c437f0 850 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 133:d4dda5c437f0 851 }
mbed_official 133:d4dda5c437f0 852
mbed_official 133:d4dda5c437f0 853 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 133:d4dda5c437f0 854 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 133:d4dda5c437f0 855
mbed_official 133:d4dda5c437f0 856 /* Get the address of the buffer start address */
mbed_official 133:d4dda5c437f0 857 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 133:d4dda5c437f0 858
mbed_official 133:d4dda5c437f0 859 /* Point to next descriptor */
mbed_official 133:d4dda5c437f0 860 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 133:d4dda5c437f0 861
mbed_official 133:d4dda5c437f0 862 /* Set HAL State to Ready */
mbed_official 133:d4dda5c437f0 863 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 864
mbed_official 133:d4dda5c437f0 865 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 866 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 867
mbed_official 133:d4dda5c437f0 868 /* Return function status */
mbed_official 133:d4dda5c437f0 869 return HAL_OK;
mbed_official 133:d4dda5c437f0 870 }
mbed_official 133:d4dda5c437f0 871 }
mbed_official 133:d4dda5c437f0 872
mbed_official 133:d4dda5c437f0 873 /* Set HAL State to Ready */
mbed_official 133:d4dda5c437f0 874 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 875
mbed_official 133:d4dda5c437f0 876 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 877 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 878
mbed_official 133:d4dda5c437f0 879 /* Return function status */
mbed_official 133:d4dda5c437f0 880 return HAL_OK;
mbed_official 133:d4dda5c437f0 881 }
mbed_official 133:d4dda5c437f0 882
mbed_official 133:d4dda5c437f0 883 /**
mbed_official 133:d4dda5c437f0 884 * @brief This function handles ETH interrupt request.
mbed_official 242:7074e42da0b2 885 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 886 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 887 * @retval HAL status
mbed_official 133:d4dda5c437f0 888 */
mbed_official 133:d4dda5c437f0 889 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 890 {
mbed_official 133:d4dda5c437f0 891 /* Frame received */
mbed_official 133:d4dda5c437f0 892 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 133:d4dda5c437f0 893 {
mbed_official 133:d4dda5c437f0 894 /* Receive complete callback */
mbed_official 133:d4dda5c437f0 895 HAL_ETH_RxCpltCallback(heth);
mbed_official 133:d4dda5c437f0 896
mbed_official 133:d4dda5c437f0 897 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 133:d4dda5c437f0 898 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 133:d4dda5c437f0 899
mbed_official 133:d4dda5c437f0 900 /* Set HAL State to Ready */
mbed_official 133:d4dda5c437f0 901 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 902
mbed_official 133:d4dda5c437f0 903 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 904 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 905
mbed_official 133:d4dda5c437f0 906 }
mbed_official 133:d4dda5c437f0 907 /* Frame transmitted */
mbed_official 133:d4dda5c437f0 908 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 133:d4dda5c437f0 909 {
mbed_official 133:d4dda5c437f0 910 /* Transfer complete callback */
mbed_official 133:d4dda5c437f0 911 HAL_ETH_TxCpltCallback(heth);
mbed_official 133:d4dda5c437f0 912
mbed_official 133:d4dda5c437f0 913 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 133:d4dda5c437f0 914 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 133:d4dda5c437f0 915
mbed_official 133:d4dda5c437f0 916 /* Set HAL State to Ready */
mbed_official 133:d4dda5c437f0 917 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 918
mbed_official 133:d4dda5c437f0 919 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 920 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 921 }
mbed_official 133:d4dda5c437f0 922
mbed_official 133:d4dda5c437f0 923 /* Clear the interrupt flags */
mbed_official 133:d4dda5c437f0 924 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 133:d4dda5c437f0 925
mbed_official 133:d4dda5c437f0 926 /* ETH DMA Error */
mbed_official 133:d4dda5c437f0 927 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 133:d4dda5c437f0 928 {
mbed_official 133:d4dda5c437f0 929 /* Ethernet Error callback */
mbed_official 133:d4dda5c437f0 930 HAL_ETH_ErrorCallback(heth);
mbed_official 133:d4dda5c437f0 931
mbed_official 133:d4dda5c437f0 932 /* Clear the interrupt flags */
mbed_official 133:d4dda5c437f0 933 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 133:d4dda5c437f0 934
mbed_official 133:d4dda5c437f0 935 /* Set HAL State to Ready */
mbed_official 133:d4dda5c437f0 936 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 937
mbed_official 133:d4dda5c437f0 938 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 939 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 940 }
mbed_official 133:d4dda5c437f0 941 }
mbed_official 133:d4dda5c437f0 942
mbed_official 133:d4dda5c437f0 943 /**
mbed_official 133:d4dda5c437f0 944 * @brief Tx Transfer completed callbacks.
mbed_official 242:7074e42da0b2 945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 946 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 947 * @retval None
mbed_official 133:d4dda5c437f0 948 */
mbed_official 133:d4dda5c437f0 949 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 950 {
mbed_official 133:d4dda5c437f0 951 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 952 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 953 */
mbed_official 133:d4dda5c437f0 954 }
mbed_official 133:d4dda5c437f0 955
mbed_official 133:d4dda5c437f0 956 /**
mbed_official 133:d4dda5c437f0 957 * @brief Rx Transfer completed callbacks.
mbed_official 242:7074e42da0b2 958 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 959 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 960 * @retval None
mbed_official 133:d4dda5c437f0 961 */
mbed_official 133:d4dda5c437f0 962 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 963 {
mbed_official 133:d4dda5c437f0 964 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 965 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 966 */
mbed_official 133:d4dda5c437f0 967 }
mbed_official 133:d4dda5c437f0 968
mbed_official 133:d4dda5c437f0 969 /**
mbed_official 133:d4dda5c437f0 970 * @brief Ethernet transfer error callbacks
mbed_official 242:7074e42da0b2 971 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 972 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 973 * @retval None
mbed_official 133:d4dda5c437f0 974 */
mbed_official 133:d4dda5c437f0 975 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 976 {
mbed_official 133:d4dda5c437f0 977 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 978 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 979 */
mbed_official 133:d4dda5c437f0 980 }
mbed_official 133:d4dda5c437f0 981
mbed_official 133:d4dda5c437f0 982 /**
mbed_official 133:d4dda5c437f0 983 * @brief Reads a PHY register
mbed_official 242:7074e42da0b2 984 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 985 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 986 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 133:d4dda5c437f0 987 * This parameter can be one of the following values:
mbed_official 242:7074e42da0b2 988 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 242:7074e42da0b2 989 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 242:7074e42da0b2 990 * More PHY register could be read depending on the used PHY
mbed_official 133:d4dda5c437f0 991 * @param RegValue: PHY register value
mbed_official 242:7074e42da0b2 992 * @retval HAL status
mbed_official 133:d4dda5c437f0 993 */
mbed_official 133:d4dda5c437f0 994 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 133:d4dda5c437f0 995 {
mbed_official 133:d4dda5c437f0 996 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 997 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 998
mbed_official 133:d4dda5c437f0 999 /* Check parameters */
mbed_official 133:d4dda5c437f0 1000 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 133:d4dda5c437f0 1001
mbed_official 133:d4dda5c437f0 1002 /* Check the ETH peripheral state */
mbed_official 133:d4dda5c437f0 1003 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 133:d4dda5c437f0 1004 {
mbed_official 133:d4dda5c437f0 1005 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1006 }
mbed_official 133:d4dda5c437f0 1007 /* Set ETH HAL State to BUSY_RD */
mbed_official 133:d4dda5c437f0 1008 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 133:d4dda5c437f0 1009
mbed_official 133:d4dda5c437f0 1010 /* Get the ETHERNET MACMIIAR value */
mbed_official 133:d4dda5c437f0 1011 tmpreg = heth->Instance->MACMIIAR;
mbed_official 133:d4dda5c437f0 1012
mbed_official 133:d4dda5c437f0 1013 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 133:d4dda5c437f0 1014 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 133:d4dda5c437f0 1015
mbed_official 133:d4dda5c437f0 1016 /* Prepare the MII address register value */
mbed_official 133:d4dda5c437f0 1017 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 133:d4dda5c437f0 1018 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 133:d4dda5c437f0 1019 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 133:d4dda5c437f0 1020 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 133:d4dda5c437f0 1021
mbed_official 133:d4dda5c437f0 1022 /* Write the result value into the MII Address register */
mbed_official 133:d4dda5c437f0 1023 heth->Instance->MACMIIAR = tmpreg;
mbed_official 133:d4dda5c437f0 1024
mbed_official 133:d4dda5c437f0 1025 /* Check for the Busy flag */
mbed_official 133:d4dda5c437f0 1026 do
mbed_official 133:d4dda5c437f0 1027 {
mbed_official 133:d4dda5c437f0 1028 timeout++;
mbed_official 133:d4dda5c437f0 1029 tmpreg = heth->Instance->MACMIIAR;
mbed_official 133:d4dda5c437f0 1030 } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO));
mbed_official 133:d4dda5c437f0 1031
mbed_official 133:d4dda5c437f0 1032 /* Return ERROR in case of timeout */
mbed_official 133:d4dda5c437f0 1033 if(timeout == PHY_READ_TO)
mbed_official 133:d4dda5c437f0 1034 {
mbed_official 133:d4dda5c437f0 1035 /* Set ETH HAL State to READY */
mbed_official 133:d4dda5c437f0 1036 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1037 /* Return HAL_TIMEOUT */
mbed_official 133:d4dda5c437f0 1038 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1039 }
mbed_official 133:d4dda5c437f0 1040
mbed_official 133:d4dda5c437f0 1041 /* Get MACMIIDR value */
mbed_official 133:d4dda5c437f0 1042 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 133:d4dda5c437f0 1043
mbed_official 133:d4dda5c437f0 1044 /* Set ETH HAL State to READY */
mbed_official 133:d4dda5c437f0 1045 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1046
mbed_official 133:d4dda5c437f0 1047 /* Return function status */
mbed_official 133:d4dda5c437f0 1048 return HAL_OK;
mbed_official 133:d4dda5c437f0 1049 }
mbed_official 133:d4dda5c437f0 1050
mbed_official 133:d4dda5c437f0 1051 /**
mbed_official 133:d4dda5c437f0 1052 * @brief Writes to a PHY register.
mbed_official 242:7074e42da0b2 1053 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1054 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1055 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 133:d4dda5c437f0 1056 * This parameter can be one of the following values:
mbed_official 242:7074e42da0b2 1057 * PHY_BCR: Transceiver Control Register.
mbed_official 242:7074e42da0b2 1058 * More PHY register could be written depending on the used PHY
mbed_official 133:d4dda5c437f0 1059 * @param RegValue: the value to write
mbed_official 133:d4dda5c437f0 1060 * @retval HAL status
mbed_official 133:d4dda5c437f0 1061 */
mbed_official 133:d4dda5c437f0 1062 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 133:d4dda5c437f0 1063 {
mbed_official 133:d4dda5c437f0 1064 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1065 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1066
mbed_official 133:d4dda5c437f0 1067 /* Check parameters */
mbed_official 133:d4dda5c437f0 1068 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 133:d4dda5c437f0 1069
mbed_official 133:d4dda5c437f0 1070 /* Check the ETH peripheral state */
mbed_official 133:d4dda5c437f0 1071 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 133:d4dda5c437f0 1072 {
mbed_official 133:d4dda5c437f0 1073 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1074 }
mbed_official 133:d4dda5c437f0 1075 /* Set ETH HAL State to BUSY_WR */
mbed_official 133:d4dda5c437f0 1076 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 133:d4dda5c437f0 1077
mbed_official 133:d4dda5c437f0 1078 /* Get the ETHERNET MACMIIAR value */
mbed_official 133:d4dda5c437f0 1079 tmpreg = heth->Instance->MACMIIAR;
mbed_official 133:d4dda5c437f0 1080
mbed_official 133:d4dda5c437f0 1081 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 133:d4dda5c437f0 1082 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 133:d4dda5c437f0 1083
mbed_official 133:d4dda5c437f0 1084 /* Prepare the MII register address value */
mbed_official 133:d4dda5c437f0 1085 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 133:d4dda5c437f0 1086 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 133:d4dda5c437f0 1087 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 133:d4dda5c437f0 1088 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 133:d4dda5c437f0 1089
mbed_official 133:d4dda5c437f0 1090 /* Give the value to the MII data register */
mbed_official 133:d4dda5c437f0 1091 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 133:d4dda5c437f0 1092
mbed_official 133:d4dda5c437f0 1093 /* Write the result value into the MII Address register */
mbed_official 133:d4dda5c437f0 1094 heth->Instance->MACMIIAR = tmpreg;
mbed_official 133:d4dda5c437f0 1095
mbed_official 133:d4dda5c437f0 1096 /* Check for the Busy flag */
mbed_official 133:d4dda5c437f0 1097 do
mbed_official 133:d4dda5c437f0 1098 {
mbed_official 133:d4dda5c437f0 1099 timeout++;
mbed_official 133:d4dda5c437f0 1100 tmpreg = heth->Instance->MACMIIAR;
mbed_official 133:d4dda5c437f0 1101 } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO));
mbed_official 133:d4dda5c437f0 1102
mbed_official 133:d4dda5c437f0 1103 /* Return TIMETOUT in case of timeout */
mbed_official 133:d4dda5c437f0 1104 if(timeout == PHY_WRITE_TO)
mbed_official 133:d4dda5c437f0 1105 {
mbed_official 133:d4dda5c437f0 1106 /* Set ETH HAL State to READY */
mbed_official 133:d4dda5c437f0 1107 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1108
mbed_official 133:d4dda5c437f0 1109 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1110 }
mbed_official 133:d4dda5c437f0 1111
mbed_official 133:d4dda5c437f0 1112 /* Set ETH HAL State to READY */
mbed_official 133:d4dda5c437f0 1113 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1114
mbed_official 133:d4dda5c437f0 1115 /* Return function status */
mbed_official 133:d4dda5c437f0 1116 return HAL_OK;
mbed_official 133:d4dda5c437f0 1117 }
mbed_official 133:d4dda5c437f0 1118
mbed_official 133:d4dda5c437f0 1119 /**
mbed_official 133:d4dda5c437f0 1120 * @}
mbed_official 133:d4dda5c437f0 1121 */
mbed_official 133:d4dda5c437f0 1122
mbed_official 133:d4dda5c437f0 1123 /** @defgroup ETH_Group3 Peripheral Control functions
mbed_official 133:d4dda5c437f0 1124 * @brief Peripheral Control functions
mbed_official 133:d4dda5c437f0 1125 *
mbed_official 133:d4dda5c437f0 1126 @verbatim
mbed_official 133:d4dda5c437f0 1127 ===============================================================================
mbed_official 133:d4dda5c437f0 1128 ##### Peripheral Control functions #####
mbed_official 133:d4dda5c437f0 1129 ===============================================================================
mbed_official 133:d4dda5c437f0 1130 [..] This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 1131 (+) Enable MAC and DMA transmission and reception.
mbed_official 133:d4dda5c437f0 1132 HAL_ETH_Start();
mbed_official 133:d4dda5c437f0 1133 (+) Disable MAC and DMA transmission and reception.
mbed_official 133:d4dda5c437f0 1134 HAL_ETH_Stop();
mbed_official 133:d4dda5c437f0 1135 (+) Set the MAC configuration in runtime mode
mbed_official 133:d4dda5c437f0 1136 HAL_ETH_ConfigMAC();
mbed_official 133:d4dda5c437f0 1137 (+) Set the DMA configuration in runtime mode
mbed_official 133:d4dda5c437f0 1138 HAL_ETH_ConfigDMA();
mbed_official 133:d4dda5c437f0 1139
mbed_official 133:d4dda5c437f0 1140 @endverbatim
mbed_official 133:d4dda5c437f0 1141 * @{
mbed_official 133:d4dda5c437f0 1142 */
mbed_official 133:d4dda5c437f0 1143
mbed_official 133:d4dda5c437f0 1144 /**
mbed_official 133:d4dda5c437f0 1145 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 242:7074e42da0b2 1146 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1147 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1148 * @retval HAL status
mbed_official 133:d4dda5c437f0 1149 */
mbed_official 133:d4dda5c437f0 1150 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1151 {
mbed_official 133:d4dda5c437f0 1152 /* Process Locked */
mbed_official 133:d4dda5c437f0 1153 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 1154
mbed_official 133:d4dda5c437f0 1155 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 1156 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1157
mbed_official 133:d4dda5c437f0 1158 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 133:d4dda5c437f0 1159 ETH_MACTransmissionEnable(heth);
mbed_official 133:d4dda5c437f0 1160
mbed_official 133:d4dda5c437f0 1161 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 133:d4dda5c437f0 1162 ETH_MACReceptionEnable(heth);
mbed_official 133:d4dda5c437f0 1163
mbed_official 133:d4dda5c437f0 1164 /* Flush Transmit FIFO */
mbed_official 133:d4dda5c437f0 1165 ETH_FlushTransmitFIFO(heth);
mbed_official 133:d4dda5c437f0 1166
mbed_official 133:d4dda5c437f0 1167 /* Start DMA transmission */
mbed_official 133:d4dda5c437f0 1168 ETH_DMATransmissionEnable(heth);
mbed_official 133:d4dda5c437f0 1169
mbed_official 133:d4dda5c437f0 1170 /* Start DMA reception */
mbed_official 133:d4dda5c437f0 1171 ETH_DMAReceptionEnable(heth);
mbed_official 133:d4dda5c437f0 1172
mbed_official 133:d4dda5c437f0 1173 /* Set the ETH state to READY*/
mbed_official 133:d4dda5c437f0 1174 heth->State= HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1175
mbed_official 133:d4dda5c437f0 1176 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1177 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 1178
mbed_official 133:d4dda5c437f0 1179 /* Return function status */
mbed_official 133:d4dda5c437f0 1180 return HAL_OK;
mbed_official 133:d4dda5c437f0 1181 }
mbed_official 133:d4dda5c437f0 1182
mbed_official 133:d4dda5c437f0 1183 /**
mbed_official 133:d4dda5c437f0 1184 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 242:7074e42da0b2 1185 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1186 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1187 * @retval HAL status
mbed_official 133:d4dda5c437f0 1188 */
mbed_official 133:d4dda5c437f0 1189 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1190 {
mbed_official 133:d4dda5c437f0 1191 /* Process Locked */
mbed_official 133:d4dda5c437f0 1192 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 1193
mbed_official 133:d4dda5c437f0 1194 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 1195 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1196
mbed_official 133:d4dda5c437f0 1197 /* Stop DMA transmission */
mbed_official 133:d4dda5c437f0 1198 ETH_DMATransmissionDisable(heth);
mbed_official 133:d4dda5c437f0 1199
mbed_official 133:d4dda5c437f0 1200 /* Stop DMA reception */
mbed_official 133:d4dda5c437f0 1201 ETH_DMAReceptionDisable(heth);
mbed_official 133:d4dda5c437f0 1202
mbed_official 133:d4dda5c437f0 1203 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 133:d4dda5c437f0 1204 ETH_MACReceptionDisable(heth);
mbed_official 133:d4dda5c437f0 1205
mbed_official 133:d4dda5c437f0 1206 /* Flush Transmit FIFO */
mbed_official 133:d4dda5c437f0 1207 ETH_FlushTransmitFIFO(heth);
mbed_official 133:d4dda5c437f0 1208
mbed_official 133:d4dda5c437f0 1209 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 133:d4dda5c437f0 1210 ETH_MACTransmissionDisable(heth);
mbed_official 133:d4dda5c437f0 1211
mbed_official 133:d4dda5c437f0 1212 /* Set the ETH state*/
mbed_official 133:d4dda5c437f0 1213 heth->State = HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1214
mbed_official 133:d4dda5c437f0 1215 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1216 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 1217
mbed_official 133:d4dda5c437f0 1218 /* Return function status */
mbed_official 133:d4dda5c437f0 1219 return HAL_OK;
mbed_official 133:d4dda5c437f0 1220 }
mbed_official 133:d4dda5c437f0 1221
mbed_official 133:d4dda5c437f0 1222 /**
mbed_official 133:d4dda5c437f0 1223 * @brief Set ETH MAC Configuration.
mbed_official 242:7074e42da0b2 1224 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1225 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1226 * @param macconf: MAC Configuration structure
mbed_official 133:d4dda5c437f0 1227 * @retval HAL status
mbed_official 133:d4dda5c437f0 1228 */
mbed_official 133:d4dda5c437f0 1229 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 133:d4dda5c437f0 1230 {
mbed_official 133:d4dda5c437f0 1231 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1232
mbed_official 133:d4dda5c437f0 1233 /* Process Locked */
mbed_official 133:d4dda5c437f0 1234 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 1235
mbed_official 133:d4dda5c437f0 1236 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 1237 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1238
mbed_official 133:d4dda5c437f0 1239 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 133:d4dda5c437f0 1240 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 133:d4dda5c437f0 1241
mbed_official 133:d4dda5c437f0 1242 if (macconf != NULL)
mbed_official 133:d4dda5c437f0 1243 {
mbed_official 133:d4dda5c437f0 1244 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1245 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 133:d4dda5c437f0 1246 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 133:d4dda5c437f0 1247 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 133:d4dda5c437f0 1248 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 133:d4dda5c437f0 1249 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 133:d4dda5c437f0 1250 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 133:d4dda5c437f0 1251 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 133:d4dda5c437f0 1252 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 133:d4dda5c437f0 1253 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 133:d4dda5c437f0 1254 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 133:d4dda5c437f0 1255 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 133:d4dda5c437f0 1256 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 133:d4dda5c437f0 1257 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 133:d4dda5c437f0 1258 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 133:d4dda5c437f0 1259 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 133:d4dda5c437f0 1260 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 133:d4dda5c437f0 1261 assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
mbed_official 133:d4dda5c437f0 1262 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 133:d4dda5c437f0 1263 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 133:d4dda5c437f0 1264 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 133:d4dda5c437f0 1265 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 133:d4dda5c437f0 1266 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 133:d4dda5c437f0 1267 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 133:d4dda5c437f0 1268 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 133:d4dda5c437f0 1269 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 133:d4dda5c437f0 1270 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 133:d4dda5c437f0 1271 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 133:d4dda5c437f0 1272
mbed_official 133:d4dda5c437f0 1273 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1274 /* Get the ETHERNET MACCR value */
mbed_official 133:d4dda5c437f0 1275 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1276 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 133:d4dda5c437f0 1277 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 133:d4dda5c437f0 1278
mbed_official 133:d4dda5c437f0 1279 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 133:d4dda5c437f0 1280 macconf->Jabber |
mbed_official 133:d4dda5c437f0 1281 macconf->InterFrameGap |
mbed_official 133:d4dda5c437f0 1282 macconf->CarrierSense |
mbed_official 133:d4dda5c437f0 1283 (heth->Init).Speed |
mbed_official 133:d4dda5c437f0 1284 macconf->ReceiveOwn |
mbed_official 133:d4dda5c437f0 1285 macconf->LoopbackMode |
mbed_official 133:d4dda5c437f0 1286 (heth->Init).DuplexMode |
mbed_official 133:d4dda5c437f0 1287 macconf->ChecksumOffload |
mbed_official 133:d4dda5c437f0 1288 macconf->RetryTransmission |
mbed_official 133:d4dda5c437f0 1289 macconf->AutomaticPadCRCStrip |
mbed_official 133:d4dda5c437f0 1290 macconf->BackOffLimit |
mbed_official 133:d4dda5c437f0 1291 macconf->DeferralCheck);
mbed_official 133:d4dda5c437f0 1292
mbed_official 133:d4dda5c437f0 1293 /* Write to ETHERNET MACCR */
mbed_official 133:d4dda5c437f0 1294 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1295
mbed_official 133:d4dda5c437f0 1296 /* Wait until the write operation will be taken into account :
mbed_official 133:d4dda5c437f0 1297 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1298 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1299 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1300 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1301
mbed_official 133:d4dda5c437f0 1302 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1303 /* Write to ETHERNET MACFFR */
mbed_official 133:d4dda5c437f0 1304 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 133:d4dda5c437f0 1305 macconf->SourceAddrFilter |
mbed_official 133:d4dda5c437f0 1306 macconf->PassControlFrames |
mbed_official 133:d4dda5c437f0 1307 macconf->BroadcastFramesReception |
mbed_official 133:d4dda5c437f0 1308 macconf->DestinationAddrFilter |
mbed_official 133:d4dda5c437f0 1309 macconf->PromiscuousMode |
mbed_official 133:d4dda5c437f0 1310 macconf->MulticastFramesFilter |
mbed_official 133:d4dda5c437f0 1311 macconf->UnicastFramesFilter);
mbed_official 133:d4dda5c437f0 1312
mbed_official 133:d4dda5c437f0 1313 /* Wait until the write operation will be taken into account :
mbed_official 133:d4dda5c437f0 1314 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1315 tmpreg = (heth->Instance)->MACFFR;
mbed_official 133:d4dda5c437f0 1316 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1317 (heth->Instance)->MACFFR = tmpreg;
mbed_official 133:d4dda5c437f0 1318
mbed_official 133:d4dda5c437f0 1319 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 133:d4dda5c437f0 1320 /* Write to ETHERNET MACHTHR */
mbed_official 133:d4dda5c437f0 1321 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 133:d4dda5c437f0 1322
mbed_official 133:d4dda5c437f0 1323 /* Write to ETHERNET MACHTLR */
mbed_official 133:d4dda5c437f0 1324 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 133:d4dda5c437f0 1325 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1326
mbed_official 133:d4dda5c437f0 1327 /* Get the ETHERNET MACFCR value */
mbed_official 133:d4dda5c437f0 1328 tmpreg = (heth->Instance)->MACFCR;
mbed_official 133:d4dda5c437f0 1329 /* Clear xx bits */
mbed_official 133:d4dda5c437f0 1330 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 133:d4dda5c437f0 1331
mbed_official 133:d4dda5c437f0 1332 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 133:d4dda5c437f0 1333 macconf->ZeroQuantaPause |
mbed_official 133:d4dda5c437f0 1334 macconf->PauseLowThreshold |
mbed_official 133:d4dda5c437f0 1335 macconf->UnicastPauseFrameDetect |
mbed_official 133:d4dda5c437f0 1336 macconf->ReceiveFlowControl |
mbed_official 133:d4dda5c437f0 1337 macconf->TransmitFlowControl);
mbed_official 133:d4dda5c437f0 1338
mbed_official 133:d4dda5c437f0 1339 /* Write to ETHERNET MACFCR */
mbed_official 133:d4dda5c437f0 1340 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1341
mbed_official 133:d4dda5c437f0 1342 /* Wait until the write operation will be taken into account :
mbed_official 133:d4dda5c437f0 1343 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1344 tmpreg = (heth->Instance)->MACFCR;
mbed_official 133:d4dda5c437f0 1345 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1346 (heth->Instance)->MACFCR = tmpreg;
mbed_official 133:d4dda5c437f0 1347
mbed_official 133:d4dda5c437f0 1348 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 133:d4dda5c437f0 1349 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 133:d4dda5c437f0 1350 macconf->VLANTagIdentifier);
mbed_official 133:d4dda5c437f0 1351
mbed_official 133:d4dda5c437f0 1352 /* Wait until the write operation will be taken into account :
mbed_official 133:d4dda5c437f0 1353 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1354 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 133:d4dda5c437f0 1355 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1356 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 133:d4dda5c437f0 1357 }
mbed_official 133:d4dda5c437f0 1358 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 133:d4dda5c437f0 1359 {
mbed_official 133:d4dda5c437f0 1360 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1361 /* Get the ETHERNET MACCR value */
mbed_official 133:d4dda5c437f0 1362 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1363
mbed_official 133:d4dda5c437f0 1364 /* Clear FES and DM bits */
mbed_official 133:d4dda5c437f0 1365 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 133:d4dda5c437f0 1366
mbed_official 133:d4dda5c437f0 1367 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 133:d4dda5c437f0 1368
mbed_official 133:d4dda5c437f0 1369 /* Write to ETHERNET MACCR */
mbed_official 133:d4dda5c437f0 1370 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1371
mbed_official 133:d4dda5c437f0 1372 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1373 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1374 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1375 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1376 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1377 }
mbed_official 133:d4dda5c437f0 1378
mbed_official 133:d4dda5c437f0 1379 /* Set the ETH state to Ready */
mbed_official 133:d4dda5c437f0 1380 heth->State= HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1381
mbed_official 133:d4dda5c437f0 1382 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1383 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 1384
mbed_official 133:d4dda5c437f0 1385 /* Return function status */
mbed_official 133:d4dda5c437f0 1386 return HAL_OK;
mbed_official 133:d4dda5c437f0 1387 }
mbed_official 133:d4dda5c437f0 1388
mbed_official 133:d4dda5c437f0 1389 /**
mbed_official 133:d4dda5c437f0 1390 * @brief Sets ETH DMA Configuration.
mbed_official 242:7074e42da0b2 1391 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1392 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1393 * @param dmaconf: DMA Configuration structure
mbed_official 133:d4dda5c437f0 1394 * @retval HAL status
mbed_official 133:d4dda5c437f0 1395 */
mbed_official 133:d4dda5c437f0 1396 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 133:d4dda5c437f0 1397 {
mbed_official 133:d4dda5c437f0 1398 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1399
mbed_official 133:d4dda5c437f0 1400 /* Process Locked */
mbed_official 133:d4dda5c437f0 1401 __HAL_LOCK(heth);
mbed_official 133:d4dda5c437f0 1402
mbed_official 133:d4dda5c437f0 1403 /* Set the ETH peripheral state to BUSY */
mbed_official 133:d4dda5c437f0 1404 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1405
mbed_official 133:d4dda5c437f0 1406 /* Check parameters */
mbed_official 133:d4dda5c437f0 1407 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 133:d4dda5c437f0 1408 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 133:d4dda5c437f0 1409 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 133:d4dda5c437f0 1410 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 133:d4dda5c437f0 1411 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 133:d4dda5c437f0 1412 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 133:d4dda5c437f0 1413 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 133:d4dda5c437f0 1414 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 133:d4dda5c437f0 1415 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 133:d4dda5c437f0 1416 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 133:d4dda5c437f0 1417 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 133:d4dda5c437f0 1418 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 133:d4dda5c437f0 1419 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 133:d4dda5c437f0 1420 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 133:d4dda5c437f0 1421 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 133:d4dda5c437f0 1422 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 133:d4dda5c437f0 1423
mbed_official 133:d4dda5c437f0 1424 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1425 /* Get the ETHERNET DMAOMR value */
mbed_official 133:d4dda5c437f0 1426 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 133:d4dda5c437f0 1427 /* Clear xx bits */
mbed_official 133:d4dda5c437f0 1428 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 133:d4dda5c437f0 1429
mbed_official 133:d4dda5c437f0 1430 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 133:d4dda5c437f0 1431 dmaconf->ReceiveStoreForward |
mbed_official 133:d4dda5c437f0 1432 dmaconf->FlushReceivedFrame |
mbed_official 133:d4dda5c437f0 1433 dmaconf->TransmitStoreForward |
mbed_official 133:d4dda5c437f0 1434 dmaconf->TransmitThresholdControl |
mbed_official 133:d4dda5c437f0 1435 dmaconf->ForwardErrorFrames |
mbed_official 133:d4dda5c437f0 1436 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 133:d4dda5c437f0 1437 dmaconf->ReceiveThresholdControl |
mbed_official 133:d4dda5c437f0 1438 dmaconf->SecondFrameOperate);
mbed_official 133:d4dda5c437f0 1439
mbed_official 133:d4dda5c437f0 1440 /* Write to ETHERNET DMAOMR */
mbed_official 133:d4dda5c437f0 1441 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1442
mbed_official 133:d4dda5c437f0 1443 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1444 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1445 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 133:d4dda5c437f0 1446 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1447 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 133:d4dda5c437f0 1448
mbed_official 133:d4dda5c437f0 1449 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1450 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 133:d4dda5c437f0 1451 dmaconf->FixedBurst |
mbed_official 133:d4dda5c437f0 1452 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 133:d4dda5c437f0 1453 dmaconf->TxDMABurstLength |
mbed_official 133:d4dda5c437f0 1454 dmaconf->EnhancedDescriptorFormat |
mbed_official 133:d4dda5c437f0 1455 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 133:d4dda5c437f0 1456 dmaconf->DMAArbitration |
mbed_official 133:d4dda5c437f0 1457 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 133:d4dda5c437f0 1458
mbed_official 133:d4dda5c437f0 1459 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1460 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1461 tmpreg = (heth->Instance)->DMABMR;
mbed_official 133:d4dda5c437f0 1462 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1463 (heth->Instance)->DMABMR = tmpreg;
mbed_official 133:d4dda5c437f0 1464
mbed_official 133:d4dda5c437f0 1465 /* Set the ETH state to Ready */
mbed_official 133:d4dda5c437f0 1466 heth->State= HAL_ETH_STATE_READY;
mbed_official 133:d4dda5c437f0 1467
mbed_official 133:d4dda5c437f0 1468 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1469 __HAL_UNLOCK(heth);
mbed_official 133:d4dda5c437f0 1470
mbed_official 133:d4dda5c437f0 1471 /* Return function status */
mbed_official 133:d4dda5c437f0 1472 return HAL_OK;
mbed_official 133:d4dda5c437f0 1473 }
mbed_official 133:d4dda5c437f0 1474
mbed_official 133:d4dda5c437f0 1475 /**
mbed_official 133:d4dda5c437f0 1476 * @}
mbed_official 133:d4dda5c437f0 1477 */
mbed_official 133:d4dda5c437f0 1478
mbed_official 133:d4dda5c437f0 1479 /** @defgroup ETH_Group4 Peripheral State functions
mbed_official 133:d4dda5c437f0 1480 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 1481 *
mbed_official 133:d4dda5c437f0 1482 @verbatim
mbed_official 133:d4dda5c437f0 1483 ===============================================================================
mbed_official 133:d4dda5c437f0 1484 ##### Peripheral State functions #####
mbed_official 133:d4dda5c437f0 1485 ===============================================================================
mbed_official 133:d4dda5c437f0 1486 [..]
mbed_official 133:d4dda5c437f0 1487 This subsection permits to get in run-time the status of the peripheral
mbed_official 133:d4dda5c437f0 1488 and the data flow.
mbed_official 133:d4dda5c437f0 1489 (+) Get the ETH handle state:
mbed_official 133:d4dda5c437f0 1490 HAL_ETH_GetState();
mbed_official 133:d4dda5c437f0 1491
mbed_official 133:d4dda5c437f0 1492
mbed_official 133:d4dda5c437f0 1493 @endverbatim
mbed_official 133:d4dda5c437f0 1494 * @{
mbed_official 133:d4dda5c437f0 1495 */
mbed_official 133:d4dda5c437f0 1496
mbed_official 133:d4dda5c437f0 1497 /**
mbed_official 133:d4dda5c437f0 1498 * @brief Return the ETH HAL state
mbed_official 242:7074e42da0b2 1499 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1500 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1501 * @retval HAL state
mbed_official 133:d4dda5c437f0 1502 */
mbed_official 133:d4dda5c437f0 1503 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1504 {
mbed_official 133:d4dda5c437f0 1505 /* Return ETH state */
mbed_official 133:d4dda5c437f0 1506 return heth->State;
mbed_official 133:d4dda5c437f0 1507 }
mbed_official 133:d4dda5c437f0 1508
mbed_official 133:d4dda5c437f0 1509 /**
mbed_official 133:d4dda5c437f0 1510 * @}
mbed_official 133:d4dda5c437f0 1511 */
mbed_official 133:d4dda5c437f0 1512
mbed_official 133:d4dda5c437f0 1513 /**
mbed_official 133:d4dda5c437f0 1514 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 242:7074e42da0b2 1515 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1516 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1517 * @param err: Ethernet Init error
mbed_official 133:d4dda5c437f0 1518 * @retval HAL status
mbed_official 133:d4dda5c437f0 1519 */
mbed_official 133:d4dda5c437f0 1520 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 133:d4dda5c437f0 1521 {
mbed_official 133:d4dda5c437f0 1522 ETH_MACInitTypeDef macinit;
mbed_official 133:d4dda5c437f0 1523 ETH_DMAInitTypeDef dmainit;
mbed_official 133:d4dda5c437f0 1524 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1525
mbed_official 133:d4dda5c437f0 1526 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 133:d4dda5c437f0 1527 {
mbed_official 133:d4dda5c437f0 1528 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 133:d4dda5c437f0 1529 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 133:d4dda5c437f0 1530
mbed_official 133:d4dda5c437f0 1531 /* Set Ethernet speed to 100M */
mbed_official 133:d4dda5c437f0 1532 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 133:d4dda5c437f0 1533 }
mbed_official 133:d4dda5c437f0 1534
mbed_official 133:d4dda5c437f0 1535 /* Ethernet MAC default initialization **************************************/
mbed_official 133:d4dda5c437f0 1536 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 133:d4dda5c437f0 1537 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 133:d4dda5c437f0 1538 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 133:d4dda5c437f0 1539 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 133:d4dda5c437f0 1540 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 133:d4dda5c437f0 1541 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 133:d4dda5c437f0 1542 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 133:d4dda5c437f0 1543 {
mbed_official 133:d4dda5c437f0 1544 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 133:d4dda5c437f0 1545 }
mbed_official 133:d4dda5c437f0 1546 else
mbed_official 133:d4dda5c437f0 1547 {
mbed_official 133:d4dda5c437f0 1548 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 133:d4dda5c437f0 1549 }
mbed_official 133:d4dda5c437f0 1550 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 133:d4dda5c437f0 1551 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 133:d4dda5c437f0 1552 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 133:d4dda5c437f0 1553 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 133:d4dda5c437f0 1554 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 133:d4dda5c437f0 1555 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 133:d4dda5c437f0 1556 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 133:d4dda5c437f0 1557 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 133:d4dda5c437f0 1558 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 133:d4dda5c437f0 1559 macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
mbed_official 133:d4dda5c437f0 1560 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 133:d4dda5c437f0 1561 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 133:d4dda5c437f0 1562 macinit.HashTableHigh = 0x0;
mbed_official 133:d4dda5c437f0 1563 macinit.HashTableLow = 0x0;
mbed_official 133:d4dda5c437f0 1564 macinit.PauseTime = 0x0;
mbed_official 133:d4dda5c437f0 1565 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 133:d4dda5c437f0 1566 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 133:d4dda5c437f0 1567 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 133:d4dda5c437f0 1568 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 133:d4dda5c437f0 1569 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 133:d4dda5c437f0 1570 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 133:d4dda5c437f0 1571 macinit.VLANTagIdentifier = 0x0;
mbed_official 133:d4dda5c437f0 1572
mbed_official 133:d4dda5c437f0 1573 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1574 /* Get the ETHERNET MACCR value */
mbed_official 133:d4dda5c437f0 1575 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1576 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 133:d4dda5c437f0 1577 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 133:d4dda5c437f0 1578 /* Set the WD bit according to ETH Watchdog value */
mbed_official 133:d4dda5c437f0 1579 /* Set the JD: bit according to ETH Jabber value */
mbed_official 133:d4dda5c437f0 1580 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 133:d4dda5c437f0 1581 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 133:d4dda5c437f0 1582 /* Set the FES bit according to ETH Speed value */
mbed_official 133:d4dda5c437f0 1583 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 133:d4dda5c437f0 1584 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 133:d4dda5c437f0 1585 /* Set the DM bit according to ETH Mode value */
mbed_official 133:d4dda5c437f0 1586 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 133:d4dda5c437f0 1587 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 133:d4dda5c437f0 1588 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 133:d4dda5c437f0 1589 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 133:d4dda5c437f0 1590 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 133:d4dda5c437f0 1591 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 133:d4dda5c437f0 1592 macinit.Jabber |
mbed_official 133:d4dda5c437f0 1593 macinit.InterFrameGap |
mbed_official 133:d4dda5c437f0 1594 macinit.CarrierSense |
mbed_official 133:d4dda5c437f0 1595 (heth->Init).Speed |
mbed_official 133:d4dda5c437f0 1596 macinit.ReceiveOwn |
mbed_official 133:d4dda5c437f0 1597 macinit.LoopbackMode |
mbed_official 133:d4dda5c437f0 1598 (heth->Init).DuplexMode |
mbed_official 133:d4dda5c437f0 1599 macinit.ChecksumOffload |
mbed_official 133:d4dda5c437f0 1600 macinit.RetryTransmission |
mbed_official 133:d4dda5c437f0 1601 macinit.AutomaticPadCRCStrip |
mbed_official 133:d4dda5c437f0 1602 macinit.BackOffLimit |
mbed_official 133:d4dda5c437f0 1603 macinit.DeferralCheck);
mbed_official 133:d4dda5c437f0 1604
mbed_official 133:d4dda5c437f0 1605 /* Write to ETHERNET MACCR */
mbed_official 133:d4dda5c437f0 1606 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1607
mbed_official 133:d4dda5c437f0 1608 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1609 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1610 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1611 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1612 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1613
mbed_official 133:d4dda5c437f0 1614 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 133:d4dda5c437f0 1615 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 133:d4dda5c437f0 1616 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 133:d4dda5c437f0 1617 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 133:d4dda5c437f0 1618 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 133:d4dda5c437f0 1619 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 133:d4dda5c437f0 1620 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 133:d4dda5c437f0 1621 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 133:d4dda5c437f0 1622 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 133:d4dda5c437f0 1623 /* Write to ETHERNET MACFFR */
mbed_official 133:d4dda5c437f0 1624 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 133:d4dda5c437f0 1625 macinit.SourceAddrFilter |
mbed_official 133:d4dda5c437f0 1626 macinit.PassControlFrames |
mbed_official 133:d4dda5c437f0 1627 macinit.BroadcastFramesReception |
mbed_official 133:d4dda5c437f0 1628 macinit.DestinationAddrFilter |
mbed_official 133:d4dda5c437f0 1629 macinit.PromiscuousMode |
mbed_official 133:d4dda5c437f0 1630 macinit.MulticastFramesFilter |
mbed_official 133:d4dda5c437f0 1631 macinit.UnicastFramesFilter);
mbed_official 133:d4dda5c437f0 1632
mbed_official 133:d4dda5c437f0 1633 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1634 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1635 tmpreg = (heth->Instance)->MACFFR;
mbed_official 133:d4dda5c437f0 1636 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1637 (heth->Instance)->MACFFR = tmpreg;
mbed_official 133:d4dda5c437f0 1638
mbed_official 133:d4dda5c437f0 1639 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 133:d4dda5c437f0 1640 /* Write to ETHERNET MACHTHR */
mbed_official 133:d4dda5c437f0 1641 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 133:d4dda5c437f0 1642
mbed_official 133:d4dda5c437f0 1643 /* Write to ETHERNET MACHTLR */
mbed_official 133:d4dda5c437f0 1644 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 133:d4dda5c437f0 1645 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 133:d4dda5c437f0 1646
mbed_official 133:d4dda5c437f0 1647 /* Get the ETHERNET MACFCR value */
mbed_official 133:d4dda5c437f0 1648 tmpreg = (heth->Instance)->MACFCR;
mbed_official 133:d4dda5c437f0 1649 /* Clear xx bits */
mbed_official 133:d4dda5c437f0 1650 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 133:d4dda5c437f0 1651
mbed_official 133:d4dda5c437f0 1652 /* Set the PT bit according to ETH PauseTime value */
mbed_official 133:d4dda5c437f0 1653 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 133:d4dda5c437f0 1654 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 133:d4dda5c437f0 1655 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 133:d4dda5c437f0 1656 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 133:d4dda5c437f0 1657 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 133:d4dda5c437f0 1658 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 133:d4dda5c437f0 1659 macinit.ZeroQuantaPause |
mbed_official 133:d4dda5c437f0 1660 macinit.PauseLowThreshold |
mbed_official 133:d4dda5c437f0 1661 macinit.UnicastPauseFrameDetect |
mbed_official 133:d4dda5c437f0 1662 macinit.ReceiveFlowControl |
mbed_official 133:d4dda5c437f0 1663 macinit.TransmitFlowControl);
mbed_official 133:d4dda5c437f0 1664
mbed_official 133:d4dda5c437f0 1665 /* Write to ETHERNET MACFCR */
mbed_official 133:d4dda5c437f0 1666 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1667
mbed_official 133:d4dda5c437f0 1668 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1669 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1670 tmpreg = (heth->Instance)->MACFCR;
mbed_official 133:d4dda5c437f0 1671 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1672 (heth->Instance)->MACFCR = tmpreg;
mbed_official 133:d4dda5c437f0 1673
mbed_official 133:d4dda5c437f0 1674 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 133:d4dda5c437f0 1675 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 133:d4dda5c437f0 1676 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 133:d4dda5c437f0 1677 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 133:d4dda5c437f0 1678 macinit.VLANTagIdentifier);
mbed_official 133:d4dda5c437f0 1679
mbed_official 133:d4dda5c437f0 1680 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1681 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1682 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 133:d4dda5c437f0 1683 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1684 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 133:d4dda5c437f0 1685
mbed_official 133:d4dda5c437f0 1686 /* Ethernet DMA default initialization ************************************/
mbed_official 133:d4dda5c437f0 1687 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 133:d4dda5c437f0 1688 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 133:d4dda5c437f0 1689 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 133:d4dda5c437f0 1690 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 133:d4dda5c437f0 1691 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 133:d4dda5c437f0 1692 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 133:d4dda5c437f0 1693 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 133:d4dda5c437f0 1694 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 133:d4dda5c437f0 1695 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 133:d4dda5c437f0 1696 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 133:d4dda5c437f0 1697 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 133:d4dda5c437f0 1698 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 133:d4dda5c437f0 1699 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 133:d4dda5c437f0 1700 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 133:d4dda5c437f0 1701 dmainit.DescriptorSkipLength = 0x0;
mbed_official 133:d4dda5c437f0 1702 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 133:d4dda5c437f0 1703
mbed_official 133:d4dda5c437f0 1704 /* Get the ETHERNET DMAOMR value */
mbed_official 133:d4dda5c437f0 1705 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 133:d4dda5c437f0 1706 /* Clear xx bits */
mbed_official 133:d4dda5c437f0 1707 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 133:d4dda5c437f0 1708
mbed_official 133:d4dda5c437f0 1709 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 133:d4dda5c437f0 1710 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 133:d4dda5c437f0 1711 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 133:d4dda5c437f0 1712 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 133:d4dda5c437f0 1713 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 133:d4dda5c437f0 1714 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 133:d4dda5c437f0 1715 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 133:d4dda5c437f0 1716 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 133:d4dda5c437f0 1717 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 133:d4dda5c437f0 1718 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 133:d4dda5c437f0 1719 dmainit.ReceiveStoreForward |
mbed_official 133:d4dda5c437f0 1720 dmainit.FlushReceivedFrame |
mbed_official 133:d4dda5c437f0 1721 dmainit.TransmitStoreForward |
mbed_official 133:d4dda5c437f0 1722 dmainit.TransmitThresholdControl |
mbed_official 133:d4dda5c437f0 1723 dmainit.ForwardErrorFrames |
mbed_official 133:d4dda5c437f0 1724 dmainit.ForwardUndersizedGoodFrames |
mbed_official 133:d4dda5c437f0 1725 dmainit.ReceiveThresholdControl |
mbed_official 133:d4dda5c437f0 1726 dmainit.SecondFrameOperate);
mbed_official 133:d4dda5c437f0 1727
mbed_official 133:d4dda5c437f0 1728 /* Write to ETHERNET DMAOMR */
mbed_official 133:d4dda5c437f0 1729 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 133:d4dda5c437f0 1730
mbed_official 133:d4dda5c437f0 1731 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1732 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1733 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 133:d4dda5c437f0 1734 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1735 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 133:d4dda5c437f0 1736
mbed_official 133:d4dda5c437f0 1737 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 133:d4dda5c437f0 1738 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 133:d4dda5c437f0 1739 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 133:d4dda5c437f0 1740 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 133:d4dda5c437f0 1741 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 133:d4dda5c437f0 1742 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 133:d4dda5c437f0 1743 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 133:d4dda5c437f0 1744 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 133:d4dda5c437f0 1745 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 133:d4dda5c437f0 1746 dmainit.FixedBurst |
mbed_official 133:d4dda5c437f0 1747 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 133:d4dda5c437f0 1748 dmainit.TxDMABurstLength |
mbed_official 133:d4dda5c437f0 1749 dmainit.EnhancedDescriptorFormat |
mbed_official 133:d4dda5c437f0 1750 (dmainit.DescriptorSkipLength << 2) |
mbed_official 133:d4dda5c437f0 1751 dmainit.DMAArbitration |
mbed_official 133:d4dda5c437f0 1752 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 133:d4dda5c437f0 1753
mbed_official 133:d4dda5c437f0 1754 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1755 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1756 tmpreg = (heth->Instance)->DMABMR;
mbed_official 133:d4dda5c437f0 1757 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1758 (heth->Instance)->DMABMR = tmpreg;
mbed_official 133:d4dda5c437f0 1759
mbed_official 133:d4dda5c437f0 1760 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 133:d4dda5c437f0 1761 {
mbed_official 133:d4dda5c437f0 1762 /* Enable the Ethernet Rx Interrupt */
mbed_official 133:d4dda5c437f0 1763 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 133:d4dda5c437f0 1764 }
mbed_official 133:d4dda5c437f0 1765
mbed_official 133:d4dda5c437f0 1766 /* Initialize MAC address in ethernet MAC */
mbed_official 133:d4dda5c437f0 1767 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 133:d4dda5c437f0 1768 }
mbed_official 133:d4dda5c437f0 1769
mbed_official 133:d4dda5c437f0 1770 /**
mbed_official 133:d4dda5c437f0 1771 * @brief Configures the selected MAC address.
mbed_official 242:7074e42da0b2 1772 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1773 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1774 * @param MacAddr: The MAC address to configure
mbed_official 133:d4dda5c437f0 1775 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1776 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 133:d4dda5c437f0 1777 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 133:d4dda5c437f0 1778 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 133:d4dda5c437f0 1779 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 133:d4dda5c437f0 1780 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 133:d4dda5c437f0 1781 * @retval HAL status
mbed_official 133:d4dda5c437f0 1782 */
mbed_official 133:d4dda5c437f0 1783 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 133:d4dda5c437f0 1784 {
mbed_official 133:d4dda5c437f0 1785 uint32_t tmpreg;
mbed_official 133:d4dda5c437f0 1786
mbed_official 133:d4dda5c437f0 1787 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1788 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 133:d4dda5c437f0 1789
mbed_official 133:d4dda5c437f0 1790 /* Calculate the selected MAC address high register */
mbed_official 133:d4dda5c437f0 1791 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 133:d4dda5c437f0 1792 /* Load the selected MAC address high register */
mbed_official 133:d4dda5c437f0 1793 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 133:d4dda5c437f0 1794 /* Calculate the selected MAC address low register */
mbed_official 133:d4dda5c437f0 1795 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 133:d4dda5c437f0 1796
mbed_official 133:d4dda5c437f0 1797 /* Load the selected MAC address low register */
mbed_official 133:d4dda5c437f0 1798 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 133:d4dda5c437f0 1799 }
mbed_official 133:d4dda5c437f0 1800
mbed_official 133:d4dda5c437f0 1801 /**
mbed_official 133:d4dda5c437f0 1802 * @brief Enables the MAC transmission.
mbed_official 242:7074e42da0b2 1803 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1804 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1805 * @retval None
mbed_official 133:d4dda5c437f0 1806 */
mbed_official 133:d4dda5c437f0 1807 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1808 {
mbed_official 133:d4dda5c437f0 1809 __IO uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1810
mbed_official 133:d4dda5c437f0 1811 /* Enable the MAC transmission */
mbed_official 133:d4dda5c437f0 1812 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 133:d4dda5c437f0 1813
mbed_official 133:d4dda5c437f0 1814 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1815 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1816 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1817 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1818 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1819 }
mbed_official 133:d4dda5c437f0 1820
mbed_official 133:d4dda5c437f0 1821 /**
mbed_official 133:d4dda5c437f0 1822 * @brief Disables the MAC transmission.
mbed_official 242:7074e42da0b2 1823 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1824 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1825 * @retval None
mbed_official 133:d4dda5c437f0 1826 */
mbed_official 133:d4dda5c437f0 1827 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1828 {
mbed_official 133:d4dda5c437f0 1829 __IO uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1830
mbed_official 133:d4dda5c437f0 1831 /* Disable the MAC transmission */
mbed_official 133:d4dda5c437f0 1832 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 133:d4dda5c437f0 1833
mbed_official 133:d4dda5c437f0 1834 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1835 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1836 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1837 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1838 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1839 }
mbed_official 133:d4dda5c437f0 1840
mbed_official 133:d4dda5c437f0 1841 /**
mbed_official 133:d4dda5c437f0 1842 * @brief Enables the MAC reception.
mbed_official 242:7074e42da0b2 1843 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1844 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1845 * @retval None
mbed_official 133:d4dda5c437f0 1846 */
mbed_official 133:d4dda5c437f0 1847 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1848 {
mbed_official 133:d4dda5c437f0 1849 __IO uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1850
mbed_official 133:d4dda5c437f0 1851 /* Enable the MAC reception */
mbed_official 133:d4dda5c437f0 1852 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 133:d4dda5c437f0 1853
mbed_official 133:d4dda5c437f0 1854 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1855 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1856 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1857 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1858 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1859 }
mbed_official 133:d4dda5c437f0 1860
mbed_official 133:d4dda5c437f0 1861 /**
mbed_official 133:d4dda5c437f0 1862 * @brief Disables the MAC reception.
mbed_official 242:7074e42da0b2 1863 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1864 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1865 * @retval None
mbed_official 133:d4dda5c437f0 1866 */
mbed_official 133:d4dda5c437f0 1867 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1868 {
mbed_official 133:d4dda5c437f0 1869 __IO uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1870
mbed_official 133:d4dda5c437f0 1871 /* Disable the MAC reception */
mbed_official 133:d4dda5c437f0 1872 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 133:d4dda5c437f0 1873
mbed_official 133:d4dda5c437f0 1874 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1875 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1876 tmpreg = (heth->Instance)->MACCR;
mbed_official 133:d4dda5c437f0 1877 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1878 (heth->Instance)->MACCR = tmpreg;
mbed_official 133:d4dda5c437f0 1879 }
mbed_official 133:d4dda5c437f0 1880
mbed_official 133:d4dda5c437f0 1881 /**
mbed_official 133:d4dda5c437f0 1882 * @brief Enables the DMA transmission.
mbed_official 242:7074e42da0b2 1883 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1884 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1885 * @retval None
mbed_official 133:d4dda5c437f0 1886 */
mbed_official 133:d4dda5c437f0 1887 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1888 {
mbed_official 133:d4dda5c437f0 1889 /* Enable the DMA transmission */
mbed_official 133:d4dda5c437f0 1890 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 133:d4dda5c437f0 1891 }
mbed_official 133:d4dda5c437f0 1892
mbed_official 133:d4dda5c437f0 1893 /**
mbed_official 133:d4dda5c437f0 1894 * @brief Disables the DMA transmission.
mbed_official 242:7074e42da0b2 1895 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1896 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1897 * @retval None
mbed_official 133:d4dda5c437f0 1898 */
mbed_official 133:d4dda5c437f0 1899 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1900 {
mbed_official 133:d4dda5c437f0 1901 /* Disable the DMA transmission */
mbed_official 133:d4dda5c437f0 1902 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 133:d4dda5c437f0 1903 }
mbed_official 133:d4dda5c437f0 1904
mbed_official 133:d4dda5c437f0 1905 /**
mbed_official 133:d4dda5c437f0 1906 * @brief Enables the DMA reception.
mbed_official 242:7074e42da0b2 1907 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1908 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1909 * @retval None
mbed_official 133:d4dda5c437f0 1910 */
mbed_official 133:d4dda5c437f0 1911 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1912 {
mbed_official 133:d4dda5c437f0 1913 /* Enable the DMA reception */
mbed_official 133:d4dda5c437f0 1914 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 133:d4dda5c437f0 1915 }
mbed_official 133:d4dda5c437f0 1916
mbed_official 133:d4dda5c437f0 1917 /**
mbed_official 133:d4dda5c437f0 1918 * @brief Disables the DMA reception.
mbed_official 242:7074e42da0b2 1919 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1920 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1921 * @retval None
mbed_official 133:d4dda5c437f0 1922 */
mbed_official 133:d4dda5c437f0 1923 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1924 {
mbed_official 133:d4dda5c437f0 1925 /* Disable the DMA reception */
mbed_official 133:d4dda5c437f0 1926 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 133:d4dda5c437f0 1927 }
mbed_official 133:d4dda5c437f0 1928
mbed_official 133:d4dda5c437f0 1929 /**
mbed_official 133:d4dda5c437f0 1930 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 242:7074e42da0b2 1931 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1932 * the configuration information for ETHERNET module
mbed_official 133:d4dda5c437f0 1933 * @retval None
mbed_official 133:d4dda5c437f0 1934 */
mbed_official 133:d4dda5c437f0 1935 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 133:d4dda5c437f0 1936 {
mbed_official 133:d4dda5c437f0 1937 __IO uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1938
mbed_official 133:d4dda5c437f0 1939 /* Set the Flush Transmit FIFO bit */
mbed_official 133:d4dda5c437f0 1940 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 133:d4dda5c437f0 1941
mbed_official 133:d4dda5c437f0 1942 /* Wait until the write operation will be taken into account:
mbed_official 133:d4dda5c437f0 1943 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 133:d4dda5c437f0 1944 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 133:d4dda5c437f0 1945 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 133:d4dda5c437f0 1946 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 133:d4dda5c437f0 1947 }
mbed_official 133:d4dda5c437f0 1948
mbed_official 133:d4dda5c437f0 1949 /**
mbed_official 133:d4dda5c437f0 1950 * @}
mbed_official 133:d4dda5c437f0 1951 */
mbed_official 133:d4dda5c437f0 1952
mbed_official 133:d4dda5c437f0 1953 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 1954 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 1955 /**
mbed_official 133:d4dda5c437f0 1956 * @}
mbed_official 133:d4dda5c437f0 1957 */
mbed_official 133:d4dda5c437f0 1958
mbed_official 133:d4dda5c437f0 1959 /**
mbed_official 133:d4dda5c437f0 1960 * @}
mbed_official 133:d4dda5c437f0 1961 */
mbed_official 133:d4dda5c437f0 1962
mbed_official 133:d4dda5c437f0 1963 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/