mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c@139:e3413eddde57, 2014-03-27 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Mar 27 09:45:07 2014 +0000
- Revision:
- 139:e3413eddde57
- Parent:
- 84:f54042cbc282
- Child:
- 167:d5744491c362
Synchronized with git revision 3d49a491d4dd16466354746d3c329428840f5a03
Full URL: https://github.com/mbedmicro/mbed/commit/3d49a491d4dd16466354746d3c329428840f5a03/
Fixed readNB() bug
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 52:a51c77007319 | 1 | /** |
mbed_official | 52:a51c77007319 | 2 | ****************************************************************************** |
mbed_official | 52:a51c77007319 | 3 | * @file system_stm32f10x.c |
mbed_official | 52:a51c77007319 | 4 | * @author MCD Application Team |
mbed_official | 84:f54042cbc282 | 5 | * @version V3.6.1 |
mbed_official | 84:f54042cbc282 | 6 | * @date 05-March-2012 |
mbed_official | 52:a51c77007319 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
mbed_official | 52:a51c77007319 | 8 | * |
mbed_official | 52:a51c77007319 | 9 | * 1. This file provides two functions and one global variable to be called from |
mbed_official | 52:a51c77007319 | 10 | * user application: |
mbed_official | 52:a51c77007319 | 11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
mbed_official | 52:a51c77007319 | 12 | * factors, AHB/APBx prescalers and Flash settings). |
mbed_official | 52:a51c77007319 | 13 | * This function is called at startup just after reset and |
mbed_official | 52:a51c77007319 | 14 | * before branch to main program. This call is made inside |
mbed_official | 52:a51c77007319 | 15 | * the "startup_stm32f10x_xx.s" file. |
mbed_official | 52:a51c77007319 | 16 | * |
mbed_official | 52:a51c77007319 | 17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 52:a51c77007319 | 18 | * by the user application to setup the SysTick |
mbed_official | 52:a51c77007319 | 19 | * timer or configure other parameters. |
mbed_official | 52:a51c77007319 | 20 | * |
mbed_official | 52:a51c77007319 | 21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 52:a51c77007319 | 22 | * be called whenever the core clock is changed |
mbed_official | 52:a51c77007319 | 23 | * during program execution. |
mbed_official | 52:a51c77007319 | 24 | * |
mbed_official | 52:a51c77007319 | 25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
mbed_official | 52:a51c77007319 | 26 | * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to |
mbed_official | 52:a51c77007319 | 27 | * configure the system clock before to branch to main program. |
mbed_official | 52:a51c77007319 | 28 | * |
mbed_official | 52:a51c77007319 | 29 | * 3. If the system clock source selected by user fails to startup, the SystemInit() |
mbed_official | 52:a51c77007319 | 30 | * function will do nothing and HSI still used as system clock source. User can |
mbed_official | 52:a51c77007319 | 31 | * add some code to deal with this issue inside the SetSysClock() function. |
mbed_official | 52:a51c77007319 | 32 | * |
mbed_official | 52:a51c77007319 | 33 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on |
mbed_official | 52:a51c77007319 | 34 | * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. |
mbed_official | 52:a51c77007319 | 35 | * When HSE is used as system clock source, directly or through PLL, and you |
mbed_official | 52:a51c77007319 | 36 | * are using different crystal you have to adapt the HSE value to your own |
mbed_official | 52:a51c77007319 | 37 | * configuration. |
mbed_official | 139:e3413eddde57 | 38 | * 5. This file configures the system clock as follows: |
mbed_official | 139:e3413eddde57 | 39 | *----------------------------------------------------------------------------- |
mbed_official | 139:e3413eddde57 | 40 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
mbed_official | 139:e3413eddde57 | 41 | * | (external 8 MHz clock) | (internal 8 MHz) |
mbed_official | 139:e3413eddde57 | 42 | * | 2- PLL_HSE_XTAL | |
mbed_official | 139:e3413eddde57 | 43 | * | (external 8 MHz xtal) | |
mbed_official | 139:e3413eddde57 | 44 | *----------------------------------------------------------------------------- |
mbed_official | 139:e3413eddde57 | 45 | * SYSCLK(MHz) | 72 | 64 |
mbed_official | 139:e3413eddde57 | 46 | *----------------------------------------------------------------------------- |
mbed_official | 139:e3413eddde57 | 47 | * AHBCLK (MHz) | 72 | 64 |
mbed_official | 139:e3413eddde57 | 48 | *----------------------------------------------------------------------------- |
mbed_official | 139:e3413eddde57 | 49 | * APB1CLK (MHz) | 36 | 32 |
mbed_official | 139:e3413eddde57 | 50 | *----------------------------------------------------------------------------- |
mbed_official | 139:e3413eddde57 | 51 | * APB2CLK (MHz) | 72 | 64 |
mbed_official | 139:e3413eddde57 | 52 | *----------------------------------------------------------------------------- |
mbed_official | 139:e3413eddde57 | 53 | * USB capable (48 MHz precise clock) | YES | NO |
mbed_official | 139:e3413eddde57 | 54 | *----------------------------------------------------------------------------- |
mbed_official | 70:c1fbde68b492 | 55 | ******************************************************************************* |
mbed_official | 70:c1fbde68b492 | 56 | * Copyright (c) 2014, STMicroelectronics |
mbed_official | 70:c1fbde68b492 | 57 | * All rights reserved. |
mbed_official | 70:c1fbde68b492 | 58 | * |
mbed_official | 70:c1fbde68b492 | 59 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 70:c1fbde68b492 | 60 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 70:c1fbde68b492 | 61 | * |
mbed_official | 70:c1fbde68b492 | 62 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 70:c1fbde68b492 | 63 | * this list of conditions and the following disclaimer. |
mbed_official | 70:c1fbde68b492 | 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 70:c1fbde68b492 | 65 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 70:c1fbde68b492 | 66 | * and/or other materials provided with the distribution. |
mbed_official | 70:c1fbde68b492 | 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 70:c1fbde68b492 | 68 | * may be used to endorse or promote products derived from this software |
mbed_official | 70:c1fbde68b492 | 69 | * without specific prior written permission. |
mbed_official | 70:c1fbde68b492 | 70 | * |
mbed_official | 70:c1fbde68b492 | 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 70:c1fbde68b492 | 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 70:c1fbde68b492 | 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 70:c1fbde68b492 | 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 70:c1fbde68b492 | 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 70:c1fbde68b492 | 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 70:c1fbde68b492 | 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 70:c1fbde68b492 | 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 70:c1fbde68b492 | 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 70:c1fbde68b492 | 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 70:c1fbde68b492 | 81 | ******************************************************************************* |
mbed_official | 70:c1fbde68b492 | 82 | */ |
mbed_official | 52:a51c77007319 | 83 | |
mbed_official | 52:a51c77007319 | 84 | /** @addtogroup CMSIS |
mbed_official | 52:a51c77007319 | 85 | * @{ |
mbed_official | 52:a51c77007319 | 86 | */ |
mbed_official | 52:a51c77007319 | 87 | |
mbed_official | 52:a51c77007319 | 88 | /** @addtogroup stm32f10x_system |
mbed_official | 52:a51c77007319 | 89 | * @{ |
mbed_official | 52:a51c77007319 | 90 | */ |
mbed_official | 52:a51c77007319 | 91 | |
mbed_official | 52:a51c77007319 | 92 | /** @addtogroup STM32F10x_System_Private_Includes |
mbed_official | 52:a51c77007319 | 93 | * @{ |
mbed_official | 52:a51c77007319 | 94 | */ |
mbed_official | 52:a51c77007319 | 95 | |
mbed_official | 52:a51c77007319 | 96 | #include "stm32f10x.h" |
mbed_official | 52:a51c77007319 | 97 | |
mbed_official | 52:a51c77007319 | 98 | /** |
mbed_official | 52:a51c77007319 | 99 | * @} |
mbed_official | 52:a51c77007319 | 100 | */ |
mbed_official | 52:a51c77007319 | 101 | |
mbed_official | 52:a51c77007319 | 102 | /** @addtogroup STM32F10x_System_Private_TypesDefinitions |
mbed_official | 52:a51c77007319 | 103 | * @{ |
mbed_official | 52:a51c77007319 | 104 | */ |
mbed_official | 52:a51c77007319 | 105 | |
mbed_official | 52:a51c77007319 | 106 | /** |
mbed_official | 52:a51c77007319 | 107 | * @} |
mbed_official | 52:a51c77007319 | 108 | */ |
mbed_official | 52:a51c77007319 | 109 | |
mbed_official | 52:a51c77007319 | 110 | /** @addtogroup STM32F10x_System_Private_Defines |
mbed_official | 52:a51c77007319 | 111 | * @{ |
mbed_official | 52:a51c77007319 | 112 | */ |
mbed_official | 52:a51c77007319 | 113 | |
mbed_official | 52:a51c77007319 | 114 | /*!< Uncomment the following line if you need to relocate your vector Table in |
mbed_official | 52:a51c77007319 | 115 | Internal SRAM. */ |
mbed_official | 52:a51c77007319 | 116 | /* #define VECT_TAB_SRAM */ |
mbed_official | 52:a51c77007319 | 117 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
mbed_official | 52:a51c77007319 | 118 | This value must be a multiple of 0x200. */ |
mbed_official | 52:a51c77007319 | 119 | /** |
mbed_official | 52:a51c77007319 | 120 | * @} |
mbed_official | 52:a51c77007319 | 121 | */ |
mbed_official | 52:a51c77007319 | 122 | |
mbed_official | 52:a51c77007319 | 123 | /** @addtogroup STM32F10x_System_Private_Macros |
mbed_official | 52:a51c77007319 | 124 | * @{ |
mbed_official | 52:a51c77007319 | 125 | */ |
mbed_official | 52:a51c77007319 | 126 | |
mbed_official | 139:e3413eddde57 | 127 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
mbed_official | 139:e3413eddde57 | 128 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
mbed_official | 139:e3413eddde57 | 129 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
mbed_official | 139:e3413eddde57 | 130 | |
mbed_official | 52:a51c77007319 | 131 | /** |
mbed_official | 52:a51c77007319 | 132 | * @} |
mbed_official | 52:a51c77007319 | 133 | */ |
mbed_official | 52:a51c77007319 | 134 | |
mbed_official | 52:a51c77007319 | 135 | /** @addtogroup STM32F10x_System_Private_Variables |
mbed_official | 52:a51c77007319 | 136 | * @{ |
mbed_official | 52:a51c77007319 | 137 | */ |
mbed_official | 52:a51c77007319 | 138 | |
mbed_official | 139:e3413eddde57 | 139 | uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */ |
mbed_official | 52:a51c77007319 | 140 | |
mbed_official | 52:a51c77007319 | 141 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 52:a51c77007319 | 142 | /** |
mbed_official | 52:a51c77007319 | 143 | * @} |
mbed_official | 52:a51c77007319 | 144 | */ |
mbed_official | 52:a51c77007319 | 145 | |
mbed_official | 52:a51c77007319 | 146 | /** @addtogroup STM32F10x_System_Private_FunctionPrototypes |
mbed_official | 52:a51c77007319 | 147 | * @{ |
mbed_official | 52:a51c77007319 | 148 | */ |
mbed_official | 52:a51c77007319 | 149 | |
mbed_official | 139:e3413eddde57 | 150 | void SetSysClock(void); |
mbed_official | 52:a51c77007319 | 151 | |
mbed_official | 139:e3413eddde57 | 152 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 139:e3413eddde57 | 153 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
mbed_official | 52:a51c77007319 | 154 | #endif |
mbed_official | 52:a51c77007319 | 155 | |
mbed_official | 139:e3413eddde57 | 156 | uint8_t SetSysClock_PLL_HSI(void); |
mbed_official | 139:e3413eddde57 | 157 | |
mbed_official | 52:a51c77007319 | 158 | #ifdef DATA_IN_ExtSRAM |
mbed_official | 52:a51c77007319 | 159 | static void SystemInit_ExtMemCtl(void); |
mbed_official | 52:a51c77007319 | 160 | #endif /* DATA_IN_ExtSRAM */ |
mbed_official | 52:a51c77007319 | 161 | |
mbed_official | 52:a51c77007319 | 162 | /** |
mbed_official | 52:a51c77007319 | 163 | * @} |
mbed_official | 52:a51c77007319 | 164 | */ |
mbed_official | 52:a51c77007319 | 165 | |
mbed_official | 52:a51c77007319 | 166 | /** @addtogroup STM32F10x_System_Private_Functions |
mbed_official | 52:a51c77007319 | 167 | * @{ |
mbed_official | 52:a51c77007319 | 168 | */ |
mbed_official | 52:a51c77007319 | 169 | |
mbed_official | 52:a51c77007319 | 170 | /** |
mbed_official | 52:a51c77007319 | 171 | * @brief Setup the microcontroller system |
mbed_official | 52:a51c77007319 | 172 | * Initialize the Embedded Flash Interface, the PLL and update the |
mbed_official | 52:a51c77007319 | 173 | * SystemCoreClock variable. |
mbed_official | 52:a51c77007319 | 174 | * @note This function should be used only after reset. |
mbed_official | 52:a51c77007319 | 175 | * @param None |
mbed_official | 52:a51c77007319 | 176 | * @retval None |
mbed_official | 52:a51c77007319 | 177 | */ |
mbed_official | 52:a51c77007319 | 178 | void SystemInit (void) |
mbed_official | 52:a51c77007319 | 179 | { |
mbed_official | 52:a51c77007319 | 180 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ |
mbed_official | 52:a51c77007319 | 181 | /* Set HSION bit */ |
mbed_official | 52:a51c77007319 | 182 | RCC->CR |= (uint32_t)0x00000001; |
mbed_official | 52:a51c77007319 | 183 | |
mbed_official | 52:a51c77007319 | 184 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
mbed_official | 52:a51c77007319 | 185 | #ifndef STM32F10X_CL |
mbed_official | 52:a51c77007319 | 186 | RCC->CFGR &= (uint32_t)0xF8FF0000; |
mbed_official | 52:a51c77007319 | 187 | #else |
mbed_official | 52:a51c77007319 | 188 | RCC->CFGR &= (uint32_t)0xF0FF0000; |
mbed_official | 52:a51c77007319 | 189 | #endif /* STM32F10X_CL */ |
mbed_official | 52:a51c77007319 | 190 | |
mbed_official | 52:a51c77007319 | 191 | /* Reset HSEON, CSSON and PLLON bits */ |
mbed_official | 52:a51c77007319 | 192 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
mbed_official | 52:a51c77007319 | 193 | |
mbed_official | 52:a51c77007319 | 194 | /* Reset HSEBYP bit */ |
mbed_official | 52:a51c77007319 | 195 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 52:a51c77007319 | 196 | |
mbed_official | 52:a51c77007319 | 197 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
mbed_official | 52:a51c77007319 | 198 | RCC->CFGR &= (uint32_t)0xFF80FFFF; |
mbed_official | 52:a51c77007319 | 199 | |
mbed_official | 52:a51c77007319 | 200 | #ifdef STM32F10X_CL |
mbed_official | 52:a51c77007319 | 201 | /* Reset PLL2ON and PLL3ON bits */ |
mbed_official | 52:a51c77007319 | 202 | RCC->CR &= (uint32_t)0xEBFFFFFF; |
mbed_official | 52:a51c77007319 | 203 | |
mbed_official | 52:a51c77007319 | 204 | /* Disable all interrupts and clear pending bits */ |
mbed_official | 52:a51c77007319 | 205 | RCC->CIR = 0x00FF0000; |
mbed_official | 52:a51c77007319 | 206 | |
mbed_official | 52:a51c77007319 | 207 | /* Reset CFGR2 register */ |
mbed_official | 52:a51c77007319 | 208 | RCC->CFGR2 = 0x00000000; |
mbed_official | 52:a51c77007319 | 209 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) |
mbed_official | 52:a51c77007319 | 210 | /* Disable all interrupts and clear pending bits */ |
mbed_official | 52:a51c77007319 | 211 | RCC->CIR = 0x009F0000; |
mbed_official | 52:a51c77007319 | 212 | |
mbed_official | 52:a51c77007319 | 213 | /* Reset CFGR2 register */ |
mbed_official | 52:a51c77007319 | 214 | RCC->CFGR2 = 0x00000000; |
mbed_official | 52:a51c77007319 | 215 | #else |
mbed_official | 52:a51c77007319 | 216 | /* Disable all interrupts and clear pending bits */ |
mbed_official | 52:a51c77007319 | 217 | RCC->CIR = 0x009F0000; |
mbed_official | 52:a51c77007319 | 218 | #endif /* STM32F10X_CL */ |
mbed_official | 52:a51c77007319 | 219 | |
mbed_official | 52:a51c77007319 | 220 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) |
mbed_official | 52:a51c77007319 | 221 | #ifdef DATA_IN_ExtSRAM |
mbed_official | 52:a51c77007319 | 222 | SystemInit_ExtMemCtl(); |
mbed_official | 52:a51c77007319 | 223 | #endif /* DATA_IN_ExtSRAM */ |
mbed_official | 52:a51c77007319 | 224 | #endif |
mbed_official | 52:a51c77007319 | 225 | |
mbed_official | 52:a51c77007319 | 226 | /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ |
mbed_official | 52:a51c77007319 | 227 | /* Configure the Flash Latency cycles and enable prefetch buffer */ |
mbed_official | 52:a51c77007319 | 228 | SetSysClock(); |
mbed_official | 52:a51c77007319 | 229 | |
mbed_official | 52:a51c77007319 | 230 | #ifdef VECT_TAB_SRAM |
mbed_official | 52:a51c77007319 | 231 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
mbed_official | 52:a51c77007319 | 232 | #else |
mbed_official | 52:a51c77007319 | 233 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
mbed_official | 52:a51c77007319 | 234 | #endif |
mbed_official | 52:a51c77007319 | 235 | } |
mbed_official | 52:a51c77007319 | 236 | |
mbed_official | 52:a51c77007319 | 237 | /** |
mbed_official | 52:a51c77007319 | 238 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
mbed_official | 52:a51c77007319 | 239 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 52:a51c77007319 | 240 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 52:a51c77007319 | 241 | * other parameters. |
mbed_official | 52:a51c77007319 | 242 | * |
mbed_official | 52:a51c77007319 | 243 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 52:a51c77007319 | 244 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 52:a51c77007319 | 245 | * based on this variable will be incorrect. |
mbed_official | 52:a51c77007319 | 246 | * |
mbed_official | 52:a51c77007319 | 247 | * @note - The system frequency computed by this function is not the real |
mbed_official | 52:a51c77007319 | 248 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 52:a51c77007319 | 249 | * constant and the selected clock source: |
mbed_official | 52:a51c77007319 | 250 | * |
mbed_official | 52:a51c77007319 | 251 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 52:a51c77007319 | 252 | * |
mbed_official | 52:a51c77007319 | 253 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 52:a51c77007319 | 254 | * |
mbed_official | 52:a51c77007319 | 255 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 52:a51c77007319 | 256 | * or HSI_VALUE(*) multiplied by the PLL factors. |
mbed_official | 52:a51c77007319 | 257 | * |
mbed_official | 52:a51c77007319 | 258 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value |
mbed_official | 52:a51c77007319 | 259 | * 8 MHz) but the real value may vary depending on the variations |
mbed_official | 52:a51c77007319 | 260 | * in voltage and temperature. |
mbed_official | 52:a51c77007319 | 261 | * |
mbed_official | 52:a51c77007319 | 262 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value |
mbed_official | 52:a51c77007319 | 263 | * 8 MHz or 25 MHz, depedning on the product used), user has to ensure |
mbed_official | 52:a51c77007319 | 264 | * that HSE_VALUE is same as the real frequency of the crystal used. |
mbed_official | 52:a51c77007319 | 265 | * Otherwise, this function may have wrong result. |
mbed_official | 52:a51c77007319 | 266 | * |
mbed_official | 52:a51c77007319 | 267 | * - The result of this function could be not correct when using fractional |
mbed_official | 52:a51c77007319 | 268 | * value for HSE crystal. |
mbed_official | 52:a51c77007319 | 269 | * @param None |
mbed_official | 52:a51c77007319 | 270 | * @retval None |
mbed_official | 52:a51c77007319 | 271 | */ |
mbed_official | 52:a51c77007319 | 272 | void SystemCoreClockUpdate (void) |
mbed_official | 52:a51c77007319 | 273 | { |
mbed_official | 52:a51c77007319 | 274 | uint32_t tmp = 0, pllmull = 0, pllsource = 0; |
mbed_official | 52:a51c77007319 | 275 | |
mbed_official | 52:a51c77007319 | 276 | #ifdef STM32F10X_CL |
mbed_official | 52:a51c77007319 | 277 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; |
mbed_official | 52:a51c77007319 | 278 | #endif /* STM32F10X_CL */ |
mbed_official | 52:a51c77007319 | 279 | |
mbed_official | 52:a51c77007319 | 280 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) |
mbed_official | 52:a51c77007319 | 281 | uint32_t prediv1factor = 0; |
mbed_official | 52:a51c77007319 | 282 | #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ |
mbed_official | 52:a51c77007319 | 283 | |
mbed_official | 52:a51c77007319 | 284 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 52:a51c77007319 | 285 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 52:a51c77007319 | 286 | |
mbed_official | 52:a51c77007319 | 287 | switch (tmp) |
mbed_official | 52:a51c77007319 | 288 | { |
mbed_official | 52:a51c77007319 | 289 | case 0x00: /* HSI used as system clock */ |
mbed_official | 52:a51c77007319 | 290 | SystemCoreClock = HSI_VALUE; |
mbed_official | 52:a51c77007319 | 291 | break; |
mbed_official | 52:a51c77007319 | 292 | case 0x04: /* HSE used as system clock */ |
mbed_official | 52:a51c77007319 | 293 | SystemCoreClock = HSE_VALUE; |
mbed_official | 52:a51c77007319 | 294 | break; |
mbed_official | 52:a51c77007319 | 295 | case 0x08: /* PLL used as system clock */ |
mbed_official | 52:a51c77007319 | 296 | |
mbed_official | 52:a51c77007319 | 297 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 52:a51c77007319 | 298 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
mbed_official | 52:a51c77007319 | 299 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 52:a51c77007319 | 300 | |
mbed_official | 52:a51c77007319 | 301 | #ifndef STM32F10X_CL |
mbed_official | 52:a51c77007319 | 302 | pllmull = ( pllmull >> 18) + 2; |
mbed_official | 52:a51c77007319 | 303 | |
mbed_official | 52:a51c77007319 | 304 | if (pllsource == 0x00) |
mbed_official | 52:a51c77007319 | 305 | { |
mbed_official | 52:a51c77007319 | 306 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
mbed_official | 52:a51c77007319 | 307 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
mbed_official | 52:a51c77007319 | 308 | } |
mbed_official | 52:a51c77007319 | 309 | else |
mbed_official | 52:a51c77007319 | 310 | { |
mbed_official | 52:a51c77007319 | 311 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) |
mbed_official | 52:a51c77007319 | 312 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
mbed_official | 52:a51c77007319 | 313 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
mbed_official | 52:a51c77007319 | 314 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
mbed_official | 52:a51c77007319 | 315 | #else |
mbed_official | 52:a51c77007319 | 316 | /* HSE selected as PLL clock entry */ |
mbed_official | 52:a51c77007319 | 317 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) |
mbed_official | 52:a51c77007319 | 318 | {/* HSE oscillator clock divided by 2 */ |
mbed_official | 52:a51c77007319 | 319 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull; |
mbed_official | 52:a51c77007319 | 320 | } |
mbed_official | 52:a51c77007319 | 321 | else |
mbed_official | 52:a51c77007319 | 322 | { |
mbed_official | 52:a51c77007319 | 323 | SystemCoreClock = HSE_VALUE * pllmull; |
mbed_official | 52:a51c77007319 | 324 | } |
mbed_official | 52:a51c77007319 | 325 | #endif |
mbed_official | 52:a51c77007319 | 326 | } |
mbed_official | 52:a51c77007319 | 327 | #else |
mbed_official | 52:a51c77007319 | 328 | pllmull = pllmull >> 18; |
mbed_official | 52:a51c77007319 | 329 | |
mbed_official | 52:a51c77007319 | 330 | if (pllmull != 0x0D) |
mbed_official | 52:a51c77007319 | 331 | { |
mbed_official | 52:a51c77007319 | 332 | pllmull += 2; |
mbed_official | 52:a51c77007319 | 333 | } |
mbed_official | 52:a51c77007319 | 334 | else |
mbed_official | 52:a51c77007319 | 335 | { /* PLL multiplication factor = PLL input clock * 6.5 */ |
mbed_official | 52:a51c77007319 | 336 | pllmull = 13 / 2; |
mbed_official | 52:a51c77007319 | 337 | } |
mbed_official | 52:a51c77007319 | 338 | |
mbed_official | 52:a51c77007319 | 339 | if (pllsource == 0x00) |
mbed_official | 52:a51c77007319 | 340 | { |
mbed_official | 52:a51c77007319 | 341 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
mbed_official | 52:a51c77007319 | 342 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
mbed_official | 52:a51c77007319 | 343 | } |
mbed_official | 52:a51c77007319 | 344 | else |
mbed_official | 52:a51c77007319 | 345 | {/* PREDIV1 selected as PLL clock entry */ |
mbed_official | 52:a51c77007319 | 346 | |
mbed_official | 52:a51c77007319 | 347 | /* Get PREDIV1 clock source and division factor */ |
mbed_official | 52:a51c77007319 | 348 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; |
mbed_official | 52:a51c77007319 | 349 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
mbed_official | 52:a51c77007319 | 350 | |
mbed_official | 52:a51c77007319 | 351 | if (prediv1source == 0) |
mbed_official | 52:a51c77007319 | 352 | { |
mbed_official | 52:a51c77007319 | 353 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
mbed_official | 52:a51c77007319 | 354 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
mbed_official | 52:a51c77007319 | 355 | } |
mbed_official | 52:a51c77007319 | 356 | else |
mbed_official | 52:a51c77007319 | 357 | {/* PLL2 clock selected as PREDIV1 clock entry */ |
mbed_official | 52:a51c77007319 | 358 | |
mbed_official | 52:a51c77007319 | 359 | /* Get PREDIV2 division factor and PLL2 multiplication factor */ |
mbed_official | 52:a51c77007319 | 360 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; |
mbed_official | 52:a51c77007319 | 361 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; |
mbed_official | 52:a51c77007319 | 362 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; |
mbed_official | 52:a51c77007319 | 363 | } |
mbed_official | 52:a51c77007319 | 364 | } |
mbed_official | 52:a51c77007319 | 365 | #endif /* STM32F10X_CL */ |
mbed_official | 52:a51c77007319 | 366 | break; |
mbed_official | 52:a51c77007319 | 367 | |
mbed_official | 52:a51c77007319 | 368 | default: |
mbed_official | 52:a51c77007319 | 369 | SystemCoreClock = HSI_VALUE; |
mbed_official | 52:a51c77007319 | 370 | break; |
mbed_official | 52:a51c77007319 | 371 | } |
mbed_official | 52:a51c77007319 | 372 | |
mbed_official | 52:a51c77007319 | 373 | /* Compute HCLK clock frequency ----------------*/ |
mbed_official | 52:a51c77007319 | 374 | /* Get HCLK prescaler */ |
mbed_official | 52:a51c77007319 | 375 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 52:a51c77007319 | 376 | /* HCLK clock frequency */ |
mbed_official | 52:a51c77007319 | 377 | SystemCoreClock >>= tmp; |
mbed_official | 52:a51c77007319 | 378 | } |
mbed_official | 52:a51c77007319 | 379 | |
mbed_official | 52:a51c77007319 | 380 | /** |
mbed_official | 52:a51c77007319 | 381 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. |
mbed_official | 52:a51c77007319 | 382 | * @param None |
mbed_official | 52:a51c77007319 | 383 | * @retval None |
mbed_official | 52:a51c77007319 | 384 | */ |
mbed_official | 139:e3413eddde57 | 385 | void SetSysClock(void) |
mbed_official | 52:a51c77007319 | 386 | { |
mbed_official | 139:e3413eddde57 | 387 | /* 1- Try to start with HSE and external clock */ |
mbed_official | 139:e3413eddde57 | 388 | #if USE_PLL_HSE_EXTC != 0 |
mbed_official | 139:e3413eddde57 | 389 | if (SetSysClock_PLL_HSE(1) == 0) |
mbed_official | 52:a51c77007319 | 390 | #endif |
mbed_official | 139:e3413eddde57 | 391 | { |
mbed_official | 139:e3413eddde57 | 392 | /* 2- If fail try to start with HSE and external xtal */ |
mbed_official | 139:e3413eddde57 | 393 | #if USE_PLL_HSE_XTAL != 0 |
mbed_official | 139:e3413eddde57 | 394 | if (SetSysClock_PLL_HSE(0) == 0) |
mbed_official | 139:e3413eddde57 | 395 | #endif |
mbed_official | 139:e3413eddde57 | 396 | { |
mbed_official | 139:e3413eddde57 | 397 | /* 3- If fail start with HSI clock */ |
mbed_official | 139:e3413eddde57 | 398 | if (SetSysClock_PLL_HSI() == 0) |
mbed_official | 139:e3413eddde57 | 399 | { |
mbed_official | 139:e3413eddde57 | 400 | while(1) |
mbed_official | 139:e3413eddde57 | 401 | { |
mbed_official | 139:e3413eddde57 | 402 | // [TODO] Put something here to tell the user that a problem occured... |
mbed_official | 139:e3413eddde57 | 403 | } |
mbed_official | 139:e3413eddde57 | 404 | } |
mbed_official | 139:e3413eddde57 | 405 | } |
mbed_official | 139:e3413eddde57 | 406 | } |
mbed_official | 139:e3413eddde57 | 407 | |
mbed_official | 139:e3413eddde57 | 408 | /* Output SYSCLK on MCO pin(PA8) for debugging purpose */ |
mbed_official | 139:e3413eddde57 | 409 | /* |
mbed_official | 139:e3413eddde57 | 410 | // Enable GPIOA clock |
mbed_official | 139:e3413eddde57 | 411 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); |
mbed_official | 139:e3413eddde57 | 412 | GPIO_InitTypeDef GPIO_InitStructure; |
mbed_official | 139:e3413eddde57 | 413 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; |
mbed_official | 139:e3413eddde57 | 414 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
mbed_official | 139:e3413eddde57 | 415 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
mbed_official | 139:e3413eddde57 | 416 | GPIO_Init(GPIOA, &GPIO_InitStructure); |
mbed_official | 139:e3413eddde57 | 417 | // Select the clock to output |
mbed_official | 139:e3413eddde57 | 418 | RCC_MCOConfig(RCC_MCO_SYSCLK); |
mbed_official | 139:e3413eddde57 | 419 | */ |
mbed_official | 52:a51c77007319 | 420 | } |
mbed_official | 52:a51c77007319 | 421 | |
mbed_official | 52:a51c77007319 | 422 | /** |
mbed_official | 52:a51c77007319 | 423 | * @brief Setup the external memory controller. Called in startup_stm32f10x.s |
mbed_official | 52:a51c77007319 | 424 | * before jump to __main |
mbed_official | 52:a51c77007319 | 425 | * @param None |
mbed_official | 52:a51c77007319 | 426 | * @retval None |
mbed_official | 52:a51c77007319 | 427 | */ |
mbed_official | 52:a51c77007319 | 428 | #ifdef DATA_IN_ExtSRAM |
mbed_official | 52:a51c77007319 | 429 | /** |
mbed_official | 52:a51c77007319 | 430 | * @brief Setup the external memory controller. |
mbed_official | 52:a51c77007319 | 431 | * Called in startup_stm32f10x_xx.s/.c before jump to main. |
mbed_official | 52:a51c77007319 | 432 | * This function configures the external SRAM mounted on STM3210E-EVAL |
mbed_official | 52:a51c77007319 | 433 | * board (STM32 High density devices). This SRAM will be used as program |
mbed_official | 52:a51c77007319 | 434 | * data memory (including heap and stack). |
mbed_official | 52:a51c77007319 | 435 | * @param None |
mbed_official | 52:a51c77007319 | 436 | * @retval None |
mbed_official | 52:a51c77007319 | 437 | */ |
mbed_official | 52:a51c77007319 | 438 | void SystemInit_ExtMemCtl(void) |
mbed_official | 52:a51c77007319 | 439 | { |
mbed_official | 52:a51c77007319 | 440 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is |
mbed_official | 52:a51c77007319 | 441 | required, then adjust the Register Addresses */ |
mbed_official | 52:a51c77007319 | 442 | |
mbed_official | 52:a51c77007319 | 443 | /* Enable FSMC clock */ |
mbed_official | 52:a51c77007319 | 444 | RCC->AHBENR = 0x00000114; |
mbed_official | 52:a51c77007319 | 445 | |
mbed_official | 52:a51c77007319 | 446 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ |
mbed_official | 52:a51c77007319 | 447 | RCC->APB2ENR = 0x000001E0; |
mbed_official | 52:a51c77007319 | 448 | |
mbed_official | 52:a51c77007319 | 449 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ |
mbed_official | 52:a51c77007319 | 450 | /*---------------- SRAM Address lines configuration -------------------------*/ |
mbed_official | 52:a51c77007319 | 451 | /*---------------- NOE and NWE configuration --------------------------------*/ |
mbed_official | 52:a51c77007319 | 452 | /*---------------- NE3 configuration ----------------------------------------*/ |
mbed_official | 52:a51c77007319 | 453 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/ |
mbed_official | 52:a51c77007319 | 454 | |
mbed_official | 52:a51c77007319 | 455 | GPIOD->CRL = 0x44BB44BB; |
mbed_official | 52:a51c77007319 | 456 | GPIOD->CRH = 0xBBBBBBBB; |
mbed_official | 52:a51c77007319 | 457 | |
mbed_official | 52:a51c77007319 | 458 | GPIOE->CRL = 0xB44444BB; |
mbed_official | 52:a51c77007319 | 459 | GPIOE->CRH = 0xBBBBBBBB; |
mbed_official | 52:a51c77007319 | 460 | |
mbed_official | 52:a51c77007319 | 461 | GPIOF->CRL = 0x44BBBBBB; |
mbed_official | 52:a51c77007319 | 462 | GPIOF->CRH = 0xBBBB4444; |
mbed_official | 52:a51c77007319 | 463 | |
mbed_official | 52:a51c77007319 | 464 | GPIOG->CRL = 0x44BBBBBB; |
mbed_official | 52:a51c77007319 | 465 | GPIOG->CRH = 0x44444B44; |
mbed_official | 52:a51c77007319 | 466 | |
mbed_official | 52:a51c77007319 | 467 | /*---------------- FSMC Configuration ---------------------------------------*/ |
mbed_official | 52:a51c77007319 | 468 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ |
mbed_official | 52:a51c77007319 | 469 | |
mbed_official | 52:a51c77007319 | 470 | FSMC_Bank1->BTCR[4] = 0x00001011; |
mbed_official | 52:a51c77007319 | 471 | FSMC_Bank1->BTCR[5] = 0x00000200; |
mbed_official | 52:a51c77007319 | 472 | } |
mbed_official | 52:a51c77007319 | 473 | #endif /* DATA_IN_ExtSRAM */ |
mbed_official | 52:a51c77007319 | 474 | |
mbed_official | 139:e3413eddde57 | 475 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 139:e3413eddde57 | 476 | /******************************************************************************/ |
mbed_official | 139:e3413eddde57 | 477 | /* PLL (clocked by HSE) used as System clock source */ |
mbed_official | 139:e3413eddde57 | 478 | /******************************************************************************/ |
mbed_official | 139:e3413eddde57 | 479 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
mbed_official | 52:a51c77007319 | 480 | { |
mbed_official | 139:e3413eddde57 | 481 | __IO uint32_t StartUpCounter = 0; |
mbed_official | 139:e3413eddde57 | 482 | __IO uint32_t HSEStatus = 0; |
mbed_official | 52:a51c77007319 | 483 | |
mbed_official | 139:e3413eddde57 | 484 | /* Bypass HSE: can be done only if HSE is OFF */ |
mbed_official | 139:e3413eddde57 | 485 | RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */ |
mbed_official | 139:e3413eddde57 | 486 | if (bypass != 0) |
mbed_official | 52:a51c77007319 | 487 | { |
mbed_official | 139:e3413eddde57 | 488 | RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); |
mbed_official | 52:a51c77007319 | 489 | } |
mbed_official | 52:a51c77007319 | 490 | else |
mbed_official | 52:a51c77007319 | 491 | { |
mbed_official | 139:e3413eddde57 | 492 | RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP); |
mbed_official | 139:e3413eddde57 | 493 | } |
mbed_official | 52:a51c77007319 | 494 | |
mbed_official | 139:e3413eddde57 | 495 | /* Enable HSE */ |
mbed_official | 139:e3413eddde57 | 496 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
mbed_official | 52:a51c77007319 | 497 | |
mbed_official | 139:e3413eddde57 | 498 | /* Wait till HSE is ready */ |
mbed_official | 52:a51c77007319 | 499 | do |
mbed_official | 52:a51c77007319 | 500 | { |
mbed_official | 52:a51c77007319 | 501 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
mbed_official | 139:e3413eddde57 | 502 | StartUpCounter++; |
mbed_official | 52:a51c77007319 | 503 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
mbed_official | 52:a51c77007319 | 504 | |
mbed_official | 139:e3413eddde57 | 505 | /* Check if HSE has started correctly */ |
mbed_official | 52:a51c77007319 | 506 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
mbed_official | 52:a51c77007319 | 507 | { |
mbed_official | 52:a51c77007319 | 508 | /* Enable Prefetch Buffer */ |
mbed_official | 52:a51c77007319 | 509 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
mbed_official | 52:a51c77007319 | 510 | |
mbed_official | 139:e3413eddde57 | 511 | /* Flash wait states |
mbed_official | 139:e3413eddde57 | 512 | 0WS for 0 < SYSCLK <= 24 MHz |
mbed_official | 139:e3413eddde57 | 513 | 1WS for 24 < SYSCLK <= 48 MHz |
mbed_official | 139:e3413eddde57 | 514 | 2WS for 48 < SYSCLK <= 72 MHz */ |
mbed_official | 52:a51c77007319 | 515 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
mbed_official | 139:e3413eddde57 | 516 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; |
mbed_official | 52:a51c77007319 | 517 | |
mbed_official | 139:e3413eddde57 | 518 | /* PLL configuration */ |
mbed_official | 139:e3413eddde57 | 519 | /* SYSCLK = 72 MHz (8 MHz * 9) */ |
mbed_official | 52:a51c77007319 | 520 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
mbed_official | 139:e3413eddde57 | 521 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9 |
mbed_official | 139:e3413eddde57 | 522 | | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */ |
mbed_official | 139:e3413eddde57 | 523 | | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */ |
mbed_official | 139:e3413eddde57 | 524 | | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */ |
mbed_official | 139:e3413eddde57 | 525 | /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */ |
mbed_official | 52:a51c77007319 | 526 | |
mbed_official | 52:a51c77007319 | 527 | /* Enable PLL */ |
mbed_official | 52:a51c77007319 | 528 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 52:a51c77007319 | 529 | |
mbed_official | 52:a51c77007319 | 530 | /* Wait till PLL is ready */ |
mbed_official | 52:a51c77007319 | 531 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 52:a51c77007319 | 532 | { |
mbed_official | 52:a51c77007319 | 533 | } |
mbed_official | 52:a51c77007319 | 534 | |
mbed_official | 52:a51c77007319 | 535 | /* Select PLL as system clock source */ |
mbed_official | 52:a51c77007319 | 536 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 139:e3413eddde57 | 537 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 52:a51c77007319 | 538 | |
mbed_official | 52:a51c77007319 | 539 | /* Wait till PLL is used as system clock source */ |
mbed_official | 139:e3413eddde57 | 540 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 52:a51c77007319 | 541 | { |
mbed_official | 52:a51c77007319 | 542 | } |
mbed_official | 139:e3413eddde57 | 543 | |
mbed_official | 139:e3413eddde57 | 544 | return 1; // OK |
mbed_official | 52:a51c77007319 | 545 | } |
mbed_official | 52:a51c77007319 | 546 | else |
mbed_official | 139:e3413eddde57 | 547 | { |
mbed_official | 139:e3413eddde57 | 548 | return 0; // FAIL |
mbed_official | 52:a51c77007319 | 549 | } |
mbed_official | 52:a51c77007319 | 550 | } |
mbed_official | 52:a51c77007319 | 551 | #endif |
mbed_official | 52:a51c77007319 | 552 | |
mbed_official | 139:e3413eddde57 | 553 | /******************************************************************************/ |
mbed_official | 139:e3413eddde57 | 554 | /* PLL (clocked by HSI) used as System clock source */ |
mbed_official | 139:e3413eddde57 | 555 | /******************************************************************************/ |
mbed_official | 139:e3413eddde57 | 556 | uint8_t SetSysClock_PLL_HSI(void) |
mbed_official | 139:e3413eddde57 | 557 | { |
mbed_official | 139:e3413eddde57 | 558 | __IO uint32_t StartUpCounter = 0; |
mbed_official | 139:e3413eddde57 | 559 | |
mbed_official | 139:e3413eddde57 | 560 | /* Enable Prefetch Buffer */ |
mbed_official | 139:e3413eddde57 | 561 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
mbed_official | 139:e3413eddde57 | 562 | |
mbed_official | 139:e3413eddde57 | 563 | /* Flash wait states |
mbed_official | 139:e3413eddde57 | 564 | 0WS for 0 < SYSCLK <= 24 MHz |
mbed_official | 139:e3413eddde57 | 565 | 1WS for 24 < SYSCLK <= 48 MHz |
mbed_official | 139:e3413eddde57 | 566 | 2WS for 48 < SYSCLK <= 72 MHz */ |
mbed_official | 139:e3413eddde57 | 567 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
mbed_official | 139:e3413eddde57 | 568 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; |
mbed_official | 139:e3413eddde57 | 569 | |
mbed_official | 139:e3413eddde57 | 570 | /* PLL configuration |
mbed_official | 139:e3413eddde57 | 571 | PLLCLK = 64 MHz (HSI/2 * 16) */ |
mbed_official | 139:e3413eddde57 | 572 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
mbed_official | 139:e3413eddde57 | 573 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL16 |
mbed_official | 139:e3413eddde57 | 574 | | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */ |
mbed_official | 139:e3413eddde57 | 575 | | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */ |
mbed_official | 139:e3413eddde57 | 576 | | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */ |
mbed_official | 139:e3413eddde57 | 577 | /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */ |
mbed_official | 139:e3413eddde57 | 578 | |
mbed_official | 139:e3413eddde57 | 579 | /* Enable PLL */ |
mbed_official | 139:e3413eddde57 | 580 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 139:e3413eddde57 | 581 | |
mbed_official | 139:e3413eddde57 | 582 | /* Wait till PLL is ready */ |
mbed_official | 139:e3413eddde57 | 583 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 139:e3413eddde57 | 584 | { |
mbed_official | 139:e3413eddde57 | 585 | } |
mbed_official | 139:e3413eddde57 | 586 | |
mbed_official | 139:e3413eddde57 | 587 | /* Select PLL as system clock source */ |
mbed_official | 139:e3413eddde57 | 588 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 139:e3413eddde57 | 589 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 139:e3413eddde57 | 590 | |
mbed_official | 139:e3413eddde57 | 591 | /* Wait till PLL is used as system clock source */ |
mbed_official | 139:e3413eddde57 | 592 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 139:e3413eddde57 | 593 | { |
mbed_official | 139:e3413eddde57 | 594 | } |
mbed_official | 139:e3413eddde57 | 595 | |
mbed_official | 139:e3413eddde57 | 596 | return 1; // OK |
mbed_official | 139:e3413eddde57 | 597 | } |
mbed_official | 139:e3413eddde57 | 598 | |
mbed_official | 52:a51c77007319 | 599 | /** |
mbed_official | 52:a51c77007319 | 600 | * @} |
mbed_official | 52:a51c77007319 | 601 | */ |
mbed_official | 52:a51c77007319 | 602 | |
mbed_official | 52:a51c77007319 | 603 | /** |
mbed_official | 52:a51c77007319 | 604 | * @} |
mbed_official | 52:a51c77007319 | 605 | */ |
mbed_official | 139:e3413eddde57 | 606 | |
mbed_official | 52:a51c77007319 | 607 | /** |
mbed_official | 52:a51c77007319 | 608 | * @} |
mbed_official | 139:e3413eddde57 | 609 | */ |
mbed_official | 139:e3413eddde57 | 610 | |
mbed_official | 84:f54042cbc282 | 611 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |