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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:: mbed_official
Date:: Wed Feb 26 09:45:12 2014 +0000
Revision:: 106:ced8cbb51063
Parent:: 87:085cde657901
Child:: 226:b062af740e40

Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_ll_fsmc.h
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	106:ced8cbb51063	5	* @version V1.0.0
mbed_official	106:ced8cbb51063	6	* @date 18-February-2014
mbed_official	87:085cde657901	7	* @brief Header file of FSMC HAL module.
mbed_official	87:085cde657901	8	******************************************************************************
mbed_official	87:085cde657901	9	* @attention
mbed_official	87:085cde657901	10	*
mbed_official	87:085cde657901	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	12	*
mbed_official	87:085cde657901	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	14	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	16	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	19	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	21	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	22	* without specific prior written permission.
mbed_official	87:085cde657901	23	*
mbed_official	87:085cde657901	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	34	*
mbed_official	87:085cde657901	35	******************************************************************************
mbed_official	87:085cde657901	36	*/
mbed_official	87:085cde657901	37
mbed_official	87:085cde657901	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	87:085cde657901	39	#ifndef __STM32F4xx_LL_FSMC_H
mbed_official	87:085cde657901	40	#define __STM32F4xx_LL_FSMC_H
mbed_official	87:085cde657901	41
mbed_official	87:085cde657901	42	#ifdef __cplusplus
mbed_official	87:085cde657901	43	extern "C" {
mbed_official	87:085cde657901	44	#endif
mbed_official	87:085cde657901	45
mbed_official	87:085cde657901	46	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	49	#include "stm32f4xx_hal_def.h"
mbed_official	87:085cde657901	50
mbed_official	87:085cde657901	51	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	52	* @{
mbed_official	87:085cde657901	53	*/
mbed_official	87:085cde657901	54
mbed_official	87:085cde657901	55	/** @addtogroup FSMC
mbed_official	87:085cde657901	56	* @{
mbed_official	87:085cde657901	57	*/
mbed_official	87:085cde657901	58
mbed_official	87:085cde657901	59	/* Exported typedef ----------------------------------------------------------*/
mbed_official	87:085cde657901	60	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
mbed_official	87:085cde657901	61	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
mbed_official	87:085cde657901	62	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
mbed_official	87:085cde657901	63	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
mbed_official	87:085cde657901	64
mbed_official	87:085cde657901	65	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
mbed_official	87:085cde657901	66	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
mbed_official	87:085cde657901	67	#define FSMC_NAND_DEVICE FSMC_Bank2_3
mbed_official	87:085cde657901	68	#define FSMC_PCCARD_DEVICE FSMC_Bank4
mbed_official	87:085cde657901	69
mbed_official	87:085cde657901	70	/**
mbed_official	87:085cde657901	71	* @brief FSMC_NORSRAM Configuration Structure definition
mbed_official	87:085cde657901	72	*/
mbed_official	87:085cde657901	73	typedef struct
mbed_official	87:085cde657901	74	{
mbed_official	87:085cde657901	75	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	87:085cde657901	76	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
mbed_official	87:085cde657901	77
mbed_official	87:085cde657901	78	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	87:085cde657901	79	multiplexed on the data bus or not.
mbed_official	87:085cde657901	80	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
mbed_official	87:085cde657901	81
mbed_official	87:085cde657901	82	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	87:085cde657901	83	the corresponding memory device.
mbed_official	87:085cde657901	84	This parameter can be a value of @ref FSMC_Memory_Type */
mbed_official	87:085cde657901	85
mbed_official	87:085cde657901	86	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	87:085cde657901	87	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
mbed_official	87:085cde657901	88
mbed_official	87:085cde657901	89	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	87:085cde657901	90	valid only with synchronous burst Flash memories.
mbed_official	87:085cde657901	91	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
mbed_official	87:085cde657901	92
mbed_official	87:085cde657901	93	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	87:085cde657901	94	the Flash memory in burst mode.
mbed_official	87:085cde657901	95	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
mbed_official	87:085cde657901	96
mbed_official	87:085cde657901	97	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	87:085cde657901	98	memory, valid only when accessing Flash memories in burst mode.
mbed_official	87:085cde657901	99	This parameter can be a value of @ref FSMC_Wrap_Mode */
mbed_official	87:085cde657901	100
mbed_official	87:085cde657901	101	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	87:085cde657901	102	clock cycle before the wait state or during the wait state,
mbed_official	87:085cde657901	103	valid only when accessing memories in burst mode.
mbed_official	87:085cde657901	104	This parameter can be a value of @ref FSMC_Wait_Timing */
mbed_official	87:085cde657901	105
mbed_official	87:085cde657901	106	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
mbed_official	87:085cde657901	107	This parameter can be a value of @ref FSMC_Write_Operation */
mbed_official	87:085cde657901	108
mbed_official	87:085cde657901	109	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	87:085cde657901	110	signal, valid for Flash memory access in burst mode.
mbed_official	87:085cde657901	111	This parameter can be a value of @ref FSMC_Wait_Signal */
mbed_official	87:085cde657901	112
mbed_official	87:085cde657901	113	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	87:085cde657901	114	This parameter can be a value of @ref FSMC_Extended_Mode */
mbed_official	87:085cde657901	115
mbed_official	87:085cde657901	116	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	87:085cde657901	117	valid only with asynchronous Flash memories.
mbed_official	87:085cde657901	118	This parameter can be a value of @ref FSMC_AsynchronousWait */
mbed_official	87:085cde657901	119
mbed_official	87:085cde657901	120	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	87:085cde657901	121	This parameter can be a value of @ref FSMC_Write_Burst */
mbed_official	87:085cde657901	122
mbed_official	87:085cde657901	123	}FSMC_NORSRAM_InitTypeDef;
mbed_official	87:085cde657901	124
mbed_official	87:085cde657901	125
mbed_official	87:085cde657901	126	/**
mbed_official	87:085cde657901	127	* @brief FSMC_NORSRAM Timing parameters structure definition
mbed_official	87:085cde657901	128	*/
mbed_official	87:085cde657901	129	typedef struct
mbed_official	87:085cde657901	130	{
mbed_official	87:085cde657901	131	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	132	the duration of the address setup time.
mbed_official	87:085cde657901	133	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	87:085cde657901	134	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	87:085cde657901	135
mbed_official	87:085cde657901	136	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	137	the duration of the address hold time.
mbed_official	87:085cde657901	138	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	87:085cde657901	139	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	87:085cde657901	140
mbed_official	87:085cde657901	141	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	142	the duration of the data setup time.
mbed_official	87:085cde657901	143	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	87:085cde657901	144	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	87:085cde657901	145	NOR Flash memories. */
mbed_official	87:085cde657901	146
mbed_official	87:085cde657901	147	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	148	the duration of the bus turnaround.
mbed_official	87:085cde657901	149	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	87:085cde657901	150	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	87:085cde657901	151
mbed_official	87:085cde657901	152	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	87:085cde657901	153	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	87:085cde657901	154	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	87:085cde657901	155	accesses. */
mbed_official	87:085cde657901	156
mbed_official	87:085cde657901	157	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	87:085cde657901	158	to the memory before getting the first data.
mbed_official	87:085cde657901	159	The parameter value depends on the memory type as shown below:
mbed_official	87:085cde657901	160	- It must be set to 0 in case of a CRAM
mbed_official	87:085cde657901	161	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	87:085cde657901	162	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	87:085cde657901	163	with synchronous burst mode enable */
mbed_official	87:085cde657901	164
mbed_official	87:085cde657901	165	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	87:085cde657901	166	This parameter can be a value of @ref FSMC_Access_Mode */
mbed_official	87:085cde657901	167
mbed_official	87:085cde657901	168	}FSMC_NORSRAM_TimingTypeDef;
mbed_official	87:085cde657901	169
mbed_official	87:085cde657901	170	/**
mbed_official	87:085cde657901	171	* @brief FSMC_NAND Configuration Structure definition
mbed_official	87:085cde657901	172	*/
mbed_official	87:085cde657901	173	typedef struct
mbed_official	87:085cde657901	174	{
mbed_official	87:085cde657901	175	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	87:085cde657901	176	This parameter can be a value of @ref FSMC_NAND_Bank */
mbed_official	87:085cde657901	177
mbed_official	87:085cde657901	178	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	87:085cde657901	179	This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official	87:085cde657901	180
mbed_official	87:085cde657901	181	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	87:085cde657901	182	This parameter can be any value of @ref FSMC_NAND_Data_Width */
mbed_official	87:085cde657901	183
mbed_official	87:085cde657901	184	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	87:085cde657901	185	This parameter can be any value of @ref FSMC_ECC */
mbed_official	87:085cde657901	186
mbed_official	87:085cde657901	187	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	87:085cde657901	188	This parameter can be any value of @ref FSMC_ECC_Page_Size */
mbed_official	87:085cde657901	189
mbed_official	87:085cde657901	190	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	191	delay between CLE low and RE low.
mbed_official	87:085cde657901	192	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	193
mbed_official	87:085cde657901	194	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	195	delay between ALE low and RE low.
mbed_official	87:085cde657901	196	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	197
mbed_official	87:085cde657901	198	}FSMC_NAND_InitTypeDef;
mbed_official	87:085cde657901	199
mbed_official	87:085cde657901	200	/**
mbed_official	87:085cde657901	201	* @brief FSMC_NAND_PCCARD Timing parameters structure definition
mbed_official	87:085cde657901	202	*/
mbed_official	87:085cde657901	203	typedef struct
mbed_official	87:085cde657901	204	{
mbed_official	87:085cde657901	205	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	87:085cde657901	206	the command assertion for NAND-Flash read or write access
mbed_official	87:085cde657901	207	to common/Attribute or I/O memory space (depending on
mbed_official	87:085cde657901	208	the memory space timing to be configured).
mbed_official	87:085cde657901	209	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	210
mbed_official	87:085cde657901	211	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	87:085cde657901	212	command for NAND-Flash read or write access to
mbed_official	87:085cde657901	213	common/Attribute or I/O memory space (depending on the
mbed_official	87:085cde657901	214	memory space timing to be configured).
mbed_official	87:085cde657901	215	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	216
mbed_official	87:085cde657901	217	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	87:085cde657901	218	(and data for write access) after the command de-assertion
mbed_official	87:085cde657901	219	for NAND-Flash read or write access to common/Attribute
mbed_official	87:085cde657901	220	or I/O memory space (depending on the memory space timing
mbed_official	87:085cde657901	221	to be configured).
mbed_official	87:085cde657901	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	223
mbed_official	87:085cde657901	224	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	87:085cde657901	225	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	87:085cde657901	226	write access to common/Attribute or I/O memory space (depending
mbed_official	87:085cde657901	227	on the memory space timing to be configured).
mbed_official	87:085cde657901	228	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	229
mbed_official	87:085cde657901	230	}FSMC_NAND_PCC_TimingTypeDef;
mbed_official	87:085cde657901	231
mbed_official	87:085cde657901	232	/**
mbed_official	87:085cde657901	233	* @brief FSMC_NAND Configuration Structure definition
mbed_official	87:085cde657901	234	*/
mbed_official	87:085cde657901	235	typedef struct
mbed_official	87:085cde657901	236	{
mbed_official	87:085cde657901	237	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official	87:085cde657901	238	This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official	87:085cde657901	239
mbed_official	87:085cde657901	240	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	241	delay between CLE low and RE low.
mbed_official	87:085cde657901	242	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	243
mbed_official	87:085cde657901	244	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	245	delay between ALE low and RE low.
mbed_official	87:085cde657901	246	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	247
mbed_official	87:085cde657901	248	}FSMC_PCCARD_InitTypeDef;
mbed_official	87:085cde657901	249
mbed_official	87:085cde657901	250	/* Exported constants --------------------------------------------------------*/
mbed_official	87:085cde657901	251
mbed_official	87:085cde657901	252	/** @defgroup FSMC_NOR_SRAM_Controller
mbed_official	87:085cde657901	253	* @{
mbed_official	87:085cde657901	254	*/
mbed_official	87:085cde657901	255
mbed_official	87:085cde657901	256	/** @defgroup FSMC_NORSRAM_Bank
mbed_official	87:085cde657901	257	* @{
mbed_official	87:085cde657901	258	*/
mbed_official	87:085cde657901	259	#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	260	#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	87:085cde657901	261	#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	87:085cde657901	262	#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	87:085cde657901	263
mbed_official	87:085cde657901	264	#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) \|\| \
mbed_official	87:085cde657901	265	((BANK) == FSMC_NORSRAM_BANK2) \|\| \
mbed_official	87:085cde657901	266	((BANK) == FSMC_NORSRAM_BANK3) \|\| \
mbed_official	87:085cde657901	267	((BANK) == FSMC_NORSRAM_BANK4))
mbed_official	87:085cde657901	268	/**
mbed_official	87:085cde657901	269	* @}
mbed_official	87:085cde657901	270	*/
mbed_official	87:085cde657901	271
mbed_official	87:085cde657901	272	/** @defgroup FSMC_Data_Address_Bus_Multiplexing
mbed_official	87:085cde657901	273	* @{
mbed_official	87:085cde657901	274	*/
mbed_official	87:085cde657901	275
mbed_official	87:085cde657901	276	#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	277	#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	87:085cde657901	278
mbed_official	87:085cde657901	279	#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	87:085cde657901	280	((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	87:085cde657901	281	/**
mbed_official	87:085cde657901	282	* @}
mbed_official	87:085cde657901	283	*/
mbed_official	87:085cde657901	284
mbed_official	87:085cde657901	285	/** @defgroup FSMC_Memory_Type
mbed_official	87:085cde657901	286	* @{
mbed_official	87:085cde657901	287	*/
mbed_official	87:085cde657901	288
mbed_official	87:085cde657901	289	#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	87:085cde657901	290	#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	87:085cde657901	291	#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	87:085cde657901	292
mbed_official	87:085cde657901	293
mbed_official	87:085cde657901	294	#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	87:085cde657901	295	((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	87:085cde657901	296	((MEMORY) == FSMC_MEMORY_TYPE_NOR))
mbed_official	87:085cde657901	297	/**
mbed_official	87:085cde657901	298	* @}
mbed_official	87:085cde657901	299	*/
mbed_official	87:085cde657901	300
mbed_official	87:085cde657901	301	/** @defgroup FSMC_NORSRAM_Data_Width
mbed_official	87:085cde657901	302	* @{
mbed_official	87:085cde657901	303	*/
mbed_official	87:085cde657901	304
mbed_official	87:085cde657901	305	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	306	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	307	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	87:085cde657901	308
mbed_official	87:085cde657901	309	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	87:085cde657901	310	((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	87:085cde657901	311	((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	87:085cde657901	312	/**
mbed_official	87:085cde657901	313	* @}
mbed_official	87:085cde657901	314	*/
mbed_official	87:085cde657901	315
mbed_official	87:085cde657901	316	/** @defgroup FSMC_NORSRAM_Flash_Access
mbed_official	87:085cde657901	317	* @{
mbed_official	87:085cde657901	318	*/
mbed_official	87:085cde657901	319	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	87:085cde657901	320	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	321	/**
mbed_official	87:085cde657901	322	* @}
mbed_official	87:085cde657901	323	*/
mbed_official	87:085cde657901	324
mbed_official	87:085cde657901	325	/** @defgroup FSMC_Burst_Access_Mode
mbed_official	87:085cde657901	326	* @{
mbed_official	87:085cde657901	327	*/
mbed_official	87:085cde657901	328
mbed_official	87:085cde657901	329	#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	330	#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	87:085cde657901	331
mbed_official	87:085cde657901	332	#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	87:085cde657901	333	((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	87:085cde657901	334	/**
mbed_official	87:085cde657901	335	* @}
mbed_official	87:085cde657901	336	*/
mbed_official	87:085cde657901	337
mbed_official	87:085cde657901	338
mbed_official	87:085cde657901	339	/** @defgroup FSMC_Wait_Signal_Polarity
mbed_official	87:085cde657901	340	* @{
mbed_official	87:085cde657901	341	*/
mbed_official	87:085cde657901	342	#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	87:085cde657901	343	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	87:085cde657901	344
mbed_official	87:085cde657901	345	#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	87:085cde657901	346	((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	87:085cde657901	347	/**
mbed_official	87:085cde657901	348	* @}
mbed_official	87:085cde657901	349	*/
mbed_official	87:085cde657901	350
mbed_official	87:085cde657901	351	/** @defgroup FSMC_Wrap_Mode
mbed_official	87:085cde657901	352	* @{
mbed_official	87:085cde657901	353	*/
mbed_official	87:085cde657901	354	#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	355	#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official	87:085cde657901	356
mbed_official	87:085cde657901	357	#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	87:085cde657901	358	((MODE) == FSMC_WRAP_MODE_ENABLE))
mbed_official	87:085cde657901	359	/**
mbed_official	87:085cde657901	360	* @}
mbed_official	87:085cde657901	361	*/
mbed_official	87:085cde657901	362
mbed_official	87:085cde657901	363	/** @defgroup FSMC_Wait_Timing
mbed_official	87:085cde657901	364	* @{
mbed_official	87:085cde657901	365	*/
mbed_official	87:085cde657901	366	#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	87:085cde657901	367	#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	87:085cde657901	368
mbed_official	87:085cde657901	369	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	87:085cde657901	370	((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
mbed_official	87:085cde657901	371	/**
mbed_official	87:085cde657901	372	* @}
mbed_official	87:085cde657901	373	*/
mbed_official	87:085cde657901	374
mbed_official	87:085cde657901	375	/** @defgroup FSMC_Write_Operation
mbed_official	87:085cde657901	376	* @{
mbed_official	87:085cde657901	377	*/
mbed_official	87:085cde657901	378	#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	379	#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	87:085cde657901	380
mbed_official	87:085cde657901	381	#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	87:085cde657901	382	((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
mbed_official	87:085cde657901	383	/**
mbed_official	87:085cde657901	384	* @}
mbed_official	87:085cde657901	385	*/
mbed_official	87:085cde657901	386
mbed_official	87:085cde657901	387	/** @defgroup FSMC_Wait_Signal
mbed_official	87:085cde657901	388	* @{
mbed_official	87:085cde657901	389	*/
mbed_official	87:085cde657901	390	#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	391	#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	87:085cde657901	392
mbed_official	87:085cde657901	393	#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	87:085cde657901	394	((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
mbed_official	87:085cde657901	395
mbed_official	87:085cde657901	396	/**
mbed_official	87:085cde657901	397	* @}
mbed_official	87:085cde657901	398	*/
mbed_official	87:085cde657901	399
mbed_official	87:085cde657901	400	/** @defgroup FSMC_Extended_Mode
mbed_official	87:085cde657901	401	* @{
mbed_official	87:085cde657901	402	*/
mbed_official	87:085cde657901	403	#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	404	#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	87:085cde657901	405
mbed_official	87:085cde657901	406	#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	87:085cde657901	407	((MODE) == FSMC_EXTENDED_MODE_ENABLE))
mbed_official	87:085cde657901	408	/**
mbed_official	87:085cde657901	409	* @}
mbed_official	87:085cde657901	410	*/
mbed_official	87:085cde657901	411
mbed_official	87:085cde657901	412	/** @defgroup FSMC_AsynchronousWait
mbed_official	87:085cde657901	413	* @{
mbed_official	87:085cde657901	414	*/
mbed_official	87:085cde657901	415	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	416	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	87:085cde657901	417
mbed_official	87:085cde657901	418	#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	87:085cde657901	419	((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	87:085cde657901	420
mbed_official	87:085cde657901	421	/**
mbed_official	87:085cde657901	422	* @}
mbed_official	87:085cde657901	423	*/
mbed_official	87:085cde657901	424
mbed_official	87:085cde657901	425	/** @defgroup FSMC_Write_Burst
mbed_official	87:085cde657901	426	* @{
mbed_official	87:085cde657901	427	*/
mbed_official	87:085cde657901	428
mbed_official	87:085cde657901	429	#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	430	#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	87:085cde657901	431
mbed_official	87:085cde657901	432	#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	87:085cde657901	433	((BURST) == FSMC_WRITE_BURST_ENABLE))
mbed_official	87:085cde657901	434
mbed_official	87:085cde657901	435	/**
mbed_official	87:085cde657901	436	* @}
mbed_official	87:085cde657901	437	*/
mbed_official	87:085cde657901	438
mbed_official	87:085cde657901	439	/** @defgroup FSMC_Continous_Clock
mbed_official	87:085cde657901	440	* @{
mbed_official	87:085cde657901	441	*/
mbed_official	87:085cde657901	442
mbed_official	87:085cde657901	443	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	87:085cde657901	444	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	87:085cde657901	445
mbed_official	87:085cde657901	446	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	87:085cde657901	447	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	87:085cde657901	448
mbed_official	87:085cde657901	449	/**
mbed_official	87:085cde657901	450	* @}
mbed_official	87:085cde657901	451	*/
mbed_official	87:085cde657901	452
mbed_official	87:085cde657901	453	/** @defgroup FSMC_Address_Setup_Time
mbed_official	87:085cde657901	454	* @{
mbed_official	87:085cde657901	455	*/
mbed_official	87:085cde657901	456	#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
mbed_official	87:085cde657901	457	/**
mbed_official	87:085cde657901	458	* @}
mbed_official	87:085cde657901	459	*/
mbed_official	87:085cde657901	460
mbed_official	87:085cde657901	461	/** @defgroup FSMC_Address_Hold_Time
mbed_official	87:085cde657901	462	* @{
mbed_official	87:085cde657901	463	*/
mbed_official	87:085cde657901	464	#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
mbed_official	87:085cde657901	465	/**
mbed_official	87:085cde657901	466	* @}
mbed_official	87:085cde657901	467	*/
mbed_official	87:085cde657901	468
mbed_official	87:085cde657901	469	/** @defgroup FSMC_Data_Setup_Time
mbed_official	87:085cde657901	470	* @{
mbed_official	87:085cde657901	471	*/
mbed_official	87:085cde657901	472	#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
mbed_official	87:085cde657901	473	/**
mbed_official	87:085cde657901	474	* @}
mbed_official	87:085cde657901	475	*/
mbed_official	87:085cde657901	476
mbed_official	87:085cde657901	477	/** @defgroup FSMC_Bus_Turn_around_Duration
mbed_official	87:085cde657901	478	* @{
mbed_official	87:085cde657901	479	*/
mbed_official	87:085cde657901	480	#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
mbed_official	87:085cde657901	481	/**
mbed_official	87:085cde657901	482	* @}
mbed_official	87:085cde657901	483	*/
mbed_official	87:085cde657901	484
mbed_official	87:085cde657901	485	/** @defgroup FSMC_CLK_Division
mbed_official	87:085cde657901	486	* @{
mbed_official	87:085cde657901	487	*/
mbed_official	87:085cde657901	488	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	87:085cde657901	489	/**
mbed_official	87:085cde657901	490	* @}
mbed_official	87:085cde657901	491	*/
mbed_official	87:085cde657901	492
mbed_official	87:085cde657901	493	/** @defgroup FSMC_Data_Latency
mbed_official	87:085cde657901	494	* @{
mbed_official	87:085cde657901	495	*/
mbed_official	87:085cde657901	496	#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
mbed_official	87:085cde657901	497	/**
mbed_official	87:085cde657901	498	* @}
mbed_official	87:085cde657901	499	*/
mbed_official	87:085cde657901	500
mbed_official	87:085cde657901	501	/** @defgroup FSMC_Access_Mode
mbed_official	87:085cde657901	502	* @{
mbed_official	87:085cde657901	503	*/
mbed_official	87:085cde657901	504	#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	87:085cde657901	505	#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	87:085cde657901	506	#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	87:085cde657901	507	#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	87:085cde657901	508
mbed_official	87:085cde657901	509	#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) \|\| \
mbed_official	87:085cde657901	510	((MODE) == FSMC_ACCESS_MODE_B) \|\| \
mbed_official	87:085cde657901	511	((MODE) == FSMC_ACCESS_MODE_C) \|\| \
mbed_official	87:085cde657901	512	((MODE) == FSMC_ACCESS_MODE_D))
mbed_official	87:085cde657901	513	/**
mbed_official	87:085cde657901	514	* @}
mbed_official	87:085cde657901	515	*/
mbed_official	87:085cde657901	516
mbed_official	87:085cde657901	517	/**
mbed_official	87:085cde657901	518	* @}
mbed_official	87:085cde657901	519	*/
mbed_official	87:085cde657901	520
mbed_official	87:085cde657901	521	/** @defgroup FSMC_NAND_Controller
mbed_official	87:085cde657901	522	* @{
mbed_official	87:085cde657901	523	*/
mbed_official	87:085cde657901	524
mbed_official	87:085cde657901	525	/** @defgroup FSMC_NAND_Bank
mbed_official	87:085cde657901	526	* @{
mbed_official	87:085cde657901	527	*/
mbed_official	87:085cde657901	528	#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	529	#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	87:085cde657901	530
mbed_official	87:085cde657901	531	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
mbed_official	87:085cde657901	532	((BANK) == FSMC_NAND_BANK3))
mbed_official	87:085cde657901	533
mbed_official	87:085cde657901	534	/**
mbed_official	87:085cde657901	535	* @}
mbed_official	87:085cde657901	536	*/
mbed_official	87:085cde657901	537
mbed_official	87:085cde657901	538	/** @defgroup FSMC_Wait_feature
mbed_official	87:085cde657901	539	* @{
mbed_official	87:085cde657901	540	*/
mbed_official	87:085cde657901	541	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	542	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	87:085cde657901	543
mbed_official	87:085cde657901	544	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	87:085cde657901	545	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official	87:085cde657901	546	/**
mbed_official	87:085cde657901	547	* @}
mbed_official	87:085cde657901	548	*/
mbed_official	87:085cde657901	549
mbed_official	87:085cde657901	550	/** @defgroup FSMC_PCR_Memory_Type
mbed_official	87:085cde657901	551	* @{
mbed_official	87:085cde657901	552	*/
mbed_official	87:085cde657901	553	#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official	87:085cde657901	554	#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	87:085cde657901	555	/**
mbed_official	87:085cde657901	556	* @}
mbed_official	87:085cde657901	557	*/
mbed_official	87:085cde657901	558
mbed_official	87:085cde657901	559	/** @defgroup FSMC_NAND_Data_Width
mbed_official	87:085cde657901	560	* @{
mbed_official	87:085cde657901	561	*/
mbed_official	87:085cde657901	562	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	563	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	564
mbed_official	87:085cde657901	565	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
mbed_official	87:085cde657901	566	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official	87:085cde657901	567	/**
mbed_official	87:085cde657901	568	* @}
mbed_official	87:085cde657901	569	*/
mbed_official	87:085cde657901	570
mbed_official	87:085cde657901	571	/** @defgroup FSMC_ECC
mbed_official	87:085cde657901	572	* @{
mbed_official	87:085cde657901	573	*/
mbed_official	87:085cde657901	574	#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	575	#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	87:085cde657901	576
mbed_official	87:085cde657901	577	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
mbed_official	87:085cde657901	578	((STATE) == FSMC_NAND_ECC_ENABLE))
mbed_official	87:085cde657901	579	/**
mbed_official	87:085cde657901	580	* @}
mbed_official	87:085cde657901	581	*/
mbed_official	87:085cde657901	582
mbed_official	87:085cde657901	583	/** @defgroup FSMC_ECC_Page_Size
mbed_official	87:085cde657901	584	* @{
mbed_official	87:085cde657901	585	*/
mbed_official	87:085cde657901	586	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	587	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	87:085cde657901	588	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	87:085cde657901	589	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	87:085cde657901	590	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	87:085cde657901	591	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	87:085cde657901	592
mbed_official	87:085cde657901	593	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	87:085cde657901	594	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	87:085cde657901	595	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	87:085cde657901	596	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	87:085cde657901	597	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	87:085cde657901	598	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	87:085cde657901	599	/**
mbed_official	87:085cde657901	600	* @}
mbed_official	87:085cde657901	601	*/
mbed_official	87:085cde657901	602
mbed_official	87:085cde657901	603	/** @defgroup FSMC_TCLR_Setup_Time
mbed_official	87:085cde657901	604	* @{
mbed_official	87:085cde657901	605	*/
mbed_official	87:085cde657901	606	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	607	/**
mbed_official	87:085cde657901	608	* @}
mbed_official	87:085cde657901	609	*/
mbed_official	87:085cde657901	610
mbed_official	87:085cde657901	611	/** @defgroup FSMC_TAR_Setup_Time
mbed_official	87:085cde657901	612	* @{
mbed_official	87:085cde657901	613	*/
mbed_official	87:085cde657901	614	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	615	/**
mbed_official	87:085cde657901	616	* @}
mbed_official	87:085cde657901	617	*/
mbed_official	87:085cde657901	618
mbed_official	87:085cde657901	619	/** @defgroup FSMC_Setup_Time
mbed_official	87:085cde657901	620	* @{
mbed_official	87:085cde657901	621	*/
mbed_official	87:085cde657901	622	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	623	/**
mbed_official	87:085cde657901	624	* @}
mbed_official	87:085cde657901	625	*/
mbed_official	87:085cde657901	626
mbed_official	87:085cde657901	627	/** @defgroup FSMC_Wait_Setup_Time
mbed_official	87:085cde657901	628	* @{
mbed_official	87:085cde657901	629	*/
mbed_official	87:085cde657901	630	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	631	/**
mbed_official	87:085cde657901	632	* @}
mbed_official	87:085cde657901	633	*/
mbed_official	87:085cde657901	634
mbed_official	87:085cde657901	635	/** @defgroup FSMC_Hold_Setup_Time
mbed_official	87:085cde657901	636	* @{
mbed_official	87:085cde657901	637	*/
mbed_official	87:085cde657901	638	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	639	/**
mbed_official	87:085cde657901	640	* @}
mbed_official	87:085cde657901	641	*/
mbed_official	87:085cde657901	642
mbed_official	87:085cde657901	643	/** @defgroup FSMC_HiZ_Setup_Time
mbed_official	87:085cde657901	644	* @{
mbed_official	87:085cde657901	645	*/
mbed_official	87:085cde657901	646	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	647	/**
mbed_official	87:085cde657901	648	* @}
mbed_official	87:085cde657901	649	*/
mbed_official	87:085cde657901	650
mbed_official	87:085cde657901	651	/**
mbed_official	87:085cde657901	652	* @}
mbed_official	87:085cde657901	653	*/
mbed_official	87:085cde657901	654
mbed_official	87:085cde657901	655
mbed_official	87:085cde657901	656	/** @defgroup FSMC_NORSRAM_Device_Instance
mbed_official	87:085cde657901	657	* @{
mbed_official	87:085cde657901	658	*/
mbed_official	87:085cde657901	659	#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
mbed_official	87:085cde657901	660
mbed_official	87:085cde657901	661	/**
mbed_official	87:085cde657901	662	* @}
mbed_official	87:085cde657901	663	*/
mbed_official	87:085cde657901	664
mbed_official	87:085cde657901	665	/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
mbed_official	87:085cde657901	666	* @{
mbed_official	87:085cde657901	667	*/
mbed_official	87:085cde657901	668	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	87:085cde657901	669
mbed_official	87:085cde657901	670	/**
mbed_official	87:085cde657901	671	* @}
mbed_official	87:085cde657901	672	*/
mbed_official	87:085cde657901	673
mbed_official	87:085cde657901	674	/** @defgroup FSMC_NAND_Device_Instance
mbed_official	87:085cde657901	675	* @{
mbed_official	87:085cde657901	676	*/
mbed_official	87:085cde657901	677	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
mbed_official	87:085cde657901	678
mbed_official	87:085cde657901	679	/**
mbed_official	87:085cde657901	680	* @}
mbed_official	87:085cde657901	681	*/
mbed_official	87:085cde657901	682
mbed_official	87:085cde657901	683	/** @defgroup FSMC_PCCARD_Device_Instance
mbed_official	87:085cde657901	684	* @{
mbed_official	87:085cde657901	685	*/
mbed_official	87:085cde657901	686	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
mbed_official	87:085cde657901	687
mbed_official	87:085cde657901	688	/**
mbed_official	87:085cde657901	689	* @}
mbed_official	87:085cde657901	690	*/
mbed_official	87:085cde657901	691
mbed_official	87:085cde657901	692	/** @defgroup FSMC_Interrupt_definition
mbed_official	87:085cde657901	693	* @brief FSMC Interrupt definition
mbed_official	87:085cde657901	694	* @{
mbed_official	87:085cde657901	695	*/
mbed_official	87:085cde657901	696	#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	87:085cde657901	697	#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	87:085cde657901	698	#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	87:085cde657901	699	#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	87:085cde657901	700
mbed_official	87:085cde657901	701	#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	87:085cde657901	702	#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) \|\| \
mbed_official	87:085cde657901	703	((IT) == FSMC_IT_LEVEL) \|\| \
mbed_official	87:085cde657901	704	((IT) == FSMC_IT_FALLING_EDGE) \|\| \
mbed_official	87:085cde657901	705	((IT) == FSMC_IT_REFRESH_ERROR))
mbed_official	87:085cde657901	706	/**
mbed_official	87:085cde657901	707	* @}
mbed_official	87:085cde657901	708	*/
mbed_official	87:085cde657901	709
mbed_official	87:085cde657901	710	/** @defgroup FSMC_Flag_definition
mbed_official	87:085cde657901	711	* @brief FSMC Flag definition
mbed_official	87:085cde657901	712	* @{
mbed_official	87:085cde657901	713	*/
mbed_official	87:085cde657901	714	#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	87:085cde657901	715	#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	87:085cde657901	716	#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	87:085cde657901	717	#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	87:085cde657901	718
mbed_official	87:085cde657901	719	#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) \|\| \
mbed_official	87:085cde657901	720	((FLAG) == FSMC_FLAG_LEVEL) \|\| \
mbed_official	87:085cde657901	721	((FLAG) == FSMC_FLAG_FALLING_EDGE) \|\| \
mbed_official	87:085cde657901	722	((FLAG) == FSMC_FLAG_FEMPT))
mbed_official	87:085cde657901	723
mbed_official	87:085cde657901	724	#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official	87:085cde657901	725
mbed_official	87:085cde657901	726
mbed_official	87:085cde657901	727	/**
mbed_official	87:085cde657901	728	* @}
mbed_official	87:085cde657901	729	*/
mbed_official	87:085cde657901	730
mbed_official	87:085cde657901	731
mbed_official	87:085cde657901	732	/* Exported macro ------------------------------------------------------------*/
mbed_official	87:085cde657901	733
mbed_official	87:085cde657901	734
mbed_official	87:085cde657901	735	/** @defgroup FSMC_NOR_Macros
mbed_official	87:085cde657901	736	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	87:085cde657901	737	* @{
mbed_official	87:085cde657901	738	*/
mbed_official	87:085cde657901	739
mbed_official	87:085cde657901	740	/**
mbed_official	87:085cde657901	741	* @brief Enable the NORSRAM device access.
mbed_official	87:085cde657901	742	* @param __INSTANCE__: FSMC_NORSRAM Instance
mbed_official	87:085cde657901	743	* @param __BANK__: FSMC_NORSRAM Bank
mbed_official	87:085cde657901	744	* @retval none
mbed_official	87:085cde657901	745	*/
mbed_official	87:085cde657901	746	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
mbed_official	87:085cde657901	747
mbed_official	87:085cde657901	748	/**
mbed_official	87:085cde657901	749	* @brief Disable the NORSRAM device access.
mbed_official	87:085cde657901	750	* @param __INSTANCE__: FSMC_NORSRAM Instance
mbed_official	87:085cde657901	751	* @param __BANK__: FSMC_NORSRAM Bank
mbed_official	87:085cde657901	752	* @retval none
mbed_official	87:085cde657901	753	*/
mbed_official	87:085cde657901	754	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
mbed_official	87:085cde657901	755
mbed_official	87:085cde657901	756	/**
mbed_official	87:085cde657901	757	* @}
mbed_official	87:085cde657901	758	*/
mbed_official	87:085cde657901	759
mbed_official	87:085cde657901	760
mbed_official	87:085cde657901	761	/** @defgroup FSMC_NAND_Macros
mbed_official	87:085cde657901	762	* @brief macros to handle NAND device enable/disable
mbed_official	87:085cde657901	763	* @{
mbed_official	87:085cde657901	764	*/
mbed_official	87:085cde657901	765
mbed_official	87:085cde657901	766	/**
mbed_official	87:085cde657901	767	* @brief Enable the NAND device access.
mbed_official	87:085cde657901	768	* @param __INSTANCE__: FSMC_NAND Instance
mbed_official	87:085cde657901	769	* @param __BANK__: FSMC_NAND Bank
mbed_official	87:085cde657901	770	* @retval none
mbed_official	87:085cde657901	771	*/
mbed_official	87:085cde657901	772	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
mbed_official	87:085cde657901	773	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
mbed_official	87:085cde657901	774
mbed_official	87:085cde657901	775
mbed_official	87:085cde657901	776	/**
mbed_official	87:085cde657901	777	* @brief Disable the NAND device access.
mbed_official	87:085cde657901	778	* @param __INSTANCE__: FSMC_NAND Instance
mbed_official	87:085cde657901	779	* @param __BANK__: FSMC_NAND Bank
mbed_official	87:085cde657901	780	* @retval none
mbed_official	87:085cde657901	781	*/
mbed_official	87:085cde657901	782	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
mbed_official	87:085cde657901	783	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
mbed_official	87:085cde657901	784
mbed_official	87:085cde657901	785
mbed_official	87:085cde657901	786	/**
mbed_official	87:085cde657901	787	* @}
mbed_official	87:085cde657901	788	*/
mbed_official	87:085cde657901	789
mbed_official	87:085cde657901	790	/** @defgroup FSMC_PCCARD_Macros
mbed_official	87:085cde657901	791	* @brief macros to handle SRAM read/write operations
mbed_official	87:085cde657901	792	* @{
mbed_official	87:085cde657901	793	*/
mbed_official	87:085cde657901	794
mbed_official	87:085cde657901	795	/**
mbed_official	87:085cde657901	796	* @brief Enable the PCCARD device access.
mbed_official	87:085cde657901	797	* @param __INSTANCE__: FSMC_PCCARD Instance
mbed_official	87:085cde657901	798	* @retval none
mbed_official	87:085cde657901	799	*/
mbed_official	87:085cde657901	800	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
mbed_official	87:085cde657901	801
mbed_official	87:085cde657901	802	/**
mbed_official	87:085cde657901	803	* @brief Disable the PCCARD device access.
mbed_official	87:085cde657901	804	* @param __INSTANCE__: FSMC_PCCARD Instance
mbed_official	87:085cde657901	805	* @retval none
mbed_official	87:085cde657901	806	*/
mbed_official	87:085cde657901	807	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
mbed_official	87:085cde657901	808
mbed_official	87:085cde657901	809	/**
mbed_official	87:085cde657901	810	* @}
mbed_official	87:085cde657901	811	*/
mbed_official	87:085cde657901	812
mbed_official	87:085cde657901	813	/** @defgroup FSMC_Interrupt
mbed_official	87:085cde657901	814	* @brief macros to handle FSMC interrupts
mbed_official	87:085cde657901	815	* @{
mbed_official	87:085cde657901	816	*/
mbed_official	87:085cde657901	817
mbed_official	87:085cde657901	818	/**
mbed_official	87:085cde657901	819	* @brief Enable the NAND device interrupt.
mbed_official	87:085cde657901	820	* @param __INSTANCE__: FSMC_NAND Instance
mbed_official	87:085cde657901	821	* @param __BANK__: FSMC_NAND Bank
mbed_official	87:085cde657901	822	* @param __INTERRUPT__: FSMC_NAND interrupt
mbed_official	87:085cde657901	823	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	824	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	825	* @arg FSMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	826	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	827	* @retval None
mbed_official	87:085cde657901	828	*/
mbed_official	87:085cde657901	829	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
mbed_official	87:085cde657901	830	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
mbed_official	87:085cde657901	831
mbed_official	87:085cde657901	832	/**
mbed_official	87:085cde657901	833	* @brief Disable the NAND device interrupt.
mbed_official	87:085cde657901	834	* @param __INSTANCE__: FSMC_NAND Instance
mbed_official	87:085cde657901	835	* @param __BANK__: FSMC_NAND Bank
mbed_official	87:085cde657901	836	* @param __INTERRUPT__: FSMC_NAND interrupt
mbed_official	87:085cde657901	837	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	838	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	839	* @arg FSMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	840	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	841	* @retval None
mbed_official	87:085cde657901	842	*/
mbed_official	87:085cde657901	843	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official	87:085cde657901	844	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official	87:085cde657901	845
mbed_official	87:085cde657901	846	/**
mbed_official	87:085cde657901	847	* @brief Get flag status of the NAND device.
mbed_official	87:085cde657901	848	* @param __INSTANCE__: FSMC_NAND Instance
mbed_official	87:085cde657901	849	* @param __BANK__: FSMC_NAND Bank
mbed_official	87:085cde657901	850	* @param __FLAG__: FSMC_NAND flag
mbed_official	87:085cde657901	851	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	852	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	853	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	854	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	855	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	856	* @retval The state of FLAG (SET or RESET).
mbed_official	87:085cde657901	857	*/
mbed_official	87:085cde657901	858	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official	87:085cde657901	859	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official	87:085cde657901	860	/**
mbed_official	87:085cde657901	861	* @brief Clear flag status of the NAND device.
mbed_official	87:085cde657901	862	* @param __INSTANCE__: FSMC_NAND Instance
mbed_official	87:085cde657901	863	* @param __BANK__: FSMC_NAND Bank
mbed_official	87:085cde657901	864	* @param __FLAG__: FSMC_NAND flag
mbed_official	87:085cde657901	865	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	866	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	867	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	868	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	869	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	870	* @retval None
mbed_official	87:085cde657901	871	*/
mbed_official	87:085cde657901	872	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official	87:085cde657901	873	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	87:085cde657901	874	/**
mbed_official	87:085cde657901	875	* @brief Enable the PCCARD device interrupt.
mbed_official	87:085cde657901	876	* @param __INSTANCE__: FSMC_PCCARD Instance
mbed_official	87:085cde657901	877	* @param __INTERRUPT__: FSMC_PCCARD interrupt
mbed_official	87:085cde657901	878	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	879	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	880	* @arg FSMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	881	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	882	* @retval None
mbed_official	87:085cde657901	883	*/
mbed_official	87:085cde657901	884	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
mbed_official	87:085cde657901	885
mbed_official	87:085cde657901	886	/**
mbed_official	87:085cde657901	887	* @brief Disable the PCCARD device interrupt.
mbed_official	87:085cde657901	888	* @param __INSTANCE__: FSMC_PCCARD Instance
mbed_official	87:085cde657901	889	* @param __INTERRUPT__: FSMC_PCCARD interrupt
mbed_official	87:085cde657901	890	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	891	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	892	* @arg FSMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	893	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	894	* @retval None
mbed_official	87:085cde657901	895	*/
mbed_official	87:085cde657901	896	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official	87:085cde657901	897
mbed_official	87:085cde657901	898	/**
mbed_official	87:085cde657901	899	* @brief Get flag status of the PCCARD device.
mbed_official	87:085cde657901	900	* @param __INSTANCE__: FSMC_PCCARD Instance
mbed_official	87:085cde657901	901	* @param __FLAG__: FSMC_PCCARD flag
mbed_official	87:085cde657901	902	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	903	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	904	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	905	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	906	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	907	* @retval The state of FLAG (SET or RESET).
mbed_official	87:085cde657901	908	*/
mbed_official	87:085cde657901	909	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official	87:085cde657901	910
mbed_official	87:085cde657901	911	/**
mbed_official	87:085cde657901	912	* @brief Clear flag status of the PCCARD device.
mbed_official	87:085cde657901	913	* @param __INSTANCE__: FSMC_PCCARD Instance
mbed_official	87:085cde657901	914	* @param __FLAG__: FSMC_PCCARD flag
mbed_official	87:085cde657901	915	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	916	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	917	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	918	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	919	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	920	* @retval None
mbed_official	87:085cde657901	921	*/
mbed_official	87:085cde657901	922	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official	87:085cde657901	923
mbed_official	87:085cde657901	924	/**
mbed_official	87:085cde657901	925	* @}
mbed_official	87:085cde657901	926	*/
mbed_official	87:085cde657901	927
mbed_official	87:085cde657901	928	/* Exported functions --------------------------------------------------------*/
mbed_official	87:085cde657901	929
mbed_official	87:085cde657901	930	/* FSMC_NORSRAM Controller functions ******************************************/
mbed_official	87:085cde657901	931	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	932	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
mbed_official	87:085cde657901	933	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	934	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	87:085cde657901	935	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	87:085cde657901	936
mbed_official	87:085cde657901	937	/* FSMC_NORSRAM Control functions */
mbed_official	87:085cde657901	938	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	939	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	940
mbed_official	87:085cde657901	941	/* FSMC_NAND Controller functions *********************************************/
mbed_official	87:085cde657901	942	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	943	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
mbed_official	87:085cde657901	944	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	945	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	946	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	947
mbed_official	87:085cde657901	948	/* FSMC_NAND Control functions */
mbed_official	87:085cde657901	949	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	950	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	951	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	87:085cde657901	952
mbed_official	87:085cde657901	953	/* FSMC_PCCARD Controller functions *******************************************/
mbed_official	87:085cde657901	954	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	955	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
mbed_official	87:085cde657901	956	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	87:085cde657901	957	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	87:085cde657901	958	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	87:085cde657901	959	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
mbed_official	87:085cde657901	960
mbed_official	87:085cde657901	961	/* FSMC APIs, macros and typedefs redefinition */
mbed_official	87:085cde657901	962	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
mbed_official	87:085cde657901	963	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
mbed_official	87:085cde657901	964	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
mbed_official	87:085cde657901	965	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
mbed_official	87:085cde657901	966
mbed_official	87:085cde657901	967	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
mbed_official	87:085cde657901	968	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
mbed_official	87:085cde657901	969	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
mbed_official	87:085cde657901	970	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
mbed_official	87:085cde657901	971	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
mbed_official	87:085cde657901	972	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
mbed_official	87:085cde657901	973
mbed_official	87:085cde657901	974	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
mbed_official	87:085cde657901	975	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
mbed_official	87:085cde657901	976
mbed_official	87:085cde657901	977	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
mbed_official	87:085cde657901	978	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
mbed_official	87:085cde657901	979	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
mbed_official	87:085cde657901	980
mbed_official	87:085cde657901	981	#define FMC_NAND_Init FSMC_NAND_Init
mbed_official	87:085cde657901	982	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
mbed_official	87:085cde657901	983	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
mbed_official	87:085cde657901	984	#define FMC_NAND_DeInit FSMC_NAND_DeInit
mbed_official	87:085cde657901	985	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
mbed_official	87:085cde657901	986	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
mbed_official	87:085cde657901	987	#define FMC_NAND_GetECC FSMC_NAND_GetECC
mbed_official	87:085cde657901	988	#define FMC_PCCARD_Init FSMC_PCCARD_Init
mbed_official	87:085cde657901	989	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
mbed_official	87:085cde657901	990	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
mbed_official	87:085cde657901	991	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
mbed_official	87:085cde657901	992	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
mbed_official	87:085cde657901	993
mbed_official	87:085cde657901	994	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
mbed_official	87:085cde657901	995	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
mbed_official	87:085cde657901	996	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
mbed_official	87:085cde657901	997	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
mbed_official	87:085cde657901	998	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
mbed_official	87:085cde657901	999	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
mbed_official	87:085cde657901	1000	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
mbed_official	87:085cde657901	1001	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
mbed_official	87:085cde657901	1002	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
mbed_official	87:085cde657901	1003	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
mbed_official	87:085cde657901	1004	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
mbed_official	87:085cde657901	1005	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
mbed_official	87:085cde657901	1006
mbed_official	87:085cde657901	1007	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
mbed_official	87:085cde657901	1008	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
mbed_official	87:085cde657901	1009	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
mbed_official	87:085cde657901	1010	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
mbed_official	87:085cde657901	1011
mbed_official	87:085cde657901	1012	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
mbed_official	87:085cde657901	1013	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
mbed_official	87:085cde657901	1014	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
mbed_official	87:085cde657901	1015	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
mbed_official	87:085cde657901	1016
mbed_official	87:085cde657901	1017	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
mbed_official	87:085cde657901	1018
mbed_official	87:085cde657901	1019	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
mbed_official	87:085cde657901	1020	#define FMC_IT_LEVEL FSMC_IT_LEVEL
mbed_official	87:085cde657901	1021	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
mbed_official	87:085cde657901	1022	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
mbed_official	87:085cde657901	1023
mbed_official	87:085cde657901	1024	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
mbed_official	87:085cde657901	1025	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
mbed_official	87:085cde657901	1026	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
mbed_official	87:085cde657901	1027	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
mbed_official	87:085cde657901	1028
mbed_official	87:085cde657901	1029	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
mbed_official	87:085cde657901	1030
mbed_official	87:085cde657901	1031	/**
mbed_official	87:085cde657901	1032	* @}
mbed_official	87:085cde657901	1033	*/
mbed_official	87:085cde657901	1034
mbed_official	87:085cde657901	1035	/**
mbed_official	87:085cde657901	1036	* @}
mbed_official	87:085cde657901	1037	*/
mbed_official	87:085cde657901	1038
mbed_official	87:085cde657901	1039	#ifdef __cplusplus
mbed_official	87:085cde657901	1040	}
mbed_official	87:085cde657901	1041	#endif
mbed_official	87:085cde657901	1042
mbed_official	87:085cde657901	1043	#endif /* __STM32F4xx_LL_FSMC_H */
mbed_official	87:085cde657901	1044
mbed_official	87:085cde657901	1045	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h@106:ced8cbb51063, 2014-02-26 (annotated)

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