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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:: mbed_official
Date:: Wed Feb 26 09:45:12 2014 +0000
Revision:: 106:ced8cbb51063
Parent:: 87:085cde657901
Child:: 226:b062af740e40

Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_ll_fmc.h
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	106:ced8cbb51063	5	* @version V1.0.0
mbed_official	106:ced8cbb51063	6	* @date 18-February-2014
mbed_official	87:085cde657901	7	* @brief Header file of FMC HAL module.
mbed_official	87:085cde657901	8	******************************************************************************
mbed_official	87:085cde657901	9	* @attention
mbed_official	87:085cde657901	10	*
mbed_official	87:085cde657901	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	12	*
mbed_official	87:085cde657901	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	14	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	16	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	19	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	21	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	22	* without specific prior written permission.
mbed_official	87:085cde657901	23	*
mbed_official	87:085cde657901	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	34	*
mbed_official	87:085cde657901	35	******************************************************************************
mbed_official	87:085cde657901	36	*/
mbed_official	87:085cde657901	37
mbed_official	87:085cde657901	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	87:085cde657901	39	#ifndef __STM32F4xx_LL_FMC_H
mbed_official	87:085cde657901	40	#define __STM32F4xx_LL_FMC_H
mbed_official	87:085cde657901	41
mbed_official	87:085cde657901	42	#ifdef __cplusplus
mbed_official	87:085cde657901	43	extern "C" {
mbed_official	87:085cde657901	44	#endif
mbed_official	87:085cde657901	45
mbed_official	87:085cde657901	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	49	#include "stm32f4xx_hal_def.h"
mbed_official	87:085cde657901	50
mbed_official	87:085cde657901	51	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	52	* @{
mbed_official	87:085cde657901	53	*/
mbed_official	87:085cde657901	54
mbed_official	87:085cde657901	55	/** @addtogroup FMC
mbed_official	87:085cde657901	56	* @{
mbed_official	87:085cde657901	57	*/
mbed_official	87:085cde657901	58
mbed_official	87:085cde657901	59	/* Exported typedef ----------------------------------------------------------*/
mbed_official	87:085cde657901	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official	87:085cde657901	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official	87:085cde657901	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
mbed_official	87:085cde657901	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official	87:085cde657901	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
mbed_official	87:085cde657901	65
mbed_official	87:085cde657901	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official	87:085cde657901	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official	87:085cde657901	68	#define FMC_NAND_DEVICE FMC_Bank2_3
mbed_official	87:085cde657901	69	#define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official	87:085cde657901	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
mbed_official	87:085cde657901	71
mbed_official	87:085cde657901	72
mbed_official	87:085cde657901	73	/**
mbed_official	87:085cde657901	74	* @brief FMC_NORSRAM Configuration Structure definition
mbed_official	87:085cde657901	75	*/
mbed_official	87:085cde657901	76	typedef struct
mbed_official	87:085cde657901	77	{
mbed_official	87:085cde657901	78	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	87:085cde657901	79	This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official	87:085cde657901	80
mbed_official	87:085cde657901	81	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	87:085cde657901	82	multiplexed on the data bus or not.
mbed_official	87:085cde657901	83	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official	87:085cde657901	84
mbed_official	87:085cde657901	85	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	87:085cde657901	86	the corresponding memory device.
mbed_official	87:085cde657901	87	This parameter can be a value of @ref FMC_Memory_Type */
mbed_official	87:085cde657901	88
mbed_official	87:085cde657901	89	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	87:085cde657901	90	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official	87:085cde657901	91
mbed_official	87:085cde657901	92	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	87:085cde657901	93	valid only with synchronous burst Flash memories.
mbed_official	87:085cde657901	94	This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official	87:085cde657901	95
mbed_official	87:085cde657901	96	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	87:085cde657901	97	the Flash memory in burst mode.
mbed_official	87:085cde657901	98	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official	87:085cde657901	99
mbed_official	87:085cde657901	100	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	87:085cde657901	101	memory, valid only when accessing Flash memories in burst mode.
mbed_official	87:085cde657901	102	This parameter can be a value of @ref FMC_Wrap_Mode */
mbed_official	87:085cde657901	103
mbed_official	87:085cde657901	104	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	87:085cde657901	105	clock cycle before the wait state or during the wait state,
mbed_official	87:085cde657901	106	valid only when accessing memories in burst mode.
mbed_official	87:085cde657901	107	This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official	87:085cde657901	108
mbed_official	87:085cde657901	109	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official	87:085cde657901	110	This parameter can be a value of @ref FMC_Write_Operation */
mbed_official	87:085cde657901	111
mbed_official	87:085cde657901	112	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	87:085cde657901	113	signal, valid for Flash memory access in burst mode.
mbed_official	87:085cde657901	114	This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official	87:085cde657901	115
mbed_official	87:085cde657901	116	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	87:085cde657901	117	This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official	87:085cde657901	118
mbed_official	87:085cde657901	119	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	87:085cde657901	120	valid only with asynchronous Flash memories.
mbed_official	87:085cde657901	121	This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official	87:085cde657901	122
mbed_official	87:085cde657901	123	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	87:085cde657901	124	This parameter can be a value of @ref FMC_Write_Burst */
mbed_official	87:085cde657901	125
mbed_official	87:085cde657901	126	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official	87:085cde657901	127	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	87:085cde657901	128	through FMC_BCR2..4 registers.
mbed_official	87:085cde657901	129	This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official	87:085cde657901	130
mbed_official	87:085cde657901	131	}FMC_NORSRAM_InitTypeDef;
mbed_official	87:085cde657901	132
mbed_official	87:085cde657901	133	/**
mbed_official	87:085cde657901	134	* @brief FMC_NORSRAM Timing parameters structure definition
mbed_official	87:085cde657901	135	*/
mbed_official	87:085cde657901	136	typedef struct
mbed_official	87:085cde657901	137	{
mbed_official	87:085cde657901	138	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	139	the duration of the address setup time.
mbed_official	87:085cde657901	140	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	87:085cde657901	141	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	87:085cde657901	142
mbed_official	87:085cde657901	143	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	144	the duration of the address hold time.
mbed_official	87:085cde657901	145	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	87:085cde657901	146	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	87:085cde657901	147
mbed_official	87:085cde657901	148	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	149	the duration of the data setup time.
mbed_official	87:085cde657901	150	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	87:085cde657901	151	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	87:085cde657901	152	NOR Flash memories. */
mbed_official	87:085cde657901	153
mbed_official	87:085cde657901	154	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	87:085cde657901	155	the duration of the bus turnaround.
mbed_official	87:085cde657901	156	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	87:085cde657901	157	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	87:085cde657901	158
mbed_official	87:085cde657901	159	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	87:085cde657901	160	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	87:085cde657901	161	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	87:085cde657901	162	accesses. */
mbed_official	87:085cde657901	163
mbed_official	87:085cde657901	164	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	87:085cde657901	165	to the memory before getting the first data.
mbed_official	87:085cde657901	166	The parameter value depends on the memory type as shown below:
mbed_official	87:085cde657901	167	- It must be set to 0 in case of a CRAM
mbed_official	87:085cde657901	168	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	87:085cde657901	169	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	87:085cde657901	170	with synchronous burst mode enable */
mbed_official	87:085cde657901	171
mbed_official	87:085cde657901	172	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	87:085cde657901	173	This parameter can be a value of @ref FMC_Access_Mode */
mbed_official	87:085cde657901	174
mbed_official	87:085cde657901	175	}FMC_NORSRAM_TimingTypeDef;
mbed_official	87:085cde657901	176
mbed_official	87:085cde657901	177	/**
mbed_official	87:085cde657901	178	* @brief FMC_NAND Configuration Structure definition
mbed_official	87:085cde657901	179	*/
mbed_official	87:085cde657901	180	typedef struct
mbed_official	87:085cde657901	181	{
mbed_official	87:085cde657901	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	87:085cde657901	183	This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official	87:085cde657901	184
mbed_official	87:085cde657901	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	87:085cde657901	186	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	87:085cde657901	187
mbed_official	87:085cde657901	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	87:085cde657901	189	This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official	87:085cde657901	190
mbed_official	87:085cde657901	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	87:085cde657901	192	This parameter can be any value of @ref FMC_ECC */
mbed_official	87:085cde657901	193
mbed_official	87:085cde657901	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	87:085cde657901	195	This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official	87:085cde657901	196
mbed_official	87:085cde657901	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	198	delay between CLE low and RE low.
mbed_official	87:085cde657901	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	200
mbed_official	87:085cde657901	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	202	delay between ALE low and RE low.
mbed_official	87:085cde657901	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	204
mbed_official	87:085cde657901	205	}FMC_NAND_InitTypeDef;
mbed_official	87:085cde657901	206
mbed_official	87:085cde657901	207	/**
mbed_official	87:085cde657901	208	* @brief FMC_NAND_PCCARD Timing parameters structure definition
mbed_official	87:085cde657901	209	*/
mbed_official	87:085cde657901	210	typedef struct
mbed_official	87:085cde657901	211	{
mbed_official	87:085cde657901	212	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	87:085cde657901	213	the command assertion for NAND-Flash read or write access
mbed_official	87:085cde657901	214	to common/Attribute or I/O memory space (depending on
mbed_official	87:085cde657901	215	the memory space timing to be configured).
mbed_official	87:085cde657901	216	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	217
mbed_official	87:085cde657901	218	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	87:085cde657901	219	command for NAND-Flash read or write access to
mbed_official	87:085cde657901	220	common/Attribute or I/O memory space (depending on the
mbed_official	87:085cde657901	221	memory space timing to be configured).
mbed_official	87:085cde657901	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	223
mbed_official	87:085cde657901	224	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	87:085cde657901	225	(and data for write access) after the command de-assertion
mbed_official	87:085cde657901	226	for NAND-Flash read or write access to common/Attribute
mbed_official	87:085cde657901	227	or I/O memory space (depending on the memory space timing
mbed_official	87:085cde657901	228	to be configured).
mbed_official	87:085cde657901	229	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	230
mbed_official	87:085cde657901	231	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	87:085cde657901	232	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	87:085cde657901	233	write access to common/Attribute or I/O memory space (depending
mbed_official	87:085cde657901	234	on the memory space timing to be configured).
mbed_official	87:085cde657901	235	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	236
mbed_official	87:085cde657901	237	}FMC_NAND_PCC_TimingTypeDef;
mbed_official	87:085cde657901	238
mbed_official	87:085cde657901	239	/**
mbed_official	87:085cde657901	240	* @brief FMC_NAND Configuration Structure definition
mbed_official	87:085cde657901	241	*/
mbed_official	87:085cde657901	242	typedef struct
mbed_official	87:085cde657901	243	{
mbed_official	87:085cde657901	244	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official	87:085cde657901	245	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	87:085cde657901	246
mbed_official	87:085cde657901	247	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	248	delay between CLE low and RE low.
mbed_official	87:085cde657901	249	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	250
mbed_official	87:085cde657901	251	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	87:085cde657901	252	delay between ALE low and RE low.
mbed_official	87:085cde657901	253	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	87:085cde657901	254
mbed_official	87:085cde657901	255	}FMC_PCCARD_InitTypeDef;
mbed_official	87:085cde657901	256
mbed_official	87:085cde657901	257	/**
mbed_official	87:085cde657901	258	* @brief FMC_SDRAM Configuration Structure definition
mbed_official	87:085cde657901	259	*/
mbed_official	87:085cde657901	260	typedef struct
mbed_official	87:085cde657901	261	{
mbed_official	87:085cde657901	262	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
mbed_official	87:085cde657901	263	This parameter can be a value of @ref FMC_SDRAM_Bank */
mbed_official	87:085cde657901	264
mbed_official	87:085cde657901	265	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	87:085cde657901	266	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
mbed_official	87:085cde657901	267
mbed_official	87:085cde657901	268	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	87:085cde657901	269	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
mbed_official	87:085cde657901	270
mbed_official	87:085cde657901	271	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
mbed_official	87:085cde657901	272	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
mbed_official	87:085cde657901	273
mbed_official	87:085cde657901	274	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
mbed_official	87:085cde657901	275	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
mbed_official	87:085cde657901	276
mbed_official	87:085cde657901	277	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
mbed_official	87:085cde657901	278	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
mbed_official	87:085cde657901	279
mbed_official	87:085cde657901	280	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
mbed_official	87:085cde657901	281	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
mbed_official	87:085cde657901	282
mbed_official	87:085cde657901	283	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
mbed_official	87:085cde657901	284	to disable the clock before changing frequency.
mbed_official	87:085cde657901	285	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
mbed_official	87:085cde657901	286
mbed_official	87:085cde657901	287	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
mbed_official	87:085cde657901	288	commands during the CAS latency and stores data in the Read FIFO.
mbed_official	87:085cde657901	289	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
mbed_official	87:085cde657901	290
mbed_official	87:085cde657901	291	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
mbed_official	87:085cde657901	292	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
mbed_official	87:085cde657901	293
mbed_official	87:085cde657901	294	}FMC_SDRAM_InitTypeDef;
mbed_official	87:085cde657901	295
mbed_official	87:085cde657901	296	/**
mbed_official	87:085cde657901	297	* @brief FMC_SDRAM Timing parameters structure definition
mbed_official	87:085cde657901	298	*/
mbed_official	87:085cde657901	299	typedef struct
mbed_official	87:085cde657901	300	{
mbed_official	87:085cde657901	301	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
mbed_official	87:085cde657901	302	an active or Refresh command in number of memory clock cycles.
mbed_official	87:085cde657901	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	304
mbed_official	87:085cde657901	305	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
mbed_official	87:085cde657901	306	issuing the Activate command in number of memory clock cycles.
mbed_official	87:085cde657901	307	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	308
mbed_official	87:085cde657901	309	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
mbed_official	87:085cde657901	310	cycles.
mbed_official	87:085cde657901	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	312
mbed_official	87:085cde657901	313	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
mbed_official	87:085cde657901	314	and the delay between two consecutive Refresh commands in number of
mbed_official	87:085cde657901	315	memory clock cycles.
mbed_official	87:085cde657901	316	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	317
mbed_official	87:085cde657901	318	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
mbed_official	87:085cde657901	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	320
mbed_official	87:085cde657901	321	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
mbed_official	87:085cde657901	322	in number of memory clock cycles.
mbed_official	87:085cde657901	323	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	324
mbed_official	87:085cde657901	325	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
mbed_official	87:085cde657901	326	command in number of memory clock cycles.
mbed_official	87:085cde657901	327	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	328
mbed_official	87:085cde657901	329	}FMC_SDRAM_TimingTypeDef;
mbed_official	87:085cde657901	330
mbed_official	87:085cde657901	331	/**
mbed_official	87:085cde657901	332	* @brief SDRAM command parameters structure definition
mbed_official	87:085cde657901	333	*/
mbed_official	87:085cde657901	334	typedef struct
mbed_official	87:085cde657901	335	{
mbed_official	87:085cde657901	336	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
mbed_official	87:085cde657901	337	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
mbed_official	87:085cde657901	338
mbed_official	87:085cde657901	339	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
mbed_official	87:085cde657901	340	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
mbed_official	87:085cde657901	341
mbed_official	87:085cde657901	342	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
mbed_official	87:085cde657901	343	in auto refresh mode.
mbed_official	87:085cde657901	344	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	87:085cde657901	345
mbed_official	87:085cde657901	346	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
mbed_official	87:085cde657901	347
mbed_official	87:085cde657901	348	}FMC_SDRAM_CommandTypeDef;
mbed_official	87:085cde657901	349
mbed_official	87:085cde657901	350	/* Exported constants --------------------------------------------------------*/
mbed_official	87:085cde657901	351
mbed_official	87:085cde657901	352	/** @defgroup FMC_NOR_SRAM_Controller
mbed_official	87:085cde657901	353	* @{
mbed_official	87:085cde657901	354	*/
mbed_official	87:085cde657901	355
mbed_official	87:085cde657901	356	/** @defgroup FMC_NORSRAM_Bank
mbed_official	87:085cde657901	357	* @{
mbed_official	87:085cde657901	358	*/
mbed_official	87:085cde657901	359	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	360	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	87:085cde657901	361	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	87:085cde657901	362	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	87:085cde657901	363
mbed_official	87:085cde657901	364	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
mbed_official	87:085cde657901	365	((BANK) == FMC_NORSRAM_BANK2) \|\| \
mbed_official	87:085cde657901	366	((BANK) == FMC_NORSRAM_BANK3) \|\| \
mbed_official	87:085cde657901	367	((BANK) == FMC_NORSRAM_BANK4))
mbed_official	87:085cde657901	368	/**
mbed_official	87:085cde657901	369	* @}
mbed_official	87:085cde657901	370	*/
mbed_official	87:085cde657901	371
mbed_official	87:085cde657901	372	/** @defgroup FMC_Data_Address_Bus_Multiplexing
mbed_official	87:085cde657901	373	* @{
mbed_official	87:085cde657901	374	*/
mbed_official	87:085cde657901	375	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	376	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	87:085cde657901	377
mbed_official	87:085cde657901	378	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	87:085cde657901	379	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	87:085cde657901	380	/**
mbed_official	87:085cde657901	381	* @}
mbed_official	87:085cde657901	382	*/
mbed_official	87:085cde657901	383
mbed_official	87:085cde657901	384	/** @defgroup FMC_Memory_Type
mbed_official	87:085cde657901	385	* @{
mbed_official	87:085cde657901	386	*/
mbed_official	87:085cde657901	387	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	87:085cde657901	388	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	87:085cde657901	389	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	87:085cde657901	390
mbed_official	87:085cde657901	391	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	87:085cde657901	392	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	87:085cde657901	393	((MEMORY) == FMC_MEMORY_TYPE_NOR))
mbed_official	87:085cde657901	394	/**
mbed_official	87:085cde657901	395	* @}
mbed_official	87:085cde657901	396	*/
mbed_official	87:085cde657901	397
mbed_official	87:085cde657901	398	/** @defgroup FMC_NORSRAM_Data_Width
mbed_official	87:085cde657901	399	* @{
mbed_official	87:085cde657901	400	*/
mbed_official	87:085cde657901	401	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	402	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	403	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	87:085cde657901	404
mbed_official	87:085cde657901	405	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	87:085cde657901	406	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	87:085cde657901	407	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	87:085cde657901	408	/**
mbed_official	87:085cde657901	409	* @}
mbed_official	87:085cde657901	410	*/
mbed_official	87:085cde657901	411
mbed_official	87:085cde657901	412	/** @defgroup FMC_NORSRAM_Flash_Access
mbed_official	87:085cde657901	413	* @{
mbed_official	87:085cde657901	414	*/
mbed_official	87:085cde657901	415	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	87:085cde657901	416	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	417	/**
mbed_official	87:085cde657901	418	* @}
mbed_official	87:085cde657901	419	*/
mbed_official	87:085cde657901	420
mbed_official	87:085cde657901	421	/** @defgroup FMC_Burst_Access_Mode
mbed_official	87:085cde657901	422	* @{
mbed_official	87:085cde657901	423	*/
mbed_official	87:085cde657901	424	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	425	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	87:085cde657901	426
mbed_official	87:085cde657901	427	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	87:085cde657901	428	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	87:085cde657901	429	/**
mbed_official	87:085cde657901	430	* @}
mbed_official	87:085cde657901	431	*/
mbed_official	87:085cde657901	432
mbed_official	87:085cde657901	433
mbed_official	87:085cde657901	434	/** @defgroup FMC_Wait_Signal_Polarity
mbed_official	87:085cde657901	435	* @{
mbed_official	87:085cde657901	436	*/
mbed_official	87:085cde657901	437	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	87:085cde657901	438	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	87:085cde657901	439
mbed_official	87:085cde657901	440	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	87:085cde657901	441	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	87:085cde657901	442	/**
mbed_official	87:085cde657901	443	* @}
mbed_official	87:085cde657901	444	*/
mbed_official	87:085cde657901	445
mbed_official	87:085cde657901	446	/** @defgroup FMC_Wrap_Mode
mbed_official	87:085cde657901	447	* @{
mbed_official	87:085cde657901	448	*/
mbed_official	87:085cde657901	449	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	450	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official	87:085cde657901	451
mbed_official	87:085cde657901	452	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	87:085cde657901	453	((MODE) == FMC_WRAP_MODE_ENABLE))
mbed_official	87:085cde657901	454	/**
mbed_official	87:085cde657901	455	* @}
mbed_official	87:085cde657901	456	*/
mbed_official	87:085cde657901	457
mbed_official	87:085cde657901	458	/** @defgroup FMC_Wait_Timing
mbed_official	87:085cde657901	459	* @{
mbed_official	87:085cde657901	460	*/
mbed_official	87:085cde657901	461	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	87:085cde657901	462	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	87:085cde657901	463
mbed_official	87:085cde657901	464	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	87:085cde657901	465	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
mbed_official	87:085cde657901	466	/**
mbed_official	87:085cde657901	467	* @}
mbed_official	87:085cde657901	468	*/
mbed_official	87:085cde657901	469
mbed_official	87:085cde657901	470	/** @defgroup FMC_Write_Operation
mbed_official	87:085cde657901	471	* @{
mbed_official	87:085cde657901	472	*/
mbed_official	87:085cde657901	473	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	474	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	87:085cde657901	475
mbed_official	87:085cde657901	476	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	87:085cde657901	477	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
mbed_official	87:085cde657901	478	/**
mbed_official	87:085cde657901	479	* @}
mbed_official	87:085cde657901	480	*/
mbed_official	87:085cde657901	481
mbed_official	87:085cde657901	482	/** @defgroup FMC_Wait_Signal
mbed_official	87:085cde657901	483	* @{
mbed_official	87:085cde657901	484	*/
mbed_official	87:085cde657901	485	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	486	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	87:085cde657901	487
mbed_official	87:085cde657901	488	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	87:085cde657901	489	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official	87:085cde657901	490	/**
mbed_official	87:085cde657901	491	* @}
mbed_official	87:085cde657901	492	*/
mbed_official	87:085cde657901	493
mbed_official	87:085cde657901	494	/** @defgroup FMC_Extended_Mode
mbed_official	87:085cde657901	495	* @{
mbed_official	87:085cde657901	496	*/
mbed_official	87:085cde657901	497	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	498	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	87:085cde657901	499
mbed_official	87:085cde657901	500	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	87:085cde657901	501	((MODE) == FMC_EXTENDED_MODE_ENABLE))
mbed_official	87:085cde657901	502	/**
mbed_official	87:085cde657901	503	* @}
mbed_official	87:085cde657901	504	*/
mbed_official	87:085cde657901	505
mbed_official	87:085cde657901	506	/** @defgroup FMC_AsynchronousWait
mbed_official	87:085cde657901	507	* @{
mbed_official	87:085cde657901	508	*/
mbed_official	87:085cde657901	509	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	510	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	87:085cde657901	511
mbed_official	87:085cde657901	512	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	87:085cde657901	513	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	87:085cde657901	514	/**
mbed_official	87:085cde657901	515	* @}
mbed_official	87:085cde657901	516	*/
mbed_official	87:085cde657901	517
mbed_official	87:085cde657901	518	/** @defgroup FMC_Write_Burst
mbed_official	87:085cde657901	519	* @{
mbed_official	87:085cde657901	520	*/
mbed_official	87:085cde657901	521	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	522	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	87:085cde657901	523
mbed_official	87:085cde657901	524	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	87:085cde657901	525	((BURST) == FMC_WRITE_BURST_ENABLE))
mbed_official	87:085cde657901	526	/**
mbed_official	87:085cde657901	527	* @}
mbed_official	87:085cde657901	528	*/
mbed_official	87:085cde657901	529
mbed_official	87:085cde657901	530	/** @defgroup FMC_Continous_Clock
mbed_official	87:085cde657901	531	* @{
mbed_official	87:085cde657901	532	*/
mbed_official	87:085cde657901	533	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	87:085cde657901	534	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	87:085cde657901	535
mbed_official	87:085cde657901	536	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	87:085cde657901	537	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	87:085cde657901	538	/**
mbed_official	87:085cde657901	539	* @}
mbed_official	87:085cde657901	540	*/
mbed_official	87:085cde657901	541
mbed_official	87:085cde657901	542	/** @defgroup FMC_Address_Setup_Time
mbed_official	87:085cde657901	543	* @{
mbed_official	87:085cde657901	544	*/
mbed_official	87:085cde657901	545	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
mbed_official	87:085cde657901	546	/**
mbed_official	87:085cde657901	547	* @}
mbed_official	87:085cde657901	548	*/
mbed_official	87:085cde657901	549
mbed_official	87:085cde657901	550	/** @defgroup FMC_Address_Hold_Time
mbed_official	87:085cde657901	551	* @{
mbed_official	87:085cde657901	552	*/
mbed_official	87:085cde657901	553	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
mbed_official	87:085cde657901	554	/**
mbed_official	87:085cde657901	555	* @}
mbed_official	87:085cde657901	556	*/
mbed_official	87:085cde657901	557
mbed_official	87:085cde657901	558	/** @defgroup FMC_Data_Setup_Time
mbed_official	87:085cde657901	559	* @{
mbed_official	87:085cde657901	560	*/
mbed_official	87:085cde657901	561	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
mbed_official	87:085cde657901	562	/**
mbed_official	87:085cde657901	563	* @}
mbed_official	87:085cde657901	564	*/
mbed_official	87:085cde657901	565
mbed_official	87:085cde657901	566	/** @defgroup FMC_Bus_Turn_around_Duration
mbed_official	87:085cde657901	567	* @{
mbed_official	87:085cde657901	568	*/
mbed_official	87:085cde657901	569	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
mbed_official	87:085cde657901	570	/**
mbed_official	87:085cde657901	571	* @}
mbed_official	87:085cde657901	572	*/
mbed_official	87:085cde657901	573
mbed_official	87:085cde657901	574	/** @defgroup FMC_CLK_Division
mbed_official	87:085cde657901	575	* @{
mbed_official	87:085cde657901	576	*/
mbed_official	87:085cde657901	577	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	87:085cde657901	578	/**
mbed_official	87:085cde657901	579	* @}
mbed_official	87:085cde657901	580	*/
mbed_official	87:085cde657901	581
mbed_official	87:085cde657901	582	/** @defgroup FMC_Data_Latency
mbed_official	87:085cde657901	583	* @{
mbed_official	87:085cde657901	584	*/
mbed_official	87:085cde657901	585	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
mbed_official	87:085cde657901	586	/**
mbed_official	87:085cde657901	587	* @}
mbed_official	87:085cde657901	588	*/
mbed_official	87:085cde657901	589
mbed_official	87:085cde657901	590	/** @defgroup FMC_Access_Mode
mbed_official	87:085cde657901	591	* @{
mbed_official	87:085cde657901	592	*/
mbed_official	87:085cde657901	593	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	87:085cde657901	594	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	87:085cde657901	595	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	87:085cde657901	596	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	87:085cde657901	597
mbed_official	87:085cde657901	598	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
mbed_official	87:085cde657901	599	((MODE) == FMC_ACCESS_MODE_B) \|\| \
mbed_official	87:085cde657901	600	((MODE) == FMC_ACCESS_MODE_C) \|\| \
mbed_official	87:085cde657901	601	((MODE) == FMC_ACCESS_MODE_D))
mbed_official	87:085cde657901	602	/**
mbed_official	87:085cde657901	603	* @}
mbed_official	87:085cde657901	604	*/
mbed_official	87:085cde657901	605
mbed_official	87:085cde657901	606	/**
mbed_official	87:085cde657901	607	* @}
mbed_official	87:085cde657901	608	*/
mbed_official	87:085cde657901	609
mbed_official	87:085cde657901	610	/** @defgroup FMC_NAND_Controller
mbed_official	87:085cde657901	611	* @{
mbed_official	87:085cde657901	612	*/
mbed_official	87:085cde657901	613
mbed_official	87:085cde657901	614	/** @defgroup FMC_NAND_Bank
mbed_official	87:085cde657901	615	* @{
mbed_official	87:085cde657901	616	*/
mbed_official	87:085cde657901	617	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	618	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	87:085cde657901	619
mbed_official	87:085cde657901	620	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
mbed_official	87:085cde657901	621	((BANK) == FMC_NAND_BANK3))
mbed_official	87:085cde657901	622	/**
mbed_official	87:085cde657901	623	* @}
mbed_official	87:085cde657901	624	*/
mbed_official	87:085cde657901	625
mbed_official	87:085cde657901	626	/** @defgroup FMC_Wait_feature
mbed_official	87:085cde657901	627	* @{
mbed_official	87:085cde657901	628	*/
mbed_official	87:085cde657901	629	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	630	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	87:085cde657901	631
mbed_official	87:085cde657901	632	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	87:085cde657901	633	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official	87:085cde657901	634	/**
mbed_official	87:085cde657901	635	* @}
mbed_official	87:085cde657901	636	*/
mbed_official	87:085cde657901	637
mbed_official	87:085cde657901	638	/** @defgroup FMC_PCR_Memory_Type
mbed_official	87:085cde657901	639	* @{
mbed_official	87:085cde657901	640	*/
mbed_official	87:085cde657901	641	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official	87:085cde657901	642	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	87:085cde657901	643	/**
mbed_official	87:085cde657901	644	* @}
mbed_official	87:085cde657901	645	*/
mbed_official	87:085cde657901	646
mbed_official	87:085cde657901	647	/** @defgroup FMC_NAND_Data_Width
mbed_official	87:085cde657901	648	* @{
mbed_official	87:085cde657901	649	*/
mbed_official	87:085cde657901	650	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	651	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	652
mbed_official	87:085cde657901	653	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
mbed_official	87:085cde657901	654	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official	87:085cde657901	655	/**
mbed_official	87:085cde657901	656	* @}
mbed_official	87:085cde657901	657	*/
mbed_official	87:085cde657901	658
mbed_official	87:085cde657901	659	/** @defgroup FMC_ECC
mbed_official	87:085cde657901	660	* @{
mbed_official	87:085cde657901	661	*/
mbed_official	87:085cde657901	662	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	663	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	87:085cde657901	664
mbed_official	87:085cde657901	665	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
mbed_official	87:085cde657901	666	((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official	87:085cde657901	667	/**
mbed_official	87:085cde657901	668	* @}
mbed_official	87:085cde657901	669	*/
mbed_official	87:085cde657901	670
mbed_official	87:085cde657901	671	/** @defgroup FMC_ECC_Page_Size
mbed_official	87:085cde657901	672	* @{
mbed_official	87:085cde657901	673	*/
mbed_official	87:085cde657901	674	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	675	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	87:085cde657901	676	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	87:085cde657901	677	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	87:085cde657901	678	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	87:085cde657901	679	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	87:085cde657901	680
mbed_official	87:085cde657901	681	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	87:085cde657901	682	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	87:085cde657901	683	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	87:085cde657901	684	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	87:085cde657901	685	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	87:085cde657901	686	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	87:085cde657901	687	/**
mbed_official	87:085cde657901	688	* @}
mbed_official	87:085cde657901	689	*/
mbed_official	87:085cde657901	690
mbed_official	87:085cde657901	691	/** @defgroup FMC_TCLR_Setup_Time
mbed_official	87:085cde657901	692	* @{
mbed_official	87:085cde657901	693	*/
mbed_official	87:085cde657901	694	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	695	/**
mbed_official	87:085cde657901	696	* @}
mbed_official	87:085cde657901	697	*/
mbed_official	87:085cde657901	698
mbed_official	87:085cde657901	699	/** @defgroup FMC_TAR_Setup_Time
mbed_official	87:085cde657901	700	* @{
mbed_official	87:085cde657901	701	*/
mbed_official	87:085cde657901	702	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	703	/**
mbed_official	87:085cde657901	704	* @}
mbed_official	87:085cde657901	705	*/
mbed_official	87:085cde657901	706
mbed_official	87:085cde657901	707	/** @defgroup FMC_Setup_Time
mbed_official	87:085cde657901	708	* @{
mbed_official	87:085cde657901	709	*/
mbed_official	87:085cde657901	710	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	711	/**
mbed_official	87:085cde657901	712	* @}
mbed_official	87:085cde657901	713	*/
mbed_official	87:085cde657901	714
mbed_official	87:085cde657901	715	/** @defgroup FMC_Wait_Setup_Time
mbed_official	87:085cde657901	716	* @{
mbed_official	87:085cde657901	717	*/
mbed_official	87:085cde657901	718	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	719	/**
mbed_official	87:085cde657901	720	* @}
mbed_official	87:085cde657901	721	*/
mbed_official	87:085cde657901	722
mbed_official	87:085cde657901	723	/** @defgroup FMC_Hold_Setup_Time
mbed_official	87:085cde657901	724	* @{
mbed_official	87:085cde657901	725	*/
mbed_official	87:085cde657901	726	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	727	/**
mbed_official	87:085cde657901	728	* @}
mbed_official	87:085cde657901	729	*/
mbed_official	87:085cde657901	730
mbed_official	87:085cde657901	731	/** @defgroup FMC_HiZ_Setup_Time
mbed_official	87:085cde657901	732	* @{
mbed_official	87:085cde657901	733	*/
mbed_official	87:085cde657901	734	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	87:085cde657901	735	/**
mbed_official	87:085cde657901	736	* @}
mbed_official	87:085cde657901	737	*/
mbed_official	87:085cde657901	738
mbed_official	87:085cde657901	739	/**
mbed_official	87:085cde657901	740	* @}
mbed_official	87:085cde657901	741	*/
mbed_official	87:085cde657901	742
mbed_official	87:085cde657901	743	/** @defgroup FMC_SDRAM_Controller
mbed_official	87:085cde657901	744	* @{
mbed_official	87:085cde657901	745	*/
mbed_official	87:085cde657901	746
mbed_official	87:085cde657901	747	/** @defgroup FMC_SDRAM_Bank
mbed_official	87:085cde657901	748	* @{
mbed_official	87:085cde657901	749	*/
mbed_official	87:085cde657901	750	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	751	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
mbed_official	87:085cde657901	752
mbed_official	87:085cde657901	753	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
mbed_official	87:085cde657901	754	((BANK) == FMC_SDRAM_BANK2))
mbed_official	87:085cde657901	755	/**
mbed_official	87:085cde657901	756	* @}
mbed_official	87:085cde657901	757	*/
mbed_official	87:085cde657901	758
mbed_official	87:085cde657901	759	/** @defgroup FMC_SDRAM_Column_Bits_number
mbed_official	87:085cde657901	760	* @{
mbed_official	87:085cde657901	761	*/
mbed_official	87:085cde657901	762	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	763	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
mbed_official	87:085cde657901	764	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
mbed_official	87:085cde657901	765	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
mbed_official	87:085cde657901	766
mbed_official	87:085cde657901	767	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
mbed_official	87:085cde657901	768	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
mbed_official	87:085cde657901	769	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
mbed_official	87:085cde657901	770	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
mbed_official	87:085cde657901	771	/**
mbed_official	87:085cde657901	772	* @}
mbed_official	87:085cde657901	773	*/
mbed_official	87:085cde657901	774
mbed_official	87:085cde657901	775	/** @defgroup FMC_SDRAM_Row_Bits_number
mbed_official	87:085cde657901	776	* @{
mbed_official	87:085cde657901	777	*/
mbed_official	87:085cde657901	778	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	779	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
mbed_official	87:085cde657901	780	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
mbed_official	87:085cde657901	781
mbed_official	87:085cde657901	782	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
mbed_official	87:085cde657901	783	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
mbed_official	87:085cde657901	784	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
mbed_official	87:085cde657901	785	/**
mbed_official	87:085cde657901	786	* @}
mbed_official	87:085cde657901	787	*/
mbed_official	87:085cde657901	788
mbed_official	87:085cde657901	789	/** @defgroup FMC_SDRAM_Memory_Bus_Width
mbed_official	87:085cde657901	790	* @{
mbed_official	87:085cde657901	791	*/
mbed_official	87:085cde657901	792	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	793	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	87:085cde657901	794	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	87:085cde657901	795
mbed_official	87:085cde657901	796	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	87:085cde657901	797	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	87:085cde657901	798	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
mbed_official	87:085cde657901	799	/**
mbed_official	87:085cde657901	800	* @}
mbed_official	87:085cde657901	801	*/
mbed_official	87:085cde657901	802
mbed_official	87:085cde657901	803	/** @defgroup FMC_SDRAM_Internal_Banks_Number
mbed_official	87:085cde657901	804	* @{
mbed_official	87:085cde657901	805	*/
mbed_official	87:085cde657901	806	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	807	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
mbed_official	87:085cde657901	808
mbed_official	87:085cde657901	809	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
mbed_official	87:085cde657901	810	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
mbed_official	87:085cde657901	811	/**
mbed_official	87:085cde657901	812	* @}
mbed_official	87:085cde657901	813	*/
mbed_official	87:085cde657901	814
mbed_official	87:085cde657901	815	/** @defgroup FMC_SDRAM_CAS_Latency
mbed_official	87:085cde657901	816	* @{
mbed_official	87:085cde657901	817	*/
mbed_official	87:085cde657901	818	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
mbed_official	87:085cde657901	819	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
mbed_official	87:085cde657901	820	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
mbed_official	87:085cde657901	821
mbed_official	87:085cde657901	822	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
mbed_official	87:085cde657901	823	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
mbed_official	87:085cde657901	824	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
mbed_official	87:085cde657901	825	/**
mbed_official	87:085cde657901	826	* @}
mbed_official	87:085cde657901	827	*/
mbed_official	87:085cde657901	828
mbed_official	87:085cde657901	829	/** @defgroup FMC_SDRAM_Write_Protection
mbed_official	87:085cde657901	830	* @{
mbed_official	87:085cde657901	831	*/
mbed_official	87:085cde657901	832	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	833	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
mbed_official	87:085cde657901	834
mbed_official	87:085cde657901	835	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
mbed_official	87:085cde657901	836	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
mbed_official	87:085cde657901	837	/**
mbed_official	87:085cde657901	838	* @}
mbed_official	87:085cde657901	839	*/
mbed_official	87:085cde657901	840
mbed_official	87:085cde657901	841	/** @defgroup FMC_SDRAM_Clock_Period
mbed_official	87:085cde657901	842	* @{
mbed_official	87:085cde657901	843	*/
mbed_official	87:085cde657901	844	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	845	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
mbed_official	87:085cde657901	846	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
mbed_official	87:085cde657901	847
mbed_official	87:085cde657901	848	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
mbed_official	87:085cde657901	849	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
mbed_official	87:085cde657901	850	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
mbed_official	87:085cde657901	851	/**
mbed_official	87:085cde657901	852	* @}
mbed_official	87:085cde657901	853	*/
mbed_official	87:085cde657901	854
mbed_official	87:085cde657901	855	/** @defgroup FMC_SDRAM_Read_Burst
mbed_official	87:085cde657901	856	* @{
mbed_official	87:085cde657901	857	*/
mbed_official	87:085cde657901	858	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	859	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
mbed_official	87:085cde657901	860
mbed_official	87:085cde657901	861	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
mbed_official	87:085cde657901	862	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
mbed_official	87:085cde657901	863	/**
mbed_official	87:085cde657901	864	* @}
mbed_official	87:085cde657901	865	*/
mbed_official	87:085cde657901	866
mbed_official	87:085cde657901	867	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
mbed_official	87:085cde657901	868	* @{
mbed_official	87:085cde657901	869	*/
mbed_official	87:085cde657901	870	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
mbed_official	87:085cde657901	871	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
mbed_official	87:085cde657901	872	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
mbed_official	87:085cde657901	873
mbed_official	87:085cde657901	874	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
mbed_official	87:085cde657901	875	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
mbed_official	87:085cde657901	876	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
mbed_official	87:085cde657901	877	/**
mbed_official	87:085cde657901	878	* @}
mbed_official	87:085cde657901	879	*/
mbed_official	87:085cde657901	880
mbed_official	87:085cde657901	881	/** @defgroup FMC_SDRAM_LoadToActive_Delay
mbed_official	87:085cde657901	882	* @{
mbed_official	87:085cde657901	883	*/
mbed_official	87:085cde657901	884	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	87:085cde657901	885	/**
mbed_official	87:085cde657901	886	* @}
mbed_official	87:085cde657901	887	*/
mbed_official	87:085cde657901	888
mbed_official	87:085cde657901	889	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
mbed_official	87:085cde657901	890	* @{
mbed_official	87:085cde657901	891	*/
mbed_official	87:085cde657901	892	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	87:085cde657901	893	/**
mbed_official	87:085cde657901	894	* @}
mbed_official	87:085cde657901	895	*/
mbed_official	87:085cde657901	896
mbed_official	87:085cde657901	897	/** @defgroup FMC_SDRAM_SelfRefresh_Time
mbed_official	87:085cde657901	898	* @{
mbed_official	87:085cde657901	899	*/
mbed_official	87:085cde657901	900	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	87:085cde657901	901	/**
mbed_official	87:085cde657901	902	* @}
mbed_official	87:085cde657901	903	*/
mbed_official	87:085cde657901	904
mbed_official	87:085cde657901	905	/** @defgroup FMC_SDRAM_RowCycle_Delay
mbed_official	87:085cde657901	906	* @{
mbed_official	87:085cde657901	907	*/
mbed_official	87:085cde657901	908	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	87:085cde657901	909	/**
mbed_official	87:085cde657901	910	* @}
mbed_official	87:085cde657901	911	*/
mbed_official	87:085cde657901	912
mbed_official	87:085cde657901	913	/** @defgroup FMC_SDRAM_Write_Recovery_Time
mbed_official	87:085cde657901	914	* @{
mbed_official	87:085cde657901	915	*/
mbed_official	87:085cde657901	916	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	87:085cde657901	917	/**
mbed_official	87:085cde657901	918	* @}
mbed_official	87:085cde657901	919	*/
mbed_official	87:085cde657901	920
mbed_official	87:085cde657901	921	/** @defgroup FMC_SDRAM_RP_Delay
mbed_official	87:085cde657901	922	* @{
mbed_official	87:085cde657901	923	*/
mbed_official	87:085cde657901	924	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	87:085cde657901	925	/**
mbed_official	87:085cde657901	926	* @}
mbed_official	87:085cde657901	927	*/
mbed_official	87:085cde657901	928
mbed_official	87:085cde657901	929	/** @defgroup FMC_SDRAM_RCD_Delay
mbed_official	87:085cde657901	930	* @{
mbed_official	87:085cde657901	931	*/
mbed_official	87:085cde657901	932	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	87:085cde657901	933
mbed_official	87:085cde657901	934	/**
mbed_official	87:085cde657901	935	* @}
mbed_official	87:085cde657901	936	*/
mbed_official	87:085cde657901	937
mbed_official	87:085cde657901	938	/** @defgroup FMC_SDRAM_Command_Mode
mbed_official	87:085cde657901	939	* @{
mbed_official	87:085cde657901	940	*/
mbed_official	87:085cde657901	941	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	942	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
mbed_official	87:085cde657901	943	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
mbed_official	87:085cde657901	944	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
mbed_official	87:085cde657901	945	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
mbed_official	87:085cde657901	946	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
mbed_official	87:085cde657901	947	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
mbed_official	87:085cde657901	948
mbed_official	87:085cde657901	949	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
mbed_official	87:085cde657901	950	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
mbed_official	87:085cde657901	951	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
mbed_official	87:085cde657901	952	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
mbed_official	87:085cde657901	953	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
mbed_official	87:085cde657901	954	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
mbed_official	87:085cde657901	955	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
mbed_official	87:085cde657901	956	/**
mbed_official	87:085cde657901	957	* @}
mbed_official	87:085cde657901	958	*/
mbed_official	87:085cde657901	959
mbed_official	87:085cde657901	960	/** @defgroup FMC_SDRAM_Command_Target
mbed_official	87:085cde657901	961	* @{
mbed_official	87:085cde657901	962	*/
mbed_official	87:085cde657901	963	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
mbed_official	87:085cde657901	964	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
mbed_official	87:085cde657901	965	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
mbed_official	87:085cde657901	966
mbed_official	87:085cde657901	967	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
mbed_official	87:085cde657901	968	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
mbed_official	87:085cde657901	969	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
mbed_official	87:085cde657901	970	/**
mbed_official	87:085cde657901	971	* @}
mbed_official	87:085cde657901	972	*/
mbed_official	87:085cde657901	973
mbed_official	87:085cde657901	974	/** @defgroup FMC_SDRAM_AutoRefresh_Number
mbed_official	87:085cde657901	975	* @{
mbed_official	87:085cde657901	976	*/
mbed_official	87:085cde657901	977	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
mbed_official	87:085cde657901	978	/**
mbed_official	87:085cde657901	979	* @}
mbed_official	87:085cde657901	980	*/
mbed_official	87:085cde657901	981
mbed_official	87:085cde657901	982	/** @defgroup FMC_SDRAM_ModeRegister_Definition
mbed_official	87:085cde657901	983	* @{
mbed_official	87:085cde657901	984	*/
mbed_official	87:085cde657901	985	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
mbed_official	87:085cde657901	986	/**
mbed_official	87:085cde657901	987	* @}
mbed_official	87:085cde657901	988	*/
mbed_official	87:085cde657901	989
mbed_official	87:085cde657901	990	/** @defgroup FMC_SDRAM_Refresh_rate
mbed_official	87:085cde657901	991	* @{
mbed_official	87:085cde657901	992	*/
mbed_official	87:085cde657901	993	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
mbed_official	87:085cde657901	994	/**
mbed_official	87:085cde657901	995	* @}
mbed_official	87:085cde657901	996	*/
mbed_official	87:085cde657901	997
mbed_official	87:085cde657901	998	/** @defgroup FMC_SDRAM_Mode_Status
mbed_official	87:085cde657901	999	* @{
mbed_official	87:085cde657901	1000	*/
mbed_official	87:085cde657901	1001	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	87:085cde657901	1002	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
mbed_official	87:085cde657901	1003	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
mbed_official	87:085cde657901	1004	/**
mbed_official	87:085cde657901	1005	* @}
mbed_official	87:085cde657901	1006	*/
mbed_official	87:085cde657901	1007
mbed_official	87:085cde657901	1008	/** @defgroup FMC_NORSRAM_Device_Instance
mbed_official	87:085cde657901	1009	* @{
mbed_official	87:085cde657901	1010	*/
mbed_official	87:085cde657901	1011	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
mbed_official	87:085cde657901	1012	/**
mbed_official	87:085cde657901	1013	* @}
mbed_official	87:085cde657901	1014	*/
mbed_official	87:085cde657901	1015
mbed_official	87:085cde657901	1016	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
mbed_official	87:085cde657901	1017	* @{
mbed_official	87:085cde657901	1018	*/
mbed_official	87:085cde657901	1019	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	87:085cde657901	1020	/**
mbed_official	87:085cde657901	1021	* @}
mbed_official	87:085cde657901	1022	*/
mbed_official	87:085cde657901	1023
mbed_official	87:085cde657901	1024	/** @defgroup FMC_NAND_Device_Instance
mbed_official	87:085cde657901	1025	* @{
mbed_official	87:085cde657901	1026	*/
mbed_official	87:085cde657901	1027	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
mbed_official	87:085cde657901	1028	/**
mbed_official	87:085cde657901	1029	* @}
mbed_official	87:085cde657901	1030	*/
mbed_official	87:085cde657901	1031
mbed_official	87:085cde657901	1032	/** @defgroup FMC_PCCARD_Device_Instance
mbed_official	87:085cde657901	1033	* @{
mbed_official	87:085cde657901	1034	*/
mbed_official	87:085cde657901	1035	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
mbed_official	87:085cde657901	1036	/**
mbed_official	87:085cde657901	1037	* @}
mbed_official	87:085cde657901	1038	*/
mbed_official	87:085cde657901	1039
mbed_official	87:085cde657901	1040	/** @defgroup FMC_SDRAM_Device_Instance
mbed_official	87:085cde657901	1041	* @{
mbed_official	87:085cde657901	1042	*/
mbed_official	87:085cde657901	1043	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
mbed_official	87:085cde657901	1044	/**
mbed_official	87:085cde657901	1045	* @}
mbed_official	87:085cde657901	1046	*/
mbed_official	87:085cde657901	1047
mbed_official	87:085cde657901	1048	/**
mbed_official	87:085cde657901	1049	* @}
mbed_official	87:085cde657901	1050	*/
mbed_official	87:085cde657901	1051
mbed_official	87:085cde657901	1052	/** @defgroup FMC_Interrupt_definition
mbed_official	87:085cde657901	1053	* @brief FMC Interrupt definition
mbed_official	87:085cde657901	1054	* @{
mbed_official	87:085cde657901	1055	*/
mbed_official	87:085cde657901	1056	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	87:085cde657901	1057	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	87:085cde657901	1058	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	87:085cde657901	1059	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	87:085cde657901	1060
mbed_official	87:085cde657901	1061	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	87:085cde657901	1062
mbed_official	87:085cde657901	1063	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
mbed_official	87:085cde657901	1064	((IT) == FMC_IT_LEVEL) \|\| \
mbed_official	87:085cde657901	1065	((IT) == FMC_IT_FALLING_EDGE) \|\| \
mbed_official	87:085cde657901	1066	((IT) == FMC_IT_REFRESH_ERROR))
mbed_official	87:085cde657901	1067	/**
mbed_official	87:085cde657901	1068	* @}
mbed_official	87:085cde657901	1069	*/
mbed_official	87:085cde657901	1070
mbed_official	87:085cde657901	1071	/** @defgroup FMC_Flag_definition
mbed_official	87:085cde657901	1072	* @brief FMC Flag definition
mbed_official	87:085cde657901	1073	* @{
mbed_official	87:085cde657901	1074	*/
mbed_official	87:085cde657901	1075	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	87:085cde657901	1076	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	87:085cde657901	1077	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	87:085cde657901	1078	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	87:085cde657901	1079	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
mbed_official	87:085cde657901	1080	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
mbed_official	87:085cde657901	1081	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
mbed_official	87:085cde657901	1082
mbed_official	87:085cde657901	1083	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
mbed_official	87:085cde657901	1084	((FLAG) == FMC_FLAG_LEVEL) \|\| \
mbed_official	87:085cde657901	1085	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
mbed_official	87:085cde657901	1086	((FLAG) == FMC_FLAG_FEMPT) \|\| \
mbed_official	87:085cde657901	1087	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
mbed_official	87:085cde657901	1088	((FLAG) == FMC_SDRAM_FLAG_BUSY))
mbed_official	87:085cde657901	1089
mbed_official	87:085cde657901	1090	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official	87:085cde657901	1091	/**
mbed_official	87:085cde657901	1092	* @}
mbed_official	87:085cde657901	1093	*/
mbed_official	87:085cde657901	1094
mbed_official	87:085cde657901	1095	/* Exported macro ------------------------------------------------------------*/
mbed_official	87:085cde657901	1096
mbed_official	87:085cde657901	1097	/** @defgroup FMC_NOR_Macros
mbed_official	87:085cde657901	1098	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	87:085cde657901	1099	* @{
mbed_official	87:085cde657901	1100	*/
mbed_official	87:085cde657901	1101
mbed_official	87:085cde657901	1102	/**
mbed_official	87:085cde657901	1103	* @brief Enable the NORSRAM device access.
mbed_official	87:085cde657901	1104	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	87:085cde657901	1105	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	87:085cde657901	1106	* @retval None
mbed_official	87:085cde657901	1107	*/
mbed_official	87:085cde657901	1108	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
mbed_official	87:085cde657901	1109
mbed_official	87:085cde657901	1110	/**
mbed_official	87:085cde657901	1111	* @brief Disable the NORSRAM device access.
mbed_official	87:085cde657901	1112	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	87:085cde657901	1113	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	87:085cde657901	1114	* @retval None
mbed_official	87:085cde657901	1115	*/
mbed_official	87:085cde657901	1116	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official	87:085cde657901	1117
mbed_official	87:085cde657901	1118	/**
mbed_official	87:085cde657901	1119	* @}
mbed_official	87:085cde657901	1120	*/
mbed_official	87:085cde657901	1121
mbed_official	87:085cde657901	1122	/** @defgroup FMC_NAND_Macros
mbed_official	87:085cde657901	1123	* @brief macros to handle NAND device enable/disable
mbed_official	87:085cde657901	1124	* @{
mbed_official	87:085cde657901	1125	*/
mbed_official	87:085cde657901	1126
mbed_official	87:085cde657901	1127	/**
mbed_official	87:085cde657901	1128	* @brief Enable the NAND device access.
mbed_official	87:085cde657901	1129	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	87:085cde657901	1130	* @param __BANK__: FMC_NAND Bank
mbed_official	87:085cde657901	1131	* @retval None
mbed_official	87:085cde657901	1132	*/
mbed_official	87:085cde657901	1133	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
mbed_official	87:085cde657901	1134	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
mbed_official	87:085cde657901	1135
mbed_official	87:085cde657901	1136	/**
mbed_official	87:085cde657901	1137	* @brief Disable the NAND device access.
mbed_official	87:085cde657901	1138	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	87:085cde657901	1139	* @param __BANK__: FMC_NAND Bank
mbed_official	87:085cde657901	1140	* @retval None
mbed_official	87:085cde657901	1141	*/
mbed_official	87:085cde657901	1142	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
mbed_official	87:085cde657901	1143	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
mbed_official	87:085cde657901	1144	/**
mbed_official	87:085cde657901	1145	* @}
mbed_official	87:085cde657901	1146	*/
mbed_official	87:085cde657901	1147
mbed_official	87:085cde657901	1148	/** @defgroup FMC_PCCARD_Macros
mbed_official	87:085cde657901	1149	* @brief macros to handle SRAM read/write operations
mbed_official	87:085cde657901	1150	* @{
mbed_official	87:085cde657901	1151	*/
mbed_official	87:085cde657901	1152
mbed_official	87:085cde657901	1153	/**
mbed_official	87:085cde657901	1154	* @brief Enable the PCCARD device access.
mbed_official	87:085cde657901	1155	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	87:085cde657901	1156	* @retval None
mbed_official	87:085cde657901	1157	*/
mbed_official	87:085cde657901	1158	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
mbed_official	87:085cde657901	1159
mbed_official	87:085cde657901	1160	/**
mbed_official	87:085cde657901	1161	* @brief Disable the PCCARD device access.
mbed_official	87:085cde657901	1162	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	87:085cde657901	1163	* @retval None
mbed_official	87:085cde657901	1164	*/
mbed_official	87:085cde657901	1165	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
mbed_official	87:085cde657901	1166	/**
mbed_official	87:085cde657901	1167	* @}
mbed_official	87:085cde657901	1168	*/
mbed_official	87:085cde657901	1169
mbed_official	87:085cde657901	1170	/** @defgroup FMC_Interrupt
mbed_official	87:085cde657901	1171	* @brief macros to handle FMC interrupts
mbed_official	87:085cde657901	1172	* @{
mbed_official	87:085cde657901	1173	*/
mbed_official	87:085cde657901	1174
mbed_official	87:085cde657901	1175	/**
mbed_official	87:085cde657901	1176	* @brief Enable the NAND device interrupt.
mbed_official	87:085cde657901	1177	* @param __INSTANCE__: FMC_NAND instance
mbed_official	87:085cde657901	1178	* @param __BANK__: FMC_NAND Bank
mbed_official	87:085cde657901	1179	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	87:085cde657901	1180	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1181	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	1182	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	1183	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	1184	* @retval None
mbed_official	87:085cde657901	1185	*/
mbed_official	87:085cde657901	1186	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
mbed_official	87:085cde657901	1187	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
mbed_official	87:085cde657901	1188
mbed_official	87:085cde657901	1189	/**
mbed_official	87:085cde657901	1190	* @brief Disable the NAND device interrupt.
mbed_official	87:085cde657901	1191	* @param __INSTANCE__: FMC_NAND handle
mbed_official	87:085cde657901	1192	* @param __BANK__: FMC_NAND Bank
mbed_official	87:085cde657901	1193	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	87:085cde657901	1194	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1195	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	1196	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	1197	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	1198	* @retval None
mbed_official	87:085cde657901	1199	*/
mbed_official	87:085cde657901	1200	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official	87:085cde657901	1201	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official	87:085cde657901	1202
mbed_official	87:085cde657901	1203	/**
mbed_official	87:085cde657901	1204	* @brief Get flag status of the NAND device.
mbed_official	87:085cde657901	1205	* @param __INSTANCE__: FMC_NAND handle
mbed_official	87:085cde657901	1206	* @param __BANK__: FMC_NAND Bank
mbed_official	87:085cde657901	1207	* @param __FLAG__: FMC_NAND flag
mbed_official	87:085cde657901	1208	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1209	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	1210	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	1211	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	1212	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	1213	* @retval The state of FLAG (SET or RESET).
mbed_official	87:085cde657901	1214	*/
mbed_official	87:085cde657901	1215	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official	87:085cde657901	1216	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official	87:085cde657901	1217	/**
mbed_official	87:085cde657901	1218	* @brief Clear flag status of the NAND device.
mbed_official	87:085cde657901	1219	* @param __INSTANCE__: FMC_NAND handle
mbed_official	87:085cde657901	1220	* @param __BANK__: FMC_NAND Bank
mbed_official	87:085cde657901	1221	* @param __FLAG__: FMC_NAND flag
mbed_official	87:085cde657901	1222	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1223	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	1224	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	1225	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	1226	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	1227	* @retval None
mbed_official	87:085cde657901	1228	*/
mbed_official	87:085cde657901	1229	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official	87:085cde657901	1230	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	87:085cde657901	1231	/**
mbed_official	87:085cde657901	1232	* @brief Enable the PCCARD device interrupt.
mbed_official	87:085cde657901	1233	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	87:085cde657901	1234	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	87:085cde657901	1235	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1236	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	1237	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	1238	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	1239	* @retval None
mbed_official	87:085cde657901	1240	*/
mbed_official	87:085cde657901	1241	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
mbed_official	87:085cde657901	1242
mbed_official	87:085cde657901	1243	/**
mbed_official	87:085cde657901	1244	* @brief Disable the PCCARD device interrupt.
mbed_official	87:085cde657901	1245	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	87:085cde657901	1246	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	87:085cde657901	1247	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1248	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	87:085cde657901	1249	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	87:085cde657901	1250	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	87:085cde657901	1251	* @retval None
mbed_official	87:085cde657901	1252	*/
mbed_official	87:085cde657901	1253	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official	87:085cde657901	1254
mbed_official	87:085cde657901	1255	/**
mbed_official	87:085cde657901	1256	* @brief Get flag status of the PCCARD device.
mbed_official	87:085cde657901	1257	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	87:085cde657901	1258	* @param __FLAG__: FMC_PCCARD flag
mbed_official	87:085cde657901	1259	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1260	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	1261	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	1262	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	1263	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	1264	* @retval The state of FLAG (SET or RESET).
mbed_official	87:085cde657901	1265	*/
mbed_official	87:085cde657901	1266	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official	87:085cde657901	1267
mbed_official	87:085cde657901	1268	/**
mbed_official	87:085cde657901	1269	* @brief Clear flag status of the PCCARD device.
mbed_official	87:085cde657901	1270	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	87:085cde657901	1271	* @param __FLAG__: FMC_PCCARD flag
mbed_official	87:085cde657901	1272	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1273	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	87:085cde657901	1274	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	87:085cde657901	1275	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	87:085cde657901	1276	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	87:085cde657901	1277	* @retval None
mbed_official	87:085cde657901	1278	*/
mbed_official	87:085cde657901	1279	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official	87:085cde657901	1280
mbed_official	87:085cde657901	1281	/**
mbed_official	87:085cde657901	1282	* @brief Enable the SDRAM device interrupt.
mbed_official	87:085cde657901	1283	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	87:085cde657901	1284	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	87:085cde657901	1285	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1286	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	87:085cde657901	1287	* @retval None
mbed_official	87:085cde657901	1288	*/
mbed_official	87:085cde657901	1289	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
mbed_official	87:085cde657901	1290
mbed_official	87:085cde657901	1291	/**
mbed_official	87:085cde657901	1292	* @brief Disable the SDRAM device interrupt.
mbed_official	87:085cde657901	1293	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	87:085cde657901	1294	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	87:085cde657901	1295	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1296	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	87:085cde657901	1297	* @retval None
mbed_official	87:085cde657901	1298	*/
mbed_official	87:085cde657901	1299	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
mbed_official	87:085cde657901	1300
mbed_official	87:085cde657901	1301	/**
mbed_official	87:085cde657901	1302	* @brief Get flag status of the SDRAM device.
mbed_official	87:085cde657901	1303	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	87:085cde657901	1304	* @param __FLAG__: FMC_SDRAM flag
mbed_official	87:085cde657901	1305	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1306	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
mbed_official	87:085cde657901	1307	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
mbed_official	87:085cde657901	1308	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
mbed_official	87:085cde657901	1309	* @retval The state of FLAG (SET or RESET).
mbed_official	87:085cde657901	1310	*/
mbed_official	87:085cde657901	1311	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
mbed_official	87:085cde657901	1312
mbed_official	87:085cde657901	1313	/**
mbed_official	87:085cde657901	1314	* @brief Clear flag status of the SDRAM device.
mbed_official	87:085cde657901	1315	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	87:085cde657901	1316	* @param __FLAG__: FMC_SDRAM flag
mbed_official	87:085cde657901	1317	* This parameter can be any combination of the following values:
mbed_official	87:085cde657901	1318	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
mbed_official	87:085cde657901	1319	* @retval None
mbed_official	87:085cde657901	1320	*/
mbed_official	87:085cde657901	1321	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
mbed_official	87:085cde657901	1322	/**
mbed_official	87:085cde657901	1323	* @}
mbed_official	87:085cde657901	1324	*/
mbed_official	87:085cde657901	1325
mbed_official	87:085cde657901	1326	/* Exported functions --------------------------------------------------------*/
mbed_official	87:085cde657901	1327
mbed_official	87:085cde657901	1328	/* FMC_NORSRAM Controller functions *******************************************/
mbed_official	87:085cde657901	1329	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	1330	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
mbed_official	87:085cde657901	1331	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	1332	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	87:085cde657901	1333	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	87:085cde657901	1334
mbed_official	87:085cde657901	1335	/* FMC_NORSRAM Control functions */
mbed_official	87:085cde657901	1336	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1337	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1338
mbed_official	87:085cde657901	1339	/* FMC_NAND Controller functions **********************************************/
mbed_official	87:085cde657901	1340	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	1341	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
mbed_official	87:085cde657901	1342	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	1343	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	1344	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1345
mbed_official	87:085cde657901	1346	/* FMC_NAND Control functions */
mbed_official	87:085cde657901	1347	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1348	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1349	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	87:085cde657901	1350
mbed_official	87:085cde657901	1351	/* FMC_PCCARD Controller functions ********************************************/
mbed_official	87:085cde657901	1352	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	1353	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
mbed_official	87:085cde657901	1354	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	87:085cde657901	1355	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	87:085cde657901	1356	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	87:085cde657901	1357	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
mbed_official	87:085cde657901	1358
mbed_official	87:085cde657901	1359	/* FMC_SDRAM Controller functions *********************************************/
mbed_official	87:085cde657901	1360	/* Initialization/de-initialization functions */
mbed_official	87:085cde657901	1361	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
mbed_official	87:085cde657901	1362	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	87:085cde657901	1363	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1364
mbed_official	87:085cde657901	1365	/* FMC_SDRAM Control functions */
mbed_official	87:085cde657901	1366	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1367	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1368	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
mbed_official	87:085cde657901	1369	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
mbed_official	87:085cde657901	1370	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
mbed_official	87:085cde657901	1371	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	87:085cde657901	1372
mbed_official	87:085cde657901	1373	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	87:085cde657901	1374	/**
mbed_official	87:085cde657901	1375	* @}
mbed_official	87:085cde657901	1376	*/
mbed_official	87:085cde657901	1377
mbed_official	87:085cde657901	1378	/**
mbed_official	87:085cde657901	1379	* @}
mbed_official	87:085cde657901	1380	*/
mbed_official	87:085cde657901	1381
mbed_official	87:085cde657901	1382	#ifdef __cplusplus
mbed_official	87:085cde657901	1383	}
mbed_official	87:085cde657901	1384	#endif
mbed_official	87:085cde657901	1385
mbed_official	87:085cde657901	1386	#endif /* __STM32F4xx_LL_FMC_H */
mbed_official	87:085cde657901	1387
mbed_official	87:085cde657901	1388	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
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Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@106:ced8cbb51063, 2014-02-26 (annotated)

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