mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_vref.h@320:be04b2b1e3f2, 2014-09-11 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 11 17:00:08 2014 +0100
- Revision:
- 320:be04b2b1e3f2
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_vref.h@149:1fb5f62b92bd
Synchronized with git revision c372035d60ac16c22e1313348a9e3f47293dc6b8
Full URL: https://github.com/mbedmicro/mbed/commit/c372035d60ac16c22e1313348a9e3f47293dc6b8/
Add derivative support to K64F and updates for MTS_GAMBIT
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_VREF_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_VREF_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 VREF |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Voltage Reference |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_VREF_TRM - VREF Trim Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_VREF_SC - VREF Status and Control Register |
mbed_official | 146:f64d43ff0c18 | 34 | * |
mbed_official | 146:f64d43ff0c18 | 35 | * - hw_vref_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 36 | */ |
mbed_official | 146:f64d43ff0c18 | 37 | |
mbed_official | 146:f64d43ff0c18 | 38 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 39 | //@{ |
mbed_official | 146:f64d43ff0c18 | 40 | #ifndef REGS_VREF_BASE |
mbed_official | 146:f64d43ff0c18 | 41 | #define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module. |
mbed_official | 146:f64d43ff0c18 | 42 | #define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF. |
mbed_official | 146:f64d43ff0c18 | 43 | #endif |
mbed_official | 146:f64d43ff0c18 | 44 | //@} |
mbed_official | 146:f64d43ff0c18 | 45 | |
mbed_official | 146:f64d43ff0c18 | 46 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 47 | // HW_VREF_TRM - VREF Trim Register |
mbed_official | 146:f64d43ff0c18 | 48 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 49 | |
mbed_official | 146:f64d43ff0c18 | 50 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 51 | /*! |
mbed_official | 146:f64d43ff0c18 | 52 | * @brief HW_VREF_TRM - VREF Trim Register (RW) |
mbed_official | 146:f64d43ff0c18 | 53 | * |
mbed_official | 146:f64d43ff0c18 | 54 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 55 | * |
mbed_official | 146:f64d43ff0c18 | 56 | * This register contains bits that contain the trim data for the Voltage |
mbed_official | 146:f64d43ff0c18 | 57 | * Reference. |
mbed_official | 146:f64d43ff0c18 | 58 | */ |
mbed_official | 146:f64d43ff0c18 | 59 | typedef union _hw_vref_trm |
mbed_official | 146:f64d43ff0c18 | 60 | { |
mbed_official | 146:f64d43ff0c18 | 61 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 62 | struct _hw_vref_trm_bitfields |
mbed_official | 146:f64d43ff0c18 | 63 | { |
mbed_official | 146:f64d43ff0c18 | 64 | uint8_t TRIM : 6; //!< [5:0] Trim bits |
mbed_official | 146:f64d43ff0c18 | 65 | uint8_t CHOPEN : 1; //!< [6] Chop oscillator enable. When set, |
mbed_official | 146:f64d43ff0c18 | 66 | //! internal chopping operation is enabled and the internal analog offset will |
mbed_official | 146:f64d43ff0c18 | 67 | //! be minimized. |
mbed_official | 146:f64d43ff0c18 | 68 | uint8_t RESERVED0 : 1; //!< [7] |
mbed_official | 146:f64d43ff0c18 | 69 | } B; |
mbed_official | 146:f64d43ff0c18 | 70 | } hw_vref_trm_t; |
mbed_official | 146:f64d43ff0c18 | 71 | #endif |
mbed_official | 146:f64d43ff0c18 | 72 | |
mbed_official | 146:f64d43ff0c18 | 73 | /*! |
mbed_official | 146:f64d43ff0c18 | 74 | * @name Constants and macros for entire VREF_TRM register |
mbed_official | 146:f64d43ff0c18 | 75 | */ |
mbed_official | 146:f64d43ff0c18 | 76 | //@{ |
mbed_official | 146:f64d43ff0c18 | 77 | #define HW_VREF_TRM_ADDR (REGS_VREF_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 78 | |
mbed_official | 146:f64d43ff0c18 | 79 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 80 | #define HW_VREF_TRM (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR) |
mbed_official | 146:f64d43ff0c18 | 81 | #define HW_VREF_TRM_RD() (HW_VREF_TRM.U) |
mbed_official | 146:f64d43ff0c18 | 82 | #define HW_VREF_TRM_WR(v) (HW_VREF_TRM.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 83 | #define HW_VREF_TRM_SET(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 84 | #define HW_VREF_TRM_CLR(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_VREF_TRM_TOG(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 86 | #endif |
mbed_official | 146:f64d43ff0c18 | 87 | //@} |
mbed_official | 146:f64d43ff0c18 | 88 | |
mbed_official | 146:f64d43ff0c18 | 89 | /* |
mbed_official | 146:f64d43ff0c18 | 90 | * Constants & macros for individual VREF_TRM bitfields |
mbed_official | 146:f64d43ff0c18 | 91 | */ |
mbed_official | 146:f64d43ff0c18 | 92 | |
mbed_official | 146:f64d43ff0c18 | 93 | /*! |
mbed_official | 146:f64d43ff0c18 | 94 | * @name Register VREF_TRM, field TRIM[5:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 95 | * |
mbed_official | 146:f64d43ff0c18 | 96 | * These bits change the resulting VREF by approximately +/- 0.5 mV for each |
mbed_official | 146:f64d43ff0c18 | 97 | * step. Min = minimum and max = maximum voltage reference output. For minimum and |
mbed_official | 146:f64d43ff0c18 | 98 | * maximum voltage reference output values, refer to the Data Sheet for this chip. |
mbed_official | 146:f64d43ff0c18 | 99 | * |
mbed_official | 146:f64d43ff0c18 | 100 | * Values: |
mbed_official | 146:f64d43ff0c18 | 101 | * - 000000 - Min |
mbed_official | 146:f64d43ff0c18 | 102 | * - 111111 - Max |
mbed_official | 146:f64d43ff0c18 | 103 | */ |
mbed_official | 146:f64d43ff0c18 | 104 | //@{ |
mbed_official | 146:f64d43ff0c18 | 105 | #define BP_VREF_TRM_TRIM (0U) //!< Bit position for VREF_TRM_TRIM. |
mbed_official | 146:f64d43ff0c18 | 106 | #define BM_VREF_TRM_TRIM (0x3FU) //!< Bit mask for VREF_TRM_TRIM. |
mbed_official | 146:f64d43ff0c18 | 107 | #define BS_VREF_TRM_TRIM (6U) //!< Bit field size in bits for VREF_TRM_TRIM. |
mbed_official | 146:f64d43ff0c18 | 108 | |
mbed_official | 146:f64d43ff0c18 | 109 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 110 | //! @brief Read current value of the VREF_TRM_TRIM field. |
mbed_official | 146:f64d43ff0c18 | 111 | #define BR_VREF_TRM_TRIM (HW_VREF_TRM.B.TRIM) |
mbed_official | 146:f64d43ff0c18 | 112 | #endif |
mbed_official | 146:f64d43ff0c18 | 113 | |
mbed_official | 146:f64d43ff0c18 | 114 | //! @brief Format value for bitfield VREF_TRM_TRIM. |
mbed_official | 146:f64d43ff0c18 | 115 | #define BF_VREF_TRM_TRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM) |
mbed_official | 146:f64d43ff0c18 | 116 | |
mbed_official | 146:f64d43ff0c18 | 117 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 118 | //! @brief Set the TRIM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 119 | #define BW_VREF_TRM_TRIM(v) (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v))) |
mbed_official | 146:f64d43ff0c18 | 120 | #endif |
mbed_official | 146:f64d43ff0c18 | 121 | //@} |
mbed_official | 146:f64d43ff0c18 | 122 | |
mbed_official | 146:f64d43ff0c18 | 123 | /*! |
mbed_official | 146:f64d43ff0c18 | 124 | * @name Register VREF_TRM, field CHOPEN[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 125 | * |
mbed_official | 146:f64d43ff0c18 | 126 | * This bit is set during factory trimming of the VREF voltage. This bit should |
mbed_official | 146:f64d43ff0c18 | 127 | * be written to 1 to achieve the performance stated in the data sheet. |
mbed_official | 146:f64d43ff0c18 | 128 | * |
mbed_official | 146:f64d43ff0c18 | 129 | * Values: |
mbed_official | 146:f64d43ff0c18 | 130 | * - 0 - Chop oscillator is disabled. |
mbed_official | 146:f64d43ff0c18 | 131 | * - 1 - Chop oscillator is enabled. |
mbed_official | 146:f64d43ff0c18 | 132 | */ |
mbed_official | 146:f64d43ff0c18 | 133 | //@{ |
mbed_official | 146:f64d43ff0c18 | 134 | #define BP_VREF_TRM_CHOPEN (6U) //!< Bit position for VREF_TRM_CHOPEN. |
mbed_official | 146:f64d43ff0c18 | 135 | #define BM_VREF_TRM_CHOPEN (0x40U) //!< Bit mask for VREF_TRM_CHOPEN. |
mbed_official | 146:f64d43ff0c18 | 136 | #define BS_VREF_TRM_CHOPEN (1U) //!< Bit field size in bits for VREF_TRM_CHOPEN. |
mbed_official | 146:f64d43ff0c18 | 137 | |
mbed_official | 146:f64d43ff0c18 | 138 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 139 | //! @brief Read current value of the VREF_TRM_CHOPEN field. |
mbed_official | 146:f64d43ff0c18 | 140 | #define BR_VREF_TRM_CHOPEN (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN)) |
mbed_official | 146:f64d43ff0c18 | 141 | #endif |
mbed_official | 146:f64d43ff0c18 | 142 | |
mbed_official | 146:f64d43ff0c18 | 143 | //! @brief Format value for bitfield VREF_TRM_CHOPEN. |
mbed_official | 146:f64d43ff0c18 | 144 | #define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN) |
mbed_official | 146:f64d43ff0c18 | 145 | |
mbed_official | 146:f64d43ff0c18 | 146 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 147 | //! @brief Set the CHOPEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 148 | #define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 149 | #endif |
mbed_official | 146:f64d43ff0c18 | 150 | //@} |
mbed_official | 146:f64d43ff0c18 | 151 | |
mbed_official | 146:f64d43ff0c18 | 152 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 153 | // HW_VREF_SC - VREF Status and Control Register |
mbed_official | 146:f64d43ff0c18 | 154 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 155 | |
mbed_official | 146:f64d43ff0c18 | 156 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 157 | /*! |
mbed_official | 146:f64d43ff0c18 | 158 | * @brief HW_VREF_SC - VREF Status and Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 159 | * |
mbed_official | 146:f64d43ff0c18 | 160 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 161 | * |
mbed_official | 146:f64d43ff0c18 | 162 | * This register contains the control bits used to enable the internal voltage |
mbed_official | 146:f64d43ff0c18 | 163 | * reference and to select the buffer mode to be used. |
mbed_official | 146:f64d43ff0c18 | 164 | */ |
mbed_official | 146:f64d43ff0c18 | 165 | typedef union _hw_vref_sc |
mbed_official | 146:f64d43ff0c18 | 166 | { |
mbed_official | 146:f64d43ff0c18 | 167 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 168 | struct _hw_vref_sc_bitfields |
mbed_official | 146:f64d43ff0c18 | 169 | { |
mbed_official | 146:f64d43ff0c18 | 170 | uint8_t MODE_LV : 2; //!< [1:0] Buffer Mode selection |
mbed_official | 146:f64d43ff0c18 | 171 | uint8_t VREFST : 1; //!< [2] Internal Voltage Reference stable |
mbed_official | 146:f64d43ff0c18 | 172 | uint8_t RESERVED0 : 2; //!< [4:3] |
mbed_official | 146:f64d43ff0c18 | 173 | uint8_t ICOMPEN : 1; //!< [5] Second order curvature compensation |
mbed_official | 146:f64d43ff0c18 | 174 | //! enable |
mbed_official | 146:f64d43ff0c18 | 175 | uint8_t REGEN : 1; //!< [6] Regulator enable |
mbed_official | 146:f64d43ff0c18 | 176 | uint8_t VREFEN : 1; //!< [7] Internal Voltage Reference enable |
mbed_official | 146:f64d43ff0c18 | 177 | } B; |
mbed_official | 146:f64d43ff0c18 | 178 | } hw_vref_sc_t; |
mbed_official | 146:f64d43ff0c18 | 179 | #endif |
mbed_official | 146:f64d43ff0c18 | 180 | |
mbed_official | 146:f64d43ff0c18 | 181 | /*! |
mbed_official | 146:f64d43ff0c18 | 182 | * @name Constants and macros for entire VREF_SC register |
mbed_official | 146:f64d43ff0c18 | 183 | */ |
mbed_official | 146:f64d43ff0c18 | 184 | //@{ |
mbed_official | 146:f64d43ff0c18 | 185 | #define HW_VREF_SC_ADDR (REGS_VREF_BASE + 0x1U) |
mbed_official | 146:f64d43ff0c18 | 186 | |
mbed_official | 146:f64d43ff0c18 | 187 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 188 | #define HW_VREF_SC (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR) |
mbed_official | 146:f64d43ff0c18 | 189 | #define HW_VREF_SC_RD() (HW_VREF_SC.U) |
mbed_official | 146:f64d43ff0c18 | 190 | #define HW_VREF_SC_WR(v) (HW_VREF_SC.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 191 | #define HW_VREF_SC_SET(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 192 | #define HW_VREF_SC_CLR(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 193 | #define HW_VREF_SC_TOG(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 194 | #endif |
mbed_official | 146:f64d43ff0c18 | 195 | //@} |
mbed_official | 146:f64d43ff0c18 | 196 | |
mbed_official | 146:f64d43ff0c18 | 197 | /* |
mbed_official | 146:f64d43ff0c18 | 198 | * Constants & macros for individual VREF_SC bitfields |
mbed_official | 146:f64d43ff0c18 | 199 | */ |
mbed_official | 146:f64d43ff0c18 | 200 | |
mbed_official | 146:f64d43ff0c18 | 201 | /*! |
mbed_official | 146:f64d43ff0c18 | 202 | * @name Register VREF_SC, field MODE_LV[1:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 203 | * |
mbed_official | 146:f64d43ff0c18 | 204 | * These bits select the buffer modes for the Voltage Reference module. |
mbed_official | 146:f64d43ff0c18 | 205 | * |
mbed_official | 146:f64d43ff0c18 | 206 | * Values: |
mbed_official | 146:f64d43ff0c18 | 207 | * - 00 - Bandgap on only, for stabilization and startup |
mbed_official | 146:f64d43ff0c18 | 208 | * - 01 - High power buffer mode enabled |
mbed_official | 146:f64d43ff0c18 | 209 | * - 10 - Low-power buffer mode enabled |
mbed_official | 146:f64d43ff0c18 | 210 | * - 11 - Reserved |
mbed_official | 146:f64d43ff0c18 | 211 | */ |
mbed_official | 146:f64d43ff0c18 | 212 | //@{ |
mbed_official | 146:f64d43ff0c18 | 213 | #define BP_VREF_SC_MODE_LV (0U) //!< Bit position for VREF_SC_MODE_LV. |
mbed_official | 146:f64d43ff0c18 | 214 | #define BM_VREF_SC_MODE_LV (0x03U) //!< Bit mask for VREF_SC_MODE_LV. |
mbed_official | 146:f64d43ff0c18 | 215 | #define BS_VREF_SC_MODE_LV (2U) //!< Bit field size in bits for VREF_SC_MODE_LV. |
mbed_official | 146:f64d43ff0c18 | 216 | |
mbed_official | 146:f64d43ff0c18 | 217 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 218 | //! @brief Read current value of the VREF_SC_MODE_LV field. |
mbed_official | 146:f64d43ff0c18 | 219 | #define BR_VREF_SC_MODE_LV (HW_VREF_SC.B.MODE_LV) |
mbed_official | 146:f64d43ff0c18 | 220 | #endif |
mbed_official | 146:f64d43ff0c18 | 221 | |
mbed_official | 146:f64d43ff0c18 | 222 | //! @brief Format value for bitfield VREF_SC_MODE_LV. |
mbed_official | 146:f64d43ff0c18 | 223 | #define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV) |
mbed_official | 146:f64d43ff0c18 | 224 | |
mbed_official | 146:f64d43ff0c18 | 225 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 226 | //! @brief Set the MODE_LV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 227 | #define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v))) |
mbed_official | 146:f64d43ff0c18 | 228 | #endif |
mbed_official | 146:f64d43ff0c18 | 229 | //@} |
mbed_official | 146:f64d43ff0c18 | 230 | |
mbed_official | 146:f64d43ff0c18 | 231 | /*! |
mbed_official | 146:f64d43ff0c18 | 232 | * @name Register VREF_SC, field VREFST[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 233 | * |
mbed_official | 146:f64d43ff0c18 | 234 | * This bit indicates that the bandgap reference within the Voltage Reference |
mbed_official | 146:f64d43ff0c18 | 235 | * module has completed its startup and stabilization. |
mbed_official | 146:f64d43ff0c18 | 236 | * |
mbed_official | 146:f64d43ff0c18 | 237 | * Values: |
mbed_official | 146:f64d43ff0c18 | 238 | * - 0 - The module is disabled or not stable. |
mbed_official | 146:f64d43ff0c18 | 239 | * - 1 - The module is stable. |
mbed_official | 146:f64d43ff0c18 | 240 | */ |
mbed_official | 146:f64d43ff0c18 | 241 | //@{ |
mbed_official | 146:f64d43ff0c18 | 242 | #define BP_VREF_SC_VREFST (2U) //!< Bit position for VREF_SC_VREFST. |
mbed_official | 146:f64d43ff0c18 | 243 | #define BM_VREF_SC_VREFST (0x04U) //!< Bit mask for VREF_SC_VREFST. |
mbed_official | 146:f64d43ff0c18 | 244 | #define BS_VREF_SC_VREFST (1U) //!< Bit field size in bits for VREF_SC_VREFST. |
mbed_official | 146:f64d43ff0c18 | 245 | |
mbed_official | 146:f64d43ff0c18 | 246 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 247 | //! @brief Read current value of the VREF_SC_VREFST field. |
mbed_official | 146:f64d43ff0c18 | 248 | #define BR_VREF_SC_VREFST (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST)) |
mbed_official | 146:f64d43ff0c18 | 249 | #endif |
mbed_official | 146:f64d43ff0c18 | 250 | //@} |
mbed_official | 146:f64d43ff0c18 | 251 | |
mbed_official | 146:f64d43ff0c18 | 252 | /*! |
mbed_official | 146:f64d43ff0c18 | 253 | * @name Register VREF_SC, field ICOMPEN[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 254 | * |
mbed_official | 146:f64d43ff0c18 | 255 | * This bit is set during factory trimming of the VREF voltage. This bit should |
mbed_official | 146:f64d43ff0c18 | 256 | * be written to 1 to achieve the performance stated in the data sheet. |
mbed_official | 146:f64d43ff0c18 | 257 | * |
mbed_official | 146:f64d43ff0c18 | 258 | * Values: |
mbed_official | 146:f64d43ff0c18 | 259 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 260 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 261 | */ |
mbed_official | 146:f64d43ff0c18 | 262 | //@{ |
mbed_official | 146:f64d43ff0c18 | 263 | #define BP_VREF_SC_ICOMPEN (5U) //!< Bit position for VREF_SC_ICOMPEN. |
mbed_official | 146:f64d43ff0c18 | 264 | #define BM_VREF_SC_ICOMPEN (0x20U) //!< Bit mask for VREF_SC_ICOMPEN. |
mbed_official | 146:f64d43ff0c18 | 265 | #define BS_VREF_SC_ICOMPEN (1U) //!< Bit field size in bits for VREF_SC_ICOMPEN. |
mbed_official | 146:f64d43ff0c18 | 266 | |
mbed_official | 146:f64d43ff0c18 | 267 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 268 | //! @brief Read current value of the VREF_SC_ICOMPEN field. |
mbed_official | 146:f64d43ff0c18 | 269 | #define BR_VREF_SC_ICOMPEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN)) |
mbed_official | 146:f64d43ff0c18 | 270 | #endif |
mbed_official | 146:f64d43ff0c18 | 271 | |
mbed_official | 146:f64d43ff0c18 | 272 | //! @brief Format value for bitfield VREF_SC_ICOMPEN. |
mbed_official | 146:f64d43ff0c18 | 273 | #define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN) |
mbed_official | 146:f64d43ff0c18 | 274 | |
mbed_official | 146:f64d43ff0c18 | 275 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 276 | //! @brief Set the ICOMPEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 277 | #define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 278 | #endif |
mbed_official | 146:f64d43ff0c18 | 279 | //@} |
mbed_official | 146:f64d43ff0c18 | 280 | |
mbed_official | 146:f64d43ff0c18 | 281 | /*! |
mbed_official | 146:f64d43ff0c18 | 282 | * @name Register VREF_SC, field REGEN[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 283 | * |
mbed_official | 146:f64d43ff0c18 | 284 | * This bit is used to enable the internal 1.75 V regulator to produce a |
mbed_official | 146:f64d43ff0c18 | 285 | * constant internal voltage supply in order to reduce the sensitivity to external |
mbed_official | 146:f64d43ff0c18 | 286 | * supply noise and variation. If it is desired to keep the regulator enabled in very |
mbed_official | 146:f64d43ff0c18 | 287 | * low power modes, refer to the Chip Configuration details for a description on |
mbed_official | 146:f64d43ff0c18 | 288 | * how this can be achieved. This bit is set during factory trimming of the VREF |
mbed_official | 146:f64d43ff0c18 | 289 | * voltage. This bit should be written to 1 to achieve the performance stated in |
mbed_official | 146:f64d43ff0c18 | 290 | * the data sheet. |
mbed_official | 146:f64d43ff0c18 | 291 | * |
mbed_official | 146:f64d43ff0c18 | 292 | * Values: |
mbed_official | 146:f64d43ff0c18 | 293 | * - 0 - Internal 1.75 V regulator is disabled. |
mbed_official | 146:f64d43ff0c18 | 294 | * - 1 - Internal 1.75 V regulator is enabled. |
mbed_official | 146:f64d43ff0c18 | 295 | */ |
mbed_official | 146:f64d43ff0c18 | 296 | //@{ |
mbed_official | 146:f64d43ff0c18 | 297 | #define BP_VREF_SC_REGEN (6U) //!< Bit position for VREF_SC_REGEN. |
mbed_official | 146:f64d43ff0c18 | 298 | #define BM_VREF_SC_REGEN (0x40U) //!< Bit mask for VREF_SC_REGEN. |
mbed_official | 146:f64d43ff0c18 | 299 | #define BS_VREF_SC_REGEN (1U) //!< Bit field size in bits for VREF_SC_REGEN. |
mbed_official | 146:f64d43ff0c18 | 300 | |
mbed_official | 146:f64d43ff0c18 | 301 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 302 | //! @brief Read current value of the VREF_SC_REGEN field. |
mbed_official | 146:f64d43ff0c18 | 303 | #define BR_VREF_SC_REGEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN)) |
mbed_official | 146:f64d43ff0c18 | 304 | #endif |
mbed_official | 146:f64d43ff0c18 | 305 | |
mbed_official | 146:f64d43ff0c18 | 306 | //! @brief Format value for bitfield VREF_SC_REGEN. |
mbed_official | 146:f64d43ff0c18 | 307 | #define BF_VREF_SC_REGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN) |
mbed_official | 146:f64d43ff0c18 | 308 | |
mbed_official | 146:f64d43ff0c18 | 309 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 310 | //! @brief Set the REGEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 311 | #define BW_VREF_SC_REGEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 312 | #endif |
mbed_official | 146:f64d43ff0c18 | 313 | //@} |
mbed_official | 146:f64d43ff0c18 | 314 | |
mbed_official | 146:f64d43ff0c18 | 315 | /*! |
mbed_official | 146:f64d43ff0c18 | 316 | * @name Register VREF_SC, field VREFEN[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 317 | * |
mbed_official | 146:f64d43ff0c18 | 318 | * This bit is used to enable the bandgap reference within the Voltage Reference |
mbed_official | 146:f64d43ff0c18 | 319 | * module. After the VREF is enabled, turning off the clock to the VREF module |
mbed_official | 146:f64d43ff0c18 | 320 | * via the corresponding clock gate register will not disable the VREF. VREF must |
mbed_official | 146:f64d43ff0c18 | 321 | * be disabled via this VREFEN bit. |
mbed_official | 146:f64d43ff0c18 | 322 | * |
mbed_official | 146:f64d43ff0c18 | 323 | * Values: |
mbed_official | 146:f64d43ff0c18 | 324 | * - 0 - The module is disabled. |
mbed_official | 146:f64d43ff0c18 | 325 | * - 1 - The module is enabled. |
mbed_official | 146:f64d43ff0c18 | 326 | */ |
mbed_official | 146:f64d43ff0c18 | 327 | //@{ |
mbed_official | 146:f64d43ff0c18 | 328 | #define BP_VREF_SC_VREFEN (7U) //!< Bit position for VREF_SC_VREFEN. |
mbed_official | 146:f64d43ff0c18 | 329 | #define BM_VREF_SC_VREFEN (0x80U) //!< Bit mask for VREF_SC_VREFEN. |
mbed_official | 146:f64d43ff0c18 | 330 | #define BS_VREF_SC_VREFEN (1U) //!< Bit field size in bits for VREF_SC_VREFEN. |
mbed_official | 146:f64d43ff0c18 | 331 | |
mbed_official | 146:f64d43ff0c18 | 332 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 333 | //! @brief Read current value of the VREF_SC_VREFEN field. |
mbed_official | 146:f64d43ff0c18 | 334 | #define BR_VREF_SC_VREFEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN)) |
mbed_official | 146:f64d43ff0c18 | 335 | #endif |
mbed_official | 146:f64d43ff0c18 | 336 | |
mbed_official | 146:f64d43ff0c18 | 337 | //! @brief Format value for bitfield VREF_SC_VREFEN. |
mbed_official | 146:f64d43ff0c18 | 338 | #define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN) |
mbed_official | 146:f64d43ff0c18 | 339 | |
mbed_official | 146:f64d43ff0c18 | 340 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 341 | //! @brief Set the VREFEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 342 | #define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 343 | #endif |
mbed_official | 146:f64d43ff0c18 | 344 | //@} |
mbed_official | 146:f64d43ff0c18 | 345 | |
mbed_official | 146:f64d43ff0c18 | 346 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 347 | // hw_vref_t - module struct |
mbed_official | 146:f64d43ff0c18 | 348 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 349 | /*! |
mbed_official | 146:f64d43ff0c18 | 350 | * @brief All VREF module registers. |
mbed_official | 146:f64d43ff0c18 | 351 | */ |
mbed_official | 146:f64d43ff0c18 | 352 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 353 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 354 | typedef struct _hw_vref |
mbed_official | 146:f64d43ff0c18 | 355 | { |
mbed_official | 146:f64d43ff0c18 | 356 | __IO hw_vref_trm_t TRM; //!< [0x0] VREF Trim Register |
mbed_official | 146:f64d43ff0c18 | 357 | __IO hw_vref_sc_t SC; //!< [0x1] VREF Status and Control Register |
mbed_official | 146:f64d43ff0c18 | 358 | } hw_vref_t; |
mbed_official | 146:f64d43ff0c18 | 359 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 360 | |
mbed_official | 146:f64d43ff0c18 | 361 | //! @brief Macro to access all VREF registers. |
mbed_official | 146:f64d43ff0c18 | 362 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 363 | //! use the '&' operator, like <code>&HW_VREF</code>. |
mbed_official | 146:f64d43ff0c18 | 364 | #define HW_VREF (*(hw_vref_t *) REGS_VREF_BASE) |
mbed_official | 146:f64d43ff0c18 | 365 | #endif |
mbed_official | 146:f64d43ff0c18 | 366 | |
mbed_official | 146:f64d43ff0c18 | 367 | #endif // __HW_VREF_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 368 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 369 | // EOF |