mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_crc.h@320:be04b2b1e3f2, 2014-09-11 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 11 17:00:08 2014 +0100
- Revision:
- 320:be04b2b1e3f2
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_crc.h@149:1fb5f62b92bd
Synchronized with git revision c372035d60ac16c22e1313348a9e3f47293dc6b8
Full URL: https://github.com/mbedmicro/mbed/commit/c372035d60ac16c22e1313348a9e3f47293dc6b8/
Add derivative support to K64F and updates for MTS_GAMBIT
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_CRC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_CRC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 CRC |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Cyclic Redundancy Check |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_CRC_DATAL - CRC_DATAL register. |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_CRC_DATAH - CRC_DATAH register. |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_CRC_DATALL - CRC_DATALL register. |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_CRC_DATALU - CRC_DATALU register. |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_CRC_DATAHL - CRC_DATAHL register. |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_CRC_DATAHU - CRC_DATAHU register. |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_CRC_DATA - CRC Data register |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_CRC_GPOLY - CRC Polynomial register |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_CRC_GPOLYL - CRC_GPOLYL register. |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_CRC_GPOLYH - CRC_GPOLYH register. |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_CRC_GPOLYLL - CRC_GPOLYLL register. |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_CRC_GPOLYLU - CRC_GPOLYLU register. |
mbed_official | 146:f64d43ff0c18 | 44 | * - HW_CRC_GPOLYHL - CRC_GPOLYHL register. |
mbed_official | 146:f64d43ff0c18 | 45 | * - HW_CRC_GPOLYHU - CRC_GPOLYHU register. |
mbed_official | 146:f64d43ff0c18 | 46 | * - HW_CRC_CTRL - CRC Control register |
mbed_official | 146:f64d43ff0c18 | 47 | * - HW_CRC_CTRLHU - CRC_CTRLHU register. |
mbed_official | 146:f64d43ff0c18 | 48 | * |
mbed_official | 146:f64d43ff0c18 | 49 | * - hw_crc_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 50 | */ |
mbed_official | 146:f64d43ff0c18 | 51 | |
mbed_official | 146:f64d43ff0c18 | 52 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 53 | //@{ |
mbed_official | 146:f64d43ff0c18 | 54 | #ifndef REGS_CRC_BASE |
mbed_official | 146:f64d43ff0c18 | 55 | #define HW_CRC_INSTANCE_COUNT (1U) //!< Number of instances of the CRC module. |
mbed_official | 146:f64d43ff0c18 | 56 | #define REGS_CRC_BASE (0x40032000U) //!< Base address for CRC. |
mbed_official | 146:f64d43ff0c18 | 57 | #endif |
mbed_official | 146:f64d43ff0c18 | 58 | //@} |
mbed_official | 146:f64d43ff0c18 | 59 | |
mbed_official | 146:f64d43ff0c18 | 60 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 61 | // HW_CRC_DATAL - CRC_DATAL register. |
mbed_official | 146:f64d43ff0c18 | 62 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 63 | |
mbed_official | 146:f64d43ff0c18 | 64 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 65 | /*! |
mbed_official | 146:f64d43ff0c18 | 66 | * @brief HW_CRC_DATAL - CRC_DATAL register. (RW) |
mbed_official | 146:f64d43ff0c18 | 67 | * |
mbed_official | 146:f64d43ff0c18 | 68 | * Reset value: 0xFFFFU |
mbed_official | 146:f64d43ff0c18 | 69 | */ |
mbed_official | 146:f64d43ff0c18 | 70 | typedef union _hw_crc_datal |
mbed_official | 146:f64d43ff0c18 | 71 | { |
mbed_official | 146:f64d43ff0c18 | 72 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 73 | struct _hw_crc_datal_bitfields |
mbed_official | 146:f64d43ff0c18 | 74 | { |
mbed_official | 146:f64d43ff0c18 | 75 | uint16_t DATAL : 16; //!< [15:0] DATAL stores the lower 16 bits of |
mbed_official | 146:f64d43ff0c18 | 76 | //! the 16/32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 77 | } B; |
mbed_official | 146:f64d43ff0c18 | 78 | } hw_crc_datal_t; |
mbed_official | 146:f64d43ff0c18 | 79 | #endif |
mbed_official | 146:f64d43ff0c18 | 80 | |
mbed_official | 146:f64d43ff0c18 | 81 | /*! |
mbed_official | 146:f64d43ff0c18 | 82 | * @name Constants and macros for entire CRC_DATAL register |
mbed_official | 146:f64d43ff0c18 | 83 | */ |
mbed_official | 146:f64d43ff0c18 | 84 | //@{ |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_CRC_DATAL_ADDR (REGS_CRC_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 86 | |
mbed_official | 146:f64d43ff0c18 | 87 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 88 | #define HW_CRC_DATAL (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 89 | #define HW_CRC_DATAL_RD() (HW_CRC_DATAL.U) |
mbed_official | 146:f64d43ff0c18 | 90 | #define HW_CRC_DATAL_WR(v) (HW_CRC_DATAL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 91 | #define HW_CRC_DATAL_SET(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 92 | #define HW_CRC_DATAL_CLR(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 93 | #define HW_CRC_DATAL_TOG(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 94 | #endif |
mbed_official | 146:f64d43ff0c18 | 95 | //@} |
mbed_official | 146:f64d43ff0c18 | 96 | |
mbed_official | 146:f64d43ff0c18 | 97 | /* |
mbed_official | 146:f64d43ff0c18 | 98 | * Constants & macros for individual CRC_DATAL bitfields |
mbed_official | 146:f64d43ff0c18 | 99 | */ |
mbed_official | 146:f64d43ff0c18 | 100 | |
mbed_official | 146:f64d43ff0c18 | 101 | /*! |
mbed_official | 146:f64d43ff0c18 | 102 | * @name Register CRC_DATAL, field DATAL[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 103 | */ |
mbed_official | 146:f64d43ff0c18 | 104 | //@{ |
mbed_official | 146:f64d43ff0c18 | 105 | #define BP_CRC_DATAL_DATAL (0U) //!< Bit position for CRC_DATAL_DATAL. |
mbed_official | 146:f64d43ff0c18 | 106 | #define BM_CRC_DATAL_DATAL (0xFFFFU) //!< Bit mask for CRC_DATAL_DATAL. |
mbed_official | 146:f64d43ff0c18 | 107 | #define BS_CRC_DATAL_DATAL (16U) //!< Bit field size in bits for CRC_DATAL_DATAL. |
mbed_official | 146:f64d43ff0c18 | 108 | |
mbed_official | 146:f64d43ff0c18 | 109 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 110 | //! @brief Read current value of the CRC_DATAL_DATAL field. |
mbed_official | 146:f64d43ff0c18 | 111 | #define BR_CRC_DATAL_DATAL (HW_CRC_DATAL.U) |
mbed_official | 146:f64d43ff0c18 | 112 | #endif |
mbed_official | 146:f64d43ff0c18 | 113 | |
mbed_official | 146:f64d43ff0c18 | 114 | //! @brief Format value for bitfield CRC_DATAL_DATAL. |
mbed_official | 146:f64d43ff0c18 | 115 | #define BF_CRC_DATAL_DATAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAL_DATAL), uint16_t) & BM_CRC_DATAL_DATAL) |
mbed_official | 146:f64d43ff0c18 | 116 | |
mbed_official | 146:f64d43ff0c18 | 117 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 118 | //! @brief Set the DATAL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 119 | #define BW_CRC_DATAL_DATAL(v) (HW_CRC_DATAL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 120 | #endif |
mbed_official | 146:f64d43ff0c18 | 121 | //@} |
mbed_official | 146:f64d43ff0c18 | 122 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 123 | // HW_CRC_DATAH - CRC_DATAH register. |
mbed_official | 146:f64d43ff0c18 | 124 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 125 | |
mbed_official | 146:f64d43ff0c18 | 126 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 127 | /*! |
mbed_official | 146:f64d43ff0c18 | 128 | * @brief HW_CRC_DATAH - CRC_DATAH register. (RW) |
mbed_official | 146:f64d43ff0c18 | 129 | * |
mbed_official | 146:f64d43ff0c18 | 130 | * Reset value: 0xFFFFU |
mbed_official | 146:f64d43ff0c18 | 131 | */ |
mbed_official | 146:f64d43ff0c18 | 132 | typedef union _hw_crc_datah |
mbed_official | 146:f64d43ff0c18 | 133 | { |
mbed_official | 146:f64d43ff0c18 | 134 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 135 | struct _hw_crc_datah_bitfields |
mbed_official | 146:f64d43ff0c18 | 136 | { |
mbed_official | 146:f64d43ff0c18 | 137 | uint16_t DATAH : 16; //!< [15:0] DATAH stores the high 16 bits of the |
mbed_official | 146:f64d43ff0c18 | 138 | //! 16/32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 139 | } B; |
mbed_official | 146:f64d43ff0c18 | 140 | } hw_crc_datah_t; |
mbed_official | 146:f64d43ff0c18 | 141 | #endif |
mbed_official | 146:f64d43ff0c18 | 142 | |
mbed_official | 146:f64d43ff0c18 | 143 | /*! |
mbed_official | 146:f64d43ff0c18 | 144 | * @name Constants and macros for entire CRC_DATAH register |
mbed_official | 146:f64d43ff0c18 | 145 | */ |
mbed_official | 146:f64d43ff0c18 | 146 | //@{ |
mbed_official | 146:f64d43ff0c18 | 147 | #define HW_CRC_DATAH_ADDR (REGS_CRC_BASE + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 148 | |
mbed_official | 146:f64d43ff0c18 | 149 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 150 | #define HW_CRC_DATAH (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 151 | #define HW_CRC_DATAH_RD() (HW_CRC_DATAH.U) |
mbed_official | 146:f64d43ff0c18 | 152 | #define HW_CRC_DATAH_WR(v) (HW_CRC_DATAH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 153 | #define HW_CRC_DATAH_SET(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 154 | #define HW_CRC_DATAH_CLR(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 155 | #define HW_CRC_DATAH_TOG(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 156 | #endif |
mbed_official | 146:f64d43ff0c18 | 157 | //@} |
mbed_official | 146:f64d43ff0c18 | 158 | |
mbed_official | 146:f64d43ff0c18 | 159 | /* |
mbed_official | 146:f64d43ff0c18 | 160 | * Constants & macros for individual CRC_DATAH bitfields |
mbed_official | 146:f64d43ff0c18 | 161 | */ |
mbed_official | 146:f64d43ff0c18 | 162 | |
mbed_official | 146:f64d43ff0c18 | 163 | /*! |
mbed_official | 146:f64d43ff0c18 | 164 | * @name Register CRC_DATAH, field DATAH[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 165 | */ |
mbed_official | 146:f64d43ff0c18 | 166 | //@{ |
mbed_official | 146:f64d43ff0c18 | 167 | #define BP_CRC_DATAH_DATAH (0U) //!< Bit position for CRC_DATAH_DATAH. |
mbed_official | 146:f64d43ff0c18 | 168 | #define BM_CRC_DATAH_DATAH (0xFFFFU) //!< Bit mask for CRC_DATAH_DATAH. |
mbed_official | 146:f64d43ff0c18 | 169 | #define BS_CRC_DATAH_DATAH (16U) //!< Bit field size in bits for CRC_DATAH_DATAH. |
mbed_official | 146:f64d43ff0c18 | 170 | |
mbed_official | 146:f64d43ff0c18 | 171 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 172 | //! @brief Read current value of the CRC_DATAH_DATAH field. |
mbed_official | 146:f64d43ff0c18 | 173 | #define BR_CRC_DATAH_DATAH (HW_CRC_DATAH.U) |
mbed_official | 146:f64d43ff0c18 | 174 | #endif |
mbed_official | 146:f64d43ff0c18 | 175 | |
mbed_official | 146:f64d43ff0c18 | 176 | //! @brief Format value for bitfield CRC_DATAH_DATAH. |
mbed_official | 146:f64d43ff0c18 | 177 | #define BF_CRC_DATAH_DATAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAH_DATAH), uint16_t) & BM_CRC_DATAH_DATAH) |
mbed_official | 146:f64d43ff0c18 | 178 | |
mbed_official | 146:f64d43ff0c18 | 179 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 180 | //! @brief Set the DATAH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 181 | #define BW_CRC_DATAH_DATAH(v) (HW_CRC_DATAH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 182 | #endif |
mbed_official | 146:f64d43ff0c18 | 183 | //@} |
mbed_official | 146:f64d43ff0c18 | 184 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 185 | // HW_CRC_DATALL - CRC_DATALL register. |
mbed_official | 146:f64d43ff0c18 | 186 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 187 | |
mbed_official | 146:f64d43ff0c18 | 188 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 189 | /*! |
mbed_official | 146:f64d43ff0c18 | 190 | * @brief HW_CRC_DATALL - CRC_DATALL register. (RW) |
mbed_official | 146:f64d43ff0c18 | 191 | * |
mbed_official | 146:f64d43ff0c18 | 192 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 193 | */ |
mbed_official | 146:f64d43ff0c18 | 194 | typedef union _hw_crc_datall |
mbed_official | 146:f64d43ff0c18 | 195 | { |
mbed_official | 146:f64d43ff0c18 | 196 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 197 | struct _hw_crc_datall_bitfields |
mbed_official | 146:f64d43ff0c18 | 198 | { |
mbed_official | 146:f64d43ff0c18 | 199 | uint8_t DATALL : 8; //!< [7:0] CRCLL stores the first 8 bits of the |
mbed_official | 146:f64d43ff0c18 | 200 | //! 32 bit DATA |
mbed_official | 146:f64d43ff0c18 | 201 | } B; |
mbed_official | 146:f64d43ff0c18 | 202 | } hw_crc_datall_t; |
mbed_official | 146:f64d43ff0c18 | 203 | #endif |
mbed_official | 146:f64d43ff0c18 | 204 | |
mbed_official | 146:f64d43ff0c18 | 205 | /*! |
mbed_official | 146:f64d43ff0c18 | 206 | * @name Constants and macros for entire CRC_DATALL register |
mbed_official | 146:f64d43ff0c18 | 207 | */ |
mbed_official | 146:f64d43ff0c18 | 208 | //@{ |
mbed_official | 146:f64d43ff0c18 | 209 | #define HW_CRC_DATALL_ADDR (REGS_CRC_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 210 | |
mbed_official | 146:f64d43ff0c18 | 211 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 212 | #define HW_CRC_DATALL (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 213 | #define HW_CRC_DATALL_RD() (HW_CRC_DATALL.U) |
mbed_official | 146:f64d43ff0c18 | 214 | #define HW_CRC_DATALL_WR(v) (HW_CRC_DATALL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 215 | #define HW_CRC_DATALL_SET(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 216 | #define HW_CRC_DATALL_CLR(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 217 | #define HW_CRC_DATALL_TOG(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 218 | #endif |
mbed_official | 146:f64d43ff0c18 | 219 | //@} |
mbed_official | 146:f64d43ff0c18 | 220 | |
mbed_official | 146:f64d43ff0c18 | 221 | /* |
mbed_official | 146:f64d43ff0c18 | 222 | * Constants & macros for individual CRC_DATALL bitfields |
mbed_official | 146:f64d43ff0c18 | 223 | */ |
mbed_official | 146:f64d43ff0c18 | 224 | |
mbed_official | 146:f64d43ff0c18 | 225 | /*! |
mbed_official | 146:f64d43ff0c18 | 226 | * @name Register CRC_DATALL, field DATALL[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 227 | */ |
mbed_official | 146:f64d43ff0c18 | 228 | //@{ |
mbed_official | 146:f64d43ff0c18 | 229 | #define BP_CRC_DATALL_DATALL (0U) //!< Bit position for CRC_DATALL_DATALL. |
mbed_official | 146:f64d43ff0c18 | 230 | #define BM_CRC_DATALL_DATALL (0xFFU) //!< Bit mask for CRC_DATALL_DATALL. |
mbed_official | 146:f64d43ff0c18 | 231 | #define BS_CRC_DATALL_DATALL (8U) //!< Bit field size in bits for CRC_DATALL_DATALL. |
mbed_official | 146:f64d43ff0c18 | 232 | |
mbed_official | 146:f64d43ff0c18 | 233 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 234 | //! @brief Read current value of the CRC_DATALL_DATALL field. |
mbed_official | 146:f64d43ff0c18 | 235 | #define BR_CRC_DATALL_DATALL (HW_CRC_DATALL.U) |
mbed_official | 146:f64d43ff0c18 | 236 | #endif |
mbed_official | 146:f64d43ff0c18 | 237 | |
mbed_official | 146:f64d43ff0c18 | 238 | //! @brief Format value for bitfield CRC_DATALL_DATALL. |
mbed_official | 146:f64d43ff0c18 | 239 | #define BF_CRC_DATALL_DATALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALL_DATALL), uint8_t) & BM_CRC_DATALL_DATALL) |
mbed_official | 146:f64d43ff0c18 | 240 | |
mbed_official | 146:f64d43ff0c18 | 241 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 242 | //! @brief Set the DATALL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 243 | #define BW_CRC_DATALL_DATALL(v) (HW_CRC_DATALL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 244 | #endif |
mbed_official | 146:f64d43ff0c18 | 245 | //@} |
mbed_official | 146:f64d43ff0c18 | 246 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 247 | // HW_CRC_DATALU - CRC_DATALU register. |
mbed_official | 146:f64d43ff0c18 | 248 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 249 | |
mbed_official | 146:f64d43ff0c18 | 250 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 251 | /*! |
mbed_official | 146:f64d43ff0c18 | 252 | * @brief HW_CRC_DATALU - CRC_DATALU register. (RW) |
mbed_official | 146:f64d43ff0c18 | 253 | * |
mbed_official | 146:f64d43ff0c18 | 254 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 255 | */ |
mbed_official | 146:f64d43ff0c18 | 256 | typedef union _hw_crc_datalu |
mbed_official | 146:f64d43ff0c18 | 257 | { |
mbed_official | 146:f64d43ff0c18 | 258 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 259 | struct _hw_crc_datalu_bitfields |
mbed_official | 146:f64d43ff0c18 | 260 | { |
mbed_official | 146:f64d43ff0c18 | 261 | uint8_t DATALU : 8; //!< [7:0] DATALL stores the second 8 bits of the |
mbed_official | 146:f64d43ff0c18 | 262 | //! 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 263 | } B; |
mbed_official | 146:f64d43ff0c18 | 264 | } hw_crc_datalu_t; |
mbed_official | 146:f64d43ff0c18 | 265 | #endif |
mbed_official | 146:f64d43ff0c18 | 266 | |
mbed_official | 146:f64d43ff0c18 | 267 | /*! |
mbed_official | 146:f64d43ff0c18 | 268 | * @name Constants and macros for entire CRC_DATALU register |
mbed_official | 146:f64d43ff0c18 | 269 | */ |
mbed_official | 146:f64d43ff0c18 | 270 | //@{ |
mbed_official | 146:f64d43ff0c18 | 271 | #define HW_CRC_DATALU_ADDR (REGS_CRC_BASE + 0x1U) |
mbed_official | 146:f64d43ff0c18 | 272 | |
mbed_official | 146:f64d43ff0c18 | 273 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 274 | #define HW_CRC_DATALU (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR) |
mbed_official | 146:f64d43ff0c18 | 275 | #define HW_CRC_DATALU_RD() (HW_CRC_DATALU.U) |
mbed_official | 146:f64d43ff0c18 | 276 | #define HW_CRC_DATALU_WR(v) (HW_CRC_DATALU.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 277 | #define HW_CRC_DATALU_SET(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 278 | #define HW_CRC_DATALU_CLR(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 279 | #define HW_CRC_DATALU_TOG(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 280 | #endif |
mbed_official | 146:f64d43ff0c18 | 281 | //@} |
mbed_official | 146:f64d43ff0c18 | 282 | |
mbed_official | 146:f64d43ff0c18 | 283 | /* |
mbed_official | 146:f64d43ff0c18 | 284 | * Constants & macros for individual CRC_DATALU bitfields |
mbed_official | 146:f64d43ff0c18 | 285 | */ |
mbed_official | 146:f64d43ff0c18 | 286 | |
mbed_official | 146:f64d43ff0c18 | 287 | /*! |
mbed_official | 146:f64d43ff0c18 | 288 | * @name Register CRC_DATALU, field DATALU[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 289 | */ |
mbed_official | 146:f64d43ff0c18 | 290 | //@{ |
mbed_official | 146:f64d43ff0c18 | 291 | #define BP_CRC_DATALU_DATALU (0U) //!< Bit position for CRC_DATALU_DATALU. |
mbed_official | 146:f64d43ff0c18 | 292 | #define BM_CRC_DATALU_DATALU (0xFFU) //!< Bit mask for CRC_DATALU_DATALU. |
mbed_official | 146:f64d43ff0c18 | 293 | #define BS_CRC_DATALU_DATALU (8U) //!< Bit field size in bits for CRC_DATALU_DATALU. |
mbed_official | 146:f64d43ff0c18 | 294 | |
mbed_official | 146:f64d43ff0c18 | 295 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 296 | //! @brief Read current value of the CRC_DATALU_DATALU field. |
mbed_official | 146:f64d43ff0c18 | 297 | #define BR_CRC_DATALU_DATALU (HW_CRC_DATALU.U) |
mbed_official | 146:f64d43ff0c18 | 298 | #endif |
mbed_official | 146:f64d43ff0c18 | 299 | |
mbed_official | 146:f64d43ff0c18 | 300 | //! @brief Format value for bitfield CRC_DATALU_DATALU. |
mbed_official | 146:f64d43ff0c18 | 301 | #define BF_CRC_DATALU_DATALU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALU_DATALU), uint8_t) & BM_CRC_DATALU_DATALU) |
mbed_official | 146:f64d43ff0c18 | 302 | |
mbed_official | 146:f64d43ff0c18 | 303 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 304 | //! @brief Set the DATALU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 305 | #define BW_CRC_DATALU_DATALU(v) (HW_CRC_DATALU_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 306 | #endif |
mbed_official | 146:f64d43ff0c18 | 307 | //@} |
mbed_official | 146:f64d43ff0c18 | 308 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 309 | // HW_CRC_DATAHL - CRC_DATAHL register. |
mbed_official | 146:f64d43ff0c18 | 310 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 311 | |
mbed_official | 146:f64d43ff0c18 | 312 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 313 | /*! |
mbed_official | 146:f64d43ff0c18 | 314 | * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW) |
mbed_official | 146:f64d43ff0c18 | 315 | * |
mbed_official | 146:f64d43ff0c18 | 316 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 317 | */ |
mbed_official | 146:f64d43ff0c18 | 318 | typedef union _hw_crc_datahl |
mbed_official | 146:f64d43ff0c18 | 319 | { |
mbed_official | 146:f64d43ff0c18 | 320 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 321 | struct _hw_crc_datahl_bitfields |
mbed_official | 146:f64d43ff0c18 | 322 | { |
mbed_official | 146:f64d43ff0c18 | 323 | uint8_t DATAHL : 8; //!< [7:0] DATAHL stores the third 8 bits of the |
mbed_official | 146:f64d43ff0c18 | 324 | //! 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 325 | } B; |
mbed_official | 146:f64d43ff0c18 | 326 | } hw_crc_datahl_t; |
mbed_official | 146:f64d43ff0c18 | 327 | #endif |
mbed_official | 146:f64d43ff0c18 | 328 | |
mbed_official | 146:f64d43ff0c18 | 329 | /*! |
mbed_official | 146:f64d43ff0c18 | 330 | * @name Constants and macros for entire CRC_DATAHL register |
mbed_official | 146:f64d43ff0c18 | 331 | */ |
mbed_official | 146:f64d43ff0c18 | 332 | //@{ |
mbed_official | 146:f64d43ff0c18 | 333 | #define HW_CRC_DATAHL_ADDR (REGS_CRC_BASE + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 334 | |
mbed_official | 146:f64d43ff0c18 | 335 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 336 | #define HW_CRC_DATAHL (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 337 | #define HW_CRC_DATAHL_RD() (HW_CRC_DATAHL.U) |
mbed_official | 146:f64d43ff0c18 | 338 | #define HW_CRC_DATAHL_WR(v) (HW_CRC_DATAHL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 339 | #define HW_CRC_DATAHL_SET(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 340 | #define HW_CRC_DATAHL_CLR(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 341 | #define HW_CRC_DATAHL_TOG(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 342 | #endif |
mbed_official | 146:f64d43ff0c18 | 343 | //@} |
mbed_official | 146:f64d43ff0c18 | 344 | |
mbed_official | 146:f64d43ff0c18 | 345 | /* |
mbed_official | 146:f64d43ff0c18 | 346 | * Constants & macros for individual CRC_DATAHL bitfields |
mbed_official | 146:f64d43ff0c18 | 347 | */ |
mbed_official | 146:f64d43ff0c18 | 348 | |
mbed_official | 146:f64d43ff0c18 | 349 | /*! |
mbed_official | 146:f64d43ff0c18 | 350 | * @name Register CRC_DATAHL, field DATAHL[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 351 | */ |
mbed_official | 146:f64d43ff0c18 | 352 | //@{ |
mbed_official | 146:f64d43ff0c18 | 353 | #define BP_CRC_DATAHL_DATAHL (0U) //!< Bit position for CRC_DATAHL_DATAHL. |
mbed_official | 146:f64d43ff0c18 | 354 | #define BM_CRC_DATAHL_DATAHL (0xFFU) //!< Bit mask for CRC_DATAHL_DATAHL. |
mbed_official | 146:f64d43ff0c18 | 355 | #define BS_CRC_DATAHL_DATAHL (8U) //!< Bit field size in bits for CRC_DATAHL_DATAHL. |
mbed_official | 146:f64d43ff0c18 | 356 | |
mbed_official | 146:f64d43ff0c18 | 357 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 358 | //! @brief Read current value of the CRC_DATAHL_DATAHL field. |
mbed_official | 146:f64d43ff0c18 | 359 | #define BR_CRC_DATAHL_DATAHL (HW_CRC_DATAHL.U) |
mbed_official | 146:f64d43ff0c18 | 360 | #endif |
mbed_official | 146:f64d43ff0c18 | 361 | |
mbed_official | 146:f64d43ff0c18 | 362 | //! @brief Format value for bitfield CRC_DATAHL_DATAHL. |
mbed_official | 146:f64d43ff0c18 | 363 | #define BF_CRC_DATAHL_DATAHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHL_DATAHL), uint8_t) & BM_CRC_DATAHL_DATAHL) |
mbed_official | 146:f64d43ff0c18 | 364 | |
mbed_official | 146:f64d43ff0c18 | 365 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 366 | //! @brief Set the DATAHL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 367 | #define BW_CRC_DATAHL_DATAHL(v) (HW_CRC_DATAHL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 368 | #endif |
mbed_official | 146:f64d43ff0c18 | 369 | //@} |
mbed_official | 146:f64d43ff0c18 | 370 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 371 | // HW_CRC_DATAHU - CRC_DATAHU register. |
mbed_official | 146:f64d43ff0c18 | 372 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 373 | |
mbed_official | 146:f64d43ff0c18 | 374 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 375 | /*! |
mbed_official | 146:f64d43ff0c18 | 376 | * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW) |
mbed_official | 146:f64d43ff0c18 | 377 | * |
mbed_official | 146:f64d43ff0c18 | 378 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 379 | */ |
mbed_official | 146:f64d43ff0c18 | 380 | typedef union _hw_crc_datahu |
mbed_official | 146:f64d43ff0c18 | 381 | { |
mbed_official | 146:f64d43ff0c18 | 382 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 383 | struct _hw_crc_datahu_bitfields |
mbed_official | 146:f64d43ff0c18 | 384 | { |
mbed_official | 146:f64d43ff0c18 | 385 | uint8_t DATAHU : 8; //!< [7:0] DATAHU stores the fourth 8 bits of the |
mbed_official | 146:f64d43ff0c18 | 386 | //! 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 387 | } B; |
mbed_official | 146:f64d43ff0c18 | 388 | } hw_crc_datahu_t; |
mbed_official | 146:f64d43ff0c18 | 389 | #endif |
mbed_official | 146:f64d43ff0c18 | 390 | |
mbed_official | 146:f64d43ff0c18 | 391 | /*! |
mbed_official | 146:f64d43ff0c18 | 392 | * @name Constants and macros for entire CRC_DATAHU register |
mbed_official | 146:f64d43ff0c18 | 393 | */ |
mbed_official | 146:f64d43ff0c18 | 394 | //@{ |
mbed_official | 146:f64d43ff0c18 | 395 | #define HW_CRC_DATAHU_ADDR (REGS_CRC_BASE + 0x3U) |
mbed_official | 146:f64d43ff0c18 | 396 | |
mbed_official | 146:f64d43ff0c18 | 397 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 398 | #define HW_CRC_DATAHU (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR) |
mbed_official | 146:f64d43ff0c18 | 399 | #define HW_CRC_DATAHU_RD() (HW_CRC_DATAHU.U) |
mbed_official | 146:f64d43ff0c18 | 400 | #define HW_CRC_DATAHU_WR(v) (HW_CRC_DATAHU.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 401 | #define HW_CRC_DATAHU_SET(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 402 | #define HW_CRC_DATAHU_CLR(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 403 | #define HW_CRC_DATAHU_TOG(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 404 | #endif |
mbed_official | 146:f64d43ff0c18 | 405 | //@} |
mbed_official | 146:f64d43ff0c18 | 406 | |
mbed_official | 146:f64d43ff0c18 | 407 | /* |
mbed_official | 146:f64d43ff0c18 | 408 | * Constants & macros for individual CRC_DATAHU bitfields |
mbed_official | 146:f64d43ff0c18 | 409 | */ |
mbed_official | 146:f64d43ff0c18 | 410 | |
mbed_official | 146:f64d43ff0c18 | 411 | /*! |
mbed_official | 146:f64d43ff0c18 | 412 | * @name Register CRC_DATAHU, field DATAHU[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 413 | */ |
mbed_official | 146:f64d43ff0c18 | 414 | //@{ |
mbed_official | 146:f64d43ff0c18 | 415 | #define BP_CRC_DATAHU_DATAHU (0U) //!< Bit position for CRC_DATAHU_DATAHU. |
mbed_official | 146:f64d43ff0c18 | 416 | #define BM_CRC_DATAHU_DATAHU (0xFFU) //!< Bit mask for CRC_DATAHU_DATAHU. |
mbed_official | 146:f64d43ff0c18 | 417 | #define BS_CRC_DATAHU_DATAHU (8U) //!< Bit field size in bits for CRC_DATAHU_DATAHU. |
mbed_official | 146:f64d43ff0c18 | 418 | |
mbed_official | 146:f64d43ff0c18 | 419 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 420 | //! @brief Read current value of the CRC_DATAHU_DATAHU field. |
mbed_official | 146:f64d43ff0c18 | 421 | #define BR_CRC_DATAHU_DATAHU (HW_CRC_DATAHU.U) |
mbed_official | 146:f64d43ff0c18 | 422 | #endif |
mbed_official | 146:f64d43ff0c18 | 423 | |
mbed_official | 146:f64d43ff0c18 | 424 | //! @brief Format value for bitfield CRC_DATAHU_DATAHU. |
mbed_official | 146:f64d43ff0c18 | 425 | #define BF_CRC_DATAHU_DATAHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHU_DATAHU), uint8_t) & BM_CRC_DATAHU_DATAHU) |
mbed_official | 146:f64d43ff0c18 | 426 | |
mbed_official | 146:f64d43ff0c18 | 427 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 428 | //! @brief Set the DATAHU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 429 | #define BW_CRC_DATAHU_DATAHU(v) (HW_CRC_DATAHU_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 430 | #endif |
mbed_official | 146:f64d43ff0c18 | 431 | //@} |
mbed_official | 146:f64d43ff0c18 | 432 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 433 | // HW_CRC_DATA - CRC Data register |
mbed_official | 146:f64d43ff0c18 | 434 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 435 | |
mbed_official | 146:f64d43ff0c18 | 436 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 437 | /*! |
mbed_official | 146:f64d43ff0c18 | 438 | * @brief HW_CRC_DATA - CRC Data register (RW) |
mbed_official | 146:f64d43ff0c18 | 439 | * |
mbed_official | 146:f64d43ff0c18 | 440 | * Reset value: 0xFFFFFFFFU |
mbed_official | 146:f64d43ff0c18 | 441 | * |
mbed_official | 146:f64d43ff0c18 | 442 | * The CRC Data register contains the value of the seed, data, and checksum. |
mbed_official | 146:f64d43ff0c18 | 443 | * When CTRL[WAS] is set, any write to the data register is regarded as the seed |
mbed_official | 146:f64d43ff0c18 | 444 | * value. When CTRL[WAS] is cleared, any write to the data register is regarded as |
mbed_official | 146:f64d43ff0c18 | 445 | * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are |
mbed_official | 146:f64d43ff0c18 | 446 | * not used for programming the seed value, and reads of these fields return an |
mbed_official | 146:f64d43ff0c18 | 447 | * indeterminate value. In 32-bit CRC mode, all fields are used for programming |
mbed_official | 146:f64d43ff0c18 | 448 | * the seed value. When programming data values, the values can be written 8 bits, |
mbed_official | 146:f64d43ff0c18 | 449 | * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of |
mbed_official | 146:f64d43ff0c18 | 450 | * data value written first. After all data values are written, the CRC result |
mbed_official | 146:f64d43ff0c18 | 451 | * can be read from this data register. In 16-bit CRC mode, the CRC result is |
mbed_official | 146:f64d43ff0c18 | 452 | * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the |
mbed_official | 146:f64d43ff0c18 | 453 | * result. Reads of this register at any time return the intermediate CRC value, |
mbed_official | 146:f64d43ff0c18 | 454 | * provided the CRC module is configured. |
mbed_official | 146:f64d43ff0c18 | 455 | */ |
mbed_official | 146:f64d43ff0c18 | 456 | typedef union _hw_crc_data |
mbed_official | 146:f64d43ff0c18 | 457 | { |
mbed_official | 146:f64d43ff0c18 | 458 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 459 | struct _hw_crc_data_bitfields |
mbed_official | 146:f64d43ff0c18 | 460 | { |
mbed_official | 146:f64d43ff0c18 | 461 | uint32_t LL : 8; //!< [7:0] CRC Low Lower Byte |
mbed_official | 146:f64d43ff0c18 | 462 | uint32_t LU : 8; //!< [15:8] CRC Low Upper Byte |
mbed_official | 146:f64d43ff0c18 | 463 | uint32_t HL : 8; //!< [23:16] CRC High Lower Byte |
mbed_official | 146:f64d43ff0c18 | 464 | uint32_t HU : 8; //!< [31:24] CRC High Upper Byte |
mbed_official | 146:f64d43ff0c18 | 465 | } B; |
mbed_official | 146:f64d43ff0c18 | 466 | } hw_crc_data_t; |
mbed_official | 146:f64d43ff0c18 | 467 | #endif |
mbed_official | 146:f64d43ff0c18 | 468 | |
mbed_official | 146:f64d43ff0c18 | 469 | /*! |
mbed_official | 146:f64d43ff0c18 | 470 | * @name Constants and macros for entire CRC_DATA register |
mbed_official | 146:f64d43ff0c18 | 471 | */ |
mbed_official | 146:f64d43ff0c18 | 472 | //@{ |
mbed_official | 146:f64d43ff0c18 | 473 | #define HW_CRC_DATA_ADDR (REGS_CRC_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 474 | |
mbed_official | 146:f64d43ff0c18 | 475 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 476 | #define HW_CRC_DATA (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR) |
mbed_official | 146:f64d43ff0c18 | 477 | #define HW_CRC_DATA_RD() (HW_CRC_DATA.U) |
mbed_official | 146:f64d43ff0c18 | 478 | #define HW_CRC_DATA_WR(v) (HW_CRC_DATA.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 479 | #define HW_CRC_DATA_SET(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 480 | #define HW_CRC_DATA_CLR(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 481 | #define HW_CRC_DATA_TOG(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 482 | #endif |
mbed_official | 146:f64d43ff0c18 | 483 | //@} |
mbed_official | 146:f64d43ff0c18 | 484 | |
mbed_official | 146:f64d43ff0c18 | 485 | /* |
mbed_official | 146:f64d43ff0c18 | 486 | * Constants & macros for individual CRC_DATA bitfields |
mbed_official | 146:f64d43ff0c18 | 487 | */ |
mbed_official | 146:f64d43ff0c18 | 488 | |
mbed_official | 146:f64d43ff0c18 | 489 | /*! |
mbed_official | 146:f64d43ff0c18 | 490 | * @name Register CRC_DATA, field LL[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 491 | * |
mbed_official | 146:f64d43ff0c18 | 492 | * When CTRL[WAS] is 1, values written to this field are part of the seed value. |
mbed_official | 146:f64d43ff0c18 | 493 | * When CTRL[WAS] is 0, data written to this field is used for CRC checksum |
mbed_official | 146:f64d43ff0c18 | 494 | * generation. |
mbed_official | 146:f64d43ff0c18 | 495 | */ |
mbed_official | 146:f64d43ff0c18 | 496 | //@{ |
mbed_official | 146:f64d43ff0c18 | 497 | #define BP_CRC_DATA_LL (0U) //!< Bit position for CRC_DATA_LL. |
mbed_official | 146:f64d43ff0c18 | 498 | #define BM_CRC_DATA_LL (0x000000FFU) //!< Bit mask for CRC_DATA_LL. |
mbed_official | 146:f64d43ff0c18 | 499 | #define BS_CRC_DATA_LL (8U) //!< Bit field size in bits for CRC_DATA_LL. |
mbed_official | 146:f64d43ff0c18 | 500 | |
mbed_official | 146:f64d43ff0c18 | 501 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 502 | //! @brief Read current value of the CRC_DATA_LL field. |
mbed_official | 146:f64d43ff0c18 | 503 | #define BR_CRC_DATA_LL (HW_CRC_DATA.B.LL) |
mbed_official | 146:f64d43ff0c18 | 504 | #endif |
mbed_official | 146:f64d43ff0c18 | 505 | |
mbed_official | 146:f64d43ff0c18 | 506 | //! @brief Format value for bitfield CRC_DATA_LL. |
mbed_official | 146:f64d43ff0c18 | 507 | #define BF_CRC_DATA_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LL), uint32_t) & BM_CRC_DATA_LL) |
mbed_official | 146:f64d43ff0c18 | 508 | |
mbed_official | 146:f64d43ff0c18 | 509 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 510 | //! @brief Set the LL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 511 | #define BW_CRC_DATA_LL(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v))) |
mbed_official | 146:f64d43ff0c18 | 512 | #endif |
mbed_official | 146:f64d43ff0c18 | 513 | //@} |
mbed_official | 146:f64d43ff0c18 | 514 | |
mbed_official | 146:f64d43ff0c18 | 515 | /*! |
mbed_official | 146:f64d43ff0c18 | 516 | * @name Register CRC_DATA, field LU[15:8] (RW) |
mbed_official | 146:f64d43ff0c18 | 517 | * |
mbed_official | 146:f64d43ff0c18 | 518 | * When CTRL[WAS] is 1, values written to this field are part of the seed value. |
mbed_official | 146:f64d43ff0c18 | 519 | * When CTRL[WAS] is 0, data written to this field is used for CRC checksum |
mbed_official | 146:f64d43ff0c18 | 520 | * generation. |
mbed_official | 146:f64d43ff0c18 | 521 | */ |
mbed_official | 146:f64d43ff0c18 | 522 | //@{ |
mbed_official | 146:f64d43ff0c18 | 523 | #define BP_CRC_DATA_LU (8U) //!< Bit position for CRC_DATA_LU. |
mbed_official | 146:f64d43ff0c18 | 524 | #define BM_CRC_DATA_LU (0x0000FF00U) //!< Bit mask for CRC_DATA_LU. |
mbed_official | 146:f64d43ff0c18 | 525 | #define BS_CRC_DATA_LU (8U) //!< Bit field size in bits for CRC_DATA_LU. |
mbed_official | 146:f64d43ff0c18 | 526 | |
mbed_official | 146:f64d43ff0c18 | 527 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 528 | //! @brief Read current value of the CRC_DATA_LU field. |
mbed_official | 146:f64d43ff0c18 | 529 | #define BR_CRC_DATA_LU (HW_CRC_DATA.B.LU) |
mbed_official | 146:f64d43ff0c18 | 530 | #endif |
mbed_official | 146:f64d43ff0c18 | 531 | |
mbed_official | 146:f64d43ff0c18 | 532 | //! @brief Format value for bitfield CRC_DATA_LU. |
mbed_official | 146:f64d43ff0c18 | 533 | #define BF_CRC_DATA_LU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LU), uint32_t) & BM_CRC_DATA_LU) |
mbed_official | 146:f64d43ff0c18 | 534 | |
mbed_official | 146:f64d43ff0c18 | 535 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 536 | //! @brief Set the LU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 537 | #define BW_CRC_DATA_LU(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v))) |
mbed_official | 146:f64d43ff0c18 | 538 | #endif |
mbed_official | 146:f64d43ff0c18 | 539 | //@} |
mbed_official | 146:f64d43ff0c18 | 540 | |
mbed_official | 146:f64d43ff0c18 | 541 | /*! |
mbed_official | 146:f64d43ff0c18 | 542 | * @name Register CRC_DATA, field HL[23:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 543 | * |
mbed_official | 146:f64d43ff0c18 | 544 | * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming |
mbed_official | 146:f64d43ff0c18 | 545 | * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this |
mbed_official | 146:f64d43ff0c18 | 546 | * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data |
mbed_official | 146:f64d43ff0c18 | 547 | * written to this field is used for CRC checksum generation in both 16-bit and |
mbed_official | 146:f64d43ff0c18 | 548 | * 32-bit CRC modes. |
mbed_official | 146:f64d43ff0c18 | 549 | */ |
mbed_official | 146:f64d43ff0c18 | 550 | //@{ |
mbed_official | 146:f64d43ff0c18 | 551 | #define BP_CRC_DATA_HL (16U) //!< Bit position for CRC_DATA_HL. |
mbed_official | 146:f64d43ff0c18 | 552 | #define BM_CRC_DATA_HL (0x00FF0000U) //!< Bit mask for CRC_DATA_HL. |
mbed_official | 146:f64d43ff0c18 | 553 | #define BS_CRC_DATA_HL (8U) //!< Bit field size in bits for CRC_DATA_HL. |
mbed_official | 146:f64d43ff0c18 | 554 | |
mbed_official | 146:f64d43ff0c18 | 555 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 556 | //! @brief Read current value of the CRC_DATA_HL field. |
mbed_official | 146:f64d43ff0c18 | 557 | #define BR_CRC_DATA_HL (HW_CRC_DATA.B.HL) |
mbed_official | 146:f64d43ff0c18 | 558 | #endif |
mbed_official | 146:f64d43ff0c18 | 559 | |
mbed_official | 146:f64d43ff0c18 | 560 | //! @brief Format value for bitfield CRC_DATA_HL. |
mbed_official | 146:f64d43ff0c18 | 561 | #define BF_CRC_DATA_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HL), uint32_t) & BM_CRC_DATA_HL) |
mbed_official | 146:f64d43ff0c18 | 562 | |
mbed_official | 146:f64d43ff0c18 | 563 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 564 | //! @brief Set the HL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 565 | #define BW_CRC_DATA_HL(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v))) |
mbed_official | 146:f64d43ff0c18 | 566 | #endif |
mbed_official | 146:f64d43ff0c18 | 567 | //@} |
mbed_official | 146:f64d43ff0c18 | 568 | |
mbed_official | 146:f64d43ff0c18 | 569 | /*! |
mbed_official | 146:f64d43ff0c18 | 570 | * @name Register CRC_DATA, field HU[31:24] (RW) |
mbed_official | 146:f64d43ff0c18 | 571 | * |
mbed_official | 146:f64d43ff0c18 | 572 | * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming |
mbed_official | 146:f64d43ff0c18 | 573 | * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this |
mbed_official | 146:f64d43ff0c18 | 574 | * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data |
mbed_official | 146:f64d43ff0c18 | 575 | * written to this field is used for CRC checksum generation in both 16-bit and |
mbed_official | 146:f64d43ff0c18 | 576 | * 32-bit CRC modes. |
mbed_official | 146:f64d43ff0c18 | 577 | */ |
mbed_official | 146:f64d43ff0c18 | 578 | //@{ |
mbed_official | 146:f64d43ff0c18 | 579 | #define BP_CRC_DATA_HU (24U) //!< Bit position for CRC_DATA_HU. |
mbed_official | 146:f64d43ff0c18 | 580 | #define BM_CRC_DATA_HU (0xFF000000U) //!< Bit mask for CRC_DATA_HU. |
mbed_official | 146:f64d43ff0c18 | 581 | #define BS_CRC_DATA_HU (8U) //!< Bit field size in bits for CRC_DATA_HU. |
mbed_official | 146:f64d43ff0c18 | 582 | |
mbed_official | 146:f64d43ff0c18 | 583 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 584 | //! @brief Read current value of the CRC_DATA_HU field. |
mbed_official | 146:f64d43ff0c18 | 585 | #define BR_CRC_DATA_HU (HW_CRC_DATA.B.HU) |
mbed_official | 146:f64d43ff0c18 | 586 | #endif |
mbed_official | 146:f64d43ff0c18 | 587 | |
mbed_official | 146:f64d43ff0c18 | 588 | //! @brief Format value for bitfield CRC_DATA_HU. |
mbed_official | 146:f64d43ff0c18 | 589 | #define BF_CRC_DATA_HU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HU), uint32_t) & BM_CRC_DATA_HU) |
mbed_official | 146:f64d43ff0c18 | 590 | |
mbed_official | 146:f64d43ff0c18 | 591 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 592 | //! @brief Set the HU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 593 | #define BW_CRC_DATA_HU(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v))) |
mbed_official | 146:f64d43ff0c18 | 594 | #endif |
mbed_official | 146:f64d43ff0c18 | 595 | //@} |
mbed_official | 146:f64d43ff0c18 | 596 | |
mbed_official | 146:f64d43ff0c18 | 597 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 598 | // HW_CRC_GPOLY - CRC Polynomial register |
mbed_official | 146:f64d43ff0c18 | 599 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 600 | |
mbed_official | 146:f64d43ff0c18 | 601 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 602 | /*! |
mbed_official | 146:f64d43ff0c18 | 603 | * @brief HW_CRC_GPOLY - CRC Polynomial register (RW) |
mbed_official | 146:f64d43ff0c18 | 604 | * |
mbed_official | 146:f64d43ff0c18 | 605 | * Reset value: 0x00001021U |
mbed_official | 146:f64d43ff0c18 | 606 | * |
mbed_official | 146:f64d43ff0c18 | 607 | * This register contains the value of the polynomial for the CRC calculation. |
mbed_official | 146:f64d43ff0c18 | 608 | * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used |
mbed_official | 146:f64d43ff0c18 | 609 | * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC |
mbed_official | 146:f64d43ff0c18 | 610 | * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are |
mbed_official | 146:f64d43ff0c18 | 611 | * used in both 16- and 32-bit CRC modes. |
mbed_official | 146:f64d43ff0c18 | 612 | */ |
mbed_official | 146:f64d43ff0c18 | 613 | typedef union _hw_crc_gpoly |
mbed_official | 146:f64d43ff0c18 | 614 | { |
mbed_official | 146:f64d43ff0c18 | 615 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 616 | struct _hw_crc_gpoly_bitfields |
mbed_official | 146:f64d43ff0c18 | 617 | { |
mbed_official | 146:f64d43ff0c18 | 618 | uint32_t LOW : 16; //!< [15:0] Low Polynominal Half-word |
mbed_official | 146:f64d43ff0c18 | 619 | uint32_t HIGH : 16; //!< [31:16] High Polynominal Half-word |
mbed_official | 146:f64d43ff0c18 | 620 | } B; |
mbed_official | 146:f64d43ff0c18 | 621 | } hw_crc_gpoly_t; |
mbed_official | 146:f64d43ff0c18 | 622 | #endif |
mbed_official | 146:f64d43ff0c18 | 623 | |
mbed_official | 146:f64d43ff0c18 | 624 | /*! |
mbed_official | 146:f64d43ff0c18 | 625 | * @name Constants and macros for entire CRC_GPOLY register |
mbed_official | 146:f64d43ff0c18 | 626 | */ |
mbed_official | 146:f64d43ff0c18 | 627 | //@{ |
mbed_official | 146:f64d43ff0c18 | 628 | #define HW_CRC_GPOLY_ADDR (REGS_CRC_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 629 | |
mbed_official | 146:f64d43ff0c18 | 630 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 631 | #define HW_CRC_GPOLY (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR) |
mbed_official | 146:f64d43ff0c18 | 632 | #define HW_CRC_GPOLY_RD() (HW_CRC_GPOLY.U) |
mbed_official | 146:f64d43ff0c18 | 633 | #define HW_CRC_GPOLY_WR(v) (HW_CRC_GPOLY.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 634 | #define HW_CRC_GPOLY_SET(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 635 | #define HW_CRC_GPOLY_CLR(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 636 | #define HW_CRC_GPOLY_TOG(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 637 | #endif |
mbed_official | 146:f64d43ff0c18 | 638 | //@} |
mbed_official | 146:f64d43ff0c18 | 639 | |
mbed_official | 146:f64d43ff0c18 | 640 | /* |
mbed_official | 146:f64d43ff0c18 | 641 | * Constants & macros for individual CRC_GPOLY bitfields |
mbed_official | 146:f64d43ff0c18 | 642 | */ |
mbed_official | 146:f64d43ff0c18 | 643 | |
mbed_official | 146:f64d43ff0c18 | 644 | /*! |
mbed_official | 146:f64d43ff0c18 | 645 | * @name Register CRC_GPOLY, field LOW[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 646 | * |
mbed_official | 146:f64d43ff0c18 | 647 | * Writable and readable in both 32-bit and 16-bit CRC modes. |
mbed_official | 146:f64d43ff0c18 | 648 | */ |
mbed_official | 146:f64d43ff0c18 | 649 | //@{ |
mbed_official | 146:f64d43ff0c18 | 650 | #define BP_CRC_GPOLY_LOW (0U) //!< Bit position for CRC_GPOLY_LOW. |
mbed_official | 146:f64d43ff0c18 | 651 | #define BM_CRC_GPOLY_LOW (0x0000FFFFU) //!< Bit mask for CRC_GPOLY_LOW. |
mbed_official | 146:f64d43ff0c18 | 652 | #define BS_CRC_GPOLY_LOW (16U) //!< Bit field size in bits for CRC_GPOLY_LOW. |
mbed_official | 146:f64d43ff0c18 | 653 | |
mbed_official | 146:f64d43ff0c18 | 654 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 655 | //! @brief Read current value of the CRC_GPOLY_LOW field. |
mbed_official | 146:f64d43ff0c18 | 656 | #define BR_CRC_GPOLY_LOW (HW_CRC_GPOLY.B.LOW) |
mbed_official | 146:f64d43ff0c18 | 657 | #endif |
mbed_official | 146:f64d43ff0c18 | 658 | |
mbed_official | 146:f64d43ff0c18 | 659 | //! @brief Format value for bitfield CRC_GPOLY_LOW. |
mbed_official | 146:f64d43ff0c18 | 660 | #define BF_CRC_GPOLY_LOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_LOW), uint32_t) & BM_CRC_GPOLY_LOW) |
mbed_official | 146:f64d43ff0c18 | 661 | |
mbed_official | 146:f64d43ff0c18 | 662 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 663 | //! @brief Set the LOW field to a new value. |
mbed_official | 146:f64d43ff0c18 | 664 | #define BW_CRC_GPOLY_LOW(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v))) |
mbed_official | 146:f64d43ff0c18 | 665 | #endif |
mbed_official | 146:f64d43ff0c18 | 666 | //@} |
mbed_official | 146:f64d43ff0c18 | 667 | |
mbed_official | 146:f64d43ff0c18 | 668 | /*! |
mbed_official | 146:f64d43ff0c18 | 669 | * @name Register CRC_GPOLY, field HIGH[31:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 670 | * |
mbed_official | 146:f64d43ff0c18 | 671 | * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not |
mbed_official | 146:f64d43ff0c18 | 672 | * writable in 16-bit CRC mode (CTRL[TCRC] is 0). |
mbed_official | 146:f64d43ff0c18 | 673 | */ |
mbed_official | 146:f64d43ff0c18 | 674 | //@{ |
mbed_official | 146:f64d43ff0c18 | 675 | #define BP_CRC_GPOLY_HIGH (16U) //!< Bit position for CRC_GPOLY_HIGH. |
mbed_official | 146:f64d43ff0c18 | 676 | #define BM_CRC_GPOLY_HIGH (0xFFFF0000U) //!< Bit mask for CRC_GPOLY_HIGH. |
mbed_official | 146:f64d43ff0c18 | 677 | #define BS_CRC_GPOLY_HIGH (16U) //!< Bit field size in bits for CRC_GPOLY_HIGH. |
mbed_official | 146:f64d43ff0c18 | 678 | |
mbed_official | 146:f64d43ff0c18 | 679 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 680 | //! @brief Read current value of the CRC_GPOLY_HIGH field. |
mbed_official | 146:f64d43ff0c18 | 681 | #define BR_CRC_GPOLY_HIGH (HW_CRC_GPOLY.B.HIGH) |
mbed_official | 146:f64d43ff0c18 | 682 | #endif |
mbed_official | 146:f64d43ff0c18 | 683 | |
mbed_official | 146:f64d43ff0c18 | 684 | //! @brief Format value for bitfield CRC_GPOLY_HIGH. |
mbed_official | 146:f64d43ff0c18 | 685 | #define BF_CRC_GPOLY_HIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_HIGH), uint32_t) & BM_CRC_GPOLY_HIGH) |
mbed_official | 146:f64d43ff0c18 | 686 | |
mbed_official | 146:f64d43ff0c18 | 687 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 688 | //! @brief Set the HIGH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 689 | #define BW_CRC_GPOLY_HIGH(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v))) |
mbed_official | 146:f64d43ff0c18 | 690 | #endif |
mbed_official | 146:f64d43ff0c18 | 691 | //@} |
mbed_official | 146:f64d43ff0c18 | 692 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 693 | // HW_CRC_GPOLYL - CRC_GPOLYL register. |
mbed_official | 146:f64d43ff0c18 | 694 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 695 | |
mbed_official | 146:f64d43ff0c18 | 696 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 697 | /*! |
mbed_official | 146:f64d43ff0c18 | 698 | * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW) |
mbed_official | 146:f64d43ff0c18 | 699 | * |
mbed_official | 146:f64d43ff0c18 | 700 | * Reset value: 0xFFFFU |
mbed_official | 146:f64d43ff0c18 | 701 | */ |
mbed_official | 146:f64d43ff0c18 | 702 | typedef union _hw_crc_gpolyl |
mbed_official | 146:f64d43ff0c18 | 703 | { |
mbed_official | 146:f64d43ff0c18 | 704 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 705 | struct _hw_crc_gpolyl_bitfields |
mbed_official | 146:f64d43ff0c18 | 706 | { |
mbed_official | 146:f64d43ff0c18 | 707 | uint16_t GPOLYL : 16; //!< [15:0] POLYL stores the lower 16 bits of |
mbed_official | 146:f64d43ff0c18 | 708 | //! the 16/32 bit CRC polynomial value |
mbed_official | 146:f64d43ff0c18 | 709 | } B; |
mbed_official | 146:f64d43ff0c18 | 710 | } hw_crc_gpolyl_t; |
mbed_official | 146:f64d43ff0c18 | 711 | #endif |
mbed_official | 146:f64d43ff0c18 | 712 | |
mbed_official | 146:f64d43ff0c18 | 713 | /*! |
mbed_official | 146:f64d43ff0c18 | 714 | * @name Constants and macros for entire CRC_GPOLYL register |
mbed_official | 146:f64d43ff0c18 | 715 | */ |
mbed_official | 146:f64d43ff0c18 | 716 | //@{ |
mbed_official | 146:f64d43ff0c18 | 717 | #define HW_CRC_GPOLYL_ADDR (REGS_CRC_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 718 | |
mbed_official | 146:f64d43ff0c18 | 719 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 720 | #define HW_CRC_GPOLYL (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 721 | #define HW_CRC_GPOLYL_RD() (HW_CRC_GPOLYL.U) |
mbed_official | 146:f64d43ff0c18 | 722 | #define HW_CRC_GPOLYL_WR(v) (HW_CRC_GPOLYL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 723 | #define HW_CRC_GPOLYL_SET(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 724 | #define HW_CRC_GPOLYL_CLR(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 725 | #define HW_CRC_GPOLYL_TOG(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 726 | #endif |
mbed_official | 146:f64d43ff0c18 | 727 | //@} |
mbed_official | 146:f64d43ff0c18 | 728 | |
mbed_official | 146:f64d43ff0c18 | 729 | /* |
mbed_official | 146:f64d43ff0c18 | 730 | * Constants & macros for individual CRC_GPOLYL bitfields |
mbed_official | 146:f64d43ff0c18 | 731 | */ |
mbed_official | 146:f64d43ff0c18 | 732 | |
mbed_official | 146:f64d43ff0c18 | 733 | /*! |
mbed_official | 146:f64d43ff0c18 | 734 | * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 735 | */ |
mbed_official | 146:f64d43ff0c18 | 736 | //@{ |
mbed_official | 146:f64d43ff0c18 | 737 | #define BP_CRC_GPOLYL_GPOLYL (0U) //!< Bit position for CRC_GPOLYL_GPOLYL. |
mbed_official | 146:f64d43ff0c18 | 738 | #define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) //!< Bit mask for CRC_GPOLYL_GPOLYL. |
mbed_official | 146:f64d43ff0c18 | 739 | #define BS_CRC_GPOLYL_GPOLYL (16U) //!< Bit field size in bits for CRC_GPOLYL_GPOLYL. |
mbed_official | 146:f64d43ff0c18 | 740 | |
mbed_official | 146:f64d43ff0c18 | 741 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 742 | //! @brief Read current value of the CRC_GPOLYL_GPOLYL field. |
mbed_official | 146:f64d43ff0c18 | 743 | #define BR_CRC_GPOLYL_GPOLYL (HW_CRC_GPOLYL.U) |
mbed_official | 146:f64d43ff0c18 | 744 | #endif |
mbed_official | 146:f64d43ff0c18 | 745 | |
mbed_official | 146:f64d43ff0c18 | 746 | //! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. |
mbed_official | 146:f64d43ff0c18 | 747 | #define BF_CRC_GPOLYL_GPOLYL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYL_GPOLYL), uint16_t) & BM_CRC_GPOLYL_GPOLYL) |
mbed_official | 146:f64d43ff0c18 | 748 | |
mbed_official | 146:f64d43ff0c18 | 749 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 750 | //! @brief Set the GPOLYL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 751 | #define BW_CRC_GPOLYL_GPOLYL(v) (HW_CRC_GPOLYL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 752 | #endif |
mbed_official | 146:f64d43ff0c18 | 753 | //@} |
mbed_official | 146:f64d43ff0c18 | 754 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 755 | // HW_CRC_GPOLYH - CRC_GPOLYH register. |
mbed_official | 146:f64d43ff0c18 | 756 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 757 | |
mbed_official | 146:f64d43ff0c18 | 758 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 759 | /*! |
mbed_official | 146:f64d43ff0c18 | 760 | * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW) |
mbed_official | 146:f64d43ff0c18 | 761 | * |
mbed_official | 146:f64d43ff0c18 | 762 | * Reset value: 0xFFFFU |
mbed_official | 146:f64d43ff0c18 | 763 | */ |
mbed_official | 146:f64d43ff0c18 | 764 | typedef union _hw_crc_gpolyh |
mbed_official | 146:f64d43ff0c18 | 765 | { |
mbed_official | 146:f64d43ff0c18 | 766 | uint16_t U; |
mbed_official | 146:f64d43ff0c18 | 767 | struct _hw_crc_gpolyh_bitfields |
mbed_official | 146:f64d43ff0c18 | 768 | { |
mbed_official | 146:f64d43ff0c18 | 769 | uint16_t GPOLYH : 16; //!< [15:0] POLYH stores the high 16 bits of |
mbed_official | 146:f64d43ff0c18 | 770 | //! the 16/32 bit CRC polynomial value |
mbed_official | 146:f64d43ff0c18 | 771 | } B; |
mbed_official | 146:f64d43ff0c18 | 772 | } hw_crc_gpolyh_t; |
mbed_official | 146:f64d43ff0c18 | 773 | #endif |
mbed_official | 146:f64d43ff0c18 | 774 | |
mbed_official | 146:f64d43ff0c18 | 775 | /*! |
mbed_official | 146:f64d43ff0c18 | 776 | * @name Constants and macros for entire CRC_GPOLYH register |
mbed_official | 146:f64d43ff0c18 | 777 | */ |
mbed_official | 146:f64d43ff0c18 | 778 | //@{ |
mbed_official | 146:f64d43ff0c18 | 779 | #define HW_CRC_GPOLYH_ADDR (REGS_CRC_BASE + 0x6U) |
mbed_official | 146:f64d43ff0c18 | 780 | |
mbed_official | 146:f64d43ff0c18 | 781 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 782 | #define HW_CRC_GPOLYH (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR) |
mbed_official | 146:f64d43ff0c18 | 783 | #define HW_CRC_GPOLYH_RD() (HW_CRC_GPOLYH.U) |
mbed_official | 146:f64d43ff0c18 | 784 | #define HW_CRC_GPOLYH_WR(v) (HW_CRC_GPOLYH.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 785 | #define HW_CRC_GPOLYH_SET(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 786 | #define HW_CRC_GPOLYH_CLR(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 787 | #define HW_CRC_GPOLYH_TOG(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 788 | #endif |
mbed_official | 146:f64d43ff0c18 | 789 | //@} |
mbed_official | 146:f64d43ff0c18 | 790 | |
mbed_official | 146:f64d43ff0c18 | 791 | /* |
mbed_official | 146:f64d43ff0c18 | 792 | * Constants & macros for individual CRC_GPOLYH bitfields |
mbed_official | 146:f64d43ff0c18 | 793 | */ |
mbed_official | 146:f64d43ff0c18 | 794 | |
mbed_official | 146:f64d43ff0c18 | 795 | /*! |
mbed_official | 146:f64d43ff0c18 | 796 | * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 797 | */ |
mbed_official | 146:f64d43ff0c18 | 798 | //@{ |
mbed_official | 146:f64d43ff0c18 | 799 | #define BP_CRC_GPOLYH_GPOLYH (0U) //!< Bit position for CRC_GPOLYH_GPOLYH. |
mbed_official | 146:f64d43ff0c18 | 800 | #define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) //!< Bit mask for CRC_GPOLYH_GPOLYH. |
mbed_official | 146:f64d43ff0c18 | 801 | #define BS_CRC_GPOLYH_GPOLYH (16U) //!< Bit field size in bits for CRC_GPOLYH_GPOLYH. |
mbed_official | 146:f64d43ff0c18 | 802 | |
mbed_official | 146:f64d43ff0c18 | 803 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 804 | //! @brief Read current value of the CRC_GPOLYH_GPOLYH field. |
mbed_official | 146:f64d43ff0c18 | 805 | #define BR_CRC_GPOLYH_GPOLYH (HW_CRC_GPOLYH.U) |
mbed_official | 146:f64d43ff0c18 | 806 | #endif |
mbed_official | 146:f64d43ff0c18 | 807 | |
mbed_official | 146:f64d43ff0c18 | 808 | //! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. |
mbed_official | 146:f64d43ff0c18 | 809 | #define BF_CRC_GPOLYH_GPOLYH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYH_GPOLYH), uint16_t) & BM_CRC_GPOLYH_GPOLYH) |
mbed_official | 146:f64d43ff0c18 | 810 | |
mbed_official | 146:f64d43ff0c18 | 811 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 812 | //! @brief Set the GPOLYH field to a new value. |
mbed_official | 146:f64d43ff0c18 | 813 | #define BW_CRC_GPOLYH_GPOLYH(v) (HW_CRC_GPOLYH_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 814 | #endif |
mbed_official | 146:f64d43ff0c18 | 815 | //@} |
mbed_official | 146:f64d43ff0c18 | 816 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 817 | // HW_CRC_GPOLYLL - CRC_GPOLYLL register. |
mbed_official | 146:f64d43ff0c18 | 818 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 819 | |
mbed_official | 146:f64d43ff0c18 | 820 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 821 | /*! |
mbed_official | 146:f64d43ff0c18 | 822 | * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW) |
mbed_official | 146:f64d43ff0c18 | 823 | * |
mbed_official | 146:f64d43ff0c18 | 824 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 825 | */ |
mbed_official | 146:f64d43ff0c18 | 826 | typedef union _hw_crc_gpolyll |
mbed_official | 146:f64d43ff0c18 | 827 | { |
mbed_official | 146:f64d43ff0c18 | 828 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 829 | struct _hw_crc_gpolyll_bitfields |
mbed_official | 146:f64d43ff0c18 | 830 | { |
mbed_official | 146:f64d43ff0c18 | 831 | uint8_t GPOLYLL : 8; //!< [7:0] POLYLL stores the first 8 bits of the |
mbed_official | 146:f64d43ff0c18 | 832 | //! 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 833 | } B; |
mbed_official | 146:f64d43ff0c18 | 834 | } hw_crc_gpolyll_t; |
mbed_official | 146:f64d43ff0c18 | 835 | #endif |
mbed_official | 146:f64d43ff0c18 | 836 | |
mbed_official | 146:f64d43ff0c18 | 837 | /*! |
mbed_official | 146:f64d43ff0c18 | 838 | * @name Constants and macros for entire CRC_GPOLYLL register |
mbed_official | 146:f64d43ff0c18 | 839 | */ |
mbed_official | 146:f64d43ff0c18 | 840 | //@{ |
mbed_official | 146:f64d43ff0c18 | 841 | #define HW_CRC_GPOLYLL_ADDR (REGS_CRC_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 842 | |
mbed_official | 146:f64d43ff0c18 | 843 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 844 | #define HW_CRC_GPOLYLL (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 845 | #define HW_CRC_GPOLYLL_RD() (HW_CRC_GPOLYLL.U) |
mbed_official | 146:f64d43ff0c18 | 846 | #define HW_CRC_GPOLYLL_WR(v) (HW_CRC_GPOLYLL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 847 | #define HW_CRC_GPOLYLL_SET(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 848 | #define HW_CRC_GPOLYLL_CLR(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 849 | #define HW_CRC_GPOLYLL_TOG(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 850 | #endif |
mbed_official | 146:f64d43ff0c18 | 851 | //@} |
mbed_official | 146:f64d43ff0c18 | 852 | |
mbed_official | 146:f64d43ff0c18 | 853 | /* |
mbed_official | 146:f64d43ff0c18 | 854 | * Constants & macros for individual CRC_GPOLYLL bitfields |
mbed_official | 146:f64d43ff0c18 | 855 | */ |
mbed_official | 146:f64d43ff0c18 | 856 | |
mbed_official | 146:f64d43ff0c18 | 857 | /*! |
mbed_official | 146:f64d43ff0c18 | 858 | * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 859 | */ |
mbed_official | 146:f64d43ff0c18 | 860 | //@{ |
mbed_official | 146:f64d43ff0c18 | 861 | #define BP_CRC_GPOLYLL_GPOLYLL (0U) //!< Bit position for CRC_GPOLYLL_GPOLYLL. |
mbed_official | 146:f64d43ff0c18 | 862 | #define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) //!< Bit mask for CRC_GPOLYLL_GPOLYLL. |
mbed_official | 146:f64d43ff0c18 | 863 | #define BS_CRC_GPOLYLL_GPOLYLL (8U) //!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. |
mbed_official | 146:f64d43ff0c18 | 864 | |
mbed_official | 146:f64d43ff0c18 | 865 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 866 | //! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. |
mbed_official | 146:f64d43ff0c18 | 867 | #define BR_CRC_GPOLYLL_GPOLYLL (HW_CRC_GPOLYLL.U) |
mbed_official | 146:f64d43ff0c18 | 868 | #endif |
mbed_official | 146:f64d43ff0c18 | 869 | |
mbed_official | 146:f64d43ff0c18 | 870 | //! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. |
mbed_official | 146:f64d43ff0c18 | 871 | #define BF_CRC_GPOLYLL_GPOLYLL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLL_GPOLYLL), uint8_t) & BM_CRC_GPOLYLL_GPOLYLL) |
mbed_official | 146:f64d43ff0c18 | 872 | |
mbed_official | 146:f64d43ff0c18 | 873 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 874 | //! @brief Set the GPOLYLL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 875 | #define BW_CRC_GPOLYLL_GPOLYLL(v) (HW_CRC_GPOLYLL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 876 | #endif |
mbed_official | 146:f64d43ff0c18 | 877 | //@} |
mbed_official | 146:f64d43ff0c18 | 878 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 879 | // HW_CRC_GPOLYLU - CRC_GPOLYLU register. |
mbed_official | 146:f64d43ff0c18 | 880 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 881 | |
mbed_official | 146:f64d43ff0c18 | 882 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 883 | /*! |
mbed_official | 146:f64d43ff0c18 | 884 | * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW) |
mbed_official | 146:f64d43ff0c18 | 885 | * |
mbed_official | 146:f64d43ff0c18 | 886 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 887 | */ |
mbed_official | 146:f64d43ff0c18 | 888 | typedef union _hw_crc_gpolylu |
mbed_official | 146:f64d43ff0c18 | 889 | { |
mbed_official | 146:f64d43ff0c18 | 890 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 891 | struct _hw_crc_gpolylu_bitfields |
mbed_official | 146:f64d43ff0c18 | 892 | { |
mbed_official | 146:f64d43ff0c18 | 893 | uint8_t GPOLYLU : 8; //!< [7:0] POLYLL stores the second 8 bits of |
mbed_official | 146:f64d43ff0c18 | 894 | //! the 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 895 | } B; |
mbed_official | 146:f64d43ff0c18 | 896 | } hw_crc_gpolylu_t; |
mbed_official | 146:f64d43ff0c18 | 897 | #endif |
mbed_official | 146:f64d43ff0c18 | 898 | |
mbed_official | 146:f64d43ff0c18 | 899 | /*! |
mbed_official | 146:f64d43ff0c18 | 900 | * @name Constants and macros for entire CRC_GPOLYLU register |
mbed_official | 146:f64d43ff0c18 | 901 | */ |
mbed_official | 146:f64d43ff0c18 | 902 | //@{ |
mbed_official | 146:f64d43ff0c18 | 903 | #define HW_CRC_GPOLYLU_ADDR (REGS_CRC_BASE + 0x5U) |
mbed_official | 146:f64d43ff0c18 | 904 | |
mbed_official | 146:f64d43ff0c18 | 905 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 906 | #define HW_CRC_GPOLYLU (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR) |
mbed_official | 146:f64d43ff0c18 | 907 | #define HW_CRC_GPOLYLU_RD() (HW_CRC_GPOLYLU.U) |
mbed_official | 146:f64d43ff0c18 | 908 | #define HW_CRC_GPOLYLU_WR(v) (HW_CRC_GPOLYLU.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 909 | #define HW_CRC_GPOLYLU_SET(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 910 | #define HW_CRC_GPOLYLU_CLR(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 911 | #define HW_CRC_GPOLYLU_TOG(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 912 | #endif |
mbed_official | 146:f64d43ff0c18 | 913 | //@} |
mbed_official | 146:f64d43ff0c18 | 914 | |
mbed_official | 146:f64d43ff0c18 | 915 | /* |
mbed_official | 146:f64d43ff0c18 | 916 | * Constants & macros for individual CRC_GPOLYLU bitfields |
mbed_official | 146:f64d43ff0c18 | 917 | */ |
mbed_official | 146:f64d43ff0c18 | 918 | |
mbed_official | 146:f64d43ff0c18 | 919 | /*! |
mbed_official | 146:f64d43ff0c18 | 920 | * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 921 | */ |
mbed_official | 146:f64d43ff0c18 | 922 | //@{ |
mbed_official | 146:f64d43ff0c18 | 923 | #define BP_CRC_GPOLYLU_GPOLYLU (0U) //!< Bit position for CRC_GPOLYLU_GPOLYLU. |
mbed_official | 146:f64d43ff0c18 | 924 | #define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) //!< Bit mask for CRC_GPOLYLU_GPOLYLU. |
mbed_official | 146:f64d43ff0c18 | 925 | #define BS_CRC_GPOLYLU_GPOLYLU (8U) //!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. |
mbed_official | 146:f64d43ff0c18 | 926 | |
mbed_official | 146:f64d43ff0c18 | 927 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 928 | //! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. |
mbed_official | 146:f64d43ff0c18 | 929 | #define BR_CRC_GPOLYLU_GPOLYLU (HW_CRC_GPOLYLU.U) |
mbed_official | 146:f64d43ff0c18 | 930 | #endif |
mbed_official | 146:f64d43ff0c18 | 931 | |
mbed_official | 146:f64d43ff0c18 | 932 | //! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. |
mbed_official | 146:f64d43ff0c18 | 933 | #define BF_CRC_GPOLYLU_GPOLYLU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLU_GPOLYLU), uint8_t) & BM_CRC_GPOLYLU_GPOLYLU) |
mbed_official | 146:f64d43ff0c18 | 934 | |
mbed_official | 146:f64d43ff0c18 | 935 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 936 | //! @brief Set the GPOLYLU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 937 | #define BW_CRC_GPOLYLU_GPOLYLU(v) (HW_CRC_GPOLYLU_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 938 | #endif |
mbed_official | 146:f64d43ff0c18 | 939 | //@} |
mbed_official | 146:f64d43ff0c18 | 940 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 941 | // HW_CRC_GPOLYHL - CRC_GPOLYHL register. |
mbed_official | 146:f64d43ff0c18 | 942 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 943 | |
mbed_official | 146:f64d43ff0c18 | 944 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 945 | /*! |
mbed_official | 146:f64d43ff0c18 | 946 | * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW) |
mbed_official | 146:f64d43ff0c18 | 947 | * |
mbed_official | 146:f64d43ff0c18 | 948 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 949 | */ |
mbed_official | 146:f64d43ff0c18 | 950 | typedef union _hw_crc_gpolyhl |
mbed_official | 146:f64d43ff0c18 | 951 | { |
mbed_official | 146:f64d43ff0c18 | 952 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 953 | struct _hw_crc_gpolyhl_bitfields |
mbed_official | 146:f64d43ff0c18 | 954 | { |
mbed_official | 146:f64d43ff0c18 | 955 | uint8_t GPOLYHL : 8; //!< [7:0] POLYHL stores the third 8 bits of the |
mbed_official | 146:f64d43ff0c18 | 956 | //! 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 957 | } B; |
mbed_official | 146:f64d43ff0c18 | 958 | } hw_crc_gpolyhl_t; |
mbed_official | 146:f64d43ff0c18 | 959 | #endif |
mbed_official | 146:f64d43ff0c18 | 960 | |
mbed_official | 146:f64d43ff0c18 | 961 | /*! |
mbed_official | 146:f64d43ff0c18 | 962 | * @name Constants and macros for entire CRC_GPOLYHL register |
mbed_official | 146:f64d43ff0c18 | 963 | */ |
mbed_official | 146:f64d43ff0c18 | 964 | //@{ |
mbed_official | 146:f64d43ff0c18 | 965 | #define HW_CRC_GPOLYHL_ADDR (REGS_CRC_BASE + 0x6U) |
mbed_official | 146:f64d43ff0c18 | 966 | |
mbed_official | 146:f64d43ff0c18 | 967 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 968 | #define HW_CRC_GPOLYHL (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 969 | #define HW_CRC_GPOLYHL_RD() (HW_CRC_GPOLYHL.U) |
mbed_official | 146:f64d43ff0c18 | 970 | #define HW_CRC_GPOLYHL_WR(v) (HW_CRC_GPOLYHL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 971 | #define HW_CRC_GPOLYHL_SET(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 972 | #define HW_CRC_GPOLYHL_CLR(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 973 | #define HW_CRC_GPOLYHL_TOG(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 974 | #endif |
mbed_official | 146:f64d43ff0c18 | 975 | //@} |
mbed_official | 146:f64d43ff0c18 | 976 | |
mbed_official | 146:f64d43ff0c18 | 977 | /* |
mbed_official | 146:f64d43ff0c18 | 978 | * Constants & macros for individual CRC_GPOLYHL bitfields |
mbed_official | 146:f64d43ff0c18 | 979 | */ |
mbed_official | 146:f64d43ff0c18 | 980 | |
mbed_official | 146:f64d43ff0c18 | 981 | /*! |
mbed_official | 146:f64d43ff0c18 | 982 | * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 983 | */ |
mbed_official | 146:f64d43ff0c18 | 984 | //@{ |
mbed_official | 146:f64d43ff0c18 | 985 | #define BP_CRC_GPOLYHL_GPOLYHL (0U) //!< Bit position for CRC_GPOLYHL_GPOLYHL. |
mbed_official | 146:f64d43ff0c18 | 986 | #define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) //!< Bit mask for CRC_GPOLYHL_GPOLYHL. |
mbed_official | 146:f64d43ff0c18 | 987 | #define BS_CRC_GPOLYHL_GPOLYHL (8U) //!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. |
mbed_official | 146:f64d43ff0c18 | 988 | |
mbed_official | 146:f64d43ff0c18 | 989 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 990 | //! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. |
mbed_official | 146:f64d43ff0c18 | 991 | #define BR_CRC_GPOLYHL_GPOLYHL (HW_CRC_GPOLYHL.U) |
mbed_official | 146:f64d43ff0c18 | 992 | #endif |
mbed_official | 146:f64d43ff0c18 | 993 | |
mbed_official | 146:f64d43ff0c18 | 994 | //! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. |
mbed_official | 146:f64d43ff0c18 | 995 | #define BF_CRC_GPOLYHL_GPOLYHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHL_GPOLYHL), uint8_t) & BM_CRC_GPOLYHL_GPOLYHL) |
mbed_official | 146:f64d43ff0c18 | 996 | |
mbed_official | 146:f64d43ff0c18 | 997 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 998 | //! @brief Set the GPOLYHL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 999 | #define BW_CRC_GPOLYHL_GPOLYHL(v) (HW_CRC_GPOLYHL_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1000 | #endif |
mbed_official | 146:f64d43ff0c18 | 1001 | //@} |
mbed_official | 146:f64d43ff0c18 | 1002 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1003 | // HW_CRC_GPOLYHU - CRC_GPOLYHU register. |
mbed_official | 146:f64d43ff0c18 | 1004 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1005 | |
mbed_official | 146:f64d43ff0c18 | 1006 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1007 | /*! |
mbed_official | 146:f64d43ff0c18 | 1008 | * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW) |
mbed_official | 146:f64d43ff0c18 | 1009 | * |
mbed_official | 146:f64d43ff0c18 | 1010 | * Reset value: 0xFFU |
mbed_official | 146:f64d43ff0c18 | 1011 | */ |
mbed_official | 146:f64d43ff0c18 | 1012 | typedef union _hw_crc_gpolyhu |
mbed_official | 146:f64d43ff0c18 | 1013 | { |
mbed_official | 146:f64d43ff0c18 | 1014 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1015 | struct _hw_crc_gpolyhu_bitfields |
mbed_official | 146:f64d43ff0c18 | 1016 | { |
mbed_official | 146:f64d43ff0c18 | 1017 | uint8_t GPOLYHU : 8; //!< [7:0] POLYHU stores the fourth 8 bits of |
mbed_official | 146:f64d43ff0c18 | 1018 | //! the 32 bit CRC |
mbed_official | 146:f64d43ff0c18 | 1019 | } B; |
mbed_official | 146:f64d43ff0c18 | 1020 | } hw_crc_gpolyhu_t; |
mbed_official | 146:f64d43ff0c18 | 1021 | #endif |
mbed_official | 146:f64d43ff0c18 | 1022 | |
mbed_official | 146:f64d43ff0c18 | 1023 | /*! |
mbed_official | 146:f64d43ff0c18 | 1024 | * @name Constants and macros for entire CRC_GPOLYHU register |
mbed_official | 146:f64d43ff0c18 | 1025 | */ |
mbed_official | 146:f64d43ff0c18 | 1026 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1027 | #define HW_CRC_GPOLYHU_ADDR (REGS_CRC_BASE + 0x7U) |
mbed_official | 146:f64d43ff0c18 | 1028 | |
mbed_official | 146:f64d43ff0c18 | 1029 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1030 | #define HW_CRC_GPOLYHU (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1031 | #define HW_CRC_GPOLYHU_RD() (HW_CRC_GPOLYHU.U) |
mbed_official | 146:f64d43ff0c18 | 1032 | #define HW_CRC_GPOLYHU_WR(v) (HW_CRC_GPOLYHU.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1033 | #define HW_CRC_GPOLYHU_SET(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1034 | #define HW_CRC_GPOLYHU_CLR(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1035 | #define HW_CRC_GPOLYHU_TOG(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1036 | #endif |
mbed_official | 146:f64d43ff0c18 | 1037 | //@} |
mbed_official | 146:f64d43ff0c18 | 1038 | |
mbed_official | 146:f64d43ff0c18 | 1039 | /* |
mbed_official | 146:f64d43ff0c18 | 1040 | * Constants & macros for individual CRC_GPOLYHU bitfields |
mbed_official | 146:f64d43ff0c18 | 1041 | */ |
mbed_official | 146:f64d43ff0c18 | 1042 | |
mbed_official | 146:f64d43ff0c18 | 1043 | /*! |
mbed_official | 146:f64d43ff0c18 | 1044 | * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1045 | */ |
mbed_official | 146:f64d43ff0c18 | 1046 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1047 | #define BP_CRC_GPOLYHU_GPOLYHU (0U) //!< Bit position for CRC_GPOLYHU_GPOLYHU. |
mbed_official | 146:f64d43ff0c18 | 1048 | #define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) //!< Bit mask for CRC_GPOLYHU_GPOLYHU. |
mbed_official | 146:f64d43ff0c18 | 1049 | #define BS_CRC_GPOLYHU_GPOLYHU (8U) //!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. |
mbed_official | 146:f64d43ff0c18 | 1050 | |
mbed_official | 146:f64d43ff0c18 | 1051 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1052 | //! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. |
mbed_official | 146:f64d43ff0c18 | 1053 | #define BR_CRC_GPOLYHU_GPOLYHU (HW_CRC_GPOLYHU.U) |
mbed_official | 146:f64d43ff0c18 | 1054 | #endif |
mbed_official | 146:f64d43ff0c18 | 1055 | |
mbed_official | 146:f64d43ff0c18 | 1056 | //! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. |
mbed_official | 146:f64d43ff0c18 | 1057 | #define BF_CRC_GPOLYHU_GPOLYHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHU_GPOLYHU), uint8_t) & BM_CRC_GPOLYHU_GPOLYHU) |
mbed_official | 146:f64d43ff0c18 | 1058 | |
mbed_official | 146:f64d43ff0c18 | 1059 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1060 | //! @brief Set the GPOLYHU field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1061 | #define BW_CRC_GPOLYHU_GPOLYHU(v) (HW_CRC_GPOLYHU_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1062 | #endif |
mbed_official | 146:f64d43ff0c18 | 1063 | //@} |
mbed_official | 146:f64d43ff0c18 | 1064 | |
mbed_official | 146:f64d43ff0c18 | 1065 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1066 | // HW_CRC_CTRL - CRC Control register |
mbed_official | 146:f64d43ff0c18 | 1067 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1068 | |
mbed_official | 146:f64d43ff0c18 | 1069 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1070 | /*! |
mbed_official | 146:f64d43ff0c18 | 1071 | * @brief HW_CRC_CTRL - CRC Control register (RW) |
mbed_official | 146:f64d43ff0c18 | 1072 | * |
mbed_official | 146:f64d43ff0c18 | 1073 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 1074 | * |
mbed_official | 146:f64d43ff0c18 | 1075 | * This register controls the configuration and working of the CRC module. |
mbed_official | 146:f64d43ff0c18 | 1076 | * Appropriate bits must be set before starting a new CRC calculation. A new CRC |
mbed_official | 146:f64d43ff0c18 | 1077 | * calculation is initialized by asserting CTRL[WAS] and then writing the seed into |
mbed_official | 146:f64d43ff0c18 | 1078 | * the CRC data register. |
mbed_official | 146:f64d43ff0c18 | 1079 | */ |
mbed_official | 146:f64d43ff0c18 | 1080 | typedef union _hw_crc_ctrl |
mbed_official | 146:f64d43ff0c18 | 1081 | { |
mbed_official | 146:f64d43ff0c18 | 1082 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1083 | struct _hw_crc_ctrl_bitfields |
mbed_official | 146:f64d43ff0c18 | 1084 | { |
mbed_official | 146:f64d43ff0c18 | 1085 | uint32_t RESERVED0 : 24; //!< [23:0] |
mbed_official | 146:f64d43ff0c18 | 1086 | uint32_t TCRC : 1; //!< [24] |
mbed_official | 146:f64d43ff0c18 | 1087 | uint32_t WAS : 1; //!< [25] Write CRC Data Register As Seed |
mbed_official | 146:f64d43ff0c18 | 1088 | uint32_t FXOR : 1; //!< [26] Complement Read Of CRC Data Register |
mbed_official | 146:f64d43ff0c18 | 1089 | uint32_t RESERVED1 : 1; //!< [27] |
mbed_official | 146:f64d43ff0c18 | 1090 | uint32_t TOTR : 2; //!< [29:28] Type Of Transpose For Read |
mbed_official | 146:f64d43ff0c18 | 1091 | uint32_t TOT : 2; //!< [31:30] Type Of Transpose For Writes |
mbed_official | 146:f64d43ff0c18 | 1092 | } B; |
mbed_official | 146:f64d43ff0c18 | 1093 | } hw_crc_ctrl_t; |
mbed_official | 146:f64d43ff0c18 | 1094 | #endif |
mbed_official | 146:f64d43ff0c18 | 1095 | |
mbed_official | 146:f64d43ff0c18 | 1096 | /*! |
mbed_official | 146:f64d43ff0c18 | 1097 | * @name Constants and macros for entire CRC_CTRL register |
mbed_official | 146:f64d43ff0c18 | 1098 | */ |
mbed_official | 146:f64d43ff0c18 | 1099 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1100 | #define HW_CRC_CTRL_ADDR (REGS_CRC_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 1101 | |
mbed_official | 146:f64d43ff0c18 | 1102 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1103 | #define HW_CRC_CTRL (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1104 | #define HW_CRC_CTRL_RD() (HW_CRC_CTRL.U) |
mbed_official | 146:f64d43ff0c18 | 1105 | #define HW_CRC_CTRL_WR(v) (HW_CRC_CTRL.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1106 | #define HW_CRC_CTRL_SET(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1107 | #define HW_CRC_CTRL_CLR(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1108 | #define HW_CRC_CTRL_TOG(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1109 | #endif |
mbed_official | 146:f64d43ff0c18 | 1110 | //@} |
mbed_official | 146:f64d43ff0c18 | 1111 | |
mbed_official | 146:f64d43ff0c18 | 1112 | /* |
mbed_official | 146:f64d43ff0c18 | 1113 | * Constants & macros for individual CRC_CTRL bitfields |
mbed_official | 146:f64d43ff0c18 | 1114 | */ |
mbed_official | 146:f64d43ff0c18 | 1115 | |
mbed_official | 146:f64d43ff0c18 | 1116 | /*! |
mbed_official | 146:f64d43ff0c18 | 1117 | * @name Register CRC_CTRL, field TCRC[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 1118 | * |
mbed_official | 146:f64d43ff0c18 | 1119 | * Width of CRC protocol. |
mbed_official | 146:f64d43ff0c18 | 1120 | * |
mbed_official | 146:f64d43ff0c18 | 1121 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1122 | * - 0 - 16-bit CRC protocol. |
mbed_official | 146:f64d43ff0c18 | 1123 | * - 1 - 32-bit CRC protocol. |
mbed_official | 146:f64d43ff0c18 | 1124 | */ |
mbed_official | 146:f64d43ff0c18 | 1125 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1126 | #define BP_CRC_CTRL_TCRC (24U) //!< Bit position for CRC_CTRL_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1127 | #define BM_CRC_CTRL_TCRC (0x01000000U) //!< Bit mask for CRC_CTRL_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1128 | #define BS_CRC_CTRL_TCRC (1U) //!< Bit field size in bits for CRC_CTRL_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1129 | |
mbed_official | 146:f64d43ff0c18 | 1130 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1131 | //! @brief Read current value of the CRC_CTRL_TCRC field. |
mbed_official | 146:f64d43ff0c18 | 1132 | #define BR_CRC_CTRL_TCRC (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC)) |
mbed_official | 146:f64d43ff0c18 | 1133 | #endif |
mbed_official | 146:f64d43ff0c18 | 1134 | |
mbed_official | 146:f64d43ff0c18 | 1135 | //! @brief Format value for bitfield CRC_CTRL_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1136 | #define BF_CRC_CTRL_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TCRC), uint32_t) & BM_CRC_CTRL_TCRC) |
mbed_official | 146:f64d43ff0c18 | 1137 | |
mbed_official | 146:f64d43ff0c18 | 1138 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1139 | //! @brief Set the TCRC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1140 | #define BW_CRC_CTRL_TCRC(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1141 | #endif |
mbed_official | 146:f64d43ff0c18 | 1142 | //@} |
mbed_official | 146:f64d43ff0c18 | 1143 | |
mbed_official | 146:f64d43ff0c18 | 1144 | /*! |
mbed_official | 146:f64d43ff0c18 | 1145 | * @name Register CRC_CTRL, field WAS[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 1146 | * |
mbed_official | 146:f64d43ff0c18 | 1147 | * When asserted, a value written to the CRC data register is considered a seed |
mbed_official | 146:f64d43ff0c18 | 1148 | * value. When deasserted, a value written to the CRC data register is taken as |
mbed_official | 146:f64d43ff0c18 | 1149 | * data for CRC computation. |
mbed_official | 146:f64d43ff0c18 | 1150 | * |
mbed_official | 146:f64d43ff0c18 | 1151 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1152 | * - 0 - Writes to the CRC data register are data values. |
mbed_official | 146:f64d43ff0c18 | 1153 | * - 1 - Writes to the CRC data register are seed values. |
mbed_official | 146:f64d43ff0c18 | 1154 | */ |
mbed_official | 146:f64d43ff0c18 | 1155 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1156 | #define BP_CRC_CTRL_WAS (25U) //!< Bit position for CRC_CTRL_WAS. |
mbed_official | 146:f64d43ff0c18 | 1157 | #define BM_CRC_CTRL_WAS (0x02000000U) //!< Bit mask for CRC_CTRL_WAS. |
mbed_official | 146:f64d43ff0c18 | 1158 | #define BS_CRC_CTRL_WAS (1U) //!< Bit field size in bits for CRC_CTRL_WAS. |
mbed_official | 146:f64d43ff0c18 | 1159 | |
mbed_official | 146:f64d43ff0c18 | 1160 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1161 | //! @brief Read current value of the CRC_CTRL_WAS field. |
mbed_official | 146:f64d43ff0c18 | 1162 | #define BR_CRC_CTRL_WAS (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS)) |
mbed_official | 146:f64d43ff0c18 | 1163 | #endif |
mbed_official | 146:f64d43ff0c18 | 1164 | |
mbed_official | 146:f64d43ff0c18 | 1165 | //! @brief Format value for bitfield CRC_CTRL_WAS. |
mbed_official | 146:f64d43ff0c18 | 1166 | #define BF_CRC_CTRL_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_WAS), uint32_t) & BM_CRC_CTRL_WAS) |
mbed_official | 146:f64d43ff0c18 | 1167 | |
mbed_official | 146:f64d43ff0c18 | 1168 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1169 | //! @brief Set the WAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1170 | #define BW_CRC_CTRL_WAS(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1171 | #endif |
mbed_official | 146:f64d43ff0c18 | 1172 | //@} |
mbed_official | 146:f64d43ff0c18 | 1173 | |
mbed_official | 146:f64d43ff0c18 | 1174 | /*! |
mbed_official | 146:f64d43ff0c18 | 1175 | * @name Register CRC_CTRL, field FXOR[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 1176 | * |
mbed_official | 146:f64d43ff0c18 | 1177 | * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or |
mbed_official | 146:f64d43ff0c18 | 1178 | * 0xFFFF. Asserting this bit enables on the fly complementing of read data. |
mbed_official | 146:f64d43ff0c18 | 1179 | * |
mbed_official | 146:f64d43ff0c18 | 1180 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1181 | * - 0 - No XOR on reading. |
mbed_official | 146:f64d43ff0c18 | 1182 | * - 1 - Invert or complement the read value of the CRC Data register. |
mbed_official | 146:f64d43ff0c18 | 1183 | */ |
mbed_official | 146:f64d43ff0c18 | 1184 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1185 | #define BP_CRC_CTRL_FXOR (26U) //!< Bit position for CRC_CTRL_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1186 | #define BM_CRC_CTRL_FXOR (0x04000000U) //!< Bit mask for CRC_CTRL_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1187 | #define BS_CRC_CTRL_FXOR (1U) //!< Bit field size in bits for CRC_CTRL_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1188 | |
mbed_official | 146:f64d43ff0c18 | 1189 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1190 | //! @brief Read current value of the CRC_CTRL_FXOR field. |
mbed_official | 146:f64d43ff0c18 | 1191 | #define BR_CRC_CTRL_FXOR (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR)) |
mbed_official | 146:f64d43ff0c18 | 1192 | #endif |
mbed_official | 146:f64d43ff0c18 | 1193 | |
mbed_official | 146:f64d43ff0c18 | 1194 | //! @brief Format value for bitfield CRC_CTRL_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1195 | #define BF_CRC_CTRL_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_FXOR), uint32_t) & BM_CRC_CTRL_FXOR) |
mbed_official | 146:f64d43ff0c18 | 1196 | |
mbed_official | 146:f64d43ff0c18 | 1197 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1198 | //! @brief Set the FXOR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1199 | #define BW_CRC_CTRL_FXOR(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1200 | #endif |
mbed_official | 146:f64d43ff0c18 | 1201 | //@} |
mbed_official | 146:f64d43ff0c18 | 1202 | |
mbed_official | 146:f64d43ff0c18 | 1203 | /*! |
mbed_official | 146:f64d43ff0c18 | 1204 | * @name Register CRC_CTRL, field TOTR[29:28] (RW) |
mbed_official | 146:f64d43ff0c18 | 1205 | * |
mbed_official | 146:f64d43ff0c18 | 1206 | * Identifies the transpose configuration of the value read from the CRC Data |
mbed_official | 146:f64d43ff0c18 | 1207 | * register. See the description of the transpose feature for the available |
mbed_official | 146:f64d43ff0c18 | 1208 | * transpose options. |
mbed_official | 146:f64d43ff0c18 | 1209 | * |
mbed_official | 146:f64d43ff0c18 | 1210 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1211 | * - 00 - No transposition. |
mbed_official | 146:f64d43ff0c18 | 1212 | * - 01 - Bits in bytes are transposed; bytes are not transposed. |
mbed_official | 146:f64d43ff0c18 | 1213 | * - 10 - Both bits in bytes and bytes are transposed. |
mbed_official | 146:f64d43ff0c18 | 1214 | * - 11 - Only bytes are transposed; no bits in a byte are transposed. |
mbed_official | 146:f64d43ff0c18 | 1215 | */ |
mbed_official | 146:f64d43ff0c18 | 1216 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1217 | #define BP_CRC_CTRL_TOTR (28U) //!< Bit position for CRC_CTRL_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1218 | #define BM_CRC_CTRL_TOTR (0x30000000U) //!< Bit mask for CRC_CTRL_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1219 | #define BS_CRC_CTRL_TOTR (2U) //!< Bit field size in bits for CRC_CTRL_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1220 | |
mbed_official | 146:f64d43ff0c18 | 1221 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1222 | //! @brief Read current value of the CRC_CTRL_TOTR field. |
mbed_official | 146:f64d43ff0c18 | 1223 | #define BR_CRC_CTRL_TOTR (HW_CRC_CTRL.B.TOTR) |
mbed_official | 146:f64d43ff0c18 | 1224 | #endif |
mbed_official | 146:f64d43ff0c18 | 1225 | |
mbed_official | 146:f64d43ff0c18 | 1226 | //! @brief Format value for bitfield CRC_CTRL_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1227 | #define BF_CRC_CTRL_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOTR), uint32_t) & BM_CRC_CTRL_TOTR) |
mbed_official | 146:f64d43ff0c18 | 1228 | |
mbed_official | 146:f64d43ff0c18 | 1229 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1230 | //! @brief Set the TOTR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1231 | #define BW_CRC_CTRL_TOTR(v) (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v))) |
mbed_official | 146:f64d43ff0c18 | 1232 | #endif |
mbed_official | 146:f64d43ff0c18 | 1233 | //@} |
mbed_official | 146:f64d43ff0c18 | 1234 | |
mbed_official | 146:f64d43ff0c18 | 1235 | /*! |
mbed_official | 146:f64d43ff0c18 | 1236 | * @name Register CRC_CTRL, field TOT[31:30] (RW) |
mbed_official | 146:f64d43ff0c18 | 1237 | * |
mbed_official | 146:f64d43ff0c18 | 1238 | * Defines the transpose configuration of the data written to the CRC data |
mbed_official | 146:f64d43ff0c18 | 1239 | * register. See the description of the transpose feature for the available transpose |
mbed_official | 146:f64d43ff0c18 | 1240 | * options. |
mbed_official | 146:f64d43ff0c18 | 1241 | * |
mbed_official | 146:f64d43ff0c18 | 1242 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1243 | * - 00 - No transposition. |
mbed_official | 146:f64d43ff0c18 | 1244 | * - 01 - Bits in bytes are transposed; bytes are not transposed. |
mbed_official | 146:f64d43ff0c18 | 1245 | * - 10 - Both bits in bytes and bytes are transposed. |
mbed_official | 146:f64d43ff0c18 | 1246 | * - 11 - Only bytes are transposed; no bits in a byte are transposed. |
mbed_official | 146:f64d43ff0c18 | 1247 | */ |
mbed_official | 146:f64d43ff0c18 | 1248 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1249 | #define BP_CRC_CTRL_TOT (30U) //!< Bit position for CRC_CTRL_TOT. |
mbed_official | 146:f64d43ff0c18 | 1250 | #define BM_CRC_CTRL_TOT (0xC0000000U) //!< Bit mask for CRC_CTRL_TOT. |
mbed_official | 146:f64d43ff0c18 | 1251 | #define BS_CRC_CTRL_TOT (2U) //!< Bit field size in bits for CRC_CTRL_TOT. |
mbed_official | 146:f64d43ff0c18 | 1252 | |
mbed_official | 146:f64d43ff0c18 | 1253 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1254 | //! @brief Read current value of the CRC_CTRL_TOT field. |
mbed_official | 146:f64d43ff0c18 | 1255 | #define BR_CRC_CTRL_TOT (HW_CRC_CTRL.B.TOT) |
mbed_official | 146:f64d43ff0c18 | 1256 | #endif |
mbed_official | 146:f64d43ff0c18 | 1257 | |
mbed_official | 146:f64d43ff0c18 | 1258 | //! @brief Format value for bitfield CRC_CTRL_TOT. |
mbed_official | 146:f64d43ff0c18 | 1259 | #define BF_CRC_CTRL_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOT), uint32_t) & BM_CRC_CTRL_TOT) |
mbed_official | 146:f64d43ff0c18 | 1260 | |
mbed_official | 146:f64d43ff0c18 | 1261 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1262 | //! @brief Set the TOT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1263 | #define BW_CRC_CTRL_TOT(v) (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v))) |
mbed_official | 146:f64d43ff0c18 | 1264 | #endif |
mbed_official | 146:f64d43ff0c18 | 1265 | //@} |
mbed_official | 146:f64d43ff0c18 | 1266 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1267 | // HW_CRC_CTRLHU - CRC_CTRLHU register. |
mbed_official | 146:f64d43ff0c18 | 1268 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1269 | |
mbed_official | 146:f64d43ff0c18 | 1270 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1271 | /*! |
mbed_official | 146:f64d43ff0c18 | 1272 | * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW) |
mbed_official | 146:f64d43ff0c18 | 1273 | * |
mbed_official | 146:f64d43ff0c18 | 1274 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1275 | */ |
mbed_official | 146:f64d43ff0c18 | 1276 | typedef union _hw_crc_ctrlhu |
mbed_official | 146:f64d43ff0c18 | 1277 | { |
mbed_official | 146:f64d43ff0c18 | 1278 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1279 | struct _hw_crc_ctrlhu_bitfields |
mbed_official | 146:f64d43ff0c18 | 1280 | { |
mbed_official | 146:f64d43ff0c18 | 1281 | uint8_t TCRC : 1; //!< [0] |
mbed_official | 146:f64d43ff0c18 | 1282 | uint8_t WAS : 1; //!< [1] |
mbed_official | 146:f64d43ff0c18 | 1283 | uint8_t FXOR : 1; //!< [2] |
mbed_official | 146:f64d43ff0c18 | 1284 | uint8_t RESERVED0 : 1; //!< [3] |
mbed_official | 146:f64d43ff0c18 | 1285 | uint8_t TOTR : 2; //!< [5:4] |
mbed_official | 146:f64d43ff0c18 | 1286 | uint8_t TOT : 2; //!< [7:6] |
mbed_official | 146:f64d43ff0c18 | 1287 | } B; |
mbed_official | 146:f64d43ff0c18 | 1288 | } hw_crc_ctrlhu_t; |
mbed_official | 146:f64d43ff0c18 | 1289 | #endif |
mbed_official | 146:f64d43ff0c18 | 1290 | |
mbed_official | 146:f64d43ff0c18 | 1291 | /*! |
mbed_official | 146:f64d43ff0c18 | 1292 | * @name Constants and macros for entire CRC_CTRLHU register |
mbed_official | 146:f64d43ff0c18 | 1293 | */ |
mbed_official | 146:f64d43ff0c18 | 1294 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1295 | #define HW_CRC_CTRLHU_ADDR (REGS_CRC_BASE + 0xBU) |
mbed_official | 146:f64d43ff0c18 | 1296 | |
mbed_official | 146:f64d43ff0c18 | 1297 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1298 | #define HW_CRC_CTRLHU (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1299 | #define HW_CRC_CTRLHU_RD() (HW_CRC_CTRLHU.U) |
mbed_official | 146:f64d43ff0c18 | 1300 | #define HW_CRC_CTRLHU_WR(v) (HW_CRC_CTRLHU.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1301 | #define HW_CRC_CTRLHU_SET(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1302 | #define HW_CRC_CTRLHU_CLR(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1303 | #define HW_CRC_CTRLHU_TOG(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1304 | #endif |
mbed_official | 146:f64d43ff0c18 | 1305 | //@} |
mbed_official | 146:f64d43ff0c18 | 1306 | |
mbed_official | 146:f64d43ff0c18 | 1307 | /* |
mbed_official | 146:f64d43ff0c18 | 1308 | * Constants & macros for individual CRC_CTRLHU bitfields |
mbed_official | 146:f64d43ff0c18 | 1309 | */ |
mbed_official | 146:f64d43ff0c18 | 1310 | |
mbed_official | 146:f64d43ff0c18 | 1311 | /*! |
mbed_official | 146:f64d43ff0c18 | 1312 | * @name Register CRC_CTRLHU, field TCRC[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1313 | * |
mbed_official | 146:f64d43ff0c18 | 1314 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1315 | * - 0 - 16-bit CRC protocol. |
mbed_official | 146:f64d43ff0c18 | 1316 | * - 1 - 32-bit CRC protocol. |
mbed_official | 146:f64d43ff0c18 | 1317 | */ |
mbed_official | 146:f64d43ff0c18 | 1318 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1319 | #define BP_CRC_CTRLHU_TCRC (0U) //!< Bit position for CRC_CTRLHU_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1320 | #define BM_CRC_CTRLHU_TCRC (0x01U) //!< Bit mask for CRC_CTRLHU_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1321 | #define BS_CRC_CTRLHU_TCRC (1U) //!< Bit field size in bits for CRC_CTRLHU_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1322 | |
mbed_official | 146:f64d43ff0c18 | 1323 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1324 | //! @brief Read current value of the CRC_CTRLHU_TCRC field. |
mbed_official | 146:f64d43ff0c18 | 1325 | #define BR_CRC_CTRLHU_TCRC (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC)) |
mbed_official | 146:f64d43ff0c18 | 1326 | #endif |
mbed_official | 146:f64d43ff0c18 | 1327 | |
mbed_official | 146:f64d43ff0c18 | 1328 | //! @brief Format value for bitfield CRC_CTRLHU_TCRC. |
mbed_official | 146:f64d43ff0c18 | 1329 | #define BF_CRC_CTRLHU_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TCRC), uint8_t) & BM_CRC_CTRLHU_TCRC) |
mbed_official | 146:f64d43ff0c18 | 1330 | |
mbed_official | 146:f64d43ff0c18 | 1331 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1332 | //! @brief Set the TCRC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1333 | #define BW_CRC_CTRLHU_TCRC(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1334 | #endif |
mbed_official | 146:f64d43ff0c18 | 1335 | //@} |
mbed_official | 146:f64d43ff0c18 | 1336 | |
mbed_official | 146:f64d43ff0c18 | 1337 | /*! |
mbed_official | 146:f64d43ff0c18 | 1338 | * @name Register CRC_CTRLHU, field WAS[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 1339 | * |
mbed_official | 146:f64d43ff0c18 | 1340 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1341 | * - 0 - Writes to CRC data register are data values. |
mbed_official | 146:f64d43ff0c18 | 1342 | * - 1 - Writes to CRC data reguster are seed values. |
mbed_official | 146:f64d43ff0c18 | 1343 | */ |
mbed_official | 146:f64d43ff0c18 | 1344 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1345 | #define BP_CRC_CTRLHU_WAS (1U) //!< Bit position for CRC_CTRLHU_WAS. |
mbed_official | 146:f64d43ff0c18 | 1346 | #define BM_CRC_CTRLHU_WAS (0x02U) //!< Bit mask for CRC_CTRLHU_WAS. |
mbed_official | 146:f64d43ff0c18 | 1347 | #define BS_CRC_CTRLHU_WAS (1U) //!< Bit field size in bits for CRC_CTRLHU_WAS. |
mbed_official | 146:f64d43ff0c18 | 1348 | |
mbed_official | 146:f64d43ff0c18 | 1349 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1350 | //! @brief Read current value of the CRC_CTRLHU_WAS field. |
mbed_official | 146:f64d43ff0c18 | 1351 | #define BR_CRC_CTRLHU_WAS (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS)) |
mbed_official | 146:f64d43ff0c18 | 1352 | #endif |
mbed_official | 146:f64d43ff0c18 | 1353 | |
mbed_official | 146:f64d43ff0c18 | 1354 | //! @brief Format value for bitfield CRC_CTRLHU_WAS. |
mbed_official | 146:f64d43ff0c18 | 1355 | #define BF_CRC_CTRLHU_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_WAS), uint8_t) & BM_CRC_CTRLHU_WAS) |
mbed_official | 146:f64d43ff0c18 | 1356 | |
mbed_official | 146:f64d43ff0c18 | 1357 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1358 | //! @brief Set the WAS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1359 | #define BW_CRC_CTRLHU_WAS(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1360 | #endif |
mbed_official | 146:f64d43ff0c18 | 1361 | //@} |
mbed_official | 146:f64d43ff0c18 | 1362 | |
mbed_official | 146:f64d43ff0c18 | 1363 | /*! |
mbed_official | 146:f64d43ff0c18 | 1364 | * @name Register CRC_CTRLHU, field FXOR[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 1365 | * |
mbed_official | 146:f64d43ff0c18 | 1366 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1367 | * - 0 - No XOR on reading. |
mbed_official | 146:f64d43ff0c18 | 1368 | * - 1 - Invert or complement the read value of CRC data register. |
mbed_official | 146:f64d43ff0c18 | 1369 | */ |
mbed_official | 146:f64d43ff0c18 | 1370 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1371 | #define BP_CRC_CTRLHU_FXOR (2U) //!< Bit position for CRC_CTRLHU_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1372 | #define BM_CRC_CTRLHU_FXOR (0x04U) //!< Bit mask for CRC_CTRLHU_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1373 | #define BS_CRC_CTRLHU_FXOR (1U) //!< Bit field size in bits for CRC_CTRLHU_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1374 | |
mbed_official | 146:f64d43ff0c18 | 1375 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1376 | //! @brief Read current value of the CRC_CTRLHU_FXOR field. |
mbed_official | 146:f64d43ff0c18 | 1377 | #define BR_CRC_CTRLHU_FXOR (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR)) |
mbed_official | 146:f64d43ff0c18 | 1378 | #endif |
mbed_official | 146:f64d43ff0c18 | 1379 | |
mbed_official | 146:f64d43ff0c18 | 1380 | //! @brief Format value for bitfield CRC_CTRLHU_FXOR. |
mbed_official | 146:f64d43ff0c18 | 1381 | #define BF_CRC_CTRLHU_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_FXOR), uint8_t) & BM_CRC_CTRLHU_FXOR) |
mbed_official | 146:f64d43ff0c18 | 1382 | |
mbed_official | 146:f64d43ff0c18 | 1383 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1384 | //! @brief Set the FXOR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1385 | #define BW_CRC_CTRLHU_FXOR(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1386 | #endif |
mbed_official | 146:f64d43ff0c18 | 1387 | //@} |
mbed_official | 146:f64d43ff0c18 | 1388 | |
mbed_official | 146:f64d43ff0c18 | 1389 | /*! |
mbed_official | 146:f64d43ff0c18 | 1390 | * @name Register CRC_CTRLHU, field TOTR[5:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 1391 | * |
mbed_official | 146:f64d43ff0c18 | 1392 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1393 | * - 00 - No Transposition. |
mbed_official | 146:f64d43ff0c18 | 1394 | * - 01 - Bits in bytes are transposed, bytes are not transposed. |
mbed_official | 146:f64d43ff0c18 | 1395 | * - 10 - Both bits in bytes and bytes are transposed. |
mbed_official | 146:f64d43ff0c18 | 1396 | * - 11 - Only bytes are transposed; no bits in a byte are transposed. |
mbed_official | 146:f64d43ff0c18 | 1397 | */ |
mbed_official | 146:f64d43ff0c18 | 1398 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1399 | #define BP_CRC_CTRLHU_TOTR (4U) //!< Bit position for CRC_CTRLHU_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1400 | #define BM_CRC_CTRLHU_TOTR (0x30U) //!< Bit mask for CRC_CTRLHU_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1401 | #define BS_CRC_CTRLHU_TOTR (2U) //!< Bit field size in bits for CRC_CTRLHU_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1402 | |
mbed_official | 146:f64d43ff0c18 | 1403 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1404 | //! @brief Read current value of the CRC_CTRLHU_TOTR field. |
mbed_official | 146:f64d43ff0c18 | 1405 | #define BR_CRC_CTRLHU_TOTR (HW_CRC_CTRLHU.B.TOTR) |
mbed_official | 146:f64d43ff0c18 | 1406 | #endif |
mbed_official | 146:f64d43ff0c18 | 1407 | |
mbed_official | 146:f64d43ff0c18 | 1408 | //! @brief Format value for bitfield CRC_CTRLHU_TOTR. |
mbed_official | 146:f64d43ff0c18 | 1409 | #define BF_CRC_CTRLHU_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOTR), uint8_t) & BM_CRC_CTRLHU_TOTR) |
mbed_official | 146:f64d43ff0c18 | 1410 | |
mbed_official | 146:f64d43ff0c18 | 1411 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1412 | //! @brief Set the TOTR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1413 | #define BW_CRC_CTRLHU_TOTR(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v))) |
mbed_official | 146:f64d43ff0c18 | 1414 | #endif |
mbed_official | 146:f64d43ff0c18 | 1415 | //@} |
mbed_official | 146:f64d43ff0c18 | 1416 | |
mbed_official | 146:f64d43ff0c18 | 1417 | /*! |
mbed_official | 146:f64d43ff0c18 | 1418 | * @name Register CRC_CTRLHU, field TOT[7:6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1419 | * |
mbed_official | 146:f64d43ff0c18 | 1420 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1421 | * - 00 - No Transposition. |
mbed_official | 146:f64d43ff0c18 | 1422 | * - 01 - Bits in bytes are transposed, bytes are not transposed. |
mbed_official | 146:f64d43ff0c18 | 1423 | * - 10 - Both bits in bytes and bytes are transposed. |
mbed_official | 146:f64d43ff0c18 | 1424 | * - 11 - Only bytes are transposed; no bits in a byte are transposed. |
mbed_official | 146:f64d43ff0c18 | 1425 | */ |
mbed_official | 146:f64d43ff0c18 | 1426 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1427 | #define BP_CRC_CTRLHU_TOT (6U) //!< Bit position for CRC_CTRLHU_TOT. |
mbed_official | 146:f64d43ff0c18 | 1428 | #define BM_CRC_CTRLHU_TOT (0xC0U) //!< Bit mask for CRC_CTRLHU_TOT. |
mbed_official | 146:f64d43ff0c18 | 1429 | #define BS_CRC_CTRLHU_TOT (2U) //!< Bit field size in bits for CRC_CTRLHU_TOT. |
mbed_official | 146:f64d43ff0c18 | 1430 | |
mbed_official | 146:f64d43ff0c18 | 1431 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1432 | //! @brief Read current value of the CRC_CTRLHU_TOT field. |
mbed_official | 146:f64d43ff0c18 | 1433 | #define BR_CRC_CTRLHU_TOT (HW_CRC_CTRLHU.B.TOT) |
mbed_official | 146:f64d43ff0c18 | 1434 | #endif |
mbed_official | 146:f64d43ff0c18 | 1435 | |
mbed_official | 146:f64d43ff0c18 | 1436 | //! @brief Format value for bitfield CRC_CTRLHU_TOT. |
mbed_official | 146:f64d43ff0c18 | 1437 | #define BF_CRC_CTRLHU_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOT), uint8_t) & BM_CRC_CTRLHU_TOT) |
mbed_official | 146:f64d43ff0c18 | 1438 | |
mbed_official | 146:f64d43ff0c18 | 1439 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1440 | //! @brief Set the TOT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1441 | #define BW_CRC_CTRLHU_TOT(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v))) |
mbed_official | 146:f64d43ff0c18 | 1442 | #endif |
mbed_official | 146:f64d43ff0c18 | 1443 | //@} |
mbed_official | 146:f64d43ff0c18 | 1444 | |
mbed_official | 146:f64d43ff0c18 | 1445 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1446 | // hw_crc_t - module struct |
mbed_official | 146:f64d43ff0c18 | 1447 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1448 | /*! |
mbed_official | 146:f64d43ff0c18 | 1449 | * @brief All CRC module registers. |
mbed_official | 146:f64d43ff0c18 | 1450 | */ |
mbed_official | 146:f64d43ff0c18 | 1451 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1452 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 1453 | typedef struct _hw_crc |
mbed_official | 146:f64d43ff0c18 | 1454 | { |
mbed_official | 146:f64d43ff0c18 | 1455 | union { |
mbed_official | 146:f64d43ff0c18 | 1456 | struct { |
mbed_official | 146:f64d43ff0c18 | 1457 | __IO hw_crc_datal_t DATAL; //!< [0x0] CRC_DATAL register. |
mbed_official | 146:f64d43ff0c18 | 1458 | __IO hw_crc_datah_t DATAH; //!< [0x2] CRC_DATAH register. |
mbed_official | 146:f64d43ff0c18 | 1459 | } ACCESS16BIT; |
mbed_official | 146:f64d43ff0c18 | 1460 | struct { |
mbed_official | 146:f64d43ff0c18 | 1461 | __IO hw_crc_datall_t DATALL; //!< [0x0] CRC_DATALL register. |
mbed_official | 146:f64d43ff0c18 | 1462 | __IO hw_crc_datalu_t DATALU; //!< [0x1] CRC_DATALU register. |
mbed_official | 146:f64d43ff0c18 | 1463 | __IO hw_crc_datahl_t DATAHL; //!< [0x2] CRC_DATAHL register. |
mbed_official | 146:f64d43ff0c18 | 1464 | __IO hw_crc_datahu_t DATAHU; //!< [0x3] CRC_DATAHU register. |
mbed_official | 146:f64d43ff0c18 | 1465 | } ACCESS8BIT; |
mbed_official | 146:f64d43ff0c18 | 1466 | __IO hw_crc_data_t DATA; //!< [0x0] CRC Data register |
mbed_official | 146:f64d43ff0c18 | 1467 | }; |
mbed_official | 146:f64d43ff0c18 | 1468 | union { |
mbed_official | 146:f64d43ff0c18 | 1469 | __IO hw_crc_gpoly_t GPOLY; //!< [0x4] CRC Polynomial register |
mbed_official | 146:f64d43ff0c18 | 1470 | struct { |
mbed_official | 146:f64d43ff0c18 | 1471 | __IO hw_crc_gpolyl_t GPOLYL; //!< [0x4] CRC_GPOLYL register. |
mbed_official | 146:f64d43ff0c18 | 1472 | __IO hw_crc_gpolyh_t GPOLYH; //!< [0x6] CRC_GPOLYH register. |
mbed_official | 146:f64d43ff0c18 | 1473 | } GPOLY_ACCESS16BIT; |
mbed_official | 146:f64d43ff0c18 | 1474 | struct { |
mbed_official | 146:f64d43ff0c18 | 1475 | __IO hw_crc_gpolyll_t GPOLYLL; //!< [0x4] CRC_GPOLYLL register. |
mbed_official | 146:f64d43ff0c18 | 1476 | __IO hw_crc_gpolylu_t GPOLYLU; //!< [0x5] CRC_GPOLYLU register. |
mbed_official | 146:f64d43ff0c18 | 1477 | __IO hw_crc_gpolyhl_t GPOLYHL; //!< [0x6] CRC_GPOLYHL register. |
mbed_official | 146:f64d43ff0c18 | 1478 | __IO hw_crc_gpolyhu_t GPOLYHU; //!< [0x7] CRC_GPOLYHU register. |
mbed_official | 146:f64d43ff0c18 | 1479 | } GPOLY_ACCESS8BIT; |
mbed_official | 146:f64d43ff0c18 | 1480 | }; |
mbed_official | 146:f64d43ff0c18 | 1481 | union { |
mbed_official | 146:f64d43ff0c18 | 1482 | __IO hw_crc_ctrl_t CTRL; //!< [0x8] CRC Control register |
mbed_official | 146:f64d43ff0c18 | 1483 | struct { |
mbed_official | 146:f64d43ff0c18 | 1484 | uint8_t _reserved0[3]; |
mbed_official | 146:f64d43ff0c18 | 1485 | __IO hw_crc_ctrlhu_t CTRLHU; //!< [0xB] CRC_CTRLHU register. |
mbed_official | 146:f64d43ff0c18 | 1486 | } CTRL_ACCESS8BIT; |
mbed_official | 146:f64d43ff0c18 | 1487 | }; |
mbed_official | 146:f64d43ff0c18 | 1488 | } hw_crc_t; |
mbed_official | 146:f64d43ff0c18 | 1489 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 1490 | |
mbed_official | 146:f64d43ff0c18 | 1491 | //! @brief Macro to access all CRC registers. |
mbed_official | 146:f64d43ff0c18 | 1492 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 1493 | //! use the '&' operator, like <code>&HW_CRC</code>. |
mbed_official | 146:f64d43ff0c18 | 1494 | #define HW_CRC (*(hw_crc_t *) REGS_CRC_BASE) |
mbed_official | 146:f64d43ff0c18 | 1495 | #endif |
mbed_official | 146:f64d43ff0c18 | 1496 | |
mbed_official | 146:f64d43ff0c18 | 1497 | #endif // __HW_CRC_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 1498 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 1499 | // EOF |