shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC15XX/can_api.c@245:b4dea936db71, 2014-06-30 (annotated)

Committer:
mbed_official
Date:
Mon Jun 30 08:00:09 2014 +0100
Revision:
245:b4dea936db71
Child:
250:a49055e7a707
Synchronized with git revision 6d2c15e80d518718dd1ce6f44299acca1ff63ea3



Full URL: https://github.com/mbedmicro/mbed/commit/6d2c15e80d518718dd1ce6f44299acca1ff63ea3/



[LPC1549] CAN support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 245:b4dea936db71 1 /* mbed Microcontroller Library
mbed_official 245:b4dea936db71 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 245:b4dea936db71 3 *
mbed_official 245:b4dea936db71 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 245:b4dea936db71 5 * you may not use this file except in compliance with the License.
mbed_official 245:b4dea936db71 6 * You may obtain a copy of the License at
mbed_official 245:b4dea936db71 7 *
mbed_official 245:b4dea936db71 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 245:b4dea936db71 9 *
mbed_official 245:b4dea936db71 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 245:b4dea936db71 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 245:b4dea936db71 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 245:b4dea936db71 13 * See the License for the specific language governing permissions and
mbed_official 245:b4dea936db71 14 * limitations under the License.
mbed_official 245:b4dea936db71 15 */
mbed_official 245:b4dea936db71 16
mbed_official 245:b4dea936db71 17 #include "can_api.h"
mbed_official 245:b4dea936db71 18
mbed_official 245:b4dea936db71 19 #include "cmsis.h"
mbed_official 245:b4dea936db71 20 #include "error.h"
mbed_official 245:b4dea936db71 21
mbed_official 245:b4dea936db71 22 #include <math.h>
mbed_official 245:b4dea936db71 23 #include <string.h>
mbed_official 245:b4dea936db71 24
mbed_official 245:b4dea936db71 25 /* Handy defines */
mbed_official 245:b4dea936db71 26 #define MSG_OBJ_MAX 32
mbed_official 245:b4dea936db71 27 #define DLC_MAX 8
mbed_official 245:b4dea936db71 28
mbed_official 245:b4dea936db71 29 #define ID_STD_MASK 0x07FF
mbed_official 245:b4dea936db71 30 #define ID_EXT_MASK 0x1FFFFFFF
mbed_official 245:b4dea936db71 31 #define DLC_MASK 0x0F
mbed_official 245:b4dea936db71 32
mbed_official 245:b4dea936db71 33 #define CANIFn_ARB2_DIR (1UL << 13)
mbed_official 245:b4dea936db71 34 #define CANIFn_ARB2_XTD (1UL << 14)
mbed_official 245:b4dea936db71 35 #define CANIFn_ARB2_MSGVAL (1UL << 15)
mbed_official 245:b4dea936db71 36 #define CANIFn_MSK2_MXTD (1UL << 15)
mbed_official 245:b4dea936db71 37 #define CANIFn_MSK2_MDIR (1UL << 14)
mbed_official 245:b4dea936db71 38 #define CANIFn_MCTRL_EOB (1UL << 7)
mbed_official 245:b4dea936db71 39 #define CANIFn_MCTRL_TXRQST (1UL << 8)
mbed_official 245:b4dea936db71 40 #define CANIFn_MCTRL_RMTEN (1UL << 9)
mbed_official 245:b4dea936db71 41 #define CANIFn_MCTRL_RXIE (1UL << 10)
mbed_official 245:b4dea936db71 42 #define CANIFn_MCTRL_TXIE (1UL << 11)
mbed_official 245:b4dea936db71 43 #define CANIFn_MCTRL_UMASK (1UL << 12)
mbed_official 245:b4dea936db71 44 #define CANIFn_MCTRL_INTPND (1UL << 13)
mbed_official 245:b4dea936db71 45 #define CANIFn_MCTRL_MSGLST (1UL << 14)
mbed_official 245:b4dea936db71 46 #define CANIFn_MCTRL_NEWDAT (1UL << 15)
mbed_official 245:b4dea936db71 47 #define CANIFn_CMDMSK_DATA_B (1UL << 0)
mbed_official 245:b4dea936db71 48 #define CANIFn_CMDMSK_DATA_A (1UL << 1)
mbed_official 245:b4dea936db71 49 #define CANIFn_CMDMSK_TXRQST (1UL << 2)
mbed_official 245:b4dea936db71 50 #define CANIFn_CMDMSK_NEWDAT (1UL << 2)
mbed_official 245:b4dea936db71 51 #define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
mbed_official 245:b4dea936db71 52 #define CANIFn_CMDMSK_CTRL (1UL << 4)
mbed_official 245:b4dea936db71 53 #define CANIFn_CMDMSK_ARB (1UL << 5)
mbed_official 245:b4dea936db71 54 #define CANIFn_CMDMSK_MASK (1UL << 6)
mbed_official 245:b4dea936db71 55 #define CANIFn_CMDMSK_WR (1UL << 7)
mbed_official 245:b4dea936db71 56 #define CANIFn_CMDMSK_RD (0UL << 7)
mbed_official 245:b4dea936db71 57 #define CANIFn_CMDREQ_BUSY (1UL << 15)
mbed_official 245:b4dea936db71 58
mbed_official 245:b4dea936db71 59 static uint32_t can_irq_id = 0;
mbed_official 245:b4dea936db71 60 static can_irq_handler irq_handler;
mbed_official 245:b4dea936db71 61
mbed_official 245:b4dea936db71 62 static inline void can_disable(can_t *obj) {
mbed_official 245:b4dea936db71 63 LPC_C_CAN0->CANCNTL |= 0x1;
mbed_official 245:b4dea936db71 64 }
mbed_official 245:b4dea936db71 65
mbed_official 245:b4dea936db71 66 static inline void can_enable(can_t *obj) {
mbed_official 245:b4dea936db71 67 if (LPC_C_CAN0->CANCNTL & 0x1) {
mbed_official 245:b4dea936db71 68 LPC_C_CAN0->CANCNTL &= ~(0x1);
mbed_official 245:b4dea936db71 69 }
mbed_official 245:b4dea936db71 70 }
mbed_official 245:b4dea936db71 71
mbed_official 245:b4dea936db71 72 int can_mode(can_t *obj, CanMode mode) {
mbed_official 245:b4dea936db71 73 return 0; // not implemented
mbed_official 245:b4dea936db71 74 }
mbed_official 245:b4dea936db71 75
mbed_official 245:b4dea936db71 76 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
mbed_official 245:b4dea936db71 77 uint16_t i;
mbed_official 245:b4dea936db71 78
mbed_official 245:b4dea936db71 79 // Find first free message object
mbed_official 245:b4dea936db71 80 if (handle == 0) {
mbed_official 245:b4dea936db71 81 uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
mbed_official 245:b4dea936db71 82
mbed_official 245:b4dea936db71 83 // Find first free messagebox
mbed_official 245:b4dea936db71 84 for (i = 0; i < 32; i++) {
mbed_official 245:b4dea936db71 85 if ((msgval & (1 << i)) == 0) {
mbed_official 245:b4dea936db71 86 handle = i+1;
mbed_official 245:b4dea936db71 87 break;
mbed_official 245:b4dea936db71 88 }
mbed_official 245:b4dea936db71 89 }
mbed_official 245:b4dea936db71 90 }
mbed_official 245:b4dea936db71 91
mbed_official 245:b4dea936db71 92 if (handle > 0 && handle < 32) {
mbed_official 245:b4dea936db71 93 if (format == CANExtended) {
mbed_official 245:b4dea936db71 94 // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
mbed_official 245:b4dea936db71 95 LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
mbed_official 245:b4dea936db71 96 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
mbed_official 245:b4dea936db71 97 LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
mbed_official 245:b4dea936db71 98 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
mbed_official 245:b4dea936db71 99 } else {
mbed_official 245:b4dea936db71 100 // Mark message valid, Direction = TX, Set Identifier and mask everything
mbed_official 245:b4dea936db71 101 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 102 LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 103 }
mbed_official 245:b4dea936db71 104
mbed_official 245:b4dea936db71 105 // Use mask, single message object and set DLC
mbed_official 245:b4dea936db71 106 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | CANIFn_MCTRL_RXIE | (DLC_MAX & 0xF);
mbed_official 245:b4dea936db71 107
mbed_official 245:b4dea936db71 108 // Transfer all fields to message object
mbed_official 245:b4dea936db71 109 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
mbed_official 245:b4dea936db71 110
mbed_official 245:b4dea936db71 111 // Start Transfer to given message number
mbed_official 245:b4dea936db71 112 LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
mbed_official 245:b4dea936db71 113
mbed_official 245:b4dea936db71 114 // Wait until transfer to message ram complete - TODO: maybe not block??
mbed_official 245:b4dea936db71 115 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 116 }
mbed_official 245:b4dea936db71 117
mbed_official 245:b4dea936db71 118 return handle;
mbed_official 245:b4dea936db71 119 }
mbed_official 245:b4dea936db71 120
mbed_official 245:b4dea936db71 121 static inline void can_irq() {
mbed_official 245:b4dea936db71 122 irq_handler(can_irq_id, IRQ_RX);
mbed_official 245:b4dea936db71 123 }
mbed_official 245:b4dea936db71 124
mbed_official 245:b4dea936db71 125 // Register CAN object's irq handler
mbed_official 245:b4dea936db71 126 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
mbed_official 245:b4dea936db71 127 irq_handler = handler;
mbed_official 245:b4dea936db71 128 can_irq_id = id;
mbed_official 245:b4dea936db71 129 }
mbed_official 245:b4dea936db71 130
mbed_official 245:b4dea936db71 131 // Unregister CAN object's irq handler
mbed_official 245:b4dea936db71 132 void can_irq_free(can_t *obj) {
mbed_official 245:b4dea936db71 133 LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
mbed_official 245:b4dea936db71 134 can_irq_id = 0;
mbed_official 245:b4dea936db71 135 NVIC_DisableIRQ(C_CAN0_IRQn);
mbed_official 245:b4dea936db71 136 }
mbed_official 245:b4dea936db71 137
mbed_official 245:b4dea936db71 138 // Clear or set a irq
mbed_official 245:b4dea936db71 139 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
mbed_official 245:b4dea936db71 140 // Put CAN in Reset Mode and enable interrupt
mbed_official 245:b4dea936db71 141 can_disable(obj);
mbed_official 245:b4dea936db71 142 if (enable == 0) {
mbed_official 245:b4dea936db71 143 LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2);
mbed_official 245:b4dea936db71 144 } else {
mbed_official 245:b4dea936db71 145 LPC_C_CAN0->CANCNTL |= 1UL << 1 | 1UL << 2;
mbed_official 245:b4dea936db71 146 }
mbed_official 245:b4dea936db71 147 // Take it out of reset...
mbed_official 245:b4dea936db71 148 can_enable(obj);
mbed_official 245:b4dea936db71 149
mbed_official 245:b4dea936db71 150 // Enable NVIC if at least 1 interrupt is active
mbed_official 245:b4dea936db71 151 NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
mbed_official 245:b4dea936db71 152 NVIC_EnableIRQ(C_CAN0_IRQn);
mbed_official 245:b4dea936db71 153 }
mbed_official 245:b4dea936db71 154
mbed_official 245:b4dea936db71 155 // This table has the sampling points as close to 75% as possible. The first
mbed_official 245:b4dea936db71 156 // value is TSEG1, the second TSEG2.
mbed_official 245:b4dea936db71 157 static const int timing_pts[23][2] = {
mbed_official 245:b4dea936db71 158 {0x0, 0x0}, // 2, 50%
mbed_official 245:b4dea936db71 159 {0x1, 0x0}, // 3, 67%
mbed_official 245:b4dea936db71 160 {0x2, 0x0}, // 4, 75%
mbed_official 245:b4dea936db71 161 {0x3, 0x0}, // 5, 80%
mbed_official 245:b4dea936db71 162 {0x3, 0x1}, // 6, 67%
mbed_official 245:b4dea936db71 163 {0x4, 0x1}, // 7, 71%
mbed_official 245:b4dea936db71 164 {0x5, 0x1}, // 8, 75%
mbed_official 245:b4dea936db71 165 {0x6, 0x1}, // 9, 78%
mbed_official 245:b4dea936db71 166 {0x6, 0x2}, // 10, 70%
mbed_official 245:b4dea936db71 167 {0x7, 0x2}, // 11, 73%
mbed_official 245:b4dea936db71 168 {0x8, 0x2}, // 12, 75%
mbed_official 245:b4dea936db71 169 {0x9, 0x2}, // 13, 77%
mbed_official 245:b4dea936db71 170 {0x9, 0x3}, // 14, 71%
mbed_official 245:b4dea936db71 171 {0xA, 0x3}, // 15, 73%
mbed_official 245:b4dea936db71 172 {0xB, 0x3}, // 16, 75%
mbed_official 245:b4dea936db71 173 {0xC, 0x3}, // 17, 76%
mbed_official 245:b4dea936db71 174 {0xD, 0x3}, // 18, 78%
mbed_official 245:b4dea936db71 175 {0xD, 0x4}, // 19, 74%
mbed_official 245:b4dea936db71 176 {0xE, 0x4}, // 20, 75%
mbed_official 245:b4dea936db71 177 {0xF, 0x4}, // 21, 76%
mbed_official 245:b4dea936db71 178 {0xF, 0x5}, // 22, 73%
mbed_official 245:b4dea936db71 179 {0xF, 0x6}, // 23, 70%
mbed_official 245:b4dea936db71 180 {0xF, 0x7}, // 24, 67%
mbed_official 245:b4dea936db71 181 };
mbed_official 245:b4dea936db71 182
mbed_official 245:b4dea936db71 183 static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
mbed_official 245:b4dea936db71 184 uint32_t btr;
mbed_official 245:b4dea936db71 185 uint32_t clkdiv = 1;
mbed_official 245:b4dea936db71 186 uint16_t brp = 0;
mbed_official 245:b4dea936db71 187 uint32_t calcbit;
mbed_official 245:b4dea936db71 188 uint32_t bitwidth;
mbed_official 245:b4dea936db71 189 int hit = 0;
mbed_official 245:b4dea936db71 190 int bits = 0;
mbed_official 245:b4dea936db71 191
mbed_official 245:b4dea936db71 192 bitwidth = sclk / cclk;
mbed_official 245:b4dea936db71 193
mbed_official 245:b4dea936db71 194 brp = bitwidth / 0x18;
mbed_official 245:b4dea936db71 195 while ((!hit) && (brp < bitwidth / 4)) {
mbed_official 245:b4dea936db71 196 brp++;
mbed_official 245:b4dea936db71 197 for (bits = 22; bits > 0; bits--) {
mbed_official 245:b4dea936db71 198 calcbit = (bits + 3) * (brp + 1);
mbed_official 245:b4dea936db71 199 if (calcbit == bitwidth) {
mbed_official 245:b4dea936db71 200 hit = 1;
mbed_official 245:b4dea936db71 201 break;
mbed_official 245:b4dea936db71 202 }
mbed_official 245:b4dea936db71 203 }
mbed_official 245:b4dea936db71 204 }
mbed_official 245:b4dea936db71 205
mbed_official 245:b4dea936db71 206 clkdiv = clkdiv - 1;
mbed_official 245:b4dea936db71 207
mbed_official 245:b4dea936db71 208 if (hit) {
mbed_official 245:b4dea936db71 209 btr = (timing_pts[bits][1] & 0x7) << 12
mbed_official 245:b4dea936db71 210 | (timing_pts[bits][0] & 0xf) << 8
mbed_official 245:b4dea936db71 211 | (psjw & 0x3) << 6
mbed_official 245:b4dea936db71 212 | (brp & 0x3F);
mbed_official 245:b4dea936db71 213 btr = btr | (clkdiv << 16);
mbed_official 245:b4dea936db71 214 } else {
mbed_official 245:b4dea936db71 215 btr = 0;
mbed_official 245:b4dea936db71 216 }
mbed_official 245:b4dea936db71 217
mbed_official 245:b4dea936db71 218 return btr;
mbed_official 245:b4dea936db71 219 }
mbed_official 245:b4dea936db71 220
mbed_official 245:b4dea936db71 221
mbed_official 245:b4dea936db71 222 int can_config_rxmsgobj(can_t *obj) {
mbed_official 245:b4dea936db71 223 uint16_t i = 0;
mbed_official 245:b4dea936db71 224
mbed_official 245:b4dea936db71 225 // Make sure the interface is available
mbed_official 245:b4dea936db71 226 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 227
mbed_official 245:b4dea936db71 228 // Mark message valid, Direction = RX, Don't care about anything else
mbed_official 245:b4dea936db71 229 LPC_C_CAN0->CANIF1_ARB1 = 0;
mbed_official 245:b4dea936db71 230 LPC_C_CAN0->CANIF1_ARB2 = 0;
mbed_official 245:b4dea936db71 231 LPC_C_CAN0->CANIF1_MCTRL = 0;
mbed_official 245:b4dea936db71 232
mbed_official 245:b4dea936db71 233 for ( i = 0; i < MSG_OBJ_MAX; i++ ) {
mbed_official 245:b4dea936db71 234 // Transfer arb and control fields to message object
mbed_official 245:b4dea936db71 235 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST;
mbed_official 245:b4dea936db71 236
mbed_official 245:b4dea936db71 237 // Start Transfer to given message number
mbed_official 245:b4dea936db71 238 LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
mbed_official 245:b4dea936db71 239
mbed_official 245:b4dea936db71 240 // Wait until transfer to message ram complete - TODO: maybe not block??
mbed_official 245:b4dea936db71 241 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 242 }
mbed_official 245:b4dea936db71 243
mbed_official 245:b4dea936db71 244 // Accept all messages
mbed_official 245:b4dea936db71 245 can_filter(obj, 0, 0, CANStandard, 1);
mbed_official 245:b4dea936db71 246
mbed_official 245:b4dea936db71 247 return 1;
mbed_official 245:b4dea936db71 248 }
mbed_official 245:b4dea936db71 249
mbed_official 245:b4dea936db71 250
mbed_official 245:b4dea936db71 251 void can_init(can_t *obj, PinName rd, PinName td) {
mbed_official 245:b4dea936db71 252 // Enable power and clock
mbed_official 245:b4dea936db71 253 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
mbed_official 245:b4dea936db71 254 LPC_SYSCON->PRESETCTRL1 |= (1UL << 7);
mbed_official 245:b4dea936db71 255 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 256
mbed_official 245:b4dea936db71 257 // Enable Initialization mode
mbed_official 245:b4dea936db71 258 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
mbed_official 245:b4dea936db71 259 LPC_C_CAN0->CANCNTL |= (1UL << 0);
mbed_official 245:b4dea936db71 260 }
mbed_official 245:b4dea936db71 261
mbed_official 245:b4dea936db71 262 LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
mbed_official 245:b4dea936db71 263 LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
mbed_official 245:b4dea936db71 264
mbed_official 245:b4dea936db71 265 can_frequency(obj, 100000);
mbed_official 245:b4dea936db71 266
mbed_official 245:b4dea936db71 267 // Resume operation
mbed_official 245:b4dea936db71 268 LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
mbed_official 245:b4dea936db71 269 while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
mbed_official 245:b4dea936db71 270
mbed_official 245:b4dea936db71 271 // Initialize RX message object
mbed_official 245:b4dea936db71 272 can_config_rxmsgobj(obj);
mbed_official 245:b4dea936db71 273 }
mbed_official 245:b4dea936db71 274
mbed_official 245:b4dea936db71 275 void can_free(can_t *obj) {
mbed_official 245:b4dea936db71 276 LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 277 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 278 }
mbed_official 245:b4dea936db71 279
mbed_official 245:b4dea936db71 280 int can_frequency(can_t *obj, int f) {
mbed_official 245:b4dea936db71 281 int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
mbed_official 245:b4dea936db71 282 int clkdiv = (btr >> 16) & 0x0F;
mbed_official 245:b4dea936db71 283 btr = btr & 0xFFFF;
mbed_official 245:b4dea936db71 284
mbed_official 245:b4dea936db71 285 if (btr > 0) {
mbed_official 245:b4dea936db71 286 // Set the bit clock
mbed_official 245:b4dea936db71 287 LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
mbed_official 245:b4dea936db71 288 LPC_C_CAN0->CANCLKDIV = clkdiv;
mbed_official 245:b4dea936db71 289 LPC_C_CAN0->CANBT = btr;
mbed_official 245:b4dea936db71 290 LPC_C_CAN0->CANBRPE = 0x0000;
mbed_official 245:b4dea936db71 291 LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
mbed_official 245:b4dea936db71 292 return 1;
mbed_official 245:b4dea936db71 293 }
mbed_official 245:b4dea936db71 294 return 0;
mbed_official 245:b4dea936db71 295 }
mbed_official 245:b4dea936db71 296
mbed_official 245:b4dea936db71 297 int can_write(can_t *obj, CAN_Message msg, int cc) {
mbed_official 245:b4dea936db71 298 uint16_t msgnum = 0;
mbed_official 245:b4dea936db71 299
mbed_official 245:b4dea936db71 300 // Make sure controller is enabled
mbed_official 245:b4dea936db71 301 can_enable(obj);
mbed_official 245:b4dea936db71 302
mbed_official 245:b4dea936db71 303 // Make sure the interface is available
mbed_official 245:b4dea936db71 304 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 305
mbed_official 245:b4dea936db71 306 // Set the direction bit based on the message type
mbed_official 245:b4dea936db71 307 uint32_t direction = 0;
mbed_official 245:b4dea936db71 308 if (msg.type == CANData) {
mbed_official 245:b4dea936db71 309 direction = CANIFn_ARB2_DIR;
mbed_official 245:b4dea936db71 310 }
mbed_official 245:b4dea936db71 311
mbed_official 245:b4dea936db71 312 if (msg.format == CANExtended) {
mbed_official 245:b4dea936db71 313 // Mark message valid, Extended Frame, Set Identifier and mask everything
mbed_official 245:b4dea936db71 314 LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
mbed_official 245:b4dea936db71 315 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
mbed_official 245:b4dea936db71 316 LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
mbed_official 245:b4dea936db71 317 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
mbed_official 245:b4dea936db71 318 } else {
mbed_official 245:b4dea936db71 319 // Mark message valid, Set Identifier and mask everything
mbed_official 245:b4dea936db71 320 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 321 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 322 }
mbed_official 245:b4dea936db71 323
mbed_official 245:b4dea936db71 324 // Use mask, request transmission, single message object and set DLC
mbed_official 245:b4dea936db71 325 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
mbed_official 245:b4dea936db71 326
mbed_official 245:b4dea936db71 327 LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
mbed_official 245:b4dea936db71 328 LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
mbed_official 245:b4dea936db71 329 LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
mbed_official 245:b4dea936db71 330 LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
mbed_official 245:b4dea936db71 331
mbed_official 245:b4dea936db71 332 // Transfer all fields to message object
mbed_official 245:b4dea936db71 333 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
mbed_official 245:b4dea936db71 334
mbed_official 245:b4dea936db71 335 // Start Transfer to given message number
mbed_official 245:b4dea936db71 336 LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
mbed_official 245:b4dea936db71 337
mbed_official 245:b4dea936db71 338 // Wait until transfer to message ram complete - TODO: maybe not block??
mbed_official 245:b4dea936db71 339 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
mbed_official 245:b4dea936db71 340
mbed_official 245:b4dea936db71 341 // Wait until TXOK is set, then clear it - TODO: maybe not block
mbed_official 245:b4dea936db71 342 //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
mbed_official 245:b4dea936db71 343 LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
mbed_official 245:b4dea936db71 344
mbed_official 245:b4dea936db71 345 return 1;
mbed_official 245:b4dea936db71 346 }
mbed_official 245:b4dea936db71 347
mbed_official 245:b4dea936db71 348 int can_read(can_t *obj, CAN_Message *msg, int handle) {
mbed_official 245:b4dea936db71 349 uint16_t i;
mbed_official 245:b4dea936db71 350
mbed_official 245:b4dea936db71 351 // Make sure controller is enabled
mbed_official 245:b4dea936db71 352 can_enable(obj);
mbed_official 245:b4dea936db71 353
mbed_official 245:b4dea936db71 354 // Find first message object with new data
mbed_official 245:b4dea936db71 355 if (handle == 0) {
mbed_official 245:b4dea936db71 356 uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
mbed_official 245:b4dea936db71 357 // Find first free messagebox
mbed_official 245:b4dea936db71 358 for (i = 0; i < 32; i++) {
mbed_official 245:b4dea936db71 359 if (newdata & (1 << i)) {
mbed_official 245:b4dea936db71 360 handle = i+1;
mbed_official 245:b4dea936db71 361 break;
mbed_official 245:b4dea936db71 362 }
mbed_official 245:b4dea936db71 363 }
mbed_official 245:b4dea936db71 364 }
mbed_official 245:b4dea936db71 365
mbed_official 245:b4dea936db71 366 if (handle > 0 && handle < 32) {
mbed_official 245:b4dea936db71 367 // Wait until message interface is free
mbed_official 245:b4dea936db71 368 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 369
mbed_official 245:b4dea936db71 370 // Transfer all fields to message object
mbed_official 245:b4dea936db71 371 LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
mbed_official 245:b4dea936db71 372
mbed_official 245:b4dea936db71 373 // Start Transfer from given message number
mbed_official 245:b4dea936db71 374 LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
mbed_official 245:b4dea936db71 375
mbed_official 245:b4dea936db71 376 // Wait until transfer to message ram complete
mbed_official 245:b4dea936db71 377 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 378
mbed_official 245:b4dea936db71 379 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
mbed_official 245:b4dea936db71 380 msg->format = CANExtended;
mbed_official 245:b4dea936db71 381 msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
mbed_official 245:b4dea936db71 382 msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
mbed_official 245:b4dea936db71 383 } else {
mbed_official 245:b4dea936db71 384 msg->format = CANStandard;
mbed_official 245:b4dea936db71 385 msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
mbed_official 245:b4dea936db71 386 }
mbed_official 245:b4dea936db71 387
mbed_official 245:b4dea936db71 388 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
mbed_official 245:b4dea936db71 389 msg->type = CANRemote;
mbed_official 245:b4dea936db71 390 }
mbed_official 245:b4dea936db71 391 else {
mbed_official 245:b4dea936db71 392 msg->type = CANData;
mbed_official 245:b4dea936db71 393 }
mbed_official 245:b4dea936db71 394
mbed_official 245:b4dea936db71 395 msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
mbed_official 245:b4dea936db71 396 msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 397 msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 398 msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 399 msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 400 msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 401 msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 402 msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 403 msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 404
mbed_official 245:b4dea936db71 405 LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
mbed_official 245:b4dea936db71 406 return 1;
mbed_official 245:b4dea936db71 407 }
mbed_official 245:b4dea936db71 408 return 0;
mbed_official 245:b4dea936db71 409 }
mbed_official 245:b4dea936db71 410
mbed_official 245:b4dea936db71 411 void can_reset(can_t *obj) {
mbed_official 245:b4dea936db71 412 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 413 LPC_C_CAN0->CANSTAT = 0;
mbed_official 245:b4dea936db71 414 can_config_rxmsgobj(obj);
mbed_official 245:b4dea936db71 415 }
mbed_official 245:b4dea936db71 416
mbed_official 245:b4dea936db71 417 unsigned char can_rderror(can_t *obj) {
mbed_official 245:b4dea936db71 418 return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
mbed_official 245:b4dea936db71 419 }
mbed_official 245:b4dea936db71 420
mbed_official 245:b4dea936db71 421 unsigned char can_tderror(can_t *obj) {
mbed_official 245:b4dea936db71 422 return (LPC_C_CAN0->CANEC & 0xFF);
mbed_official 245:b4dea936db71 423 }
mbed_official 245:b4dea936db71 424
mbed_official 245:b4dea936db71 425 void can_monitor(can_t *obj, int silent) {
mbed_official 245:b4dea936db71 426 if (silent) {
mbed_official 245:b4dea936db71 427 LPC_C_CAN0->CANCNTL |= (1UL << 7);
mbed_official 245:b4dea936db71 428 LPC_C_CAN0->CANTEST |= (1UL << 3);
mbed_official 245:b4dea936db71 429 } else {
mbed_official 245:b4dea936db71 430 LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
mbed_official 245:b4dea936db71 431 LPC_C_CAN0->CANTEST &= ~(1UL << 3);
mbed_official 245:b4dea936db71 432 }
mbed_official 245:b4dea936db71 433
mbed_official 245:b4dea936db71 434 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
mbed_official 245:b4dea936db71 435 LPC_C_CAN0->CANCNTL |= (1UL << 0);
mbed_official 245:b4dea936db71 436 }
mbed_official 245:b4dea936db71 437 }