shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_fsmc.c@52:a51c77007319, 2013-12-02 (annotated)

Committer:
mbed_official
Date:
Mon Dec 02 11:30:05 2013 +0000
Revision:
52:a51c77007319
Child:
70:c1fbde68b492
Synchronized with git revision 49df530ae72ce97ccc773d1f2c13b38e868e6abd



Full URL: https://github.com/mbedmicro/mbed/commit/49df530ae72ce97ccc773d1f2c13b38e868e6abd/



Add STMicroelectronics NUCLEO_F103RB target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 52:a51c77007319 1 /**
mbed_official 52:a51c77007319 2 ******************************************************************************
mbed_official 52:a51c77007319 3 * @file stm32f10x_fsmc.c
mbed_official 52:a51c77007319 4 * @author MCD Application Team
mbed_official 52:a51c77007319 5 * @version V3.5.0
mbed_official 52:a51c77007319 6 * @date 11-March-2011
mbed_official 52:a51c77007319 7 * @brief This file provides all the FSMC firmware functions.
mbed_official 52:a51c77007319 8 ******************************************************************************
mbed_official 52:a51c77007319 9 * @attention
mbed_official 52:a51c77007319 10 *
mbed_official 52:a51c77007319 11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
mbed_official 52:a51c77007319 12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
mbed_official 52:a51c77007319 13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
mbed_official 52:a51c77007319 14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
mbed_official 52:a51c77007319 15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
mbed_official 52:a51c77007319 16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
mbed_official 52:a51c77007319 17 *
mbed_official 52:a51c77007319 18 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
mbed_official 52:a51c77007319 19 ******************************************************************************
mbed_official 52:a51c77007319 20 */
mbed_official 52:a51c77007319 21
mbed_official 52:a51c77007319 22 /* Includes ------------------------------------------------------------------*/
mbed_official 52:a51c77007319 23 #include "stm32f10x_fsmc.h"
mbed_official 52:a51c77007319 24 #include "stm32f10x_rcc.h"
mbed_official 52:a51c77007319 25
mbed_official 52:a51c77007319 26 /** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official 52:a51c77007319 27 * @{
mbed_official 52:a51c77007319 28 */
mbed_official 52:a51c77007319 29
mbed_official 52:a51c77007319 30 /** @defgroup FSMC
mbed_official 52:a51c77007319 31 * @brief FSMC driver modules
mbed_official 52:a51c77007319 32 * @{
mbed_official 52:a51c77007319 33 */
mbed_official 52:a51c77007319 34
mbed_official 52:a51c77007319 35 /** @defgroup FSMC_Private_TypesDefinitions
mbed_official 52:a51c77007319 36 * @{
mbed_official 52:a51c77007319 37 */
mbed_official 52:a51c77007319 38 /**
mbed_official 52:a51c77007319 39 * @}
mbed_official 52:a51c77007319 40 */
mbed_official 52:a51c77007319 41
mbed_official 52:a51c77007319 42 /** @defgroup FSMC_Private_Defines
mbed_official 52:a51c77007319 43 * @{
mbed_official 52:a51c77007319 44 */
mbed_official 52:a51c77007319 45
mbed_official 52:a51c77007319 46 /* --------------------- FSMC registers bit mask ---------------------------- */
mbed_official 52:a51c77007319 47
mbed_official 52:a51c77007319 48 /* FSMC BCRx Mask */
mbed_official 52:a51c77007319 49 #define BCR_MBKEN_Set ((uint32_t)0x00000001)
mbed_official 52:a51c77007319 50 #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
mbed_official 52:a51c77007319 51 #define BCR_FACCEN_Set ((uint32_t)0x00000040)
mbed_official 52:a51c77007319 52
mbed_official 52:a51c77007319 53 /* FSMC PCRx Mask */
mbed_official 52:a51c77007319 54 #define PCR_PBKEN_Set ((uint32_t)0x00000004)
mbed_official 52:a51c77007319 55 #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
mbed_official 52:a51c77007319 56 #define PCR_ECCEN_Set ((uint32_t)0x00000040)
mbed_official 52:a51c77007319 57 #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
mbed_official 52:a51c77007319 58 #define PCR_MemoryType_NAND ((uint32_t)0x00000008)
mbed_official 52:a51c77007319 59 /**
mbed_official 52:a51c77007319 60 * @}
mbed_official 52:a51c77007319 61 */
mbed_official 52:a51c77007319 62
mbed_official 52:a51c77007319 63 /** @defgroup FSMC_Private_Macros
mbed_official 52:a51c77007319 64 * @{
mbed_official 52:a51c77007319 65 */
mbed_official 52:a51c77007319 66
mbed_official 52:a51c77007319 67 /**
mbed_official 52:a51c77007319 68 * @}
mbed_official 52:a51c77007319 69 */
mbed_official 52:a51c77007319 70
mbed_official 52:a51c77007319 71 /** @defgroup FSMC_Private_Variables
mbed_official 52:a51c77007319 72 * @{
mbed_official 52:a51c77007319 73 */
mbed_official 52:a51c77007319 74
mbed_official 52:a51c77007319 75 /**
mbed_official 52:a51c77007319 76 * @}
mbed_official 52:a51c77007319 77 */
mbed_official 52:a51c77007319 78
mbed_official 52:a51c77007319 79 /** @defgroup FSMC_Private_FunctionPrototypes
mbed_official 52:a51c77007319 80 * @{
mbed_official 52:a51c77007319 81 */
mbed_official 52:a51c77007319 82
mbed_official 52:a51c77007319 83 /**
mbed_official 52:a51c77007319 84 * @}
mbed_official 52:a51c77007319 85 */
mbed_official 52:a51c77007319 86
mbed_official 52:a51c77007319 87 /** @defgroup FSMC_Private_Functions
mbed_official 52:a51c77007319 88 * @{
mbed_official 52:a51c77007319 89 */
mbed_official 52:a51c77007319 90
mbed_official 52:a51c77007319 91 /**
mbed_official 52:a51c77007319 92 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
mbed_official 52:a51c77007319 93 * reset values.
mbed_official 52:a51c77007319 94 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 95 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 96 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 52:a51c77007319 97 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 52:a51c77007319 98 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 52:a51c77007319 99 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 52:a51c77007319 100 * @retval None
mbed_official 52:a51c77007319 101 */
mbed_official 52:a51c77007319 102 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
mbed_official 52:a51c77007319 103 {
mbed_official 52:a51c77007319 104 /* Check the parameter */
mbed_official 52:a51c77007319 105 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 106
mbed_official 52:a51c77007319 107 /* FSMC_Bank1_NORSRAM1 */
mbed_official 52:a51c77007319 108 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
mbed_official 52:a51c77007319 109 {
mbed_official 52:a51c77007319 110 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
mbed_official 52:a51c77007319 111 }
mbed_official 52:a51c77007319 112 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
mbed_official 52:a51c77007319 113 else
mbed_official 52:a51c77007319 114 {
mbed_official 52:a51c77007319 115 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
mbed_official 52:a51c77007319 116 }
mbed_official 52:a51c77007319 117 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
mbed_official 52:a51c77007319 118 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
mbed_official 52:a51c77007319 119 }
mbed_official 52:a51c77007319 120
mbed_official 52:a51c77007319 121 /**
mbed_official 52:a51c77007319 122 * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
mbed_official 52:a51c77007319 123 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 124 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 125 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 126 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 127 * @retval None
mbed_official 52:a51c77007319 128 */
mbed_official 52:a51c77007319 129 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
mbed_official 52:a51c77007319 130 {
mbed_official 52:a51c77007319 131 /* Check the parameter */
mbed_official 52:a51c77007319 132 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 133
mbed_official 52:a51c77007319 134 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 135 {
mbed_official 52:a51c77007319 136 /* Set the FSMC_Bank2 registers to their reset values */
mbed_official 52:a51c77007319 137 FSMC_Bank2->PCR2 = 0x00000018;
mbed_official 52:a51c77007319 138 FSMC_Bank2->SR2 = 0x00000040;
mbed_official 52:a51c77007319 139 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 140 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 141 }
mbed_official 52:a51c77007319 142 /* FSMC_Bank3_NAND */
mbed_official 52:a51c77007319 143 else
mbed_official 52:a51c77007319 144 {
mbed_official 52:a51c77007319 145 /* Set the FSMC_Bank3 registers to their reset values */
mbed_official 52:a51c77007319 146 FSMC_Bank3->PCR3 = 0x00000018;
mbed_official 52:a51c77007319 147 FSMC_Bank3->SR3 = 0x00000040;
mbed_official 52:a51c77007319 148 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 149 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 150 }
mbed_official 52:a51c77007319 151 }
mbed_official 52:a51c77007319 152
mbed_official 52:a51c77007319 153 /**
mbed_official 52:a51c77007319 154 * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
mbed_official 52:a51c77007319 155 * @param None
mbed_official 52:a51c77007319 156 * @retval None
mbed_official 52:a51c77007319 157 */
mbed_official 52:a51c77007319 158 void FSMC_PCCARDDeInit(void)
mbed_official 52:a51c77007319 159 {
mbed_official 52:a51c77007319 160 /* Set the FSMC_Bank4 registers to their reset values */
mbed_official 52:a51c77007319 161 FSMC_Bank4->PCR4 = 0x00000018;
mbed_official 52:a51c77007319 162 FSMC_Bank4->SR4 = 0x00000000;
mbed_official 52:a51c77007319 163 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 164 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 165 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 166 }
mbed_official 52:a51c77007319 167
mbed_official 52:a51c77007319 168 /**
mbed_official 52:a51c77007319 169 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
mbed_official 52:a51c77007319 170 * parameters in the FSMC_NORSRAMInitStruct.
mbed_official 52:a51c77007319 171 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 52:a51c77007319 172 * structure that contains the configuration information for
mbed_official 52:a51c77007319 173 * the FSMC NOR/SRAM specified Banks.
mbed_official 52:a51c77007319 174 * @retval None
mbed_official 52:a51c77007319 175 */
mbed_official 52:a51c77007319 176 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 52:a51c77007319 177 {
mbed_official 52:a51c77007319 178 /* Check the parameters */
mbed_official 52:a51c77007319 179 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
mbed_official 52:a51c77007319 180 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
mbed_official 52:a51c77007319 181 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
mbed_official 52:a51c77007319 182 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
mbed_official 52:a51c77007319 183 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
mbed_official 52:a51c77007319 184 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
mbed_official 52:a51c77007319 185 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
mbed_official 52:a51c77007319 186 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
mbed_official 52:a51c77007319 187 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
mbed_official 52:a51c77007319 188 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
mbed_official 52:a51c77007319 189 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
mbed_official 52:a51c77007319 190 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
mbed_official 52:a51c77007319 191 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
mbed_official 52:a51c77007319 192 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 52:a51c77007319 193 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 52:a51c77007319 194 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
mbed_official 52:a51c77007319 195 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
mbed_official 52:a51c77007319 196 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
mbed_official 52:a51c77007319 197 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
mbed_official 52:a51c77007319 198 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
mbed_official 52:a51c77007319 199
mbed_official 52:a51c77007319 200 /* Bank1 NOR/SRAM control register configuration */
mbed_official 52:a51c77007319 201 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 52:a51c77007319 202 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
mbed_official 52:a51c77007319 203 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
mbed_official 52:a51c77007319 204 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
mbed_official 52:a51c77007319 205 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
mbed_official 52:a51c77007319 206 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
mbed_official 52:a51c77007319 207 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
mbed_official 52:a51c77007319 208 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
mbed_official 52:a51c77007319 209 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
mbed_official 52:a51c77007319 210 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
mbed_official 52:a51c77007319 211 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
mbed_official 52:a51c77007319 212 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
mbed_official 52:a51c77007319 213 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
mbed_official 52:a51c77007319 214
mbed_official 52:a51c77007319 215 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
mbed_official 52:a51c77007319 216 {
mbed_official 52:a51c77007319 217 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
mbed_official 52:a51c77007319 218 }
mbed_official 52:a51c77007319 219
mbed_official 52:a51c77007319 220 /* Bank1 NOR/SRAM timing register configuration */
mbed_official 52:a51c77007319 221 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
mbed_official 52:a51c77007319 222 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 52:a51c77007319 223 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
mbed_official 52:a51c77007319 224 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 52:a51c77007319 225 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
mbed_official 52:a51c77007319 226 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 52:a51c77007319 227 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 52:a51c77007319 228 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
mbed_official 52:a51c77007319 229
mbed_official 52:a51c77007319 230
mbed_official 52:a51c77007319 231 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
mbed_official 52:a51c77007319 232 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
mbed_official 52:a51c77007319 233 {
mbed_official 52:a51c77007319 234 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 52:a51c77007319 235 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 52:a51c77007319 236 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
mbed_official 52:a51c77007319 237 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
mbed_official 52:a51c77007319 238 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
mbed_official 52:a51c77007319 239 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
mbed_official 52:a51c77007319 240 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 52:a51c77007319 241 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 52:a51c77007319 242 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
mbed_official 52:a51c77007319 243 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 52:a51c77007319 244 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 52:a51c77007319 245 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 52:a51c77007319 246 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
mbed_official 52:a51c77007319 247 }
mbed_official 52:a51c77007319 248 else
mbed_official 52:a51c77007319 249 {
mbed_official 52:a51c77007319 250 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
mbed_official 52:a51c77007319 251 }
mbed_official 52:a51c77007319 252 }
mbed_official 52:a51c77007319 253
mbed_official 52:a51c77007319 254 /**
mbed_official 52:a51c77007319 255 * @brief Initializes the FSMC NAND Banks according to the specified
mbed_official 52:a51c77007319 256 * parameters in the FSMC_NANDInitStruct.
mbed_official 52:a51c77007319 257 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
mbed_official 52:a51c77007319 258 * structure that contains the configuration information for the FSMC
mbed_official 52:a51c77007319 259 * NAND specified Banks.
mbed_official 52:a51c77007319 260 * @retval None
mbed_official 52:a51c77007319 261 */
mbed_official 52:a51c77007319 262 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
mbed_official 52:a51c77007319 263 {
mbed_official 52:a51c77007319 264 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
mbed_official 52:a51c77007319 265
mbed_official 52:a51c77007319 266 /* Check the parameters */
mbed_official 52:a51c77007319 267 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
mbed_official 52:a51c77007319 268 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
mbed_official 52:a51c77007319 269 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
mbed_official 52:a51c77007319 270 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
mbed_official 52:a51c77007319 271 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
mbed_official 52:a51c77007319 272 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
mbed_official 52:a51c77007319 273 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
mbed_official 52:a51c77007319 274 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 275 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 276 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 277 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 278 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 279 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 280 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 281 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 282
mbed_official 52:a51c77007319 283 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
mbed_official 52:a51c77007319 284 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
mbed_official 52:a51c77007319 285 PCR_MemoryType_NAND |
mbed_official 52:a51c77007319 286 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
mbed_official 52:a51c77007319 287 FSMC_NANDInitStruct->FSMC_ECC |
mbed_official 52:a51c77007319 288 FSMC_NANDInitStruct->FSMC_ECCPageSize |
mbed_official 52:a51c77007319 289 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
mbed_official 52:a51c77007319 290 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
mbed_official 52:a51c77007319 291
mbed_official 52:a51c77007319 292 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 293 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 294 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 295 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 296 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 297
mbed_official 52:a51c77007319 298 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 299 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 300 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 301 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 302 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 303
mbed_official 52:a51c77007319 304 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 305 {
mbed_official 52:a51c77007319 306 /* FSMC_Bank2_NAND registers configuration */
mbed_official 52:a51c77007319 307 FSMC_Bank2->PCR2 = tmppcr;
mbed_official 52:a51c77007319 308 FSMC_Bank2->PMEM2 = tmppmem;
mbed_official 52:a51c77007319 309 FSMC_Bank2->PATT2 = tmppatt;
mbed_official 52:a51c77007319 310 }
mbed_official 52:a51c77007319 311 else
mbed_official 52:a51c77007319 312 {
mbed_official 52:a51c77007319 313 /* FSMC_Bank3_NAND registers configuration */
mbed_official 52:a51c77007319 314 FSMC_Bank3->PCR3 = tmppcr;
mbed_official 52:a51c77007319 315 FSMC_Bank3->PMEM3 = tmppmem;
mbed_official 52:a51c77007319 316 FSMC_Bank3->PATT3 = tmppatt;
mbed_official 52:a51c77007319 317 }
mbed_official 52:a51c77007319 318 }
mbed_official 52:a51c77007319 319
mbed_official 52:a51c77007319 320 /**
mbed_official 52:a51c77007319 321 * @brief Initializes the FSMC PCCARD Bank according to the specified
mbed_official 52:a51c77007319 322 * parameters in the FSMC_PCCARDInitStruct.
mbed_official 52:a51c77007319 323 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
mbed_official 52:a51c77007319 324 * structure that contains the configuration information for the FSMC
mbed_official 52:a51c77007319 325 * PCCARD Bank.
mbed_official 52:a51c77007319 326 * @retval None
mbed_official 52:a51c77007319 327 */
mbed_official 52:a51c77007319 328 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
mbed_official 52:a51c77007319 329 {
mbed_official 52:a51c77007319 330 /* Check the parameters */
mbed_official 52:a51c77007319 331 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
mbed_official 52:a51c77007319 332 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
mbed_official 52:a51c77007319 333 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
mbed_official 52:a51c77007319 334
mbed_official 52:a51c77007319 335 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 336 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 337 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 338 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 339
mbed_official 52:a51c77007319 340 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 341 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 342 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 343 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 344 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 345 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 346 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 347 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 348
mbed_official 52:a51c77007319 349 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
mbed_official 52:a51c77007319 350 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
mbed_official 52:a51c77007319 351 FSMC_MemoryDataWidth_16b |
mbed_official 52:a51c77007319 352 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
mbed_official 52:a51c77007319 353 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
mbed_official 52:a51c77007319 354
mbed_official 52:a51c77007319 355 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 356 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 357 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 358 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 359 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 360
mbed_official 52:a51c77007319 361 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 362 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 363 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 364 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 365 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 366
mbed_official 52:a51c77007319 367 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 368 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 369 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 370 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 371 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 372 }
mbed_official 52:a51c77007319 373
mbed_official 52:a51c77007319 374 /**
mbed_official 52:a51c77007319 375 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
mbed_official 52:a51c77007319 376 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 52:a51c77007319 377 * structure which will be initialized.
mbed_official 52:a51c77007319 378 * @retval None
mbed_official 52:a51c77007319 379 */
mbed_official 52:a51c77007319 380 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 52:a51c77007319 381 {
mbed_official 52:a51c77007319 382 /* Reset NOR/SRAM Init structure parameters values */
mbed_official 52:a51c77007319 383 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
mbed_official 52:a51c77007319 384 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
mbed_official 52:a51c77007319 385 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official 52:a51c77007319 386 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
mbed_official 52:a51c77007319 387 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official 52:a51c77007319 388 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official 52:a51c77007319 389 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official 52:a51c77007319 390 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official 52:a51c77007319 391 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official 52:a51c77007319 392 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official 52:a51c77007319 393 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
mbed_official 52:a51c77007319 394 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official 52:a51c77007319 395 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official 52:a51c77007319 396 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 52:a51c77007319 397 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 52:a51c77007319 398 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 52:a51c77007319 399 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 52:a51c77007319 400 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 52:a51c77007319 401 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 52:a51c77007319 402 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 52:a51c77007319 403 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 52:a51c77007319 404 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 52:a51c77007319 405 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 52:a51c77007319 406 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 52:a51c77007319 407 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 52:a51c77007319 408 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 52:a51c77007319 409 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 52:a51c77007319 410 }
mbed_official 52:a51c77007319 411
mbed_official 52:a51c77007319 412 /**
mbed_official 52:a51c77007319 413 * @brief Fills each FSMC_NANDInitStruct member with its default value.
mbed_official 52:a51c77007319 414 * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
mbed_official 52:a51c77007319 415 * structure which will be initialized.
mbed_official 52:a51c77007319 416 * @retval None
mbed_official 52:a51c77007319 417 */
mbed_official 52:a51c77007319 418 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
mbed_official 52:a51c77007319 419 {
mbed_official 52:a51c77007319 420 /* Reset NAND Init structure parameters values */
mbed_official 52:a51c77007319 421 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
mbed_official 52:a51c77007319 422 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
mbed_official 52:a51c77007319 423 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
mbed_official 52:a51c77007319 424 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
mbed_official 52:a51c77007319 425 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
mbed_official 52:a51c77007319 426 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
mbed_official 52:a51c77007319 427 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
mbed_official 52:a51c77007319 428 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 429 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 430 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 431 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 432 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 433 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 434 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 435 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 436 }
mbed_official 52:a51c77007319 437
mbed_official 52:a51c77007319 438 /**
mbed_official 52:a51c77007319 439 * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
mbed_official 52:a51c77007319 440 * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
mbed_official 52:a51c77007319 441 * structure which will be initialized.
mbed_official 52:a51c77007319 442 * @retval None
mbed_official 52:a51c77007319 443 */
mbed_official 52:a51c77007319 444 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
mbed_official 52:a51c77007319 445 {
mbed_official 52:a51c77007319 446 /* Reset PCCARD Init structure parameters values */
mbed_official 52:a51c77007319 447 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
mbed_official 52:a51c77007319 448 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
mbed_official 52:a51c77007319 449 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
mbed_official 52:a51c77007319 450 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 451 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 452 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 453 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 454 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 455 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 456 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 457 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 458 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 459 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 460 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 461 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 462 }
mbed_official 52:a51c77007319 463
mbed_official 52:a51c77007319 464 /**
mbed_official 52:a51c77007319 465 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
mbed_official 52:a51c77007319 466 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 467 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 468 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 52:a51c77007319 469 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 52:a51c77007319 470 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 52:a51c77007319 471 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 52:a51c77007319 472 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 473 * @retval None
mbed_official 52:a51c77007319 474 */
mbed_official 52:a51c77007319 475 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 52:a51c77007319 476 {
mbed_official 52:a51c77007319 477 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 478 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 479
mbed_official 52:a51c77007319 480 if (NewState != DISABLE)
mbed_official 52:a51c77007319 481 {
mbed_official 52:a51c77007319 482 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
mbed_official 52:a51c77007319 483 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
mbed_official 52:a51c77007319 484 }
mbed_official 52:a51c77007319 485 else
mbed_official 52:a51c77007319 486 {
mbed_official 52:a51c77007319 487 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
mbed_official 52:a51c77007319 488 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
mbed_official 52:a51c77007319 489 }
mbed_official 52:a51c77007319 490 }
mbed_official 52:a51c77007319 491
mbed_official 52:a51c77007319 492 /**
mbed_official 52:a51c77007319 493 * @brief Enables or disables the specified NAND Memory Bank.
mbed_official 52:a51c77007319 494 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 495 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 496 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 497 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 498 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 499 * @retval None
mbed_official 52:a51c77007319 500 */
mbed_official 52:a51c77007319 501 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 52:a51c77007319 502 {
mbed_official 52:a51c77007319 503 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 504 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 505
mbed_official 52:a51c77007319 506 if (NewState != DISABLE)
mbed_official 52:a51c77007319 507 {
mbed_official 52:a51c77007319 508 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
mbed_official 52:a51c77007319 509 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 510 {
mbed_official 52:a51c77007319 511 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
mbed_official 52:a51c77007319 512 }
mbed_official 52:a51c77007319 513 else
mbed_official 52:a51c77007319 514 {
mbed_official 52:a51c77007319 515 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
mbed_official 52:a51c77007319 516 }
mbed_official 52:a51c77007319 517 }
mbed_official 52:a51c77007319 518 else
mbed_official 52:a51c77007319 519 {
mbed_official 52:a51c77007319 520 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
mbed_official 52:a51c77007319 521 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 522 {
mbed_official 52:a51c77007319 523 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
mbed_official 52:a51c77007319 524 }
mbed_official 52:a51c77007319 525 else
mbed_official 52:a51c77007319 526 {
mbed_official 52:a51c77007319 527 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
mbed_official 52:a51c77007319 528 }
mbed_official 52:a51c77007319 529 }
mbed_official 52:a51c77007319 530 }
mbed_official 52:a51c77007319 531
mbed_official 52:a51c77007319 532 /**
mbed_official 52:a51c77007319 533 * @brief Enables or disables the PCCARD Memory Bank.
mbed_official 52:a51c77007319 534 * @param NewState: new state of the PCCARD Memory Bank.
mbed_official 52:a51c77007319 535 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 536 * @retval None
mbed_official 52:a51c77007319 537 */
mbed_official 52:a51c77007319 538 void FSMC_PCCARDCmd(FunctionalState NewState)
mbed_official 52:a51c77007319 539 {
mbed_official 52:a51c77007319 540 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 541
mbed_official 52:a51c77007319 542 if (NewState != DISABLE)
mbed_official 52:a51c77007319 543 {
mbed_official 52:a51c77007319 544 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
mbed_official 52:a51c77007319 545 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
mbed_official 52:a51c77007319 546 }
mbed_official 52:a51c77007319 547 else
mbed_official 52:a51c77007319 548 {
mbed_official 52:a51c77007319 549 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
mbed_official 52:a51c77007319 550 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
mbed_official 52:a51c77007319 551 }
mbed_official 52:a51c77007319 552 }
mbed_official 52:a51c77007319 553
mbed_official 52:a51c77007319 554 /**
mbed_official 52:a51c77007319 555 * @brief Enables or disables the FSMC NAND ECC feature.
mbed_official 52:a51c77007319 556 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 557 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 558 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 559 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 560 * @param NewState: new state of the FSMC NAND ECC feature.
mbed_official 52:a51c77007319 561 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 562 * @retval None
mbed_official 52:a51c77007319 563 */
mbed_official 52:a51c77007319 564 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 52:a51c77007319 565 {
mbed_official 52:a51c77007319 566 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 567 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 568
mbed_official 52:a51c77007319 569 if (NewState != DISABLE)
mbed_official 52:a51c77007319 570 {
mbed_official 52:a51c77007319 571 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
mbed_official 52:a51c77007319 572 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 573 {
mbed_official 52:a51c77007319 574 FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
mbed_official 52:a51c77007319 575 }
mbed_official 52:a51c77007319 576 else
mbed_official 52:a51c77007319 577 {
mbed_official 52:a51c77007319 578 FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
mbed_official 52:a51c77007319 579 }
mbed_official 52:a51c77007319 580 }
mbed_official 52:a51c77007319 581 else
mbed_official 52:a51c77007319 582 {
mbed_official 52:a51c77007319 583 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
mbed_official 52:a51c77007319 584 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 585 {
mbed_official 52:a51c77007319 586 FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
mbed_official 52:a51c77007319 587 }
mbed_official 52:a51c77007319 588 else
mbed_official 52:a51c77007319 589 {
mbed_official 52:a51c77007319 590 FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
mbed_official 52:a51c77007319 591 }
mbed_official 52:a51c77007319 592 }
mbed_official 52:a51c77007319 593 }
mbed_official 52:a51c77007319 594
mbed_official 52:a51c77007319 595 /**
mbed_official 52:a51c77007319 596 * @brief Returns the error correction code register value.
mbed_official 52:a51c77007319 597 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 598 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 599 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 600 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 601 * @retval The Error Correction Code (ECC) value.
mbed_official 52:a51c77007319 602 */
mbed_official 52:a51c77007319 603 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
mbed_official 52:a51c77007319 604 {
mbed_official 52:a51c77007319 605 uint32_t eccval = 0x00000000;
mbed_official 52:a51c77007319 606
mbed_official 52:a51c77007319 607 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 608 {
mbed_official 52:a51c77007319 609 /* Get the ECCR2 register value */
mbed_official 52:a51c77007319 610 eccval = FSMC_Bank2->ECCR2;
mbed_official 52:a51c77007319 611 }
mbed_official 52:a51c77007319 612 else
mbed_official 52:a51c77007319 613 {
mbed_official 52:a51c77007319 614 /* Get the ECCR3 register value */
mbed_official 52:a51c77007319 615 eccval = FSMC_Bank3->ECCR3;
mbed_official 52:a51c77007319 616 }
mbed_official 52:a51c77007319 617 /* Return the error correction code value */
mbed_official 52:a51c77007319 618 return(eccval);
mbed_official 52:a51c77007319 619 }
mbed_official 52:a51c77007319 620
mbed_official 52:a51c77007319 621 /**
mbed_official 52:a51c77007319 622 * @brief Enables or disables the specified FSMC interrupts.
mbed_official 52:a51c77007319 623 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 624 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 625 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 626 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 627 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 628 * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
mbed_official 52:a51c77007319 629 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 630 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
mbed_official 52:a51c77007319 631 * @arg FSMC_IT_Level: Level edge detection interrupt.
mbed_official 52:a51c77007319 632 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
mbed_official 52:a51c77007319 633 * @param NewState: new state of the specified FSMC interrupts.
mbed_official 52:a51c77007319 634 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 635 * @retval None
mbed_official 52:a51c77007319 636 */
mbed_official 52:a51c77007319 637 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
mbed_official 52:a51c77007319 638 {
mbed_official 52:a51c77007319 639 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 640 assert_param(IS_FSMC_IT(FSMC_IT));
mbed_official 52:a51c77007319 641 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 642
mbed_official 52:a51c77007319 643 if (NewState != DISABLE)
mbed_official 52:a51c77007319 644 {
mbed_official 52:a51c77007319 645 /* Enable the selected FSMC_Bank2 interrupts */
mbed_official 52:a51c77007319 646 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 647 {
mbed_official 52:a51c77007319 648 FSMC_Bank2->SR2 |= FSMC_IT;
mbed_official 52:a51c77007319 649 }
mbed_official 52:a51c77007319 650 /* Enable the selected FSMC_Bank3 interrupts */
mbed_official 52:a51c77007319 651 else if (FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 652 {
mbed_official 52:a51c77007319 653 FSMC_Bank3->SR3 |= FSMC_IT;
mbed_official 52:a51c77007319 654 }
mbed_official 52:a51c77007319 655 /* Enable the selected FSMC_Bank4 interrupts */
mbed_official 52:a51c77007319 656 else
mbed_official 52:a51c77007319 657 {
mbed_official 52:a51c77007319 658 FSMC_Bank4->SR4 |= FSMC_IT;
mbed_official 52:a51c77007319 659 }
mbed_official 52:a51c77007319 660 }
mbed_official 52:a51c77007319 661 else
mbed_official 52:a51c77007319 662 {
mbed_official 52:a51c77007319 663 /* Disable the selected FSMC_Bank2 interrupts */
mbed_official 52:a51c77007319 664 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 665 {
mbed_official 52:a51c77007319 666
mbed_official 52:a51c77007319 667 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
mbed_official 52:a51c77007319 668 }
mbed_official 52:a51c77007319 669 /* Disable the selected FSMC_Bank3 interrupts */
mbed_official 52:a51c77007319 670 else if (FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 671 {
mbed_official 52:a51c77007319 672 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
mbed_official 52:a51c77007319 673 }
mbed_official 52:a51c77007319 674 /* Disable the selected FSMC_Bank4 interrupts */
mbed_official 52:a51c77007319 675 else
mbed_official 52:a51c77007319 676 {
mbed_official 52:a51c77007319 677 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
mbed_official 52:a51c77007319 678 }
mbed_official 52:a51c77007319 679 }
mbed_official 52:a51c77007319 680 }
mbed_official 52:a51c77007319 681
mbed_official 52:a51c77007319 682 /**
mbed_official 52:a51c77007319 683 * @brief Checks whether the specified FSMC flag is set or not.
mbed_official 52:a51c77007319 684 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 685 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 686 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 687 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 688 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 689 * @param FSMC_FLAG: specifies the flag to check.
mbed_official 52:a51c77007319 690 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 691 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
mbed_official 52:a51c77007319 692 * @arg FSMC_FLAG_Level: Level detection Flag.
mbed_official 52:a51c77007319 693 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
mbed_official 52:a51c77007319 694 * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
mbed_official 52:a51c77007319 695 * @retval The new state of FSMC_FLAG (SET or RESET).
mbed_official 52:a51c77007319 696 */
mbed_official 52:a51c77007319 697 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
mbed_official 52:a51c77007319 698 {
mbed_official 52:a51c77007319 699 FlagStatus bitstatus = RESET;
mbed_official 52:a51c77007319 700 uint32_t tmpsr = 0x00000000;
mbed_official 52:a51c77007319 701
mbed_official 52:a51c77007319 702 /* Check the parameters */
mbed_official 52:a51c77007319 703 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 704 assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
mbed_official 52:a51c77007319 705
mbed_official 52:a51c77007319 706 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 707 {
mbed_official 52:a51c77007319 708 tmpsr = FSMC_Bank2->SR2;
mbed_official 52:a51c77007319 709 }
mbed_official 52:a51c77007319 710 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 711 {
mbed_official 52:a51c77007319 712 tmpsr = FSMC_Bank3->SR3;
mbed_official 52:a51c77007319 713 }
mbed_official 52:a51c77007319 714 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 715 else
mbed_official 52:a51c77007319 716 {
mbed_official 52:a51c77007319 717 tmpsr = FSMC_Bank4->SR4;
mbed_official 52:a51c77007319 718 }
mbed_official 52:a51c77007319 719
mbed_official 52:a51c77007319 720 /* Get the flag status */
mbed_official 52:a51c77007319 721 if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
mbed_official 52:a51c77007319 722 {
mbed_official 52:a51c77007319 723 bitstatus = SET;
mbed_official 52:a51c77007319 724 }
mbed_official 52:a51c77007319 725 else
mbed_official 52:a51c77007319 726 {
mbed_official 52:a51c77007319 727 bitstatus = RESET;
mbed_official 52:a51c77007319 728 }
mbed_official 52:a51c77007319 729 /* Return the flag status */
mbed_official 52:a51c77007319 730 return bitstatus;
mbed_official 52:a51c77007319 731 }
mbed_official 52:a51c77007319 732
mbed_official 52:a51c77007319 733 /**
mbed_official 52:a51c77007319 734 * @brief Clears the FSMC's pending flags.
mbed_official 52:a51c77007319 735 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 736 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 737 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 738 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 739 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 740 * @param FSMC_FLAG: specifies the flag to clear.
mbed_official 52:a51c77007319 741 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 742 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
mbed_official 52:a51c77007319 743 * @arg FSMC_FLAG_Level: Level detection Flag.
mbed_official 52:a51c77007319 744 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
mbed_official 52:a51c77007319 745 * @retval None
mbed_official 52:a51c77007319 746 */
mbed_official 52:a51c77007319 747 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
mbed_official 52:a51c77007319 748 {
mbed_official 52:a51c77007319 749 /* Check the parameters */
mbed_official 52:a51c77007319 750 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 751 assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
mbed_official 52:a51c77007319 752
mbed_official 52:a51c77007319 753 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 754 {
mbed_official 52:a51c77007319 755 FSMC_Bank2->SR2 &= ~FSMC_FLAG;
mbed_official 52:a51c77007319 756 }
mbed_official 52:a51c77007319 757 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 758 {
mbed_official 52:a51c77007319 759 FSMC_Bank3->SR3 &= ~FSMC_FLAG;
mbed_official 52:a51c77007319 760 }
mbed_official 52:a51c77007319 761 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 762 else
mbed_official 52:a51c77007319 763 {
mbed_official 52:a51c77007319 764 FSMC_Bank4->SR4 &= ~FSMC_FLAG;
mbed_official 52:a51c77007319 765 }
mbed_official 52:a51c77007319 766 }
mbed_official 52:a51c77007319 767
mbed_official 52:a51c77007319 768 /**
mbed_official 52:a51c77007319 769 * @brief Checks whether the specified FSMC interrupt has occurred or not.
mbed_official 52:a51c77007319 770 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 771 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 772 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 773 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 774 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 775 * @param FSMC_IT: specifies the FSMC interrupt source to check.
mbed_official 52:a51c77007319 776 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 777 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
mbed_official 52:a51c77007319 778 * @arg FSMC_IT_Level: Level edge detection interrupt.
mbed_official 52:a51c77007319 779 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
mbed_official 52:a51c77007319 780 * @retval The new state of FSMC_IT (SET or RESET).
mbed_official 52:a51c77007319 781 */
mbed_official 52:a51c77007319 782 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
mbed_official 52:a51c77007319 783 {
mbed_official 52:a51c77007319 784 ITStatus bitstatus = RESET;
mbed_official 52:a51c77007319 785 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
mbed_official 52:a51c77007319 786
mbed_official 52:a51c77007319 787 /* Check the parameters */
mbed_official 52:a51c77007319 788 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 789 assert_param(IS_FSMC_GET_IT(FSMC_IT));
mbed_official 52:a51c77007319 790
mbed_official 52:a51c77007319 791 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 792 {
mbed_official 52:a51c77007319 793 tmpsr = FSMC_Bank2->SR2;
mbed_official 52:a51c77007319 794 }
mbed_official 52:a51c77007319 795 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 796 {
mbed_official 52:a51c77007319 797 tmpsr = FSMC_Bank3->SR3;
mbed_official 52:a51c77007319 798 }
mbed_official 52:a51c77007319 799 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 800 else
mbed_official 52:a51c77007319 801 {
mbed_official 52:a51c77007319 802 tmpsr = FSMC_Bank4->SR4;
mbed_official 52:a51c77007319 803 }
mbed_official 52:a51c77007319 804
mbed_official 52:a51c77007319 805 itstatus = tmpsr & FSMC_IT;
mbed_official 52:a51c77007319 806
mbed_official 52:a51c77007319 807 itenable = tmpsr & (FSMC_IT >> 3);
mbed_official 52:a51c77007319 808 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
mbed_official 52:a51c77007319 809 {
mbed_official 52:a51c77007319 810 bitstatus = SET;
mbed_official 52:a51c77007319 811 }
mbed_official 52:a51c77007319 812 else
mbed_official 52:a51c77007319 813 {
mbed_official 52:a51c77007319 814 bitstatus = RESET;
mbed_official 52:a51c77007319 815 }
mbed_official 52:a51c77007319 816 return bitstatus;
mbed_official 52:a51c77007319 817 }
mbed_official 52:a51c77007319 818
mbed_official 52:a51c77007319 819 /**
mbed_official 52:a51c77007319 820 * @brief Clears the FSMC's interrupt pending bits.
mbed_official 52:a51c77007319 821 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 822 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 823 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 824 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 825 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 826 * @param FSMC_IT: specifies the interrupt pending bit to clear.
mbed_official 52:a51c77007319 827 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 828 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
mbed_official 52:a51c77007319 829 * @arg FSMC_IT_Level: Level edge detection interrupt.
mbed_official 52:a51c77007319 830 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
mbed_official 52:a51c77007319 831 * @retval None
mbed_official 52:a51c77007319 832 */
mbed_official 52:a51c77007319 833 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
mbed_official 52:a51c77007319 834 {
mbed_official 52:a51c77007319 835 /* Check the parameters */
mbed_official 52:a51c77007319 836 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 837 assert_param(IS_FSMC_IT(FSMC_IT));
mbed_official 52:a51c77007319 838
mbed_official 52:a51c77007319 839 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 840 {
mbed_official 52:a51c77007319 841 FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
mbed_official 52:a51c77007319 842 }
mbed_official 52:a51c77007319 843 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 844 {
mbed_official 52:a51c77007319 845 FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
mbed_official 52:a51c77007319 846 }
mbed_official 52:a51c77007319 847 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 848 else
mbed_official 52:a51c77007319 849 {
mbed_official 52:a51c77007319 850 FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
mbed_official 52:a51c77007319 851 }
mbed_official 52:a51c77007319 852 }
mbed_official 52:a51c77007319 853
mbed_official 52:a51c77007319 854 /**
mbed_official 52:a51c77007319 855 * @}
mbed_official 52:a51c77007319 856 */
mbed_official 52:a51c77007319 857
mbed_official 52:a51c77007319 858 /**
mbed_official 52:a51c77007319 859 * @}
mbed_official 52:a51c77007319 860 */
mbed_official 52:a51c77007319 861
mbed_official 52:a51c77007319 862 /**
mbed_official 52:a51c77007319 863 * @}
mbed_official 52:a51c77007319 864 */
mbed_official 52:a51c77007319 865
mbed_official 52:a51c77007319 866 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/