shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c@250:a49055e7a707, 2014-07-08 (annotated)

Committer:
mbed_official
Date:
Tue Jul 08 11:15:08 2014 +0100
Revision:
250:a49055e7a707
Parent:
46:bebbbd80dd87
Child:
251:de9a1e4ffd79
Synchronized with git revision 3197042b65f8d28e856e1a7812d45e2fbe80e3f1



Full URL: https://github.com/mbedmicro/mbed/commit/3197042b65f8d28e856e1a7812d45e2fbe80e3f1/



error.h -> mbed_error.h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 46:bebbbd80dd87 1 /* mbed Microcontroller Library
mbed_official 46:bebbbd80dd87 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 46:bebbbd80dd87 3 *
mbed_official 46:bebbbd80dd87 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 46:bebbbd80dd87 5 * you may not use this file except in compliance with the License.
mbed_official 46:bebbbd80dd87 6 * You may obtain a copy of the License at
mbed_official 46:bebbbd80dd87 7 *
mbed_official 46:bebbbd80dd87 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 46:bebbbd80dd87 9 *
mbed_official 46:bebbbd80dd87 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 46:bebbbd80dd87 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 46:bebbbd80dd87 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 46:bebbbd80dd87 13 * See the License for the specific language governing permissions and
mbed_official 46:bebbbd80dd87 14 * limitations under the License.
mbed_official 46:bebbbd80dd87 15 */
mbed_official 46:bebbbd80dd87 16 #include <stddef.h>
mbed_official 46:bebbbd80dd87 17
mbed_official 46:bebbbd80dd87 18 #include "cmsis.h"
mbed_official 46:bebbbd80dd87 19 #include "gpio_irq_api.h"
mbed_official 250:a49055e7a707 20 #include "mbed_error.h"
mbed_official 46:bebbbd80dd87 21
mbed_official 46:bebbbd80dd87 22 #define CHANNEL_NUM 8
mbed_official 46:bebbbd80dd87 23 #define LPC_GPIO_X LPC_PIN_INT
mbed_official 46:bebbbd80dd87 24 #define PININT_IRQ PININT0_IRQn
mbed_official 46:bebbbd80dd87 25
mbed_official 46:bebbbd80dd87 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
mbed_official 46:bebbbd80dd87 27 static gpio_irq_handler irq_handler;
mbed_official 46:bebbbd80dd87 28
mbed_official 46:bebbbd80dd87 29 static inline void handle_interrupt_in(uint32_t channel) {
mbed_official 46:bebbbd80dd87 30 uint32_t ch_bit = (1 << channel);
mbed_official 46:bebbbd80dd87 31 // Return immediately if:
mbed_official 46:bebbbd80dd87 32 // * The interrupt was already served
mbed_official 46:bebbbd80dd87 33 // * There is no user handler
mbed_official 46:bebbbd80dd87 34 // * It is a level interrupt, not an edge interrupt
mbed_official 46:bebbbd80dd87 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
mbed_official 46:bebbbd80dd87 36 (channel_ids[channel] == 0 ) ||
mbed_official 46:bebbbd80dd87 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
mbed_official 46:bebbbd80dd87 38
mbed_official 46:bebbbd80dd87 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
mbed_official 46:bebbbd80dd87 40 irq_handler(channel_ids[channel], IRQ_RISE);
mbed_official 46:bebbbd80dd87 41 LPC_GPIO_X->RISE = ch_bit;
mbed_official 46:bebbbd80dd87 42 }
mbed_official 46:bebbbd80dd87 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
mbed_official 46:bebbbd80dd87 44 irq_handler(channel_ids[channel], IRQ_FALL);
mbed_official 46:bebbbd80dd87 45 }
mbed_official 46:bebbbd80dd87 46 LPC_GPIO_X->IST = ch_bit;
mbed_official 46:bebbbd80dd87 47 }
mbed_official 46:bebbbd80dd87 48
mbed_official 46:bebbbd80dd87 49 void gpio_irq0(void) {handle_interrupt_in(0);}
mbed_official 46:bebbbd80dd87 50 void gpio_irq1(void) {handle_interrupt_in(1);}
mbed_official 46:bebbbd80dd87 51 void gpio_irq2(void) {handle_interrupt_in(2);}
mbed_official 46:bebbbd80dd87 52 void gpio_irq3(void) {handle_interrupt_in(3);}
mbed_official 46:bebbbd80dd87 53 void gpio_irq4(void) {handle_interrupt_in(4);}
mbed_official 46:bebbbd80dd87 54 void gpio_irq5(void) {handle_interrupt_in(5);}
mbed_official 46:bebbbd80dd87 55 void gpio_irq6(void) {handle_interrupt_in(6);}
mbed_official 46:bebbbd80dd87 56 void gpio_irq7(void) {handle_interrupt_in(7);}
mbed_official 46:bebbbd80dd87 57
mbed_official 46:bebbbd80dd87 58 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
mbed_official 46:bebbbd80dd87 59 if (pin == NC) return -1;
mbed_official 46:bebbbd80dd87 60
mbed_official 46:bebbbd80dd87 61 irq_handler = handler;
mbed_official 46:bebbbd80dd87 62
mbed_official 46:bebbbd80dd87 63 int found_free_channel = 0;
mbed_official 46:bebbbd80dd87 64 int i = 0;
mbed_official 46:bebbbd80dd87 65 for (i=0; i<CHANNEL_NUM; i++) {
mbed_official 46:bebbbd80dd87 66 if (channel_ids[i] == 0) {
mbed_official 46:bebbbd80dd87 67 channel_ids[i] = id;
mbed_official 46:bebbbd80dd87 68 obj->ch = i;
mbed_official 46:bebbbd80dd87 69 found_free_channel = 1;
mbed_official 46:bebbbd80dd87 70 break;
mbed_official 46:bebbbd80dd87 71 }
mbed_official 46:bebbbd80dd87 72 }
mbed_official 46:bebbbd80dd87 73 if (!found_free_channel) return -1;
mbed_official 46:bebbbd80dd87 74
mbed_official 46:bebbbd80dd87 75 /* Enable AHB clock to the GPIO domain. */
mbed_official 46:bebbbd80dd87 76 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
mbed_official 46:bebbbd80dd87 77
mbed_official 46:bebbbd80dd87 78 LPC_SYSCON->PINTSEL[obj->ch] = pin;
mbed_official 46:bebbbd80dd87 79
mbed_official 46:bebbbd80dd87 80 // Interrupt Wake-Up Enable
mbed_official 46:bebbbd80dd87 81 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
mbed_official 46:bebbbd80dd87 82
mbed_official 46:bebbbd80dd87 83 void (*channels_irq)(void) = NULL;
mbed_official 46:bebbbd80dd87 84 switch (obj->ch) {
mbed_official 46:bebbbd80dd87 85 case 0: channels_irq = &gpio_irq0; break;
mbed_official 46:bebbbd80dd87 86 case 1: channels_irq = &gpio_irq1; break;
mbed_official 46:bebbbd80dd87 87 case 2: channels_irq = &gpio_irq2; break;
mbed_official 46:bebbbd80dd87 88 case 3: channels_irq = &gpio_irq3; break;
mbed_official 46:bebbbd80dd87 89 case 4: channels_irq = &gpio_irq4; break;
mbed_official 46:bebbbd80dd87 90 case 5: channels_irq = &gpio_irq5; break;
mbed_official 46:bebbbd80dd87 91 case 6: channels_irq = &gpio_irq6; break;
mbed_official 46:bebbbd80dd87 92 case 7: channels_irq = &gpio_irq7; break;
mbed_official 46:bebbbd80dd87 93 }
mbed_official 46:bebbbd80dd87 94 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
mbed_official 46:bebbbd80dd87 95 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 46:bebbbd80dd87 96
mbed_official 46:bebbbd80dd87 97 return 0;
mbed_official 46:bebbbd80dd87 98 }
mbed_official 46:bebbbd80dd87 99
mbed_official 46:bebbbd80dd87 100 void gpio_irq_free(gpio_irq_t *obj) {
mbed_official 46:bebbbd80dd87 101 channel_ids[obj->ch] = 0;
mbed_official 46:bebbbd80dd87 102 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
mbed_official 46:bebbbd80dd87 103 }
mbed_official 46:bebbbd80dd87 104
mbed_official 46:bebbbd80dd87 105 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
mbed_official 46:bebbbd80dd87 106 unsigned int ch_bit = (1 << obj->ch);
mbed_official 46:bebbbd80dd87 107
mbed_official 46:bebbbd80dd87 108 // Clear interrupt
mbed_official 46:bebbbd80dd87 109 if (!(LPC_GPIO_X->ISEL & ch_bit))
mbed_official 46:bebbbd80dd87 110 LPC_GPIO_X->IST = ch_bit;
mbed_official 46:bebbbd80dd87 111
mbed_official 46:bebbbd80dd87 112 // Edge trigger
mbed_official 46:bebbbd80dd87 113 LPC_GPIO_X->ISEL &= ~ch_bit;
mbed_official 46:bebbbd80dd87 114 if (event == IRQ_RISE) {
mbed_official 46:bebbbd80dd87 115 if (enable) {
mbed_official 46:bebbbd80dd87 116 LPC_GPIO_X->IENR |= ch_bit;
mbed_official 46:bebbbd80dd87 117 } else {
mbed_official 46:bebbbd80dd87 118 LPC_GPIO_X->IENR &= ~ch_bit;
mbed_official 46:bebbbd80dd87 119 }
mbed_official 46:bebbbd80dd87 120 } else {
mbed_official 46:bebbbd80dd87 121 if (enable) {
mbed_official 46:bebbbd80dd87 122 LPC_GPIO_X->IENF |= ch_bit;
mbed_official 46:bebbbd80dd87 123 } else {
mbed_official 46:bebbbd80dd87 124 LPC_GPIO_X->IENF &= ~ch_bit;
mbed_official 46:bebbbd80dd87 125 }
mbed_official 46:bebbbd80dd87 126 }
mbed_official 46:bebbbd80dd87 127 }
mbed_official 46:bebbbd80dd87 128
mbed_official 46:bebbbd80dd87 129 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 46:bebbbd80dd87 130 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 46:bebbbd80dd87 131 }
mbed_official 46:bebbbd80dd87 132
mbed_official 46:bebbbd80dd87 133 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 46:bebbbd80dd87 134 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 46:bebbbd80dd87 135 }